1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2021, Martin Botka <martin.botka@somainline.org> 4 */ 5 6#include <dt-bindings/clock/qcom,gcc-sm6125.h> 7#include <dt-bindings/clock/qcom,rpmcc.h> 8#include <dt-bindings/dma/qcom-gpi.h> 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/power/qcom-rpmpd.h> 12 13/ { 14 interrupt-parent = <&intc>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 chosen { }; 19 20 clocks { 21 xo_board: xo-board { 22 compatible = "fixed-clock"; 23 #clock-cells = <0>; 24 clock-frequency = <19200000>; 25 clock-output-names = "xo_board"; 26 }; 27 28 sleep_clk: sleep-clk { 29 compatible = "fixed-clock"; 30 #clock-cells = <0>; 31 clock-frequency = <32000>; 32 clock-output-names = "sleep_clk"; 33 }; 34 }; 35 36 cpus { 37 #address-cells = <2>; 38 #size-cells = <0>; 39 40 CPU0: cpu@0 { 41 device_type = "cpu"; 42 compatible = "qcom,kryo260"; 43 reg = <0x0 0x0>; 44 enable-method = "psci"; 45 capacity-dmips-mhz = <1024>; 46 next-level-cache = <&L2_0>; 47 L2_0: l2-cache { 48 compatible = "cache"; 49 cache-level = <2>; 50 }; 51 }; 52 53 CPU1: cpu@1 { 54 device_type = "cpu"; 55 compatible = "qcom,kryo260"; 56 reg = <0x0 0x1>; 57 enable-method = "psci"; 58 capacity-dmips-mhz = <1024>; 59 next-level-cache = <&L2_0>; 60 }; 61 62 CPU2: cpu@2 { 63 device_type = "cpu"; 64 compatible = "qcom,kryo260"; 65 reg = <0x0 0x2>; 66 enable-method = "psci"; 67 capacity-dmips-mhz = <1024>; 68 next-level-cache = <&L2_0>; 69 }; 70 71 CPU3: cpu@3 { 72 device_type = "cpu"; 73 compatible = "qcom,kryo260"; 74 reg = <0x0 0x3>; 75 enable-method = "psci"; 76 capacity-dmips-mhz = <1024>; 77 next-level-cache = <&L2_0>; 78 }; 79 80 CPU4: cpu@100 { 81 device_type = "cpu"; 82 compatible = "qcom,kryo260"; 83 reg = <0x0 0x100>; 84 enable-method = "psci"; 85 capacity-dmips-mhz = <1638>; 86 next-level-cache = <&L2_1>; 87 L2_1: l2-cache { 88 compatible = "cache"; 89 cache-level = <2>; 90 }; 91 }; 92 93 CPU5: cpu@101 { 94 device_type = "cpu"; 95 compatible = "qcom,kryo260"; 96 reg = <0x0 0x101>; 97 enable-method = "psci"; 98 capacity-dmips-mhz = <1638>; 99 next-level-cache = <&L2_1>; 100 }; 101 102 CPU6: cpu@102 { 103 device_type = "cpu"; 104 compatible = "qcom,kryo260"; 105 reg = <0x0 0x102>; 106 enable-method = "psci"; 107 capacity-dmips-mhz = <1638>; 108 next-level-cache = <&L2_1>; 109 }; 110 111 CPU7: cpu@103 { 112 device_type = "cpu"; 113 compatible = "qcom,kryo260"; 114 reg = <0x0 0x103>; 115 enable-method = "psci"; 116 capacity-dmips-mhz = <1638>; 117 next-level-cache = <&L2_1>; 118 }; 119 120 cpu-map { 121 cluster0 { 122 core0 { 123 cpu = <&CPU0>; 124 }; 125 126 core1 { 127 cpu = <&CPU1>; 128 }; 129 130 core2 { 131 cpu = <&CPU2>; 132 }; 133 134 core3 { 135 cpu = <&CPU3>; 136 }; 137 }; 138 139 cluster1 { 140 core0 { 141 cpu = <&CPU4>; 142 }; 143 144 core1 { 145 cpu = <&CPU5>; 146 }; 147 148 core2 { 149 cpu = <&CPU6>; 150 }; 151 152 core3 { 153 cpu = <&CPU7>; 154 }; 155 }; 156 }; 157 }; 158 159 firmware { 160 scm: scm { 161 compatible = "qcom,scm-sm6125", "qcom,scm"; 162 #reset-cells = <1>; 163 }; 164 }; 165 166 memory@40000000 { 167 /* We expect the bootloader to fill in the size */ 168 reg = <0x0 0x40000000 0x0 0x0>; 169 device_type = "memory"; 170 }; 171 172 pmu { 173 compatible = "arm,armv8-pmuv3"; 174 interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>; 175 }; 176 177 psci { 178 compatible = "arm,psci-1.0"; 179 method = "smc"; 180 }; 181 182 reserved_memory: reserved-memory { 183 #address-cells = <2>; 184 #size-cells = <2>; 185 ranges; 186 187 hyp_mem: memory@45700000 { 188 reg = <0x0 0x45700000 0x0 0x600000>; 189 no-map; 190 }; 191 192 xbl_aop_mem: memory@45e00000 { 193 reg = <0x0 0x45e00000 0x0 0x140000>; 194 no-map; 195 }; 196 197 sec_apps_mem: memory@45fff000 { 198 reg = <0x0 0x45fff000 0x0 0x1000>; 199 no-map; 200 }; 201 202 smem_mem: memory@46000000 { 203 reg = <0x0 0x46000000 0x0 0x200000>; 204 no-map; 205 }; 206 207 reserved_mem1: memory@46200000 { 208 reg = <0x0 0x46200000 0x0 0x2d00000>; 209 no-map; 210 }; 211 212 camera_mem: memory@4ab00000 { 213 reg = <0x0 0x4ab00000 0x0 0x500000>; 214 no-map; 215 }; 216 217 modem_mem: memory@4b000000 { 218 reg = <0x0 0x4b000000 0x0 0x7e00000>; 219 no-map; 220 }; 221 222 venus_mem: memory@52e00000 { 223 reg = <0x0 0x52e00000 0x0 0x500000>; 224 no-map; 225 }; 226 227 wlan_msa_mem: memory@53300000 { 228 reg = <0x0 0x53300000 0x0 0x200000>; 229 no-map; 230 }; 231 232 cdsp_mem: memory@53500000 { 233 reg = <0x0 0x53500000 0x0 0x1e00000>; 234 no-map; 235 }; 236 237 adsp_pil_mem: memory@55300000 { 238 reg = <0x0 0x55300000 0x0 0x1e00000>; 239 no-map; 240 }; 241 242 ipa_fw_mem: memory@57100000 { 243 reg = <0x0 0x57100000 0x0 0x10000>; 244 no-map; 245 }; 246 247 ipa_gsi_mem: memory@57110000 { 248 reg = <0x0 0x57110000 0x0 0x5000>; 249 no-map; 250 }; 251 252 gpu_mem: memory@57115000 { 253 reg = <0x0 0x57115000 0x0 0x2000>; 254 no-map; 255 }; 256 257 cont_splash_mem: memory@5c000000 { 258 reg = <0x0 0x5c000000 0x0 0x00f00000>; 259 no-map; 260 }; 261 262 dfps_data_mem: memory@5cf00000 { 263 reg = <0x0 0x5cf00000 0x0 0x0100000>; 264 no-map; 265 }; 266 267 cdsp_sec_mem: memory@5f800000 { 268 reg = <0x0 0x5f800000 0x0 0x1e00000>; 269 no-map; 270 }; 271 272 qseecom_mem: memory@5e400000 { 273 reg = <0x0 0x5e400000 0x0 0x1400000>; 274 no-map; 275 }; 276 277 sdsp_mem: memory@f3000000 { 278 reg = <0x0 0xf3000000 0x0 0x400000>; 279 no-map; 280 }; 281 282 adsp_mem: memory@f3400000 { 283 reg = <0x0 0xf3400000 0x0 0x800000>; 284 no-map; 285 }; 286 287 qseecom_ta_mem: memory@13fc00000 { 288 reg = <0x1 0x3fc00000 0x0 0x400000>; 289 no-map; 290 }; 291 }; 292 293 rpm-glink { 294 compatible = "qcom,glink-rpm"; 295 296 interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>; 297 qcom,rpm-msg-ram = <&rpm_msg_ram>; 298 mboxes = <&apcs_glb 0>; 299 300 rpm_requests: rpm-requests { 301 compatible = "qcom,rpm-sm6125"; 302 qcom,glink-channels = "rpm_requests"; 303 304 rpmcc: clock-controller { 305 compatible = "qcom,rpmcc-sm6125", "qcom,rpmcc"; 306 #clock-cells = <1>; 307 }; 308 309 rpmpd: power-controller { 310 compatible = "qcom,sm6125-rpmpd"; 311 #power-domain-cells = <1>; 312 operating-points-v2 = <&rpmpd_opp_table>; 313 314 rpmpd_opp_table: opp-table { 315 compatible = "operating-points-v2"; 316 317 rpmpd_opp_ret: opp1 { 318 opp-level = <RPM_SMD_LEVEL_RETENTION>; 319 }; 320 321 rpmpd_opp_ret_plus: opp2 { 322 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>; 323 }; 324 325 rpmpd_opp_min_svs: opp3 { 326 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 327 }; 328 329 rpmpd_opp_low_svs: opp4 { 330 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 331 }; 332 333 rpmpd_opp_svs: opp5 { 334 opp-level = <RPM_SMD_LEVEL_SVS>; 335 }; 336 337 rpmpd_opp_svs_plus: opp6 { 338 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 339 }; 340 341 rpmpd_opp_nom: opp7 { 342 opp-level = <RPM_SMD_LEVEL_NOM>; 343 }; 344 345 rpmpd_opp_nom_plus: opp8 { 346 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 347 }; 348 349 rpmpd_opp_turbo: opp9 { 350 opp-level = <RPM_SMD_LEVEL_TURBO>; 351 }; 352 353 rpmpd_opp_turbo_no_cpr: opp10 { 354 opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>; 355 }; 356 }; 357 }; 358 }; 359 }; 360 361 smem: smem { 362 compatible = "qcom,smem"; 363 memory-region = <&smem_mem>; 364 hwlocks = <&tcsr_mutex 3>; 365 }; 366 367 soc { 368 #address-cells = <1>; 369 #size-cells = <1>; 370 ranges = <0x00 0x00 0x00 0xffffffff>; 371 compatible = "simple-bus"; 372 373 tcsr_mutex: hwlock@340000 { 374 compatible = "qcom,tcsr-mutex"; 375 reg = <0x00340000 0x20000>; 376 #hwlock-cells = <1>; 377 }; 378 379 tlmm: pinctrl@500000 { 380 compatible = "qcom,sm6125-tlmm"; 381 reg = <0x00500000 0x400000>, 382 <0x00900000 0x400000>, 383 <0x00d00000 0x400000>; 384 reg-names = "west", "south", "east"; 385 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 386 gpio-controller; 387 gpio-ranges = <&tlmm 0 0 134>; 388 #gpio-cells = <2>; 389 interrupt-controller; 390 #interrupt-cells = <2>; 391 392 sdc2_off_state: sdc2-off-state { 393 clk-pins { 394 pins = "sdc2_clk"; 395 drive-strength = <2>; 396 bias-disable; 397 }; 398 399 cmd-pins { 400 pins = "sdc2_cmd"; 401 drive-strength = <2>; 402 bias-pull-up; 403 }; 404 405 data-pins { 406 pins = "sdc2_data"; 407 drive-strength = <2>; 408 bias-pull-up; 409 }; 410 }; 411 412 sdc2_on_state: sdc2-on-state { 413 clk-pins { 414 pins = "sdc2_clk"; 415 drive-strength = <16>; 416 bias-disable; 417 }; 418 419 cmd-pins { 420 pins = "sdc2_cmd"; 421 drive-strength = <10>; 422 bias-pull-up; 423 }; 424 425 data-pins { 426 pins = "sdc2_data"; 427 drive-strength = <10>; 428 bias-pull-up; 429 }; 430 }; 431 432 qup_i2c0_default: qup-i2c0-default-state { 433 pins = "gpio0", "gpio1"; 434 function = "qup00"; 435 drive-strength = <2>; 436 bias-disable; 437 }; 438 439 qup_i2c0_sleep: qup-i2c0-sleep-state { 440 pins = "gpio0", "gpio1"; 441 function = "gpio"; 442 drive-strength = <2>; 443 bias-pull-up; 444 }; 445 446 qup_i2c1_default: qup-i2c1-default-state { 447 pins = "gpio4", "gpio5"; 448 function = "qup01"; 449 drive-strength = <2>; 450 bias-disable; 451 }; 452 453 qup_i2c1_sleep: qup-i2c1-sleep-state { 454 pins = "gpio4", "gpio5"; 455 function = "gpio"; 456 drive-strength = <2>; 457 bias-pull-up; 458 }; 459 460 qup_i2c2_default: qup-i2c2-default-state { 461 pins = "gpio6", "gpio7"; 462 function = "qup02"; 463 drive-strength = <2>; 464 bias-disable; 465 }; 466 467 qup_i2c2_sleep: qup-i2c2-sleep-state { 468 pins = "gpio6", "gpio7"; 469 function = "gpio"; 470 drive-strength = <2>; 471 bias-pull-up; 472 }; 473 474 qup_i2c3_default: qup-i2c3-default-state { 475 pins = "gpio14", "gpio15"; 476 function = "qup03"; 477 drive-strength = <2>; 478 bias-disable; 479 }; 480 481 qup_i2c3_sleep: qup-i2c3-sleep-state { 482 pins = "gpio14", "gpio15"; 483 function = "gpio"; 484 drive-strength = <2>; 485 bias-pull-up; 486 }; 487 488 qup_i2c4_default: qup-i2c4-default-state { 489 pins = "gpio16", "gpio17"; 490 function = "qup04"; 491 drive-strength = <2>; 492 bias-disable; 493 }; 494 495 qup_i2c4_sleep: qup-i2c4-sleep-state { 496 pins = "gpio16", "gpio17"; 497 function = "gpio"; 498 drive-strength = <2>; 499 bias-pull-up; 500 }; 501 502 qup_i2c5_default: qup-i2c5-default-state { 503 pins = "gpio22", "gpio23"; 504 function = "qup10"; 505 drive-strength = <2>; 506 bias-disable; 507 }; 508 509 qup_i2c5_sleep: qup-i2c5-sleep-state { 510 pins = "gpio22", "gpio23"; 511 function = "gpio"; 512 drive-strength = <2>; 513 bias-pull-up; 514 }; 515 516 qup_i2c6_default: qup-i2c6-default-state { 517 pins = "gpio30", "gpio31"; 518 function = "qup11"; 519 drive-strength = <2>; 520 bias-disable; 521 }; 522 523 qup_i2c6_sleep: qup-i2c6-sleep-state { 524 pins = "gpio30", "gpio31"; 525 function = "gpio"; 526 drive-strength = <2>; 527 bias-pull-up; 528 }; 529 530 qup_i2c7_default: qup-i2c7-default-state { 531 pins = "gpio28", "gpio29"; 532 function = "qup12"; 533 drive-strength = <2>; 534 bias-disable; 535 }; 536 537 qup_i2c7_sleep: qup-i2c7-sleep-state { 538 pins = "gpio28", "gpio29"; 539 function = "gpio"; 540 drive-strength = <2>; 541 bias-pull-up; 542 }; 543 544 qup_i2c8_default: qup-i2c8-default-state { 545 pins = "gpio18", "gpio19"; 546 function = "qup13"; 547 drive-strength = <2>; 548 bias-disable; 549 }; 550 551 qup_i2c8_sleep: qup-i2c8-sleep-state { 552 pins = "gpio18", "gpio19"; 553 function = "gpio"; 554 drive-strength = <2>; 555 bias-pull-up; 556 }; 557 558 qup_i2c9_default: qup-i2c9-default-state { 559 pins = "gpio10", "gpio11"; 560 function = "qup14"; 561 drive-strength = <2>; 562 bias-disable; 563 }; 564 565 qup_i2c9_sleep: qup-i2c9-sleep-state { 566 pins = "gpio10", "gpio11"; 567 function = "gpio"; 568 drive-strength = <2>; 569 bias-pull-up; 570 }; 571 572 qup_spi0_default: qup-spi0-default-state { 573 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 574 function = "qup00"; 575 drive-strength = <6>; 576 bias-disable; 577 }; 578 579 qup_spi0_sleep: qup-spi0-sleep-state { 580 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 581 function = "gpio"; 582 drive-strength = <6>; 583 bias-disable; 584 }; 585 586 qup_spi2_default: qup-spi2-default-state { 587 pins = "gpio6", "gpio7", "gpio8", "gpio9"; 588 function = "qup02"; 589 drive-strength = <6>; 590 bias-disable; 591 }; 592 593 qup_spi2_sleep: qup-spi2-sleep-state { 594 pins = "gpio6", "gpio7", "gpio8", "gpio9"; 595 function = "gpio"; 596 drive-strength = <6>; 597 bias-disable; 598 }; 599 600 qup_spi5_default: qup-spi5-default-state { 601 pins = "gpio22", "gpio23", "gpio24", "gpio25"; 602 function = "qup10"; 603 drive-strength = <6>; 604 bias-disable; 605 }; 606 607 qup_spi5_sleep: qup-spi5-sleep-state { 608 pins = "gpio22", "gpio23", "gpio24", "gpio25"; 609 function = "gpio"; 610 drive-strength = <6>; 611 bias-disable; 612 }; 613 614 qup_spi6_default: qup-spi6-default-state { 615 pins = "gpio30", "gpio31", "gpio32", "gpio33"; 616 function = "qup11"; 617 drive-strength = <6>; 618 bias-disable; 619 }; 620 621 qup_spi6_sleep: qup-spi6-sleep-state { 622 pins = "gpio30", "gpio31", "gpio32", "gpio33"; 623 function = "gpio"; 624 drive-strength = <6>; 625 bias-disable; 626 }; 627 628 qup_spi8_default: qup-spi8-default-state { 629 pins = "gpio18", "gpio19", "gpio20", "gpio21"; 630 function = "qup13"; 631 drive-strength = <6>; 632 bias-disable; 633 }; 634 635 qup_spi8_sleep: qup-spi8-sleep-state { 636 pins = "gpio18", "gpio19", "gpio20", "gpio21"; 637 function = "gpio"; 638 drive-strength = <6>; 639 bias-disable; 640 }; 641 642 qup_spi9_default: qup-spi9-default-state { 643 pins = "gpio10", "gpio11", "gpio12", "gpio13"; 644 function = "qup14"; 645 drive-strength = <6>; 646 bias-disable; 647 }; 648 649 qup_spi9_sleep: qup-spi9-sleep-state { 650 pins = "gpio10", "gpio11", "gpio12", "gpio13"; 651 function = "gpio"; 652 drive-strength = <6>; 653 bias-disable; 654 }; 655 }; 656 657 gcc: clock-controller@1400000 { 658 compatible = "qcom,gcc-sm6125"; 659 reg = <0x01400000 0x1f0000>; 660 #clock-cells = <1>; 661 #reset-cells = <1>; 662 #power-domain-cells = <1>; 663 clock-names = "bi_tcxo", "sleep_clk"; 664 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>; 665 }; 666 667 hsusb_phy1: phy@1613000 { 668 compatible = "qcom,msm8996-qusb2-phy"; 669 reg = <0x01613000 0x180>; 670 #phy-cells = <0>; 671 672 clocks = <&gcc GCC_AHB2PHY_USB_CLK>, 673 <&rpmcc RPM_SMD_XO_CLK_SRC>; 674 clock-names = "cfg_ahb", "ref"; 675 676 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 677 status = "disabled"; 678 }; 679 680 rpm_msg_ram: sram@45f0000 { 681 compatible = "qcom,rpm-msg-ram"; 682 reg = <0x045f0000 0x7000>; 683 }; 684 685 sdhc_1: mmc@4744000 { 686 compatible = "qcom,sm6125-sdhci", "qcom,sdhci-msm-v5"; 687 reg = <0x04744000 0x1000>, <0x04745000 0x1000>; 688 reg-names = "hc", "cqhci"; 689 690 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, 691 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 692 interrupt-names = "hc_irq", "pwr_irq"; 693 694 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 695 <&gcc GCC_SDCC1_APPS_CLK>, 696 <&xo_board>; 697 clock-names = "iface", "core", "xo"; 698 iommus = <&apps_smmu 0x160 0x0>; 699 700 power-domains = <&rpmpd SM6125_VDDCX>; 701 702 qcom,dll-config = <0x000f642c>; 703 qcom,ddr-config = <0x80040873>; 704 705 bus-width = <8>; 706 non-removable; 707 supports-cqe; 708 709 status = "disabled"; 710 }; 711 712 sdhc_2: mmc@4784000 { 713 compatible = "qcom,sm6125-sdhci", "qcom,sdhci-msm-v5"; 714 reg = <0x04784000 0x1000>; 715 reg-names = "hc"; 716 717 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 718 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 719 interrupt-names = "hc_irq", "pwr_irq"; 720 721 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 722 <&gcc GCC_SDCC2_APPS_CLK>, 723 <&xo_board>; 724 clock-names = "iface", "core", "xo"; 725 iommus = <&apps_smmu 0x180 0x0>; 726 727 pinctrl-0 = <&sdc2_on_state>; 728 pinctrl-1 = <&sdc2_off_state>; 729 pinctrl-names = "default", "sleep"; 730 731 power-domains = <&rpmpd SM6125_VDDCX>; 732 733 qcom,dll-config = <0x0007642c>; 734 qcom,ddr-config = <0x80040873>; 735 736 bus-width = <4>; 737 status = "disabled"; 738 }; 739 740 ufs_mem_hc: ufs@4804000 { 741 compatible = "qcom,sm6125-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; 742 reg = <0x04804000 0x3000>, <0x04810000 0x8000>; 743 reg-names = "std", "ice"; 744 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 745 746 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 747 <&gcc GCC_SYS_NOC_UFS_PHY_AXI_CLK>, 748 <&gcc GCC_UFS_PHY_AHB_CLK>, 749 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 750 <&rpmcc RPM_SMD_XO_CLK_SRC>, 751 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 752 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 753 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 754 clock-names = "core_clk", 755 "bus_aggr_clk", 756 "iface_clk", 757 "core_clk_unipro", 758 "ref_clk", 759 "tx_lane0_sync_clk", 760 "rx_lane0_sync_clk", 761 "ice_core_clk"; 762 freq-table-hz = <50000000 240000000>, 763 <0 0>, 764 <0 0>, 765 <37500000 150000000>, 766 <0 0>, 767 <0 0>, 768 <0 0>, 769 <75000000 300000000>; 770 771 resets = <&gcc GCC_UFS_PHY_BCR>; 772 reset-names = "rst"; 773 #reset-cells = <1>; 774 775 phys = <&ufs_mem_phy>; 776 phy-names = "ufsphy"; 777 778 lanes-per-direction = <1>; 779 780 iommus = <&apps_smmu 0x200 0x0>; 781 782 status = "disabled"; 783 }; 784 785 ufs_mem_phy: phy@4807000 { 786 compatible = "qcom,sm6125-qmp-ufs-phy"; 787 reg = <0x04807000 0xdb8>; 788 789 clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, 790 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 791 clock-names = "ref", 792 "ref_aux"; 793 794 resets = <&ufs_mem_hc 0>; 795 reset-names = "ufsphy"; 796 797 power-domains = <&gcc UFS_PHY_GDSC>; 798 799 #phy-cells = <0>; 800 801 status = "disabled"; 802 }; 803 804 gpi_dma0: dma-controller@4a00000 { 805 compatible = "qcom,sm6125-gpi-dma", "qcom,sdm845-gpi-dma"; 806 reg = <0x04a00000 0x60000>; 807 interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 808 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 809 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 810 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 811 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 812 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 813 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 814 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>; 815 dma-channels = <8>; 816 dma-channel-mask = <0x1f>; 817 iommus = <&apps_smmu 0x136 0x0>; 818 #dma-cells = <3>; 819 status = "disabled"; 820 }; 821 822 qupv3_id_0: geniqup@4ac0000 { 823 compatible = "qcom,geni-se-qup"; 824 reg = <0x04ac0000 0x2000>; 825 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 826 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 827 clock-names = "m-ahb", "s-ahb"; 828 iommus = <&apps_smmu 0x123 0x0>; 829 #address-cells = <1>; 830 #size-cells = <1>; 831 ranges; 832 status = "disabled"; 833 834 i2c0: i2c@4a80000 { 835 compatible = "qcom,geni-i2c"; 836 reg = <0x04a80000 0x4000>; 837 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 838 clock-names = "se"; 839 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 840 pinctrl-0 = <&qup_i2c0_default>; 841 pinctrl-1 = <&qup_i2c0_sleep>; 842 pinctrl-names = "default", "sleep"; 843 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 844 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 845 dma-names = "tx", "rx"; 846 #address-cells = <1>; 847 #size-cells = <0>; 848 status = "disabled"; 849 }; 850 851 spi0: spi@4a80000 { 852 compatible = "qcom,geni-spi"; 853 reg = <0x04a80000 0x4000>; 854 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 855 clock-names = "se"; 856 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 857 pinctrl-0 = <&qup_spi0_default>; 858 pinctrl-1 = <&qup_spi0_sleep>; 859 pinctrl-names = "default", "sleep"; 860 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 861 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 862 dma-names = "tx", "rx"; 863 #address-cells = <1>; 864 #size-cells = <0>; 865 status = "disabled"; 866 }; 867 868 i2c1: i2c@4a84000 { 869 compatible = "qcom,geni-i2c"; 870 reg = <0x04a84000 0x4000>; 871 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 872 clock-names = "se"; 873 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 874 pinctrl-0 = <&qup_i2c1_default>; 875 pinctrl-1 = <&qup_i2c1_sleep>; 876 pinctrl-names = "default", "sleep"; 877 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 878 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 879 dma-names = "tx", "rx"; 880 #address-cells = <1>; 881 #size-cells = <0>; 882 status = "disabled"; 883 }; 884 885 i2c2: i2c@4a88000 { 886 compatible = "qcom,geni-i2c"; 887 reg = <0x04a88000 0x4000>; 888 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 889 clock-names = "se"; 890 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; 891 pinctrl-0 = <&qup_i2c2_default>; 892 pinctrl-1 = <&qup_i2c2_sleep>; 893 pinctrl-names = "default", "sleep"; 894 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 895 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 896 dma-names = "tx", "rx"; 897 #address-cells = <1>; 898 #size-cells = <0>; 899 status = "disabled"; 900 }; 901 902 spi2: spi@4a88000 { 903 compatible = "qcom,geni-spi"; 904 reg = <0x04a88000 0x4000>; 905 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 906 clock-names = "se"; 907 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; 908 pinctrl-0 = <&qup_spi2_default>; 909 pinctrl-1 = <&qup_spi2_sleep>; 910 pinctrl-names = "default", "sleep"; 911 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 912 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 913 dma-names = "tx", "rx"; 914 #address-cells = <1>; 915 #size-cells = <0>; 916 status = "disabled"; 917 }; 918 919 i2c3: i2c@4a8c000 { 920 compatible = "qcom,geni-i2c"; 921 reg = <0x04a8c000 0x4000>; 922 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 923 clock-names = "se"; 924 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 925 pinctrl-0 = <&qup_i2c3_default>; 926 pinctrl-1 = <&qup_i2c3_sleep>; 927 pinctrl-names = "default", "sleep"; 928 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 929 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 930 dma-names = "tx", "rx"; 931 #address-cells = <1>; 932 #size-cells = <0>; 933 status = "disabled"; 934 }; 935 936 i2c4: i2c@4a90000 { 937 compatible = "qcom,geni-i2c"; 938 reg = <0x04a90000 0x4000>; 939 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 940 clock-names = "se"; 941 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 942 pinctrl-0 = <&qup_i2c4_default>; 943 pinctrl-1 = <&qup_i2c4_sleep>; 944 pinctrl-names = "default", "sleep"; 945 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 946 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 947 dma-names = "tx", "rx"; 948 #address-cells = <1>; 949 #size-cells = <0>; 950 status = "disabled"; 951 }; 952 }; 953 954 gpi_dma1: dma-controller@4c00000 { 955 compatible = "qcom,sm6125-gpi-dma", "qcom,sdm845-gpi-dma"; 956 reg = <0x04c00000 0x60000>; 957 interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 958 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 959 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 960 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 961 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 962 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 963 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 964 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; 965 dma-channels = <8>; 966 dma-channel-mask = <0x0f>; 967 iommus = <&apps_smmu 0x156 0x0>; 968 #dma-cells = <3>; 969 status = "disabled"; 970 }; 971 972 qupv3_id_1: geniqup@4cc0000 { 973 compatible = "qcom,geni-se-qup"; 974 reg = <0x04cc0000 0x2000>; 975 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 976 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 977 clock-names = "m-ahb", "s-ahb"; 978 iommus = <&apps_smmu 0x143 0x0>; 979 #address-cells = <1>; 980 #size-cells = <1>; 981 ranges; 982 status = "disabled"; 983 984 i2c5: i2c@4c80000 { 985 compatible = "qcom,geni-i2c"; 986 reg = <0x04c80000 0x4000>; 987 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 988 clock-names = "se"; 989 interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>; 990 pinctrl-0 = <&qup_i2c5_default>; 991 pinctrl-1 = <&qup_i2c5_sleep>; 992 pinctrl-names = "default", "sleep"; 993 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 994 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 995 dma-names = "tx", "rx"; 996 #address-cells = <1>; 997 #size-cells = <0>; 998 status = "disabled"; 999 }; 1000 1001 spi5: spi@4c80000 { 1002 compatible = "qcom,geni-spi"; 1003 reg = <0x04c80000 0x4000>; 1004 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1005 clock-names = "se"; 1006 interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>; 1007 pinctrl-0 = <&qup_spi5_default>; 1008 pinctrl-1 = <&qup_spi5_sleep>; 1009 pinctrl-names = "default", "sleep"; 1010 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1011 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1012 dma-names = "tx", "rx"; 1013 #address-cells = <1>; 1014 #size-cells = <0>; 1015 status = "disabled"; 1016 }; 1017 1018 i2c6: i2c@4c84000 { 1019 compatible = "qcom,geni-i2c"; 1020 reg = <0x04c84000 0x4000>; 1021 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1022 clock-names = "se"; 1023 interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>; 1024 pinctrl-0 = <&qup_i2c6_default>; 1025 pinctrl-1 = <&qup_i2c6_sleep>; 1026 pinctrl-names = "default", "sleep"; 1027 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1028 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1029 dma-names = "tx", "rx"; 1030 #address-cells = <1>; 1031 #size-cells = <0>; 1032 status = "disabled"; 1033 }; 1034 1035 spi6: spi@4c84000 { 1036 compatible = "qcom,geni-spi"; 1037 reg = <0x04c84000 0x4000>; 1038 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1039 clock-names = "se"; 1040 interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>; 1041 pinctrl-0 = <&qup_spi6_default>; 1042 pinctrl-1 = <&qup_spi6_sleep>; 1043 pinctrl-names = "default", "sleep"; 1044 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1045 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1046 dma-names = "tx", "rx"; 1047 #address-cells = <1>; 1048 #size-cells = <0>; 1049 status = "disabled"; 1050 }; 1051 1052 i2c7: i2c@4c88000 { 1053 compatible = "qcom,geni-i2c"; 1054 reg = <0x04c88000 0x4000>; 1055 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1056 clock-names = "se"; 1057 interrupts = <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>; 1058 pinctrl-0 = <&qup_i2c7_default>; 1059 pinctrl-1 = <&qup_i2c7_sleep>; 1060 pinctrl-names = "default", "sleep"; 1061 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1062 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1063 dma-names = "tx", "rx"; 1064 #address-cells = <1>; 1065 #size-cells = <0>; 1066 status = "disabled"; 1067 }; 1068 1069 i2c8: i2c@4c8c000 { 1070 compatible = "qcom,geni-i2c"; 1071 reg = <0x04c8c000 0x4000>; 1072 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1073 clock-names = "se"; 1074 interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>; 1075 pinctrl-0 = <&qup_i2c8_default>; 1076 pinctrl-1 = <&qup_i2c8_sleep>; 1077 pinctrl-names = "default", "sleep"; 1078 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1079 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1080 dma-names = "tx", "rx"; 1081 #address-cells = <1>; 1082 #size-cells = <0>; 1083 status = "disabled"; 1084 }; 1085 1086 spi8: spi@4c8c000 { 1087 compatible = "qcom,geni-spi"; 1088 reg = <0x04c8c000 0x4000>; 1089 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1090 clock-names = "se"; 1091 interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>; 1092 pinctrl-0 = <&qup_spi8_default>; 1093 pinctrl-1 = <&qup_spi8_sleep>; 1094 pinctrl-names = "default", "sleep"; 1095 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1096 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1097 dma-names = "tx", "rx"; 1098 #address-cells = <1>; 1099 #size-cells = <0>; 1100 status = "disabled"; 1101 }; 1102 1103 i2c9: i2c@4c90000 { 1104 compatible = "qcom,geni-i2c"; 1105 reg = <0x04c90000 0x4000>; 1106 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1107 clock-names = "se"; 1108 interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>; 1109 pinctrl-0 = <&qup_i2c9_default>; 1110 pinctrl-1 = <&qup_i2c9_sleep>; 1111 pinctrl-names = "default", "sleep"; 1112 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1113 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1114 dma-names = "tx", "rx"; 1115 #address-cells = <1>; 1116 #size-cells = <0>; 1117 status = "disabled"; 1118 }; 1119 1120 spi9: spi@4c90000 { 1121 compatible = "qcom,geni-spi"; 1122 reg = <0x04c90000 0x4000>; 1123 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1124 clock-names = "se"; 1125 interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>; 1126 pinctrl-0 = <&qup_spi9_default>; 1127 pinctrl-1 = <&qup_spi9_sleep>; 1128 pinctrl-names = "default", "sleep"; 1129 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1130 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1131 dma-names = "tx", "rx"; 1132 #address-cells = <1>; 1133 #size-cells = <0>; 1134 status = "disabled"; 1135 }; 1136 }; 1137 1138 usb3: usb@4ef8800 { 1139 compatible = "qcom,sm6125-dwc3", "qcom,dwc3"; 1140 reg = <0x04ef8800 0x400>; 1141 #address-cells = <1>; 1142 #size-cells = <1>; 1143 ranges; 1144 1145 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 1146 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 1147 <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>, 1148 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 1149 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1150 <&gcc GCC_USB3_PRIM_CLKREF_CLK>; 1151 clock-names = "cfg_noc", 1152 "core", 1153 "iface", 1154 "sleep", 1155 "mock_utmi", 1156 "xo"; 1157 1158 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1159 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 1160 assigned-clock-rates = <19200000>, <66666667>; 1161 1162 power-domains = <&gcc USB30_PRIM_GDSC>; 1163 qcom,select-utmi-as-pipe-clk; 1164 status = "disabled"; 1165 1166 usb3_dwc3: usb@4e00000 { 1167 compatible = "snps,dwc3"; 1168 reg = <0x04e00000 0xcd00>; 1169 interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 1170 iommus = <&apps_smmu 0x100 0x0>; 1171 phys = <&hsusb_phy1>; 1172 phy-names = "usb2-phy"; 1173 snps,dis_u2_susphy_quirk; 1174 snps,dis_enblslpm_quirk; 1175 maximum-speed = "high-speed"; 1176 dr_mode = "peripheral"; 1177 }; 1178 }; 1179 1180 sram@4690000 { 1181 compatible = "qcom,rpm-stats"; 1182 reg = <0x04690000 0x10000>; 1183 }; 1184 1185 spmi_bus: spmi@1c40000 { 1186 compatible = "qcom,spmi-pmic-arb"; 1187 reg = <0x01c40000 0x1100>, 1188 <0x01e00000 0x2000000>, 1189 <0x03e00000 0x100000>, 1190 <0x03f00000 0xa0000>, 1191 <0x01c0a000 0x26000>; 1192 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1193 interrupt-names = "periph_irq"; 1194 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 1195 qcom,ee = <0>; 1196 qcom,channel = <0>; 1197 #address-cells = <2>; 1198 #size-cells = <0>; 1199 interrupt-controller; 1200 #interrupt-cells = <4>; 1201 }; 1202 1203 apps_smmu: iommu@c600000 { 1204 compatible = "qcom,sm6125-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 1205 reg = <0xc600000 0x80000>; 1206 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 1207 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 1208 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 1209 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 1210 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 1211 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 1212 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 1213 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 1214 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 1215 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 1216 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 1217 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 1218 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 1219 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 1220 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 1221 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 1222 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 1223 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 1224 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 1225 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 1226 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 1227 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 1228 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 1229 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1230 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 1231 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 1232 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 1233 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 1234 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 1235 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1236 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1237 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1238 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 1239 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1240 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1241 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1242 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1243 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1244 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1245 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1246 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 1247 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 1248 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 1249 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 1250 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 1251 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 1252 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1253 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 1254 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1255 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 1256 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 1257 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 1258 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 1259 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 1260 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 1261 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1262 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 1263 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1264 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1265 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1266 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1267 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 1268 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 1269 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 1270 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 1271 1272 #global-interrupts = <1>; 1273 #iommu-cells = <2>; 1274 }; 1275 1276 apcs_glb: mailbox@f111000 { 1277 compatible = "qcom,sm6125-apcs-hmss-global", 1278 "qcom,msm8994-apcs-kpss-global"; 1279 reg = <0x0f111000 0x1000>; 1280 1281 #mbox-cells = <1>; 1282 }; 1283 1284 timer@f120000 { 1285 compatible = "arm,armv7-timer-mem"; 1286 #address-cells = <1>; 1287 #size-cells = <1>; 1288 ranges; 1289 reg = <0x0f120000 0x1000>; 1290 clock-frequency = <19200000>; 1291 1292 frame@f121000 { 1293 frame-number = <0>; 1294 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1295 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 1296 reg = <0x0f121000 0x1000>, 1297 <0x0f122000 0x1000>; 1298 }; 1299 1300 frame@f123000 { 1301 frame-number = <1>; 1302 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1303 reg = <0x0f123000 0x1000>; 1304 status = "disabled"; 1305 }; 1306 1307 frame@f124000 { 1308 frame-number = <2>; 1309 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1310 reg = <0x0f124000 0x1000>; 1311 status = "disabled"; 1312 }; 1313 1314 frame@f125000 { 1315 frame-number = <3>; 1316 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1317 reg = <0x0f125000 0x1000>; 1318 status = "disabled"; 1319 }; 1320 1321 frame@f126000 { 1322 frame-number = <4>; 1323 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1324 reg = <0x0f126000 0x1000>; 1325 status = "disabled"; 1326 }; 1327 1328 frame@f127000 { 1329 frame-number = <5>; 1330 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1331 reg = <0x0f127000 0x1000>; 1332 status = "disabled"; 1333 }; 1334 1335 frame@f128000 { 1336 frame-number = <6>; 1337 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1338 reg = <0x0f128000 0x1000>; 1339 status = "disabled"; 1340 }; 1341 }; 1342 1343 intc: interrupt-controller@f200000 { 1344 compatible = "arm,gic-v3"; 1345 reg = <0x0f200000 0x20000>, 1346 <0x0f300000 0x100000>; 1347 #interrupt-cells = <3>; 1348 interrupt-controller; 1349 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 1350 }; 1351 }; 1352 1353 timer { 1354 compatible = "arm,armv8-timer"; 1355 interrupts = <GIC_PPI 1 0xf08 1356 GIC_PPI 2 0xf08 1357 GIC_PPI 3 0xf08 1358 GIC_PPI 0 0xf08>; 1359 clock-frequency = <19200000>; 1360 }; 1361}; 1362