1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2021, Martin Botka <martin.botka@somainline.org> 4 */ 5 6#include <dt-bindings/clock/qcom,gcc-sm6125.h> 7#include <dt-bindings/clock/qcom,rpmcc.h> 8#include <dt-bindings/dma/qcom-gpi.h> 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/power/qcom-rpmpd.h> 12 13/ { 14 interrupt-parent = <&intc>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 chosen { }; 19 20 clocks { 21 xo_board: xo-board { 22 compatible = "fixed-clock"; 23 #clock-cells = <0>; 24 clock-frequency = <19200000>; 25 clock-output-names = "xo_board"; 26 }; 27 28 sleep_clk: sleep-clk { 29 compatible = "fixed-clock"; 30 #clock-cells = <0>; 31 clock-frequency = <32000>; 32 clock-output-names = "sleep_clk"; 33 }; 34 }; 35 36 cpus { 37 #address-cells = <2>; 38 #size-cells = <0>; 39 40 CPU0: cpu@0 { 41 device_type = "cpu"; 42 compatible = "qcom,kryo260"; 43 reg = <0x0 0x0>; 44 enable-method = "psci"; 45 capacity-dmips-mhz = <1024>; 46 next-level-cache = <&L2_0>; 47 L2_0: l2-cache { 48 compatible = "cache"; 49 cache-level = <2>; 50 }; 51 }; 52 53 CPU1: cpu@1 { 54 device_type = "cpu"; 55 compatible = "qcom,kryo260"; 56 reg = <0x0 0x1>; 57 enable-method = "psci"; 58 capacity-dmips-mhz = <1024>; 59 next-level-cache = <&L2_0>; 60 }; 61 62 CPU2: cpu@2 { 63 device_type = "cpu"; 64 compatible = "qcom,kryo260"; 65 reg = <0x0 0x2>; 66 enable-method = "psci"; 67 capacity-dmips-mhz = <1024>; 68 next-level-cache = <&L2_0>; 69 }; 70 71 CPU3: cpu@3 { 72 device_type = "cpu"; 73 compatible = "qcom,kryo260"; 74 reg = <0x0 0x3>; 75 enable-method = "psci"; 76 capacity-dmips-mhz = <1024>; 77 next-level-cache = <&L2_0>; 78 }; 79 80 CPU4: cpu@100 { 81 device_type = "cpu"; 82 compatible = "qcom,kryo260"; 83 reg = <0x0 0x100>; 84 enable-method = "psci"; 85 capacity-dmips-mhz = <1638>; 86 next-level-cache = <&L2_1>; 87 L2_1: l2-cache { 88 compatible = "cache"; 89 cache-level = <2>; 90 }; 91 }; 92 93 CPU5: cpu@101 { 94 device_type = "cpu"; 95 compatible = "qcom,kryo260"; 96 reg = <0x0 0x101>; 97 enable-method = "psci"; 98 capacity-dmips-mhz = <1638>; 99 next-level-cache = <&L2_1>; 100 }; 101 102 CPU6: cpu@102 { 103 device_type = "cpu"; 104 compatible = "qcom,kryo260"; 105 reg = <0x0 0x102>; 106 enable-method = "psci"; 107 capacity-dmips-mhz = <1638>; 108 next-level-cache = <&L2_1>; 109 }; 110 111 CPU7: cpu@103 { 112 device_type = "cpu"; 113 compatible = "qcom,kryo260"; 114 reg = <0x0 0x103>; 115 enable-method = "psci"; 116 capacity-dmips-mhz = <1638>; 117 next-level-cache = <&L2_1>; 118 }; 119 120 cpu-map { 121 cluster0 { 122 core0 { 123 cpu = <&CPU0>; 124 }; 125 126 core1 { 127 cpu = <&CPU1>; 128 }; 129 130 core2 { 131 cpu = <&CPU2>; 132 }; 133 134 core3 { 135 cpu = <&CPU3>; 136 }; 137 }; 138 139 cluster1 { 140 core0 { 141 cpu = <&CPU4>; 142 }; 143 144 core1 { 145 cpu = <&CPU5>; 146 }; 147 148 core2 { 149 cpu = <&CPU6>; 150 }; 151 152 core3 { 153 cpu = <&CPU7>; 154 }; 155 }; 156 }; 157 }; 158 159 firmware { 160 scm: scm { 161 compatible = "qcom,scm-sm6125", "qcom,scm"; 162 #reset-cells = <1>; 163 }; 164 }; 165 166 memory@40000000 { 167 /* We expect the bootloader to fill in the size */ 168 reg = <0x0 0x40000000 0x0 0x0>; 169 device_type = "memory"; 170 }; 171 172 pmu { 173 compatible = "arm,armv8-pmuv3"; 174 interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>; 175 }; 176 177 psci { 178 compatible = "arm,psci-1.0"; 179 method = "smc"; 180 }; 181 182 reserved_memory: reserved-memory { 183 #address-cells = <2>; 184 #size-cells = <2>; 185 ranges; 186 187 hyp_mem: memory@45700000 { 188 reg = <0x0 0x45700000 0x0 0x600000>; 189 no-map; 190 }; 191 192 xbl_aop_mem: memory@45e00000 { 193 reg = <0x0 0x45e00000 0x0 0x140000>; 194 no-map; 195 }; 196 197 sec_apps_mem: memory@45fff000 { 198 reg = <0x0 0x45fff000 0x0 0x1000>; 199 no-map; 200 }; 201 202 smem_mem: memory@46000000 { 203 reg = <0x0 0x46000000 0x0 0x200000>; 204 no-map; 205 }; 206 207 reserved_mem1: memory@46200000 { 208 reg = <0x0 0x46200000 0x0 0x2d00000>; 209 no-map; 210 }; 211 212 camera_mem: memory@4ab00000 { 213 reg = <0x0 0x4ab00000 0x0 0x500000>; 214 no-map; 215 }; 216 217 modem_mem: memory@4b000000 { 218 reg = <0x0 0x4b000000 0x0 0x7e00000>; 219 no-map; 220 }; 221 222 venus_mem: memory@52e00000 { 223 reg = <0x0 0x52e00000 0x0 0x500000>; 224 no-map; 225 }; 226 227 wlan_msa_mem: memory@53300000 { 228 reg = <0x0 0x53300000 0x0 0x200000>; 229 no-map; 230 }; 231 232 cdsp_mem: memory@53500000 { 233 reg = <0x0 0x53500000 0x0 0x1e00000>; 234 no-map; 235 }; 236 237 adsp_pil_mem: memory@55300000 { 238 reg = <0x0 0x55300000 0x0 0x1e00000>; 239 no-map; 240 }; 241 242 ipa_fw_mem: memory@57100000 { 243 reg = <0x0 0x57100000 0x0 0x10000>; 244 no-map; 245 }; 246 247 ipa_gsi_mem: memory@57110000 { 248 reg = <0x0 0x57110000 0x0 0x5000>; 249 no-map; 250 }; 251 252 gpu_mem: memory@57115000 { 253 reg = <0x0 0x57115000 0x0 0x2000>; 254 no-map; 255 }; 256 257 cont_splash_mem: memory@5c000000 { 258 reg = <0x0 0x5c000000 0x0 0x00f00000>; 259 no-map; 260 }; 261 262 dfps_data_mem: memory@5cf00000 { 263 reg = <0x0 0x5cf00000 0x0 0x0100000>; 264 no-map; 265 }; 266 267 cdsp_sec_mem: memory@5f800000 { 268 reg = <0x0 0x5f800000 0x0 0x1e00000>; 269 no-map; 270 }; 271 272 qseecom_mem: memory@5e400000 { 273 reg = <0x0 0x5e400000 0x0 0x1400000>; 274 no-map; 275 }; 276 277 sdsp_mem: memory@f3000000 { 278 reg = <0x0 0xf3000000 0x0 0x400000>; 279 no-map; 280 }; 281 282 adsp_mem: memory@f3400000 { 283 reg = <0x0 0xf3400000 0x0 0x800000>; 284 no-map; 285 }; 286 287 qseecom_ta_mem: memory@13fc00000 { 288 reg = <0x1 0x3fc00000 0x0 0x400000>; 289 no-map; 290 }; 291 }; 292 293 rpm-glink { 294 compatible = "qcom,glink-rpm"; 295 296 interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>; 297 qcom,rpm-msg-ram = <&rpm_msg_ram>; 298 mboxes = <&apcs_glb 0>; 299 300 rpm_requests: rpm-requests { 301 compatible = "qcom,rpm-sm6125"; 302 qcom,glink-channels = "rpm_requests"; 303 304 rpmcc: clock-controller { 305 compatible = "qcom,rpmcc-sm6125", "qcom,rpmcc"; 306 #clock-cells = <1>; 307 }; 308 309 rpmpd: power-controller { 310 compatible = "qcom,sm6125-rpmpd"; 311 #power-domain-cells = <1>; 312 operating-points-v2 = <&rpmpd_opp_table>; 313 314 rpmpd_opp_table: opp-table { 315 compatible = "operating-points-v2"; 316 317 rpmpd_opp_ret: opp1 { 318 opp-level = <RPM_SMD_LEVEL_RETENTION>; 319 }; 320 321 rpmpd_opp_ret_plus: opp2 { 322 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>; 323 }; 324 325 rpmpd_opp_min_svs: opp3 { 326 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 327 }; 328 329 rpmpd_opp_low_svs: opp4 { 330 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 331 }; 332 333 rpmpd_opp_svs: opp5 { 334 opp-level = <RPM_SMD_LEVEL_SVS>; 335 }; 336 337 rpmpd_opp_svs_plus: opp6 { 338 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 339 }; 340 341 rpmpd_opp_nom: opp7 { 342 opp-level = <RPM_SMD_LEVEL_NOM>; 343 }; 344 345 rpmpd_opp_nom_plus: opp8 { 346 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 347 }; 348 349 rpmpd_opp_turbo: opp9 { 350 opp-level = <RPM_SMD_LEVEL_TURBO>; 351 }; 352 353 rpmpd_opp_turbo_no_cpr: opp10 { 354 opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>; 355 }; 356 }; 357 }; 358 }; 359 }; 360 361 smem: smem { 362 compatible = "qcom,smem"; 363 memory-region = <&smem_mem>; 364 hwlocks = <&tcsr_mutex 3>; 365 }; 366 367 soc { 368 #address-cells = <1>; 369 #size-cells = <1>; 370 ranges = <0x00 0x00 0x00 0xffffffff>; 371 compatible = "simple-bus"; 372 373 tcsr_mutex: hwlock@340000 { 374 compatible = "qcom,tcsr-mutex"; 375 reg = <0x00340000 0x20000>; 376 #hwlock-cells = <1>; 377 }; 378 379 tlmm: pinctrl@500000 { 380 compatible = "qcom,sm6125-tlmm"; 381 reg = <0x00500000 0x400000>, 382 <0x00900000 0x400000>, 383 <0x00d00000 0x400000>; 384 reg-names = "west", "south", "east"; 385 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 386 gpio-controller; 387 gpio-ranges = <&tlmm 0 0 134>; 388 #gpio-cells = <2>; 389 interrupt-controller; 390 #interrupt-cells = <2>; 391 392 sdc2_off_state: sdc2-off-state { 393 clk-pins { 394 pins = "sdc2_clk"; 395 drive-strength = <2>; 396 bias-disable; 397 }; 398 399 cmd-pins { 400 pins = "sdc2_cmd"; 401 drive-strength = <2>; 402 bias-pull-up; 403 }; 404 405 data-pins { 406 pins = "sdc2_data"; 407 drive-strength = <2>; 408 bias-pull-up; 409 }; 410 }; 411 412 sdc2_on_state: sdc2-on-state { 413 clk-pins { 414 pins = "sdc2_clk"; 415 drive-strength = <16>; 416 bias-disable; 417 }; 418 419 cmd-pins { 420 pins = "sdc2_cmd"; 421 drive-strength = <10>; 422 bias-pull-up; 423 }; 424 425 data-pins { 426 pins = "sdc2_data"; 427 drive-strength = <10>; 428 bias-pull-up; 429 }; 430 }; 431 432 qup_i2c0_default: qup-i2c0-default-state { 433 pins = "gpio0", "gpio1"; 434 function = "qup00"; 435 drive-strength = <2>; 436 bias-disable; 437 }; 438 439 qup_i2c0_sleep: qup-i2c0-sleep-state { 440 pins = "gpio0", "gpio1"; 441 function = "gpio"; 442 drive-strength = <2>; 443 bias-pull-up; 444 }; 445 446 qup_i2c1_default: qup-i2c1-default-state { 447 pins = "gpio4", "gpio5"; 448 function = "qup01"; 449 drive-strength = <2>; 450 bias-disable; 451 }; 452 453 qup_i2c1_sleep: qup-i2c1-sleep-state { 454 pins = "gpio4", "gpio5"; 455 function = "gpio"; 456 drive-strength = <2>; 457 bias-pull-up; 458 }; 459 460 qup_i2c2_default: qup-i2c2-default-state { 461 pins = "gpio6", "gpio7"; 462 function = "qup02"; 463 drive-strength = <2>; 464 bias-disable; 465 }; 466 467 qup_i2c2_sleep: qup-i2c2-sleep-state { 468 pins = "gpio6", "gpio7"; 469 function = "gpio"; 470 drive-strength = <2>; 471 bias-pull-up; 472 }; 473 474 qup_i2c3_default: qup-i2c3-default-state { 475 pins = "gpio14", "gpio15"; 476 function = "qup03"; 477 drive-strength = <2>; 478 bias-disable; 479 }; 480 481 qup_i2c3_sleep: qup-i2c3-sleep-state { 482 pins = "gpio14", "gpio15"; 483 function = "gpio"; 484 drive-strength = <2>; 485 bias-pull-up; 486 }; 487 488 qup_i2c4_default: qup-i2c4-default-state { 489 pins = "gpio16", "gpio17"; 490 function = "qup04"; 491 drive-strength = <2>; 492 bias-disable; 493 }; 494 495 qup_i2c4_sleep: qup-i2c4-sleep-state { 496 pins = "gpio16", "gpio17"; 497 function = "gpio"; 498 drive-strength = <2>; 499 bias-pull-up; 500 }; 501 502 qup_i2c5_default: qup-i2c5-default-state { 503 pins = "gpio22", "gpio23"; 504 function = "qup10"; 505 drive-strength = <2>; 506 bias-disable; 507 }; 508 509 qup_i2c5_sleep: qup-i2c5-sleep-state { 510 pins = "gpio22", "gpio23"; 511 function = "gpio"; 512 drive-strength = <2>; 513 bias-pull-up; 514 }; 515 516 qup_i2c6_default: qup-i2c6-default-state { 517 pins = "gpio30", "gpio31"; 518 function = "qup11"; 519 drive-strength = <2>; 520 bias-disable; 521 }; 522 523 qup_i2c6_sleep: qup-i2c6-sleep-state { 524 pins = "gpio30", "gpio31"; 525 function = "gpio"; 526 drive-strength = <2>; 527 bias-pull-up; 528 }; 529 530 qup_i2c7_default: qup-i2c7-default-state { 531 pins = "gpio28", "gpio29"; 532 function = "qup12"; 533 drive-strength = <2>; 534 bias-disable; 535 }; 536 537 qup_i2c7_sleep: qup-i2c7-sleep-state { 538 pins = "gpio28", "gpio29"; 539 function = "gpio"; 540 drive-strength = <2>; 541 bias-pull-up; 542 }; 543 544 qup_i2c8_default: qup-i2c8-default-state { 545 pins = "gpio18", "gpio19"; 546 function = "qup13"; 547 drive-strength = <2>; 548 bias-disable; 549 }; 550 551 qup_i2c8_sleep: qup-i2c8-sleep-state { 552 pins = "gpio18", "gpio19"; 553 function = "gpio"; 554 drive-strength = <2>; 555 bias-pull-up; 556 }; 557 558 qup_i2c9_default: qup-i2c9-default-state { 559 pins = "gpio10", "gpio11"; 560 function = "qup14"; 561 drive-strength = <2>; 562 bias-disable; 563 }; 564 565 qup_i2c9_sleep: qup-i2c9-sleep-state { 566 pins = "gpio10", "gpio11"; 567 function = "gpio"; 568 drive-strength = <2>; 569 bias-pull-up; 570 }; 571 572 qup_spi0_default: qup-spi0-default-state { 573 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 574 function = "qup00"; 575 drive-strength = <6>; 576 bias-disable; 577 }; 578 579 qup_spi0_sleep: qup-spi0-sleep-state { 580 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 581 function = "gpio"; 582 drive-strength = <6>; 583 bias-disable; 584 }; 585 586 qup_spi2_default: qup-spi2-default-state { 587 pins = "gpio6", "gpio7", "gpio8", "gpio9"; 588 function = "qup02"; 589 drive-strength = <6>; 590 bias-disable; 591 }; 592 593 qup_spi2_sleep: qup-spi2-sleep-state { 594 pins = "gpio6", "gpio7", "gpio8", "gpio9"; 595 function = "gpio"; 596 drive-strength = <6>; 597 bias-disable; 598 }; 599 600 qup_spi5_default: qup-spi5-default-state { 601 pins = "gpio22", "gpio23", "gpio24", "gpio25"; 602 function = "qup10"; 603 drive-strength = <6>; 604 bias-disable; 605 }; 606 607 qup_spi5_sleep: qup-spi5-sleep-state { 608 pins = "gpio22", "gpio23", "gpio24", "gpio25"; 609 function = "gpio"; 610 drive-strength = <6>; 611 bias-disable; 612 }; 613 614 qup_spi6_default: qup-spi6-default-state { 615 pins = "gpio30", "gpio31", "gpio32", "gpio33"; 616 function = "qup11"; 617 drive-strength = <6>; 618 bias-disable; 619 }; 620 621 qup_spi6_sleep: qup-spi6-sleep-state { 622 pins = "gpio30", "gpio31", "gpio32", "gpio33"; 623 function = "gpio"; 624 drive-strength = <6>; 625 bias-disable; 626 }; 627 628 qup_spi8_default: qup-spi8-default-state { 629 pins = "gpio18", "gpio19", "gpio20", "gpio21"; 630 function = "qup13"; 631 drive-strength = <6>; 632 bias-disable; 633 }; 634 635 qup_spi8_sleep: qup-spi8-sleep-state { 636 pins = "gpio18", "gpio19", "gpio20", "gpio21"; 637 function = "gpio"; 638 drive-strength = <6>; 639 bias-disable; 640 }; 641 642 qup_spi9_default: qup-spi9-default-state { 643 pins = "gpio10", "gpio11", "gpio12", "gpio13"; 644 function = "qup14"; 645 drive-strength = <6>; 646 bias-disable; 647 }; 648 649 qup_spi9_sleep: qup-spi9-sleep-state { 650 pins = "gpio10", "gpio11", "gpio12", "gpio13"; 651 function = "gpio"; 652 drive-strength = <6>; 653 bias-disable; 654 }; 655 }; 656 657 gcc: clock-controller@1400000 { 658 compatible = "qcom,gcc-sm6125"; 659 reg = <0x01400000 0x1f0000>; 660 #clock-cells = <1>; 661 #reset-cells = <1>; 662 #power-domain-cells = <1>; 663 clock-names = "bi_tcxo", "sleep_clk"; 664 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>; 665 }; 666 667 hsusb_phy1: phy@1613000 { 668 compatible = "qcom,msm8996-qusb2-phy"; 669 reg = <0x01613000 0x180>; 670 #phy-cells = <0>; 671 672 clocks = <&gcc GCC_AHB2PHY_USB_CLK>, 673 <&rpmcc RPM_SMD_XO_CLK_SRC>; 674 clock-names = "cfg_ahb", "ref"; 675 676 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 677 status = "disabled"; 678 }; 679 680 rpm_msg_ram: sram@45f0000 { 681 compatible = "qcom,rpm-msg-ram"; 682 reg = <0x045f0000 0x7000>; 683 }; 684 685 sdhc_1: mmc@4744000 { 686 compatible = "qcom,sm6125-sdhci", "qcom,sdhci-msm-v5"; 687 reg = <0x04744000 0x1000>, <0x04745000 0x1000>; 688 reg-names = "hc", "cqhci"; 689 690 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, 691 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 692 interrupt-names = "hc_irq", "pwr_irq"; 693 694 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 695 <&gcc GCC_SDCC1_APPS_CLK>, 696 <&xo_board>; 697 clock-names = "iface", "core", "xo"; 698 iommus = <&apps_smmu 0x160 0x0>; 699 700 power-domains = <&rpmpd SM6125_VDDCX>; 701 702 qcom,dll-config = <0x000f642c>; 703 qcom,ddr-config = <0x80040873>; 704 705 bus-width = <8>; 706 non-removable; 707 supports-cqe; 708 709 status = "disabled"; 710 }; 711 712 sdhc_2: mmc@4784000 { 713 compatible = "qcom,sm6125-sdhci", "qcom,sdhci-msm-v5"; 714 reg = <0x04784000 0x1000>; 715 reg-names = "hc"; 716 717 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 718 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 719 interrupt-names = "hc_irq", "pwr_irq"; 720 721 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 722 <&gcc GCC_SDCC2_APPS_CLK>, 723 <&xo_board>; 724 clock-names = "iface", "core", "xo"; 725 iommus = <&apps_smmu 0x180 0x0>; 726 727 pinctrl-0 = <&sdc2_on_state>; 728 pinctrl-1 = <&sdc2_off_state>; 729 pinctrl-names = "default", "sleep"; 730 731 power-domains = <&rpmpd SM6125_VDDCX>; 732 733 qcom,dll-config = <0x0007642c>; 734 qcom,ddr-config = <0x80040873>; 735 736 bus-width = <4>; 737 status = "disabled"; 738 }; 739 740 gpi_dma0: dma-controller@4a00000 { 741 compatible = "qcom,sm6125-gpi-dma", "qcom,sdm845-gpi-dma"; 742 reg = <0x04a00000 0x60000>; 743 interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 744 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 745 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 746 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 747 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 748 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 749 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 750 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>; 751 dma-channels = <8>; 752 dma-channel-mask = <0x1f>; 753 iommus = <&apps_smmu 0x136 0x0>; 754 #dma-cells = <3>; 755 status = "disabled"; 756 }; 757 758 qupv3_id_0: geniqup@4ac0000 { 759 compatible = "qcom,geni-se-qup"; 760 reg = <0x04ac0000 0x2000>; 761 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 762 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 763 clock-names = "m-ahb", "s-ahb"; 764 iommus = <&apps_smmu 0x123 0x0>; 765 #address-cells = <1>; 766 #size-cells = <1>; 767 ranges; 768 status = "disabled"; 769 770 i2c0: i2c@4a80000 { 771 compatible = "qcom,geni-i2c"; 772 reg = <0x04a80000 0x4000>; 773 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 774 clock-names = "se"; 775 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 776 pinctrl-0 = <&qup_i2c0_default>; 777 pinctrl-1 = <&qup_i2c0_sleep>; 778 pinctrl-names = "default", "sleep"; 779 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 780 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 781 dma-names = "tx", "rx"; 782 #address-cells = <1>; 783 #size-cells = <0>; 784 status = "disabled"; 785 }; 786 787 spi0: spi@4a80000 { 788 compatible = "qcom,geni-spi"; 789 reg = <0x04a80000 0x4000>; 790 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 791 clock-names = "se"; 792 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 793 pinctrl-0 = <&qup_spi0_default>; 794 pinctrl-1 = <&qup_spi0_sleep>; 795 pinctrl-names = "default", "sleep"; 796 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 797 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 798 dma-names = "tx", "rx"; 799 #address-cells = <1>; 800 #size-cells = <0>; 801 status = "disabled"; 802 }; 803 804 i2c1: i2c@4a84000 { 805 compatible = "qcom,geni-i2c"; 806 reg = <0x04a84000 0x4000>; 807 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 808 clock-names = "se"; 809 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 810 pinctrl-0 = <&qup_i2c1_default>; 811 pinctrl-1 = <&qup_i2c1_sleep>; 812 pinctrl-names = "default", "sleep"; 813 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 814 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 815 dma-names = "tx", "rx"; 816 #address-cells = <1>; 817 #size-cells = <0>; 818 status = "disabled"; 819 }; 820 821 i2c2: i2c@4a88000 { 822 compatible = "qcom,geni-i2c"; 823 reg = <0x04a88000 0x4000>; 824 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 825 clock-names = "se"; 826 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; 827 pinctrl-0 = <&qup_i2c2_default>; 828 pinctrl-1 = <&qup_i2c2_sleep>; 829 pinctrl-names = "default", "sleep"; 830 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 831 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 832 dma-names = "tx", "rx"; 833 #address-cells = <1>; 834 #size-cells = <0>; 835 status = "disabled"; 836 }; 837 838 spi2: spi@4a88000 { 839 compatible = "qcom,geni-spi"; 840 reg = <0x04a88000 0x4000>; 841 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 842 clock-names = "se"; 843 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; 844 pinctrl-0 = <&qup_spi2_default>; 845 pinctrl-1 = <&qup_spi2_sleep>; 846 pinctrl-names = "default", "sleep"; 847 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 848 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 849 dma-names = "tx", "rx"; 850 #address-cells = <1>; 851 #size-cells = <0>; 852 status = "disabled"; 853 }; 854 855 i2c3: i2c@4a8c000 { 856 compatible = "qcom,geni-i2c"; 857 reg = <0x04a8c000 0x4000>; 858 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 859 clock-names = "se"; 860 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 861 pinctrl-0 = <&qup_i2c3_default>; 862 pinctrl-1 = <&qup_i2c3_sleep>; 863 pinctrl-names = "default", "sleep"; 864 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 865 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 866 dma-names = "tx", "rx"; 867 #address-cells = <1>; 868 #size-cells = <0>; 869 status = "disabled"; 870 }; 871 872 i2c4: i2c@4a90000 { 873 compatible = "qcom,geni-i2c"; 874 reg = <0x04a90000 0x4000>; 875 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 876 clock-names = "se"; 877 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 878 pinctrl-0 = <&qup_i2c4_default>; 879 pinctrl-1 = <&qup_i2c4_sleep>; 880 pinctrl-names = "default", "sleep"; 881 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 882 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 883 dma-names = "tx", "rx"; 884 #address-cells = <1>; 885 #size-cells = <0>; 886 status = "disabled"; 887 }; 888 }; 889 890 gpi_dma1: dma-controller@4c00000 { 891 compatible = "qcom,sm6125-gpi-dma", "qcom,sdm845-gpi-dma"; 892 reg = <0x04c00000 0x60000>; 893 interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 894 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 895 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 896 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 897 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 898 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 899 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 900 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; 901 dma-channels = <8>; 902 dma-channel-mask = <0x0f>; 903 iommus = <&apps_smmu 0x156 0x0>; 904 #dma-cells = <3>; 905 status = "disabled"; 906 }; 907 908 qupv3_id_1: geniqup@4cc0000 { 909 compatible = "qcom,geni-se-qup"; 910 reg = <0x04cc0000 0x2000>; 911 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 912 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 913 clock-names = "m-ahb", "s-ahb"; 914 iommus = <&apps_smmu 0x143 0x0>; 915 #address-cells = <1>; 916 #size-cells = <1>; 917 ranges; 918 status = "disabled"; 919 920 i2c5: i2c@4c80000 { 921 compatible = "qcom,geni-i2c"; 922 reg = <0x04c80000 0x4000>; 923 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 924 clock-names = "se"; 925 interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>; 926 pinctrl-0 = <&qup_i2c5_default>; 927 pinctrl-1 = <&qup_i2c5_sleep>; 928 pinctrl-names = "default", "sleep"; 929 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 930 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 931 dma-names = "tx", "rx"; 932 #address-cells = <1>; 933 #size-cells = <0>; 934 status = "disabled"; 935 }; 936 937 spi5: spi@4c80000 { 938 compatible = "qcom,geni-spi"; 939 reg = <0x04c80000 0x4000>; 940 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 941 clock-names = "se"; 942 interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>; 943 pinctrl-0 = <&qup_spi5_default>; 944 pinctrl-1 = <&qup_spi5_sleep>; 945 pinctrl-names = "default", "sleep"; 946 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 947 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 948 dma-names = "tx", "rx"; 949 #address-cells = <1>; 950 #size-cells = <0>; 951 status = "disabled"; 952 }; 953 954 i2c6: i2c@4c84000 { 955 compatible = "qcom,geni-i2c"; 956 reg = <0x04c84000 0x4000>; 957 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 958 clock-names = "se"; 959 interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>; 960 pinctrl-0 = <&qup_i2c6_default>; 961 pinctrl-1 = <&qup_i2c6_sleep>; 962 pinctrl-names = "default", "sleep"; 963 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 964 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 965 dma-names = "tx", "rx"; 966 #address-cells = <1>; 967 #size-cells = <0>; 968 status = "disabled"; 969 }; 970 971 spi6: spi@4c84000 { 972 compatible = "qcom,geni-spi"; 973 reg = <0x04c84000 0x4000>; 974 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 975 clock-names = "se"; 976 interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>; 977 pinctrl-0 = <&qup_spi6_default>; 978 pinctrl-1 = <&qup_spi6_sleep>; 979 pinctrl-names = "default", "sleep"; 980 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 981 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 982 dma-names = "tx", "rx"; 983 #address-cells = <1>; 984 #size-cells = <0>; 985 status = "disabled"; 986 }; 987 988 i2c7: i2c@4c88000 { 989 compatible = "qcom,geni-i2c"; 990 reg = <0x04c88000 0x4000>; 991 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 992 clock-names = "se"; 993 interrupts = <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>; 994 pinctrl-0 = <&qup_i2c7_default>; 995 pinctrl-1 = <&qup_i2c7_sleep>; 996 pinctrl-names = "default", "sleep"; 997 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 998 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 999 dma-names = "tx", "rx"; 1000 #address-cells = <1>; 1001 #size-cells = <0>; 1002 status = "disabled"; 1003 }; 1004 1005 i2c8: i2c@4c8c000 { 1006 compatible = "qcom,geni-i2c"; 1007 reg = <0x04c8c000 0x4000>; 1008 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1009 clock-names = "se"; 1010 interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>; 1011 pinctrl-0 = <&qup_i2c8_default>; 1012 pinctrl-1 = <&qup_i2c8_sleep>; 1013 pinctrl-names = "default", "sleep"; 1014 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1015 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1016 dma-names = "tx", "rx"; 1017 #address-cells = <1>; 1018 #size-cells = <0>; 1019 status = "disabled"; 1020 }; 1021 1022 spi8: spi@4c8c000 { 1023 compatible = "qcom,geni-spi"; 1024 reg = <0x04c8c000 0x4000>; 1025 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1026 clock-names = "se"; 1027 interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>; 1028 pinctrl-0 = <&qup_spi8_default>; 1029 pinctrl-1 = <&qup_spi8_sleep>; 1030 pinctrl-names = "default", "sleep"; 1031 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1032 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1033 dma-names = "tx", "rx"; 1034 #address-cells = <1>; 1035 #size-cells = <0>; 1036 status = "disabled"; 1037 }; 1038 1039 i2c9: i2c@4c90000 { 1040 compatible = "qcom,geni-i2c"; 1041 reg = <0x04c90000 0x4000>; 1042 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1043 clock-names = "se"; 1044 interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>; 1045 pinctrl-0 = <&qup_i2c9_default>; 1046 pinctrl-1 = <&qup_i2c9_sleep>; 1047 pinctrl-names = "default", "sleep"; 1048 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1049 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1050 dma-names = "tx", "rx"; 1051 #address-cells = <1>; 1052 #size-cells = <0>; 1053 status = "disabled"; 1054 }; 1055 1056 spi9: spi@4c90000 { 1057 compatible = "qcom,geni-spi"; 1058 reg = <0x04c90000 0x4000>; 1059 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1060 clock-names = "se"; 1061 interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>; 1062 pinctrl-0 = <&qup_spi9_default>; 1063 pinctrl-1 = <&qup_spi9_sleep>; 1064 pinctrl-names = "default", "sleep"; 1065 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1066 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1067 dma-names = "tx", "rx"; 1068 #address-cells = <1>; 1069 #size-cells = <0>; 1070 status = "disabled"; 1071 }; 1072 }; 1073 1074 usb3: usb@4ef8800 { 1075 compatible = "qcom,sm6125-dwc3", "qcom,dwc3"; 1076 reg = <0x04ef8800 0x400>; 1077 #address-cells = <1>; 1078 #size-cells = <1>; 1079 ranges; 1080 1081 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 1082 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 1083 <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>, 1084 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 1085 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1086 <&gcc GCC_USB3_PRIM_CLKREF_CLK>; 1087 clock-names = "cfg_noc", 1088 "core", 1089 "iface", 1090 "sleep", 1091 "mock_utmi", 1092 "xo"; 1093 1094 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1095 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 1096 assigned-clock-rates = <19200000>, <66666667>; 1097 1098 power-domains = <&gcc USB30_PRIM_GDSC>; 1099 qcom,select-utmi-as-pipe-clk; 1100 status = "disabled"; 1101 1102 usb3_dwc3: usb@4e00000 { 1103 compatible = "snps,dwc3"; 1104 reg = <0x04e00000 0xcd00>; 1105 interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 1106 iommus = <&apps_smmu 0x100 0x0>; 1107 phys = <&hsusb_phy1>; 1108 phy-names = "usb2-phy"; 1109 snps,dis_u2_susphy_quirk; 1110 snps,dis_enblslpm_quirk; 1111 maximum-speed = "high-speed"; 1112 dr_mode = "peripheral"; 1113 }; 1114 }; 1115 1116 sram@4690000 { 1117 compatible = "qcom,rpm-stats"; 1118 reg = <0x04690000 0x10000>; 1119 }; 1120 1121 spmi_bus: spmi@1c40000 { 1122 compatible = "qcom,spmi-pmic-arb"; 1123 reg = <0x01c40000 0x1100>, 1124 <0x01e00000 0x2000000>, 1125 <0x03e00000 0x100000>, 1126 <0x03f00000 0xa0000>, 1127 <0x01c0a000 0x26000>; 1128 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1129 interrupt-names = "periph_irq"; 1130 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 1131 qcom,ee = <0>; 1132 qcom,channel = <0>; 1133 #address-cells = <2>; 1134 #size-cells = <0>; 1135 interrupt-controller; 1136 #interrupt-cells = <4>; 1137 cell-index = <0>; 1138 }; 1139 1140 apps_smmu: iommu@c600000 { 1141 compatible = "qcom,sm6125-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 1142 reg = <0xc600000 0x80000>; 1143 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 1144 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 1145 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 1146 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 1147 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 1148 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 1149 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 1150 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 1151 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 1152 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 1153 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 1154 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 1155 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 1156 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 1157 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 1158 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 1159 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 1160 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 1161 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 1162 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 1163 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 1164 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 1165 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 1166 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1167 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 1168 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 1169 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 1170 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 1171 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 1172 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1173 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1174 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1175 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 1176 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1177 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1178 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1179 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1180 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1181 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1182 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1183 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 1184 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 1185 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 1186 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 1187 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 1188 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 1189 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1190 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 1191 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1192 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 1193 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 1194 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 1195 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 1196 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 1197 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 1198 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1199 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 1200 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1201 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1202 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1203 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1204 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 1205 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 1206 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 1207 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 1208 1209 #global-interrupts = <1>; 1210 #iommu-cells = <2>; 1211 }; 1212 1213 apcs_glb: mailbox@f111000 { 1214 compatible = "qcom,sm6125-apcs-hmss-global"; 1215 reg = <0x0f111000 0x1000>; 1216 1217 #mbox-cells = <1>; 1218 }; 1219 1220 timer@f120000 { 1221 compatible = "arm,armv7-timer-mem"; 1222 #address-cells = <1>; 1223 #size-cells = <1>; 1224 ranges; 1225 reg = <0x0f120000 0x1000>; 1226 clock-frequency = <19200000>; 1227 1228 frame@f121000 { 1229 frame-number = <0>; 1230 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1231 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 1232 reg = <0x0f121000 0x1000>, 1233 <0x0f122000 0x1000>; 1234 }; 1235 1236 frame@f123000 { 1237 frame-number = <1>; 1238 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1239 reg = <0x0f123000 0x1000>; 1240 status = "disabled"; 1241 }; 1242 1243 frame@f124000 { 1244 frame-number = <2>; 1245 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1246 reg = <0x0f124000 0x1000>; 1247 status = "disabled"; 1248 }; 1249 1250 frame@f125000 { 1251 frame-number = <3>; 1252 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1253 reg = <0x0f125000 0x1000>; 1254 status = "disabled"; 1255 }; 1256 1257 frame@f126000 { 1258 frame-number = <4>; 1259 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1260 reg = <0x0f126000 0x1000>; 1261 status = "disabled"; 1262 }; 1263 1264 frame@f127000 { 1265 frame-number = <5>; 1266 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1267 reg = <0x0f127000 0x1000>; 1268 status = "disabled"; 1269 }; 1270 1271 frame@f128000 { 1272 frame-number = <6>; 1273 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1274 reg = <0x0f128000 0x1000>; 1275 status = "disabled"; 1276 }; 1277 }; 1278 1279 intc: interrupt-controller@f200000 { 1280 compatible = "arm,gic-v3"; 1281 reg = <0x0f200000 0x20000>, 1282 <0x0f300000 0x100000>; 1283 #interrupt-cells = <3>; 1284 interrupt-controller; 1285 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 1286 }; 1287 }; 1288 1289 timer { 1290 compatible = "arm,armv8-timer"; 1291 interrupts = <GIC_PPI 1 0xf08 1292 GIC_PPI 2 0xf08 1293 GIC_PPI 3 0xf08 1294 GIC_PPI 0 0xf08>; 1295 clock-frequency = <19200000>; 1296 }; 1297}; 1298