1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2021, Martin Botka <martin.botka@somainline.org> 4 */ 5 6#include <dt-bindings/clock/qcom,gcc-sm6125.h> 7#include <dt-bindings/clock/qcom,rpmcc.h> 8#include <dt-bindings/dma/qcom-gpi.h> 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/power/qcom-rpmpd.h> 12 13/ { 14 interrupt-parent = <&intc>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 chosen { }; 19 20 clocks { 21 xo_board: xo-board { 22 compatible = "fixed-clock"; 23 #clock-cells = <0>; 24 clock-frequency = <19200000>; 25 clock-output-names = "xo_board"; 26 }; 27 28 sleep_clk: sleep-clk { 29 compatible = "fixed-clock"; 30 #clock-cells = <0>; 31 clock-frequency = <32000>; 32 clock-output-names = "sleep_clk"; 33 }; 34 }; 35 36 cpus { 37 #address-cells = <2>; 38 #size-cells = <0>; 39 40 CPU0: cpu@0 { 41 device_type = "cpu"; 42 compatible = "qcom,kryo260"; 43 reg = <0x0 0x0>; 44 enable-method = "psci"; 45 capacity-dmips-mhz = <1024>; 46 next-level-cache = <&L2_0>; 47 L2_0: l2-cache { 48 compatible = "cache"; 49 cache-level = <2>; 50 cache-unified; 51 }; 52 }; 53 54 CPU1: cpu@1 { 55 device_type = "cpu"; 56 compatible = "qcom,kryo260"; 57 reg = <0x0 0x1>; 58 enable-method = "psci"; 59 capacity-dmips-mhz = <1024>; 60 next-level-cache = <&L2_0>; 61 }; 62 63 CPU2: cpu@2 { 64 device_type = "cpu"; 65 compatible = "qcom,kryo260"; 66 reg = <0x0 0x2>; 67 enable-method = "psci"; 68 capacity-dmips-mhz = <1024>; 69 next-level-cache = <&L2_0>; 70 }; 71 72 CPU3: cpu@3 { 73 device_type = "cpu"; 74 compatible = "qcom,kryo260"; 75 reg = <0x0 0x3>; 76 enable-method = "psci"; 77 capacity-dmips-mhz = <1024>; 78 next-level-cache = <&L2_0>; 79 }; 80 81 CPU4: cpu@100 { 82 device_type = "cpu"; 83 compatible = "qcom,kryo260"; 84 reg = <0x0 0x100>; 85 enable-method = "psci"; 86 capacity-dmips-mhz = <1638>; 87 next-level-cache = <&L2_1>; 88 L2_1: l2-cache { 89 compatible = "cache"; 90 cache-level = <2>; 91 cache-unified; 92 }; 93 }; 94 95 CPU5: cpu@101 { 96 device_type = "cpu"; 97 compatible = "qcom,kryo260"; 98 reg = <0x0 0x101>; 99 enable-method = "psci"; 100 capacity-dmips-mhz = <1638>; 101 next-level-cache = <&L2_1>; 102 }; 103 104 CPU6: cpu@102 { 105 device_type = "cpu"; 106 compatible = "qcom,kryo260"; 107 reg = <0x0 0x102>; 108 enable-method = "psci"; 109 capacity-dmips-mhz = <1638>; 110 next-level-cache = <&L2_1>; 111 }; 112 113 CPU7: cpu@103 { 114 device_type = "cpu"; 115 compatible = "qcom,kryo260"; 116 reg = <0x0 0x103>; 117 enable-method = "psci"; 118 capacity-dmips-mhz = <1638>; 119 next-level-cache = <&L2_1>; 120 }; 121 122 cpu-map { 123 cluster0 { 124 core0 { 125 cpu = <&CPU0>; 126 }; 127 128 core1 { 129 cpu = <&CPU1>; 130 }; 131 132 core2 { 133 cpu = <&CPU2>; 134 }; 135 136 core3 { 137 cpu = <&CPU3>; 138 }; 139 }; 140 141 cluster1 { 142 core0 { 143 cpu = <&CPU4>; 144 }; 145 146 core1 { 147 cpu = <&CPU5>; 148 }; 149 150 core2 { 151 cpu = <&CPU6>; 152 }; 153 154 core3 { 155 cpu = <&CPU7>; 156 }; 157 }; 158 }; 159 }; 160 161 firmware { 162 scm: scm { 163 compatible = "qcom,scm-sm6125", "qcom,scm"; 164 #reset-cells = <1>; 165 }; 166 }; 167 168 memory@40000000 { 169 /* We expect the bootloader to fill in the size */ 170 reg = <0x0 0x40000000 0x0 0x0>; 171 device_type = "memory"; 172 }; 173 174 pmu { 175 compatible = "arm,armv8-pmuv3"; 176 interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>; 177 }; 178 179 psci { 180 compatible = "arm,psci-1.0"; 181 method = "smc"; 182 }; 183 184 rpm: remoteproc { 185 compatible = "qcom,sm6125-rpm-proc", "qcom,rpm-proc"; 186 187 glink-edge { 188 compatible = "qcom,glink-rpm"; 189 190 interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>; 191 qcom,rpm-msg-ram = <&rpm_msg_ram>; 192 mboxes = <&apcs_glb 0>; 193 194 rpm_requests: rpm-requests { 195 compatible = "qcom,rpm-sm6125"; 196 qcom,glink-channels = "rpm_requests"; 197 198 rpmcc: clock-controller { 199 compatible = "qcom,rpmcc-sm6125", "qcom,rpmcc"; 200 #clock-cells = <1>; 201 }; 202 203 rpmpd: power-controller { 204 compatible = "qcom,sm6125-rpmpd"; 205 #power-domain-cells = <1>; 206 operating-points-v2 = <&rpmpd_opp_table>; 207 208 rpmpd_opp_table: opp-table { 209 compatible = "operating-points-v2"; 210 211 rpmpd_opp_ret: opp1 { 212 opp-level = <RPM_SMD_LEVEL_RETENTION>; 213 }; 214 215 rpmpd_opp_ret_plus: opp2 { 216 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>; 217 }; 218 219 rpmpd_opp_min_svs: opp3 { 220 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 221 }; 222 223 rpmpd_opp_low_svs: opp4 { 224 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 225 }; 226 227 rpmpd_opp_svs: opp5 { 228 opp-level = <RPM_SMD_LEVEL_SVS>; 229 }; 230 231 rpmpd_opp_svs_plus: opp6 { 232 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 233 }; 234 235 rpmpd_opp_nom: opp7 { 236 opp-level = <RPM_SMD_LEVEL_NOM>; 237 }; 238 239 rpmpd_opp_nom_plus: opp8 { 240 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 241 }; 242 243 rpmpd_opp_turbo: opp9 { 244 opp-level = <RPM_SMD_LEVEL_TURBO>; 245 }; 246 247 rpmpd_opp_turbo_no_cpr: opp10 { 248 opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>; 249 }; 250 }; 251 }; 252 }; 253 }; 254 }; 255 256 reserved_memory: reserved-memory { 257 #address-cells = <2>; 258 #size-cells = <2>; 259 ranges; 260 261 hyp_mem: memory@45700000 { 262 reg = <0x0 0x45700000 0x0 0x600000>; 263 no-map; 264 }; 265 266 xbl_aop_mem: memory@45e00000 { 267 reg = <0x0 0x45e00000 0x0 0x140000>; 268 no-map; 269 }; 270 271 sec_apps_mem: memory@45fff000 { 272 reg = <0x0 0x45fff000 0x0 0x1000>; 273 no-map; 274 }; 275 276 smem_mem: memory@46000000 { 277 reg = <0x0 0x46000000 0x0 0x200000>; 278 no-map; 279 }; 280 281 reserved_mem1: memory@46200000 { 282 reg = <0x0 0x46200000 0x0 0x2d00000>; 283 no-map; 284 }; 285 286 camera_mem: memory@4ab00000 { 287 reg = <0x0 0x4ab00000 0x0 0x500000>; 288 no-map; 289 }; 290 291 modem_mem: memory@4b000000 { 292 reg = <0x0 0x4b000000 0x0 0x7e00000>; 293 no-map; 294 }; 295 296 venus_mem: memory@52e00000 { 297 reg = <0x0 0x52e00000 0x0 0x500000>; 298 no-map; 299 }; 300 301 wlan_msa_mem: memory@53300000 { 302 reg = <0x0 0x53300000 0x0 0x200000>; 303 no-map; 304 }; 305 306 cdsp_mem: memory@53500000 { 307 reg = <0x0 0x53500000 0x0 0x1e00000>; 308 no-map; 309 }; 310 311 adsp_pil_mem: memory@55300000 { 312 reg = <0x0 0x55300000 0x0 0x1e00000>; 313 no-map; 314 }; 315 316 ipa_fw_mem: memory@57100000 { 317 reg = <0x0 0x57100000 0x0 0x10000>; 318 no-map; 319 }; 320 321 ipa_gsi_mem: memory@57110000 { 322 reg = <0x0 0x57110000 0x0 0x5000>; 323 no-map; 324 }; 325 326 gpu_mem: memory@57115000 { 327 reg = <0x0 0x57115000 0x0 0x2000>; 328 no-map; 329 }; 330 331 cont_splash_mem: memory@5c000000 { 332 reg = <0x0 0x5c000000 0x0 0x00f00000>; 333 no-map; 334 }; 335 336 dfps_data_mem: memory@5cf00000 { 337 reg = <0x0 0x5cf00000 0x0 0x0100000>; 338 no-map; 339 }; 340 341 cdsp_sec_mem: memory@5f800000 { 342 reg = <0x0 0x5f800000 0x0 0x1e00000>; 343 no-map; 344 }; 345 346 qseecom_mem: memory@5e400000 { 347 reg = <0x0 0x5e400000 0x0 0x1400000>; 348 no-map; 349 }; 350 351 sdsp_mem: memory@f3000000 { 352 reg = <0x0 0xf3000000 0x0 0x400000>; 353 no-map; 354 }; 355 356 adsp_mem: memory@f3400000 { 357 reg = <0x0 0xf3400000 0x0 0x800000>; 358 no-map; 359 }; 360 361 qseecom_ta_mem: memory@13fc00000 { 362 reg = <0x1 0x3fc00000 0x0 0x400000>; 363 no-map; 364 }; 365 }; 366 367 smem: smem { 368 compatible = "qcom,smem"; 369 memory-region = <&smem_mem>; 370 hwlocks = <&tcsr_mutex 3>; 371 }; 372 373 soc@0 { 374 #address-cells = <1>; 375 #size-cells = <1>; 376 ranges = <0x00 0x00 0x00 0xffffffff>; 377 compatible = "simple-bus"; 378 379 tcsr_mutex: hwlock@340000 { 380 compatible = "qcom,tcsr-mutex"; 381 reg = <0x00340000 0x20000>; 382 #hwlock-cells = <1>; 383 }; 384 385 tlmm: pinctrl@500000 { 386 compatible = "qcom,sm6125-tlmm"; 387 reg = <0x00500000 0x400000>, 388 <0x00900000 0x400000>, 389 <0x00d00000 0x400000>; 390 reg-names = "west", "south", "east"; 391 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 392 gpio-controller; 393 gpio-ranges = <&tlmm 0 0 134>; 394 #gpio-cells = <2>; 395 interrupt-controller; 396 #interrupt-cells = <2>; 397 398 sdc2_off_state: sdc2-off-state { 399 clk-pins { 400 pins = "sdc2_clk"; 401 drive-strength = <2>; 402 bias-disable; 403 }; 404 405 cmd-pins { 406 pins = "sdc2_cmd"; 407 drive-strength = <2>; 408 bias-pull-up; 409 }; 410 411 data-pins { 412 pins = "sdc2_data"; 413 drive-strength = <2>; 414 bias-pull-up; 415 }; 416 }; 417 418 sdc2_on_state: sdc2-on-state { 419 clk-pins { 420 pins = "sdc2_clk"; 421 drive-strength = <16>; 422 bias-disable; 423 }; 424 425 cmd-pins { 426 pins = "sdc2_cmd"; 427 drive-strength = <10>; 428 bias-pull-up; 429 }; 430 431 data-pins { 432 pins = "sdc2_data"; 433 drive-strength = <10>; 434 bias-pull-up; 435 }; 436 }; 437 438 qup_i2c0_default: qup-i2c0-default-state { 439 pins = "gpio0", "gpio1"; 440 function = "qup00"; 441 drive-strength = <2>; 442 bias-disable; 443 }; 444 445 qup_i2c0_sleep: qup-i2c0-sleep-state { 446 pins = "gpio0", "gpio1"; 447 function = "gpio"; 448 drive-strength = <2>; 449 bias-pull-up; 450 }; 451 452 qup_i2c1_default: qup-i2c1-default-state { 453 pins = "gpio4", "gpio5"; 454 function = "qup01"; 455 drive-strength = <2>; 456 bias-disable; 457 }; 458 459 qup_i2c1_sleep: qup-i2c1-sleep-state { 460 pins = "gpio4", "gpio5"; 461 function = "gpio"; 462 drive-strength = <2>; 463 bias-pull-up; 464 }; 465 466 qup_i2c2_default: qup-i2c2-default-state { 467 pins = "gpio6", "gpio7"; 468 function = "qup02"; 469 drive-strength = <2>; 470 bias-disable; 471 }; 472 473 qup_i2c2_sleep: qup-i2c2-sleep-state { 474 pins = "gpio6", "gpio7"; 475 function = "gpio"; 476 drive-strength = <2>; 477 bias-pull-up; 478 }; 479 480 qup_i2c3_default: qup-i2c3-default-state { 481 pins = "gpio14", "gpio15"; 482 function = "qup03"; 483 drive-strength = <2>; 484 bias-disable; 485 }; 486 487 qup_i2c3_sleep: qup-i2c3-sleep-state { 488 pins = "gpio14", "gpio15"; 489 function = "gpio"; 490 drive-strength = <2>; 491 bias-pull-up; 492 }; 493 494 qup_i2c4_default: qup-i2c4-default-state { 495 pins = "gpio16", "gpio17"; 496 function = "qup04"; 497 drive-strength = <2>; 498 bias-disable; 499 }; 500 501 qup_i2c4_sleep: qup-i2c4-sleep-state { 502 pins = "gpio16", "gpio17"; 503 function = "gpio"; 504 drive-strength = <2>; 505 bias-pull-up; 506 }; 507 508 qup_i2c5_default: qup-i2c5-default-state { 509 pins = "gpio22", "gpio23"; 510 function = "qup10"; 511 drive-strength = <2>; 512 bias-disable; 513 }; 514 515 qup_i2c5_sleep: qup-i2c5-sleep-state { 516 pins = "gpio22", "gpio23"; 517 function = "gpio"; 518 drive-strength = <2>; 519 bias-pull-up; 520 }; 521 522 qup_i2c6_default: qup-i2c6-default-state { 523 pins = "gpio30", "gpio31"; 524 function = "qup11"; 525 drive-strength = <2>; 526 bias-disable; 527 }; 528 529 qup_i2c6_sleep: qup-i2c6-sleep-state { 530 pins = "gpio30", "gpio31"; 531 function = "gpio"; 532 drive-strength = <2>; 533 bias-pull-up; 534 }; 535 536 qup_i2c7_default: qup-i2c7-default-state { 537 pins = "gpio28", "gpio29"; 538 function = "qup12"; 539 drive-strength = <2>; 540 bias-disable; 541 }; 542 543 qup_i2c7_sleep: qup-i2c7-sleep-state { 544 pins = "gpio28", "gpio29"; 545 function = "gpio"; 546 drive-strength = <2>; 547 bias-pull-up; 548 }; 549 550 qup_i2c8_default: qup-i2c8-default-state { 551 pins = "gpio18", "gpio19"; 552 function = "qup13"; 553 drive-strength = <2>; 554 bias-disable; 555 }; 556 557 qup_i2c8_sleep: qup-i2c8-sleep-state { 558 pins = "gpio18", "gpio19"; 559 function = "gpio"; 560 drive-strength = <2>; 561 bias-pull-up; 562 }; 563 564 qup_i2c9_default: qup-i2c9-default-state { 565 pins = "gpio10", "gpio11"; 566 function = "qup14"; 567 drive-strength = <2>; 568 bias-disable; 569 }; 570 571 qup_i2c9_sleep: qup-i2c9-sleep-state { 572 pins = "gpio10", "gpio11"; 573 function = "gpio"; 574 drive-strength = <2>; 575 bias-pull-up; 576 }; 577 578 qup_spi0_default: qup-spi0-default-state { 579 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 580 function = "qup00"; 581 drive-strength = <6>; 582 bias-disable; 583 }; 584 585 qup_spi0_sleep: qup-spi0-sleep-state { 586 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 587 function = "gpio"; 588 drive-strength = <6>; 589 bias-disable; 590 }; 591 592 qup_spi2_default: qup-spi2-default-state { 593 pins = "gpio6", "gpio7", "gpio8", "gpio9"; 594 function = "qup02"; 595 drive-strength = <6>; 596 bias-disable; 597 }; 598 599 qup_spi2_sleep: qup-spi2-sleep-state { 600 pins = "gpio6", "gpio7", "gpio8", "gpio9"; 601 function = "gpio"; 602 drive-strength = <6>; 603 bias-disable; 604 }; 605 606 qup_spi5_default: qup-spi5-default-state { 607 pins = "gpio22", "gpio23", "gpio24", "gpio25"; 608 function = "qup10"; 609 drive-strength = <6>; 610 bias-disable; 611 }; 612 613 qup_spi5_sleep: qup-spi5-sleep-state { 614 pins = "gpio22", "gpio23", "gpio24", "gpio25"; 615 function = "gpio"; 616 drive-strength = <6>; 617 bias-disable; 618 }; 619 620 qup_spi6_default: qup-spi6-default-state { 621 pins = "gpio30", "gpio31", "gpio32", "gpio33"; 622 function = "qup11"; 623 drive-strength = <6>; 624 bias-disable; 625 }; 626 627 qup_spi6_sleep: qup-spi6-sleep-state { 628 pins = "gpio30", "gpio31", "gpio32", "gpio33"; 629 function = "gpio"; 630 drive-strength = <6>; 631 bias-disable; 632 }; 633 634 qup_spi8_default: qup-spi8-default-state { 635 pins = "gpio18", "gpio19", "gpio20", "gpio21"; 636 function = "qup13"; 637 drive-strength = <6>; 638 bias-disable; 639 }; 640 641 qup_spi8_sleep: qup-spi8-sleep-state { 642 pins = "gpio18", "gpio19", "gpio20", "gpio21"; 643 function = "gpio"; 644 drive-strength = <6>; 645 bias-disable; 646 }; 647 648 qup_spi9_default: qup-spi9-default-state { 649 pins = "gpio10", "gpio11", "gpio12", "gpio13"; 650 function = "qup14"; 651 drive-strength = <6>; 652 bias-disable; 653 }; 654 655 qup_spi9_sleep: qup-spi9-sleep-state { 656 pins = "gpio10", "gpio11", "gpio12", "gpio13"; 657 function = "gpio"; 658 drive-strength = <6>; 659 bias-disable; 660 }; 661 }; 662 663 gcc: clock-controller@1400000 { 664 compatible = "qcom,gcc-sm6125"; 665 reg = <0x01400000 0x1f0000>; 666 #clock-cells = <1>; 667 #reset-cells = <1>; 668 #power-domain-cells = <1>; 669 clock-names = "bi_tcxo", "sleep_clk"; 670 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>; 671 }; 672 673 hsusb_phy1: phy@1613000 { 674 compatible = "qcom,msm8996-qusb2-phy"; 675 reg = <0x01613000 0x180>; 676 #phy-cells = <0>; 677 678 clocks = <&gcc GCC_AHB2PHY_USB_CLK>, 679 <&rpmcc RPM_SMD_XO_CLK_SRC>; 680 clock-names = "cfg_ahb", "ref"; 681 682 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 683 status = "disabled"; 684 }; 685 686 rpm_msg_ram: sram@45f0000 { 687 compatible = "qcom,rpm-msg-ram"; 688 reg = <0x045f0000 0x7000>; 689 }; 690 691 sdhc_1: mmc@4744000 { 692 compatible = "qcom,sm6125-sdhci", "qcom,sdhci-msm-v5"; 693 reg = <0x04744000 0x1000>, <0x04745000 0x1000>; 694 reg-names = "hc", "cqhci"; 695 696 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, 697 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 698 interrupt-names = "hc_irq", "pwr_irq"; 699 700 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 701 <&gcc GCC_SDCC1_APPS_CLK>, 702 <&xo_board>; 703 clock-names = "iface", "core", "xo"; 704 iommus = <&apps_smmu 0x160 0x0>; 705 706 power-domains = <&rpmpd SM6125_VDDCX>; 707 708 qcom,dll-config = <0x000f642c>; 709 qcom,ddr-config = <0x80040873>; 710 711 bus-width = <8>; 712 non-removable; 713 supports-cqe; 714 715 status = "disabled"; 716 }; 717 718 sdhc_2: mmc@4784000 { 719 compatible = "qcom,sm6125-sdhci", "qcom,sdhci-msm-v5"; 720 reg = <0x04784000 0x1000>; 721 reg-names = "hc"; 722 723 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 724 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 725 interrupt-names = "hc_irq", "pwr_irq"; 726 727 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 728 <&gcc GCC_SDCC2_APPS_CLK>, 729 <&xo_board>; 730 clock-names = "iface", "core", "xo"; 731 iommus = <&apps_smmu 0x180 0x0>; 732 733 pinctrl-0 = <&sdc2_on_state>; 734 pinctrl-1 = <&sdc2_off_state>; 735 pinctrl-names = "default", "sleep"; 736 737 power-domains = <&rpmpd SM6125_VDDCX>; 738 739 qcom,dll-config = <0x0007642c>; 740 qcom,ddr-config = <0x80040873>; 741 742 bus-width = <4>; 743 status = "disabled"; 744 }; 745 746 ufs_mem_hc: ufs@4804000 { 747 compatible = "qcom,sm6125-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; 748 reg = <0x04804000 0x3000>, <0x04810000 0x8000>; 749 reg-names = "std", "ice"; 750 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 751 752 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 753 <&gcc GCC_SYS_NOC_UFS_PHY_AXI_CLK>, 754 <&gcc GCC_UFS_PHY_AHB_CLK>, 755 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 756 <&rpmcc RPM_SMD_XO_CLK_SRC>, 757 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 758 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 759 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 760 clock-names = "core_clk", 761 "bus_aggr_clk", 762 "iface_clk", 763 "core_clk_unipro", 764 "ref_clk", 765 "tx_lane0_sync_clk", 766 "rx_lane0_sync_clk", 767 "ice_core_clk"; 768 freq-table-hz = <50000000 240000000>, 769 <0 0>, 770 <0 0>, 771 <37500000 150000000>, 772 <0 0>, 773 <0 0>, 774 <0 0>, 775 <75000000 300000000>; 776 777 resets = <&gcc GCC_UFS_PHY_BCR>; 778 reset-names = "rst"; 779 #reset-cells = <1>; 780 781 phys = <&ufs_mem_phy>; 782 phy-names = "ufsphy"; 783 784 lanes-per-direction = <1>; 785 786 iommus = <&apps_smmu 0x200 0x0>; 787 788 status = "disabled"; 789 }; 790 791 ufs_mem_phy: phy@4807000 { 792 compatible = "qcom,sm6125-qmp-ufs-phy"; 793 reg = <0x04807000 0xdb8>; 794 795 clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, 796 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 797 clock-names = "ref", 798 "ref_aux"; 799 800 resets = <&ufs_mem_hc 0>; 801 reset-names = "ufsphy"; 802 803 power-domains = <&gcc UFS_PHY_GDSC>; 804 805 #phy-cells = <0>; 806 807 status = "disabled"; 808 }; 809 810 gpi_dma0: dma-controller@4a00000 { 811 compatible = "qcom,sm6125-gpi-dma", "qcom,sdm845-gpi-dma"; 812 reg = <0x04a00000 0x60000>; 813 interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 814 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 815 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 816 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 817 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 818 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 819 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 820 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>; 821 dma-channels = <8>; 822 dma-channel-mask = <0x1f>; 823 iommus = <&apps_smmu 0x136 0x0>; 824 #dma-cells = <3>; 825 status = "disabled"; 826 }; 827 828 qupv3_id_0: geniqup@4ac0000 { 829 compatible = "qcom,geni-se-qup"; 830 reg = <0x04ac0000 0x2000>; 831 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 832 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 833 clock-names = "m-ahb", "s-ahb"; 834 iommus = <&apps_smmu 0x123 0x0>; 835 #address-cells = <1>; 836 #size-cells = <1>; 837 ranges; 838 status = "disabled"; 839 840 i2c0: i2c@4a80000 { 841 compatible = "qcom,geni-i2c"; 842 reg = <0x04a80000 0x4000>; 843 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 844 clock-names = "se"; 845 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 846 pinctrl-0 = <&qup_i2c0_default>; 847 pinctrl-1 = <&qup_i2c0_sleep>; 848 pinctrl-names = "default", "sleep"; 849 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 850 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 851 dma-names = "tx", "rx"; 852 #address-cells = <1>; 853 #size-cells = <0>; 854 status = "disabled"; 855 }; 856 857 spi0: spi@4a80000 { 858 compatible = "qcom,geni-spi"; 859 reg = <0x04a80000 0x4000>; 860 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 861 clock-names = "se"; 862 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 863 pinctrl-0 = <&qup_spi0_default>; 864 pinctrl-1 = <&qup_spi0_sleep>; 865 pinctrl-names = "default", "sleep"; 866 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 867 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 868 dma-names = "tx", "rx"; 869 #address-cells = <1>; 870 #size-cells = <0>; 871 status = "disabled"; 872 }; 873 874 i2c1: i2c@4a84000 { 875 compatible = "qcom,geni-i2c"; 876 reg = <0x04a84000 0x4000>; 877 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 878 clock-names = "se"; 879 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 880 pinctrl-0 = <&qup_i2c1_default>; 881 pinctrl-1 = <&qup_i2c1_sleep>; 882 pinctrl-names = "default", "sleep"; 883 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 884 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 885 dma-names = "tx", "rx"; 886 #address-cells = <1>; 887 #size-cells = <0>; 888 status = "disabled"; 889 }; 890 891 i2c2: i2c@4a88000 { 892 compatible = "qcom,geni-i2c"; 893 reg = <0x04a88000 0x4000>; 894 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 895 clock-names = "se"; 896 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; 897 pinctrl-0 = <&qup_i2c2_default>; 898 pinctrl-1 = <&qup_i2c2_sleep>; 899 pinctrl-names = "default", "sleep"; 900 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 901 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 902 dma-names = "tx", "rx"; 903 #address-cells = <1>; 904 #size-cells = <0>; 905 status = "disabled"; 906 }; 907 908 spi2: spi@4a88000 { 909 compatible = "qcom,geni-spi"; 910 reg = <0x04a88000 0x4000>; 911 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 912 clock-names = "se"; 913 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; 914 pinctrl-0 = <&qup_spi2_default>; 915 pinctrl-1 = <&qup_spi2_sleep>; 916 pinctrl-names = "default", "sleep"; 917 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 918 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 919 dma-names = "tx", "rx"; 920 #address-cells = <1>; 921 #size-cells = <0>; 922 status = "disabled"; 923 }; 924 925 i2c3: i2c@4a8c000 { 926 compatible = "qcom,geni-i2c"; 927 reg = <0x04a8c000 0x4000>; 928 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 929 clock-names = "se"; 930 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 931 pinctrl-0 = <&qup_i2c3_default>; 932 pinctrl-1 = <&qup_i2c3_sleep>; 933 pinctrl-names = "default", "sleep"; 934 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 935 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 936 dma-names = "tx", "rx"; 937 #address-cells = <1>; 938 #size-cells = <0>; 939 status = "disabled"; 940 }; 941 942 i2c4: i2c@4a90000 { 943 compatible = "qcom,geni-i2c"; 944 reg = <0x04a90000 0x4000>; 945 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 946 clock-names = "se"; 947 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 948 pinctrl-0 = <&qup_i2c4_default>; 949 pinctrl-1 = <&qup_i2c4_sleep>; 950 pinctrl-names = "default", "sleep"; 951 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 952 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 953 dma-names = "tx", "rx"; 954 #address-cells = <1>; 955 #size-cells = <0>; 956 status = "disabled"; 957 }; 958 }; 959 960 gpi_dma1: dma-controller@4c00000 { 961 compatible = "qcom,sm6125-gpi-dma", "qcom,sdm845-gpi-dma"; 962 reg = <0x04c00000 0x60000>; 963 interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 964 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 965 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 966 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 967 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 968 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 969 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 970 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; 971 dma-channels = <8>; 972 dma-channel-mask = <0x0f>; 973 iommus = <&apps_smmu 0x156 0x0>; 974 #dma-cells = <3>; 975 status = "disabled"; 976 }; 977 978 qupv3_id_1: geniqup@4cc0000 { 979 compatible = "qcom,geni-se-qup"; 980 reg = <0x04cc0000 0x2000>; 981 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 982 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 983 clock-names = "m-ahb", "s-ahb"; 984 iommus = <&apps_smmu 0x143 0x0>; 985 #address-cells = <1>; 986 #size-cells = <1>; 987 ranges; 988 status = "disabled"; 989 990 i2c5: i2c@4c80000 { 991 compatible = "qcom,geni-i2c"; 992 reg = <0x04c80000 0x4000>; 993 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 994 clock-names = "se"; 995 interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>; 996 pinctrl-0 = <&qup_i2c5_default>; 997 pinctrl-1 = <&qup_i2c5_sleep>; 998 pinctrl-names = "default", "sleep"; 999 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1000 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1001 dma-names = "tx", "rx"; 1002 #address-cells = <1>; 1003 #size-cells = <0>; 1004 status = "disabled"; 1005 }; 1006 1007 spi5: spi@4c80000 { 1008 compatible = "qcom,geni-spi"; 1009 reg = <0x04c80000 0x4000>; 1010 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1011 clock-names = "se"; 1012 interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>; 1013 pinctrl-0 = <&qup_spi5_default>; 1014 pinctrl-1 = <&qup_spi5_sleep>; 1015 pinctrl-names = "default", "sleep"; 1016 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1017 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1018 dma-names = "tx", "rx"; 1019 #address-cells = <1>; 1020 #size-cells = <0>; 1021 status = "disabled"; 1022 }; 1023 1024 i2c6: i2c@4c84000 { 1025 compatible = "qcom,geni-i2c"; 1026 reg = <0x04c84000 0x4000>; 1027 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1028 clock-names = "se"; 1029 interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>; 1030 pinctrl-0 = <&qup_i2c6_default>; 1031 pinctrl-1 = <&qup_i2c6_sleep>; 1032 pinctrl-names = "default", "sleep"; 1033 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1034 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1035 dma-names = "tx", "rx"; 1036 #address-cells = <1>; 1037 #size-cells = <0>; 1038 status = "disabled"; 1039 }; 1040 1041 spi6: spi@4c84000 { 1042 compatible = "qcom,geni-spi"; 1043 reg = <0x04c84000 0x4000>; 1044 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1045 clock-names = "se"; 1046 interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>; 1047 pinctrl-0 = <&qup_spi6_default>; 1048 pinctrl-1 = <&qup_spi6_sleep>; 1049 pinctrl-names = "default", "sleep"; 1050 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1051 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1052 dma-names = "tx", "rx"; 1053 #address-cells = <1>; 1054 #size-cells = <0>; 1055 status = "disabled"; 1056 }; 1057 1058 i2c7: i2c@4c88000 { 1059 compatible = "qcom,geni-i2c"; 1060 reg = <0x04c88000 0x4000>; 1061 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1062 clock-names = "se"; 1063 interrupts = <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>; 1064 pinctrl-0 = <&qup_i2c7_default>; 1065 pinctrl-1 = <&qup_i2c7_sleep>; 1066 pinctrl-names = "default", "sleep"; 1067 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1068 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1069 dma-names = "tx", "rx"; 1070 #address-cells = <1>; 1071 #size-cells = <0>; 1072 status = "disabled"; 1073 }; 1074 1075 i2c8: i2c@4c8c000 { 1076 compatible = "qcom,geni-i2c"; 1077 reg = <0x04c8c000 0x4000>; 1078 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1079 clock-names = "se"; 1080 interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>; 1081 pinctrl-0 = <&qup_i2c8_default>; 1082 pinctrl-1 = <&qup_i2c8_sleep>; 1083 pinctrl-names = "default", "sleep"; 1084 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1085 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1086 dma-names = "tx", "rx"; 1087 #address-cells = <1>; 1088 #size-cells = <0>; 1089 status = "disabled"; 1090 }; 1091 1092 spi8: spi@4c8c000 { 1093 compatible = "qcom,geni-spi"; 1094 reg = <0x04c8c000 0x4000>; 1095 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1096 clock-names = "se"; 1097 interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>; 1098 pinctrl-0 = <&qup_spi8_default>; 1099 pinctrl-1 = <&qup_spi8_sleep>; 1100 pinctrl-names = "default", "sleep"; 1101 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1102 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1103 dma-names = "tx", "rx"; 1104 #address-cells = <1>; 1105 #size-cells = <0>; 1106 status = "disabled"; 1107 }; 1108 1109 i2c9: i2c@4c90000 { 1110 compatible = "qcom,geni-i2c"; 1111 reg = <0x04c90000 0x4000>; 1112 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1113 clock-names = "se"; 1114 interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>; 1115 pinctrl-0 = <&qup_i2c9_default>; 1116 pinctrl-1 = <&qup_i2c9_sleep>; 1117 pinctrl-names = "default", "sleep"; 1118 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1119 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1120 dma-names = "tx", "rx"; 1121 #address-cells = <1>; 1122 #size-cells = <0>; 1123 status = "disabled"; 1124 }; 1125 1126 spi9: spi@4c90000 { 1127 compatible = "qcom,geni-spi"; 1128 reg = <0x04c90000 0x4000>; 1129 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1130 clock-names = "se"; 1131 interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>; 1132 pinctrl-0 = <&qup_spi9_default>; 1133 pinctrl-1 = <&qup_spi9_sleep>; 1134 pinctrl-names = "default", "sleep"; 1135 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1136 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1137 dma-names = "tx", "rx"; 1138 #address-cells = <1>; 1139 #size-cells = <0>; 1140 status = "disabled"; 1141 }; 1142 }; 1143 1144 usb3: usb@4ef8800 { 1145 compatible = "qcom,sm6125-dwc3", "qcom,dwc3"; 1146 reg = <0x04ef8800 0x400>; 1147 #address-cells = <1>; 1148 #size-cells = <1>; 1149 ranges; 1150 1151 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 1152 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 1153 <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>, 1154 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 1155 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1156 <&gcc GCC_USB3_PRIM_CLKREF_CLK>; 1157 clock-names = "cfg_noc", 1158 "core", 1159 "iface", 1160 "sleep", 1161 "mock_utmi", 1162 "xo"; 1163 1164 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1165 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 1166 assigned-clock-rates = <19200000>, <66666667>; 1167 1168 power-domains = <&gcc USB30_PRIM_GDSC>; 1169 qcom,select-utmi-as-pipe-clk; 1170 status = "disabled"; 1171 1172 usb3_dwc3: usb@4e00000 { 1173 compatible = "snps,dwc3"; 1174 reg = <0x04e00000 0xcd00>; 1175 interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 1176 iommus = <&apps_smmu 0x100 0x0>; 1177 phys = <&hsusb_phy1>; 1178 phy-names = "usb2-phy"; 1179 snps,dis_u2_susphy_quirk; 1180 snps,dis_enblslpm_quirk; 1181 maximum-speed = "high-speed"; 1182 dr_mode = "peripheral"; 1183 }; 1184 }; 1185 1186 sram@4690000 { 1187 compatible = "qcom,rpm-stats"; 1188 reg = <0x04690000 0x10000>; 1189 }; 1190 1191 spmi_bus: spmi@1c40000 { 1192 compatible = "qcom,spmi-pmic-arb"; 1193 reg = <0x01c40000 0x1100>, 1194 <0x01e00000 0x2000000>, 1195 <0x03e00000 0x100000>, 1196 <0x03f00000 0xa0000>, 1197 <0x01c0a000 0x26000>; 1198 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1199 interrupt-names = "periph_irq"; 1200 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 1201 qcom,ee = <0>; 1202 qcom,channel = <0>; 1203 #address-cells = <2>; 1204 #size-cells = <0>; 1205 interrupt-controller; 1206 #interrupt-cells = <4>; 1207 }; 1208 1209 apps_smmu: iommu@c600000 { 1210 compatible = "qcom,sm6125-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 1211 reg = <0x0c600000 0x80000>; 1212 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 1213 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 1214 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 1215 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 1216 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 1217 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 1218 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 1219 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 1220 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 1221 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 1222 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 1223 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 1224 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 1225 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 1226 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 1227 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 1228 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 1229 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 1230 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 1231 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 1232 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 1233 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 1234 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 1235 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1236 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 1237 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 1238 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 1239 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 1240 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 1241 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1242 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1243 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1244 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 1245 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1246 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1247 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1248 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1249 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1250 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1251 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1252 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 1253 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 1254 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 1255 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 1256 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 1257 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 1258 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1259 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 1260 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1261 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 1262 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 1263 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 1264 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 1265 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 1266 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 1267 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1268 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 1269 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1270 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1271 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1272 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1273 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 1274 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 1275 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 1276 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 1277 1278 #global-interrupts = <1>; 1279 #iommu-cells = <2>; 1280 }; 1281 1282 apcs_glb: mailbox@f111000 { 1283 compatible = "qcom,sm6125-apcs-hmss-global", 1284 "qcom,msm8994-apcs-kpss-global"; 1285 reg = <0x0f111000 0x1000>; 1286 1287 #mbox-cells = <1>; 1288 }; 1289 1290 timer@f120000 { 1291 compatible = "arm,armv7-timer-mem"; 1292 #address-cells = <1>; 1293 #size-cells = <1>; 1294 ranges; 1295 reg = <0x0f120000 0x1000>; 1296 clock-frequency = <19200000>; 1297 1298 frame@f121000 { 1299 frame-number = <0>; 1300 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1301 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 1302 reg = <0x0f121000 0x1000>, 1303 <0x0f122000 0x1000>; 1304 }; 1305 1306 frame@f123000 { 1307 frame-number = <1>; 1308 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1309 reg = <0x0f123000 0x1000>; 1310 status = "disabled"; 1311 }; 1312 1313 frame@f124000 { 1314 frame-number = <2>; 1315 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1316 reg = <0x0f124000 0x1000>; 1317 status = "disabled"; 1318 }; 1319 1320 frame@f125000 { 1321 frame-number = <3>; 1322 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1323 reg = <0x0f125000 0x1000>; 1324 status = "disabled"; 1325 }; 1326 1327 frame@f126000 { 1328 frame-number = <4>; 1329 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1330 reg = <0x0f126000 0x1000>; 1331 status = "disabled"; 1332 }; 1333 1334 frame@f127000 { 1335 frame-number = <5>; 1336 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1337 reg = <0x0f127000 0x1000>; 1338 status = "disabled"; 1339 }; 1340 1341 frame@f128000 { 1342 frame-number = <6>; 1343 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1344 reg = <0x0f128000 0x1000>; 1345 status = "disabled"; 1346 }; 1347 }; 1348 1349 intc: interrupt-controller@f200000 { 1350 compatible = "arm,gic-v3"; 1351 reg = <0x0f200000 0x20000>, 1352 <0x0f300000 0x100000>; 1353 #interrupt-cells = <3>; 1354 interrupt-controller; 1355 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 1356 }; 1357 }; 1358 1359 timer { 1360 compatible = "arm,armv8-timer"; 1361 interrupts = <GIC_PPI 1 0xf08 1362 GIC_PPI 2 0xf08 1363 GIC_PPI 3 0xf08 1364 GIC_PPI 0 0xf08>; 1365 clock-frequency = <19200000>; 1366 }; 1367}; 1368