1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright (c) 2021, Iskren Chernev <iskren.chernev@gmail.com> 4 */ 5 6#include <dt-bindings/clock/qcom,gcc-sm6115.h> 7#include <dt-bindings/clock/qcom,sm6115-dispcc.h> 8#include <dt-bindings/clock/qcom,sm6115-gpucc.h> 9#include <dt-bindings/clock/qcom,rpmcc.h> 10#include <dt-bindings/dma/qcom-gpi.h> 11#include <dt-bindings/firmware/qcom,scm.h> 12#include <dt-bindings/gpio/gpio.h> 13#include <dt-bindings/interrupt-controller/arm-gic.h> 14#include <dt-bindings/power/qcom-rpmpd.h> 15 16/ { 17 interrupt-parent = <&intc>; 18 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 chosen { }; 23 24 clocks { 25 xo_board: xo-board { 26 compatible = "fixed-clock"; 27 #clock-cells = <0>; 28 }; 29 30 sleep_clk: sleep-clk { 31 compatible = "fixed-clock"; 32 #clock-cells = <0>; 33 }; 34 }; 35 36 cpus { 37 #address-cells = <2>; 38 #size-cells = <0>; 39 40 CPU0: cpu@0 { 41 device_type = "cpu"; 42 compatible = "qcom,kryo260"; 43 reg = <0x0 0x0>; 44 clocks = <&cpufreq_hw 0>; 45 capacity-dmips-mhz = <1024>; 46 dynamic-power-coefficient = <100>; 47 enable-method = "psci"; 48 next-level-cache = <&L2_0>; 49 qcom,freq-domain = <&cpufreq_hw 0>; 50 L2_0: l2-cache { 51 compatible = "cache"; 52 cache-level = <2>; 53 }; 54 }; 55 56 CPU1: cpu@1 { 57 device_type = "cpu"; 58 compatible = "qcom,kryo260"; 59 reg = <0x0 0x1>; 60 clocks = <&cpufreq_hw 0>; 61 capacity-dmips-mhz = <1024>; 62 dynamic-power-coefficient = <100>; 63 enable-method = "psci"; 64 next-level-cache = <&L2_0>; 65 qcom,freq-domain = <&cpufreq_hw 0>; 66 }; 67 68 CPU2: cpu@2 { 69 device_type = "cpu"; 70 compatible = "qcom,kryo260"; 71 reg = <0x0 0x2>; 72 clocks = <&cpufreq_hw 0>; 73 capacity-dmips-mhz = <1024>; 74 dynamic-power-coefficient = <100>; 75 enable-method = "psci"; 76 next-level-cache = <&L2_0>; 77 qcom,freq-domain = <&cpufreq_hw 0>; 78 }; 79 80 CPU3: cpu@3 { 81 device_type = "cpu"; 82 compatible = "qcom,kryo260"; 83 reg = <0x0 0x3>; 84 clocks = <&cpufreq_hw 0>; 85 capacity-dmips-mhz = <1024>; 86 dynamic-power-coefficient = <100>; 87 enable-method = "psci"; 88 next-level-cache = <&L2_0>; 89 qcom,freq-domain = <&cpufreq_hw 0>; 90 }; 91 92 CPU4: cpu@100 { 93 device_type = "cpu"; 94 compatible = "qcom,kryo260"; 95 reg = <0x0 0x100>; 96 clocks = <&cpufreq_hw 1>; 97 enable-method = "psci"; 98 capacity-dmips-mhz = <1638>; 99 dynamic-power-coefficient = <282>; 100 next-level-cache = <&L2_1>; 101 qcom,freq-domain = <&cpufreq_hw 1>; 102 L2_1: l2-cache { 103 compatible = "cache"; 104 cache-level = <2>; 105 }; 106 }; 107 108 CPU5: cpu@101 { 109 device_type = "cpu"; 110 compatible = "qcom,kryo260"; 111 reg = <0x0 0x101>; 112 clocks = <&cpufreq_hw 1>; 113 capacity-dmips-mhz = <1638>; 114 dynamic-power-coefficient = <282>; 115 enable-method = "psci"; 116 next-level-cache = <&L2_1>; 117 qcom,freq-domain = <&cpufreq_hw 1>; 118 }; 119 120 CPU6: cpu@102 { 121 device_type = "cpu"; 122 compatible = "qcom,kryo260"; 123 reg = <0x0 0x102>; 124 clocks = <&cpufreq_hw 1>; 125 capacity-dmips-mhz = <1638>; 126 dynamic-power-coefficient = <282>; 127 enable-method = "psci"; 128 next-level-cache = <&L2_1>; 129 qcom,freq-domain = <&cpufreq_hw 1>; 130 }; 131 132 CPU7: cpu@103 { 133 device_type = "cpu"; 134 compatible = "qcom,kryo260"; 135 reg = <0x0 0x103>; 136 clocks = <&cpufreq_hw 1>; 137 capacity-dmips-mhz = <1638>; 138 dynamic-power-coefficient = <282>; 139 enable-method = "psci"; 140 next-level-cache = <&L2_1>; 141 qcom,freq-domain = <&cpufreq_hw 1>; 142 }; 143 144 cpu-map { 145 cluster0 { 146 core0 { 147 cpu = <&CPU0>; 148 }; 149 150 core1 { 151 cpu = <&CPU1>; 152 }; 153 154 core2 { 155 cpu = <&CPU2>; 156 }; 157 158 core3 { 159 cpu = <&CPU3>; 160 }; 161 }; 162 163 cluster1 { 164 core0 { 165 cpu = <&CPU4>; 166 }; 167 168 core1 { 169 cpu = <&CPU5>; 170 }; 171 172 core2 { 173 cpu = <&CPU6>; 174 }; 175 176 core3 { 177 cpu = <&CPU7>; 178 }; 179 }; 180 }; 181 }; 182 183 firmware { 184 scm: scm { 185 compatible = "qcom,scm-sm6115", "qcom,scm"; 186 #reset-cells = <1>; 187 }; 188 }; 189 190 memory@80000000 { 191 device_type = "memory"; 192 /* We expect the bootloader to fill in the size */ 193 reg = <0 0x80000000 0 0>; 194 }; 195 196 pmu { 197 compatible = "arm,armv8-pmuv3"; 198 interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>; 199 }; 200 201 psci { 202 compatible = "arm,psci-1.0"; 203 method = "smc"; 204 }; 205 206 reserved_memory: reserved-memory { 207 #address-cells = <2>; 208 #size-cells = <2>; 209 ranges; 210 211 hyp_mem: memory@45700000 { 212 reg = <0x0 0x45700000 0x0 0x600000>; 213 no-map; 214 }; 215 216 xbl_aop_mem: memory@45e00000 { 217 reg = <0x0 0x45e00000 0x0 0x140000>; 218 no-map; 219 }; 220 221 sec_apps_mem: memory@45fff000 { 222 reg = <0x0 0x45fff000 0x0 0x1000>; 223 no-map; 224 }; 225 226 smem_mem: memory@46000000 { 227 compatible = "qcom,smem"; 228 reg = <0x0 0x46000000 0x0 0x200000>; 229 no-map; 230 231 hwlocks = <&tcsr_mutex 3>; 232 qcom,rpm-msg-ram = <&rpm_msg_ram>; 233 }; 234 235 cdsp_sec_mem: memory@46200000 { 236 reg = <0x0 0x46200000 0x0 0x1e00000>; 237 no-map; 238 }; 239 240 pil_modem_mem: memory@4ab00000 { 241 reg = <0x0 0x4ab00000 0x0 0x6900000>; 242 no-map; 243 }; 244 245 pil_video_mem: memory@51400000 { 246 reg = <0x0 0x51400000 0x0 0x500000>; 247 no-map; 248 }; 249 250 wlan_msa_mem: memory@51900000 { 251 reg = <0x0 0x51900000 0x0 0x100000>; 252 no-map; 253 }; 254 255 pil_cdsp_mem: memory@51a00000 { 256 reg = <0x0 0x51a00000 0x0 0x1e00000>; 257 no-map; 258 }; 259 260 pil_adsp_mem: memory@53800000 { 261 reg = <0x0 0x53800000 0x0 0x2800000>; 262 no-map; 263 }; 264 265 pil_ipa_fw_mem: memory@56100000 { 266 reg = <0x0 0x56100000 0x0 0x10000>; 267 no-map; 268 }; 269 270 pil_ipa_gsi_mem: memory@56110000 { 271 reg = <0x0 0x56110000 0x0 0x5000>; 272 no-map; 273 }; 274 275 pil_gpu_mem: memory@56115000 { 276 reg = <0x0 0x56115000 0x0 0x2000>; 277 no-map; 278 }; 279 280 cont_splash_memory: memory@5c000000 { 281 reg = <0x0 0x5c000000 0x0 0x00f00000>; 282 no-map; 283 }; 284 285 dfps_data_memory: memory@5cf00000 { 286 reg = <0x0 0x5cf00000 0x0 0x0100000>; 287 no-map; 288 }; 289 290 removed_mem: memory@60000000 { 291 reg = <0x0 0x60000000 0x0 0x3900000>; 292 no-map; 293 }; 294 295 rmtfs_mem: memory@89b01000 { 296 compatible = "qcom,rmtfs-mem"; 297 reg = <0x0 0x89b01000 0x0 0x200000>; 298 no-map; 299 300 qcom,client-id = <1>; 301 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA QCOM_SCM_VMID_NAV>; 302 }; 303 }; 304 305 rpm-glink { 306 compatible = "qcom,glink-rpm"; 307 308 interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>; 309 qcom,rpm-msg-ram = <&rpm_msg_ram>; 310 mboxes = <&apcs_glb 0>; 311 312 rpm_requests: rpm-requests { 313 compatible = "qcom,rpm-sm6115"; 314 qcom,glink-channels = "rpm_requests"; 315 316 rpmcc: clock-controller { 317 compatible = "qcom,rpmcc-sm6115", "qcom,rpmcc"; 318 clocks = <&xo_board>; 319 clock-names = "xo"; 320 #clock-cells = <1>; 321 }; 322 323 rpmpd: power-controller { 324 compatible = "qcom,sm6115-rpmpd"; 325 #power-domain-cells = <1>; 326 operating-points-v2 = <&rpmpd_opp_table>; 327 328 rpmpd_opp_table: opp-table { 329 compatible = "operating-points-v2"; 330 331 rpmpd_opp_min_svs: opp1 { 332 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 333 }; 334 335 rpmpd_opp_low_svs: opp2 { 336 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 337 }; 338 339 rpmpd_opp_svs: opp3 { 340 opp-level = <RPM_SMD_LEVEL_SVS>; 341 }; 342 343 rpmpd_opp_svs_plus: opp4 { 344 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 345 }; 346 347 rpmpd_opp_nom: opp5 { 348 opp-level = <RPM_SMD_LEVEL_NOM>; 349 }; 350 351 rpmpd_opp_nom_plus: opp6 { 352 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 353 }; 354 355 rpmpd_opp_turbo: opp7 { 356 opp-level = <RPM_SMD_LEVEL_TURBO>; 357 }; 358 359 rpmpd_opp_turbo_plus: opp8 { 360 opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>; 361 }; 362 }; 363 }; 364 }; 365 }; 366 367 smp2p-adsp { 368 compatible = "qcom,smp2p"; 369 qcom,smem = <443>, <429>; 370 371 interrupts = <GIC_SPI 279 IRQ_TYPE_EDGE_RISING>; 372 373 mboxes = <&apcs_glb 10>; 374 375 qcom,local-pid = <0>; 376 qcom,remote-pid = <2>; 377 378 adsp_smp2p_out: master-kernel { 379 qcom,entry-name = "master-kernel"; 380 #qcom,smem-state-cells = <1>; 381 }; 382 383 adsp_smp2p_in: slave-kernel { 384 qcom,entry-name = "slave-kernel"; 385 386 interrupt-controller; 387 #interrupt-cells = <2>; 388 }; 389 }; 390 391 smp2p-cdsp { 392 compatible = "qcom,smp2p"; 393 qcom,smem = <94>, <432>; 394 395 interrupts = <GIC_SPI 263 IRQ_TYPE_EDGE_RISING>; 396 397 mboxes = <&apcs_glb 30>; 398 399 qcom,local-pid = <0>; 400 qcom,remote-pid = <5>; 401 402 cdsp_smp2p_out: master-kernel { 403 qcom,entry-name = "master-kernel"; 404 #qcom,smem-state-cells = <1>; 405 }; 406 407 cdsp_smp2p_in: slave-kernel { 408 qcom,entry-name = "slave-kernel"; 409 410 interrupt-controller; 411 #interrupt-cells = <2>; 412 }; 413 }; 414 415 smp2p-mpss { 416 compatible = "qcom,smp2p"; 417 qcom,smem = <435>, <428>; 418 419 interrupts = <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>; 420 421 mboxes = <&apcs_glb 14>; 422 423 qcom,local-pid = <0>; 424 qcom,remote-pid = <1>; 425 426 modem_smp2p_out: master-kernel { 427 qcom,entry-name = "master-kernel"; 428 #qcom,smem-state-cells = <1>; 429 }; 430 431 modem_smp2p_in: slave-kernel { 432 qcom,entry-name = "slave-kernel"; 433 434 interrupt-controller; 435 #interrupt-cells = <2>; 436 }; 437 }; 438 439 soc: soc@0 { 440 compatible = "simple-bus"; 441 #address-cells = <2>; 442 #size-cells = <2>; 443 ranges = <0 0 0 0 0x10 0>; 444 dma-ranges = <0 0 0 0 0x10 0>; 445 446 tcsr_mutex: hwlock@340000 { 447 compatible = "qcom,tcsr-mutex"; 448 reg = <0x0 0x00340000 0x0 0x20000>; 449 #hwlock-cells = <1>; 450 }; 451 452 tlmm: pinctrl@500000 { 453 compatible = "qcom,sm6115-tlmm"; 454 reg = <0x0 0x00500000 0x0 0x400000>, 455 <0x0 0x00900000 0x0 0x400000>, 456 <0x0 0x00d00000 0x0 0x400000>; 457 reg-names = "west", "south", "east"; 458 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 459 gpio-controller; 460 gpio-ranges = <&tlmm 0 0 114>; /* GPIOs + ufs_reset */ 461 #gpio-cells = <2>; 462 interrupt-controller; 463 #interrupt-cells = <2>; 464 465 qup_i2c0_default: qup-i2c0-default-state { 466 pins = "gpio0", "gpio1"; 467 function = "qup0"; 468 drive-strength = <2>; 469 bias-pull-up; 470 }; 471 472 qup_i2c1_default: qup-i2c1-default-state { 473 pins = "gpio4", "gpio5"; 474 function = "qup1"; 475 drive-strength = <2>; 476 bias-pull-up; 477 }; 478 479 qup_i2c2_default: qup-i2c2-default-state { 480 pins = "gpio6", "gpio7"; 481 function = "qup2"; 482 drive-strength = <2>; 483 bias-pull-up; 484 }; 485 486 qup_i2c3_default: qup-i2c3-default-state { 487 pins = "gpio8", "gpio9"; 488 function = "qup3"; 489 drive-strength = <2>; 490 bias-pull-up; 491 }; 492 493 qup_i2c4_default: qup-i2c4-default-state { 494 pins = "gpio12", "gpio13"; 495 function = "qup4"; 496 drive-strength = <2>; 497 bias-pull-up; 498 }; 499 500 qup_i2c5_default: qup-i2c5-default-state { 501 pins = "gpio14", "gpio15"; 502 function = "qup5"; 503 drive-strength = <2>; 504 bias-pull-up; 505 }; 506 507 qup_spi0_default: qup-spi0-default-state { 508 pins = "gpio0", "gpio1","gpio2", "gpio3"; 509 function = "qup0"; 510 drive-strength = <2>; 511 bias-pull-up; 512 }; 513 514 qup_spi1_default: qup-spi1-default-state { 515 pins = "gpio4", "gpio5", "gpio69", "gpio70"; 516 function = "qup1"; 517 drive-strength = <2>; 518 bias-pull-up; 519 }; 520 521 qup_spi2_default: qup-spi2-default-state { 522 pins = "gpio6", "gpio7", "gpio71", "gpio80"; 523 function = "qup2"; 524 drive-strength = <2>; 525 bias-pull-up; 526 }; 527 528 qup_spi3_default: qup-spi3-default-state { 529 pins = "gpio8", "gpio9", "gpio10", "gpio11"; 530 function = "qup3"; 531 drive-strength = <2>; 532 bias-pull-up; 533 }; 534 535 qup_spi4_default: qup-spi4-default-state { 536 pins = "gpio12", "gpio13", "gpio96", "gpio97"; 537 function = "qup4"; 538 drive-strength = <2>; 539 bias-pull-up; 540 }; 541 542 qup_spi5_default: qup-spi5-default-state { 543 pins = "gpio14", "gpio15", "gpio16", "gpio17"; 544 function = "qup5"; 545 drive-strength = <2>; 546 bias-pull-up; 547 }; 548 549 sdc1_state_on: sdc1-on-state { 550 clk-pins { 551 pins = "sdc1_clk"; 552 bias-disable; 553 drive-strength = <16>; 554 }; 555 556 cmd-pins { 557 pins = "sdc1_cmd"; 558 bias-pull-up; 559 drive-strength = <10>; 560 }; 561 562 data-pins { 563 pins = "sdc1_data"; 564 bias-pull-up; 565 drive-strength = <10>; 566 }; 567 568 rclk-pins { 569 pins = "sdc1_rclk"; 570 bias-pull-down; 571 }; 572 }; 573 574 sdc1_state_off: sdc1-off-state { 575 clk-pins { 576 pins = "sdc1_clk"; 577 bias-disable; 578 drive-strength = <2>; 579 }; 580 581 cmd-pins { 582 pins = "sdc1_cmd"; 583 bias-pull-up; 584 drive-strength = <2>; 585 }; 586 587 data-pins { 588 pins = "sdc1_data"; 589 bias-pull-up; 590 drive-strength = <2>; 591 }; 592 593 rclk-pins { 594 pins = "sdc1_rclk"; 595 bias-pull-down; 596 }; 597 }; 598 599 sdc2_state_on: sdc2-on-state { 600 clk-pins { 601 pins = "sdc2_clk"; 602 bias-disable; 603 drive-strength = <16>; 604 }; 605 606 cmd-pins { 607 pins = "sdc2_cmd"; 608 bias-pull-up; 609 drive-strength = <10>; 610 }; 611 612 data-pins { 613 pins = "sdc2_data"; 614 bias-pull-up; 615 drive-strength = <10>; 616 }; 617 }; 618 619 sdc2_state_off: sdc2-off-state { 620 clk-pins { 621 pins = "sdc2_clk"; 622 bias-disable; 623 drive-strength = <2>; 624 }; 625 626 cmd-pins { 627 pins = "sdc2_cmd"; 628 bias-pull-up; 629 drive-strength = <2>; 630 }; 631 632 data-pins { 633 pins = "sdc2_data"; 634 bias-pull-up; 635 drive-strength = <2>; 636 }; 637 }; 638 }; 639 640 gcc: clock-controller@1400000 { 641 compatible = "qcom,gcc-sm6115"; 642 reg = <0x0 0x01400000 0x0 0x1f0000>; 643 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>; 644 clock-names = "bi_tcxo", "sleep_clk"; 645 #clock-cells = <1>; 646 #reset-cells = <1>; 647 #power-domain-cells = <1>; 648 }; 649 650 usb_hsphy: phy@1613000 { 651 compatible = "qcom,sm6115-qusb2-phy"; 652 reg = <0x0 0x01613000 0x0 0x180>; 653 #phy-cells = <0>; 654 655 clocks = <&gcc GCC_AHB2PHY_USB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>; 656 clock-names = "cfg_ahb", "ref"; 657 658 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 659 nvmem-cells = <&qusb2_hstx_trim>; 660 661 status = "disabled"; 662 }; 663 664 qfprom@1b40000 { 665 compatible = "qcom,sm6115-qfprom", "qcom,qfprom"; 666 reg = <0x0 0x01b40000 0x0 0x7000>; 667 #address-cells = <1>; 668 #size-cells = <1>; 669 670 qusb2_hstx_trim: hstx-trim@25b { 671 reg = <0x25b 0x1>; 672 bits = <1 4>; 673 }; 674 }; 675 676 rng: rng@1b53000 { 677 compatible = "qcom,prng-ee"; 678 reg = <0x0 0x01b53000 0x0 0x1000>; 679 clocks = <&gcc GCC_PRNG_AHB_CLK>; 680 clock-names = "core"; 681 }; 682 683 spmi_bus: spmi@1c40000 { 684 compatible = "qcom,spmi-pmic-arb"; 685 reg = <0x0 0x01c40000 0x0 0x1100>, 686 <0x0 0x01e00000 0x0 0x2000000>, 687 <0x0 0x03e00000 0x0 0x100000>, 688 <0x0 0x03f00000 0x0 0xa0000>, 689 <0x0 0x01c0a000 0x0 0x26000>; 690 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 691 interrupt-names = "periph_irq"; 692 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 693 qcom,ee = <0>; 694 qcom,channel = <0>; 695 #address-cells = <2>; 696 #size-cells = <0>; 697 interrupt-controller; 698 #interrupt-cells = <4>; 699 }; 700 701 tsens0: thermal-sensor@4410000 { 702 compatible = "qcom,sm6115-tsens", "qcom,tsens-v2"; 703 reg = <0x0 0x04411000 0x0 0x1ff>, /* TM */ 704 <0x0 0x04410000 0x0 0x8>; /* SROT */ 705 #qcom,sensors = <16>; 706 interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 707 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 708 interrupt-names = "uplow", "critical"; 709 #thermal-sensor-cells = <1>; 710 }; 711 712 rpm_msg_ram: sram@45f0000 { 713 compatible = "qcom,rpm-msg-ram"; 714 reg = <0x0 0x045f0000 0x0 0x7000>; 715 }; 716 717 sram@4690000 { 718 compatible = "qcom,rpm-stats"; 719 reg = <0x0 0x04690000 0x0 0x10000>; 720 }; 721 722 sdhc_1: mmc@4744000 { 723 compatible = "qcom,sm6115-sdhci", "qcom,sdhci-msm-v5"; 724 reg = <0x0 0x04744000 0x0 0x1000>, 725 <0x0 0x04745000 0x0 0x1000>, 726 <0x0 0x04748000 0x0 0x8000>; 727 reg-names = "hc", "cqhci", "ice"; 728 729 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, 730 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 731 interrupt-names = "hc_irq", "pwr_irq"; 732 733 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 734 <&gcc GCC_SDCC1_APPS_CLK>, 735 <&rpmcc RPM_SMD_XO_CLK_SRC>, 736 <&gcc GCC_SDCC1_ICE_CORE_CLK>; 737 clock-names = "iface", "core", "xo", "ice"; 738 739 bus-width = <8>; 740 status = "disabled"; 741 }; 742 743 sdhc_2: mmc@4784000 { 744 compatible = "qcom,sm6115-sdhci", "qcom,sdhci-msm-v5"; 745 reg = <0x0 0x04784000 0x0 0x1000>; 746 reg-names = "hc"; 747 748 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 749 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 750 interrupt-names = "hc_irq", "pwr_irq"; 751 752 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 753 <&gcc GCC_SDCC2_APPS_CLK>, 754 <&rpmcc RPM_SMD_XO_CLK_SRC>; 755 clock-names = "iface", "core", "xo"; 756 757 power-domains = <&rpmpd SM6115_VDDCX>; 758 operating-points-v2 = <&sdhc2_opp_table>; 759 iommus = <&apps_smmu 0x00a0 0x0>; 760 resets = <&gcc GCC_SDCC2_BCR>; 761 762 bus-width = <4>; 763 qcom,dll-config = <0x0007642c>; 764 qcom,ddr-config = <0x80040868>; 765 status = "disabled"; 766 767 sdhc2_opp_table: opp-table { 768 compatible = "operating-points-v2"; 769 770 opp-100000000 { 771 opp-hz = /bits/ 64 <100000000>; 772 required-opps = <&rpmpd_opp_low_svs>; 773 }; 774 775 opp-202000000 { 776 opp-hz = /bits/ 64 <202000000>; 777 required-opps = <&rpmpd_opp_nom>; 778 }; 779 }; 780 }; 781 782 ufs_mem_hc: ufs@4804000 { 783 compatible = "qcom,sm6115-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; 784 reg = <0x0 0x04804000 0x0 0x3000>, <0x0 0x04810000 0x0 0x8000>; 785 reg-names = "std", "ice"; 786 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 787 phys = <&ufs_mem_phy_lanes>; 788 phy-names = "ufsphy"; 789 lanes-per-direction = <1>; 790 #reset-cells = <1>; 791 resets = <&gcc GCC_UFS_PHY_BCR>; 792 reset-names = "rst"; 793 794 power-domains = <&gcc GCC_UFS_PHY_GDSC>; 795 iommus = <&apps_smmu 0x100 0>; 796 797 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 798 <&gcc GCC_SYS_NOC_UFS_PHY_AXI_CLK>, 799 <&gcc GCC_UFS_PHY_AHB_CLK>, 800 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 801 <&rpmcc RPM_SMD_XO_CLK_SRC>, 802 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 803 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 804 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 805 clock-names = "core_clk", 806 "bus_aggr_clk", 807 "iface_clk", 808 "core_clk_unipro", 809 "ref_clk", 810 "tx_lane0_sync_clk", 811 "rx_lane0_sync_clk", 812 "ice_core_clk"; 813 814 freq-table-hz = <50000000 200000000>, 815 <0 0>, 816 <0 0>, 817 <37500000 150000000>, 818 <0 0>, 819 <0 0>, 820 <0 0>, 821 <75000000 300000000>; 822 823 status = "disabled"; 824 }; 825 826 ufs_mem_phy: phy@4807000 { 827 compatible = "qcom,sm6115-qmp-ufs-phy"; 828 reg = <0x0 0x04807000 0x0 0x1c4>; 829 #address-cells = <2>; 830 #size-cells = <2>; 831 ranges; 832 833 clocks = <&gcc GCC_UFS_CLKREF_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 834 clock-names = "ref", "ref_aux"; 835 836 resets = <&ufs_mem_hc 0>; 837 reset-names = "ufsphy"; 838 status = "disabled"; 839 840 ufs_mem_phy_lanes: phy@4807400 { 841 reg = <0x0 0x04807400 0x0 0x098>, 842 <0x0 0x04807600 0x0 0x130>, 843 <0x0 0x04807c00 0x0 0x16c>; 844 #phy-cells = <0>; 845 }; 846 }; 847 848 gpi_dma0: dma-controller@4a00000 { 849 compatible = "qcom,sm6115-gpi-dma", "qcom,sm6350-gpi-dma"; 850 reg = <0x0 0x04a00000 0x0 0x60000>; 851 interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 852 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 853 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 854 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 855 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 856 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 857 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 858 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 859 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 860 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; 861 dma-channels = <10>; 862 dma-channel-mask = <0xf>; 863 iommus = <&apps_smmu 0xf6 0x0>; 864 #dma-cells = <3>; 865 status = "disabled"; 866 }; 867 868 qupv3_id_0: geniqup@4ac0000 { 869 compatible = "qcom,geni-se-qup"; 870 reg = <0x0 0x04ac0000 0x0 0x2000>; 871 clock-names = "m-ahb", "s-ahb"; 872 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 873 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 874 #address-cells = <2>; 875 #size-cells = <2>; 876 iommus = <&apps_smmu 0xe3 0x0>; 877 ranges; 878 status = "disabled"; 879 880 i2c0: i2c@4a80000 { 881 compatible = "qcom,geni-i2c"; 882 reg = <0x0 0x04a80000 0x0 0x4000>; 883 clock-names = "se"; 884 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 885 pinctrl-names = "default"; 886 pinctrl-0 = <&qup_i2c0_default>; 887 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 888 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 889 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 890 dma-names = "tx", "rx"; 891 #address-cells = <1>; 892 #size-cells = <0>; 893 status = "disabled"; 894 }; 895 896 spi0: spi@4a80000 { 897 compatible = "qcom,geni-spi"; 898 reg = <0x0 0x04a80000 0x0 0x4000>; 899 clock-names = "se"; 900 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 901 pinctrl-names = "default"; 902 pinctrl-0 = <&qup_spi0_default>; 903 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 904 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 905 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 906 dma-names = "tx", "rx"; 907 #address-cells = <1>; 908 #size-cells = <0>; 909 status = "disabled"; 910 }; 911 912 i2c1: i2c@4a84000 { 913 compatible = "qcom,geni-i2c"; 914 reg = <0x0 0x04a84000 0x0 0x4000>; 915 clock-names = "se"; 916 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 917 pinctrl-names = "default"; 918 pinctrl-0 = <&qup_i2c1_default>; 919 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 920 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 921 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 922 dma-names = "tx", "rx"; 923 #address-cells = <1>; 924 #size-cells = <0>; 925 status = "disabled"; 926 }; 927 928 spi1: spi@4a84000 { 929 compatible = "qcom,geni-spi"; 930 reg = <0x0 0x04a84000 0x0 0x4000>; 931 clock-names = "se"; 932 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 933 pinctrl-names = "default"; 934 pinctrl-0 = <&qup_spi1_default>; 935 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 936 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 937 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 938 dma-names = "tx", "rx"; 939 #address-cells = <1>; 940 #size-cells = <0>; 941 status = "disabled"; 942 }; 943 944 i2c2: i2c@4a88000 { 945 compatible = "qcom,geni-i2c"; 946 reg = <0x0 0x04a88000 0x0 0x4000>; 947 clock-names = "se"; 948 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 949 pinctrl-names = "default"; 950 pinctrl-0 = <&qup_i2c2_default>; 951 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; 952 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 953 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 954 dma-names = "tx", "rx"; 955 #address-cells = <1>; 956 #size-cells = <0>; 957 status = "disabled"; 958 }; 959 960 spi2: spi@4a88000 { 961 compatible = "qcom,geni-spi"; 962 reg = <0x0 0x04a88000 0x0 0x4000>; 963 clock-names = "se"; 964 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 965 pinctrl-names = "default"; 966 pinctrl-0 = <&qup_spi2_default>; 967 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; 968 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 969 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 970 dma-names = "tx", "rx"; 971 #address-cells = <1>; 972 #size-cells = <0>; 973 status = "disabled"; 974 }; 975 976 i2c3: i2c@4a8c000 { 977 compatible = "qcom,geni-i2c"; 978 reg = <0x0 0x04a8c000 0x0 0x4000>; 979 clock-names = "se"; 980 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 981 pinctrl-names = "default"; 982 pinctrl-0 = <&qup_i2c3_default>; 983 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 984 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 985 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 986 dma-names = "tx", "rx"; 987 #address-cells = <1>; 988 #size-cells = <0>; 989 status = "disabled"; 990 }; 991 992 spi3: spi@4a8c000 { 993 compatible = "qcom,geni-spi"; 994 reg = <0x0 0x04a8c000 0x0 0x4000>; 995 clock-names = "se"; 996 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 997 pinctrl-names = "default"; 998 pinctrl-0 = <&qup_spi3_default>; 999 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 1000 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1001 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1002 dma-names = "tx", "rx"; 1003 #address-cells = <1>; 1004 #size-cells = <0>; 1005 status = "disabled"; 1006 }; 1007 1008 i2c4: i2c@4a90000 { 1009 compatible = "qcom,geni-i2c"; 1010 reg = <0x0 0x04a90000 0x0 0x4000>; 1011 clock-names = "se"; 1012 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1013 pinctrl-names = "default"; 1014 pinctrl-0 = <&qup_i2c4_default>; 1015 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 1016 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1017 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1018 dma-names = "tx", "rx"; 1019 #address-cells = <1>; 1020 #size-cells = <0>; 1021 status = "disabled"; 1022 }; 1023 1024 spi4: spi@4a90000 { 1025 compatible = "qcom,geni-spi"; 1026 reg = <0x0 0x04a90000 0x0 0x4000>; 1027 clock-names = "se"; 1028 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1029 pinctrl-names = "default"; 1030 pinctrl-0 = <&qup_spi4_default>; 1031 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 1032 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1033 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1034 dma-names = "tx", "rx"; 1035 #address-cells = <1>; 1036 #size-cells = <0>; 1037 status = "disabled"; 1038 }; 1039 1040 uart4: serial@4a90000 { 1041 compatible = "qcom,geni-debug-uart"; 1042 reg = <0x0 0x04a90000 0x0 0x4000>; 1043 clock-names = "se"; 1044 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1045 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 1046 status = "disabled"; 1047 }; 1048 1049 i2c5: i2c@4a94000 { 1050 compatible = "qcom,geni-i2c"; 1051 reg = <0x0 0x04a94000 0x0 0x4000>; 1052 clock-names = "se"; 1053 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1054 pinctrl-names = "default"; 1055 pinctrl-0 = <&qup_i2c5_default>; 1056 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; 1057 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1058 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1059 dma-names = "tx", "rx"; 1060 #address-cells = <1>; 1061 #size-cells = <0>; 1062 status = "disabled"; 1063 }; 1064 1065 spi5: spi@4a94000 { 1066 compatible = "qcom,geni-spi"; 1067 reg = <0x0 0x04a94000 0x0 0x4000>; 1068 clock-names = "se"; 1069 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1070 pinctrl-names = "default"; 1071 pinctrl-0 = <&qup_spi5_default>; 1072 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; 1073 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1074 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1075 dma-names = "tx", "rx"; 1076 #address-cells = <1>; 1077 #size-cells = <0>; 1078 status = "disabled"; 1079 }; 1080 }; 1081 1082 usb: usb@4ef8800 { 1083 compatible = "qcom,sm6115-dwc3", "qcom,dwc3"; 1084 reg = <0x0 0x04ef8800 0x0 0x400>; 1085 #address-cells = <2>; 1086 #size-cells = <2>; 1087 ranges; 1088 1089 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 1090 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 1091 <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>, 1092 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 1093 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1094 <&gcc GCC_USB3_PRIM_CLKREF_CLK>; 1095 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", "xo"; 1096 1097 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1098 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 1099 assigned-clock-rates = <19200000>, <66666667>; 1100 1101 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 1102 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>; 1103 interrupt-names = "hs_phy_irq", "ss_phy_irq"; 1104 1105 resets = <&gcc GCC_USB30_PRIM_BCR>; 1106 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 1107 qcom,select-utmi-as-pipe-clk; 1108 status = "disabled"; 1109 1110 usb_dwc3: usb@4e00000 { 1111 compatible = "snps,dwc3"; 1112 reg = <0x0 0x04e00000 0x0 0xcd00>; 1113 interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 1114 phys = <&usb_hsphy>; 1115 phy-names = "usb2-phy"; 1116 iommus = <&apps_smmu 0x120 0x0>; 1117 snps,dis_u2_susphy_quirk; 1118 snps,dis_enblslpm_quirk; 1119 snps,has-lpm-erratum; 1120 snps,hird-threshold = /bits/ 8 <0x10>; 1121 snps,usb3_lpm_capable; 1122 }; 1123 }; 1124 1125 gpucc: clock-controller@5990000 { 1126 compatible = "qcom,sm6115-gpucc"; 1127 reg = <0x0 0x05990000 0x0 0x9000>; 1128 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 1129 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 1130 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 1131 #clock-cells = <1>; 1132 #reset-cells = <1>; 1133 #power-domain-cells = <1>; 1134 }; 1135 1136 adreno_smmu: iommu@59a0000 { 1137 compatible = "qcom,sm6115-smmu-500", "qcom,adreno-smmu", 1138 "qcom,smmu-500", "arm,mmu-500"; 1139 reg = <0x0 0x059a0000 0x0 0x10000>; 1140 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 1141 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 1142 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 1143 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 1144 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1145 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 1146 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, 1147 <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, 1148 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1149 1150 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1151 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 1152 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 1153 clock-names = "mem", 1154 "hlos", 1155 "iface"; 1156 power-domains = <&gpucc GPU_CX_GDSC>; 1157 1158 #global-interrupts = <1>; 1159 #iommu-cells = <2>; 1160 }; 1161 1162 mdss: display-subsystem@5e00000 { 1163 compatible = "qcom,sm6115-mdss"; 1164 reg = <0x0 0x05e00000 0x0 0x1000>; 1165 reg-names = "mdss"; 1166 1167 power-domains = <&dispcc MDSS_GDSC>; 1168 1169 clocks = <&gcc GCC_DISP_AHB_CLK>, 1170 <&gcc GCC_DISP_HF_AXI_CLK>, 1171 <&dispcc DISP_CC_MDSS_MDP_CLK>; 1172 1173 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 1174 interrupt-controller; 1175 #interrupt-cells = <1>; 1176 1177 iommus = <&apps_smmu 0x420 0x2>, 1178 <&apps_smmu 0x421 0x0>; 1179 1180 #address-cells = <2>; 1181 #size-cells = <2>; 1182 ranges; 1183 1184 status = "disabled"; 1185 1186 mdp: display-controller@5e01000 { 1187 compatible = "qcom,sm6115-dpu"; 1188 reg = <0x0 0x05e01000 0x0 0x8f000>, 1189 <0x0 0x05eb0000 0x0 0x2008>; 1190 reg-names = "mdp", "vbif"; 1191 1192 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 1193 <&dispcc DISP_CC_MDSS_AHB_CLK>, 1194 <&dispcc DISP_CC_MDSS_MDP_CLK>, 1195 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 1196 <&dispcc DISP_CC_MDSS_ROT_CLK>, 1197 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 1198 clock-names = "bus", 1199 "iface", 1200 "core", 1201 "lut", 1202 "rot", 1203 "vsync"; 1204 1205 operating-points-v2 = <&mdp_opp_table>; 1206 power-domains = <&rpmpd SM6115_VDDCX>; 1207 1208 interrupt-parent = <&mdss>; 1209 interrupts = <0>; 1210 1211 ports { 1212 #address-cells = <1>; 1213 #size-cells = <0>; 1214 1215 port@0 { 1216 reg = <0>; 1217 dpu_intf1_out: endpoint { 1218 remote-endpoint = <&mdss_dsi0_in>; 1219 }; 1220 }; 1221 }; 1222 1223 mdp_opp_table: opp-table { 1224 compatible = "operating-points-v2"; 1225 1226 opp-19200000 { 1227 opp-hz = /bits/ 64 <19200000>; 1228 required-opps = <&rpmpd_opp_min_svs>; 1229 }; 1230 1231 opp-192000000 { 1232 opp-hz = /bits/ 64 <192000000>; 1233 required-opps = <&rpmpd_opp_low_svs>; 1234 }; 1235 1236 opp-256000000 { 1237 opp-hz = /bits/ 64 <256000000>; 1238 required-opps = <&rpmpd_opp_svs>; 1239 }; 1240 1241 opp-307200000 { 1242 opp-hz = /bits/ 64 <307200000>; 1243 required-opps = <&rpmpd_opp_svs_plus>; 1244 }; 1245 1246 opp-384000000 { 1247 opp-hz = /bits/ 64 <384000000>; 1248 required-opps = <&rpmpd_opp_nom>; 1249 }; 1250 }; 1251 }; 1252 1253 mdss_dsi0: dsi@5e94000 { 1254 compatible = "qcom,sm6115-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 1255 reg = <0x0 0x05e94000 0x0 0x400>; 1256 reg-names = "dsi_ctrl"; 1257 1258 interrupt-parent = <&mdss>; 1259 interrupts = <4>; 1260 1261 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 1262 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 1263 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 1264 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 1265 <&dispcc DISP_CC_MDSS_AHB_CLK>, 1266 <&gcc GCC_DISP_HF_AXI_CLK>; 1267 clock-names = "byte", 1268 "byte_intf", 1269 "pixel", 1270 "core", 1271 "iface", 1272 "bus"; 1273 1274 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 1275 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 1276 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; 1277 1278 operating-points-v2 = <&dsi_opp_table>; 1279 power-domains = <&rpmpd SM6115_VDDCX>; 1280 phys = <&mdss_dsi0_phy>; 1281 1282 #address-cells = <1>; 1283 #size-cells = <0>; 1284 1285 status = "disabled"; 1286 1287 ports { 1288 #address-cells = <1>; 1289 #size-cells = <0>; 1290 1291 port@0 { 1292 reg = <0>; 1293 mdss_dsi0_in: endpoint { 1294 remote-endpoint = <&dpu_intf1_out>; 1295 }; 1296 }; 1297 1298 port@1 { 1299 reg = <1>; 1300 mdss_dsi0_out: endpoint { 1301 }; 1302 }; 1303 }; 1304 1305 dsi_opp_table: opp-table { 1306 compatible = "operating-points-v2"; 1307 1308 opp-19200000 { 1309 opp-hz = /bits/ 64 <19200000>; 1310 required-opps = <&rpmpd_opp_min_svs>; 1311 }; 1312 1313 opp-164000000 { 1314 opp-hz = /bits/ 64 <164000000>; 1315 required-opps = <&rpmpd_opp_low_svs>; 1316 }; 1317 1318 opp-187500000 { 1319 opp-hz = /bits/ 64 <187500000>; 1320 required-opps = <&rpmpd_opp_svs>; 1321 }; 1322 }; 1323 }; 1324 1325 mdss_dsi0_phy: phy@5e94400 { 1326 compatible = "qcom,dsi-phy-14nm-2290"; 1327 reg = <0x0 0x05e94400 0x0 0x100>, 1328 <0x0 0x05e94500 0x0 0x300>, 1329 <0x0 0x05e94800 0x0 0x188>; 1330 reg-names = "dsi_phy", 1331 "dsi_phy_lane", 1332 "dsi_pll"; 1333 1334 #clock-cells = <1>; 1335 #phy-cells = <0>; 1336 1337 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 1338 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1339 clock-names = "iface", "ref"; 1340 1341 status = "disabled"; 1342 }; 1343 }; 1344 1345 dispcc: clock-controller@5f00000 { 1346 compatible = "qcom,sm6115-dispcc"; 1347 reg = <0x0 0x05f00000 0 0x20000>; 1348 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 1349 <&sleep_clk>, 1350 <&mdss_dsi0_phy 0>, 1351 <&mdss_dsi0_phy 1>, 1352 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>; 1353 #clock-cells = <1>; 1354 #reset-cells = <1>; 1355 #power-domain-cells = <1>; 1356 }; 1357 1358 remoteproc_mpss: remoteproc@6080000 { 1359 compatible = "qcom,sm6115-mpss-pas"; 1360 reg = <0x0 0x06080000 0x0 0x100>; 1361 1362 interrupts-extended = <&intc GIC_SPI 307 IRQ_TYPE_EDGE_RISING>, 1363 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1364 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1365 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1366 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 1367 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 1368 interrupt-names = "wdog", "fatal", "ready", "handover", 1369 "stop-ack", "shutdown-ack"; 1370 1371 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 1372 clock-names = "xo"; 1373 1374 power-domains = <&rpmpd SM6115_VDDCX>; 1375 1376 memory-region = <&pil_modem_mem>; 1377 1378 qcom,smem-states = <&modem_smp2p_out 0>; 1379 qcom,smem-state-names = "stop"; 1380 1381 status = "disabled"; 1382 1383 glink-edge { 1384 interrupts = <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>; 1385 label = "mpss"; 1386 qcom,remote-pid = <1>; 1387 mboxes = <&apcs_glb 12>; 1388 }; 1389 }; 1390 1391 stm@8002000 { 1392 compatible = "arm,coresight-stm", "arm,primecell"; 1393 reg = <0x0 0x08002000 0x0 0x1000>, 1394 <0x0 0x0e280000 0x0 0x180000>; 1395 reg-names = "stm-base", "stm-stimulus-base"; 1396 1397 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1398 clock-names = "apb_pclk"; 1399 1400 status = "disabled"; 1401 1402 out-ports { 1403 port { 1404 stm_out: endpoint { 1405 remote-endpoint = <&funnel_in0_in>; 1406 }; 1407 }; 1408 }; 1409 }; 1410 1411 cti0: cti@8010000 { 1412 compatible = "arm,coresight-cti", "arm,primecell"; 1413 reg = <0x0 0x08010000 0x0 0x1000>; 1414 1415 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1416 clock-names = "apb_pclk"; 1417 1418 status = "disabled"; 1419 }; 1420 1421 cti1: cti@8011000 { 1422 compatible = "arm,coresight-cti", "arm,primecell"; 1423 reg = <0x0 0x08011000 0x0 0x1000>; 1424 1425 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1426 clock-names = "apb_pclk"; 1427 1428 status = "disabled"; 1429 }; 1430 1431 cti2: cti@8012000 { 1432 compatible = "arm,coresight-cti", "arm,primecell"; 1433 reg = <0x0 0x08012000 0x0 0x1000>; 1434 1435 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1436 clock-names = "apb_pclk"; 1437 1438 status = "disabled"; 1439 }; 1440 1441 cti3: cti@8013000 { 1442 compatible = "arm,coresight-cti", "arm,primecell"; 1443 reg = <0x0 0x08013000 0x0 0x1000>; 1444 1445 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1446 clock-names = "apb_pclk"; 1447 1448 status = "disabled"; 1449 }; 1450 1451 cti4: cti@8014000 { 1452 compatible = "arm,coresight-cti", "arm,primecell"; 1453 reg = <0x0 0x08014000 0x0 0x1000>; 1454 1455 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1456 clock-names = "apb_pclk"; 1457 1458 status = "disabled"; 1459 }; 1460 1461 cti5: cti@8015000 { 1462 compatible = "arm,coresight-cti", "arm,primecell"; 1463 reg = <0x0 0x08015000 0x0 0x1000>; 1464 1465 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1466 clock-names = "apb_pclk"; 1467 1468 status = "disabled"; 1469 }; 1470 1471 cti6: cti@8016000 { 1472 compatible = "arm,coresight-cti", "arm,primecell"; 1473 reg = <0x0 0x08016000 0x0 0x1000>; 1474 1475 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1476 clock-names = "apb_pclk"; 1477 1478 status = "disabled"; 1479 }; 1480 1481 cti7: cti@8017000 { 1482 compatible = "arm,coresight-cti", "arm,primecell"; 1483 reg = <0x0 0x08017000 0x0 0x1000>; 1484 1485 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1486 clock-names = "apb_pclk"; 1487 1488 status = "disabled"; 1489 }; 1490 1491 cti8: cti@8018000 { 1492 compatible = "arm,coresight-cti", "arm,primecell"; 1493 reg = <0x0 0x08018000 0x0 0x1000>; 1494 1495 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1496 clock-names = "apb_pclk"; 1497 1498 status = "disabled"; 1499 }; 1500 1501 cti9: cti@8019000 { 1502 compatible = "arm,coresight-cti", "arm,primecell"; 1503 reg = <0x0 0x08019000 0x0 0x1000>; 1504 1505 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1506 clock-names = "apb_pclk"; 1507 1508 status = "disabled"; 1509 }; 1510 1511 cti10: cti@801a000 { 1512 compatible = "arm,coresight-cti", "arm,primecell"; 1513 reg = <0x0 0x0801a000 0x0 0x1000>; 1514 1515 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1516 clock-names = "apb_pclk"; 1517 1518 status = "disabled"; 1519 }; 1520 1521 cti11: cti@801b000 { 1522 compatible = "arm,coresight-cti", "arm,primecell"; 1523 reg = <0x0 0x0801b000 0x0 0x1000>; 1524 1525 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1526 clock-names = "apb_pclk"; 1527 1528 status = "disabled"; 1529 }; 1530 1531 cti12: cti@801c000 { 1532 compatible = "arm,coresight-cti", "arm,primecell"; 1533 reg = <0x0 0x0801c000 0x0 0x1000>; 1534 1535 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1536 clock-names = "apb_pclk"; 1537 1538 status = "disabled"; 1539 }; 1540 1541 cti13: cti@801d000 { 1542 compatible = "arm,coresight-cti", "arm,primecell"; 1543 reg = <0x0 0x0801d000 0x0 0x1000>; 1544 1545 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1546 clock-names = "apb_pclk"; 1547 1548 status = "disabled"; 1549 }; 1550 1551 cti14: cti@801e000 { 1552 compatible = "arm,coresight-cti", "arm,primecell"; 1553 reg = <0x0 0x0801e000 0x0 0x1000>; 1554 1555 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1556 clock-names = "apb_pclk"; 1557 1558 status = "disabled"; 1559 }; 1560 1561 cti15: cti@801f000 { 1562 compatible = "arm,coresight-cti", "arm,primecell"; 1563 reg = <0x0 0x0801f000 0x0 0x1000>; 1564 1565 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1566 clock-names = "apb_pclk"; 1567 1568 status = "disabled"; 1569 }; 1570 1571 replicator@8046000 { 1572 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 1573 reg = <0x0 0x08046000 0x0 0x1000>; 1574 1575 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1576 clock-names = "apb_pclk"; 1577 1578 status = "disabled"; 1579 1580 out-ports { 1581 port { 1582 replicator_out: endpoint { 1583 remote-endpoint = <&etr_in>; 1584 }; 1585 }; 1586 }; 1587 1588 in-ports { 1589 port { 1590 replicator_in: endpoint { 1591 remote-endpoint = <&etf_out>; 1592 }; 1593 }; 1594 }; 1595 }; 1596 1597 etf@8047000 { 1598 compatible = "arm,coresight-tmc", "arm,primecell"; 1599 reg = <0x0 0x08047000 0x0 0x1000>; 1600 1601 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1602 clock-names = "apb_pclk"; 1603 1604 status = "disabled"; 1605 1606 in-ports { 1607 port { 1608 etf_in: endpoint { 1609 remote-endpoint = <&merge_funnel_out>; 1610 }; 1611 }; 1612 }; 1613 1614 out-ports { 1615 port { 1616 etf_out: endpoint { 1617 remote-endpoint = <&replicator_in>; 1618 }; 1619 }; 1620 }; 1621 }; 1622 1623 etr@8048000 { 1624 compatible = "arm,coresight-tmc", "arm,primecell"; 1625 reg = <0x0 0x08048000 0x0 0x1000>; 1626 1627 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1628 clock-names = "apb_pclk"; 1629 1630 status = "disabled"; 1631 1632 in-ports { 1633 port { 1634 etr_in: endpoint { 1635 remote-endpoint = <&replicator_out>; 1636 }; 1637 }; 1638 }; 1639 }; 1640 1641 funnel@8041000 { 1642 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1643 reg = <0x0 0x08041000 0x0 0x1000>; 1644 1645 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1646 clock-names = "apb_pclk"; 1647 1648 status = "disabled"; 1649 1650 out-ports { 1651 port { 1652 funnel_in0_out: endpoint { 1653 remote-endpoint = <&merge_funnel_in0>; 1654 }; 1655 }; 1656 }; 1657 1658 in-ports { 1659 port { 1660 funnel_in0_in: endpoint { 1661 remote-endpoint = <&stm_out>; 1662 }; 1663 }; 1664 }; 1665 }; 1666 1667 funnel@8042000 { 1668 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1669 reg = <0x0 0x08042000 0x0 0x1000>; 1670 1671 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1672 clock-names = "apb_pclk"; 1673 1674 status = "disabled"; 1675 1676 out-ports { 1677 port { 1678 funnel_in1_out: endpoint { 1679 remote-endpoint = <&merge_funnel_in1>; 1680 }; 1681 }; 1682 }; 1683 1684 in-ports { 1685 port { 1686 funnel_in1_in: endpoint { 1687 remote-endpoint = <&funnel_apss1_out>; 1688 }; 1689 }; 1690 }; 1691 }; 1692 1693 funnel@8045000 { 1694 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1695 reg = <0x0 0x08045000 0x0 0x1000>; 1696 1697 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1698 clock-names = "apb_pclk"; 1699 1700 status = "disabled"; 1701 1702 out-ports { 1703 port { 1704 merge_funnel_out: endpoint { 1705 remote-endpoint = <&etf_in>; 1706 }; 1707 }; 1708 }; 1709 1710 in-ports { 1711 #address-cells = <1>; 1712 #size-cells = <0>; 1713 1714 port@0 { 1715 reg = <0>; 1716 merge_funnel_in0: endpoint { 1717 remote-endpoint = <&funnel_in0_out>; 1718 }; 1719 }; 1720 1721 port@1 { 1722 reg = <1>; 1723 merge_funnel_in1: endpoint { 1724 remote-endpoint = <&funnel_in1_out>; 1725 }; 1726 }; 1727 }; 1728 }; 1729 1730 etm@9040000 { 1731 compatible = "arm,coresight-etm4x", "arm,primecell"; 1732 reg = <0x0 0x09040000 0x0 0x1000>; 1733 1734 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1735 clock-names = "apb_pclk"; 1736 arm,coresight-loses-context-with-cpu; 1737 1738 cpu = <&CPU0>; 1739 1740 status = "disabled"; 1741 1742 out-ports { 1743 port { 1744 etm0_out: endpoint { 1745 remote-endpoint = <&funnel_apss0_in0>; 1746 }; 1747 }; 1748 }; 1749 }; 1750 1751 etm@9140000 { 1752 compatible = "arm,coresight-etm4x", "arm,primecell"; 1753 reg = <0x0 0x09140000 0x0 0x1000>; 1754 1755 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1756 clock-names = "apb_pclk"; 1757 arm,coresight-loses-context-with-cpu; 1758 1759 cpu = <&CPU1>; 1760 1761 status = "disabled"; 1762 1763 out-ports { 1764 port { 1765 etm1_out: endpoint { 1766 remote-endpoint = <&funnel_apss0_in1>; 1767 }; 1768 }; 1769 }; 1770 }; 1771 1772 etm@9240000 { 1773 compatible = "arm,coresight-etm4x", "arm,primecell"; 1774 reg = <0x0 0x09240000 0x0 0x1000>; 1775 1776 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1777 clock-names = "apb_pclk"; 1778 arm,coresight-loses-context-with-cpu; 1779 1780 cpu = <&CPU2>; 1781 1782 status = "disabled"; 1783 1784 out-ports { 1785 port { 1786 etm2_out: endpoint { 1787 remote-endpoint = <&funnel_apss0_in2>; 1788 }; 1789 }; 1790 }; 1791 }; 1792 1793 etm@9340000 { 1794 compatible = "arm,coresight-etm4x", "arm,primecell"; 1795 reg = <0x0 0x09340000 0x0 0x1000>; 1796 1797 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1798 clock-names = "apb_pclk"; 1799 arm,coresight-loses-context-with-cpu; 1800 1801 cpu = <&CPU3>; 1802 1803 status = "disabled"; 1804 1805 out-ports { 1806 port { 1807 etm3_out: endpoint { 1808 remote-endpoint = <&funnel_apss0_in3>; 1809 }; 1810 }; 1811 }; 1812 }; 1813 1814 etm@9440000 { 1815 compatible = "arm,coresight-etm4x", "arm,primecell"; 1816 reg = <0x0 0x09440000 0x0 0x1000>; 1817 1818 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1819 clock-names = "apb_pclk"; 1820 arm,coresight-loses-context-with-cpu; 1821 1822 cpu = <&CPU4>; 1823 1824 status = "disabled"; 1825 1826 out-ports { 1827 port { 1828 etm4_out: endpoint { 1829 remote-endpoint = <&funnel_apss0_in4>; 1830 }; 1831 }; 1832 }; 1833 }; 1834 1835 etm@9540000 { 1836 compatible = "arm,coresight-etm4x", "arm,primecell"; 1837 reg = <0x0 0x09540000 0x0 0x1000>; 1838 1839 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1840 clock-names = "apb_pclk"; 1841 arm,coresight-loses-context-with-cpu; 1842 1843 cpu = <&CPU5>; 1844 1845 status = "disabled"; 1846 1847 out-ports { 1848 port { 1849 etm5_out: endpoint { 1850 remote-endpoint = <&funnel_apss0_in5>; 1851 }; 1852 }; 1853 }; 1854 }; 1855 1856 etm@9640000 { 1857 compatible = "arm,coresight-etm4x", "arm,primecell"; 1858 reg = <0x0 0x09640000 0x0 0x1000>; 1859 1860 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1861 clock-names = "apb_pclk"; 1862 arm,coresight-loses-context-with-cpu; 1863 1864 cpu = <&CPU6>; 1865 1866 status = "disabled"; 1867 1868 out-ports { 1869 port { 1870 etm6_out: endpoint { 1871 remote-endpoint = <&funnel_apss0_in6>; 1872 }; 1873 }; 1874 }; 1875 }; 1876 1877 etm@9740000 { 1878 compatible = "arm,coresight-etm4x", "arm,primecell"; 1879 reg = <0x0 0x09740000 0x0 0x1000>; 1880 1881 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1882 clock-names = "apb_pclk"; 1883 arm,coresight-loses-context-with-cpu; 1884 1885 cpu = <&CPU7>; 1886 1887 status = "disabled"; 1888 1889 out-ports { 1890 port { 1891 etm7_out: endpoint { 1892 remote-endpoint = <&funnel_apss0_in7>; 1893 }; 1894 }; 1895 }; 1896 }; 1897 1898 funnel@9800000 { 1899 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1900 reg = <0x0 0x09800000 0x0 0x1000>; 1901 1902 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1903 clock-names = "apb_pclk"; 1904 1905 status = "disabled"; 1906 1907 out-ports { 1908 port { 1909 funnel_apss0_out: endpoint { 1910 remote-endpoint = <&funnel_apss1_in>; 1911 }; 1912 }; 1913 }; 1914 1915 in-ports { 1916 #address-cells = <1>; 1917 #size-cells = <0>; 1918 1919 port@0 { 1920 reg = <0>; 1921 funnel_apss0_in0: endpoint { 1922 remote-endpoint = <&etm0_out>; 1923 }; 1924 }; 1925 1926 port@1 { 1927 reg = <1>; 1928 funnel_apss0_in1: endpoint { 1929 remote-endpoint = <&etm1_out>; 1930 }; 1931 }; 1932 1933 port@2 { 1934 reg = <2>; 1935 funnel_apss0_in2: endpoint { 1936 remote-endpoint = <&etm2_out>; 1937 }; 1938 }; 1939 1940 port@3 { 1941 reg = <3>; 1942 funnel_apss0_in3: endpoint { 1943 remote-endpoint = <&etm3_out>; 1944 }; 1945 }; 1946 1947 port@4 { 1948 reg = <4>; 1949 funnel_apss0_in4: endpoint { 1950 remote-endpoint = <&etm4_out>; 1951 }; 1952 }; 1953 1954 port@5 { 1955 reg = <5>; 1956 funnel_apss0_in5: endpoint { 1957 remote-endpoint = <&etm5_out>; 1958 }; 1959 }; 1960 1961 port@6 { 1962 reg = <6>; 1963 funnel_apss0_in6: endpoint { 1964 remote-endpoint = <&etm6_out>; 1965 }; 1966 }; 1967 1968 port@7 { 1969 reg = <7>; 1970 funnel_apss0_in7: endpoint { 1971 remote-endpoint = <&etm7_out>; 1972 }; 1973 }; 1974 }; 1975 }; 1976 1977 funnel@9810000 { 1978 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1979 reg = <0x0 0x09810000 0x0 0x1000>; 1980 1981 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1982 clock-names = "apb_pclk"; 1983 1984 status = "disabled"; 1985 1986 out-ports { 1987 port { 1988 funnel_apss1_out: endpoint { 1989 remote-endpoint = <&funnel_in1_in>; 1990 }; 1991 }; 1992 }; 1993 1994 in-ports { 1995 port { 1996 funnel_apss1_in: endpoint { 1997 remote-endpoint = <&funnel_apss0_out>; 1998 }; 1999 }; 2000 }; 2001 }; 2002 2003 remoteproc_adsp: remoteproc@ab00000 { 2004 compatible = "qcom,sm6115-adsp-pas"; 2005 reg = <0x0 0x0ab00000 0x0 0x100>; 2006 2007 interrupts-extended = <&intc GIC_SPI 282 IRQ_TYPE_EDGE_RISING>, 2008 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2009 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2010 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2011 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2012 interrupt-names = "wdog", "fatal", "ready", 2013 "handover", "stop-ack"; 2014 2015 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 2016 clock-names = "xo"; 2017 2018 power-domains = <&rpmpd SM6115_VDD_LPI_CX>, 2019 <&rpmpd SM6115_VDD_LPI_MX>; 2020 2021 memory-region = <&pil_adsp_mem>; 2022 2023 qcom,smem-states = <&adsp_smp2p_out 0>; 2024 qcom,smem-state-names = "stop"; 2025 2026 status = "disabled"; 2027 2028 glink-edge { 2029 interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>; 2030 label = "lpass"; 2031 qcom,remote-pid = <2>; 2032 mboxes = <&apcs_glb 8>; 2033 2034 fastrpc { 2035 compatible = "qcom,fastrpc"; 2036 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2037 label = "adsp"; 2038 qcom,non-secure-domain; 2039 #address-cells = <1>; 2040 #size-cells = <0>; 2041 2042 compute-cb@3 { 2043 compatible = "qcom,fastrpc-compute-cb"; 2044 reg = <3>; 2045 iommus = <&apps_smmu 0x01c3 0x0>; 2046 }; 2047 2048 compute-cb@4 { 2049 compatible = "qcom,fastrpc-compute-cb"; 2050 reg = <4>; 2051 iommus = <&apps_smmu 0x01c4 0x0>; 2052 }; 2053 2054 compute-cb@5 { 2055 compatible = "qcom,fastrpc-compute-cb"; 2056 reg = <5>; 2057 iommus = <&apps_smmu 0x01c5 0x0>; 2058 }; 2059 2060 compute-cb@6 { 2061 compatible = "qcom,fastrpc-compute-cb"; 2062 reg = <6>; 2063 iommus = <&apps_smmu 0x01c6 0x0>; 2064 }; 2065 2066 compute-cb@7 { 2067 compatible = "qcom,fastrpc-compute-cb"; 2068 reg = <7>; 2069 iommus = <&apps_smmu 0x01c7 0x0>; 2070 }; 2071 }; 2072 }; 2073 }; 2074 2075 remoteproc_cdsp: remoteproc@b300000 { 2076 compatible = "qcom,sm6115-cdsp-pas"; 2077 reg = <0x0 0x0b300000 0x0 0x100000>; 2078 2079 interrupts-extended = <&intc GIC_SPI 265 IRQ_TYPE_EDGE_RISING>, 2080 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2081 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2082 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2083 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2084 interrupt-names = "wdog", "fatal", "ready", 2085 "handover", "stop-ack"; 2086 2087 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 2088 clock-names = "xo"; 2089 2090 power-domains = <&rpmpd SM6115_VDDCX>; 2091 2092 memory-region = <&pil_cdsp_mem>; 2093 2094 qcom,smem-states = <&cdsp_smp2p_out 0>; 2095 qcom,smem-state-names = "stop"; 2096 2097 status = "disabled"; 2098 2099 glink-edge { 2100 interrupts = <GIC_SPI 261 IRQ_TYPE_EDGE_RISING>; 2101 label = "cdsp"; 2102 qcom,remote-pid = <5>; 2103 mboxes = <&apcs_glb 28>; 2104 2105 fastrpc { 2106 compatible = "qcom,fastrpc"; 2107 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2108 label = "cdsp"; 2109 qcom,non-secure-domain; 2110 #address-cells = <1>; 2111 #size-cells = <0>; 2112 2113 compute-cb@1 { 2114 compatible = "qcom,fastrpc-compute-cb"; 2115 reg = <1>; 2116 iommus = <&apps_smmu 0x0c01 0x0>; 2117 }; 2118 2119 compute-cb@2 { 2120 compatible = "qcom,fastrpc-compute-cb"; 2121 reg = <2>; 2122 iommus = <&apps_smmu 0x0c02 0x0>; 2123 }; 2124 2125 compute-cb@3 { 2126 compatible = "qcom,fastrpc-compute-cb"; 2127 reg = <3>; 2128 iommus = <&apps_smmu 0x0c03 0x0>; 2129 }; 2130 2131 compute-cb@4 { 2132 compatible = "qcom,fastrpc-compute-cb"; 2133 reg = <4>; 2134 iommus = <&apps_smmu 0x0c04 0x0>; 2135 }; 2136 2137 compute-cb@5 { 2138 compatible = "qcom,fastrpc-compute-cb"; 2139 reg = <5>; 2140 iommus = <&apps_smmu 0x0c05 0x0>; 2141 }; 2142 2143 compute-cb@6 { 2144 compatible = "qcom,fastrpc-compute-cb"; 2145 reg = <6>; 2146 iommus = <&apps_smmu 0x0c06 0x0>; 2147 }; 2148 2149 /* note: secure cb9 in downstream */ 2150 }; 2151 }; 2152 }; 2153 2154 apps_smmu: iommu@c600000 { 2155 compatible = "qcom,sm6115-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 2156 reg = <0x0 0x0c600000 0x0 0x80000>; 2157 #iommu-cells = <2>; 2158 #global-interrupts = <1>; 2159 2160 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 2161 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 2162 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 2163 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 2164 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 2165 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 2166 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 2167 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 2168 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 2169 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 2170 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 2171 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 2172 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 2173 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 2174 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 2175 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 2176 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 2177 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 2178 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 2179 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 2180 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 2181 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 2182 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 2183 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 2184 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 2185 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 2186 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 2187 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 2188 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 2189 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 2190 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 2191 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 2192 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 2193 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 2194 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 2195 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 2196 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 2197 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 2198 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 2199 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 2200 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 2201 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 2202 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 2203 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 2204 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 2205 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 2206 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 2207 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 2208 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 2209 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 2210 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 2211 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 2212 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 2213 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 2214 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 2215 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 2216 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 2217 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 2218 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 2219 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 2220 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 2221 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 2222 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 2223 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 2224 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 2225 }; 2226 2227 wifi: wifi@c800000 { 2228 compatible = "qcom,wcn3990-wifi"; 2229 reg = <0x0 0x0c800000 0x0 0x800000>; 2230 reg-names = "membase"; 2231 memory-region = <&wlan_msa_mem>; 2232 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, 2233 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, 2234 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, 2235 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>, 2236 <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>, 2237 <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>, 2238 <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>, 2239 <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>, 2240 <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>, 2241 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>, 2242 <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, 2243 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 2244 iommus = <&apps_smmu 0x1a0 0x1>; 2245 qcom,msa-fixed-perm; 2246 status = "disabled"; 2247 }; 2248 2249 watchdog@f017000 { 2250 compatible = "qcom,apss-wdt-sm6115", "qcom,kpss-wdt"; 2251 reg = <0x0 0x0f017000 0x0 0x1000>; 2252 clocks = <&sleep_clk>; 2253 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 2254 }; 2255 2256 apcs_glb: mailbox@f111000 { 2257 compatible = "qcom,sm6115-apcs-hmss-global", 2258 "qcom,msm8994-apcs-kpss-global"; 2259 reg = <0x0 0x0f111000 0x0 0x1000>; 2260 2261 #mbox-cells = <1>; 2262 }; 2263 2264 timer@f120000 { 2265 compatible = "arm,armv7-timer-mem"; 2266 reg = <0x0 0x0f120000 0x0 0x1000>; 2267 #address-cells = <2>; 2268 #size-cells = <2>; 2269 ranges; 2270 clock-frequency = <19200000>; 2271 2272 frame@f121000 { 2273 reg = <0x0 0x0f121000 0x0 0x1000>, <0x0 0x0f122000 0x0 0x1000>; 2274 frame-number = <0>; 2275 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 2276 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 2277 }; 2278 2279 frame@f123000 { 2280 reg = <0x0 0x0f123000 0x0 0x1000>; 2281 frame-number = <1>; 2282 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 2283 status = "disabled"; 2284 }; 2285 2286 frame@f124000 { 2287 reg = <0x0 0x0f124000 0x0 0x1000>; 2288 frame-number = <2>; 2289 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 2290 status = "disabled"; 2291 }; 2292 2293 frame@f125000 { 2294 reg = <0x0 0x0f125000 0x0 0x1000>; 2295 frame-number = <3>; 2296 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 2297 status = "disabled"; 2298 }; 2299 2300 frame@f126000 { 2301 reg = <0x0 0x0f126000 0x0 0x1000>; 2302 frame-number = <4>; 2303 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 2304 status = "disabled"; 2305 }; 2306 2307 frame@f127000 { 2308 reg = <0x0 0x0f127000 0x0 0x1000>; 2309 frame-number = <5>; 2310 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 2311 status = "disabled"; 2312 }; 2313 2314 frame@f128000 { 2315 reg = <0x0 0x0f128000 0x0 0x1000>; 2316 frame-number = <6>; 2317 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 2318 status = "disabled"; 2319 }; 2320 }; 2321 2322 intc: interrupt-controller@f200000 { 2323 compatible = "arm,gic-v3"; 2324 reg = <0x0 0x0f200000 0x0 0x10000>, 2325 <0x0 0x0f300000 0x0 0x100000>; 2326 #interrupt-cells = <3>; 2327 interrupt-controller; 2328 interrupt-parent = <&intc>; 2329 #redistributor-regions = <1>; 2330 redistributor-stride = <0x0 0x20000>; 2331 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 2332 }; 2333 2334 cpufreq_hw: cpufreq@f521000 { 2335 compatible = "qcom,sm6115-cpufreq-hw", "qcom,cpufreq-hw"; 2336 reg = <0x0 0x0f521000 0x0 0x1000>, 2337 <0x0 0x0f523000 0x0 0x1000>; 2338 2339 reg-names = "freq-domain0", "freq-domain1"; 2340 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>; 2341 clock-names = "xo", "alternate"; 2342 2343 #freq-domain-cells = <1>; 2344 #clock-cells = <1>; 2345 }; 2346 }; 2347 2348 thermal-zones { 2349 mapss-thermal { 2350 polling-delay-passive = <0>; 2351 polling-delay = <0>; 2352 thermal-sensors = <&tsens0 0>; 2353 2354 trips { 2355 trip-point0 { 2356 temperature = <115000>; 2357 hysteresis = <5000>; 2358 type = "passive"; 2359 }; 2360 2361 trip-point1 { 2362 temperature = <125000>; 2363 hysteresis = <1000>; 2364 type = "passive"; 2365 }; 2366 }; 2367 }; 2368 2369 cdsp-hvx-thermal { 2370 polling-delay-passive = <0>; 2371 polling-delay = <0>; 2372 thermal-sensors = <&tsens0 1>; 2373 2374 trips { 2375 trip-point0 { 2376 temperature = <115000>; 2377 hysteresis = <5000>; 2378 type = "passive"; 2379 }; 2380 2381 trip-point1 { 2382 temperature = <125000>; 2383 hysteresis = <1000>; 2384 type = "passive"; 2385 }; 2386 }; 2387 }; 2388 2389 wlan-thermal { 2390 polling-delay-passive = <0>; 2391 polling-delay = <0>; 2392 thermal-sensors = <&tsens0 2>; 2393 2394 trips { 2395 trip-point0 { 2396 temperature = <115000>; 2397 hysteresis = <5000>; 2398 type = "passive"; 2399 }; 2400 2401 trip-point1 { 2402 temperature = <125000>; 2403 hysteresis = <1000>; 2404 type = "passive"; 2405 }; 2406 }; 2407 }; 2408 2409 camera-thermal { 2410 polling-delay-passive = <0>; 2411 polling-delay = <0>; 2412 thermal-sensors = <&tsens0 3>; 2413 2414 trips { 2415 trip-point0 { 2416 temperature = <115000>; 2417 hysteresis = <5000>; 2418 type = "passive"; 2419 }; 2420 2421 trip-point1 { 2422 temperature = <125000>; 2423 hysteresis = <1000>; 2424 type = "passive"; 2425 }; 2426 }; 2427 }; 2428 2429 video-thermal { 2430 polling-delay-passive = <0>; 2431 polling-delay = <0>; 2432 thermal-sensors = <&tsens0 4>; 2433 2434 trips { 2435 trip-point0 { 2436 temperature = <115000>; 2437 hysteresis = <5000>; 2438 type = "passive"; 2439 }; 2440 2441 trip-point1 { 2442 temperature = <125000>; 2443 hysteresis = <1000>; 2444 type = "passive"; 2445 }; 2446 }; 2447 }; 2448 2449 modem1-thermal { 2450 polling-delay-passive = <0>; 2451 polling-delay = <0>; 2452 thermal-sensors = <&tsens0 5>; 2453 2454 trips { 2455 trip-point0 { 2456 temperature = <115000>; 2457 hysteresis = <5000>; 2458 type = "passive"; 2459 }; 2460 2461 trip-point1 { 2462 temperature = <125000>; 2463 hysteresis = <1000>; 2464 type = "passive"; 2465 }; 2466 }; 2467 }; 2468 2469 cpu4-thermal { 2470 polling-delay-passive = <0>; 2471 polling-delay = <0>; 2472 thermal-sensors = <&tsens0 6>; 2473 2474 trips { 2475 cpu4_alert0: trip-point0 { 2476 temperature = <90000>; 2477 hysteresis = <2000>; 2478 type = "passive"; 2479 }; 2480 2481 cpu4_alert1: trip-point1 { 2482 temperature = <95000>; 2483 hysteresis = <2000>; 2484 type = "passive"; 2485 }; 2486 2487 cpu4_crit: cpu_crit { 2488 temperature = <110000>; 2489 hysteresis = <1000>; 2490 type = "critical"; 2491 }; 2492 }; 2493 }; 2494 2495 cpu5-thermal { 2496 polling-delay-passive = <0>; 2497 polling-delay = <0>; 2498 thermal-sensors = <&tsens0 7>; 2499 2500 trips { 2501 cpu5_alert0: trip-point0 { 2502 temperature = <90000>; 2503 hysteresis = <2000>; 2504 type = "passive"; 2505 }; 2506 2507 cpu5_alert1: trip-point1 { 2508 temperature = <95000>; 2509 hysteresis = <2000>; 2510 type = "passive"; 2511 }; 2512 2513 cpu5_crit: cpu_crit { 2514 temperature = <110000>; 2515 hysteresis = <1000>; 2516 type = "critical"; 2517 }; 2518 }; 2519 }; 2520 2521 cpu6-thermal { 2522 polling-delay-passive = <0>; 2523 polling-delay = <0>; 2524 thermal-sensors = <&tsens0 8>; 2525 2526 trips { 2527 cpu6_alert0: trip-point0 { 2528 temperature = <90000>; 2529 hysteresis = <2000>; 2530 type = "passive"; 2531 }; 2532 2533 cpu6_alert1: trip-point1 { 2534 temperature = <95000>; 2535 hysteresis = <2000>; 2536 type = "passive"; 2537 }; 2538 2539 cpu6_crit: cpu_crit { 2540 temperature = <110000>; 2541 hysteresis = <1000>; 2542 type = "critical"; 2543 }; 2544 }; 2545 }; 2546 2547 cpu7-thermal { 2548 polling-delay-passive = <0>; 2549 polling-delay = <0>; 2550 thermal-sensors = <&tsens0 9>; 2551 2552 trips { 2553 cpu7_alert0: trip-point0 { 2554 temperature = <90000>; 2555 hysteresis = <2000>; 2556 type = "passive"; 2557 }; 2558 2559 cpu7_alert1: trip-point1 { 2560 temperature = <95000>; 2561 hysteresis = <2000>; 2562 type = "passive"; 2563 }; 2564 2565 cpu7_crit: cpu_crit { 2566 temperature = <110000>; 2567 hysteresis = <1000>; 2568 type = "critical"; 2569 }; 2570 }; 2571 }; 2572 2573 cpu45-thermal { 2574 polling-delay-passive = <0>; 2575 polling-delay = <0>; 2576 thermal-sensors = <&tsens0 10>; 2577 2578 trips { 2579 cpu45_alert0: trip-point0 { 2580 temperature = <90000>; 2581 hysteresis = <2000>; 2582 type = "passive"; 2583 }; 2584 2585 cpu45_alert1: trip-point1 { 2586 temperature = <95000>; 2587 hysteresis = <2000>; 2588 type = "passive"; 2589 }; 2590 2591 cpu45_crit: cpu_crit { 2592 temperature = <110000>; 2593 hysteresis = <1000>; 2594 type = "critical"; 2595 }; 2596 }; 2597 }; 2598 2599 cpu67-thermal { 2600 polling-delay-passive = <0>; 2601 polling-delay = <0>; 2602 thermal-sensors = <&tsens0 11>; 2603 2604 trips { 2605 cpu67_alert0: trip-point0 { 2606 temperature = <90000>; 2607 hysteresis = <2000>; 2608 type = "passive"; 2609 }; 2610 2611 cpu67_alert1: trip-point1 { 2612 temperature = <95000>; 2613 hysteresis = <2000>; 2614 type = "passive"; 2615 }; 2616 2617 cpu67_crit: cpu_crit { 2618 temperature = <110000>; 2619 hysteresis = <1000>; 2620 type = "critical"; 2621 }; 2622 }; 2623 }; 2624 2625 cpu0123-thermal { 2626 polling-delay-passive = <0>; 2627 polling-delay = <0>; 2628 thermal-sensors = <&tsens0 12>; 2629 2630 trips { 2631 cpu0123_alert0: trip-point0 { 2632 temperature = <90000>; 2633 hysteresis = <2000>; 2634 type = "passive"; 2635 }; 2636 2637 cpu0123_alert1: trip-point1 { 2638 temperature = <95000>; 2639 hysteresis = <2000>; 2640 type = "passive"; 2641 }; 2642 2643 cpu0123_crit: cpu_crit { 2644 temperature = <110000>; 2645 hysteresis = <1000>; 2646 type = "critical"; 2647 }; 2648 }; 2649 }; 2650 2651 modem0-thermal { 2652 polling-delay-passive = <0>; 2653 polling-delay = <0>; 2654 thermal-sensors = <&tsens0 13>; 2655 2656 trips { 2657 trip-point0 { 2658 temperature = <115000>; 2659 hysteresis = <5000>; 2660 type = "passive"; 2661 }; 2662 2663 trip-point1 { 2664 temperature = <125000>; 2665 hysteresis = <1000>; 2666 type = "passive"; 2667 }; 2668 }; 2669 }; 2670 2671 display-thermal { 2672 polling-delay-passive = <0>; 2673 polling-delay = <0>; 2674 thermal-sensors = <&tsens0 14>; 2675 2676 trips { 2677 trip-point0 { 2678 temperature = <115000>; 2679 hysteresis = <5000>; 2680 type = "passive"; 2681 }; 2682 2683 trip-point1 { 2684 temperature = <125000>; 2685 hysteresis = <1000>; 2686 type = "passive"; 2687 }; 2688 }; 2689 }; 2690 2691 gpu-thermal { 2692 polling-delay-passive = <0>; 2693 polling-delay = <0>; 2694 thermal-sensors = <&tsens0 15>; 2695 2696 trips { 2697 trip-point0 { 2698 temperature = <115000>; 2699 hysteresis = <5000>; 2700 type = "passive"; 2701 }; 2702 2703 trip-point1 { 2704 temperature = <125000>; 2705 hysteresis = <1000>; 2706 type = "passive"; 2707 }; 2708 }; 2709 }; 2710 }; 2711 2712 timer { 2713 compatible = "arm,armv8-timer"; 2714 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2715 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2716 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2717 <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 2718 }; 2719}; 2720