1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright (c) 2021, Iskren Chernev <iskren.chernev@gmail.com> 4 */ 5 6#include <dt-bindings/clock/qcom,gcc-sm6115.h> 7#include <dt-bindings/clock/qcom,sm6115-dispcc.h> 8#include <dt-bindings/clock/qcom,sm6115-gpucc.h> 9#include <dt-bindings/clock/qcom,rpmcc.h> 10#include <dt-bindings/dma/qcom-gpi.h> 11#include <dt-bindings/firmware/qcom,scm.h> 12#include <dt-bindings/gpio/gpio.h> 13#include <dt-bindings/interrupt-controller/arm-gic.h> 14#include <dt-bindings/power/qcom-rpmpd.h> 15 16/ { 17 interrupt-parent = <&intc>; 18 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 chosen { }; 23 24 clocks { 25 xo_board: xo-board { 26 compatible = "fixed-clock"; 27 #clock-cells = <0>; 28 }; 29 30 sleep_clk: sleep-clk { 31 compatible = "fixed-clock"; 32 #clock-cells = <0>; 33 }; 34 }; 35 36 cpus { 37 #address-cells = <2>; 38 #size-cells = <0>; 39 40 CPU0: cpu@0 { 41 device_type = "cpu"; 42 compatible = "qcom,kryo260"; 43 reg = <0x0 0x0>; 44 clocks = <&cpufreq_hw 0>; 45 capacity-dmips-mhz = <1024>; 46 dynamic-power-coefficient = <100>; 47 enable-method = "psci"; 48 next-level-cache = <&L2_0>; 49 qcom,freq-domain = <&cpufreq_hw 0>; 50 power-domains = <&CPU_PD0>; 51 power-domain-names = "psci"; 52 L2_0: l2-cache { 53 compatible = "cache"; 54 cache-level = <2>; 55 cache-unified; 56 }; 57 }; 58 59 CPU1: cpu@1 { 60 device_type = "cpu"; 61 compatible = "qcom,kryo260"; 62 reg = <0x0 0x1>; 63 clocks = <&cpufreq_hw 0>; 64 capacity-dmips-mhz = <1024>; 65 dynamic-power-coefficient = <100>; 66 enable-method = "psci"; 67 next-level-cache = <&L2_0>; 68 qcom,freq-domain = <&cpufreq_hw 0>; 69 power-domains = <&CPU_PD1>; 70 power-domain-names = "psci"; 71 }; 72 73 CPU2: cpu@2 { 74 device_type = "cpu"; 75 compatible = "qcom,kryo260"; 76 reg = <0x0 0x2>; 77 clocks = <&cpufreq_hw 0>; 78 capacity-dmips-mhz = <1024>; 79 dynamic-power-coefficient = <100>; 80 enable-method = "psci"; 81 next-level-cache = <&L2_0>; 82 qcom,freq-domain = <&cpufreq_hw 0>; 83 power-domains = <&CPU_PD2>; 84 power-domain-names = "psci"; 85 }; 86 87 CPU3: cpu@3 { 88 device_type = "cpu"; 89 compatible = "qcom,kryo260"; 90 reg = <0x0 0x3>; 91 clocks = <&cpufreq_hw 0>; 92 capacity-dmips-mhz = <1024>; 93 dynamic-power-coefficient = <100>; 94 enable-method = "psci"; 95 next-level-cache = <&L2_0>; 96 qcom,freq-domain = <&cpufreq_hw 0>; 97 power-domains = <&CPU_PD3>; 98 power-domain-names = "psci"; 99 }; 100 101 CPU4: cpu@100 { 102 device_type = "cpu"; 103 compatible = "qcom,kryo260"; 104 reg = <0x0 0x100>; 105 clocks = <&cpufreq_hw 1>; 106 enable-method = "psci"; 107 capacity-dmips-mhz = <1638>; 108 dynamic-power-coefficient = <282>; 109 next-level-cache = <&L2_1>; 110 qcom,freq-domain = <&cpufreq_hw 1>; 111 power-domains = <&CPU_PD4>; 112 power-domain-names = "psci"; 113 L2_1: l2-cache { 114 compatible = "cache"; 115 cache-level = <2>; 116 cache-unified; 117 }; 118 }; 119 120 CPU5: cpu@101 { 121 device_type = "cpu"; 122 compatible = "qcom,kryo260"; 123 reg = <0x0 0x101>; 124 clocks = <&cpufreq_hw 1>; 125 capacity-dmips-mhz = <1638>; 126 dynamic-power-coefficient = <282>; 127 enable-method = "psci"; 128 next-level-cache = <&L2_1>; 129 qcom,freq-domain = <&cpufreq_hw 1>; 130 power-domains = <&CPU_PD5>; 131 power-domain-names = "psci"; 132 }; 133 134 CPU6: cpu@102 { 135 device_type = "cpu"; 136 compatible = "qcom,kryo260"; 137 reg = <0x0 0x102>; 138 clocks = <&cpufreq_hw 1>; 139 capacity-dmips-mhz = <1638>; 140 dynamic-power-coefficient = <282>; 141 enable-method = "psci"; 142 next-level-cache = <&L2_1>; 143 qcom,freq-domain = <&cpufreq_hw 1>; 144 power-domains = <&CPU_PD6>; 145 power-domain-names = "psci"; 146 }; 147 148 CPU7: cpu@103 { 149 device_type = "cpu"; 150 compatible = "qcom,kryo260"; 151 reg = <0x0 0x103>; 152 clocks = <&cpufreq_hw 1>; 153 capacity-dmips-mhz = <1638>; 154 dynamic-power-coefficient = <282>; 155 enable-method = "psci"; 156 next-level-cache = <&L2_1>; 157 qcom,freq-domain = <&cpufreq_hw 1>; 158 power-domains = <&CPU_PD7>; 159 power-domain-names = "psci"; 160 }; 161 162 cpu-map { 163 cluster0 { 164 core0 { 165 cpu = <&CPU0>; 166 }; 167 168 core1 { 169 cpu = <&CPU1>; 170 }; 171 172 core2 { 173 cpu = <&CPU2>; 174 }; 175 176 core3 { 177 cpu = <&CPU3>; 178 }; 179 }; 180 181 cluster1 { 182 core0 { 183 cpu = <&CPU4>; 184 }; 185 186 core1 { 187 cpu = <&CPU5>; 188 }; 189 190 core2 { 191 cpu = <&CPU6>; 192 }; 193 194 core3 { 195 cpu = <&CPU7>; 196 }; 197 }; 198 }; 199 200 idle-states { 201 entry-method = "psci"; 202 203 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 204 compatible = "arm,idle-state"; 205 idle-state-name = "silver-rail-power-collapse"; 206 arm,psci-suspend-param = <0x40000003>; 207 entry-latency-us = <290>; 208 exit-latency-us = <376>; 209 min-residency-us = <1182>; 210 local-timer-stop; 211 }; 212 213 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 214 compatible = "arm,idle-state"; 215 idle-state-name = "gold-rail-power-collapse"; 216 arm,psci-suspend-param = <0x40000003>; 217 entry-latency-us = <297>; 218 exit-latency-us = <324>; 219 min-residency-us = <1110>; 220 local-timer-stop; 221 }; 222 }; 223 224 domain-idle-states { 225 CLUSTER_0_SLEEP_0: cluster-sleep-0-0 { 226 /* GDHS */ 227 compatible = "domain-idle-state"; 228 arm,psci-suspend-param = <0x40000022>; 229 entry-latency-us = <360>; 230 exit-latency-us = <421>; 231 min-residency-us = <782>; 232 }; 233 234 CLUSTER_0_SLEEP_1: cluster-sleep-0-1 { 235 /* Power Collapse */ 236 compatible = "domain-idle-state"; 237 arm,psci-suspend-param = <0x41000044>; 238 entry-latency-us = <800>; 239 exit-latency-us = <2118>; 240 min-residency-us = <7376>; 241 }; 242 243 CLUSTER_1_SLEEP_0: cluster-sleep-1-0 { 244 /* GDHS */ 245 compatible = "domain-idle-state"; 246 arm,psci-suspend-param = <0x40000042>; 247 entry-latency-us = <314>; 248 exit-latency-us = <345>; 249 min-residency-us = <660>; 250 }; 251 252 CLUSTER_1_SLEEP_1: cluster-sleep-1-1 { 253 /* Power Collapse */ 254 compatible = "domain-idle-state"; 255 arm,psci-suspend-param = <0x41000044>; 256 entry-latency-us = <640>; 257 exit-latency-us = <1654>; 258 min-residency-us = <8094>; 259 }; 260 }; 261 }; 262 263 firmware { 264 scm: scm { 265 compatible = "qcom,scm-sm6115", "qcom,scm"; 266 #reset-cells = <1>; 267 }; 268 }; 269 270 memory@80000000 { 271 device_type = "memory"; 272 /* We expect the bootloader to fill in the size */ 273 reg = <0 0x80000000 0 0>; 274 }; 275 276 pmu { 277 compatible = "arm,armv8-pmuv3"; 278 interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>; 279 }; 280 281 psci { 282 compatible = "arm,psci-1.0"; 283 method = "smc"; 284 285 CPU_PD0: power-domain-cpu0 { 286 #power-domain-cells = <0>; 287 power-domains = <&CLUSTER_0_PD>; 288 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 289 }; 290 291 CPU_PD1: power-domain-cpu1 { 292 #power-domain-cells = <0>; 293 power-domains = <&CLUSTER_0_PD>; 294 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 295 }; 296 297 CPU_PD2: power-domain-cpu2 { 298 #power-domain-cells = <0>; 299 power-domains = <&CLUSTER_0_PD>; 300 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 301 }; 302 303 CPU_PD3: power-domain-cpu3 { 304 #power-domain-cells = <0>; 305 power-domains = <&CLUSTER_0_PD>; 306 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 307 }; 308 309 CPU_PD4: power-domain-cpu4 { 310 #power-domain-cells = <0>; 311 power-domains = <&CLUSTER_1_PD>; 312 domain-idle-states = <&BIG_CPU_SLEEP_0>; 313 }; 314 315 CPU_PD5: power-domain-cpu5 { 316 #power-domain-cells = <0>; 317 power-domains = <&CLUSTER_1_PD>; 318 domain-idle-states = <&BIG_CPU_SLEEP_0>; 319 }; 320 321 CPU_PD6: power-domain-cpu6 { 322 #power-domain-cells = <0>; 323 power-domains = <&CLUSTER_1_PD>; 324 domain-idle-states = <&BIG_CPU_SLEEP_0>; 325 }; 326 327 CPU_PD7: power-domain-cpu7 { 328 #power-domain-cells = <0>; 329 power-domains = <&CLUSTER_1_PD>; 330 domain-idle-states = <&BIG_CPU_SLEEP_0>; 331 }; 332 333 CLUSTER_0_PD: power-domain-cpu-cluster0 { 334 #power-domain-cells = <0>; 335 domain-idle-states = <&CLUSTER_0_SLEEP_0>, <&CLUSTER_0_SLEEP_1>; 336 }; 337 338 CLUSTER_1_PD: power-domain-cpu-cluster1 { 339 #power-domain-cells = <0>; 340 domain-idle-states = <&CLUSTER_1_SLEEP_0>, <&CLUSTER_1_SLEEP_1>; 341 }; 342 }; 343 344 rpm: remoteproc { 345 compatible = "qcom,sm6115-rpm-proc", "qcom,rpm-proc"; 346 347 glink-edge { 348 compatible = "qcom,glink-rpm"; 349 350 interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>; 351 qcom,rpm-msg-ram = <&rpm_msg_ram>; 352 mboxes = <&apcs_glb 0>; 353 354 rpm_requests: rpm-requests { 355 compatible = "qcom,rpm-sm6115"; 356 qcom,glink-channels = "rpm_requests"; 357 358 rpmcc: clock-controller { 359 compatible = "qcom,rpmcc-sm6115", "qcom,rpmcc"; 360 clocks = <&xo_board>; 361 clock-names = "xo"; 362 #clock-cells = <1>; 363 }; 364 365 rpmpd: power-controller { 366 compatible = "qcom,sm6115-rpmpd"; 367 #power-domain-cells = <1>; 368 operating-points-v2 = <&rpmpd_opp_table>; 369 370 rpmpd_opp_table: opp-table { 371 compatible = "operating-points-v2"; 372 373 rpmpd_opp_min_svs: opp1 { 374 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 375 }; 376 377 rpmpd_opp_low_svs: opp2 { 378 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 379 }; 380 381 rpmpd_opp_svs: opp3 { 382 opp-level = <RPM_SMD_LEVEL_SVS>; 383 }; 384 385 rpmpd_opp_svs_plus: opp4 { 386 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 387 }; 388 389 rpmpd_opp_nom: opp5 { 390 opp-level = <RPM_SMD_LEVEL_NOM>; 391 }; 392 393 rpmpd_opp_nom_plus: opp6 { 394 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 395 }; 396 397 rpmpd_opp_turbo: opp7 { 398 opp-level = <RPM_SMD_LEVEL_TURBO>; 399 }; 400 401 rpmpd_opp_turbo_plus: opp8 { 402 opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>; 403 }; 404 }; 405 }; 406 }; 407 }; 408 }; 409 410 reserved_memory: reserved-memory { 411 #address-cells = <2>; 412 #size-cells = <2>; 413 ranges; 414 415 hyp_mem: memory@45700000 { 416 reg = <0x0 0x45700000 0x0 0x600000>; 417 no-map; 418 }; 419 420 xbl_aop_mem: memory@45e00000 { 421 reg = <0x0 0x45e00000 0x0 0x140000>; 422 no-map; 423 }; 424 425 sec_apps_mem: memory@45fff000 { 426 reg = <0x0 0x45fff000 0x0 0x1000>; 427 no-map; 428 }; 429 430 smem_mem: memory@46000000 { 431 compatible = "qcom,smem"; 432 reg = <0x0 0x46000000 0x0 0x200000>; 433 no-map; 434 435 hwlocks = <&tcsr_mutex 3>; 436 qcom,rpm-msg-ram = <&rpm_msg_ram>; 437 }; 438 439 cdsp_sec_mem: memory@46200000 { 440 reg = <0x0 0x46200000 0x0 0x1e00000>; 441 no-map; 442 }; 443 444 pil_modem_mem: memory@4ab00000 { 445 reg = <0x0 0x4ab00000 0x0 0x6900000>; 446 no-map; 447 }; 448 449 pil_video_mem: memory@51400000 { 450 reg = <0x0 0x51400000 0x0 0x500000>; 451 no-map; 452 }; 453 454 wlan_msa_mem: memory@51900000 { 455 reg = <0x0 0x51900000 0x0 0x100000>; 456 no-map; 457 }; 458 459 pil_cdsp_mem: memory@51a00000 { 460 reg = <0x0 0x51a00000 0x0 0x1e00000>; 461 no-map; 462 }; 463 464 pil_adsp_mem: memory@53800000 { 465 reg = <0x0 0x53800000 0x0 0x2800000>; 466 no-map; 467 }; 468 469 pil_ipa_fw_mem: memory@56100000 { 470 reg = <0x0 0x56100000 0x0 0x10000>; 471 no-map; 472 }; 473 474 pil_ipa_gsi_mem: memory@56110000 { 475 reg = <0x0 0x56110000 0x0 0x5000>; 476 no-map; 477 }; 478 479 pil_gpu_mem: memory@56115000 { 480 reg = <0x0 0x56115000 0x0 0x2000>; 481 no-map; 482 }; 483 484 cont_splash_memory: memory@5c000000 { 485 reg = <0x0 0x5c000000 0x0 0x00f00000>; 486 no-map; 487 }; 488 489 dfps_data_memory: memory@5cf00000 { 490 reg = <0x0 0x5cf00000 0x0 0x0100000>; 491 no-map; 492 }; 493 494 removed_mem: memory@60000000 { 495 reg = <0x0 0x60000000 0x0 0x3900000>; 496 no-map; 497 }; 498 499 rmtfs_mem: memory@89b01000 { 500 compatible = "qcom,rmtfs-mem"; 501 reg = <0x0 0x89b01000 0x0 0x200000>; 502 no-map; 503 504 qcom,client-id = <1>; 505 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA QCOM_SCM_VMID_NAV>; 506 }; 507 }; 508 509 smp2p-adsp { 510 compatible = "qcom,smp2p"; 511 qcom,smem = <443>, <429>; 512 513 interrupts = <GIC_SPI 279 IRQ_TYPE_EDGE_RISING>; 514 515 mboxes = <&apcs_glb 10>; 516 517 qcom,local-pid = <0>; 518 qcom,remote-pid = <2>; 519 520 adsp_smp2p_out: master-kernel { 521 qcom,entry-name = "master-kernel"; 522 #qcom,smem-state-cells = <1>; 523 }; 524 525 adsp_smp2p_in: slave-kernel { 526 qcom,entry-name = "slave-kernel"; 527 528 interrupt-controller; 529 #interrupt-cells = <2>; 530 }; 531 }; 532 533 smp2p-cdsp { 534 compatible = "qcom,smp2p"; 535 qcom,smem = <94>, <432>; 536 537 interrupts = <GIC_SPI 263 IRQ_TYPE_EDGE_RISING>; 538 539 mboxes = <&apcs_glb 30>; 540 541 qcom,local-pid = <0>; 542 qcom,remote-pid = <5>; 543 544 cdsp_smp2p_out: master-kernel { 545 qcom,entry-name = "master-kernel"; 546 #qcom,smem-state-cells = <1>; 547 }; 548 549 cdsp_smp2p_in: slave-kernel { 550 qcom,entry-name = "slave-kernel"; 551 552 interrupt-controller; 553 #interrupt-cells = <2>; 554 }; 555 }; 556 557 smp2p-mpss { 558 compatible = "qcom,smp2p"; 559 qcom,smem = <435>, <428>; 560 561 interrupts = <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>; 562 563 mboxes = <&apcs_glb 14>; 564 565 qcom,local-pid = <0>; 566 qcom,remote-pid = <1>; 567 568 modem_smp2p_out: master-kernel { 569 qcom,entry-name = "master-kernel"; 570 #qcom,smem-state-cells = <1>; 571 }; 572 573 modem_smp2p_in: slave-kernel { 574 qcom,entry-name = "slave-kernel"; 575 576 interrupt-controller; 577 #interrupt-cells = <2>; 578 }; 579 }; 580 581 soc: soc@0 { 582 compatible = "simple-bus"; 583 #address-cells = <2>; 584 #size-cells = <2>; 585 ranges = <0 0 0 0 0x10 0>; 586 dma-ranges = <0 0 0 0 0x10 0>; 587 588 tcsr_mutex: hwlock@340000 { 589 compatible = "qcom,tcsr-mutex"; 590 reg = <0x0 0x00340000 0x0 0x20000>; 591 #hwlock-cells = <1>; 592 }; 593 594 tcsr_regs: syscon@3c0000 { 595 compatible = "qcom,sm6115-tcsr", "syscon"; 596 reg = <0x0 0x003c0000 0x0 0x40000>; 597 }; 598 599 tlmm: pinctrl@500000 { 600 compatible = "qcom,sm6115-tlmm"; 601 reg = <0x0 0x00500000 0x0 0x400000>, 602 <0x0 0x00900000 0x0 0x400000>, 603 <0x0 0x00d00000 0x0 0x400000>; 604 reg-names = "west", "south", "east"; 605 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 606 gpio-controller; 607 gpio-ranges = <&tlmm 0 0 114>; /* GPIOs + ufs_reset */ 608 #gpio-cells = <2>; 609 interrupt-controller; 610 #interrupt-cells = <2>; 611 612 qup_i2c0_default: qup-i2c0-default-state { 613 pins = "gpio0", "gpio1"; 614 function = "qup0"; 615 drive-strength = <2>; 616 bias-pull-up; 617 }; 618 619 qup_i2c1_default: qup-i2c1-default-state { 620 pins = "gpio4", "gpio5"; 621 function = "qup1"; 622 drive-strength = <2>; 623 bias-pull-up; 624 }; 625 626 qup_i2c2_default: qup-i2c2-default-state { 627 pins = "gpio6", "gpio7"; 628 function = "qup2"; 629 drive-strength = <2>; 630 bias-pull-up; 631 }; 632 633 qup_i2c3_default: qup-i2c3-default-state { 634 pins = "gpio8", "gpio9"; 635 function = "qup3"; 636 drive-strength = <2>; 637 bias-pull-up; 638 }; 639 640 qup_i2c4_default: qup-i2c4-default-state { 641 pins = "gpio12", "gpio13"; 642 function = "qup4"; 643 drive-strength = <2>; 644 bias-pull-up; 645 }; 646 647 qup_i2c5_default: qup-i2c5-default-state { 648 pins = "gpio14", "gpio15"; 649 function = "qup5"; 650 drive-strength = <2>; 651 bias-pull-up; 652 }; 653 654 qup_spi0_default: qup-spi0-default-state { 655 pins = "gpio0", "gpio1","gpio2", "gpio3"; 656 function = "qup0"; 657 drive-strength = <2>; 658 bias-pull-up; 659 }; 660 661 qup_spi1_default: qup-spi1-default-state { 662 pins = "gpio4", "gpio5", "gpio69", "gpio70"; 663 function = "qup1"; 664 drive-strength = <2>; 665 bias-pull-up; 666 }; 667 668 qup_spi2_default: qup-spi2-default-state { 669 pins = "gpio6", "gpio7", "gpio71", "gpio80"; 670 function = "qup2"; 671 drive-strength = <2>; 672 bias-pull-up; 673 }; 674 675 qup_spi3_default: qup-spi3-default-state { 676 pins = "gpio8", "gpio9", "gpio10", "gpio11"; 677 function = "qup3"; 678 drive-strength = <2>; 679 bias-pull-up; 680 }; 681 682 qup_spi4_default: qup-spi4-default-state { 683 pins = "gpio12", "gpio13", "gpio96", "gpio97"; 684 function = "qup4"; 685 drive-strength = <2>; 686 bias-pull-up; 687 }; 688 689 qup_spi5_default: qup-spi5-default-state { 690 pins = "gpio14", "gpio15", "gpio16", "gpio17"; 691 function = "qup5"; 692 drive-strength = <2>; 693 bias-pull-up; 694 }; 695 696 sdc1_state_on: sdc1-on-state { 697 clk-pins { 698 pins = "sdc1_clk"; 699 bias-disable; 700 drive-strength = <16>; 701 }; 702 703 cmd-pins { 704 pins = "sdc1_cmd"; 705 bias-pull-up; 706 drive-strength = <10>; 707 }; 708 709 data-pins { 710 pins = "sdc1_data"; 711 bias-pull-up; 712 drive-strength = <10>; 713 }; 714 715 rclk-pins { 716 pins = "sdc1_rclk"; 717 bias-pull-down; 718 }; 719 }; 720 721 sdc1_state_off: sdc1-off-state { 722 clk-pins { 723 pins = "sdc1_clk"; 724 bias-disable; 725 drive-strength = <2>; 726 }; 727 728 cmd-pins { 729 pins = "sdc1_cmd"; 730 bias-pull-up; 731 drive-strength = <2>; 732 }; 733 734 data-pins { 735 pins = "sdc1_data"; 736 bias-pull-up; 737 drive-strength = <2>; 738 }; 739 740 rclk-pins { 741 pins = "sdc1_rclk"; 742 bias-pull-down; 743 }; 744 }; 745 746 sdc2_state_on: sdc2-on-state { 747 clk-pins { 748 pins = "sdc2_clk"; 749 bias-disable; 750 drive-strength = <16>; 751 }; 752 753 cmd-pins { 754 pins = "sdc2_cmd"; 755 bias-pull-up; 756 drive-strength = <10>; 757 }; 758 759 data-pins { 760 pins = "sdc2_data"; 761 bias-pull-up; 762 drive-strength = <10>; 763 }; 764 }; 765 766 sdc2_state_off: sdc2-off-state { 767 clk-pins { 768 pins = "sdc2_clk"; 769 bias-disable; 770 drive-strength = <2>; 771 }; 772 773 cmd-pins { 774 pins = "sdc2_cmd"; 775 bias-pull-up; 776 drive-strength = <2>; 777 }; 778 779 data-pins { 780 pins = "sdc2_data"; 781 bias-pull-up; 782 drive-strength = <2>; 783 }; 784 }; 785 }; 786 787 gcc: clock-controller@1400000 { 788 compatible = "qcom,gcc-sm6115"; 789 reg = <0x0 0x01400000 0x0 0x1f0000>; 790 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>; 791 clock-names = "bi_tcxo", "sleep_clk"; 792 #clock-cells = <1>; 793 #reset-cells = <1>; 794 #power-domain-cells = <1>; 795 }; 796 797 usb_hsphy: phy@1613000 { 798 compatible = "qcom,sm6115-qusb2-phy"; 799 reg = <0x0 0x01613000 0x0 0x180>; 800 #phy-cells = <0>; 801 802 clocks = <&gcc GCC_AHB2PHY_USB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>; 803 clock-names = "cfg_ahb", "ref"; 804 805 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 806 nvmem-cells = <&qusb2_hstx_trim>; 807 808 status = "disabled"; 809 }; 810 811 cryptobam: dma-controller@1b04000 { 812 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 813 reg = <0x0 0x01b04000 0x0 0x24000>; 814 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>; 815 clocks = <&rpmcc RPM_SMD_CE1_CLK>; 816 clock-names = "bam_clk"; 817 #dma-cells = <1>; 818 qcom,ee = <0>; 819 qcom,controlled-remotely; 820 iommus = <&apps_smmu 0x92 0>, 821 <&apps_smmu 0x94 0x11>, 822 <&apps_smmu 0x96 0x11>, 823 <&apps_smmu 0x98 0x1>, 824 <&apps_smmu 0x9F 0>; 825 }; 826 827 crypto: crypto@1b3a000 { 828 compatible = "qcom,sm6115-qce", "qcom,ipq4019-qce", "qcom,qce"; 829 reg = <0x0 0x01b3a000 0x0 0x6000>; 830 clocks = <&rpmcc RPM_SMD_CE1_CLK>; 831 clock-names = "core"; 832 833 dmas = <&cryptobam 6>, <&cryptobam 7>; 834 dma-names = "rx", "tx"; 835 iommus = <&apps_smmu 0x92 0>, 836 <&apps_smmu 0x94 0x11>, 837 <&apps_smmu 0x96 0x11>, 838 <&apps_smmu 0x98 0x1>, 839 <&apps_smmu 0x9F 0>; 840 }; 841 842 usb_qmpphy: phy@1615000 { 843 compatible = "qcom,sm6115-qmp-usb3-phy"; 844 reg = <0x0 0x01615000 0x0 0x1000>; 845 846 clocks = <&gcc GCC_AHB2PHY_USB_CLK>, 847 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 848 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 849 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 850 clock-names = "cfg_ahb", 851 "ref", 852 "com_aux", 853 "pipe"; 854 855 resets = <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>, 856 <&gcc GCC_USB3PHY_PHY_PRIM_SP0_BCR>; 857 reset-names = "phy", "phy_phy"; 858 859 #clock-cells = <0>; 860 clock-output-names = "usb3_phy_pipe_clk_src"; 861 862 #phy-cells = <0>; 863 864 qcom,tcsr-reg = <&tcsr_regs 0xb244>; 865 866 status = "disabled"; 867 }; 868 869 qfprom@1b40000 { 870 compatible = "qcom,sm6115-qfprom", "qcom,qfprom"; 871 reg = <0x0 0x01b40000 0x0 0x7000>; 872 #address-cells = <1>; 873 #size-cells = <1>; 874 875 qusb2_hstx_trim: hstx-trim@25b { 876 reg = <0x25b 0x1>; 877 bits = <1 4>; 878 }; 879 880 gpu_speed_bin: gpu-speed-bin@6006 { 881 reg = <0x6006 0x2>; 882 bits = <5 8>; 883 }; 884 }; 885 886 rng: rng@1b53000 { 887 compatible = "qcom,prng-ee"; 888 reg = <0x0 0x01b53000 0x0 0x1000>; 889 clocks = <&gcc GCC_PRNG_AHB_CLK>; 890 clock-names = "core"; 891 }; 892 893 spmi_bus: spmi@1c40000 { 894 compatible = "qcom,spmi-pmic-arb"; 895 reg = <0x0 0x01c40000 0x0 0x1100>, 896 <0x0 0x01e00000 0x0 0x2000000>, 897 <0x0 0x03e00000 0x0 0x100000>, 898 <0x0 0x03f00000 0x0 0xa0000>, 899 <0x0 0x01c0a000 0x0 0x26000>; 900 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 901 interrupt-names = "periph_irq"; 902 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 903 qcom,ee = <0>; 904 qcom,channel = <0>; 905 #address-cells = <2>; 906 #size-cells = <0>; 907 interrupt-controller; 908 #interrupt-cells = <4>; 909 }; 910 911 tsens0: thermal-sensor@4411000 { 912 compatible = "qcom,sm6115-tsens", "qcom,tsens-v2"; 913 reg = <0x0 0x04411000 0x0 0x1ff>, /* TM */ 914 <0x0 0x04410000 0x0 0x8>; /* SROT */ 915 #qcom,sensors = <16>; 916 interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 917 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 918 interrupt-names = "uplow", "critical"; 919 #thermal-sensor-cells = <1>; 920 }; 921 922 rpm_msg_ram: sram@45f0000 { 923 compatible = "qcom,rpm-msg-ram"; 924 reg = <0x0 0x045f0000 0x0 0x7000>; 925 }; 926 927 sram@4690000 { 928 compatible = "qcom,rpm-stats"; 929 reg = <0x0 0x04690000 0x0 0x10000>; 930 }; 931 932 sdhc_1: mmc@4744000 { 933 compatible = "qcom,sm6115-sdhci", "qcom,sdhci-msm-v5"; 934 reg = <0x0 0x04744000 0x0 0x1000>, 935 <0x0 0x04745000 0x0 0x1000>, 936 <0x0 0x04748000 0x0 0x8000>; 937 reg-names = "hc", "cqhci", "ice"; 938 939 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, 940 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 941 interrupt-names = "hc_irq", "pwr_irq"; 942 943 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 944 <&gcc GCC_SDCC1_APPS_CLK>, 945 <&rpmcc RPM_SMD_XO_CLK_SRC>, 946 <&gcc GCC_SDCC1_ICE_CORE_CLK>; 947 clock-names = "iface", "core", "xo", "ice"; 948 949 bus-width = <8>; 950 status = "disabled"; 951 }; 952 953 sdhc_2: mmc@4784000 { 954 compatible = "qcom,sm6115-sdhci", "qcom,sdhci-msm-v5"; 955 reg = <0x0 0x04784000 0x0 0x1000>; 956 reg-names = "hc"; 957 958 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 959 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 960 interrupt-names = "hc_irq", "pwr_irq"; 961 962 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 963 <&gcc GCC_SDCC2_APPS_CLK>, 964 <&rpmcc RPM_SMD_XO_CLK_SRC>; 965 clock-names = "iface", "core", "xo"; 966 967 power-domains = <&rpmpd SM6115_VDDCX>; 968 operating-points-v2 = <&sdhc2_opp_table>; 969 iommus = <&apps_smmu 0x00a0 0x0>; 970 resets = <&gcc GCC_SDCC2_BCR>; 971 972 bus-width = <4>; 973 qcom,dll-config = <0x0007642c>; 974 qcom,ddr-config = <0x80040868>; 975 status = "disabled"; 976 977 sdhc2_opp_table: opp-table { 978 compatible = "operating-points-v2"; 979 980 opp-100000000 { 981 opp-hz = /bits/ 64 <100000000>; 982 required-opps = <&rpmpd_opp_low_svs>; 983 }; 984 985 opp-202000000 { 986 opp-hz = /bits/ 64 <202000000>; 987 required-opps = <&rpmpd_opp_nom>; 988 }; 989 }; 990 }; 991 992 ufs_mem_hc: ufs@4804000 { 993 compatible = "qcom,sm6115-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; 994 reg = <0x0 0x04804000 0x0 0x3000>, <0x0 0x04810000 0x0 0x8000>; 995 reg-names = "std", "ice"; 996 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 997 phys = <&ufs_mem_phy_lanes>; 998 phy-names = "ufsphy"; 999 lanes-per-direction = <1>; 1000 #reset-cells = <1>; 1001 resets = <&gcc GCC_UFS_PHY_BCR>; 1002 reset-names = "rst"; 1003 1004 power-domains = <&gcc GCC_UFS_PHY_GDSC>; 1005 iommus = <&apps_smmu 0x100 0>; 1006 1007 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 1008 <&gcc GCC_SYS_NOC_UFS_PHY_AXI_CLK>, 1009 <&gcc GCC_UFS_PHY_AHB_CLK>, 1010 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 1011 <&rpmcc RPM_SMD_XO_CLK_SRC>, 1012 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 1013 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 1014 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 1015 clock-names = "core_clk", 1016 "bus_aggr_clk", 1017 "iface_clk", 1018 "core_clk_unipro", 1019 "ref_clk", 1020 "tx_lane0_sync_clk", 1021 "rx_lane0_sync_clk", 1022 "ice_core_clk"; 1023 1024 freq-table-hz = <50000000 200000000>, 1025 <0 0>, 1026 <0 0>, 1027 <37500000 150000000>, 1028 <0 0>, 1029 <0 0>, 1030 <0 0>, 1031 <75000000 300000000>; 1032 1033 status = "disabled"; 1034 }; 1035 1036 ufs_mem_phy: phy@4807000 { 1037 compatible = "qcom,sm6115-qmp-ufs-phy"; 1038 reg = <0x0 0x04807000 0x0 0x1c4>; 1039 #address-cells = <2>; 1040 #size-cells = <2>; 1041 ranges; 1042 1043 clocks = <&gcc GCC_UFS_CLKREF_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 1044 clock-names = "ref", "ref_aux"; 1045 1046 power-domains = <&gcc GCC_UFS_PHY_GDSC>; 1047 1048 resets = <&ufs_mem_hc 0>; 1049 reset-names = "ufsphy"; 1050 status = "disabled"; 1051 1052 ufs_mem_phy_lanes: phy@4807400 { 1053 reg = <0x0 0x04807400 0x0 0x098>, 1054 <0x0 0x04807600 0x0 0x130>, 1055 <0x0 0x04807c00 0x0 0x16c>; 1056 #phy-cells = <0>; 1057 }; 1058 }; 1059 1060 gpi_dma0: dma-controller@4a00000 { 1061 compatible = "qcom,sm6115-gpi-dma", "qcom,sm6350-gpi-dma"; 1062 reg = <0x0 0x04a00000 0x0 0x60000>; 1063 interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 1064 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 1065 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 1066 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 1067 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 1068 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 1069 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 1070 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 1071 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 1072 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; 1073 dma-channels = <10>; 1074 dma-channel-mask = <0xf>; 1075 iommus = <&apps_smmu 0xf6 0x0>; 1076 #dma-cells = <3>; 1077 status = "disabled"; 1078 }; 1079 1080 qupv3_id_0: geniqup@4ac0000 { 1081 compatible = "qcom,geni-se-qup"; 1082 reg = <0x0 0x04ac0000 0x0 0x2000>; 1083 clock-names = "m-ahb", "s-ahb"; 1084 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1085 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1086 #address-cells = <2>; 1087 #size-cells = <2>; 1088 iommus = <&apps_smmu 0xe3 0x0>; 1089 ranges; 1090 status = "disabled"; 1091 1092 i2c0: i2c@4a80000 { 1093 compatible = "qcom,geni-i2c"; 1094 reg = <0x0 0x04a80000 0x0 0x4000>; 1095 clock-names = "se"; 1096 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1097 pinctrl-names = "default"; 1098 pinctrl-0 = <&qup_i2c0_default>; 1099 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 1100 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1101 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1102 dma-names = "tx", "rx"; 1103 #address-cells = <1>; 1104 #size-cells = <0>; 1105 status = "disabled"; 1106 }; 1107 1108 spi0: spi@4a80000 { 1109 compatible = "qcom,geni-spi"; 1110 reg = <0x0 0x04a80000 0x0 0x4000>; 1111 clock-names = "se"; 1112 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1113 pinctrl-names = "default"; 1114 pinctrl-0 = <&qup_spi0_default>; 1115 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 1116 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1117 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1118 dma-names = "tx", "rx"; 1119 #address-cells = <1>; 1120 #size-cells = <0>; 1121 status = "disabled"; 1122 }; 1123 1124 i2c1: i2c@4a84000 { 1125 compatible = "qcom,geni-i2c"; 1126 reg = <0x0 0x04a84000 0x0 0x4000>; 1127 clock-names = "se"; 1128 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1129 pinctrl-names = "default"; 1130 pinctrl-0 = <&qup_i2c1_default>; 1131 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 1132 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1133 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1134 dma-names = "tx", "rx"; 1135 #address-cells = <1>; 1136 #size-cells = <0>; 1137 status = "disabled"; 1138 }; 1139 1140 spi1: spi@4a84000 { 1141 compatible = "qcom,geni-spi"; 1142 reg = <0x0 0x04a84000 0x0 0x4000>; 1143 clock-names = "se"; 1144 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1145 pinctrl-names = "default"; 1146 pinctrl-0 = <&qup_spi1_default>; 1147 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 1148 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1149 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1150 dma-names = "tx", "rx"; 1151 #address-cells = <1>; 1152 #size-cells = <0>; 1153 status = "disabled"; 1154 }; 1155 1156 i2c2: i2c@4a88000 { 1157 compatible = "qcom,geni-i2c"; 1158 reg = <0x0 0x04a88000 0x0 0x4000>; 1159 clock-names = "se"; 1160 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1161 pinctrl-names = "default"; 1162 pinctrl-0 = <&qup_i2c2_default>; 1163 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; 1164 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1165 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1166 dma-names = "tx", "rx"; 1167 #address-cells = <1>; 1168 #size-cells = <0>; 1169 status = "disabled"; 1170 }; 1171 1172 spi2: spi@4a88000 { 1173 compatible = "qcom,geni-spi"; 1174 reg = <0x0 0x04a88000 0x0 0x4000>; 1175 clock-names = "se"; 1176 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1177 pinctrl-names = "default"; 1178 pinctrl-0 = <&qup_spi2_default>; 1179 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; 1180 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1181 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1182 dma-names = "tx", "rx"; 1183 #address-cells = <1>; 1184 #size-cells = <0>; 1185 status = "disabled"; 1186 }; 1187 1188 i2c3: i2c@4a8c000 { 1189 compatible = "qcom,geni-i2c"; 1190 reg = <0x0 0x04a8c000 0x0 0x4000>; 1191 clock-names = "se"; 1192 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1193 pinctrl-names = "default"; 1194 pinctrl-0 = <&qup_i2c3_default>; 1195 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 1196 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1197 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1198 dma-names = "tx", "rx"; 1199 #address-cells = <1>; 1200 #size-cells = <0>; 1201 status = "disabled"; 1202 }; 1203 1204 spi3: spi@4a8c000 { 1205 compatible = "qcom,geni-spi"; 1206 reg = <0x0 0x04a8c000 0x0 0x4000>; 1207 clock-names = "se"; 1208 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1209 pinctrl-names = "default"; 1210 pinctrl-0 = <&qup_spi3_default>; 1211 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 1212 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1213 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1214 dma-names = "tx", "rx"; 1215 #address-cells = <1>; 1216 #size-cells = <0>; 1217 status = "disabled"; 1218 }; 1219 1220 i2c4: i2c@4a90000 { 1221 compatible = "qcom,geni-i2c"; 1222 reg = <0x0 0x04a90000 0x0 0x4000>; 1223 clock-names = "se"; 1224 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1225 pinctrl-names = "default"; 1226 pinctrl-0 = <&qup_i2c4_default>; 1227 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 1228 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1229 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1230 dma-names = "tx", "rx"; 1231 #address-cells = <1>; 1232 #size-cells = <0>; 1233 status = "disabled"; 1234 }; 1235 1236 spi4: spi@4a90000 { 1237 compatible = "qcom,geni-spi"; 1238 reg = <0x0 0x04a90000 0x0 0x4000>; 1239 clock-names = "se"; 1240 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1241 pinctrl-names = "default"; 1242 pinctrl-0 = <&qup_spi4_default>; 1243 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 1244 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1245 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1246 dma-names = "tx", "rx"; 1247 #address-cells = <1>; 1248 #size-cells = <0>; 1249 status = "disabled"; 1250 }; 1251 1252 uart4: serial@4a90000 { 1253 compatible = "qcom,geni-debug-uart"; 1254 reg = <0x0 0x04a90000 0x0 0x4000>; 1255 clock-names = "se"; 1256 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1257 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 1258 status = "disabled"; 1259 }; 1260 1261 i2c5: i2c@4a94000 { 1262 compatible = "qcom,geni-i2c"; 1263 reg = <0x0 0x04a94000 0x0 0x4000>; 1264 clock-names = "se"; 1265 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1266 pinctrl-names = "default"; 1267 pinctrl-0 = <&qup_i2c5_default>; 1268 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; 1269 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1270 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1271 dma-names = "tx", "rx"; 1272 #address-cells = <1>; 1273 #size-cells = <0>; 1274 status = "disabled"; 1275 }; 1276 1277 spi5: spi@4a94000 { 1278 compatible = "qcom,geni-spi"; 1279 reg = <0x0 0x04a94000 0x0 0x4000>; 1280 clock-names = "se"; 1281 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1282 pinctrl-names = "default"; 1283 pinctrl-0 = <&qup_spi5_default>; 1284 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; 1285 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1286 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1287 dma-names = "tx", "rx"; 1288 #address-cells = <1>; 1289 #size-cells = <0>; 1290 status = "disabled"; 1291 }; 1292 }; 1293 1294 usb: usb@4ef8800 { 1295 compatible = "qcom,sm6115-dwc3", "qcom,dwc3"; 1296 reg = <0x0 0x04ef8800 0x0 0x400>; 1297 #address-cells = <2>; 1298 #size-cells = <2>; 1299 ranges; 1300 1301 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 1302 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 1303 <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>, 1304 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 1305 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1306 <&gcc GCC_USB3_PRIM_CLKREF_CLK>; 1307 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", "xo"; 1308 1309 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1310 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 1311 assigned-clock-rates = <19200000>, <66666667>; 1312 1313 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 1314 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>; 1315 interrupt-names = "hs_phy_irq", "ss_phy_irq"; 1316 1317 resets = <&gcc GCC_USB30_PRIM_BCR>; 1318 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 1319 qcom,select-utmi-as-pipe-clk; 1320 status = "disabled"; 1321 1322 usb_dwc3: usb@4e00000 { 1323 compatible = "snps,dwc3"; 1324 reg = <0x0 0x04e00000 0x0 0xcd00>; 1325 interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 1326 phys = <&usb_hsphy>, <&usb_qmpphy>; 1327 phy-names = "usb2-phy", "usb3-phy"; 1328 iommus = <&apps_smmu 0x120 0x0>; 1329 snps,dis_u2_susphy_quirk; 1330 snps,dis_enblslpm_quirk; 1331 snps,has-lpm-erratum; 1332 snps,hird-threshold = /bits/ 8 <0x10>; 1333 snps,usb3_lpm_capable; 1334 }; 1335 }; 1336 1337 gpu: gpu@5900000 { 1338 compatible = "qcom,adreno-610.0", "qcom,adreno"; 1339 reg = <0x0 0x05900000 0x0 0x40000>; 1340 reg-names = "kgsl_3d0_reg_memory"; 1341 1342 /* There's no (real) GMU, so we have to handle quite a bunch of clocks! */ 1343 clocks = <&gpucc GPU_CC_GX_GFX3D_CLK>, 1344 <&gpucc GPU_CC_AHB_CLK>, 1345 <&gcc GCC_BIMC_GPU_AXI_CLK>, 1346 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1347 <&gpucc GPU_CC_CX_GMU_CLK>, 1348 <&gpucc GPU_CC_CXO_CLK>; 1349 clock-names = "core", 1350 "iface", 1351 "mem_iface", 1352 "alt_mem_iface", 1353 "gmu", 1354 "xo"; 1355 1356 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 1357 1358 iommus = <&adreno_smmu 0 1>; 1359 operating-points-v2 = <&gpu_opp_table>; 1360 power-domains = <&rpmpd SM6115_VDDCX>; 1361 qcom,gmu = <&gmu_wrapper>; 1362 1363 nvmem-cells = <&gpu_speed_bin>; 1364 nvmem-cell-names = "speed_bin"; 1365 1366 status = "disabled"; 1367 1368 zap-shader { 1369 memory-region = <&pil_gpu_mem>; 1370 }; 1371 1372 gpu_opp_table: opp-table { 1373 compatible = "operating-points-v2"; 1374 1375 opp-320000000 { 1376 opp-hz = /bits/ 64 <320000000>; 1377 required-opps = <&rpmpd_opp_low_svs>; 1378 opp-supported-hw = <0x1f>; 1379 }; 1380 1381 opp-465000000 { 1382 opp-hz = /bits/ 64 <465000000>; 1383 required-opps = <&rpmpd_opp_svs>; 1384 opp-supported-hw = <0x1f>; 1385 }; 1386 1387 opp-600000000 { 1388 opp-hz = /bits/ 64 <600000000>; 1389 required-opps = <&rpmpd_opp_svs_plus>; 1390 opp-supported-hw = <0x1f>; 1391 }; 1392 1393 opp-745000000 { 1394 opp-hz = /bits/ 64 <745000000>; 1395 required-opps = <&rpmpd_opp_nom>; 1396 opp-supported-hw = <0xf>; 1397 }; 1398 1399 opp-820000000 { 1400 opp-hz = /bits/ 64 <820000000>; 1401 required-opps = <&rpmpd_opp_nom_plus>; 1402 opp-supported-hw = <0x7>; 1403 }; 1404 1405 opp-900000000 { 1406 opp-hz = /bits/ 64 <900000000>; 1407 required-opps = <&rpmpd_opp_turbo>; 1408 opp-supported-hw = <0x7>; 1409 }; 1410 1411 /* Speed bin 2 can reach 950 Mhz instead of 980 like the rest. */ 1412 opp-950000000 { 1413 opp-hz = /bits/ 64 <950000000>; 1414 required-opps = <&rpmpd_opp_turbo_plus>; 1415 opp-supported-hw = <0x4>; 1416 }; 1417 1418 opp-980000000 { 1419 opp-hz = /bits/ 64 <980000000>; 1420 required-opps = <&rpmpd_opp_turbo_plus>; 1421 opp-supported-hw = <0x3>; 1422 }; 1423 }; 1424 }; 1425 1426 gmu_wrapper: gmu@596a000 { 1427 compatible = "qcom,adreno-gmu-wrapper"; 1428 reg = <0x0 0x0596a000 0x0 0x30000>; 1429 reg-names = "gmu"; 1430 power-domains = <&gpucc GPU_CX_GDSC>, 1431 <&gpucc GPU_GX_GDSC>; 1432 power-domain-names = "cx", "gx"; 1433 }; 1434 1435 gpucc: clock-controller@5990000 { 1436 compatible = "qcom,sm6115-gpucc"; 1437 reg = <0x0 0x05990000 0x0 0x9000>; 1438 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 1439 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 1440 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 1441 #clock-cells = <1>; 1442 #reset-cells = <1>; 1443 #power-domain-cells = <1>; 1444 }; 1445 1446 adreno_smmu: iommu@59a0000 { 1447 compatible = "qcom,sm6115-smmu-500", "qcom,adreno-smmu", 1448 "qcom,smmu-500", "arm,mmu-500"; 1449 reg = <0x0 0x059a0000 0x0 0x10000>; 1450 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 1451 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 1452 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 1453 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 1454 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1455 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 1456 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, 1457 <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, 1458 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1459 1460 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1461 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 1462 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 1463 clock-names = "mem", 1464 "hlos", 1465 "iface"; 1466 power-domains = <&gpucc GPU_CX_GDSC>; 1467 1468 #global-interrupts = <1>; 1469 #iommu-cells = <2>; 1470 }; 1471 1472 mdss: display-subsystem@5e00000 { 1473 compatible = "qcom,sm6115-mdss"; 1474 reg = <0x0 0x05e00000 0x0 0x1000>; 1475 reg-names = "mdss"; 1476 1477 power-domains = <&dispcc MDSS_GDSC>; 1478 1479 clocks = <&gcc GCC_DISP_AHB_CLK>, 1480 <&gcc GCC_DISP_HF_AXI_CLK>, 1481 <&dispcc DISP_CC_MDSS_MDP_CLK>; 1482 1483 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 1484 interrupt-controller; 1485 #interrupt-cells = <1>; 1486 1487 iommus = <&apps_smmu 0x420 0x2>, 1488 <&apps_smmu 0x421 0x0>; 1489 1490 #address-cells = <2>; 1491 #size-cells = <2>; 1492 ranges; 1493 1494 status = "disabled"; 1495 1496 mdp: display-controller@5e01000 { 1497 compatible = "qcom,sm6115-dpu"; 1498 reg = <0x0 0x05e01000 0x0 0x8f000>, 1499 <0x0 0x05eb0000 0x0 0x2008>; 1500 reg-names = "mdp", "vbif"; 1501 1502 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 1503 <&dispcc DISP_CC_MDSS_AHB_CLK>, 1504 <&dispcc DISP_CC_MDSS_MDP_CLK>, 1505 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 1506 <&dispcc DISP_CC_MDSS_ROT_CLK>, 1507 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 1508 clock-names = "bus", 1509 "iface", 1510 "core", 1511 "lut", 1512 "rot", 1513 "vsync"; 1514 1515 operating-points-v2 = <&mdp_opp_table>; 1516 power-domains = <&rpmpd SM6115_VDDCX>; 1517 1518 interrupt-parent = <&mdss>; 1519 interrupts = <0>; 1520 1521 ports { 1522 #address-cells = <1>; 1523 #size-cells = <0>; 1524 1525 port@0 { 1526 reg = <0>; 1527 dpu_intf1_out: endpoint { 1528 remote-endpoint = <&mdss_dsi0_in>; 1529 }; 1530 }; 1531 }; 1532 1533 mdp_opp_table: opp-table { 1534 compatible = "operating-points-v2"; 1535 1536 opp-19200000 { 1537 opp-hz = /bits/ 64 <19200000>; 1538 required-opps = <&rpmpd_opp_min_svs>; 1539 }; 1540 1541 opp-192000000 { 1542 opp-hz = /bits/ 64 <192000000>; 1543 required-opps = <&rpmpd_opp_low_svs>; 1544 }; 1545 1546 opp-256000000 { 1547 opp-hz = /bits/ 64 <256000000>; 1548 required-opps = <&rpmpd_opp_svs>; 1549 }; 1550 1551 opp-307200000 { 1552 opp-hz = /bits/ 64 <307200000>; 1553 required-opps = <&rpmpd_opp_svs_plus>; 1554 }; 1555 1556 opp-384000000 { 1557 opp-hz = /bits/ 64 <384000000>; 1558 required-opps = <&rpmpd_opp_nom>; 1559 }; 1560 }; 1561 }; 1562 1563 mdss_dsi0: dsi@5e94000 { 1564 compatible = "qcom,sm6115-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 1565 reg = <0x0 0x05e94000 0x0 0x400>; 1566 reg-names = "dsi_ctrl"; 1567 1568 interrupt-parent = <&mdss>; 1569 interrupts = <4>; 1570 1571 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 1572 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 1573 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 1574 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 1575 <&dispcc DISP_CC_MDSS_AHB_CLK>, 1576 <&gcc GCC_DISP_HF_AXI_CLK>; 1577 clock-names = "byte", 1578 "byte_intf", 1579 "pixel", 1580 "core", 1581 "iface", 1582 "bus"; 1583 1584 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 1585 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 1586 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; 1587 1588 operating-points-v2 = <&dsi_opp_table>; 1589 power-domains = <&rpmpd SM6115_VDDCX>; 1590 phys = <&mdss_dsi0_phy>; 1591 1592 #address-cells = <1>; 1593 #size-cells = <0>; 1594 1595 status = "disabled"; 1596 1597 ports { 1598 #address-cells = <1>; 1599 #size-cells = <0>; 1600 1601 port@0 { 1602 reg = <0>; 1603 mdss_dsi0_in: endpoint { 1604 remote-endpoint = <&dpu_intf1_out>; 1605 }; 1606 }; 1607 1608 port@1 { 1609 reg = <1>; 1610 mdss_dsi0_out: endpoint { 1611 }; 1612 }; 1613 }; 1614 1615 dsi_opp_table: opp-table { 1616 compatible = "operating-points-v2"; 1617 1618 opp-19200000 { 1619 opp-hz = /bits/ 64 <19200000>; 1620 required-opps = <&rpmpd_opp_min_svs>; 1621 }; 1622 1623 opp-164000000 { 1624 opp-hz = /bits/ 64 <164000000>; 1625 required-opps = <&rpmpd_opp_low_svs>; 1626 }; 1627 1628 opp-187500000 { 1629 opp-hz = /bits/ 64 <187500000>; 1630 required-opps = <&rpmpd_opp_svs>; 1631 }; 1632 }; 1633 }; 1634 1635 mdss_dsi0_phy: phy@5e94400 { 1636 compatible = "qcom,dsi-phy-14nm-2290"; 1637 reg = <0x0 0x05e94400 0x0 0x100>, 1638 <0x0 0x05e94500 0x0 0x300>, 1639 <0x0 0x05e94800 0x0 0x188>; 1640 reg-names = "dsi_phy", 1641 "dsi_phy_lane", 1642 "dsi_pll"; 1643 1644 #clock-cells = <1>; 1645 #phy-cells = <0>; 1646 1647 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 1648 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1649 clock-names = "iface", "ref"; 1650 1651 status = "disabled"; 1652 }; 1653 }; 1654 1655 dispcc: clock-controller@5f00000 { 1656 compatible = "qcom,sm6115-dispcc"; 1657 reg = <0x0 0x05f00000 0 0x20000>; 1658 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 1659 <&sleep_clk>, 1660 <&mdss_dsi0_phy 0>, 1661 <&mdss_dsi0_phy 1>, 1662 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>; 1663 #clock-cells = <1>; 1664 #reset-cells = <1>; 1665 #power-domain-cells = <1>; 1666 }; 1667 1668 remoteproc_mpss: remoteproc@6080000 { 1669 compatible = "qcom,sm6115-mpss-pas"; 1670 reg = <0x0 0x06080000 0x0 0x100>; 1671 1672 interrupts-extended = <&intc GIC_SPI 307 IRQ_TYPE_EDGE_RISING>, 1673 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1674 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1675 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1676 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 1677 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 1678 interrupt-names = "wdog", "fatal", "ready", "handover", 1679 "stop-ack", "shutdown-ack"; 1680 1681 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 1682 clock-names = "xo"; 1683 1684 power-domains = <&rpmpd SM6115_VDDCX>; 1685 1686 memory-region = <&pil_modem_mem>; 1687 1688 qcom,smem-states = <&modem_smp2p_out 0>; 1689 qcom,smem-state-names = "stop"; 1690 1691 status = "disabled"; 1692 1693 glink-edge { 1694 interrupts = <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>; 1695 label = "mpss"; 1696 qcom,remote-pid = <1>; 1697 mboxes = <&apcs_glb 12>; 1698 }; 1699 }; 1700 1701 stm@8002000 { 1702 compatible = "arm,coresight-stm", "arm,primecell"; 1703 reg = <0x0 0x08002000 0x0 0x1000>, 1704 <0x0 0x0e280000 0x0 0x180000>; 1705 reg-names = "stm-base", "stm-stimulus-base"; 1706 1707 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1708 clock-names = "apb_pclk"; 1709 1710 status = "disabled"; 1711 1712 out-ports { 1713 port { 1714 stm_out: endpoint { 1715 remote-endpoint = <&funnel_in0_in>; 1716 }; 1717 }; 1718 }; 1719 }; 1720 1721 cti0: cti@8010000 { 1722 compatible = "arm,coresight-cti", "arm,primecell"; 1723 reg = <0x0 0x08010000 0x0 0x1000>; 1724 1725 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1726 clock-names = "apb_pclk"; 1727 1728 status = "disabled"; 1729 }; 1730 1731 cti1: cti@8011000 { 1732 compatible = "arm,coresight-cti", "arm,primecell"; 1733 reg = <0x0 0x08011000 0x0 0x1000>; 1734 1735 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1736 clock-names = "apb_pclk"; 1737 1738 status = "disabled"; 1739 }; 1740 1741 cti2: cti@8012000 { 1742 compatible = "arm,coresight-cti", "arm,primecell"; 1743 reg = <0x0 0x08012000 0x0 0x1000>; 1744 1745 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1746 clock-names = "apb_pclk"; 1747 1748 status = "disabled"; 1749 }; 1750 1751 cti3: cti@8013000 { 1752 compatible = "arm,coresight-cti", "arm,primecell"; 1753 reg = <0x0 0x08013000 0x0 0x1000>; 1754 1755 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1756 clock-names = "apb_pclk"; 1757 1758 status = "disabled"; 1759 }; 1760 1761 cti4: cti@8014000 { 1762 compatible = "arm,coresight-cti", "arm,primecell"; 1763 reg = <0x0 0x08014000 0x0 0x1000>; 1764 1765 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1766 clock-names = "apb_pclk"; 1767 1768 status = "disabled"; 1769 }; 1770 1771 cti5: cti@8015000 { 1772 compatible = "arm,coresight-cti", "arm,primecell"; 1773 reg = <0x0 0x08015000 0x0 0x1000>; 1774 1775 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1776 clock-names = "apb_pclk"; 1777 1778 status = "disabled"; 1779 }; 1780 1781 cti6: cti@8016000 { 1782 compatible = "arm,coresight-cti", "arm,primecell"; 1783 reg = <0x0 0x08016000 0x0 0x1000>; 1784 1785 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1786 clock-names = "apb_pclk"; 1787 1788 status = "disabled"; 1789 }; 1790 1791 cti7: cti@8017000 { 1792 compatible = "arm,coresight-cti", "arm,primecell"; 1793 reg = <0x0 0x08017000 0x0 0x1000>; 1794 1795 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1796 clock-names = "apb_pclk"; 1797 1798 status = "disabled"; 1799 }; 1800 1801 cti8: cti@8018000 { 1802 compatible = "arm,coresight-cti", "arm,primecell"; 1803 reg = <0x0 0x08018000 0x0 0x1000>; 1804 1805 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1806 clock-names = "apb_pclk"; 1807 1808 status = "disabled"; 1809 }; 1810 1811 cti9: cti@8019000 { 1812 compatible = "arm,coresight-cti", "arm,primecell"; 1813 reg = <0x0 0x08019000 0x0 0x1000>; 1814 1815 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1816 clock-names = "apb_pclk"; 1817 1818 status = "disabled"; 1819 }; 1820 1821 cti10: cti@801a000 { 1822 compatible = "arm,coresight-cti", "arm,primecell"; 1823 reg = <0x0 0x0801a000 0x0 0x1000>; 1824 1825 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1826 clock-names = "apb_pclk"; 1827 1828 status = "disabled"; 1829 }; 1830 1831 cti11: cti@801b000 { 1832 compatible = "arm,coresight-cti", "arm,primecell"; 1833 reg = <0x0 0x0801b000 0x0 0x1000>; 1834 1835 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1836 clock-names = "apb_pclk"; 1837 1838 status = "disabled"; 1839 }; 1840 1841 cti12: cti@801c000 { 1842 compatible = "arm,coresight-cti", "arm,primecell"; 1843 reg = <0x0 0x0801c000 0x0 0x1000>; 1844 1845 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1846 clock-names = "apb_pclk"; 1847 1848 status = "disabled"; 1849 }; 1850 1851 cti13: cti@801d000 { 1852 compatible = "arm,coresight-cti", "arm,primecell"; 1853 reg = <0x0 0x0801d000 0x0 0x1000>; 1854 1855 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1856 clock-names = "apb_pclk"; 1857 1858 status = "disabled"; 1859 }; 1860 1861 cti14: cti@801e000 { 1862 compatible = "arm,coresight-cti", "arm,primecell"; 1863 reg = <0x0 0x0801e000 0x0 0x1000>; 1864 1865 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1866 clock-names = "apb_pclk"; 1867 1868 status = "disabled"; 1869 }; 1870 1871 cti15: cti@801f000 { 1872 compatible = "arm,coresight-cti", "arm,primecell"; 1873 reg = <0x0 0x0801f000 0x0 0x1000>; 1874 1875 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1876 clock-names = "apb_pclk"; 1877 1878 status = "disabled"; 1879 }; 1880 1881 replicator@8046000 { 1882 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 1883 reg = <0x0 0x08046000 0x0 0x1000>; 1884 1885 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1886 clock-names = "apb_pclk"; 1887 1888 status = "disabled"; 1889 1890 out-ports { 1891 port { 1892 replicator_out: endpoint { 1893 remote-endpoint = <&etr_in>; 1894 }; 1895 }; 1896 }; 1897 1898 in-ports { 1899 port { 1900 replicator_in: endpoint { 1901 remote-endpoint = <&etf_out>; 1902 }; 1903 }; 1904 }; 1905 }; 1906 1907 etf@8047000 { 1908 compatible = "arm,coresight-tmc", "arm,primecell"; 1909 reg = <0x0 0x08047000 0x0 0x1000>; 1910 1911 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1912 clock-names = "apb_pclk"; 1913 1914 status = "disabled"; 1915 1916 in-ports { 1917 port { 1918 etf_in: endpoint { 1919 remote-endpoint = <&merge_funnel_out>; 1920 }; 1921 }; 1922 }; 1923 1924 out-ports { 1925 port { 1926 etf_out: endpoint { 1927 remote-endpoint = <&replicator_in>; 1928 }; 1929 }; 1930 }; 1931 }; 1932 1933 etr@8048000 { 1934 compatible = "arm,coresight-tmc", "arm,primecell"; 1935 reg = <0x0 0x08048000 0x0 0x1000>; 1936 1937 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1938 clock-names = "apb_pclk"; 1939 1940 status = "disabled"; 1941 1942 in-ports { 1943 port { 1944 etr_in: endpoint { 1945 remote-endpoint = <&replicator_out>; 1946 }; 1947 }; 1948 }; 1949 }; 1950 1951 funnel@8041000 { 1952 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1953 reg = <0x0 0x08041000 0x0 0x1000>; 1954 1955 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1956 clock-names = "apb_pclk"; 1957 1958 status = "disabled"; 1959 1960 out-ports { 1961 port { 1962 funnel_in0_out: endpoint { 1963 remote-endpoint = <&merge_funnel_in0>; 1964 }; 1965 }; 1966 }; 1967 1968 in-ports { 1969 port { 1970 funnel_in0_in: endpoint { 1971 remote-endpoint = <&stm_out>; 1972 }; 1973 }; 1974 }; 1975 }; 1976 1977 funnel@8042000 { 1978 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1979 reg = <0x0 0x08042000 0x0 0x1000>; 1980 1981 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1982 clock-names = "apb_pclk"; 1983 1984 status = "disabled"; 1985 1986 out-ports { 1987 port { 1988 funnel_in1_out: endpoint { 1989 remote-endpoint = <&merge_funnel_in1>; 1990 }; 1991 }; 1992 }; 1993 1994 in-ports { 1995 port { 1996 funnel_in1_in: endpoint { 1997 remote-endpoint = <&funnel_apss1_out>; 1998 }; 1999 }; 2000 }; 2001 }; 2002 2003 funnel@8045000 { 2004 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2005 reg = <0x0 0x08045000 0x0 0x1000>; 2006 2007 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2008 clock-names = "apb_pclk"; 2009 2010 status = "disabled"; 2011 2012 out-ports { 2013 port { 2014 merge_funnel_out: endpoint { 2015 remote-endpoint = <&etf_in>; 2016 }; 2017 }; 2018 }; 2019 2020 in-ports { 2021 #address-cells = <1>; 2022 #size-cells = <0>; 2023 2024 port@0 { 2025 reg = <0>; 2026 merge_funnel_in0: endpoint { 2027 remote-endpoint = <&funnel_in0_out>; 2028 }; 2029 }; 2030 2031 port@1 { 2032 reg = <1>; 2033 merge_funnel_in1: endpoint { 2034 remote-endpoint = <&funnel_in1_out>; 2035 }; 2036 }; 2037 }; 2038 }; 2039 2040 etm@9040000 { 2041 compatible = "arm,coresight-etm4x", "arm,primecell"; 2042 reg = <0x0 0x09040000 0x0 0x1000>; 2043 2044 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2045 clock-names = "apb_pclk"; 2046 arm,coresight-loses-context-with-cpu; 2047 2048 cpu = <&CPU0>; 2049 2050 status = "disabled"; 2051 2052 out-ports { 2053 port { 2054 etm0_out: endpoint { 2055 remote-endpoint = <&funnel_apss0_in0>; 2056 }; 2057 }; 2058 }; 2059 }; 2060 2061 etm@9140000 { 2062 compatible = "arm,coresight-etm4x", "arm,primecell"; 2063 reg = <0x0 0x09140000 0x0 0x1000>; 2064 2065 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2066 clock-names = "apb_pclk"; 2067 arm,coresight-loses-context-with-cpu; 2068 2069 cpu = <&CPU1>; 2070 2071 status = "disabled"; 2072 2073 out-ports { 2074 port { 2075 etm1_out: endpoint { 2076 remote-endpoint = <&funnel_apss0_in1>; 2077 }; 2078 }; 2079 }; 2080 }; 2081 2082 etm@9240000 { 2083 compatible = "arm,coresight-etm4x", "arm,primecell"; 2084 reg = <0x0 0x09240000 0x0 0x1000>; 2085 2086 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2087 clock-names = "apb_pclk"; 2088 arm,coresight-loses-context-with-cpu; 2089 2090 cpu = <&CPU2>; 2091 2092 status = "disabled"; 2093 2094 out-ports { 2095 port { 2096 etm2_out: endpoint { 2097 remote-endpoint = <&funnel_apss0_in2>; 2098 }; 2099 }; 2100 }; 2101 }; 2102 2103 etm@9340000 { 2104 compatible = "arm,coresight-etm4x", "arm,primecell"; 2105 reg = <0x0 0x09340000 0x0 0x1000>; 2106 2107 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2108 clock-names = "apb_pclk"; 2109 arm,coresight-loses-context-with-cpu; 2110 2111 cpu = <&CPU3>; 2112 2113 status = "disabled"; 2114 2115 out-ports { 2116 port { 2117 etm3_out: endpoint { 2118 remote-endpoint = <&funnel_apss0_in3>; 2119 }; 2120 }; 2121 }; 2122 }; 2123 2124 etm@9440000 { 2125 compatible = "arm,coresight-etm4x", "arm,primecell"; 2126 reg = <0x0 0x09440000 0x0 0x1000>; 2127 2128 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2129 clock-names = "apb_pclk"; 2130 arm,coresight-loses-context-with-cpu; 2131 2132 cpu = <&CPU4>; 2133 2134 status = "disabled"; 2135 2136 out-ports { 2137 port { 2138 etm4_out: endpoint { 2139 remote-endpoint = <&funnel_apss0_in4>; 2140 }; 2141 }; 2142 }; 2143 }; 2144 2145 etm@9540000 { 2146 compatible = "arm,coresight-etm4x", "arm,primecell"; 2147 reg = <0x0 0x09540000 0x0 0x1000>; 2148 2149 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2150 clock-names = "apb_pclk"; 2151 arm,coresight-loses-context-with-cpu; 2152 2153 cpu = <&CPU5>; 2154 2155 status = "disabled"; 2156 2157 out-ports { 2158 port { 2159 etm5_out: endpoint { 2160 remote-endpoint = <&funnel_apss0_in5>; 2161 }; 2162 }; 2163 }; 2164 }; 2165 2166 etm@9640000 { 2167 compatible = "arm,coresight-etm4x", "arm,primecell"; 2168 reg = <0x0 0x09640000 0x0 0x1000>; 2169 2170 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2171 clock-names = "apb_pclk"; 2172 arm,coresight-loses-context-with-cpu; 2173 2174 cpu = <&CPU6>; 2175 2176 status = "disabled"; 2177 2178 out-ports { 2179 port { 2180 etm6_out: endpoint { 2181 remote-endpoint = <&funnel_apss0_in6>; 2182 }; 2183 }; 2184 }; 2185 }; 2186 2187 etm@9740000 { 2188 compatible = "arm,coresight-etm4x", "arm,primecell"; 2189 reg = <0x0 0x09740000 0x0 0x1000>; 2190 2191 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2192 clock-names = "apb_pclk"; 2193 arm,coresight-loses-context-with-cpu; 2194 2195 cpu = <&CPU7>; 2196 2197 status = "disabled"; 2198 2199 out-ports { 2200 port { 2201 etm7_out: endpoint { 2202 remote-endpoint = <&funnel_apss0_in7>; 2203 }; 2204 }; 2205 }; 2206 }; 2207 2208 funnel@9800000 { 2209 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2210 reg = <0x0 0x09800000 0x0 0x1000>; 2211 2212 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2213 clock-names = "apb_pclk"; 2214 2215 status = "disabled"; 2216 2217 out-ports { 2218 port { 2219 funnel_apss0_out: endpoint { 2220 remote-endpoint = <&funnel_apss1_in>; 2221 }; 2222 }; 2223 }; 2224 2225 in-ports { 2226 #address-cells = <1>; 2227 #size-cells = <0>; 2228 2229 port@0 { 2230 reg = <0>; 2231 funnel_apss0_in0: endpoint { 2232 remote-endpoint = <&etm0_out>; 2233 }; 2234 }; 2235 2236 port@1 { 2237 reg = <1>; 2238 funnel_apss0_in1: endpoint { 2239 remote-endpoint = <&etm1_out>; 2240 }; 2241 }; 2242 2243 port@2 { 2244 reg = <2>; 2245 funnel_apss0_in2: endpoint { 2246 remote-endpoint = <&etm2_out>; 2247 }; 2248 }; 2249 2250 port@3 { 2251 reg = <3>; 2252 funnel_apss0_in3: endpoint { 2253 remote-endpoint = <&etm3_out>; 2254 }; 2255 }; 2256 2257 port@4 { 2258 reg = <4>; 2259 funnel_apss0_in4: endpoint { 2260 remote-endpoint = <&etm4_out>; 2261 }; 2262 }; 2263 2264 port@5 { 2265 reg = <5>; 2266 funnel_apss0_in5: endpoint { 2267 remote-endpoint = <&etm5_out>; 2268 }; 2269 }; 2270 2271 port@6 { 2272 reg = <6>; 2273 funnel_apss0_in6: endpoint { 2274 remote-endpoint = <&etm6_out>; 2275 }; 2276 }; 2277 2278 port@7 { 2279 reg = <7>; 2280 funnel_apss0_in7: endpoint { 2281 remote-endpoint = <&etm7_out>; 2282 }; 2283 }; 2284 }; 2285 }; 2286 2287 funnel@9810000 { 2288 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2289 reg = <0x0 0x09810000 0x0 0x1000>; 2290 2291 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2292 clock-names = "apb_pclk"; 2293 2294 status = "disabled"; 2295 2296 out-ports { 2297 port { 2298 funnel_apss1_out: endpoint { 2299 remote-endpoint = <&funnel_in1_in>; 2300 }; 2301 }; 2302 }; 2303 2304 in-ports { 2305 port { 2306 funnel_apss1_in: endpoint { 2307 remote-endpoint = <&funnel_apss0_out>; 2308 }; 2309 }; 2310 }; 2311 }; 2312 2313 remoteproc_adsp: remoteproc@ab00000 { 2314 compatible = "qcom,sm6115-adsp-pas"; 2315 reg = <0x0 0x0ab00000 0x0 0x100>; 2316 2317 interrupts-extended = <&intc GIC_SPI 282 IRQ_TYPE_EDGE_RISING>, 2318 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2319 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2320 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2321 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2322 interrupt-names = "wdog", "fatal", "ready", 2323 "handover", "stop-ack"; 2324 2325 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 2326 clock-names = "xo"; 2327 2328 power-domains = <&rpmpd SM6115_VDD_LPI_CX>, 2329 <&rpmpd SM6115_VDD_LPI_MX>; 2330 2331 memory-region = <&pil_adsp_mem>; 2332 2333 qcom,smem-states = <&adsp_smp2p_out 0>; 2334 qcom,smem-state-names = "stop"; 2335 2336 status = "disabled"; 2337 2338 glink-edge { 2339 interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>; 2340 label = "lpass"; 2341 qcom,remote-pid = <2>; 2342 mboxes = <&apcs_glb 8>; 2343 2344 fastrpc { 2345 compatible = "qcom,fastrpc"; 2346 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2347 label = "adsp"; 2348 qcom,non-secure-domain; 2349 #address-cells = <1>; 2350 #size-cells = <0>; 2351 2352 compute-cb@3 { 2353 compatible = "qcom,fastrpc-compute-cb"; 2354 reg = <3>; 2355 iommus = <&apps_smmu 0x01c3 0x0>; 2356 }; 2357 2358 compute-cb@4 { 2359 compatible = "qcom,fastrpc-compute-cb"; 2360 reg = <4>; 2361 iommus = <&apps_smmu 0x01c4 0x0>; 2362 }; 2363 2364 compute-cb@5 { 2365 compatible = "qcom,fastrpc-compute-cb"; 2366 reg = <5>; 2367 iommus = <&apps_smmu 0x01c5 0x0>; 2368 }; 2369 2370 compute-cb@6 { 2371 compatible = "qcom,fastrpc-compute-cb"; 2372 reg = <6>; 2373 iommus = <&apps_smmu 0x01c6 0x0>; 2374 }; 2375 2376 compute-cb@7 { 2377 compatible = "qcom,fastrpc-compute-cb"; 2378 reg = <7>; 2379 iommus = <&apps_smmu 0x01c7 0x0>; 2380 }; 2381 }; 2382 }; 2383 }; 2384 2385 remoteproc_cdsp: remoteproc@b300000 { 2386 compatible = "qcom,sm6115-cdsp-pas"; 2387 reg = <0x0 0x0b300000 0x0 0x100000>; 2388 2389 interrupts-extended = <&intc GIC_SPI 265 IRQ_TYPE_EDGE_RISING>, 2390 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2391 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2392 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2393 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2394 interrupt-names = "wdog", "fatal", "ready", 2395 "handover", "stop-ack"; 2396 2397 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 2398 clock-names = "xo"; 2399 2400 power-domains = <&rpmpd SM6115_VDDCX>; 2401 2402 memory-region = <&pil_cdsp_mem>; 2403 2404 qcom,smem-states = <&cdsp_smp2p_out 0>; 2405 qcom,smem-state-names = "stop"; 2406 2407 status = "disabled"; 2408 2409 glink-edge { 2410 interrupts = <GIC_SPI 261 IRQ_TYPE_EDGE_RISING>; 2411 label = "cdsp"; 2412 qcom,remote-pid = <5>; 2413 mboxes = <&apcs_glb 28>; 2414 2415 fastrpc { 2416 compatible = "qcom,fastrpc"; 2417 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2418 label = "cdsp"; 2419 qcom,non-secure-domain; 2420 #address-cells = <1>; 2421 #size-cells = <0>; 2422 2423 compute-cb@1 { 2424 compatible = "qcom,fastrpc-compute-cb"; 2425 reg = <1>; 2426 iommus = <&apps_smmu 0x0c01 0x0>; 2427 }; 2428 2429 compute-cb@2 { 2430 compatible = "qcom,fastrpc-compute-cb"; 2431 reg = <2>; 2432 iommus = <&apps_smmu 0x0c02 0x0>; 2433 }; 2434 2435 compute-cb@3 { 2436 compatible = "qcom,fastrpc-compute-cb"; 2437 reg = <3>; 2438 iommus = <&apps_smmu 0x0c03 0x0>; 2439 }; 2440 2441 compute-cb@4 { 2442 compatible = "qcom,fastrpc-compute-cb"; 2443 reg = <4>; 2444 iommus = <&apps_smmu 0x0c04 0x0>; 2445 }; 2446 2447 compute-cb@5 { 2448 compatible = "qcom,fastrpc-compute-cb"; 2449 reg = <5>; 2450 iommus = <&apps_smmu 0x0c05 0x0>; 2451 }; 2452 2453 compute-cb@6 { 2454 compatible = "qcom,fastrpc-compute-cb"; 2455 reg = <6>; 2456 iommus = <&apps_smmu 0x0c06 0x0>; 2457 }; 2458 2459 /* note: secure cb9 in downstream */ 2460 }; 2461 }; 2462 }; 2463 2464 apps_smmu: iommu@c600000 { 2465 compatible = "qcom,sm6115-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 2466 reg = <0x0 0x0c600000 0x0 0x80000>; 2467 #iommu-cells = <2>; 2468 #global-interrupts = <1>; 2469 2470 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 2471 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 2472 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 2473 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 2474 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 2475 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 2476 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 2477 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 2478 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 2479 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 2480 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 2481 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 2482 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 2483 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 2484 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 2485 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 2486 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 2487 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 2488 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 2489 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 2490 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 2491 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 2492 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 2493 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 2494 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 2495 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 2496 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 2497 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 2498 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 2499 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 2500 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 2501 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 2502 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 2503 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 2504 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 2505 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 2506 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 2507 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 2508 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 2509 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 2510 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 2511 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 2512 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 2513 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 2514 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 2515 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 2516 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 2517 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 2518 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 2519 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 2520 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 2521 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 2522 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 2523 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 2524 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 2525 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 2526 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 2527 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 2528 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 2529 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 2530 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 2531 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 2532 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 2533 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 2534 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 2535 }; 2536 2537 wifi: wifi@c800000 { 2538 compatible = "qcom,wcn3990-wifi"; 2539 reg = <0x0 0x0c800000 0x0 0x800000>; 2540 reg-names = "membase"; 2541 memory-region = <&wlan_msa_mem>; 2542 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, 2543 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, 2544 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, 2545 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>, 2546 <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>, 2547 <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>, 2548 <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>, 2549 <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>, 2550 <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>, 2551 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>, 2552 <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, 2553 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 2554 iommus = <&apps_smmu 0x1a0 0x1>; 2555 qcom,msa-fixed-perm; 2556 status = "disabled"; 2557 }; 2558 2559 watchdog@f017000 { 2560 compatible = "qcom,apss-wdt-sm6115", "qcom,kpss-wdt"; 2561 reg = <0x0 0x0f017000 0x0 0x1000>; 2562 clocks = <&sleep_clk>; 2563 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 2564 }; 2565 2566 apcs_glb: mailbox@f111000 { 2567 compatible = "qcom,sm6115-apcs-hmss-global", 2568 "qcom,msm8994-apcs-kpss-global"; 2569 reg = <0x0 0x0f111000 0x0 0x1000>; 2570 2571 #mbox-cells = <1>; 2572 }; 2573 2574 timer@f120000 { 2575 compatible = "arm,armv7-timer-mem"; 2576 reg = <0x0 0x0f120000 0x0 0x1000>; 2577 #address-cells = <2>; 2578 #size-cells = <2>; 2579 ranges; 2580 clock-frequency = <19200000>; 2581 2582 frame@f121000 { 2583 reg = <0x0 0x0f121000 0x0 0x1000>, <0x0 0x0f122000 0x0 0x1000>; 2584 frame-number = <0>; 2585 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 2586 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 2587 }; 2588 2589 frame@f123000 { 2590 reg = <0x0 0x0f123000 0x0 0x1000>; 2591 frame-number = <1>; 2592 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 2593 status = "disabled"; 2594 }; 2595 2596 frame@f124000 { 2597 reg = <0x0 0x0f124000 0x0 0x1000>; 2598 frame-number = <2>; 2599 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 2600 status = "disabled"; 2601 }; 2602 2603 frame@f125000 { 2604 reg = <0x0 0x0f125000 0x0 0x1000>; 2605 frame-number = <3>; 2606 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 2607 status = "disabled"; 2608 }; 2609 2610 frame@f126000 { 2611 reg = <0x0 0x0f126000 0x0 0x1000>; 2612 frame-number = <4>; 2613 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 2614 status = "disabled"; 2615 }; 2616 2617 frame@f127000 { 2618 reg = <0x0 0x0f127000 0x0 0x1000>; 2619 frame-number = <5>; 2620 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 2621 status = "disabled"; 2622 }; 2623 2624 frame@f128000 { 2625 reg = <0x0 0x0f128000 0x0 0x1000>; 2626 frame-number = <6>; 2627 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 2628 status = "disabled"; 2629 }; 2630 }; 2631 2632 intc: interrupt-controller@f200000 { 2633 compatible = "arm,gic-v3"; 2634 reg = <0x0 0x0f200000 0x0 0x10000>, 2635 <0x0 0x0f300000 0x0 0x100000>; 2636 #interrupt-cells = <3>; 2637 interrupt-controller; 2638 interrupt-parent = <&intc>; 2639 #redistributor-regions = <1>; 2640 redistributor-stride = <0x0 0x20000>; 2641 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 2642 }; 2643 2644 cpufreq_hw: cpufreq@f521000 { 2645 compatible = "qcom,sm6115-cpufreq-hw", "qcom,cpufreq-hw"; 2646 reg = <0x0 0x0f521000 0x0 0x1000>, 2647 <0x0 0x0f523000 0x0 0x1000>; 2648 2649 reg-names = "freq-domain0", "freq-domain1"; 2650 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>; 2651 clock-names = "xo", "alternate"; 2652 2653 #freq-domain-cells = <1>; 2654 #clock-cells = <1>; 2655 }; 2656 }; 2657 2658 thermal-zones { 2659 mapss-thermal { 2660 polling-delay-passive = <0>; 2661 polling-delay = <0>; 2662 thermal-sensors = <&tsens0 0>; 2663 2664 trips { 2665 trip-point0 { 2666 temperature = <115000>; 2667 hysteresis = <5000>; 2668 type = "passive"; 2669 }; 2670 2671 trip-point1 { 2672 temperature = <125000>; 2673 hysteresis = <1000>; 2674 type = "passive"; 2675 }; 2676 }; 2677 }; 2678 2679 cdsp-hvx-thermal { 2680 polling-delay-passive = <0>; 2681 polling-delay = <0>; 2682 thermal-sensors = <&tsens0 1>; 2683 2684 trips { 2685 trip-point0 { 2686 temperature = <115000>; 2687 hysteresis = <5000>; 2688 type = "passive"; 2689 }; 2690 2691 trip-point1 { 2692 temperature = <125000>; 2693 hysteresis = <1000>; 2694 type = "passive"; 2695 }; 2696 }; 2697 }; 2698 2699 wlan-thermal { 2700 polling-delay-passive = <0>; 2701 polling-delay = <0>; 2702 thermal-sensors = <&tsens0 2>; 2703 2704 trips { 2705 trip-point0 { 2706 temperature = <115000>; 2707 hysteresis = <5000>; 2708 type = "passive"; 2709 }; 2710 2711 trip-point1 { 2712 temperature = <125000>; 2713 hysteresis = <1000>; 2714 type = "passive"; 2715 }; 2716 }; 2717 }; 2718 2719 camera-thermal { 2720 polling-delay-passive = <0>; 2721 polling-delay = <0>; 2722 thermal-sensors = <&tsens0 3>; 2723 2724 trips { 2725 trip-point0 { 2726 temperature = <115000>; 2727 hysteresis = <5000>; 2728 type = "passive"; 2729 }; 2730 2731 trip-point1 { 2732 temperature = <125000>; 2733 hysteresis = <1000>; 2734 type = "passive"; 2735 }; 2736 }; 2737 }; 2738 2739 video-thermal { 2740 polling-delay-passive = <0>; 2741 polling-delay = <0>; 2742 thermal-sensors = <&tsens0 4>; 2743 2744 trips { 2745 trip-point0 { 2746 temperature = <115000>; 2747 hysteresis = <5000>; 2748 type = "passive"; 2749 }; 2750 2751 trip-point1 { 2752 temperature = <125000>; 2753 hysteresis = <1000>; 2754 type = "passive"; 2755 }; 2756 }; 2757 }; 2758 2759 modem1-thermal { 2760 polling-delay-passive = <0>; 2761 polling-delay = <0>; 2762 thermal-sensors = <&tsens0 5>; 2763 2764 trips { 2765 trip-point0 { 2766 temperature = <115000>; 2767 hysteresis = <5000>; 2768 type = "passive"; 2769 }; 2770 2771 trip-point1 { 2772 temperature = <125000>; 2773 hysteresis = <1000>; 2774 type = "passive"; 2775 }; 2776 }; 2777 }; 2778 2779 cpu4-thermal { 2780 polling-delay-passive = <0>; 2781 polling-delay = <0>; 2782 thermal-sensors = <&tsens0 6>; 2783 2784 trips { 2785 cpu4_alert0: trip-point0 { 2786 temperature = <90000>; 2787 hysteresis = <2000>; 2788 type = "passive"; 2789 }; 2790 2791 cpu4_alert1: trip-point1 { 2792 temperature = <95000>; 2793 hysteresis = <2000>; 2794 type = "passive"; 2795 }; 2796 2797 cpu4_crit: cpu_crit { 2798 temperature = <110000>; 2799 hysteresis = <1000>; 2800 type = "critical"; 2801 }; 2802 }; 2803 }; 2804 2805 cpu5-thermal { 2806 polling-delay-passive = <0>; 2807 polling-delay = <0>; 2808 thermal-sensors = <&tsens0 7>; 2809 2810 trips { 2811 cpu5_alert0: trip-point0 { 2812 temperature = <90000>; 2813 hysteresis = <2000>; 2814 type = "passive"; 2815 }; 2816 2817 cpu5_alert1: trip-point1 { 2818 temperature = <95000>; 2819 hysteresis = <2000>; 2820 type = "passive"; 2821 }; 2822 2823 cpu5_crit: cpu_crit { 2824 temperature = <110000>; 2825 hysteresis = <1000>; 2826 type = "critical"; 2827 }; 2828 }; 2829 }; 2830 2831 cpu6-thermal { 2832 polling-delay-passive = <0>; 2833 polling-delay = <0>; 2834 thermal-sensors = <&tsens0 8>; 2835 2836 trips { 2837 cpu6_alert0: trip-point0 { 2838 temperature = <90000>; 2839 hysteresis = <2000>; 2840 type = "passive"; 2841 }; 2842 2843 cpu6_alert1: trip-point1 { 2844 temperature = <95000>; 2845 hysteresis = <2000>; 2846 type = "passive"; 2847 }; 2848 2849 cpu6_crit: cpu_crit { 2850 temperature = <110000>; 2851 hysteresis = <1000>; 2852 type = "critical"; 2853 }; 2854 }; 2855 }; 2856 2857 cpu7-thermal { 2858 polling-delay-passive = <0>; 2859 polling-delay = <0>; 2860 thermal-sensors = <&tsens0 9>; 2861 2862 trips { 2863 cpu7_alert0: trip-point0 { 2864 temperature = <90000>; 2865 hysteresis = <2000>; 2866 type = "passive"; 2867 }; 2868 2869 cpu7_alert1: trip-point1 { 2870 temperature = <95000>; 2871 hysteresis = <2000>; 2872 type = "passive"; 2873 }; 2874 2875 cpu7_crit: cpu_crit { 2876 temperature = <110000>; 2877 hysteresis = <1000>; 2878 type = "critical"; 2879 }; 2880 }; 2881 }; 2882 2883 cpu45-thermal { 2884 polling-delay-passive = <0>; 2885 polling-delay = <0>; 2886 thermal-sensors = <&tsens0 10>; 2887 2888 trips { 2889 cpu45_alert0: trip-point0 { 2890 temperature = <90000>; 2891 hysteresis = <2000>; 2892 type = "passive"; 2893 }; 2894 2895 cpu45_alert1: trip-point1 { 2896 temperature = <95000>; 2897 hysteresis = <2000>; 2898 type = "passive"; 2899 }; 2900 2901 cpu45_crit: cpu_crit { 2902 temperature = <110000>; 2903 hysteresis = <1000>; 2904 type = "critical"; 2905 }; 2906 }; 2907 }; 2908 2909 cpu67-thermal { 2910 polling-delay-passive = <0>; 2911 polling-delay = <0>; 2912 thermal-sensors = <&tsens0 11>; 2913 2914 trips { 2915 cpu67_alert0: trip-point0 { 2916 temperature = <90000>; 2917 hysteresis = <2000>; 2918 type = "passive"; 2919 }; 2920 2921 cpu67_alert1: trip-point1 { 2922 temperature = <95000>; 2923 hysteresis = <2000>; 2924 type = "passive"; 2925 }; 2926 2927 cpu67_crit: cpu_crit { 2928 temperature = <110000>; 2929 hysteresis = <1000>; 2930 type = "critical"; 2931 }; 2932 }; 2933 }; 2934 2935 cpu0123-thermal { 2936 polling-delay-passive = <0>; 2937 polling-delay = <0>; 2938 thermal-sensors = <&tsens0 12>; 2939 2940 trips { 2941 cpu0123_alert0: trip-point0 { 2942 temperature = <90000>; 2943 hysteresis = <2000>; 2944 type = "passive"; 2945 }; 2946 2947 cpu0123_alert1: trip-point1 { 2948 temperature = <95000>; 2949 hysteresis = <2000>; 2950 type = "passive"; 2951 }; 2952 2953 cpu0123_crit: cpu_crit { 2954 temperature = <110000>; 2955 hysteresis = <1000>; 2956 type = "critical"; 2957 }; 2958 }; 2959 }; 2960 2961 modem0-thermal { 2962 polling-delay-passive = <0>; 2963 polling-delay = <0>; 2964 thermal-sensors = <&tsens0 13>; 2965 2966 trips { 2967 trip-point0 { 2968 temperature = <115000>; 2969 hysteresis = <5000>; 2970 type = "passive"; 2971 }; 2972 2973 trip-point1 { 2974 temperature = <125000>; 2975 hysteresis = <1000>; 2976 type = "passive"; 2977 }; 2978 }; 2979 }; 2980 2981 display-thermal { 2982 polling-delay-passive = <0>; 2983 polling-delay = <0>; 2984 thermal-sensors = <&tsens0 14>; 2985 2986 trips { 2987 trip-point0 { 2988 temperature = <115000>; 2989 hysteresis = <5000>; 2990 type = "passive"; 2991 }; 2992 2993 trip-point1 { 2994 temperature = <125000>; 2995 hysteresis = <1000>; 2996 type = "passive"; 2997 }; 2998 }; 2999 }; 3000 3001 gpu-thermal { 3002 polling-delay-passive = <0>; 3003 polling-delay = <0>; 3004 thermal-sensors = <&tsens0 15>; 3005 3006 trips { 3007 trip-point0 { 3008 temperature = <115000>; 3009 hysteresis = <5000>; 3010 type = "passive"; 3011 }; 3012 3013 trip-point1 { 3014 temperature = <125000>; 3015 hysteresis = <1000>; 3016 type = "passive"; 3017 }; 3018 }; 3019 }; 3020 }; 3021 3022 timer { 3023 compatible = "arm,armv8-timer"; 3024 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 3025 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 3026 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 3027 <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 3028 }; 3029}; 3030