1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright (c) 2021, Iskren Chernev <iskren.chernev@gmail.com> 4 */ 5 6#include <dt-bindings/clock/qcom,gcc-sm6115.h> 7#include <dt-bindings/clock/qcom,sm6115-dispcc.h> 8#include <dt-bindings/clock/qcom,sm6115-gpucc.h> 9#include <dt-bindings/clock/qcom,rpmcc.h> 10#include <dt-bindings/dma/qcom-gpi.h> 11#include <dt-bindings/firmware/qcom,scm.h> 12#include <dt-bindings/gpio/gpio.h> 13#include <dt-bindings/interrupt-controller/arm-gic.h> 14#include <dt-bindings/power/qcom-rpmpd.h> 15 16/ { 17 interrupt-parent = <&intc>; 18 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 chosen { }; 23 24 clocks { 25 xo_board: xo-board { 26 compatible = "fixed-clock"; 27 #clock-cells = <0>; 28 }; 29 30 sleep_clk: sleep-clk { 31 compatible = "fixed-clock"; 32 #clock-cells = <0>; 33 }; 34 }; 35 36 cpus { 37 #address-cells = <2>; 38 #size-cells = <0>; 39 40 CPU0: cpu@0 { 41 device_type = "cpu"; 42 compatible = "qcom,kryo260"; 43 reg = <0x0 0x0>; 44 clocks = <&cpufreq_hw 0>; 45 capacity-dmips-mhz = <1024>; 46 dynamic-power-coefficient = <100>; 47 enable-method = "psci"; 48 next-level-cache = <&L2_0>; 49 qcom,freq-domain = <&cpufreq_hw 0>; 50 power-domains = <&CPU_PD0>; 51 power-domain-names = "psci"; 52 L2_0: l2-cache { 53 compatible = "cache"; 54 cache-level = <2>; 55 cache-unified; 56 }; 57 }; 58 59 CPU1: cpu@1 { 60 device_type = "cpu"; 61 compatible = "qcom,kryo260"; 62 reg = <0x0 0x1>; 63 clocks = <&cpufreq_hw 0>; 64 capacity-dmips-mhz = <1024>; 65 dynamic-power-coefficient = <100>; 66 enable-method = "psci"; 67 next-level-cache = <&L2_0>; 68 qcom,freq-domain = <&cpufreq_hw 0>; 69 power-domains = <&CPU_PD1>; 70 power-domain-names = "psci"; 71 }; 72 73 CPU2: cpu@2 { 74 device_type = "cpu"; 75 compatible = "qcom,kryo260"; 76 reg = <0x0 0x2>; 77 clocks = <&cpufreq_hw 0>; 78 capacity-dmips-mhz = <1024>; 79 dynamic-power-coefficient = <100>; 80 enable-method = "psci"; 81 next-level-cache = <&L2_0>; 82 qcom,freq-domain = <&cpufreq_hw 0>; 83 power-domains = <&CPU_PD2>; 84 power-domain-names = "psci"; 85 }; 86 87 CPU3: cpu@3 { 88 device_type = "cpu"; 89 compatible = "qcom,kryo260"; 90 reg = <0x0 0x3>; 91 clocks = <&cpufreq_hw 0>; 92 capacity-dmips-mhz = <1024>; 93 dynamic-power-coefficient = <100>; 94 enable-method = "psci"; 95 next-level-cache = <&L2_0>; 96 qcom,freq-domain = <&cpufreq_hw 0>; 97 power-domains = <&CPU_PD3>; 98 power-domain-names = "psci"; 99 }; 100 101 CPU4: cpu@100 { 102 device_type = "cpu"; 103 compatible = "qcom,kryo260"; 104 reg = <0x0 0x100>; 105 clocks = <&cpufreq_hw 1>; 106 enable-method = "psci"; 107 capacity-dmips-mhz = <1638>; 108 dynamic-power-coefficient = <282>; 109 next-level-cache = <&L2_1>; 110 qcom,freq-domain = <&cpufreq_hw 1>; 111 power-domains = <&CPU_PD4>; 112 power-domain-names = "psci"; 113 L2_1: l2-cache { 114 compatible = "cache"; 115 cache-level = <2>; 116 cache-unified; 117 }; 118 }; 119 120 CPU5: cpu@101 { 121 device_type = "cpu"; 122 compatible = "qcom,kryo260"; 123 reg = <0x0 0x101>; 124 clocks = <&cpufreq_hw 1>; 125 capacity-dmips-mhz = <1638>; 126 dynamic-power-coefficient = <282>; 127 enable-method = "psci"; 128 next-level-cache = <&L2_1>; 129 qcom,freq-domain = <&cpufreq_hw 1>; 130 power-domains = <&CPU_PD5>; 131 power-domain-names = "psci"; 132 }; 133 134 CPU6: cpu@102 { 135 device_type = "cpu"; 136 compatible = "qcom,kryo260"; 137 reg = <0x0 0x102>; 138 clocks = <&cpufreq_hw 1>; 139 capacity-dmips-mhz = <1638>; 140 dynamic-power-coefficient = <282>; 141 enable-method = "psci"; 142 next-level-cache = <&L2_1>; 143 qcom,freq-domain = <&cpufreq_hw 1>; 144 power-domains = <&CPU_PD6>; 145 power-domain-names = "psci"; 146 }; 147 148 CPU7: cpu@103 { 149 device_type = "cpu"; 150 compatible = "qcom,kryo260"; 151 reg = <0x0 0x103>; 152 clocks = <&cpufreq_hw 1>; 153 capacity-dmips-mhz = <1638>; 154 dynamic-power-coefficient = <282>; 155 enable-method = "psci"; 156 next-level-cache = <&L2_1>; 157 qcom,freq-domain = <&cpufreq_hw 1>; 158 power-domains = <&CPU_PD7>; 159 power-domain-names = "psci"; 160 }; 161 162 cpu-map { 163 cluster0 { 164 core0 { 165 cpu = <&CPU0>; 166 }; 167 168 core1 { 169 cpu = <&CPU1>; 170 }; 171 172 core2 { 173 cpu = <&CPU2>; 174 }; 175 176 core3 { 177 cpu = <&CPU3>; 178 }; 179 }; 180 181 cluster1 { 182 core0 { 183 cpu = <&CPU4>; 184 }; 185 186 core1 { 187 cpu = <&CPU5>; 188 }; 189 190 core2 { 191 cpu = <&CPU6>; 192 }; 193 194 core3 { 195 cpu = <&CPU7>; 196 }; 197 }; 198 }; 199 200 idle-states { 201 entry-method = "psci"; 202 203 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 204 compatible = "arm,idle-state"; 205 idle-state-name = "silver-rail-power-collapse"; 206 arm,psci-suspend-param = <0x40000003>; 207 entry-latency-us = <290>; 208 exit-latency-us = <376>; 209 min-residency-us = <1182>; 210 local-timer-stop; 211 }; 212 213 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 214 compatible = "arm,idle-state"; 215 idle-state-name = "gold-rail-power-collapse"; 216 arm,psci-suspend-param = <0x40000003>; 217 entry-latency-us = <297>; 218 exit-latency-us = <324>; 219 min-residency-us = <1110>; 220 local-timer-stop; 221 }; 222 }; 223 224 domain-idle-states { 225 CLUSTER_0_SLEEP_0: cluster-sleep-0-0 { 226 /* GDHS */ 227 compatible = "domain-idle-state"; 228 arm,psci-suspend-param = <0x40000022>; 229 entry-latency-us = <360>; 230 exit-latency-us = <421>; 231 min-residency-us = <782>; 232 }; 233 234 CLUSTER_0_SLEEP_1: cluster-sleep-0-1 { 235 /* Power Collapse */ 236 compatible = "domain-idle-state"; 237 arm,psci-suspend-param = <0x41000044>; 238 entry-latency-us = <800>; 239 exit-latency-us = <2118>; 240 min-residency-us = <7376>; 241 }; 242 243 CLUSTER_1_SLEEP_0: cluster-sleep-1-0 { 244 /* GDHS */ 245 compatible = "domain-idle-state"; 246 arm,psci-suspend-param = <0x40000042>; 247 entry-latency-us = <314>; 248 exit-latency-us = <345>; 249 min-residency-us = <660>; 250 }; 251 252 CLUSTER_1_SLEEP_1: cluster-sleep-1-1 { 253 /* Power Collapse */ 254 compatible = "domain-idle-state"; 255 arm,psci-suspend-param = <0x41000044>; 256 entry-latency-us = <640>; 257 exit-latency-us = <1654>; 258 min-residency-us = <8094>; 259 }; 260 }; 261 }; 262 263 firmware { 264 scm: scm { 265 compatible = "qcom,scm-sm6115", "qcom,scm"; 266 #reset-cells = <1>; 267 }; 268 }; 269 270 memory@80000000 { 271 device_type = "memory"; 272 /* We expect the bootloader to fill in the size */ 273 reg = <0 0x80000000 0 0>; 274 }; 275 276 pmu { 277 compatible = "arm,armv8-pmuv3"; 278 interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>; 279 }; 280 281 psci { 282 compatible = "arm,psci-1.0"; 283 method = "smc"; 284 285 CPU_PD0: power-domain-cpu0 { 286 #power-domain-cells = <0>; 287 power-domains = <&CLUSTER_0_PD>; 288 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 289 }; 290 291 CPU_PD1: power-domain-cpu1 { 292 #power-domain-cells = <0>; 293 power-domains = <&CLUSTER_0_PD>; 294 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 295 }; 296 297 CPU_PD2: power-domain-cpu2 { 298 #power-domain-cells = <0>; 299 power-domains = <&CLUSTER_0_PD>; 300 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 301 }; 302 303 CPU_PD3: power-domain-cpu3 { 304 #power-domain-cells = <0>; 305 power-domains = <&CLUSTER_0_PD>; 306 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 307 }; 308 309 CPU_PD4: power-domain-cpu4 { 310 #power-domain-cells = <0>; 311 power-domains = <&CLUSTER_1_PD>; 312 domain-idle-states = <&BIG_CPU_SLEEP_0>; 313 }; 314 315 CPU_PD5: power-domain-cpu5 { 316 #power-domain-cells = <0>; 317 power-domains = <&CLUSTER_1_PD>; 318 domain-idle-states = <&BIG_CPU_SLEEP_0>; 319 }; 320 321 CPU_PD6: power-domain-cpu6 { 322 #power-domain-cells = <0>; 323 power-domains = <&CLUSTER_1_PD>; 324 domain-idle-states = <&BIG_CPU_SLEEP_0>; 325 }; 326 327 CPU_PD7: power-domain-cpu7 { 328 #power-domain-cells = <0>; 329 power-domains = <&CLUSTER_1_PD>; 330 domain-idle-states = <&BIG_CPU_SLEEP_0>; 331 }; 332 333 CLUSTER_0_PD: power-domain-cpu-cluster0 { 334 #power-domain-cells = <0>; 335 domain-idle-states = <&CLUSTER_0_SLEEP_0>, <&CLUSTER_0_SLEEP_1>; 336 }; 337 338 CLUSTER_1_PD: power-domain-cpu-cluster1 { 339 #power-domain-cells = <0>; 340 domain-idle-states = <&CLUSTER_1_SLEEP_0>, <&CLUSTER_1_SLEEP_1>; 341 }; 342 }; 343 344 rpm: remoteproc { 345 compatible = "qcom,sm6115-rpm-proc", "qcom,rpm-proc"; 346 347 glink-edge { 348 compatible = "qcom,glink-rpm"; 349 350 interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>; 351 qcom,rpm-msg-ram = <&rpm_msg_ram>; 352 mboxes = <&apcs_glb 0>; 353 354 rpm_requests: rpm-requests { 355 compatible = "qcom,rpm-sm6115"; 356 qcom,glink-channels = "rpm_requests"; 357 358 rpmcc: clock-controller { 359 compatible = "qcom,rpmcc-sm6115", "qcom,rpmcc"; 360 clocks = <&xo_board>; 361 clock-names = "xo"; 362 #clock-cells = <1>; 363 }; 364 365 rpmpd: power-controller { 366 compatible = "qcom,sm6115-rpmpd"; 367 #power-domain-cells = <1>; 368 operating-points-v2 = <&rpmpd_opp_table>; 369 370 rpmpd_opp_table: opp-table { 371 compatible = "operating-points-v2"; 372 373 rpmpd_opp_min_svs: opp1 { 374 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 375 }; 376 377 rpmpd_opp_low_svs: opp2 { 378 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 379 }; 380 381 rpmpd_opp_svs: opp3 { 382 opp-level = <RPM_SMD_LEVEL_SVS>; 383 }; 384 385 rpmpd_opp_svs_plus: opp4 { 386 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 387 }; 388 389 rpmpd_opp_nom: opp5 { 390 opp-level = <RPM_SMD_LEVEL_NOM>; 391 }; 392 393 rpmpd_opp_nom_plus: opp6 { 394 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 395 }; 396 397 rpmpd_opp_turbo: opp7 { 398 opp-level = <RPM_SMD_LEVEL_TURBO>; 399 }; 400 401 rpmpd_opp_turbo_plus: opp8 { 402 opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>; 403 }; 404 }; 405 }; 406 }; 407 }; 408 }; 409 410 reserved_memory: reserved-memory { 411 #address-cells = <2>; 412 #size-cells = <2>; 413 ranges; 414 415 hyp_mem: memory@45700000 { 416 reg = <0x0 0x45700000 0x0 0x600000>; 417 no-map; 418 }; 419 420 xbl_aop_mem: memory@45e00000 { 421 reg = <0x0 0x45e00000 0x0 0x140000>; 422 no-map; 423 }; 424 425 sec_apps_mem: memory@45fff000 { 426 reg = <0x0 0x45fff000 0x0 0x1000>; 427 no-map; 428 }; 429 430 smem_mem: memory@46000000 { 431 compatible = "qcom,smem"; 432 reg = <0x0 0x46000000 0x0 0x200000>; 433 no-map; 434 435 hwlocks = <&tcsr_mutex 3>; 436 qcom,rpm-msg-ram = <&rpm_msg_ram>; 437 }; 438 439 cdsp_sec_mem: memory@46200000 { 440 reg = <0x0 0x46200000 0x0 0x1e00000>; 441 no-map; 442 }; 443 444 pil_modem_mem: memory@4ab00000 { 445 reg = <0x0 0x4ab00000 0x0 0x6900000>; 446 no-map; 447 }; 448 449 pil_video_mem: memory@51400000 { 450 reg = <0x0 0x51400000 0x0 0x500000>; 451 no-map; 452 }; 453 454 wlan_msa_mem: memory@51900000 { 455 reg = <0x0 0x51900000 0x0 0x100000>; 456 no-map; 457 }; 458 459 pil_cdsp_mem: memory@51a00000 { 460 reg = <0x0 0x51a00000 0x0 0x1e00000>; 461 no-map; 462 }; 463 464 pil_adsp_mem: memory@53800000 { 465 reg = <0x0 0x53800000 0x0 0x2800000>; 466 no-map; 467 }; 468 469 pil_ipa_fw_mem: memory@56100000 { 470 reg = <0x0 0x56100000 0x0 0x10000>; 471 no-map; 472 }; 473 474 pil_ipa_gsi_mem: memory@56110000 { 475 reg = <0x0 0x56110000 0x0 0x5000>; 476 no-map; 477 }; 478 479 pil_gpu_mem: memory@56115000 { 480 reg = <0x0 0x56115000 0x0 0x2000>; 481 no-map; 482 }; 483 484 cont_splash_memory: memory@5c000000 { 485 reg = <0x0 0x5c000000 0x0 0x00f00000>; 486 no-map; 487 }; 488 489 dfps_data_memory: memory@5cf00000 { 490 reg = <0x0 0x5cf00000 0x0 0x0100000>; 491 no-map; 492 }; 493 494 removed_mem: memory@60000000 { 495 reg = <0x0 0x60000000 0x0 0x3900000>; 496 no-map; 497 }; 498 499 rmtfs_mem: memory@89b01000 { 500 compatible = "qcom,rmtfs-mem"; 501 reg = <0x0 0x89b01000 0x0 0x200000>; 502 no-map; 503 504 qcom,client-id = <1>; 505 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA QCOM_SCM_VMID_NAV>; 506 }; 507 }; 508 509 smp2p-adsp { 510 compatible = "qcom,smp2p"; 511 qcom,smem = <443>, <429>; 512 513 interrupts = <GIC_SPI 279 IRQ_TYPE_EDGE_RISING>; 514 515 mboxes = <&apcs_glb 10>; 516 517 qcom,local-pid = <0>; 518 qcom,remote-pid = <2>; 519 520 adsp_smp2p_out: master-kernel { 521 qcom,entry-name = "master-kernel"; 522 #qcom,smem-state-cells = <1>; 523 }; 524 525 adsp_smp2p_in: slave-kernel { 526 qcom,entry-name = "slave-kernel"; 527 528 interrupt-controller; 529 #interrupt-cells = <2>; 530 }; 531 }; 532 533 smp2p-cdsp { 534 compatible = "qcom,smp2p"; 535 qcom,smem = <94>, <432>; 536 537 interrupts = <GIC_SPI 263 IRQ_TYPE_EDGE_RISING>; 538 539 mboxes = <&apcs_glb 30>; 540 541 qcom,local-pid = <0>; 542 qcom,remote-pid = <5>; 543 544 cdsp_smp2p_out: master-kernel { 545 qcom,entry-name = "master-kernel"; 546 #qcom,smem-state-cells = <1>; 547 }; 548 549 cdsp_smp2p_in: slave-kernel { 550 qcom,entry-name = "slave-kernel"; 551 552 interrupt-controller; 553 #interrupt-cells = <2>; 554 }; 555 }; 556 557 smp2p-mpss { 558 compatible = "qcom,smp2p"; 559 qcom,smem = <435>, <428>; 560 561 interrupts = <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>; 562 563 mboxes = <&apcs_glb 14>; 564 565 qcom,local-pid = <0>; 566 qcom,remote-pid = <1>; 567 568 modem_smp2p_out: master-kernel { 569 qcom,entry-name = "master-kernel"; 570 #qcom,smem-state-cells = <1>; 571 }; 572 573 modem_smp2p_in: slave-kernel { 574 qcom,entry-name = "slave-kernel"; 575 576 interrupt-controller; 577 #interrupt-cells = <2>; 578 }; 579 }; 580 581 soc: soc@0 { 582 compatible = "simple-bus"; 583 #address-cells = <2>; 584 #size-cells = <2>; 585 ranges = <0 0 0 0 0x10 0>; 586 dma-ranges = <0 0 0 0 0x10 0>; 587 588 tcsr_mutex: hwlock@340000 { 589 compatible = "qcom,tcsr-mutex"; 590 reg = <0x0 0x00340000 0x0 0x20000>; 591 #hwlock-cells = <1>; 592 }; 593 594 tcsr_regs: syscon@3c0000 { 595 compatible = "qcom,sm6115-tcsr", "syscon"; 596 reg = <0x0 0x003c0000 0x0 0x40000>; 597 }; 598 599 tlmm: pinctrl@500000 { 600 compatible = "qcom,sm6115-tlmm"; 601 reg = <0x0 0x00500000 0x0 0x400000>, 602 <0x0 0x00900000 0x0 0x400000>, 603 <0x0 0x00d00000 0x0 0x400000>; 604 reg-names = "west", "south", "east"; 605 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 606 gpio-controller; 607 gpio-ranges = <&tlmm 0 0 114>; /* GPIOs + ufs_reset */ 608 #gpio-cells = <2>; 609 interrupt-controller; 610 #interrupt-cells = <2>; 611 612 qup_i2c0_default: qup-i2c0-default-state { 613 pins = "gpio0", "gpio1"; 614 function = "qup0"; 615 drive-strength = <2>; 616 bias-pull-up; 617 }; 618 619 qup_i2c1_default: qup-i2c1-default-state { 620 pins = "gpio4", "gpio5"; 621 function = "qup1"; 622 drive-strength = <2>; 623 bias-pull-up; 624 }; 625 626 qup_i2c2_default: qup-i2c2-default-state { 627 pins = "gpio6", "gpio7"; 628 function = "qup2"; 629 drive-strength = <2>; 630 bias-pull-up; 631 }; 632 633 qup_i2c3_default: qup-i2c3-default-state { 634 pins = "gpio8", "gpio9"; 635 function = "qup3"; 636 drive-strength = <2>; 637 bias-pull-up; 638 }; 639 640 qup_i2c4_default: qup-i2c4-default-state { 641 pins = "gpio12", "gpio13"; 642 function = "qup4"; 643 drive-strength = <2>; 644 bias-pull-up; 645 }; 646 647 qup_i2c5_default: qup-i2c5-default-state { 648 pins = "gpio14", "gpio15"; 649 function = "qup5"; 650 drive-strength = <2>; 651 bias-pull-up; 652 }; 653 654 qup_spi0_default: qup-spi0-default-state { 655 pins = "gpio0", "gpio1","gpio2", "gpio3"; 656 function = "qup0"; 657 drive-strength = <2>; 658 bias-pull-up; 659 }; 660 661 qup_spi1_default: qup-spi1-default-state { 662 pins = "gpio4", "gpio5", "gpio69", "gpio70"; 663 function = "qup1"; 664 drive-strength = <2>; 665 bias-pull-up; 666 }; 667 668 qup_spi2_default: qup-spi2-default-state { 669 pins = "gpio6", "gpio7", "gpio71", "gpio80"; 670 function = "qup2"; 671 drive-strength = <2>; 672 bias-pull-up; 673 }; 674 675 qup_spi3_default: qup-spi3-default-state { 676 pins = "gpio8", "gpio9", "gpio10", "gpio11"; 677 function = "qup3"; 678 drive-strength = <2>; 679 bias-pull-up; 680 }; 681 682 qup_spi4_default: qup-spi4-default-state { 683 pins = "gpio12", "gpio13", "gpio96", "gpio97"; 684 function = "qup4"; 685 drive-strength = <2>; 686 bias-pull-up; 687 }; 688 689 qup_spi5_default: qup-spi5-default-state { 690 pins = "gpio14", "gpio15", "gpio16", "gpio17"; 691 function = "qup5"; 692 drive-strength = <2>; 693 bias-pull-up; 694 }; 695 696 sdc1_state_on: sdc1-on-state { 697 clk-pins { 698 pins = "sdc1_clk"; 699 bias-disable; 700 drive-strength = <16>; 701 }; 702 703 cmd-pins { 704 pins = "sdc1_cmd"; 705 bias-pull-up; 706 drive-strength = <10>; 707 }; 708 709 data-pins { 710 pins = "sdc1_data"; 711 bias-pull-up; 712 drive-strength = <10>; 713 }; 714 715 rclk-pins { 716 pins = "sdc1_rclk"; 717 bias-pull-down; 718 }; 719 }; 720 721 sdc1_state_off: sdc1-off-state { 722 clk-pins { 723 pins = "sdc1_clk"; 724 bias-disable; 725 drive-strength = <2>; 726 }; 727 728 cmd-pins { 729 pins = "sdc1_cmd"; 730 bias-pull-up; 731 drive-strength = <2>; 732 }; 733 734 data-pins { 735 pins = "sdc1_data"; 736 bias-pull-up; 737 drive-strength = <2>; 738 }; 739 740 rclk-pins { 741 pins = "sdc1_rclk"; 742 bias-pull-down; 743 }; 744 }; 745 746 sdc2_state_on: sdc2-on-state { 747 clk-pins { 748 pins = "sdc2_clk"; 749 bias-disable; 750 drive-strength = <16>; 751 }; 752 753 cmd-pins { 754 pins = "sdc2_cmd"; 755 bias-pull-up; 756 drive-strength = <10>; 757 }; 758 759 data-pins { 760 pins = "sdc2_data"; 761 bias-pull-up; 762 drive-strength = <10>; 763 }; 764 }; 765 766 sdc2_state_off: sdc2-off-state { 767 clk-pins { 768 pins = "sdc2_clk"; 769 bias-disable; 770 drive-strength = <2>; 771 }; 772 773 cmd-pins { 774 pins = "sdc2_cmd"; 775 bias-pull-up; 776 drive-strength = <2>; 777 }; 778 779 data-pins { 780 pins = "sdc2_data"; 781 bias-pull-up; 782 drive-strength = <2>; 783 }; 784 }; 785 }; 786 787 gcc: clock-controller@1400000 { 788 compatible = "qcom,gcc-sm6115"; 789 reg = <0x0 0x01400000 0x0 0x1f0000>; 790 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>; 791 clock-names = "bi_tcxo", "sleep_clk"; 792 #clock-cells = <1>; 793 #reset-cells = <1>; 794 #power-domain-cells = <1>; 795 }; 796 797 usb_hsphy: phy@1613000 { 798 compatible = "qcom,sm6115-qusb2-phy"; 799 reg = <0x0 0x01613000 0x0 0x180>; 800 #phy-cells = <0>; 801 802 clocks = <&gcc GCC_AHB2PHY_USB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>; 803 clock-names = "cfg_ahb", "ref"; 804 805 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 806 nvmem-cells = <&qusb2_hstx_trim>; 807 808 status = "disabled"; 809 }; 810 811 cryptobam: dma-controller@1b04000 { 812 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 813 reg = <0x0 0x01b04000 0x0 0x24000>; 814 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>; 815 clocks = <&rpmcc RPM_SMD_CE1_CLK>; 816 clock-names = "bam_clk"; 817 #dma-cells = <1>; 818 qcom,ee = <0>; 819 qcom,controlled-remotely; 820 iommus = <&apps_smmu 0x92 0>, 821 <&apps_smmu 0x94 0x11>, 822 <&apps_smmu 0x96 0x11>, 823 <&apps_smmu 0x98 0x1>, 824 <&apps_smmu 0x9F 0>; 825 }; 826 827 crypto: crypto@1b3a000 { 828 compatible = "qcom,sm6115-qce", "qcom,ipq4019-qce", "qcom,qce"; 829 reg = <0x0 0x01b3a000 0x0 0x6000>; 830 clocks = <&rpmcc RPM_SMD_CE1_CLK>; 831 clock-names = "core"; 832 833 dmas = <&cryptobam 6>, <&cryptobam 7>; 834 dma-names = "rx", "tx"; 835 iommus = <&apps_smmu 0x92 0>, 836 <&apps_smmu 0x94 0x11>, 837 <&apps_smmu 0x96 0x11>, 838 <&apps_smmu 0x98 0x1>, 839 <&apps_smmu 0x9F 0>; 840 }; 841 842 usb_qmpphy: phy@1615000 { 843 compatible = "qcom,sm6115-qmp-usb3-phy"; 844 reg = <0x0 0x01615000 0x0 0x1000>; 845 846 clocks = <&gcc GCC_AHB2PHY_USB_CLK>, 847 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 848 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 849 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 850 clock-names = "cfg_ahb", 851 "ref", 852 "com_aux", 853 "pipe"; 854 855 resets = <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>, 856 <&gcc GCC_USB3PHY_PHY_PRIM_SP0_BCR>; 857 reset-names = "phy", "phy_phy"; 858 859 #clock-cells = <0>; 860 clock-output-names = "usb3_phy_pipe_clk_src"; 861 862 #phy-cells = <0>; 863 864 qcom,tcsr-reg = <&tcsr_regs 0xb244>; 865 866 status = "disabled"; 867 }; 868 869 qfprom@1b40000 { 870 compatible = "qcom,sm6115-qfprom", "qcom,qfprom"; 871 reg = <0x0 0x01b40000 0x0 0x7000>; 872 #address-cells = <1>; 873 #size-cells = <1>; 874 875 qusb2_hstx_trim: hstx-trim@25b { 876 reg = <0x25b 0x1>; 877 bits = <1 4>; 878 }; 879 880 gpu_speed_bin: gpu-speed-bin@6006 { 881 reg = <0x6006 0x2>; 882 bits = <5 8>; 883 }; 884 }; 885 886 rng: rng@1b53000 { 887 compatible = "qcom,prng-ee"; 888 reg = <0x0 0x01b53000 0x0 0x1000>; 889 clocks = <&gcc GCC_PRNG_AHB_CLK>; 890 clock-names = "core"; 891 }; 892 893 spmi_bus: spmi@1c40000 { 894 compatible = "qcom,spmi-pmic-arb"; 895 reg = <0x0 0x01c40000 0x0 0x1100>, 896 <0x0 0x01e00000 0x0 0x2000000>, 897 <0x0 0x03e00000 0x0 0x100000>, 898 <0x0 0x03f00000 0x0 0xa0000>, 899 <0x0 0x01c0a000 0x0 0x26000>; 900 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 901 interrupt-names = "periph_irq"; 902 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 903 qcom,ee = <0>; 904 qcom,channel = <0>; 905 #address-cells = <2>; 906 #size-cells = <0>; 907 interrupt-controller; 908 #interrupt-cells = <4>; 909 }; 910 911 tsens0: thermal-sensor@4411000 { 912 compatible = "qcom,sm6115-tsens", "qcom,tsens-v2"; 913 reg = <0x0 0x04411000 0x0 0x1ff>, /* TM */ 914 <0x0 0x04410000 0x0 0x8>; /* SROT */ 915 #qcom,sensors = <16>; 916 interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 917 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 918 interrupt-names = "uplow", "critical"; 919 #thermal-sensor-cells = <1>; 920 }; 921 922 rpm_msg_ram: sram@45f0000 { 923 compatible = "qcom,rpm-msg-ram"; 924 reg = <0x0 0x045f0000 0x0 0x7000>; 925 }; 926 927 sram@4690000 { 928 compatible = "qcom,rpm-stats"; 929 reg = <0x0 0x04690000 0x0 0x10000>; 930 }; 931 932 sdhc_1: mmc@4744000 { 933 compatible = "qcom,sm6115-sdhci", "qcom,sdhci-msm-v5"; 934 reg = <0x0 0x04744000 0x0 0x1000>, 935 <0x0 0x04745000 0x0 0x1000>, 936 <0x0 0x04748000 0x0 0x8000>; 937 reg-names = "hc", "cqhci", "ice"; 938 939 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, 940 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 941 interrupt-names = "hc_irq", "pwr_irq"; 942 943 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 944 <&gcc GCC_SDCC1_APPS_CLK>, 945 <&rpmcc RPM_SMD_XO_CLK_SRC>, 946 <&gcc GCC_SDCC1_ICE_CORE_CLK>; 947 clock-names = "iface", "core", "xo", "ice"; 948 949 bus-width = <8>; 950 status = "disabled"; 951 }; 952 953 sdhc_2: mmc@4784000 { 954 compatible = "qcom,sm6115-sdhci", "qcom,sdhci-msm-v5"; 955 reg = <0x0 0x04784000 0x0 0x1000>; 956 reg-names = "hc"; 957 958 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 959 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 960 interrupt-names = "hc_irq", "pwr_irq"; 961 962 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 963 <&gcc GCC_SDCC2_APPS_CLK>, 964 <&rpmcc RPM_SMD_XO_CLK_SRC>; 965 clock-names = "iface", "core", "xo"; 966 967 power-domains = <&rpmpd SM6115_VDDCX>; 968 operating-points-v2 = <&sdhc2_opp_table>; 969 iommus = <&apps_smmu 0x00a0 0x0>; 970 resets = <&gcc GCC_SDCC2_BCR>; 971 972 bus-width = <4>; 973 qcom,dll-config = <0x0007642c>; 974 qcom,ddr-config = <0x80040868>; 975 status = "disabled"; 976 977 sdhc2_opp_table: opp-table { 978 compatible = "operating-points-v2"; 979 980 opp-100000000 { 981 opp-hz = /bits/ 64 <100000000>; 982 required-opps = <&rpmpd_opp_low_svs>; 983 }; 984 985 opp-202000000 { 986 opp-hz = /bits/ 64 <202000000>; 987 required-opps = <&rpmpd_opp_nom>; 988 }; 989 }; 990 }; 991 992 ufs_mem_hc: ufs@4804000 { 993 compatible = "qcom,sm6115-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; 994 reg = <0x0 0x04804000 0x0 0x3000>, <0x0 0x04810000 0x0 0x8000>; 995 reg-names = "std", "ice"; 996 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 997 phys = <&ufs_mem_phy_lanes>; 998 phy-names = "ufsphy"; 999 lanes-per-direction = <1>; 1000 #reset-cells = <1>; 1001 resets = <&gcc GCC_UFS_PHY_BCR>; 1002 reset-names = "rst"; 1003 1004 power-domains = <&gcc GCC_UFS_PHY_GDSC>; 1005 iommus = <&apps_smmu 0x100 0>; 1006 1007 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 1008 <&gcc GCC_SYS_NOC_UFS_PHY_AXI_CLK>, 1009 <&gcc GCC_UFS_PHY_AHB_CLK>, 1010 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 1011 <&rpmcc RPM_SMD_XO_CLK_SRC>, 1012 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 1013 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 1014 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 1015 clock-names = "core_clk", 1016 "bus_aggr_clk", 1017 "iface_clk", 1018 "core_clk_unipro", 1019 "ref_clk", 1020 "tx_lane0_sync_clk", 1021 "rx_lane0_sync_clk", 1022 "ice_core_clk"; 1023 1024 freq-table-hz = <50000000 200000000>, 1025 <0 0>, 1026 <0 0>, 1027 <37500000 150000000>, 1028 <0 0>, 1029 <0 0>, 1030 <0 0>, 1031 <75000000 300000000>; 1032 1033 status = "disabled"; 1034 }; 1035 1036 ufs_mem_phy: phy@4807000 { 1037 compatible = "qcom,sm6115-qmp-ufs-phy"; 1038 reg = <0x0 0x04807000 0x0 0x1c4>; 1039 #address-cells = <2>; 1040 #size-cells = <2>; 1041 ranges; 1042 1043 clocks = <&gcc GCC_UFS_CLKREF_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 1044 clock-names = "ref", "ref_aux"; 1045 1046 resets = <&ufs_mem_hc 0>; 1047 reset-names = "ufsphy"; 1048 status = "disabled"; 1049 1050 ufs_mem_phy_lanes: phy@4807400 { 1051 reg = <0x0 0x04807400 0x0 0x098>, 1052 <0x0 0x04807600 0x0 0x130>, 1053 <0x0 0x04807c00 0x0 0x16c>; 1054 #phy-cells = <0>; 1055 }; 1056 }; 1057 1058 gpi_dma0: dma-controller@4a00000 { 1059 compatible = "qcom,sm6115-gpi-dma", "qcom,sm6350-gpi-dma"; 1060 reg = <0x0 0x04a00000 0x0 0x60000>; 1061 interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 1062 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 1063 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 1064 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 1065 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 1066 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 1067 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 1068 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 1069 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 1070 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; 1071 dma-channels = <10>; 1072 dma-channel-mask = <0xf>; 1073 iommus = <&apps_smmu 0xf6 0x0>; 1074 #dma-cells = <3>; 1075 status = "disabled"; 1076 }; 1077 1078 qupv3_id_0: geniqup@4ac0000 { 1079 compatible = "qcom,geni-se-qup"; 1080 reg = <0x0 0x04ac0000 0x0 0x2000>; 1081 clock-names = "m-ahb", "s-ahb"; 1082 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1083 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1084 #address-cells = <2>; 1085 #size-cells = <2>; 1086 iommus = <&apps_smmu 0xe3 0x0>; 1087 ranges; 1088 status = "disabled"; 1089 1090 i2c0: i2c@4a80000 { 1091 compatible = "qcom,geni-i2c"; 1092 reg = <0x0 0x04a80000 0x0 0x4000>; 1093 clock-names = "se"; 1094 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1095 pinctrl-names = "default"; 1096 pinctrl-0 = <&qup_i2c0_default>; 1097 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 1098 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1099 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1100 dma-names = "tx", "rx"; 1101 #address-cells = <1>; 1102 #size-cells = <0>; 1103 status = "disabled"; 1104 }; 1105 1106 spi0: spi@4a80000 { 1107 compatible = "qcom,geni-spi"; 1108 reg = <0x0 0x04a80000 0x0 0x4000>; 1109 clock-names = "se"; 1110 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1111 pinctrl-names = "default"; 1112 pinctrl-0 = <&qup_spi0_default>; 1113 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 1114 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1115 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1116 dma-names = "tx", "rx"; 1117 #address-cells = <1>; 1118 #size-cells = <0>; 1119 status = "disabled"; 1120 }; 1121 1122 i2c1: i2c@4a84000 { 1123 compatible = "qcom,geni-i2c"; 1124 reg = <0x0 0x04a84000 0x0 0x4000>; 1125 clock-names = "se"; 1126 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1127 pinctrl-names = "default"; 1128 pinctrl-0 = <&qup_i2c1_default>; 1129 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 1130 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1131 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1132 dma-names = "tx", "rx"; 1133 #address-cells = <1>; 1134 #size-cells = <0>; 1135 status = "disabled"; 1136 }; 1137 1138 spi1: spi@4a84000 { 1139 compatible = "qcom,geni-spi"; 1140 reg = <0x0 0x04a84000 0x0 0x4000>; 1141 clock-names = "se"; 1142 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1143 pinctrl-names = "default"; 1144 pinctrl-0 = <&qup_spi1_default>; 1145 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 1146 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1147 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1148 dma-names = "tx", "rx"; 1149 #address-cells = <1>; 1150 #size-cells = <0>; 1151 status = "disabled"; 1152 }; 1153 1154 i2c2: i2c@4a88000 { 1155 compatible = "qcom,geni-i2c"; 1156 reg = <0x0 0x04a88000 0x0 0x4000>; 1157 clock-names = "se"; 1158 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1159 pinctrl-names = "default"; 1160 pinctrl-0 = <&qup_i2c2_default>; 1161 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; 1162 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1163 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1164 dma-names = "tx", "rx"; 1165 #address-cells = <1>; 1166 #size-cells = <0>; 1167 status = "disabled"; 1168 }; 1169 1170 spi2: spi@4a88000 { 1171 compatible = "qcom,geni-spi"; 1172 reg = <0x0 0x04a88000 0x0 0x4000>; 1173 clock-names = "se"; 1174 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1175 pinctrl-names = "default"; 1176 pinctrl-0 = <&qup_spi2_default>; 1177 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; 1178 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1179 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1180 dma-names = "tx", "rx"; 1181 #address-cells = <1>; 1182 #size-cells = <0>; 1183 status = "disabled"; 1184 }; 1185 1186 i2c3: i2c@4a8c000 { 1187 compatible = "qcom,geni-i2c"; 1188 reg = <0x0 0x04a8c000 0x0 0x4000>; 1189 clock-names = "se"; 1190 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1191 pinctrl-names = "default"; 1192 pinctrl-0 = <&qup_i2c3_default>; 1193 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 1194 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1195 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1196 dma-names = "tx", "rx"; 1197 #address-cells = <1>; 1198 #size-cells = <0>; 1199 status = "disabled"; 1200 }; 1201 1202 spi3: spi@4a8c000 { 1203 compatible = "qcom,geni-spi"; 1204 reg = <0x0 0x04a8c000 0x0 0x4000>; 1205 clock-names = "se"; 1206 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1207 pinctrl-names = "default"; 1208 pinctrl-0 = <&qup_spi3_default>; 1209 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 1210 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1211 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1212 dma-names = "tx", "rx"; 1213 #address-cells = <1>; 1214 #size-cells = <0>; 1215 status = "disabled"; 1216 }; 1217 1218 i2c4: i2c@4a90000 { 1219 compatible = "qcom,geni-i2c"; 1220 reg = <0x0 0x04a90000 0x0 0x4000>; 1221 clock-names = "se"; 1222 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1223 pinctrl-names = "default"; 1224 pinctrl-0 = <&qup_i2c4_default>; 1225 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 1226 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1227 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1228 dma-names = "tx", "rx"; 1229 #address-cells = <1>; 1230 #size-cells = <0>; 1231 status = "disabled"; 1232 }; 1233 1234 spi4: spi@4a90000 { 1235 compatible = "qcom,geni-spi"; 1236 reg = <0x0 0x04a90000 0x0 0x4000>; 1237 clock-names = "se"; 1238 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1239 pinctrl-names = "default"; 1240 pinctrl-0 = <&qup_spi4_default>; 1241 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 1242 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1243 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1244 dma-names = "tx", "rx"; 1245 #address-cells = <1>; 1246 #size-cells = <0>; 1247 status = "disabled"; 1248 }; 1249 1250 uart4: serial@4a90000 { 1251 compatible = "qcom,geni-debug-uart"; 1252 reg = <0x0 0x04a90000 0x0 0x4000>; 1253 clock-names = "se"; 1254 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1255 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 1256 status = "disabled"; 1257 }; 1258 1259 i2c5: i2c@4a94000 { 1260 compatible = "qcom,geni-i2c"; 1261 reg = <0x0 0x04a94000 0x0 0x4000>; 1262 clock-names = "se"; 1263 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1264 pinctrl-names = "default"; 1265 pinctrl-0 = <&qup_i2c5_default>; 1266 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; 1267 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1268 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1269 dma-names = "tx", "rx"; 1270 #address-cells = <1>; 1271 #size-cells = <0>; 1272 status = "disabled"; 1273 }; 1274 1275 spi5: spi@4a94000 { 1276 compatible = "qcom,geni-spi"; 1277 reg = <0x0 0x04a94000 0x0 0x4000>; 1278 clock-names = "se"; 1279 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1280 pinctrl-names = "default"; 1281 pinctrl-0 = <&qup_spi5_default>; 1282 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; 1283 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1284 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1285 dma-names = "tx", "rx"; 1286 #address-cells = <1>; 1287 #size-cells = <0>; 1288 status = "disabled"; 1289 }; 1290 }; 1291 1292 usb: usb@4ef8800 { 1293 compatible = "qcom,sm6115-dwc3", "qcom,dwc3"; 1294 reg = <0x0 0x04ef8800 0x0 0x400>; 1295 #address-cells = <2>; 1296 #size-cells = <2>; 1297 ranges; 1298 1299 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 1300 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 1301 <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>, 1302 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 1303 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1304 <&gcc GCC_USB3_PRIM_CLKREF_CLK>; 1305 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", "xo"; 1306 1307 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1308 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 1309 assigned-clock-rates = <19200000>, <66666667>; 1310 1311 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 1312 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>; 1313 interrupt-names = "hs_phy_irq", "ss_phy_irq"; 1314 1315 resets = <&gcc GCC_USB30_PRIM_BCR>; 1316 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 1317 qcom,select-utmi-as-pipe-clk; 1318 status = "disabled"; 1319 1320 usb_dwc3: usb@4e00000 { 1321 compatible = "snps,dwc3"; 1322 reg = <0x0 0x04e00000 0x0 0xcd00>; 1323 interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 1324 phys = <&usb_hsphy>, <&usb_qmpphy>; 1325 phy-names = "usb2-phy", "usb3-phy"; 1326 iommus = <&apps_smmu 0x120 0x0>; 1327 snps,dis_u2_susphy_quirk; 1328 snps,dis_enblslpm_quirk; 1329 snps,has-lpm-erratum; 1330 snps,hird-threshold = /bits/ 8 <0x10>; 1331 snps,usb3_lpm_capable; 1332 }; 1333 }; 1334 1335 gpu: gpu@5900000 { 1336 compatible = "qcom,adreno-610.0", "qcom,adreno"; 1337 reg = <0x0 0x05900000 0x0 0x40000>; 1338 reg-names = "kgsl_3d0_reg_memory"; 1339 1340 /* There's no (real) GMU, so we have to handle quite a bunch of clocks! */ 1341 clocks = <&gpucc GPU_CC_GX_GFX3D_CLK>, 1342 <&gpucc GPU_CC_AHB_CLK>, 1343 <&gcc GCC_BIMC_GPU_AXI_CLK>, 1344 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1345 <&gpucc GPU_CC_CX_GMU_CLK>, 1346 <&gpucc GPU_CC_CXO_CLK>; 1347 clock-names = "core", 1348 "iface", 1349 "mem_iface", 1350 "alt_mem_iface", 1351 "gmu", 1352 "xo"; 1353 1354 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 1355 1356 iommus = <&adreno_smmu 0 1>; 1357 operating-points-v2 = <&gpu_opp_table>; 1358 power-domains = <&rpmpd SM6115_VDDCX>; 1359 qcom,gmu = <&gmu_wrapper>; 1360 1361 nvmem-cells = <&gpu_speed_bin>; 1362 nvmem-cell-names = "speed_bin"; 1363 1364 status = "disabled"; 1365 1366 zap-shader { 1367 memory-region = <&pil_gpu_mem>; 1368 }; 1369 1370 gpu_opp_table: opp-table { 1371 compatible = "operating-points-v2"; 1372 1373 opp-320000000 { 1374 opp-hz = /bits/ 64 <320000000>; 1375 required-opps = <&rpmpd_opp_low_svs>; 1376 opp-supported-hw = <0x1f>; 1377 }; 1378 1379 opp-465000000 { 1380 opp-hz = /bits/ 64 <465000000>; 1381 required-opps = <&rpmpd_opp_svs>; 1382 opp-supported-hw = <0x1f>; 1383 }; 1384 1385 opp-600000000 { 1386 opp-hz = /bits/ 64 <600000000>; 1387 required-opps = <&rpmpd_opp_svs_plus>; 1388 opp-supported-hw = <0x1f>; 1389 }; 1390 1391 opp-745000000 { 1392 opp-hz = /bits/ 64 <745000000>; 1393 required-opps = <&rpmpd_opp_nom>; 1394 opp-supported-hw = <0xf>; 1395 }; 1396 1397 opp-820000000 { 1398 opp-hz = /bits/ 64 <820000000>; 1399 required-opps = <&rpmpd_opp_nom_plus>; 1400 opp-supported-hw = <0x7>; 1401 }; 1402 1403 opp-900000000 { 1404 opp-hz = /bits/ 64 <900000000>; 1405 required-opps = <&rpmpd_opp_turbo>; 1406 opp-supported-hw = <0x7>; 1407 }; 1408 1409 /* Speed bin 2 can reach 950 Mhz instead of 980 like the rest. */ 1410 opp-950000000 { 1411 opp-hz = /bits/ 64 <950000000>; 1412 required-opps = <&rpmpd_opp_turbo_plus>; 1413 opp-supported-hw = <0x4>; 1414 }; 1415 1416 opp-980000000 { 1417 opp-hz = /bits/ 64 <980000000>; 1418 required-opps = <&rpmpd_opp_turbo_plus>; 1419 opp-supported-hw = <0x3>; 1420 }; 1421 }; 1422 }; 1423 1424 gmu_wrapper: gmu@596a000 { 1425 compatible = "qcom,adreno-gmu-wrapper"; 1426 reg = <0x0 0x0596a000 0x0 0x30000>; 1427 reg-names = "gmu"; 1428 power-domains = <&gpucc GPU_CX_GDSC>, 1429 <&gpucc GPU_GX_GDSC>; 1430 power-domain-names = "cx", "gx"; 1431 }; 1432 1433 gpucc: clock-controller@5990000 { 1434 compatible = "qcom,sm6115-gpucc"; 1435 reg = <0x0 0x05990000 0x0 0x9000>; 1436 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 1437 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 1438 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 1439 #clock-cells = <1>; 1440 #reset-cells = <1>; 1441 #power-domain-cells = <1>; 1442 }; 1443 1444 adreno_smmu: iommu@59a0000 { 1445 compatible = "qcom,sm6115-smmu-500", "qcom,adreno-smmu", 1446 "qcom,smmu-500", "arm,mmu-500"; 1447 reg = <0x0 0x059a0000 0x0 0x10000>; 1448 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 1449 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 1450 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 1451 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 1452 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1453 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 1454 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, 1455 <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, 1456 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1457 1458 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1459 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 1460 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 1461 clock-names = "mem", 1462 "hlos", 1463 "iface"; 1464 power-domains = <&gpucc GPU_CX_GDSC>; 1465 1466 #global-interrupts = <1>; 1467 #iommu-cells = <2>; 1468 }; 1469 1470 mdss: display-subsystem@5e00000 { 1471 compatible = "qcom,sm6115-mdss"; 1472 reg = <0x0 0x05e00000 0x0 0x1000>; 1473 reg-names = "mdss"; 1474 1475 power-domains = <&dispcc MDSS_GDSC>; 1476 1477 clocks = <&gcc GCC_DISP_AHB_CLK>, 1478 <&gcc GCC_DISP_HF_AXI_CLK>, 1479 <&dispcc DISP_CC_MDSS_MDP_CLK>; 1480 1481 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 1482 interrupt-controller; 1483 #interrupt-cells = <1>; 1484 1485 iommus = <&apps_smmu 0x420 0x2>, 1486 <&apps_smmu 0x421 0x0>; 1487 1488 #address-cells = <2>; 1489 #size-cells = <2>; 1490 ranges; 1491 1492 status = "disabled"; 1493 1494 mdp: display-controller@5e01000 { 1495 compatible = "qcom,sm6115-dpu"; 1496 reg = <0x0 0x05e01000 0x0 0x8f000>, 1497 <0x0 0x05eb0000 0x0 0x2008>; 1498 reg-names = "mdp", "vbif"; 1499 1500 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 1501 <&dispcc DISP_CC_MDSS_AHB_CLK>, 1502 <&dispcc DISP_CC_MDSS_MDP_CLK>, 1503 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 1504 <&dispcc DISP_CC_MDSS_ROT_CLK>, 1505 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 1506 clock-names = "bus", 1507 "iface", 1508 "core", 1509 "lut", 1510 "rot", 1511 "vsync"; 1512 1513 operating-points-v2 = <&mdp_opp_table>; 1514 power-domains = <&rpmpd SM6115_VDDCX>; 1515 1516 interrupt-parent = <&mdss>; 1517 interrupts = <0>; 1518 1519 ports { 1520 #address-cells = <1>; 1521 #size-cells = <0>; 1522 1523 port@0 { 1524 reg = <0>; 1525 dpu_intf1_out: endpoint { 1526 remote-endpoint = <&mdss_dsi0_in>; 1527 }; 1528 }; 1529 }; 1530 1531 mdp_opp_table: opp-table { 1532 compatible = "operating-points-v2"; 1533 1534 opp-19200000 { 1535 opp-hz = /bits/ 64 <19200000>; 1536 required-opps = <&rpmpd_opp_min_svs>; 1537 }; 1538 1539 opp-192000000 { 1540 opp-hz = /bits/ 64 <192000000>; 1541 required-opps = <&rpmpd_opp_low_svs>; 1542 }; 1543 1544 opp-256000000 { 1545 opp-hz = /bits/ 64 <256000000>; 1546 required-opps = <&rpmpd_opp_svs>; 1547 }; 1548 1549 opp-307200000 { 1550 opp-hz = /bits/ 64 <307200000>; 1551 required-opps = <&rpmpd_opp_svs_plus>; 1552 }; 1553 1554 opp-384000000 { 1555 opp-hz = /bits/ 64 <384000000>; 1556 required-opps = <&rpmpd_opp_nom>; 1557 }; 1558 }; 1559 }; 1560 1561 mdss_dsi0: dsi@5e94000 { 1562 compatible = "qcom,sm6115-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 1563 reg = <0x0 0x05e94000 0x0 0x400>; 1564 reg-names = "dsi_ctrl"; 1565 1566 interrupt-parent = <&mdss>; 1567 interrupts = <4>; 1568 1569 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 1570 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 1571 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 1572 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 1573 <&dispcc DISP_CC_MDSS_AHB_CLK>, 1574 <&gcc GCC_DISP_HF_AXI_CLK>; 1575 clock-names = "byte", 1576 "byte_intf", 1577 "pixel", 1578 "core", 1579 "iface", 1580 "bus"; 1581 1582 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 1583 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 1584 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; 1585 1586 operating-points-v2 = <&dsi_opp_table>; 1587 power-domains = <&rpmpd SM6115_VDDCX>; 1588 phys = <&mdss_dsi0_phy>; 1589 1590 #address-cells = <1>; 1591 #size-cells = <0>; 1592 1593 status = "disabled"; 1594 1595 ports { 1596 #address-cells = <1>; 1597 #size-cells = <0>; 1598 1599 port@0 { 1600 reg = <0>; 1601 mdss_dsi0_in: endpoint { 1602 remote-endpoint = <&dpu_intf1_out>; 1603 }; 1604 }; 1605 1606 port@1 { 1607 reg = <1>; 1608 mdss_dsi0_out: endpoint { 1609 }; 1610 }; 1611 }; 1612 1613 dsi_opp_table: opp-table { 1614 compatible = "operating-points-v2"; 1615 1616 opp-19200000 { 1617 opp-hz = /bits/ 64 <19200000>; 1618 required-opps = <&rpmpd_opp_min_svs>; 1619 }; 1620 1621 opp-164000000 { 1622 opp-hz = /bits/ 64 <164000000>; 1623 required-opps = <&rpmpd_opp_low_svs>; 1624 }; 1625 1626 opp-187500000 { 1627 opp-hz = /bits/ 64 <187500000>; 1628 required-opps = <&rpmpd_opp_svs>; 1629 }; 1630 }; 1631 }; 1632 1633 mdss_dsi0_phy: phy@5e94400 { 1634 compatible = "qcom,dsi-phy-14nm-2290"; 1635 reg = <0x0 0x05e94400 0x0 0x100>, 1636 <0x0 0x05e94500 0x0 0x300>, 1637 <0x0 0x05e94800 0x0 0x188>; 1638 reg-names = "dsi_phy", 1639 "dsi_phy_lane", 1640 "dsi_pll"; 1641 1642 #clock-cells = <1>; 1643 #phy-cells = <0>; 1644 1645 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 1646 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1647 clock-names = "iface", "ref"; 1648 1649 status = "disabled"; 1650 }; 1651 }; 1652 1653 dispcc: clock-controller@5f00000 { 1654 compatible = "qcom,sm6115-dispcc"; 1655 reg = <0x0 0x05f00000 0 0x20000>; 1656 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 1657 <&sleep_clk>, 1658 <&mdss_dsi0_phy 0>, 1659 <&mdss_dsi0_phy 1>, 1660 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>; 1661 #clock-cells = <1>; 1662 #reset-cells = <1>; 1663 #power-domain-cells = <1>; 1664 }; 1665 1666 remoteproc_mpss: remoteproc@6080000 { 1667 compatible = "qcom,sm6115-mpss-pas"; 1668 reg = <0x0 0x06080000 0x0 0x100>; 1669 1670 interrupts-extended = <&intc GIC_SPI 307 IRQ_TYPE_EDGE_RISING>, 1671 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1672 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1673 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1674 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 1675 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 1676 interrupt-names = "wdog", "fatal", "ready", "handover", 1677 "stop-ack", "shutdown-ack"; 1678 1679 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 1680 clock-names = "xo"; 1681 1682 power-domains = <&rpmpd SM6115_VDDCX>; 1683 1684 memory-region = <&pil_modem_mem>; 1685 1686 qcom,smem-states = <&modem_smp2p_out 0>; 1687 qcom,smem-state-names = "stop"; 1688 1689 status = "disabled"; 1690 1691 glink-edge { 1692 interrupts = <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>; 1693 label = "mpss"; 1694 qcom,remote-pid = <1>; 1695 mboxes = <&apcs_glb 12>; 1696 }; 1697 }; 1698 1699 stm@8002000 { 1700 compatible = "arm,coresight-stm", "arm,primecell"; 1701 reg = <0x0 0x08002000 0x0 0x1000>, 1702 <0x0 0x0e280000 0x0 0x180000>; 1703 reg-names = "stm-base", "stm-stimulus-base"; 1704 1705 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1706 clock-names = "apb_pclk"; 1707 1708 status = "disabled"; 1709 1710 out-ports { 1711 port { 1712 stm_out: endpoint { 1713 remote-endpoint = <&funnel_in0_in>; 1714 }; 1715 }; 1716 }; 1717 }; 1718 1719 cti0: cti@8010000 { 1720 compatible = "arm,coresight-cti", "arm,primecell"; 1721 reg = <0x0 0x08010000 0x0 0x1000>; 1722 1723 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1724 clock-names = "apb_pclk"; 1725 1726 status = "disabled"; 1727 }; 1728 1729 cti1: cti@8011000 { 1730 compatible = "arm,coresight-cti", "arm,primecell"; 1731 reg = <0x0 0x08011000 0x0 0x1000>; 1732 1733 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1734 clock-names = "apb_pclk"; 1735 1736 status = "disabled"; 1737 }; 1738 1739 cti2: cti@8012000 { 1740 compatible = "arm,coresight-cti", "arm,primecell"; 1741 reg = <0x0 0x08012000 0x0 0x1000>; 1742 1743 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1744 clock-names = "apb_pclk"; 1745 1746 status = "disabled"; 1747 }; 1748 1749 cti3: cti@8013000 { 1750 compatible = "arm,coresight-cti", "arm,primecell"; 1751 reg = <0x0 0x08013000 0x0 0x1000>; 1752 1753 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1754 clock-names = "apb_pclk"; 1755 1756 status = "disabled"; 1757 }; 1758 1759 cti4: cti@8014000 { 1760 compatible = "arm,coresight-cti", "arm,primecell"; 1761 reg = <0x0 0x08014000 0x0 0x1000>; 1762 1763 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1764 clock-names = "apb_pclk"; 1765 1766 status = "disabled"; 1767 }; 1768 1769 cti5: cti@8015000 { 1770 compatible = "arm,coresight-cti", "arm,primecell"; 1771 reg = <0x0 0x08015000 0x0 0x1000>; 1772 1773 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1774 clock-names = "apb_pclk"; 1775 1776 status = "disabled"; 1777 }; 1778 1779 cti6: cti@8016000 { 1780 compatible = "arm,coresight-cti", "arm,primecell"; 1781 reg = <0x0 0x08016000 0x0 0x1000>; 1782 1783 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1784 clock-names = "apb_pclk"; 1785 1786 status = "disabled"; 1787 }; 1788 1789 cti7: cti@8017000 { 1790 compatible = "arm,coresight-cti", "arm,primecell"; 1791 reg = <0x0 0x08017000 0x0 0x1000>; 1792 1793 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1794 clock-names = "apb_pclk"; 1795 1796 status = "disabled"; 1797 }; 1798 1799 cti8: cti@8018000 { 1800 compatible = "arm,coresight-cti", "arm,primecell"; 1801 reg = <0x0 0x08018000 0x0 0x1000>; 1802 1803 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1804 clock-names = "apb_pclk"; 1805 1806 status = "disabled"; 1807 }; 1808 1809 cti9: cti@8019000 { 1810 compatible = "arm,coresight-cti", "arm,primecell"; 1811 reg = <0x0 0x08019000 0x0 0x1000>; 1812 1813 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1814 clock-names = "apb_pclk"; 1815 1816 status = "disabled"; 1817 }; 1818 1819 cti10: cti@801a000 { 1820 compatible = "arm,coresight-cti", "arm,primecell"; 1821 reg = <0x0 0x0801a000 0x0 0x1000>; 1822 1823 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1824 clock-names = "apb_pclk"; 1825 1826 status = "disabled"; 1827 }; 1828 1829 cti11: cti@801b000 { 1830 compatible = "arm,coresight-cti", "arm,primecell"; 1831 reg = <0x0 0x0801b000 0x0 0x1000>; 1832 1833 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1834 clock-names = "apb_pclk"; 1835 1836 status = "disabled"; 1837 }; 1838 1839 cti12: cti@801c000 { 1840 compatible = "arm,coresight-cti", "arm,primecell"; 1841 reg = <0x0 0x0801c000 0x0 0x1000>; 1842 1843 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1844 clock-names = "apb_pclk"; 1845 1846 status = "disabled"; 1847 }; 1848 1849 cti13: cti@801d000 { 1850 compatible = "arm,coresight-cti", "arm,primecell"; 1851 reg = <0x0 0x0801d000 0x0 0x1000>; 1852 1853 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1854 clock-names = "apb_pclk"; 1855 1856 status = "disabled"; 1857 }; 1858 1859 cti14: cti@801e000 { 1860 compatible = "arm,coresight-cti", "arm,primecell"; 1861 reg = <0x0 0x0801e000 0x0 0x1000>; 1862 1863 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1864 clock-names = "apb_pclk"; 1865 1866 status = "disabled"; 1867 }; 1868 1869 cti15: cti@801f000 { 1870 compatible = "arm,coresight-cti", "arm,primecell"; 1871 reg = <0x0 0x0801f000 0x0 0x1000>; 1872 1873 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1874 clock-names = "apb_pclk"; 1875 1876 status = "disabled"; 1877 }; 1878 1879 replicator@8046000 { 1880 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 1881 reg = <0x0 0x08046000 0x0 0x1000>; 1882 1883 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1884 clock-names = "apb_pclk"; 1885 1886 status = "disabled"; 1887 1888 out-ports { 1889 port { 1890 replicator_out: endpoint { 1891 remote-endpoint = <&etr_in>; 1892 }; 1893 }; 1894 }; 1895 1896 in-ports { 1897 port { 1898 replicator_in: endpoint { 1899 remote-endpoint = <&etf_out>; 1900 }; 1901 }; 1902 }; 1903 }; 1904 1905 etf@8047000 { 1906 compatible = "arm,coresight-tmc", "arm,primecell"; 1907 reg = <0x0 0x08047000 0x0 0x1000>; 1908 1909 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1910 clock-names = "apb_pclk"; 1911 1912 status = "disabled"; 1913 1914 in-ports { 1915 port { 1916 etf_in: endpoint { 1917 remote-endpoint = <&merge_funnel_out>; 1918 }; 1919 }; 1920 }; 1921 1922 out-ports { 1923 port { 1924 etf_out: endpoint { 1925 remote-endpoint = <&replicator_in>; 1926 }; 1927 }; 1928 }; 1929 }; 1930 1931 etr@8048000 { 1932 compatible = "arm,coresight-tmc", "arm,primecell"; 1933 reg = <0x0 0x08048000 0x0 0x1000>; 1934 1935 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1936 clock-names = "apb_pclk"; 1937 1938 status = "disabled"; 1939 1940 in-ports { 1941 port { 1942 etr_in: endpoint { 1943 remote-endpoint = <&replicator_out>; 1944 }; 1945 }; 1946 }; 1947 }; 1948 1949 funnel@8041000 { 1950 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1951 reg = <0x0 0x08041000 0x0 0x1000>; 1952 1953 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1954 clock-names = "apb_pclk"; 1955 1956 status = "disabled"; 1957 1958 out-ports { 1959 port { 1960 funnel_in0_out: endpoint { 1961 remote-endpoint = <&merge_funnel_in0>; 1962 }; 1963 }; 1964 }; 1965 1966 in-ports { 1967 port { 1968 funnel_in0_in: endpoint { 1969 remote-endpoint = <&stm_out>; 1970 }; 1971 }; 1972 }; 1973 }; 1974 1975 funnel@8042000 { 1976 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1977 reg = <0x0 0x08042000 0x0 0x1000>; 1978 1979 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1980 clock-names = "apb_pclk"; 1981 1982 status = "disabled"; 1983 1984 out-ports { 1985 port { 1986 funnel_in1_out: endpoint { 1987 remote-endpoint = <&merge_funnel_in1>; 1988 }; 1989 }; 1990 }; 1991 1992 in-ports { 1993 port { 1994 funnel_in1_in: endpoint { 1995 remote-endpoint = <&funnel_apss1_out>; 1996 }; 1997 }; 1998 }; 1999 }; 2000 2001 funnel@8045000 { 2002 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2003 reg = <0x0 0x08045000 0x0 0x1000>; 2004 2005 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2006 clock-names = "apb_pclk"; 2007 2008 status = "disabled"; 2009 2010 out-ports { 2011 port { 2012 merge_funnel_out: endpoint { 2013 remote-endpoint = <&etf_in>; 2014 }; 2015 }; 2016 }; 2017 2018 in-ports { 2019 #address-cells = <1>; 2020 #size-cells = <0>; 2021 2022 port@0 { 2023 reg = <0>; 2024 merge_funnel_in0: endpoint { 2025 remote-endpoint = <&funnel_in0_out>; 2026 }; 2027 }; 2028 2029 port@1 { 2030 reg = <1>; 2031 merge_funnel_in1: endpoint { 2032 remote-endpoint = <&funnel_in1_out>; 2033 }; 2034 }; 2035 }; 2036 }; 2037 2038 etm@9040000 { 2039 compatible = "arm,coresight-etm4x", "arm,primecell"; 2040 reg = <0x0 0x09040000 0x0 0x1000>; 2041 2042 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2043 clock-names = "apb_pclk"; 2044 arm,coresight-loses-context-with-cpu; 2045 2046 cpu = <&CPU0>; 2047 2048 status = "disabled"; 2049 2050 out-ports { 2051 port { 2052 etm0_out: endpoint { 2053 remote-endpoint = <&funnel_apss0_in0>; 2054 }; 2055 }; 2056 }; 2057 }; 2058 2059 etm@9140000 { 2060 compatible = "arm,coresight-etm4x", "arm,primecell"; 2061 reg = <0x0 0x09140000 0x0 0x1000>; 2062 2063 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2064 clock-names = "apb_pclk"; 2065 arm,coresight-loses-context-with-cpu; 2066 2067 cpu = <&CPU1>; 2068 2069 status = "disabled"; 2070 2071 out-ports { 2072 port { 2073 etm1_out: endpoint { 2074 remote-endpoint = <&funnel_apss0_in1>; 2075 }; 2076 }; 2077 }; 2078 }; 2079 2080 etm@9240000 { 2081 compatible = "arm,coresight-etm4x", "arm,primecell"; 2082 reg = <0x0 0x09240000 0x0 0x1000>; 2083 2084 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2085 clock-names = "apb_pclk"; 2086 arm,coresight-loses-context-with-cpu; 2087 2088 cpu = <&CPU2>; 2089 2090 status = "disabled"; 2091 2092 out-ports { 2093 port { 2094 etm2_out: endpoint { 2095 remote-endpoint = <&funnel_apss0_in2>; 2096 }; 2097 }; 2098 }; 2099 }; 2100 2101 etm@9340000 { 2102 compatible = "arm,coresight-etm4x", "arm,primecell"; 2103 reg = <0x0 0x09340000 0x0 0x1000>; 2104 2105 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2106 clock-names = "apb_pclk"; 2107 arm,coresight-loses-context-with-cpu; 2108 2109 cpu = <&CPU3>; 2110 2111 status = "disabled"; 2112 2113 out-ports { 2114 port { 2115 etm3_out: endpoint { 2116 remote-endpoint = <&funnel_apss0_in3>; 2117 }; 2118 }; 2119 }; 2120 }; 2121 2122 etm@9440000 { 2123 compatible = "arm,coresight-etm4x", "arm,primecell"; 2124 reg = <0x0 0x09440000 0x0 0x1000>; 2125 2126 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2127 clock-names = "apb_pclk"; 2128 arm,coresight-loses-context-with-cpu; 2129 2130 cpu = <&CPU4>; 2131 2132 status = "disabled"; 2133 2134 out-ports { 2135 port { 2136 etm4_out: endpoint { 2137 remote-endpoint = <&funnel_apss0_in4>; 2138 }; 2139 }; 2140 }; 2141 }; 2142 2143 etm@9540000 { 2144 compatible = "arm,coresight-etm4x", "arm,primecell"; 2145 reg = <0x0 0x09540000 0x0 0x1000>; 2146 2147 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2148 clock-names = "apb_pclk"; 2149 arm,coresight-loses-context-with-cpu; 2150 2151 cpu = <&CPU5>; 2152 2153 status = "disabled"; 2154 2155 out-ports { 2156 port { 2157 etm5_out: endpoint { 2158 remote-endpoint = <&funnel_apss0_in5>; 2159 }; 2160 }; 2161 }; 2162 }; 2163 2164 etm@9640000 { 2165 compatible = "arm,coresight-etm4x", "arm,primecell"; 2166 reg = <0x0 0x09640000 0x0 0x1000>; 2167 2168 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2169 clock-names = "apb_pclk"; 2170 arm,coresight-loses-context-with-cpu; 2171 2172 cpu = <&CPU6>; 2173 2174 status = "disabled"; 2175 2176 out-ports { 2177 port { 2178 etm6_out: endpoint { 2179 remote-endpoint = <&funnel_apss0_in6>; 2180 }; 2181 }; 2182 }; 2183 }; 2184 2185 etm@9740000 { 2186 compatible = "arm,coresight-etm4x", "arm,primecell"; 2187 reg = <0x0 0x09740000 0x0 0x1000>; 2188 2189 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2190 clock-names = "apb_pclk"; 2191 arm,coresight-loses-context-with-cpu; 2192 2193 cpu = <&CPU7>; 2194 2195 status = "disabled"; 2196 2197 out-ports { 2198 port { 2199 etm7_out: endpoint { 2200 remote-endpoint = <&funnel_apss0_in7>; 2201 }; 2202 }; 2203 }; 2204 }; 2205 2206 funnel@9800000 { 2207 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2208 reg = <0x0 0x09800000 0x0 0x1000>; 2209 2210 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2211 clock-names = "apb_pclk"; 2212 2213 status = "disabled"; 2214 2215 out-ports { 2216 port { 2217 funnel_apss0_out: endpoint { 2218 remote-endpoint = <&funnel_apss1_in>; 2219 }; 2220 }; 2221 }; 2222 2223 in-ports { 2224 #address-cells = <1>; 2225 #size-cells = <0>; 2226 2227 port@0 { 2228 reg = <0>; 2229 funnel_apss0_in0: endpoint { 2230 remote-endpoint = <&etm0_out>; 2231 }; 2232 }; 2233 2234 port@1 { 2235 reg = <1>; 2236 funnel_apss0_in1: endpoint { 2237 remote-endpoint = <&etm1_out>; 2238 }; 2239 }; 2240 2241 port@2 { 2242 reg = <2>; 2243 funnel_apss0_in2: endpoint { 2244 remote-endpoint = <&etm2_out>; 2245 }; 2246 }; 2247 2248 port@3 { 2249 reg = <3>; 2250 funnel_apss0_in3: endpoint { 2251 remote-endpoint = <&etm3_out>; 2252 }; 2253 }; 2254 2255 port@4 { 2256 reg = <4>; 2257 funnel_apss0_in4: endpoint { 2258 remote-endpoint = <&etm4_out>; 2259 }; 2260 }; 2261 2262 port@5 { 2263 reg = <5>; 2264 funnel_apss0_in5: endpoint { 2265 remote-endpoint = <&etm5_out>; 2266 }; 2267 }; 2268 2269 port@6 { 2270 reg = <6>; 2271 funnel_apss0_in6: endpoint { 2272 remote-endpoint = <&etm6_out>; 2273 }; 2274 }; 2275 2276 port@7 { 2277 reg = <7>; 2278 funnel_apss0_in7: endpoint { 2279 remote-endpoint = <&etm7_out>; 2280 }; 2281 }; 2282 }; 2283 }; 2284 2285 funnel@9810000 { 2286 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2287 reg = <0x0 0x09810000 0x0 0x1000>; 2288 2289 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2290 clock-names = "apb_pclk"; 2291 2292 status = "disabled"; 2293 2294 out-ports { 2295 port { 2296 funnel_apss1_out: endpoint { 2297 remote-endpoint = <&funnel_in1_in>; 2298 }; 2299 }; 2300 }; 2301 2302 in-ports { 2303 port { 2304 funnel_apss1_in: endpoint { 2305 remote-endpoint = <&funnel_apss0_out>; 2306 }; 2307 }; 2308 }; 2309 }; 2310 2311 remoteproc_adsp: remoteproc@ab00000 { 2312 compatible = "qcom,sm6115-adsp-pas"; 2313 reg = <0x0 0x0ab00000 0x0 0x100>; 2314 2315 interrupts-extended = <&intc GIC_SPI 282 IRQ_TYPE_EDGE_RISING>, 2316 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2317 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2318 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2319 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2320 interrupt-names = "wdog", "fatal", "ready", 2321 "handover", "stop-ack"; 2322 2323 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 2324 clock-names = "xo"; 2325 2326 power-domains = <&rpmpd SM6115_VDD_LPI_CX>, 2327 <&rpmpd SM6115_VDD_LPI_MX>; 2328 2329 memory-region = <&pil_adsp_mem>; 2330 2331 qcom,smem-states = <&adsp_smp2p_out 0>; 2332 qcom,smem-state-names = "stop"; 2333 2334 status = "disabled"; 2335 2336 glink-edge { 2337 interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>; 2338 label = "lpass"; 2339 qcom,remote-pid = <2>; 2340 mboxes = <&apcs_glb 8>; 2341 2342 fastrpc { 2343 compatible = "qcom,fastrpc"; 2344 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2345 label = "adsp"; 2346 qcom,non-secure-domain; 2347 #address-cells = <1>; 2348 #size-cells = <0>; 2349 2350 compute-cb@3 { 2351 compatible = "qcom,fastrpc-compute-cb"; 2352 reg = <3>; 2353 iommus = <&apps_smmu 0x01c3 0x0>; 2354 }; 2355 2356 compute-cb@4 { 2357 compatible = "qcom,fastrpc-compute-cb"; 2358 reg = <4>; 2359 iommus = <&apps_smmu 0x01c4 0x0>; 2360 }; 2361 2362 compute-cb@5 { 2363 compatible = "qcom,fastrpc-compute-cb"; 2364 reg = <5>; 2365 iommus = <&apps_smmu 0x01c5 0x0>; 2366 }; 2367 2368 compute-cb@6 { 2369 compatible = "qcom,fastrpc-compute-cb"; 2370 reg = <6>; 2371 iommus = <&apps_smmu 0x01c6 0x0>; 2372 }; 2373 2374 compute-cb@7 { 2375 compatible = "qcom,fastrpc-compute-cb"; 2376 reg = <7>; 2377 iommus = <&apps_smmu 0x01c7 0x0>; 2378 }; 2379 }; 2380 }; 2381 }; 2382 2383 remoteproc_cdsp: remoteproc@b300000 { 2384 compatible = "qcom,sm6115-cdsp-pas"; 2385 reg = <0x0 0x0b300000 0x0 0x100000>; 2386 2387 interrupts-extended = <&intc GIC_SPI 265 IRQ_TYPE_EDGE_RISING>, 2388 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2389 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2390 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2391 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2392 interrupt-names = "wdog", "fatal", "ready", 2393 "handover", "stop-ack"; 2394 2395 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 2396 clock-names = "xo"; 2397 2398 power-domains = <&rpmpd SM6115_VDDCX>; 2399 2400 memory-region = <&pil_cdsp_mem>; 2401 2402 qcom,smem-states = <&cdsp_smp2p_out 0>; 2403 qcom,smem-state-names = "stop"; 2404 2405 status = "disabled"; 2406 2407 glink-edge { 2408 interrupts = <GIC_SPI 261 IRQ_TYPE_EDGE_RISING>; 2409 label = "cdsp"; 2410 qcom,remote-pid = <5>; 2411 mboxes = <&apcs_glb 28>; 2412 2413 fastrpc { 2414 compatible = "qcom,fastrpc"; 2415 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2416 label = "cdsp"; 2417 qcom,non-secure-domain; 2418 #address-cells = <1>; 2419 #size-cells = <0>; 2420 2421 compute-cb@1 { 2422 compatible = "qcom,fastrpc-compute-cb"; 2423 reg = <1>; 2424 iommus = <&apps_smmu 0x0c01 0x0>; 2425 }; 2426 2427 compute-cb@2 { 2428 compatible = "qcom,fastrpc-compute-cb"; 2429 reg = <2>; 2430 iommus = <&apps_smmu 0x0c02 0x0>; 2431 }; 2432 2433 compute-cb@3 { 2434 compatible = "qcom,fastrpc-compute-cb"; 2435 reg = <3>; 2436 iommus = <&apps_smmu 0x0c03 0x0>; 2437 }; 2438 2439 compute-cb@4 { 2440 compatible = "qcom,fastrpc-compute-cb"; 2441 reg = <4>; 2442 iommus = <&apps_smmu 0x0c04 0x0>; 2443 }; 2444 2445 compute-cb@5 { 2446 compatible = "qcom,fastrpc-compute-cb"; 2447 reg = <5>; 2448 iommus = <&apps_smmu 0x0c05 0x0>; 2449 }; 2450 2451 compute-cb@6 { 2452 compatible = "qcom,fastrpc-compute-cb"; 2453 reg = <6>; 2454 iommus = <&apps_smmu 0x0c06 0x0>; 2455 }; 2456 2457 /* note: secure cb9 in downstream */ 2458 }; 2459 }; 2460 }; 2461 2462 apps_smmu: iommu@c600000 { 2463 compatible = "qcom,sm6115-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 2464 reg = <0x0 0x0c600000 0x0 0x80000>; 2465 #iommu-cells = <2>; 2466 #global-interrupts = <1>; 2467 2468 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 2469 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 2470 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 2471 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 2472 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 2473 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 2474 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 2475 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 2476 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 2477 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 2478 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 2479 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 2480 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 2481 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 2482 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 2483 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 2484 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 2485 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 2486 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 2487 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 2488 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 2489 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 2490 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 2491 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 2492 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 2493 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 2494 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 2495 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 2496 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 2497 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 2498 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 2499 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 2500 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 2501 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 2502 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 2503 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 2504 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 2505 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 2506 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 2507 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 2508 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 2509 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 2510 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 2511 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 2512 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 2513 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 2514 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 2515 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 2516 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 2517 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 2518 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 2519 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 2520 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 2521 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 2522 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 2523 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 2524 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 2525 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 2526 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 2527 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 2528 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 2529 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 2530 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 2531 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 2532 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 2533 }; 2534 2535 wifi: wifi@c800000 { 2536 compatible = "qcom,wcn3990-wifi"; 2537 reg = <0x0 0x0c800000 0x0 0x800000>; 2538 reg-names = "membase"; 2539 memory-region = <&wlan_msa_mem>; 2540 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, 2541 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, 2542 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, 2543 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>, 2544 <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>, 2545 <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>, 2546 <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>, 2547 <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>, 2548 <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>, 2549 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>, 2550 <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, 2551 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 2552 iommus = <&apps_smmu 0x1a0 0x1>; 2553 qcom,msa-fixed-perm; 2554 status = "disabled"; 2555 }; 2556 2557 watchdog@f017000 { 2558 compatible = "qcom,apss-wdt-sm6115", "qcom,kpss-wdt"; 2559 reg = <0x0 0x0f017000 0x0 0x1000>; 2560 clocks = <&sleep_clk>; 2561 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 2562 }; 2563 2564 apcs_glb: mailbox@f111000 { 2565 compatible = "qcom,sm6115-apcs-hmss-global", 2566 "qcom,msm8994-apcs-kpss-global"; 2567 reg = <0x0 0x0f111000 0x0 0x1000>; 2568 2569 #mbox-cells = <1>; 2570 }; 2571 2572 timer@f120000 { 2573 compatible = "arm,armv7-timer-mem"; 2574 reg = <0x0 0x0f120000 0x0 0x1000>; 2575 #address-cells = <2>; 2576 #size-cells = <2>; 2577 ranges; 2578 clock-frequency = <19200000>; 2579 2580 frame@f121000 { 2581 reg = <0x0 0x0f121000 0x0 0x1000>, <0x0 0x0f122000 0x0 0x1000>; 2582 frame-number = <0>; 2583 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 2584 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 2585 }; 2586 2587 frame@f123000 { 2588 reg = <0x0 0x0f123000 0x0 0x1000>; 2589 frame-number = <1>; 2590 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 2591 status = "disabled"; 2592 }; 2593 2594 frame@f124000 { 2595 reg = <0x0 0x0f124000 0x0 0x1000>; 2596 frame-number = <2>; 2597 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 2598 status = "disabled"; 2599 }; 2600 2601 frame@f125000 { 2602 reg = <0x0 0x0f125000 0x0 0x1000>; 2603 frame-number = <3>; 2604 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 2605 status = "disabled"; 2606 }; 2607 2608 frame@f126000 { 2609 reg = <0x0 0x0f126000 0x0 0x1000>; 2610 frame-number = <4>; 2611 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 2612 status = "disabled"; 2613 }; 2614 2615 frame@f127000 { 2616 reg = <0x0 0x0f127000 0x0 0x1000>; 2617 frame-number = <5>; 2618 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 2619 status = "disabled"; 2620 }; 2621 2622 frame@f128000 { 2623 reg = <0x0 0x0f128000 0x0 0x1000>; 2624 frame-number = <6>; 2625 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 2626 status = "disabled"; 2627 }; 2628 }; 2629 2630 intc: interrupt-controller@f200000 { 2631 compatible = "arm,gic-v3"; 2632 reg = <0x0 0x0f200000 0x0 0x10000>, 2633 <0x0 0x0f300000 0x0 0x100000>; 2634 #interrupt-cells = <3>; 2635 interrupt-controller; 2636 interrupt-parent = <&intc>; 2637 #redistributor-regions = <1>; 2638 redistributor-stride = <0x0 0x20000>; 2639 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 2640 }; 2641 2642 cpufreq_hw: cpufreq@f521000 { 2643 compatible = "qcom,sm6115-cpufreq-hw", "qcom,cpufreq-hw"; 2644 reg = <0x0 0x0f521000 0x0 0x1000>, 2645 <0x0 0x0f523000 0x0 0x1000>; 2646 2647 reg-names = "freq-domain0", "freq-domain1"; 2648 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>; 2649 clock-names = "xo", "alternate"; 2650 2651 #freq-domain-cells = <1>; 2652 #clock-cells = <1>; 2653 }; 2654 }; 2655 2656 thermal-zones { 2657 mapss-thermal { 2658 polling-delay-passive = <0>; 2659 polling-delay = <0>; 2660 thermal-sensors = <&tsens0 0>; 2661 2662 trips { 2663 trip-point0 { 2664 temperature = <115000>; 2665 hysteresis = <5000>; 2666 type = "passive"; 2667 }; 2668 2669 trip-point1 { 2670 temperature = <125000>; 2671 hysteresis = <1000>; 2672 type = "passive"; 2673 }; 2674 }; 2675 }; 2676 2677 cdsp-hvx-thermal { 2678 polling-delay-passive = <0>; 2679 polling-delay = <0>; 2680 thermal-sensors = <&tsens0 1>; 2681 2682 trips { 2683 trip-point0 { 2684 temperature = <115000>; 2685 hysteresis = <5000>; 2686 type = "passive"; 2687 }; 2688 2689 trip-point1 { 2690 temperature = <125000>; 2691 hysteresis = <1000>; 2692 type = "passive"; 2693 }; 2694 }; 2695 }; 2696 2697 wlan-thermal { 2698 polling-delay-passive = <0>; 2699 polling-delay = <0>; 2700 thermal-sensors = <&tsens0 2>; 2701 2702 trips { 2703 trip-point0 { 2704 temperature = <115000>; 2705 hysteresis = <5000>; 2706 type = "passive"; 2707 }; 2708 2709 trip-point1 { 2710 temperature = <125000>; 2711 hysteresis = <1000>; 2712 type = "passive"; 2713 }; 2714 }; 2715 }; 2716 2717 camera-thermal { 2718 polling-delay-passive = <0>; 2719 polling-delay = <0>; 2720 thermal-sensors = <&tsens0 3>; 2721 2722 trips { 2723 trip-point0 { 2724 temperature = <115000>; 2725 hysteresis = <5000>; 2726 type = "passive"; 2727 }; 2728 2729 trip-point1 { 2730 temperature = <125000>; 2731 hysteresis = <1000>; 2732 type = "passive"; 2733 }; 2734 }; 2735 }; 2736 2737 video-thermal { 2738 polling-delay-passive = <0>; 2739 polling-delay = <0>; 2740 thermal-sensors = <&tsens0 4>; 2741 2742 trips { 2743 trip-point0 { 2744 temperature = <115000>; 2745 hysteresis = <5000>; 2746 type = "passive"; 2747 }; 2748 2749 trip-point1 { 2750 temperature = <125000>; 2751 hysteresis = <1000>; 2752 type = "passive"; 2753 }; 2754 }; 2755 }; 2756 2757 modem1-thermal { 2758 polling-delay-passive = <0>; 2759 polling-delay = <0>; 2760 thermal-sensors = <&tsens0 5>; 2761 2762 trips { 2763 trip-point0 { 2764 temperature = <115000>; 2765 hysteresis = <5000>; 2766 type = "passive"; 2767 }; 2768 2769 trip-point1 { 2770 temperature = <125000>; 2771 hysteresis = <1000>; 2772 type = "passive"; 2773 }; 2774 }; 2775 }; 2776 2777 cpu4-thermal { 2778 polling-delay-passive = <0>; 2779 polling-delay = <0>; 2780 thermal-sensors = <&tsens0 6>; 2781 2782 trips { 2783 cpu4_alert0: trip-point0 { 2784 temperature = <90000>; 2785 hysteresis = <2000>; 2786 type = "passive"; 2787 }; 2788 2789 cpu4_alert1: trip-point1 { 2790 temperature = <95000>; 2791 hysteresis = <2000>; 2792 type = "passive"; 2793 }; 2794 2795 cpu4_crit: cpu_crit { 2796 temperature = <110000>; 2797 hysteresis = <1000>; 2798 type = "critical"; 2799 }; 2800 }; 2801 }; 2802 2803 cpu5-thermal { 2804 polling-delay-passive = <0>; 2805 polling-delay = <0>; 2806 thermal-sensors = <&tsens0 7>; 2807 2808 trips { 2809 cpu5_alert0: trip-point0 { 2810 temperature = <90000>; 2811 hysteresis = <2000>; 2812 type = "passive"; 2813 }; 2814 2815 cpu5_alert1: trip-point1 { 2816 temperature = <95000>; 2817 hysteresis = <2000>; 2818 type = "passive"; 2819 }; 2820 2821 cpu5_crit: cpu_crit { 2822 temperature = <110000>; 2823 hysteresis = <1000>; 2824 type = "critical"; 2825 }; 2826 }; 2827 }; 2828 2829 cpu6-thermal { 2830 polling-delay-passive = <0>; 2831 polling-delay = <0>; 2832 thermal-sensors = <&tsens0 8>; 2833 2834 trips { 2835 cpu6_alert0: trip-point0 { 2836 temperature = <90000>; 2837 hysteresis = <2000>; 2838 type = "passive"; 2839 }; 2840 2841 cpu6_alert1: trip-point1 { 2842 temperature = <95000>; 2843 hysteresis = <2000>; 2844 type = "passive"; 2845 }; 2846 2847 cpu6_crit: cpu_crit { 2848 temperature = <110000>; 2849 hysteresis = <1000>; 2850 type = "critical"; 2851 }; 2852 }; 2853 }; 2854 2855 cpu7-thermal { 2856 polling-delay-passive = <0>; 2857 polling-delay = <0>; 2858 thermal-sensors = <&tsens0 9>; 2859 2860 trips { 2861 cpu7_alert0: trip-point0 { 2862 temperature = <90000>; 2863 hysteresis = <2000>; 2864 type = "passive"; 2865 }; 2866 2867 cpu7_alert1: trip-point1 { 2868 temperature = <95000>; 2869 hysteresis = <2000>; 2870 type = "passive"; 2871 }; 2872 2873 cpu7_crit: cpu_crit { 2874 temperature = <110000>; 2875 hysteresis = <1000>; 2876 type = "critical"; 2877 }; 2878 }; 2879 }; 2880 2881 cpu45-thermal { 2882 polling-delay-passive = <0>; 2883 polling-delay = <0>; 2884 thermal-sensors = <&tsens0 10>; 2885 2886 trips { 2887 cpu45_alert0: trip-point0 { 2888 temperature = <90000>; 2889 hysteresis = <2000>; 2890 type = "passive"; 2891 }; 2892 2893 cpu45_alert1: trip-point1 { 2894 temperature = <95000>; 2895 hysteresis = <2000>; 2896 type = "passive"; 2897 }; 2898 2899 cpu45_crit: cpu_crit { 2900 temperature = <110000>; 2901 hysteresis = <1000>; 2902 type = "critical"; 2903 }; 2904 }; 2905 }; 2906 2907 cpu67-thermal { 2908 polling-delay-passive = <0>; 2909 polling-delay = <0>; 2910 thermal-sensors = <&tsens0 11>; 2911 2912 trips { 2913 cpu67_alert0: trip-point0 { 2914 temperature = <90000>; 2915 hysteresis = <2000>; 2916 type = "passive"; 2917 }; 2918 2919 cpu67_alert1: trip-point1 { 2920 temperature = <95000>; 2921 hysteresis = <2000>; 2922 type = "passive"; 2923 }; 2924 2925 cpu67_crit: cpu_crit { 2926 temperature = <110000>; 2927 hysteresis = <1000>; 2928 type = "critical"; 2929 }; 2930 }; 2931 }; 2932 2933 cpu0123-thermal { 2934 polling-delay-passive = <0>; 2935 polling-delay = <0>; 2936 thermal-sensors = <&tsens0 12>; 2937 2938 trips { 2939 cpu0123_alert0: trip-point0 { 2940 temperature = <90000>; 2941 hysteresis = <2000>; 2942 type = "passive"; 2943 }; 2944 2945 cpu0123_alert1: trip-point1 { 2946 temperature = <95000>; 2947 hysteresis = <2000>; 2948 type = "passive"; 2949 }; 2950 2951 cpu0123_crit: cpu_crit { 2952 temperature = <110000>; 2953 hysteresis = <1000>; 2954 type = "critical"; 2955 }; 2956 }; 2957 }; 2958 2959 modem0-thermal { 2960 polling-delay-passive = <0>; 2961 polling-delay = <0>; 2962 thermal-sensors = <&tsens0 13>; 2963 2964 trips { 2965 trip-point0 { 2966 temperature = <115000>; 2967 hysteresis = <5000>; 2968 type = "passive"; 2969 }; 2970 2971 trip-point1 { 2972 temperature = <125000>; 2973 hysteresis = <1000>; 2974 type = "passive"; 2975 }; 2976 }; 2977 }; 2978 2979 display-thermal { 2980 polling-delay-passive = <0>; 2981 polling-delay = <0>; 2982 thermal-sensors = <&tsens0 14>; 2983 2984 trips { 2985 trip-point0 { 2986 temperature = <115000>; 2987 hysteresis = <5000>; 2988 type = "passive"; 2989 }; 2990 2991 trip-point1 { 2992 temperature = <125000>; 2993 hysteresis = <1000>; 2994 type = "passive"; 2995 }; 2996 }; 2997 }; 2998 2999 gpu-thermal { 3000 polling-delay-passive = <0>; 3001 polling-delay = <0>; 3002 thermal-sensors = <&tsens0 15>; 3003 3004 trips { 3005 trip-point0 { 3006 temperature = <115000>; 3007 hysteresis = <5000>; 3008 type = "passive"; 3009 }; 3010 3011 trip-point1 { 3012 temperature = <125000>; 3013 hysteresis = <1000>; 3014 type = "passive"; 3015 }; 3016 }; 3017 }; 3018 }; 3019 3020 timer { 3021 compatible = "arm,armv8-timer"; 3022 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 3023 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 3024 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 3025 <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 3026 }; 3027}; 3028