1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright (c) 2021, Iskren Chernev <iskren.chernev@gmail.com> 4 */ 5 6#include <dt-bindings/clock/qcom,gcc-sm6115.h> 7#include <dt-bindings/clock/qcom,sm6115-dispcc.h> 8#include <dt-bindings/clock/qcom,sm6115-gpucc.h> 9#include <dt-bindings/clock/qcom,rpmcc.h> 10#include <dt-bindings/dma/qcom-gpi.h> 11#include <dt-bindings/firmware/qcom,scm.h> 12#include <dt-bindings/gpio/gpio.h> 13#include <dt-bindings/interrupt-controller/arm-gic.h> 14#include <dt-bindings/power/qcom-rpmpd.h> 15 16/ { 17 interrupt-parent = <&intc>; 18 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 chosen { }; 23 24 clocks { 25 xo_board: xo-board { 26 compatible = "fixed-clock"; 27 #clock-cells = <0>; 28 }; 29 30 sleep_clk: sleep-clk { 31 compatible = "fixed-clock"; 32 #clock-cells = <0>; 33 }; 34 }; 35 36 cpus { 37 #address-cells = <2>; 38 #size-cells = <0>; 39 40 CPU0: cpu@0 { 41 device_type = "cpu"; 42 compatible = "qcom,kryo260"; 43 reg = <0x0 0x0>; 44 clocks = <&cpufreq_hw 0>; 45 capacity-dmips-mhz = <1024>; 46 dynamic-power-coefficient = <100>; 47 enable-method = "psci"; 48 next-level-cache = <&L2_0>; 49 qcom,freq-domain = <&cpufreq_hw 0>; 50 power-domains = <&CPU_PD0>; 51 power-domain-names = "psci"; 52 L2_0: l2-cache { 53 compatible = "cache"; 54 cache-level = <2>; 55 cache-unified; 56 }; 57 }; 58 59 CPU1: cpu@1 { 60 device_type = "cpu"; 61 compatible = "qcom,kryo260"; 62 reg = <0x0 0x1>; 63 clocks = <&cpufreq_hw 0>; 64 capacity-dmips-mhz = <1024>; 65 dynamic-power-coefficient = <100>; 66 enable-method = "psci"; 67 next-level-cache = <&L2_0>; 68 qcom,freq-domain = <&cpufreq_hw 0>; 69 power-domains = <&CPU_PD1>; 70 power-domain-names = "psci"; 71 }; 72 73 CPU2: cpu@2 { 74 device_type = "cpu"; 75 compatible = "qcom,kryo260"; 76 reg = <0x0 0x2>; 77 clocks = <&cpufreq_hw 0>; 78 capacity-dmips-mhz = <1024>; 79 dynamic-power-coefficient = <100>; 80 enable-method = "psci"; 81 next-level-cache = <&L2_0>; 82 qcom,freq-domain = <&cpufreq_hw 0>; 83 power-domains = <&CPU_PD2>; 84 power-domain-names = "psci"; 85 }; 86 87 CPU3: cpu@3 { 88 device_type = "cpu"; 89 compatible = "qcom,kryo260"; 90 reg = <0x0 0x3>; 91 clocks = <&cpufreq_hw 0>; 92 capacity-dmips-mhz = <1024>; 93 dynamic-power-coefficient = <100>; 94 enable-method = "psci"; 95 next-level-cache = <&L2_0>; 96 qcom,freq-domain = <&cpufreq_hw 0>; 97 power-domains = <&CPU_PD3>; 98 power-domain-names = "psci"; 99 }; 100 101 CPU4: cpu@100 { 102 device_type = "cpu"; 103 compatible = "qcom,kryo260"; 104 reg = <0x0 0x100>; 105 clocks = <&cpufreq_hw 1>; 106 enable-method = "psci"; 107 capacity-dmips-mhz = <1638>; 108 dynamic-power-coefficient = <282>; 109 next-level-cache = <&L2_1>; 110 qcom,freq-domain = <&cpufreq_hw 1>; 111 power-domains = <&CPU_PD4>; 112 power-domain-names = "psci"; 113 L2_1: l2-cache { 114 compatible = "cache"; 115 cache-level = <2>; 116 cache-unified; 117 }; 118 }; 119 120 CPU5: cpu@101 { 121 device_type = "cpu"; 122 compatible = "qcom,kryo260"; 123 reg = <0x0 0x101>; 124 clocks = <&cpufreq_hw 1>; 125 capacity-dmips-mhz = <1638>; 126 dynamic-power-coefficient = <282>; 127 enable-method = "psci"; 128 next-level-cache = <&L2_1>; 129 qcom,freq-domain = <&cpufreq_hw 1>; 130 power-domains = <&CPU_PD5>; 131 power-domain-names = "psci"; 132 }; 133 134 CPU6: cpu@102 { 135 device_type = "cpu"; 136 compatible = "qcom,kryo260"; 137 reg = <0x0 0x102>; 138 clocks = <&cpufreq_hw 1>; 139 capacity-dmips-mhz = <1638>; 140 dynamic-power-coefficient = <282>; 141 enable-method = "psci"; 142 next-level-cache = <&L2_1>; 143 qcom,freq-domain = <&cpufreq_hw 1>; 144 power-domains = <&CPU_PD6>; 145 power-domain-names = "psci"; 146 }; 147 148 CPU7: cpu@103 { 149 device_type = "cpu"; 150 compatible = "qcom,kryo260"; 151 reg = <0x0 0x103>; 152 clocks = <&cpufreq_hw 1>; 153 capacity-dmips-mhz = <1638>; 154 dynamic-power-coefficient = <282>; 155 enable-method = "psci"; 156 next-level-cache = <&L2_1>; 157 qcom,freq-domain = <&cpufreq_hw 1>; 158 power-domains = <&CPU_PD7>; 159 power-domain-names = "psci"; 160 }; 161 162 cpu-map { 163 cluster0 { 164 core0 { 165 cpu = <&CPU0>; 166 }; 167 168 core1 { 169 cpu = <&CPU1>; 170 }; 171 172 core2 { 173 cpu = <&CPU2>; 174 }; 175 176 core3 { 177 cpu = <&CPU3>; 178 }; 179 }; 180 181 cluster1 { 182 core0 { 183 cpu = <&CPU4>; 184 }; 185 186 core1 { 187 cpu = <&CPU5>; 188 }; 189 190 core2 { 191 cpu = <&CPU6>; 192 }; 193 194 core3 { 195 cpu = <&CPU7>; 196 }; 197 }; 198 }; 199 200 idle-states { 201 entry-method = "psci"; 202 203 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 204 compatible = "arm,idle-state"; 205 idle-state-name = "silver-rail-power-collapse"; 206 arm,psci-suspend-param = <0x40000003>; 207 entry-latency-us = <290>; 208 exit-latency-us = <376>; 209 min-residency-us = <1182>; 210 local-timer-stop; 211 }; 212 213 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 214 compatible = "arm,idle-state"; 215 idle-state-name = "gold-rail-power-collapse"; 216 arm,psci-suspend-param = <0x40000003>; 217 entry-latency-us = <297>; 218 exit-latency-us = <324>; 219 min-residency-us = <1110>; 220 local-timer-stop; 221 }; 222 }; 223 224 domain-idle-states { 225 CLUSTER_0_SLEEP_0: cluster-sleep-0-0 { 226 /* GDHS */ 227 compatible = "domain-idle-state"; 228 arm,psci-suspend-param = <0x40000022>; 229 entry-latency-us = <360>; 230 exit-latency-us = <421>; 231 min-residency-us = <782>; 232 }; 233 234 CLUSTER_0_SLEEP_1: cluster-sleep-0-1 { 235 /* Power Collapse */ 236 compatible = "domain-idle-state"; 237 arm,psci-suspend-param = <0x41000044>; 238 entry-latency-us = <800>; 239 exit-latency-us = <2118>; 240 min-residency-us = <7376>; 241 }; 242 243 CLUSTER_1_SLEEP_0: cluster-sleep-1-0 { 244 /* GDHS */ 245 compatible = "domain-idle-state"; 246 arm,psci-suspend-param = <0x40000042>; 247 entry-latency-us = <314>; 248 exit-latency-us = <345>; 249 min-residency-us = <660>; 250 }; 251 252 CLUSTER_1_SLEEP_1: cluster-sleep-1-1 { 253 /* Power Collapse */ 254 compatible = "domain-idle-state"; 255 arm,psci-suspend-param = <0x41000044>; 256 entry-latency-us = <640>; 257 exit-latency-us = <1654>; 258 min-residency-us = <8094>; 259 }; 260 }; 261 }; 262 263 firmware { 264 scm: scm { 265 compatible = "qcom,scm-sm6115", "qcom,scm"; 266 #reset-cells = <1>; 267 }; 268 }; 269 270 memory@80000000 { 271 device_type = "memory"; 272 /* We expect the bootloader to fill in the size */ 273 reg = <0 0x80000000 0 0>; 274 }; 275 276 pmu { 277 compatible = "arm,armv8-pmuv3"; 278 interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>; 279 }; 280 281 psci { 282 compatible = "arm,psci-1.0"; 283 method = "smc"; 284 285 CPU_PD0: power-domain-cpu0 { 286 #power-domain-cells = <0>; 287 power-domains = <&CLUSTER_0_PD>; 288 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 289 }; 290 291 CPU_PD1: power-domain-cpu1 { 292 #power-domain-cells = <0>; 293 power-domains = <&CLUSTER_0_PD>; 294 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 295 }; 296 297 CPU_PD2: power-domain-cpu2 { 298 #power-domain-cells = <0>; 299 power-domains = <&CLUSTER_0_PD>; 300 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 301 }; 302 303 CPU_PD3: power-domain-cpu3 { 304 #power-domain-cells = <0>; 305 power-domains = <&CLUSTER_0_PD>; 306 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 307 }; 308 309 CPU_PD4: power-domain-cpu4 { 310 #power-domain-cells = <0>; 311 power-domains = <&CLUSTER_1_PD>; 312 domain-idle-states = <&BIG_CPU_SLEEP_0>; 313 }; 314 315 CPU_PD5: power-domain-cpu5 { 316 #power-domain-cells = <0>; 317 power-domains = <&CLUSTER_1_PD>; 318 domain-idle-states = <&BIG_CPU_SLEEP_0>; 319 }; 320 321 CPU_PD6: power-domain-cpu6 { 322 #power-domain-cells = <0>; 323 power-domains = <&CLUSTER_1_PD>; 324 domain-idle-states = <&BIG_CPU_SLEEP_0>; 325 }; 326 327 CPU_PD7: power-domain-cpu7 { 328 #power-domain-cells = <0>; 329 power-domains = <&CLUSTER_1_PD>; 330 domain-idle-states = <&BIG_CPU_SLEEP_0>; 331 }; 332 333 CLUSTER_0_PD: power-domain-cpu-cluster0 { 334 #power-domain-cells = <0>; 335 domain-idle-states = <&CLUSTER_0_SLEEP_0>, <&CLUSTER_0_SLEEP_1>; 336 }; 337 338 CLUSTER_1_PD: power-domain-cpu-cluster1 { 339 #power-domain-cells = <0>; 340 domain-idle-states = <&CLUSTER_1_SLEEP_0>, <&CLUSTER_1_SLEEP_1>; 341 }; 342 }; 343 344 reserved_memory: reserved-memory { 345 #address-cells = <2>; 346 #size-cells = <2>; 347 ranges; 348 349 hyp_mem: memory@45700000 { 350 reg = <0x0 0x45700000 0x0 0x600000>; 351 no-map; 352 }; 353 354 xbl_aop_mem: memory@45e00000 { 355 reg = <0x0 0x45e00000 0x0 0x140000>; 356 no-map; 357 }; 358 359 sec_apps_mem: memory@45fff000 { 360 reg = <0x0 0x45fff000 0x0 0x1000>; 361 no-map; 362 }; 363 364 smem_mem: memory@46000000 { 365 compatible = "qcom,smem"; 366 reg = <0x0 0x46000000 0x0 0x200000>; 367 no-map; 368 369 hwlocks = <&tcsr_mutex 3>; 370 qcom,rpm-msg-ram = <&rpm_msg_ram>; 371 }; 372 373 cdsp_sec_mem: memory@46200000 { 374 reg = <0x0 0x46200000 0x0 0x1e00000>; 375 no-map; 376 }; 377 378 pil_modem_mem: memory@4ab00000 { 379 reg = <0x0 0x4ab00000 0x0 0x6900000>; 380 no-map; 381 }; 382 383 pil_video_mem: memory@51400000 { 384 reg = <0x0 0x51400000 0x0 0x500000>; 385 no-map; 386 }; 387 388 wlan_msa_mem: memory@51900000 { 389 reg = <0x0 0x51900000 0x0 0x100000>; 390 no-map; 391 }; 392 393 pil_cdsp_mem: memory@51a00000 { 394 reg = <0x0 0x51a00000 0x0 0x1e00000>; 395 no-map; 396 }; 397 398 pil_adsp_mem: memory@53800000 { 399 reg = <0x0 0x53800000 0x0 0x2800000>; 400 no-map; 401 }; 402 403 pil_ipa_fw_mem: memory@56100000 { 404 reg = <0x0 0x56100000 0x0 0x10000>; 405 no-map; 406 }; 407 408 pil_ipa_gsi_mem: memory@56110000 { 409 reg = <0x0 0x56110000 0x0 0x5000>; 410 no-map; 411 }; 412 413 pil_gpu_mem: memory@56115000 { 414 reg = <0x0 0x56115000 0x0 0x2000>; 415 no-map; 416 }; 417 418 cont_splash_memory: memory@5c000000 { 419 reg = <0x0 0x5c000000 0x0 0x00f00000>; 420 no-map; 421 }; 422 423 dfps_data_memory: memory@5cf00000 { 424 reg = <0x0 0x5cf00000 0x0 0x0100000>; 425 no-map; 426 }; 427 428 removed_mem: memory@60000000 { 429 reg = <0x0 0x60000000 0x0 0x3900000>; 430 no-map; 431 }; 432 433 rmtfs_mem: memory@89b01000 { 434 compatible = "qcom,rmtfs-mem"; 435 reg = <0x0 0x89b01000 0x0 0x200000>; 436 no-map; 437 438 qcom,client-id = <1>; 439 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA QCOM_SCM_VMID_NAV>; 440 }; 441 }; 442 443 rpm-glink { 444 compatible = "qcom,glink-rpm"; 445 446 interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>; 447 qcom,rpm-msg-ram = <&rpm_msg_ram>; 448 mboxes = <&apcs_glb 0>; 449 450 rpm_requests: rpm-requests { 451 compatible = "qcom,rpm-sm6115"; 452 qcom,glink-channels = "rpm_requests"; 453 454 rpmcc: clock-controller { 455 compatible = "qcom,rpmcc-sm6115", "qcom,rpmcc"; 456 clocks = <&xo_board>; 457 clock-names = "xo"; 458 #clock-cells = <1>; 459 }; 460 461 rpmpd: power-controller { 462 compatible = "qcom,sm6115-rpmpd"; 463 #power-domain-cells = <1>; 464 operating-points-v2 = <&rpmpd_opp_table>; 465 466 rpmpd_opp_table: opp-table { 467 compatible = "operating-points-v2"; 468 469 rpmpd_opp_min_svs: opp1 { 470 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 471 }; 472 473 rpmpd_opp_low_svs: opp2 { 474 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 475 }; 476 477 rpmpd_opp_svs: opp3 { 478 opp-level = <RPM_SMD_LEVEL_SVS>; 479 }; 480 481 rpmpd_opp_svs_plus: opp4 { 482 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 483 }; 484 485 rpmpd_opp_nom: opp5 { 486 opp-level = <RPM_SMD_LEVEL_NOM>; 487 }; 488 489 rpmpd_opp_nom_plus: opp6 { 490 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 491 }; 492 493 rpmpd_opp_turbo: opp7 { 494 opp-level = <RPM_SMD_LEVEL_TURBO>; 495 }; 496 497 rpmpd_opp_turbo_plus: opp8 { 498 opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>; 499 }; 500 }; 501 }; 502 }; 503 }; 504 505 smp2p-adsp { 506 compatible = "qcom,smp2p"; 507 qcom,smem = <443>, <429>; 508 509 interrupts = <GIC_SPI 279 IRQ_TYPE_EDGE_RISING>; 510 511 mboxes = <&apcs_glb 10>; 512 513 qcom,local-pid = <0>; 514 qcom,remote-pid = <2>; 515 516 adsp_smp2p_out: master-kernel { 517 qcom,entry-name = "master-kernel"; 518 #qcom,smem-state-cells = <1>; 519 }; 520 521 adsp_smp2p_in: slave-kernel { 522 qcom,entry-name = "slave-kernel"; 523 524 interrupt-controller; 525 #interrupt-cells = <2>; 526 }; 527 }; 528 529 smp2p-cdsp { 530 compatible = "qcom,smp2p"; 531 qcom,smem = <94>, <432>; 532 533 interrupts = <GIC_SPI 263 IRQ_TYPE_EDGE_RISING>; 534 535 mboxes = <&apcs_glb 30>; 536 537 qcom,local-pid = <0>; 538 qcom,remote-pid = <5>; 539 540 cdsp_smp2p_out: master-kernel { 541 qcom,entry-name = "master-kernel"; 542 #qcom,smem-state-cells = <1>; 543 }; 544 545 cdsp_smp2p_in: slave-kernel { 546 qcom,entry-name = "slave-kernel"; 547 548 interrupt-controller; 549 #interrupt-cells = <2>; 550 }; 551 }; 552 553 smp2p-mpss { 554 compatible = "qcom,smp2p"; 555 qcom,smem = <435>, <428>; 556 557 interrupts = <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>; 558 559 mboxes = <&apcs_glb 14>; 560 561 qcom,local-pid = <0>; 562 qcom,remote-pid = <1>; 563 564 modem_smp2p_out: master-kernel { 565 qcom,entry-name = "master-kernel"; 566 #qcom,smem-state-cells = <1>; 567 }; 568 569 modem_smp2p_in: slave-kernel { 570 qcom,entry-name = "slave-kernel"; 571 572 interrupt-controller; 573 #interrupt-cells = <2>; 574 }; 575 }; 576 577 soc: soc@0 { 578 compatible = "simple-bus"; 579 #address-cells = <2>; 580 #size-cells = <2>; 581 ranges = <0 0 0 0 0x10 0>; 582 dma-ranges = <0 0 0 0 0x10 0>; 583 584 tcsr_mutex: hwlock@340000 { 585 compatible = "qcom,tcsr-mutex"; 586 reg = <0x0 0x00340000 0x0 0x20000>; 587 #hwlock-cells = <1>; 588 }; 589 590 tlmm: pinctrl@500000 { 591 compatible = "qcom,sm6115-tlmm"; 592 reg = <0x0 0x00500000 0x0 0x400000>, 593 <0x0 0x00900000 0x0 0x400000>, 594 <0x0 0x00d00000 0x0 0x400000>; 595 reg-names = "west", "south", "east"; 596 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 597 gpio-controller; 598 gpio-ranges = <&tlmm 0 0 114>; /* GPIOs + ufs_reset */ 599 #gpio-cells = <2>; 600 interrupt-controller; 601 #interrupt-cells = <2>; 602 603 qup_i2c0_default: qup-i2c0-default-state { 604 pins = "gpio0", "gpio1"; 605 function = "qup0"; 606 drive-strength = <2>; 607 bias-pull-up; 608 }; 609 610 qup_i2c1_default: qup-i2c1-default-state { 611 pins = "gpio4", "gpio5"; 612 function = "qup1"; 613 drive-strength = <2>; 614 bias-pull-up; 615 }; 616 617 qup_i2c2_default: qup-i2c2-default-state { 618 pins = "gpio6", "gpio7"; 619 function = "qup2"; 620 drive-strength = <2>; 621 bias-pull-up; 622 }; 623 624 qup_i2c3_default: qup-i2c3-default-state { 625 pins = "gpio8", "gpio9"; 626 function = "qup3"; 627 drive-strength = <2>; 628 bias-pull-up; 629 }; 630 631 qup_i2c4_default: qup-i2c4-default-state { 632 pins = "gpio12", "gpio13"; 633 function = "qup4"; 634 drive-strength = <2>; 635 bias-pull-up; 636 }; 637 638 qup_i2c5_default: qup-i2c5-default-state { 639 pins = "gpio14", "gpio15"; 640 function = "qup5"; 641 drive-strength = <2>; 642 bias-pull-up; 643 }; 644 645 qup_spi0_default: qup-spi0-default-state { 646 pins = "gpio0", "gpio1","gpio2", "gpio3"; 647 function = "qup0"; 648 drive-strength = <2>; 649 bias-pull-up; 650 }; 651 652 qup_spi1_default: qup-spi1-default-state { 653 pins = "gpio4", "gpio5", "gpio69", "gpio70"; 654 function = "qup1"; 655 drive-strength = <2>; 656 bias-pull-up; 657 }; 658 659 qup_spi2_default: qup-spi2-default-state { 660 pins = "gpio6", "gpio7", "gpio71", "gpio80"; 661 function = "qup2"; 662 drive-strength = <2>; 663 bias-pull-up; 664 }; 665 666 qup_spi3_default: qup-spi3-default-state { 667 pins = "gpio8", "gpio9", "gpio10", "gpio11"; 668 function = "qup3"; 669 drive-strength = <2>; 670 bias-pull-up; 671 }; 672 673 qup_spi4_default: qup-spi4-default-state { 674 pins = "gpio12", "gpio13", "gpio96", "gpio97"; 675 function = "qup4"; 676 drive-strength = <2>; 677 bias-pull-up; 678 }; 679 680 qup_spi5_default: qup-spi5-default-state { 681 pins = "gpio14", "gpio15", "gpio16", "gpio17"; 682 function = "qup5"; 683 drive-strength = <2>; 684 bias-pull-up; 685 }; 686 687 sdc1_state_on: sdc1-on-state { 688 clk-pins { 689 pins = "sdc1_clk"; 690 bias-disable; 691 drive-strength = <16>; 692 }; 693 694 cmd-pins { 695 pins = "sdc1_cmd"; 696 bias-pull-up; 697 drive-strength = <10>; 698 }; 699 700 data-pins { 701 pins = "sdc1_data"; 702 bias-pull-up; 703 drive-strength = <10>; 704 }; 705 706 rclk-pins { 707 pins = "sdc1_rclk"; 708 bias-pull-down; 709 }; 710 }; 711 712 sdc1_state_off: sdc1-off-state { 713 clk-pins { 714 pins = "sdc1_clk"; 715 bias-disable; 716 drive-strength = <2>; 717 }; 718 719 cmd-pins { 720 pins = "sdc1_cmd"; 721 bias-pull-up; 722 drive-strength = <2>; 723 }; 724 725 data-pins { 726 pins = "sdc1_data"; 727 bias-pull-up; 728 drive-strength = <2>; 729 }; 730 731 rclk-pins { 732 pins = "sdc1_rclk"; 733 bias-pull-down; 734 }; 735 }; 736 737 sdc2_state_on: sdc2-on-state { 738 clk-pins { 739 pins = "sdc2_clk"; 740 bias-disable; 741 drive-strength = <16>; 742 }; 743 744 cmd-pins { 745 pins = "sdc2_cmd"; 746 bias-pull-up; 747 drive-strength = <10>; 748 }; 749 750 data-pins { 751 pins = "sdc2_data"; 752 bias-pull-up; 753 drive-strength = <10>; 754 }; 755 }; 756 757 sdc2_state_off: sdc2-off-state { 758 clk-pins { 759 pins = "sdc2_clk"; 760 bias-disable; 761 drive-strength = <2>; 762 }; 763 764 cmd-pins { 765 pins = "sdc2_cmd"; 766 bias-pull-up; 767 drive-strength = <2>; 768 }; 769 770 data-pins { 771 pins = "sdc2_data"; 772 bias-pull-up; 773 drive-strength = <2>; 774 }; 775 }; 776 }; 777 778 gcc: clock-controller@1400000 { 779 compatible = "qcom,gcc-sm6115"; 780 reg = <0x0 0x01400000 0x0 0x1f0000>; 781 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>; 782 clock-names = "bi_tcxo", "sleep_clk"; 783 #clock-cells = <1>; 784 #reset-cells = <1>; 785 #power-domain-cells = <1>; 786 }; 787 788 usb_hsphy: phy@1613000 { 789 compatible = "qcom,sm6115-qusb2-phy"; 790 reg = <0x0 0x01613000 0x0 0x180>; 791 #phy-cells = <0>; 792 793 clocks = <&gcc GCC_AHB2PHY_USB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>; 794 clock-names = "cfg_ahb", "ref"; 795 796 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 797 nvmem-cells = <&qusb2_hstx_trim>; 798 799 status = "disabled"; 800 }; 801 802 cryptobam: dma-controller@1b04000 { 803 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 804 reg = <0x0 0x01b04000 0x0 0x24000>; 805 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>; 806 clocks = <&rpmcc RPM_SMD_CE1_CLK>; 807 clock-names = "bam_clk"; 808 #dma-cells = <1>; 809 qcom,ee = <0>; 810 qcom,controlled-remotely; 811 iommus = <&apps_smmu 0x92 0>, 812 <&apps_smmu 0x94 0x11>, 813 <&apps_smmu 0x96 0x11>, 814 <&apps_smmu 0x98 0x1>, 815 <&apps_smmu 0x9F 0>; 816 }; 817 818 crypto: crypto@1b3a000 { 819 compatible = "qcom,sm6115-qce", "qcom,ipq4019-qce", "qcom,qce"; 820 reg = <0x0 0x01b3a000 0x0 0x6000>; 821 clocks = <&rpmcc RPM_SMD_CE1_CLK>; 822 clock-names = "core"; 823 824 dmas = <&cryptobam 6>, <&cryptobam 7>; 825 dma-names = "rx", "tx"; 826 iommus = <&apps_smmu 0x92 0>, 827 <&apps_smmu 0x94 0x11>, 828 <&apps_smmu 0x96 0x11>, 829 <&apps_smmu 0x98 0x1>, 830 <&apps_smmu 0x9F 0>; 831 }; 832 833 usb_qmpphy: phy@1615000 { 834 compatible = "qcom,sm6115-qmp-usb3-phy"; 835 reg = <0x0 0x01615000 0x0 0x1000>; 836 837 clocks = <&gcc GCC_AHB2PHY_USB_CLK>, 838 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 839 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 840 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 841 clock-names = "cfg_ahb", 842 "ref", 843 "com_aux", 844 "pipe"; 845 846 resets = <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>, 847 <&gcc GCC_USB3PHY_PHY_PRIM_SP0_BCR>; 848 reset-names = "phy", "phy_phy"; 849 850 #clock-cells = <0>; 851 clock-output-names = "usb3_phy_pipe_clk_src"; 852 853 #phy-cells = <0>; 854 855 status = "disabled"; 856 }; 857 858 qfprom@1b40000 { 859 compatible = "qcom,sm6115-qfprom", "qcom,qfprom"; 860 reg = <0x0 0x01b40000 0x0 0x7000>; 861 #address-cells = <1>; 862 #size-cells = <1>; 863 864 qusb2_hstx_trim: hstx-trim@25b { 865 reg = <0x25b 0x1>; 866 bits = <1 4>; 867 }; 868 }; 869 870 rng: rng@1b53000 { 871 compatible = "qcom,prng-ee"; 872 reg = <0x0 0x01b53000 0x0 0x1000>; 873 clocks = <&gcc GCC_PRNG_AHB_CLK>; 874 clock-names = "core"; 875 }; 876 877 spmi_bus: spmi@1c40000 { 878 compatible = "qcom,spmi-pmic-arb"; 879 reg = <0x0 0x01c40000 0x0 0x1100>, 880 <0x0 0x01e00000 0x0 0x2000000>, 881 <0x0 0x03e00000 0x0 0x100000>, 882 <0x0 0x03f00000 0x0 0xa0000>, 883 <0x0 0x01c0a000 0x0 0x26000>; 884 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 885 interrupt-names = "periph_irq"; 886 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 887 qcom,ee = <0>; 888 qcom,channel = <0>; 889 #address-cells = <2>; 890 #size-cells = <0>; 891 interrupt-controller; 892 #interrupt-cells = <4>; 893 }; 894 895 tsens0: thermal-sensor@4411000 { 896 compatible = "qcom,sm6115-tsens", "qcom,tsens-v2"; 897 reg = <0x0 0x04411000 0x0 0x1ff>, /* TM */ 898 <0x0 0x04410000 0x0 0x8>; /* SROT */ 899 #qcom,sensors = <16>; 900 interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 901 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 902 interrupt-names = "uplow", "critical"; 903 #thermal-sensor-cells = <1>; 904 }; 905 906 rpm_msg_ram: sram@45f0000 { 907 compatible = "qcom,rpm-msg-ram"; 908 reg = <0x0 0x045f0000 0x0 0x7000>; 909 }; 910 911 sram@4690000 { 912 compatible = "qcom,rpm-stats"; 913 reg = <0x0 0x04690000 0x0 0x10000>; 914 }; 915 916 sdhc_1: mmc@4744000 { 917 compatible = "qcom,sm6115-sdhci", "qcom,sdhci-msm-v5"; 918 reg = <0x0 0x04744000 0x0 0x1000>, 919 <0x0 0x04745000 0x0 0x1000>, 920 <0x0 0x04748000 0x0 0x8000>; 921 reg-names = "hc", "cqhci", "ice"; 922 923 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, 924 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 925 interrupt-names = "hc_irq", "pwr_irq"; 926 927 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 928 <&gcc GCC_SDCC1_APPS_CLK>, 929 <&rpmcc RPM_SMD_XO_CLK_SRC>, 930 <&gcc GCC_SDCC1_ICE_CORE_CLK>; 931 clock-names = "iface", "core", "xo", "ice"; 932 933 bus-width = <8>; 934 status = "disabled"; 935 }; 936 937 sdhc_2: mmc@4784000 { 938 compatible = "qcom,sm6115-sdhci", "qcom,sdhci-msm-v5"; 939 reg = <0x0 0x04784000 0x0 0x1000>; 940 reg-names = "hc"; 941 942 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 943 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 944 interrupt-names = "hc_irq", "pwr_irq"; 945 946 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 947 <&gcc GCC_SDCC2_APPS_CLK>, 948 <&rpmcc RPM_SMD_XO_CLK_SRC>; 949 clock-names = "iface", "core", "xo"; 950 951 power-domains = <&rpmpd SM6115_VDDCX>; 952 operating-points-v2 = <&sdhc2_opp_table>; 953 iommus = <&apps_smmu 0x00a0 0x0>; 954 resets = <&gcc GCC_SDCC2_BCR>; 955 956 bus-width = <4>; 957 qcom,dll-config = <0x0007642c>; 958 qcom,ddr-config = <0x80040868>; 959 status = "disabled"; 960 961 sdhc2_opp_table: opp-table { 962 compatible = "operating-points-v2"; 963 964 opp-100000000 { 965 opp-hz = /bits/ 64 <100000000>; 966 required-opps = <&rpmpd_opp_low_svs>; 967 }; 968 969 opp-202000000 { 970 opp-hz = /bits/ 64 <202000000>; 971 required-opps = <&rpmpd_opp_nom>; 972 }; 973 }; 974 }; 975 976 ufs_mem_hc: ufs@4804000 { 977 compatible = "qcom,sm6115-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; 978 reg = <0x0 0x04804000 0x0 0x3000>, <0x0 0x04810000 0x0 0x8000>; 979 reg-names = "std", "ice"; 980 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 981 phys = <&ufs_mem_phy_lanes>; 982 phy-names = "ufsphy"; 983 lanes-per-direction = <1>; 984 #reset-cells = <1>; 985 resets = <&gcc GCC_UFS_PHY_BCR>; 986 reset-names = "rst"; 987 988 power-domains = <&gcc GCC_UFS_PHY_GDSC>; 989 iommus = <&apps_smmu 0x100 0>; 990 991 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 992 <&gcc GCC_SYS_NOC_UFS_PHY_AXI_CLK>, 993 <&gcc GCC_UFS_PHY_AHB_CLK>, 994 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 995 <&rpmcc RPM_SMD_XO_CLK_SRC>, 996 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 997 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 998 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 999 clock-names = "core_clk", 1000 "bus_aggr_clk", 1001 "iface_clk", 1002 "core_clk_unipro", 1003 "ref_clk", 1004 "tx_lane0_sync_clk", 1005 "rx_lane0_sync_clk", 1006 "ice_core_clk"; 1007 1008 freq-table-hz = <50000000 200000000>, 1009 <0 0>, 1010 <0 0>, 1011 <37500000 150000000>, 1012 <0 0>, 1013 <0 0>, 1014 <0 0>, 1015 <75000000 300000000>; 1016 1017 status = "disabled"; 1018 }; 1019 1020 ufs_mem_phy: phy@4807000 { 1021 compatible = "qcom,sm6115-qmp-ufs-phy"; 1022 reg = <0x0 0x04807000 0x0 0x1c4>; 1023 #address-cells = <2>; 1024 #size-cells = <2>; 1025 ranges; 1026 1027 clocks = <&gcc GCC_UFS_CLKREF_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 1028 clock-names = "ref", "ref_aux"; 1029 1030 resets = <&ufs_mem_hc 0>; 1031 reset-names = "ufsphy"; 1032 status = "disabled"; 1033 1034 ufs_mem_phy_lanes: phy@4807400 { 1035 reg = <0x0 0x04807400 0x0 0x098>, 1036 <0x0 0x04807600 0x0 0x130>, 1037 <0x0 0x04807c00 0x0 0x16c>; 1038 #phy-cells = <0>; 1039 }; 1040 }; 1041 1042 gpi_dma0: dma-controller@4a00000 { 1043 compatible = "qcom,sm6115-gpi-dma", "qcom,sm6350-gpi-dma"; 1044 reg = <0x0 0x04a00000 0x0 0x60000>; 1045 interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 1046 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 1047 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 1048 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 1049 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 1050 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 1051 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 1052 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 1053 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 1054 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; 1055 dma-channels = <10>; 1056 dma-channel-mask = <0xf>; 1057 iommus = <&apps_smmu 0xf6 0x0>; 1058 #dma-cells = <3>; 1059 status = "disabled"; 1060 }; 1061 1062 qupv3_id_0: geniqup@4ac0000 { 1063 compatible = "qcom,geni-se-qup"; 1064 reg = <0x0 0x04ac0000 0x0 0x2000>; 1065 clock-names = "m-ahb", "s-ahb"; 1066 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1067 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1068 #address-cells = <2>; 1069 #size-cells = <2>; 1070 iommus = <&apps_smmu 0xe3 0x0>; 1071 ranges; 1072 status = "disabled"; 1073 1074 i2c0: i2c@4a80000 { 1075 compatible = "qcom,geni-i2c"; 1076 reg = <0x0 0x04a80000 0x0 0x4000>; 1077 clock-names = "se"; 1078 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1079 pinctrl-names = "default"; 1080 pinctrl-0 = <&qup_i2c0_default>; 1081 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 1082 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1083 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1084 dma-names = "tx", "rx"; 1085 #address-cells = <1>; 1086 #size-cells = <0>; 1087 status = "disabled"; 1088 }; 1089 1090 spi0: spi@4a80000 { 1091 compatible = "qcom,geni-spi"; 1092 reg = <0x0 0x04a80000 0x0 0x4000>; 1093 clock-names = "se"; 1094 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1095 pinctrl-names = "default"; 1096 pinctrl-0 = <&qup_spi0_default>; 1097 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 1098 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1099 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1100 dma-names = "tx", "rx"; 1101 #address-cells = <1>; 1102 #size-cells = <0>; 1103 status = "disabled"; 1104 }; 1105 1106 i2c1: i2c@4a84000 { 1107 compatible = "qcom,geni-i2c"; 1108 reg = <0x0 0x04a84000 0x0 0x4000>; 1109 clock-names = "se"; 1110 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1111 pinctrl-names = "default"; 1112 pinctrl-0 = <&qup_i2c1_default>; 1113 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 1114 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1115 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1116 dma-names = "tx", "rx"; 1117 #address-cells = <1>; 1118 #size-cells = <0>; 1119 status = "disabled"; 1120 }; 1121 1122 spi1: spi@4a84000 { 1123 compatible = "qcom,geni-spi"; 1124 reg = <0x0 0x04a84000 0x0 0x4000>; 1125 clock-names = "se"; 1126 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1127 pinctrl-names = "default"; 1128 pinctrl-0 = <&qup_spi1_default>; 1129 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 1130 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1131 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1132 dma-names = "tx", "rx"; 1133 #address-cells = <1>; 1134 #size-cells = <0>; 1135 status = "disabled"; 1136 }; 1137 1138 i2c2: i2c@4a88000 { 1139 compatible = "qcom,geni-i2c"; 1140 reg = <0x0 0x04a88000 0x0 0x4000>; 1141 clock-names = "se"; 1142 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1143 pinctrl-names = "default"; 1144 pinctrl-0 = <&qup_i2c2_default>; 1145 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; 1146 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1147 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1148 dma-names = "tx", "rx"; 1149 #address-cells = <1>; 1150 #size-cells = <0>; 1151 status = "disabled"; 1152 }; 1153 1154 spi2: spi@4a88000 { 1155 compatible = "qcom,geni-spi"; 1156 reg = <0x0 0x04a88000 0x0 0x4000>; 1157 clock-names = "se"; 1158 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1159 pinctrl-names = "default"; 1160 pinctrl-0 = <&qup_spi2_default>; 1161 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; 1162 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1163 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1164 dma-names = "tx", "rx"; 1165 #address-cells = <1>; 1166 #size-cells = <0>; 1167 status = "disabled"; 1168 }; 1169 1170 i2c3: i2c@4a8c000 { 1171 compatible = "qcom,geni-i2c"; 1172 reg = <0x0 0x04a8c000 0x0 0x4000>; 1173 clock-names = "se"; 1174 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1175 pinctrl-names = "default"; 1176 pinctrl-0 = <&qup_i2c3_default>; 1177 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 1178 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1179 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1180 dma-names = "tx", "rx"; 1181 #address-cells = <1>; 1182 #size-cells = <0>; 1183 status = "disabled"; 1184 }; 1185 1186 spi3: spi@4a8c000 { 1187 compatible = "qcom,geni-spi"; 1188 reg = <0x0 0x04a8c000 0x0 0x4000>; 1189 clock-names = "se"; 1190 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1191 pinctrl-names = "default"; 1192 pinctrl-0 = <&qup_spi3_default>; 1193 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 1194 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1195 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1196 dma-names = "tx", "rx"; 1197 #address-cells = <1>; 1198 #size-cells = <0>; 1199 status = "disabled"; 1200 }; 1201 1202 i2c4: i2c@4a90000 { 1203 compatible = "qcom,geni-i2c"; 1204 reg = <0x0 0x04a90000 0x0 0x4000>; 1205 clock-names = "se"; 1206 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1207 pinctrl-names = "default"; 1208 pinctrl-0 = <&qup_i2c4_default>; 1209 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 1210 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1211 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1212 dma-names = "tx", "rx"; 1213 #address-cells = <1>; 1214 #size-cells = <0>; 1215 status = "disabled"; 1216 }; 1217 1218 spi4: spi@4a90000 { 1219 compatible = "qcom,geni-spi"; 1220 reg = <0x0 0x04a90000 0x0 0x4000>; 1221 clock-names = "se"; 1222 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1223 pinctrl-names = "default"; 1224 pinctrl-0 = <&qup_spi4_default>; 1225 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 1226 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1227 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1228 dma-names = "tx", "rx"; 1229 #address-cells = <1>; 1230 #size-cells = <0>; 1231 status = "disabled"; 1232 }; 1233 1234 uart4: serial@4a90000 { 1235 compatible = "qcom,geni-debug-uart"; 1236 reg = <0x0 0x04a90000 0x0 0x4000>; 1237 clock-names = "se"; 1238 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1239 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 1240 status = "disabled"; 1241 }; 1242 1243 i2c5: i2c@4a94000 { 1244 compatible = "qcom,geni-i2c"; 1245 reg = <0x0 0x04a94000 0x0 0x4000>; 1246 clock-names = "se"; 1247 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1248 pinctrl-names = "default"; 1249 pinctrl-0 = <&qup_i2c5_default>; 1250 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; 1251 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1252 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1253 dma-names = "tx", "rx"; 1254 #address-cells = <1>; 1255 #size-cells = <0>; 1256 status = "disabled"; 1257 }; 1258 1259 spi5: spi@4a94000 { 1260 compatible = "qcom,geni-spi"; 1261 reg = <0x0 0x04a94000 0x0 0x4000>; 1262 clock-names = "se"; 1263 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1264 pinctrl-names = "default"; 1265 pinctrl-0 = <&qup_spi5_default>; 1266 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; 1267 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1268 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1269 dma-names = "tx", "rx"; 1270 #address-cells = <1>; 1271 #size-cells = <0>; 1272 status = "disabled"; 1273 }; 1274 }; 1275 1276 usb: usb@4ef8800 { 1277 compatible = "qcom,sm6115-dwc3", "qcom,dwc3"; 1278 reg = <0x0 0x04ef8800 0x0 0x400>; 1279 #address-cells = <2>; 1280 #size-cells = <2>; 1281 ranges; 1282 1283 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 1284 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 1285 <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>, 1286 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 1287 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1288 <&gcc GCC_USB3_PRIM_CLKREF_CLK>; 1289 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", "xo"; 1290 1291 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1292 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 1293 assigned-clock-rates = <19200000>, <66666667>; 1294 1295 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 1296 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>; 1297 interrupt-names = "hs_phy_irq", "ss_phy_irq"; 1298 1299 resets = <&gcc GCC_USB30_PRIM_BCR>; 1300 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 1301 qcom,select-utmi-as-pipe-clk; 1302 status = "disabled"; 1303 1304 usb_dwc3: usb@4e00000 { 1305 compatible = "snps,dwc3"; 1306 reg = <0x0 0x04e00000 0x0 0xcd00>; 1307 interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 1308 phys = <&usb_hsphy>, <&usb_qmpphy>; 1309 phy-names = "usb2-phy", "usb3-phy"; 1310 iommus = <&apps_smmu 0x120 0x0>; 1311 snps,dis_u2_susphy_quirk; 1312 snps,dis_enblslpm_quirk; 1313 snps,has-lpm-erratum; 1314 snps,hird-threshold = /bits/ 8 <0x10>; 1315 snps,usb3_lpm_capable; 1316 }; 1317 }; 1318 1319 gpucc: clock-controller@5990000 { 1320 compatible = "qcom,sm6115-gpucc"; 1321 reg = <0x0 0x05990000 0x0 0x9000>; 1322 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 1323 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 1324 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 1325 #clock-cells = <1>; 1326 #reset-cells = <1>; 1327 #power-domain-cells = <1>; 1328 }; 1329 1330 adreno_smmu: iommu@59a0000 { 1331 compatible = "qcom,sm6115-smmu-500", "qcom,adreno-smmu", 1332 "qcom,smmu-500", "arm,mmu-500"; 1333 reg = <0x0 0x059a0000 0x0 0x10000>; 1334 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 1335 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 1336 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 1337 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 1338 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1339 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 1340 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, 1341 <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, 1342 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1343 1344 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1345 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 1346 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 1347 clock-names = "mem", 1348 "hlos", 1349 "iface"; 1350 power-domains = <&gpucc GPU_CX_GDSC>; 1351 1352 #global-interrupts = <1>; 1353 #iommu-cells = <2>; 1354 }; 1355 1356 mdss: display-subsystem@5e00000 { 1357 compatible = "qcom,sm6115-mdss"; 1358 reg = <0x0 0x05e00000 0x0 0x1000>; 1359 reg-names = "mdss"; 1360 1361 power-domains = <&dispcc MDSS_GDSC>; 1362 1363 clocks = <&gcc GCC_DISP_AHB_CLK>, 1364 <&gcc GCC_DISP_HF_AXI_CLK>, 1365 <&dispcc DISP_CC_MDSS_MDP_CLK>; 1366 1367 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 1368 interrupt-controller; 1369 #interrupt-cells = <1>; 1370 1371 iommus = <&apps_smmu 0x420 0x2>, 1372 <&apps_smmu 0x421 0x0>; 1373 1374 #address-cells = <2>; 1375 #size-cells = <2>; 1376 ranges; 1377 1378 status = "disabled"; 1379 1380 mdp: display-controller@5e01000 { 1381 compatible = "qcom,sm6115-dpu"; 1382 reg = <0x0 0x05e01000 0x0 0x8f000>, 1383 <0x0 0x05eb0000 0x0 0x2008>; 1384 reg-names = "mdp", "vbif"; 1385 1386 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 1387 <&dispcc DISP_CC_MDSS_AHB_CLK>, 1388 <&dispcc DISP_CC_MDSS_MDP_CLK>, 1389 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 1390 <&dispcc DISP_CC_MDSS_ROT_CLK>, 1391 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 1392 clock-names = "bus", 1393 "iface", 1394 "core", 1395 "lut", 1396 "rot", 1397 "vsync"; 1398 1399 operating-points-v2 = <&mdp_opp_table>; 1400 power-domains = <&rpmpd SM6115_VDDCX>; 1401 1402 interrupt-parent = <&mdss>; 1403 interrupts = <0>; 1404 1405 ports { 1406 #address-cells = <1>; 1407 #size-cells = <0>; 1408 1409 port@0 { 1410 reg = <0>; 1411 dpu_intf1_out: endpoint { 1412 remote-endpoint = <&mdss_dsi0_in>; 1413 }; 1414 }; 1415 }; 1416 1417 mdp_opp_table: opp-table { 1418 compatible = "operating-points-v2"; 1419 1420 opp-19200000 { 1421 opp-hz = /bits/ 64 <19200000>; 1422 required-opps = <&rpmpd_opp_min_svs>; 1423 }; 1424 1425 opp-192000000 { 1426 opp-hz = /bits/ 64 <192000000>; 1427 required-opps = <&rpmpd_opp_low_svs>; 1428 }; 1429 1430 opp-256000000 { 1431 opp-hz = /bits/ 64 <256000000>; 1432 required-opps = <&rpmpd_opp_svs>; 1433 }; 1434 1435 opp-307200000 { 1436 opp-hz = /bits/ 64 <307200000>; 1437 required-opps = <&rpmpd_opp_svs_plus>; 1438 }; 1439 1440 opp-384000000 { 1441 opp-hz = /bits/ 64 <384000000>; 1442 required-opps = <&rpmpd_opp_nom>; 1443 }; 1444 }; 1445 }; 1446 1447 mdss_dsi0: dsi@5e94000 { 1448 compatible = "qcom,sm6115-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 1449 reg = <0x0 0x05e94000 0x0 0x400>; 1450 reg-names = "dsi_ctrl"; 1451 1452 interrupt-parent = <&mdss>; 1453 interrupts = <4>; 1454 1455 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 1456 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 1457 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 1458 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 1459 <&dispcc DISP_CC_MDSS_AHB_CLK>, 1460 <&gcc GCC_DISP_HF_AXI_CLK>; 1461 clock-names = "byte", 1462 "byte_intf", 1463 "pixel", 1464 "core", 1465 "iface", 1466 "bus"; 1467 1468 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 1469 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 1470 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; 1471 1472 operating-points-v2 = <&dsi_opp_table>; 1473 power-domains = <&rpmpd SM6115_VDDCX>; 1474 phys = <&mdss_dsi0_phy>; 1475 1476 #address-cells = <1>; 1477 #size-cells = <0>; 1478 1479 status = "disabled"; 1480 1481 ports { 1482 #address-cells = <1>; 1483 #size-cells = <0>; 1484 1485 port@0 { 1486 reg = <0>; 1487 mdss_dsi0_in: endpoint { 1488 remote-endpoint = <&dpu_intf1_out>; 1489 }; 1490 }; 1491 1492 port@1 { 1493 reg = <1>; 1494 mdss_dsi0_out: endpoint { 1495 }; 1496 }; 1497 }; 1498 1499 dsi_opp_table: opp-table { 1500 compatible = "operating-points-v2"; 1501 1502 opp-19200000 { 1503 opp-hz = /bits/ 64 <19200000>; 1504 required-opps = <&rpmpd_opp_min_svs>; 1505 }; 1506 1507 opp-164000000 { 1508 opp-hz = /bits/ 64 <164000000>; 1509 required-opps = <&rpmpd_opp_low_svs>; 1510 }; 1511 1512 opp-187500000 { 1513 opp-hz = /bits/ 64 <187500000>; 1514 required-opps = <&rpmpd_opp_svs>; 1515 }; 1516 }; 1517 }; 1518 1519 mdss_dsi0_phy: phy@5e94400 { 1520 compatible = "qcom,dsi-phy-14nm-2290"; 1521 reg = <0x0 0x05e94400 0x0 0x100>, 1522 <0x0 0x05e94500 0x0 0x300>, 1523 <0x0 0x05e94800 0x0 0x188>; 1524 reg-names = "dsi_phy", 1525 "dsi_phy_lane", 1526 "dsi_pll"; 1527 1528 #clock-cells = <1>; 1529 #phy-cells = <0>; 1530 1531 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 1532 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1533 clock-names = "iface", "ref"; 1534 1535 status = "disabled"; 1536 }; 1537 }; 1538 1539 dispcc: clock-controller@5f00000 { 1540 compatible = "qcom,sm6115-dispcc"; 1541 reg = <0x0 0x05f00000 0 0x20000>; 1542 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 1543 <&sleep_clk>, 1544 <&mdss_dsi0_phy 0>, 1545 <&mdss_dsi0_phy 1>, 1546 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>; 1547 #clock-cells = <1>; 1548 #reset-cells = <1>; 1549 #power-domain-cells = <1>; 1550 }; 1551 1552 remoteproc_mpss: remoteproc@6080000 { 1553 compatible = "qcom,sm6115-mpss-pas"; 1554 reg = <0x0 0x06080000 0x0 0x100>; 1555 1556 interrupts-extended = <&intc GIC_SPI 307 IRQ_TYPE_EDGE_RISING>, 1557 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1558 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1559 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1560 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 1561 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 1562 interrupt-names = "wdog", "fatal", "ready", "handover", 1563 "stop-ack", "shutdown-ack"; 1564 1565 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 1566 clock-names = "xo"; 1567 1568 power-domains = <&rpmpd SM6115_VDDCX>; 1569 1570 memory-region = <&pil_modem_mem>; 1571 1572 qcom,smem-states = <&modem_smp2p_out 0>; 1573 qcom,smem-state-names = "stop"; 1574 1575 status = "disabled"; 1576 1577 glink-edge { 1578 interrupts = <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>; 1579 label = "mpss"; 1580 qcom,remote-pid = <1>; 1581 mboxes = <&apcs_glb 12>; 1582 }; 1583 }; 1584 1585 stm@8002000 { 1586 compatible = "arm,coresight-stm", "arm,primecell"; 1587 reg = <0x0 0x08002000 0x0 0x1000>, 1588 <0x0 0x0e280000 0x0 0x180000>; 1589 reg-names = "stm-base", "stm-stimulus-base"; 1590 1591 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1592 clock-names = "apb_pclk"; 1593 1594 status = "disabled"; 1595 1596 out-ports { 1597 port { 1598 stm_out: endpoint { 1599 remote-endpoint = <&funnel_in0_in>; 1600 }; 1601 }; 1602 }; 1603 }; 1604 1605 cti0: cti@8010000 { 1606 compatible = "arm,coresight-cti", "arm,primecell"; 1607 reg = <0x0 0x08010000 0x0 0x1000>; 1608 1609 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1610 clock-names = "apb_pclk"; 1611 1612 status = "disabled"; 1613 }; 1614 1615 cti1: cti@8011000 { 1616 compatible = "arm,coresight-cti", "arm,primecell"; 1617 reg = <0x0 0x08011000 0x0 0x1000>; 1618 1619 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1620 clock-names = "apb_pclk"; 1621 1622 status = "disabled"; 1623 }; 1624 1625 cti2: cti@8012000 { 1626 compatible = "arm,coresight-cti", "arm,primecell"; 1627 reg = <0x0 0x08012000 0x0 0x1000>; 1628 1629 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1630 clock-names = "apb_pclk"; 1631 1632 status = "disabled"; 1633 }; 1634 1635 cti3: cti@8013000 { 1636 compatible = "arm,coresight-cti", "arm,primecell"; 1637 reg = <0x0 0x08013000 0x0 0x1000>; 1638 1639 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1640 clock-names = "apb_pclk"; 1641 1642 status = "disabled"; 1643 }; 1644 1645 cti4: cti@8014000 { 1646 compatible = "arm,coresight-cti", "arm,primecell"; 1647 reg = <0x0 0x08014000 0x0 0x1000>; 1648 1649 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1650 clock-names = "apb_pclk"; 1651 1652 status = "disabled"; 1653 }; 1654 1655 cti5: cti@8015000 { 1656 compatible = "arm,coresight-cti", "arm,primecell"; 1657 reg = <0x0 0x08015000 0x0 0x1000>; 1658 1659 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1660 clock-names = "apb_pclk"; 1661 1662 status = "disabled"; 1663 }; 1664 1665 cti6: cti@8016000 { 1666 compatible = "arm,coresight-cti", "arm,primecell"; 1667 reg = <0x0 0x08016000 0x0 0x1000>; 1668 1669 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1670 clock-names = "apb_pclk"; 1671 1672 status = "disabled"; 1673 }; 1674 1675 cti7: cti@8017000 { 1676 compatible = "arm,coresight-cti", "arm,primecell"; 1677 reg = <0x0 0x08017000 0x0 0x1000>; 1678 1679 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1680 clock-names = "apb_pclk"; 1681 1682 status = "disabled"; 1683 }; 1684 1685 cti8: cti@8018000 { 1686 compatible = "arm,coresight-cti", "arm,primecell"; 1687 reg = <0x0 0x08018000 0x0 0x1000>; 1688 1689 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1690 clock-names = "apb_pclk"; 1691 1692 status = "disabled"; 1693 }; 1694 1695 cti9: cti@8019000 { 1696 compatible = "arm,coresight-cti", "arm,primecell"; 1697 reg = <0x0 0x08019000 0x0 0x1000>; 1698 1699 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1700 clock-names = "apb_pclk"; 1701 1702 status = "disabled"; 1703 }; 1704 1705 cti10: cti@801a000 { 1706 compatible = "arm,coresight-cti", "arm,primecell"; 1707 reg = <0x0 0x0801a000 0x0 0x1000>; 1708 1709 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1710 clock-names = "apb_pclk"; 1711 1712 status = "disabled"; 1713 }; 1714 1715 cti11: cti@801b000 { 1716 compatible = "arm,coresight-cti", "arm,primecell"; 1717 reg = <0x0 0x0801b000 0x0 0x1000>; 1718 1719 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1720 clock-names = "apb_pclk"; 1721 1722 status = "disabled"; 1723 }; 1724 1725 cti12: cti@801c000 { 1726 compatible = "arm,coresight-cti", "arm,primecell"; 1727 reg = <0x0 0x0801c000 0x0 0x1000>; 1728 1729 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1730 clock-names = "apb_pclk"; 1731 1732 status = "disabled"; 1733 }; 1734 1735 cti13: cti@801d000 { 1736 compatible = "arm,coresight-cti", "arm,primecell"; 1737 reg = <0x0 0x0801d000 0x0 0x1000>; 1738 1739 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1740 clock-names = "apb_pclk"; 1741 1742 status = "disabled"; 1743 }; 1744 1745 cti14: cti@801e000 { 1746 compatible = "arm,coresight-cti", "arm,primecell"; 1747 reg = <0x0 0x0801e000 0x0 0x1000>; 1748 1749 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1750 clock-names = "apb_pclk"; 1751 1752 status = "disabled"; 1753 }; 1754 1755 cti15: cti@801f000 { 1756 compatible = "arm,coresight-cti", "arm,primecell"; 1757 reg = <0x0 0x0801f000 0x0 0x1000>; 1758 1759 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1760 clock-names = "apb_pclk"; 1761 1762 status = "disabled"; 1763 }; 1764 1765 replicator@8046000 { 1766 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 1767 reg = <0x0 0x08046000 0x0 0x1000>; 1768 1769 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1770 clock-names = "apb_pclk"; 1771 1772 status = "disabled"; 1773 1774 out-ports { 1775 port { 1776 replicator_out: endpoint { 1777 remote-endpoint = <&etr_in>; 1778 }; 1779 }; 1780 }; 1781 1782 in-ports { 1783 port { 1784 replicator_in: endpoint { 1785 remote-endpoint = <&etf_out>; 1786 }; 1787 }; 1788 }; 1789 }; 1790 1791 etf@8047000 { 1792 compatible = "arm,coresight-tmc", "arm,primecell"; 1793 reg = <0x0 0x08047000 0x0 0x1000>; 1794 1795 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1796 clock-names = "apb_pclk"; 1797 1798 status = "disabled"; 1799 1800 in-ports { 1801 port { 1802 etf_in: endpoint { 1803 remote-endpoint = <&merge_funnel_out>; 1804 }; 1805 }; 1806 }; 1807 1808 out-ports { 1809 port { 1810 etf_out: endpoint { 1811 remote-endpoint = <&replicator_in>; 1812 }; 1813 }; 1814 }; 1815 }; 1816 1817 etr@8048000 { 1818 compatible = "arm,coresight-tmc", "arm,primecell"; 1819 reg = <0x0 0x08048000 0x0 0x1000>; 1820 1821 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1822 clock-names = "apb_pclk"; 1823 1824 status = "disabled"; 1825 1826 in-ports { 1827 port { 1828 etr_in: endpoint { 1829 remote-endpoint = <&replicator_out>; 1830 }; 1831 }; 1832 }; 1833 }; 1834 1835 funnel@8041000 { 1836 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1837 reg = <0x0 0x08041000 0x0 0x1000>; 1838 1839 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1840 clock-names = "apb_pclk"; 1841 1842 status = "disabled"; 1843 1844 out-ports { 1845 port { 1846 funnel_in0_out: endpoint { 1847 remote-endpoint = <&merge_funnel_in0>; 1848 }; 1849 }; 1850 }; 1851 1852 in-ports { 1853 port { 1854 funnel_in0_in: endpoint { 1855 remote-endpoint = <&stm_out>; 1856 }; 1857 }; 1858 }; 1859 }; 1860 1861 funnel@8042000 { 1862 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1863 reg = <0x0 0x08042000 0x0 0x1000>; 1864 1865 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1866 clock-names = "apb_pclk"; 1867 1868 status = "disabled"; 1869 1870 out-ports { 1871 port { 1872 funnel_in1_out: endpoint { 1873 remote-endpoint = <&merge_funnel_in1>; 1874 }; 1875 }; 1876 }; 1877 1878 in-ports { 1879 port { 1880 funnel_in1_in: endpoint { 1881 remote-endpoint = <&funnel_apss1_out>; 1882 }; 1883 }; 1884 }; 1885 }; 1886 1887 funnel@8045000 { 1888 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1889 reg = <0x0 0x08045000 0x0 0x1000>; 1890 1891 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1892 clock-names = "apb_pclk"; 1893 1894 status = "disabled"; 1895 1896 out-ports { 1897 port { 1898 merge_funnel_out: endpoint { 1899 remote-endpoint = <&etf_in>; 1900 }; 1901 }; 1902 }; 1903 1904 in-ports { 1905 #address-cells = <1>; 1906 #size-cells = <0>; 1907 1908 port@0 { 1909 reg = <0>; 1910 merge_funnel_in0: endpoint { 1911 remote-endpoint = <&funnel_in0_out>; 1912 }; 1913 }; 1914 1915 port@1 { 1916 reg = <1>; 1917 merge_funnel_in1: endpoint { 1918 remote-endpoint = <&funnel_in1_out>; 1919 }; 1920 }; 1921 }; 1922 }; 1923 1924 etm@9040000 { 1925 compatible = "arm,coresight-etm4x", "arm,primecell"; 1926 reg = <0x0 0x09040000 0x0 0x1000>; 1927 1928 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1929 clock-names = "apb_pclk"; 1930 arm,coresight-loses-context-with-cpu; 1931 1932 cpu = <&CPU0>; 1933 1934 status = "disabled"; 1935 1936 out-ports { 1937 port { 1938 etm0_out: endpoint { 1939 remote-endpoint = <&funnel_apss0_in0>; 1940 }; 1941 }; 1942 }; 1943 }; 1944 1945 etm@9140000 { 1946 compatible = "arm,coresight-etm4x", "arm,primecell"; 1947 reg = <0x0 0x09140000 0x0 0x1000>; 1948 1949 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1950 clock-names = "apb_pclk"; 1951 arm,coresight-loses-context-with-cpu; 1952 1953 cpu = <&CPU1>; 1954 1955 status = "disabled"; 1956 1957 out-ports { 1958 port { 1959 etm1_out: endpoint { 1960 remote-endpoint = <&funnel_apss0_in1>; 1961 }; 1962 }; 1963 }; 1964 }; 1965 1966 etm@9240000 { 1967 compatible = "arm,coresight-etm4x", "arm,primecell"; 1968 reg = <0x0 0x09240000 0x0 0x1000>; 1969 1970 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1971 clock-names = "apb_pclk"; 1972 arm,coresight-loses-context-with-cpu; 1973 1974 cpu = <&CPU2>; 1975 1976 status = "disabled"; 1977 1978 out-ports { 1979 port { 1980 etm2_out: endpoint { 1981 remote-endpoint = <&funnel_apss0_in2>; 1982 }; 1983 }; 1984 }; 1985 }; 1986 1987 etm@9340000 { 1988 compatible = "arm,coresight-etm4x", "arm,primecell"; 1989 reg = <0x0 0x09340000 0x0 0x1000>; 1990 1991 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1992 clock-names = "apb_pclk"; 1993 arm,coresight-loses-context-with-cpu; 1994 1995 cpu = <&CPU3>; 1996 1997 status = "disabled"; 1998 1999 out-ports { 2000 port { 2001 etm3_out: endpoint { 2002 remote-endpoint = <&funnel_apss0_in3>; 2003 }; 2004 }; 2005 }; 2006 }; 2007 2008 etm@9440000 { 2009 compatible = "arm,coresight-etm4x", "arm,primecell"; 2010 reg = <0x0 0x09440000 0x0 0x1000>; 2011 2012 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2013 clock-names = "apb_pclk"; 2014 arm,coresight-loses-context-with-cpu; 2015 2016 cpu = <&CPU4>; 2017 2018 status = "disabled"; 2019 2020 out-ports { 2021 port { 2022 etm4_out: endpoint { 2023 remote-endpoint = <&funnel_apss0_in4>; 2024 }; 2025 }; 2026 }; 2027 }; 2028 2029 etm@9540000 { 2030 compatible = "arm,coresight-etm4x", "arm,primecell"; 2031 reg = <0x0 0x09540000 0x0 0x1000>; 2032 2033 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2034 clock-names = "apb_pclk"; 2035 arm,coresight-loses-context-with-cpu; 2036 2037 cpu = <&CPU5>; 2038 2039 status = "disabled"; 2040 2041 out-ports { 2042 port { 2043 etm5_out: endpoint { 2044 remote-endpoint = <&funnel_apss0_in5>; 2045 }; 2046 }; 2047 }; 2048 }; 2049 2050 etm@9640000 { 2051 compatible = "arm,coresight-etm4x", "arm,primecell"; 2052 reg = <0x0 0x09640000 0x0 0x1000>; 2053 2054 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2055 clock-names = "apb_pclk"; 2056 arm,coresight-loses-context-with-cpu; 2057 2058 cpu = <&CPU6>; 2059 2060 status = "disabled"; 2061 2062 out-ports { 2063 port { 2064 etm6_out: endpoint { 2065 remote-endpoint = <&funnel_apss0_in6>; 2066 }; 2067 }; 2068 }; 2069 }; 2070 2071 etm@9740000 { 2072 compatible = "arm,coresight-etm4x", "arm,primecell"; 2073 reg = <0x0 0x09740000 0x0 0x1000>; 2074 2075 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2076 clock-names = "apb_pclk"; 2077 arm,coresight-loses-context-with-cpu; 2078 2079 cpu = <&CPU7>; 2080 2081 status = "disabled"; 2082 2083 out-ports { 2084 port { 2085 etm7_out: endpoint { 2086 remote-endpoint = <&funnel_apss0_in7>; 2087 }; 2088 }; 2089 }; 2090 }; 2091 2092 funnel@9800000 { 2093 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2094 reg = <0x0 0x09800000 0x0 0x1000>; 2095 2096 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2097 clock-names = "apb_pclk"; 2098 2099 status = "disabled"; 2100 2101 out-ports { 2102 port { 2103 funnel_apss0_out: endpoint { 2104 remote-endpoint = <&funnel_apss1_in>; 2105 }; 2106 }; 2107 }; 2108 2109 in-ports { 2110 #address-cells = <1>; 2111 #size-cells = <0>; 2112 2113 port@0 { 2114 reg = <0>; 2115 funnel_apss0_in0: endpoint { 2116 remote-endpoint = <&etm0_out>; 2117 }; 2118 }; 2119 2120 port@1 { 2121 reg = <1>; 2122 funnel_apss0_in1: endpoint { 2123 remote-endpoint = <&etm1_out>; 2124 }; 2125 }; 2126 2127 port@2 { 2128 reg = <2>; 2129 funnel_apss0_in2: endpoint { 2130 remote-endpoint = <&etm2_out>; 2131 }; 2132 }; 2133 2134 port@3 { 2135 reg = <3>; 2136 funnel_apss0_in3: endpoint { 2137 remote-endpoint = <&etm3_out>; 2138 }; 2139 }; 2140 2141 port@4 { 2142 reg = <4>; 2143 funnel_apss0_in4: endpoint { 2144 remote-endpoint = <&etm4_out>; 2145 }; 2146 }; 2147 2148 port@5 { 2149 reg = <5>; 2150 funnel_apss0_in5: endpoint { 2151 remote-endpoint = <&etm5_out>; 2152 }; 2153 }; 2154 2155 port@6 { 2156 reg = <6>; 2157 funnel_apss0_in6: endpoint { 2158 remote-endpoint = <&etm6_out>; 2159 }; 2160 }; 2161 2162 port@7 { 2163 reg = <7>; 2164 funnel_apss0_in7: endpoint { 2165 remote-endpoint = <&etm7_out>; 2166 }; 2167 }; 2168 }; 2169 }; 2170 2171 funnel@9810000 { 2172 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2173 reg = <0x0 0x09810000 0x0 0x1000>; 2174 2175 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2176 clock-names = "apb_pclk"; 2177 2178 status = "disabled"; 2179 2180 out-ports { 2181 port { 2182 funnel_apss1_out: endpoint { 2183 remote-endpoint = <&funnel_in1_in>; 2184 }; 2185 }; 2186 }; 2187 2188 in-ports { 2189 port { 2190 funnel_apss1_in: endpoint { 2191 remote-endpoint = <&funnel_apss0_out>; 2192 }; 2193 }; 2194 }; 2195 }; 2196 2197 remoteproc_adsp: remoteproc@ab00000 { 2198 compatible = "qcom,sm6115-adsp-pas"; 2199 reg = <0x0 0x0ab00000 0x0 0x100>; 2200 2201 interrupts-extended = <&intc GIC_SPI 282 IRQ_TYPE_EDGE_RISING>, 2202 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2203 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2204 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2205 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2206 interrupt-names = "wdog", "fatal", "ready", 2207 "handover", "stop-ack"; 2208 2209 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 2210 clock-names = "xo"; 2211 2212 power-domains = <&rpmpd SM6115_VDD_LPI_CX>, 2213 <&rpmpd SM6115_VDD_LPI_MX>; 2214 2215 memory-region = <&pil_adsp_mem>; 2216 2217 qcom,smem-states = <&adsp_smp2p_out 0>; 2218 qcom,smem-state-names = "stop"; 2219 2220 status = "disabled"; 2221 2222 glink-edge { 2223 interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>; 2224 label = "lpass"; 2225 qcom,remote-pid = <2>; 2226 mboxes = <&apcs_glb 8>; 2227 2228 fastrpc { 2229 compatible = "qcom,fastrpc"; 2230 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2231 label = "adsp"; 2232 qcom,non-secure-domain; 2233 #address-cells = <1>; 2234 #size-cells = <0>; 2235 2236 compute-cb@3 { 2237 compatible = "qcom,fastrpc-compute-cb"; 2238 reg = <3>; 2239 iommus = <&apps_smmu 0x01c3 0x0>; 2240 }; 2241 2242 compute-cb@4 { 2243 compatible = "qcom,fastrpc-compute-cb"; 2244 reg = <4>; 2245 iommus = <&apps_smmu 0x01c4 0x0>; 2246 }; 2247 2248 compute-cb@5 { 2249 compatible = "qcom,fastrpc-compute-cb"; 2250 reg = <5>; 2251 iommus = <&apps_smmu 0x01c5 0x0>; 2252 }; 2253 2254 compute-cb@6 { 2255 compatible = "qcom,fastrpc-compute-cb"; 2256 reg = <6>; 2257 iommus = <&apps_smmu 0x01c6 0x0>; 2258 }; 2259 2260 compute-cb@7 { 2261 compatible = "qcom,fastrpc-compute-cb"; 2262 reg = <7>; 2263 iommus = <&apps_smmu 0x01c7 0x0>; 2264 }; 2265 }; 2266 }; 2267 }; 2268 2269 remoteproc_cdsp: remoteproc@b300000 { 2270 compatible = "qcom,sm6115-cdsp-pas"; 2271 reg = <0x0 0x0b300000 0x0 0x100000>; 2272 2273 interrupts-extended = <&intc GIC_SPI 265 IRQ_TYPE_EDGE_RISING>, 2274 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2275 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2276 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2277 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2278 interrupt-names = "wdog", "fatal", "ready", 2279 "handover", "stop-ack"; 2280 2281 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 2282 clock-names = "xo"; 2283 2284 power-domains = <&rpmpd SM6115_VDDCX>; 2285 2286 memory-region = <&pil_cdsp_mem>; 2287 2288 qcom,smem-states = <&cdsp_smp2p_out 0>; 2289 qcom,smem-state-names = "stop"; 2290 2291 status = "disabled"; 2292 2293 glink-edge { 2294 interrupts = <GIC_SPI 261 IRQ_TYPE_EDGE_RISING>; 2295 label = "cdsp"; 2296 qcom,remote-pid = <5>; 2297 mboxes = <&apcs_glb 28>; 2298 2299 fastrpc { 2300 compatible = "qcom,fastrpc"; 2301 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2302 label = "cdsp"; 2303 qcom,non-secure-domain; 2304 #address-cells = <1>; 2305 #size-cells = <0>; 2306 2307 compute-cb@1 { 2308 compatible = "qcom,fastrpc-compute-cb"; 2309 reg = <1>; 2310 iommus = <&apps_smmu 0x0c01 0x0>; 2311 }; 2312 2313 compute-cb@2 { 2314 compatible = "qcom,fastrpc-compute-cb"; 2315 reg = <2>; 2316 iommus = <&apps_smmu 0x0c02 0x0>; 2317 }; 2318 2319 compute-cb@3 { 2320 compatible = "qcom,fastrpc-compute-cb"; 2321 reg = <3>; 2322 iommus = <&apps_smmu 0x0c03 0x0>; 2323 }; 2324 2325 compute-cb@4 { 2326 compatible = "qcom,fastrpc-compute-cb"; 2327 reg = <4>; 2328 iommus = <&apps_smmu 0x0c04 0x0>; 2329 }; 2330 2331 compute-cb@5 { 2332 compatible = "qcom,fastrpc-compute-cb"; 2333 reg = <5>; 2334 iommus = <&apps_smmu 0x0c05 0x0>; 2335 }; 2336 2337 compute-cb@6 { 2338 compatible = "qcom,fastrpc-compute-cb"; 2339 reg = <6>; 2340 iommus = <&apps_smmu 0x0c06 0x0>; 2341 }; 2342 2343 /* note: secure cb9 in downstream */ 2344 }; 2345 }; 2346 }; 2347 2348 apps_smmu: iommu@c600000 { 2349 compatible = "qcom,sm6115-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 2350 reg = <0x0 0x0c600000 0x0 0x80000>; 2351 #iommu-cells = <2>; 2352 #global-interrupts = <1>; 2353 2354 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 2355 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 2356 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 2357 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 2358 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 2359 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 2360 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 2361 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 2362 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 2363 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 2364 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 2365 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 2366 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 2367 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 2368 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 2369 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 2370 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 2371 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 2372 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 2373 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 2374 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 2375 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 2376 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 2377 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 2378 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 2379 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 2380 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 2381 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 2382 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 2383 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 2384 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 2385 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 2386 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 2387 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 2388 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 2389 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 2390 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 2391 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 2392 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 2393 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 2394 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 2395 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 2396 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 2397 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 2398 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 2399 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 2400 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 2401 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 2402 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 2403 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 2404 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 2405 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 2406 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 2407 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 2408 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 2409 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 2410 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 2411 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 2412 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 2413 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 2414 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 2415 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 2416 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 2417 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 2418 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 2419 }; 2420 2421 wifi: wifi@c800000 { 2422 compatible = "qcom,wcn3990-wifi"; 2423 reg = <0x0 0x0c800000 0x0 0x800000>; 2424 reg-names = "membase"; 2425 memory-region = <&wlan_msa_mem>; 2426 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, 2427 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, 2428 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, 2429 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>, 2430 <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>, 2431 <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>, 2432 <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>, 2433 <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>, 2434 <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>, 2435 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>, 2436 <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, 2437 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 2438 iommus = <&apps_smmu 0x1a0 0x1>; 2439 qcom,msa-fixed-perm; 2440 status = "disabled"; 2441 }; 2442 2443 watchdog@f017000 { 2444 compatible = "qcom,apss-wdt-sm6115", "qcom,kpss-wdt"; 2445 reg = <0x0 0x0f017000 0x0 0x1000>; 2446 clocks = <&sleep_clk>; 2447 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 2448 }; 2449 2450 apcs_glb: mailbox@f111000 { 2451 compatible = "qcom,sm6115-apcs-hmss-global", 2452 "qcom,msm8994-apcs-kpss-global"; 2453 reg = <0x0 0x0f111000 0x0 0x1000>; 2454 2455 #mbox-cells = <1>; 2456 }; 2457 2458 timer@f120000 { 2459 compatible = "arm,armv7-timer-mem"; 2460 reg = <0x0 0x0f120000 0x0 0x1000>; 2461 #address-cells = <2>; 2462 #size-cells = <2>; 2463 ranges; 2464 clock-frequency = <19200000>; 2465 2466 frame@f121000 { 2467 reg = <0x0 0x0f121000 0x0 0x1000>, <0x0 0x0f122000 0x0 0x1000>; 2468 frame-number = <0>; 2469 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 2470 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 2471 }; 2472 2473 frame@f123000 { 2474 reg = <0x0 0x0f123000 0x0 0x1000>; 2475 frame-number = <1>; 2476 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 2477 status = "disabled"; 2478 }; 2479 2480 frame@f124000 { 2481 reg = <0x0 0x0f124000 0x0 0x1000>; 2482 frame-number = <2>; 2483 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 2484 status = "disabled"; 2485 }; 2486 2487 frame@f125000 { 2488 reg = <0x0 0x0f125000 0x0 0x1000>; 2489 frame-number = <3>; 2490 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 2491 status = "disabled"; 2492 }; 2493 2494 frame@f126000 { 2495 reg = <0x0 0x0f126000 0x0 0x1000>; 2496 frame-number = <4>; 2497 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 2498 status = "disabled"; 2499 }; 2500 2501 frame@f127000 { 2502 reg = <0x0 0x0f127000 0x0 0x1000>; 2503 frame-number = <5>; 2504 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 2505 status = "disabled"; 2506 }; 2507 2508 frame@f128000 { 2509 reg = <0x0 0x0f128000 0x0 0x1000>; 2510 frame-number = <6>; 2511 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 2512 status = "disabled"; 2513 }; 2514 }; 2515 2516 intc: interrupt-controller@f200000 { 2517 compatible = "arm,gic-v3"; 2518 reg = <0x0 0x0f200000 0x0 0x10000>, 2519 <0x0 0x0f300000 0x0 0x100000>; 2520 #interrupt-cells = <3>; 2521 interrupt-controller; 2522 interrupt-parent = <&intc>; 2523 #redistributor-regions = <1>; 2524 redistributor-stride = <0x0 0x20000>; 2525 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 2526 }; 2527 2528 cpufreq_hw: cpufreq@f521000 { 2529 compatible = "qcom,sm6115-cpufreq-hw", "qcom,cpufreq-hw"; 2530 reg = <0x0 0x0f521000 0x0 0x1000>, 2531 <0x0 0x0f523000 0x0 0x1000>; 2532 2533 reg-names = "freq-domain0", "freq-domain1"; 2534 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>; 2535 clock-names = "xo", "alternate"; 2536 2537 #freq-domain-cells = <1>; 2538 #clock-cells = <1>; 2539 }; 2540 }; 2541 2542 thermal-zones { 2543 mapss-thermal { 2544 polling-delay-passive = <0>; 2545 polling-delay = <0>; 2546 thermal-sensors = <&tsens0 0>; 2547 2548 trips { 2549 trip-point0 { 2550 temperature = <115000>; 2551 hysteresis = <5000>; 2552 type = "passive"; 2553 }; 2554 2555 trip-point1 { 2556 temperature = <125000>; 2557 hysteresis = <1000>; 2558 type = "passive"; 2559 }; 2560 }; 2561 }; 2562 2563 cdsp-hvx-thermal { 2564 polling-delay-passive = <0>; 2565 polling-delay = <0>; 2566 thermal-sensors = <&tsens0 1>; 2567 2568 trips { 2569 trip-point0 { 2570 temperature = <115000>; 2571 hysteresis = <5000>; 2572 type = "passive"; 2573 }; 2574 2575 trip-point1 { 2576 temperature = <125000>; 2577 hysteresis = <1000>; 2578 type = "passive"; 2579 }; 2580 }; 2581 }; 2582 2583 wlan-thermal { 2584 polling-delay-passive = <0>; 2585 polling-delay = <0>; 2586 thermal-sensors = <&tsens0 2>; 2587 2588 trips { 2589 trip-point0 { 2590 temperature = <115000>; 2591 hysteresis = <5000>; 2592 type = "passive"; 2593 }; 2594 2595 trip-point1 { 2596 temperature = <125000>; 2597 hysteresis = <1000>; 2598 type = "passive"; 2599 }; 2600 }; 2601 }; 2602 2603 camera-thermal { 2604 polling-delay-passive = <0>; 2605 polling-delay = <0>; 2606 thermal-sensors = <&tsens0 3>; 2607 2608 trips { 2609 trip-point0 { 2610 temperature = <115000>; 2611 hysteresis = <5000>; 2612 type = "passive"; 2613 }; 2614 2615 trip-point1 { 2616 temperature = <125000>; 2617 hysteresis = <1000>; 2618 type = "passive"; 2619 }; 2620 }; 2621 }; 2622 2623 video-thermal { 2624 polling-delay-passive = <0>; 2625 polling-delay = <0>; 2626 thermal-sensors = <&tsens0 4>; 2627 2628 trips { 2629 trip-point0 { 2630 temperature = <115000>; 2631 hysteresis = <5000>; 2632 type = "passive"; 2633 }; 2634 2635 trip-point1 { 2636 temperature = <125000>; 2637 hysteresis = <1000>; 2638 type = "passive"; 2639 }; 2640 }; 2641 }; 2642 2643 modem1-thermal { 2644 polling-delay-passive = <0>; 2645 polling-delay = <0>; 2646 thermal-sensors = <&tsens0 5>; 2647 2648 trips { 2649 trip-point0 { 2650 temperature = <115000>; 2651 hysteresis = <5000>; 2652 type = "passive"; 2653 }; 2654 2655 trip-point1 { 2656 temperature = <125000>; 2657 hysteresis = <1000>; 2658 type = "passive"; 2659 }; 2660 }; 2661 }; 2662 2663 cpu4-thermal { 2664 polling-delay-passive = <0>; 2665 polling-delay = <0>; 2666 thermal-sensors = <&tsens0 6>; 2667 2668 trips { 2669 cpu4_alert0: trip-point0 { 2670 temperature = <90000>; 2671 hysteresis = <2000>; 2672 type = "passive"; 2673 }; 2674 2675 cpu4_alert1: trip-point1 { 2676 temperature = <95000>; 2677 hysteresis = <2000>; 2678 type = "passive"; 2679 }; 2680 2681 cpu4_crit: cpu_crit { 2682 temperature = <110000>; 2683 hysteresis = <1000>; 2684 type = "critical"; 2685 }; 2686 }; 2687 }; 2688 2689 cpu5-thermal { 2690 polling-delay-passive = <0>; 2691 polling-delay = <0>; 2692 thermal-sensors = <&tsens0 7>; 2693 2694 trips { 2695 cpu5_alert0: trip-point0 { 2696 temperature = <90000>; 2697 hysteresis = <2000>; 2698 type = "passive"; 2699 }; 2700 2701 cpu5_alert1: trip-point1 { 2702 temperature = <95000>; 2703 hysteresis = <2000>; 2704 type = "passive"; 2705 }; 2706 2707 cpu5_crit: cpu_crit { 2708 temperature = <110000>; 2709 hysteresis = <1000>; 2710 type = "critical"; 2711 }; 2712 }; 2713 }; 2714 2715 cpu6-thermal { 2716 polling-delay-passive = <0>; 2717 polling-delay = <0>; 2718 thermal-sensors = <&tsens0 8>; 2719 2720 trips { 2721 cpu6_alert0: trip-point0 { 2722 temperature = <90000>; 2723 hysteresis = <2000>; 2724 type = "passive"; 2725 }; 2726 2727 cpu6_alert1: trip-point1 { 2728 temperature = <95000>; 2729 hysteresis = <2000>; 2730 type = "passive"; 2731 }; 2732 2733 cpu6_crit: cpu_crit { 2734 temperature = <110000>; 2735 hysteresis = <1000>; 2736 type = "critical"; 2737 }; 2738 }; 2739 }; 2740 2741 cpu7-thermal { 2742 polling-delay-passive = <0>; 2743 polling-delay = <0>; 2744 thermal-sensors = <&tsens0 9>; 2745 2746 trips { 2747 cpu7_alert0: trip-point0 { 2748 temperature = <90000>; 2749 hysteresis = <2000>; 2750 type = "passive"; 2751 }; 2752 2753 cpu7_alert1: trip-point1 { 2754 temperature = <95000>; 2755 hysteresis = <2000>; 2756 type = "passive"; 2757 }; 2758 2759 cpu7_crit: cpu_crit { 2760 temperature = <110000>; 2761 hysteresis = <1000>; 2762 type = "critical"; 2763 }; 2764 }; 2765 }; 2766 2767 cpu45-thermal { 2768 polling-delay-passive = <0>; 2769 polling-delay = <0>; 2770 thermal-sensors = <&tsens0 10>; 2771 2772 trips { 2773 cpu45_alert0: trip-point0 { 2774 temperature = <90000>; 2775 hysteresis = <2000>; 2776 type = "passive"; 2777 }; 2778 2779 cpu45_alert1: trip-point1 { 2780 temperature = <95000>; 2781 hysteresis = <2000>; 2782 type = "passive"; 2783 }; 2784 2785 cpu45_crit: cpu_crit { 2786 temperature = <110000>; 2787 hysteresis = <1000>; 2788 type = "critical"; 2789 }; 2790 }; 2791 }; 2792 2793 cpu67-thermal { 2794 polling-delay-passive = <0>; 2795 polling-delay = <0>; 2796 thermal-sensors = <&tsens0 11>; 2797 2798 trips { 2799 cpu67_alert0: trip-point0 { 2800 temperature = <90000>; 2801 hysteresis = <2000>; 2802 type = "passive"; 2803 }; 2804 2805 cpu67_alert1: trip-point1 { 2806 temperature = <95000>; 2807 hysteresis = <2000>; 2808 type = "passive"; 2809 }; 2810 2811 cpu67_crit: cpu_crit { 2812 temperature = <110000>; 2813 hysteresis = <1000>; 2814 type = "critical"; 2815 }; 2816 }; 2817 }; 2818 2819 cpu0123-thermal { 2820 polling-delay-passive = <0>; 2821 polling-delay = <0>; 2822 thermal-sensors = <&tsens0 12>; 2823 2824 trips { 2825 cpu0123_alert0: trip-point0 { 2826 temperature = <90000>; 2827 hysteresis = <2000>; 2828 type = "passive"; 2829 }; 2830 2831 cpu0123_alert1: trip-point1 { 2832 temperature = <95000>; 2833 hysteresis = <2000>; 2834 type = "passive"; 2835 }; 2836 2837 cpu0123_crit: cpu_crit { 2838 temperature = <110000>; 2839 hysteresis = <1000>; 2840 type = "critical"; 2841 }; 2842 }; 2843 }; 2844 2845 modem0-thermal { 2846 polling-delay-passive = <0>; 2847 polling-delay = <0>; 2848 thermal-sensors = <&tsens0 13>; 2849 2850 trips { 2851 trip-point0 { 2852 temperature = <115000>; 2853 hysteresis = <5000>; 2854 type = "passive"; 2855 }; 2856 2857 trip-point1 { 2858 temperature = <125000>; 2859 hysteresis = <1000>; 2860 type = "passive"; 2861 }; 2862 }; 2863 }; 2864 2865 display-thermal { 2866 polling-delay-passive = <0>; 2867 polling-delay = <0>; 2868 thermal-sensors = <&tsens0 14>; 2869 2870 trips { 2871 trip-point0 { 2872 temperature = <115000>; 2873 hysteresis = <5000>; 2874 type = "passive"; 2875 }; 2876 2877 trip-point1 { 2878 temperature = <125000>; 2879 hysteresis = <1000>; 2880 type = "passive"; 2881 }; 2882 }; 2883 }; 2884 2885 gpu-thermal { 2886 polling-delay-passive = <0>; 2887 polling-delay = <0>; 2888 thermal-sensors = <&tsens0 15>; 2889 2890 trips { 2891 trip-point0 { 2892 temperature = <115000>; 2893 hysteresis = <5000>; 2894 type = "passive"; 2895 }; 2896 2897 trip-point1 { 2898 temperature = <125000>; 2899 hysteresis = <1000>; 2900 type = "passive"; 2901 }; 2902 }; 2903 }; 2904 }; 2905 2906 timer { 2907 compatible = "arm,armv8-timer"; 2908 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2909 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2910 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2911 <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 2912 }; 2913}; 2914