1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright (c) 2021, Iskren Chernev <iskren.chernev@gmail.com> 4 */ 5 6#include <dt-bindings/clock/qcom,gcc-sm6115.h> 7#include <dt-bindings/clock/qcom,sm6115-dispcc.h> 8#include <dt-bindings/clock/qcom,sm6115-gpucc.h> 9#include <dt-bindings/clock/qcom,rpmcc.h> 10#include <dt-bindings/dma/qcom-gpi.h> 11#include <dt-bindings/firmware/qcom,scm.h> 12#include <dt-bindings/gpio/gpio.h> 13#include <dt-bindings/interrupt-controller/arm-gic.h> 14#include <dt-bindings/power/qcom-rpmpd.h> 15 16/ { 17 interrupt-parent = <&intc>; 18 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 chosen { }; 23 24 clocks { 25 xo_board: xo-board { 26 compatible = "fixed-clock"; 27 #clock-cells = <0>; 28 }; 29 30 sleep_clk: sleep-clk { 31 compatible = "fixed-clock"; 32 #clock-cells = <0>; 33 }; 34 }; 35 36 cpus { 37 #address-cells = <2>; 38 #size-cells = <0>; 39 40 CPU0: cpu@0 { 41 device_type = "cpu"; 42 compatible = "qcom,kryo260"; 43 reg = <0x0 0x0>; 44 clocks = <&cpufreq_hw 0>; 45 capacity-dmips-mhz = <1024>; 46 dynamic-power-coefficient = <100>; 47 enable-method = "psci"; 48 next-level-cache = <&L2_0>; 49 qcom,freq-domain = <&cpufreq_hw 0>; 50 power-domains = <&CPU_PD0>; 51 power-domain-names = "psci"; 52 L2_0: l2-cache { 53 compatible = "cache"; 54 cache-level = <2>; 55 }; 56 }; 57 58 CPU1: cpu@1 { 59 device_type = "cpu"; 60 compatible = "qcom,kryo260"; 61 reg = <0x0 0x1>; 62 clocks = <&cpufreq_hw 0>; 63 capacity-dmips-mhz = <1024>; 64 dynamic-power-coefficient = <100>; 65 enable-method = "psci"; 66 next-level-cache = <&L2_0>; 67 qcom,freq-domain = <&cpufreq_hw 0>; 68 power-domains = <&CPU_PD1>; 69 power-domain-names = "psci"; 70 }; 71 72 CPU2: cpu@2 { 73 device_type = "cpu"; 74 compatible = "qcom,kryo260"; 75 reg = <0x0 0x2>; 76 clocks = <&cpufreq_hw 0>; 77 capacity-dmips-mhz = <1024>; 78 dynamic-power-coefficient = <100>; 79 enable-method = "psci"; 80 next-level-cache = <&L2_0>; 81 qcom,freq-domain = <&cpufreq_hw 0>; 82 power-domains = <&CPU_PD2>; 83 power-domain-names = "psci"; 84 }; 85 86 CPU3: cpu@3 { 87 device_type = "cpu"; 88 compatible = "qcom,kryo260"; 89 reg = <0x0 0x3>; 90 clocks = <&cpufreq_hw 0>; 91 capacity-dmips-mhz = <1024>; 92 dynamic-power-coefficient = <100>; 93 enable-method = "psci"; 94 next-level-cache = <&L2_0>; 95 qcom,freq-domain = <&cpufreq_hw 0>; 96 power-domains = <&CPU_PD3>; 97 power-domain-names = "psci"; 98 }; 99 100 CPU4: cpu@100 { 101 device_type = "cpu"; 102 compatible = "qcom,kryo260"; 103 reg = <0x0 0x100>; 104 clocks = <&cpufreq_hw 1>; 105 enable-method = "psci"; 106 capacity-dmips-mhz = <1638>; 107 dynamic-power-coefficient = <282>; 108 next-level-cache = <&L2_1>; 109 qcom,freq-domain = <&cpufreq_hw 1>; 110 power-domains = <&CPU_PD4>; 111 power-domain-names = "psci"; 112 L2_1: l2-cache { 113 compatible = "cache"; 114 cache-level = <2>; 115 }; 116 }; 117 118 CPU5: cpu@101 { 119 device_type = "cpu"; 120 compatible = "qcom,kryo260"; 121 reg = <0x0 0x101>; 122 clocks = <&cpufreq_hw 1>; 123 capacity-dmips-mhz = <1638>; 124 dynamic-power-coefficient = <282>; 125 enable-method = "psci"; 126 next-level-cache = <&L2_1>; 127 qcom,freq-domain = <&cpufreq_hw 1>; 128 power-domains = <&CPU_PD5>; 129 power-domain-names = "psci"; 130 }; 131 132 CPU6: cpu@102 { 133 device_type = "cpu"; 134 compatible = "qcom,kryo260"; 135 reg = <0x0 0x102>; 136 clocks = <&cpufreq_hw 1>; 137 capacity-dmips-mhz = <1638>; 138 dynamic-power-coefficient = <282>; 139 enable-method = "psci"; 140 next-level-cache = <&L2_1>; 141 qcom,freq-domain = <&cpufreq_hw 1>; 142 power-domains = <&CPU_PD6>; 143 power-domain-names = "psci"; 144 }; 145 146 CPU7: cpu@103 { 147 device_type = "cpu"; 148 compatible = "qcom,kryo260"; 149 reg = <0x0 0x103>; 150 clocks = <&cpufreq_hw 1>; 151 capacity-dmips-mhz = <1638>; 152 dynamic-power-coefficient = <282>; 153 enable-method = "psci"; 154 next-level-cache = <&L2_1>; 155 qcom,freq-domain = <&cpufreq_hw 1>; 156 power-domains = <&CPU_PD7>; 157 power-domain-names = "psci"; 158 }; 159 160 cpu-map { 161 cluster0 { 162 core0 { 163 cpu = <&CPU0>; 164 }; 165 166 core1 { 167 cpu = <&CPU1>; 168 }; 169 170 core2 { 171 cpu = <&CPU2>; 172 }; 173 174 core3 { 175 cpu = <&CPU3>; 176 }; 177 }; 178 179 cluster1 { 180 core0 { 181 cpu = <&CPU4>; 182 }; 183 184 core1 { 185 cpu = <&CPU5>; 186 }; 187 188 core2 { 189 cpu = <&CPU6>; 190 }; 191 192 core3 { 193 cpu = <&CPU7>; 194 }; 195 }; 196 }; 197 198 idle-states { 199 entry-method = "psci"; 200 201 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 202 compatible = "arm,idle-state"; 203 idle-state-name = "silver-rail-power-collapse"; 204 arm,psci-suspend-param = <0x40000003>; 205 entry-latency-us = <290>; 206 exit-latency-us = <376>; 207 min-residency-us = <1182>; 208 local-timer-stop; 209 }; 210 211 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 212 compatible = "arm,idle-state"; 213 idle-state-name = "gold-rail-power-collapse"; 214 arm,psci-suspend-param = <0x40000003>; 215 entry-latency-us = <297>; 216 exit-latency-us = <324>; 217 min-residency-us = <1110>; 218 local-timer-stop; 219 }; 220 }; 221 222 domain-idle-states { 223 CLUSTER_0_SLEEP_0: cluster-sleep-0-0 { 224 /* GDHS */ 225 compatible = "domain-idle-state"; 226 arm,psci-suspend-param = <0x40000022>; 227 entry-latency-us = <360>; 228 exit-latency-us = <421>; 229 min-residency-us = <782>; 230 }; 231 232 CLUSTER_0_SLEEP_1: cluster-sleep-0-1 { 233 /* Power Collapse */ 234 compatible = "domain-idle-state"; 235 arm,psci-suspend-param = <0x41000044>; 236 entry-latency-us = <800>; 237 exit-latency-us = <2118>; 238 min-residency-us = <7376>; 239 }; 240 241 CLUSTER_1_SLEEP_0: cluster-sleep-1-0 { 242 /* GDHS */ 243 compatible = "domain-idle-state"; 244 arm,psci-suspend-param = <0x40000042>; 245 entry-latency-us = <314>; 246 exit-latency-us = <345>; 247 min-residency-us = <660>; 248 }; 249 250 CLUSTER_1_SLEEP_1: cluster-sleep-1-1 { 251 /* Power Collapse */ 252 compatible = "domain-idle-state"; 253 arm,psci-suspend-param = <0x41000044>; 254 entry-latency-us = <640>; 255 exit-latency-us = <1654>; 256 min-residency-us = <8094>; 257 }; 258 }; 259 }; 260 261 firmware { 262 scm: scm { 263 compatible = "qcom,scm-sm6115", "qcom,scm"; 264 #reset-cells = <1>; 265 }; 266 }; 267 268 memory@80000000 { 269 device_type = "memory"; 270 /* We expect the bootloader to fill in the size */ 271 reg = <0 0x80000000 0 0>; 272 }; 273 274 pmu { 275 compatible = "arm,armv8-pmuv3"; 276 interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>; 277 }; 278 279 psci { 280 compatible = "arm,psci-1.0"; 281 method = "smc"; 282 283 CPU_PD0: power-domain-cpu0 { 284 #power-domain-cells = <0>; 285 power-domains = <&CLUSTER_0_PD>; 286 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 287 }; 288 289 CPU_PD1: power-domain-cpu1 { 290 #power-domain-cells = <0>; 291 power-domains = <&CLUSTER_0_PD>; 292 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 293 }; 294 295 CPU_PD2: power-domain-cpu2 { 296 #power-domain-cells = <0>; 297 power-domains = <&CLUSTER_0_PD>; 298 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 299 }; 300 301 CPU_PD3: power-domain-cpu3 { 302 #power-domain-cells = <0>; 303 power-domains = <&CLUSTER_0_PD>; 304 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 305 }; 306 307 CPU_PD4: power-domain-cpu4 { 308 #power-domain-cells = <0>; 309 power-domains = <&CLUSTER_1_PD>; 310 domain-idle-states = <&BIG_CPU_SLEEP_0>; 311 }; 312 313 CPU_PD5: power-domain-cpu5 { 314 #power-domain-cells = <0>; 315 power-domains = <&CLUSTER_1_PD>; 316 domain-idle-states = <&BIG_CPU_SLEEP_0>; 317 }; 318 319 CPU_PD6: power-domain-cpu6 { 320 #power-domain-cells = <0>; 321 power-domains = <&CLUSTER_1_PD>; 322 domain-idle-states = <&BIG_CPU_SLEEP_0>; 323 }; 324 325 CPU_PD7: power-domain-cpu7 { 326 #power-domain-cells = <0>; 327 power-domains = <&CLUSTER_1_PD>; 328 domain-idle-states = <&BIG_CPU_SLEEP_0>; 329 }; 330 331 CLUSTER_0_PD: power-domain-cpu-cluster0 { 332 #power-domain-cells = <0>; 333 domain-idle-states = <&CLUSTER_0_SLEEP_0>, <&CLUSTER_0_SLEEP_1>; 334 }; 335 336 CLUSTER_1_PD: power-domain-cpu-cluster1 { 337 #power-domain-cells = <0>; 338 domain-idle-states = <&CLUSTER_1_SLEEP_0>, <&CLUSTER_1_SLEEP_1>; 339 }; 340 }; 341 342 reserved_memory: reserved-memory { 343 #address-cells = <2>; 344 #size-cells = <2>; 345 ranges; 346 347 hyp_mem: memory@45700000 { 348 reg = <0x0 0x45700000 0x0 0x600000>; 349 no-map; 350 }; 351 352 xbl_aop_mem: memory@45e00000 { 353 reg = <0x0 0x45e00000 0x0 0x140000>; 354 no-map; 355 }; 356 357 sec_apps_mem: memory@45fff000 { 358 reg = <0x0 0x45fff000 0x0 0x1000>; 359 no-map; 360 }; 361 362 smem_mem: memory@46000000 { 363 compatible = "qcom,smem"; 364 reg = <0x0 0x46000000 0x0 0x200000>; 365 no-map; 366 367 hwlocks = <&tcsr_mutex 3>; 368 qcom,rpm-msg-ram = <&rpm_msg_ram>; 369 }; 370 371 cdsp_sec_mem: memory@46200000 { 372 reg = <0x0 0x46200000 0x0 0x1e00000>; 373 no-map; 374 }; 375 376 pil_modem_mem: memory@4ab00000 { 377 reg = <0x0 0x4ab00000 0x0 0x6900000>; 378 no-map; 379 }; 380 381 pil_video_mem: memory@51400000 { 382 reg = <0x0 0x51400000 0x0 0x500000>; 383 no-map; 384 }; 385 386 wlan_msa_mem: memory@51900000 { 387 reg = <0x0 0x51900000 0x0 0x100000>; 388 no-map; 389 }; 390 391 pil_cdsp_mem: memory@51a00000 { 392 reg = <0x0 0x51a00000 0x0 0x1e00000>; 393 no-map; 394 }; 395 396 pil_adsp_mem: memory@53800000 { 397 reg = <0x0 0x53800000 0x0 0x2800000>; 398 no-map; 399 }; 400 401 pil_ipa_fw_mem: memory@56100000 { 402 reg = <0x0 0x56100000 0x0 0x10000>; 403 no-map; 404 }; 405 406 pil_ipa_gsi_mem: memory@56110000 { 407 reg = <0x0 0x56110000 0x0 0x5000>; 408 no-map; 409 }; 410 411 pil_gpu_mem: memory@56115000 { 412 reg = <0x0 0x56115000 0x0 0x2000>; 413 no-map; 414 }; 415 416 cont_splash_memory: memory@5c000000 { 417 reg = <0x0 0x5c000000 0x0 0x00f00000>; 418 no-map; 419 }; 420 421 dfps_data_memory: memory@5cf00000 { 422 reg = <0x0 0x5cf00000 0x0 0x0100000>; 423 no-map; 424 }; 425 426 removed_mem: memory@60000000 { 427 reg = <0x0 0x60000000 0x0 0x3900000>; 428 no-map; 429 }; 430 431 rmtfs_mem: memory@89b01000 { 432 compatible = "qcom,rmtfs-mem"; 433 reg = <0x0 0x89b01000 0x0 0x200000>; 434 no-map; 435 436 qcom,client-id = <1>; 437 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA QCOM_SCM_VMID_NAV>; 438 }; 439 }; 440 441 rpm-glink { 442 compatible = "qcom,glink-rpm"; 443 444 interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>; 445 qcom,rpm-msg-ram = <&rpm_msg_ram>; 446 mboxes = <&apcs_glb 0>; 447 448 rpm_requests: rpm-requests { 449 compatible = "qcom,rpm-sm6115"; 450 qcom,glink-channels = "rpm_requests"; 451 452 rpmcc: clock-controller { 453 compatible = "qcom,rpmcc-sm6115", "qcom,rpmcc"; 454 clocks = <&xo_board>; 455 clock-names = "xo"; 456 #clock-cells = <1>; 457 }; 458 459 rpmpd: power-controller { 460 compatible = "qcom,sm6115-rpmpd"; 461 #power-domain-cells = <1>; 462 operating-points-v2 = <&rpmpd_opp_table>; 463 464 rpmpd_opp_table: opp-table { 465 compatible = "operating-points-v2"; 466 467 rpmpd_opp_min_svs: opp1 { 468 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 469 }; 470 471 rpmpd_opp_low_svs: opp2 { 472 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 473 }; 474 475 rpmpd_opp_svs: opp3 { 476 opp-level = <RPM_SMD_LEVEL_SVS>; 477 }; 478 479 rpmpd_opp_svs_plus: opp4 { 480 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 481 }; 482 483 rpmpd_opp_nom: opp5 { 484 opp-level = <RPM_SMD_LEVEL_NOM>; 485 }; 486 487 rpmpd_opp_nom_plus: opp6 { 488 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 489 }; 490 491 rpmpd_opp_turbo: opp7 { 492 opp-level = <RPM_SMD_LEVEL_TURBO>; 493 }; 494 495 rpmpd_opp_turbo_plus: opp8 { 496 opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>; 497 }; 498 }; 499 }; 500 }; 501 }; 502 503 smp2p-adsp { 504 compatible = "qcom,smp2p"; 505 qcom,smem = <443>, <429>; 506 507 interrupts = <GIC_SPI 279 IRQ_TYPE_EDGE_RISING>; 508 509 mboxes = <&apcs_glb 10>; 510 511 qcom,local-pid = <0>; 512 qcom,remote-pid = <2>; 513 514 adsp_smp2p_out: master-kernel { 515 qcom,entry-name = "master-kernel"; 516 #qcom,smem-state-cells = <1>; 517 }; 518 519 adsp_smp2p_in: slave-kernel { 520 qcom,entry-name = "slave-kernel"; 521 522 interrupt-controller; 523 #interrupt-cells = <2>; 524 }; 525 }; 526 527 smp2p-cdsp { 528 compatible = "qcom,smp2p"; 529 qcom,smem = <94>, <432>; 530 531 interrupts = <GIC_SPI 263 IRQ_TYPE_EDGE_RISING>; 532 533 mboxes = <&apcs_glb 30>; 534 535 qcom,local-pid = <0>; 536 qcom,remote-pid = <5>; 537 538 cdsp_smp2p_out: master-kernel { 539 qcom,entry-name = "master-kernel"; 540 #qcom,smem-state-cells = <1>; 541 }; 542 543 cdsp_smp2p_in: slave-kernel { 544 qcom,entry-name = "slave-kernel"; 545 546 interrupt-controller; 547 #interrupt-cells = <2>; 548 }; 549 }; 550 551 smp2p-mpss { 552 compatible = "qcom,smp2p"; 553 qcom,smem = <435>, <428>; 554 555 interrupts = <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>; 556 557 mboxes = <&apcs_glb 14>; 558 559 qcom,local-pid = <0>; 560 qcom,remote-pid = <1>; 561 562 modem_smp2p_out: master-kernel { 563 qcom,entry-name = "master-kernel"; 564 #qcom,smem-state-cells = <1>; 565 }; 566 567 modem_smp2p_in: slave-kernel { 568 qcom,entry-name = "slave-kernel"; 569 570 interrupt-controller; 571 #interrupt-cells = <2>; 572 }; 573 }; 574 575 soc: soc@0 { 576 compatible = "simple-bus"; 577 #address-cells = <2>; 578 #size-cells = <2>; 579 ranges = <0 0 0 0 0x10 0>; 580 dma-ranges = <0 0 0 0 0x10 0>; 581 582 tcsr_mutex: hwlock@340000 { 583 compatible = "qcom,tcsr-mutex"; 584 reg = <0x0 0x00340000 0x0 0x20000>; 585 #hwlock-cells = <1>; 586 }; 587 588 tlmm: pinctrl@500000 { 589 compatible = "qcom,sm6115-tlmm"; 590 reg = <0x0 0x00500000 0x0 0x400000>, 591 <0x0 0x00900000 0x0 0x400000>, 592 <0x0 0x00d00000 0x0 0x400000>; 593 reg-names = "west", "south", "east"; 594 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 595 gpio-controller; 596 gpio-ranges = <&tlmm 0 0 114>; /* GPIOs + ufs_reset */ 597 #gpio-cells = <2>; 598 interrupt-controller; 599 #interrupt-cells = <2>; 600 601 qup_i2c0_default: qup-i2c0-default-state { 602 pins = "gpio0", "gpio1"; 603 function = "qup0"; 604 drive-strength = <2>; 605 bias-pull-up; 606 }; 607 608 qup_i2c1_default: qup-i2c1-default-state { 609 pins = "gpio4", "gpio5"; 610 function = "qup1"; 611 drive-strength = <2>; 612 bias-pull-up; 613 }; 614 615 qup_i2c2_default: qup-i2c2-default-state { 616 pins = "gpio6", "gpio7"; 617 function = "qup2"; 618 drive-strength = <2>; 619 bias-pull-up; 620 }; 621 622 qup_i2c3_default: qup-i2c3-default-state { 623 pins = "gpio8", "gpio9"; 624 function = "qup3"; 625 drive-strength = <2>; 626 bias-pull-up; 627 }; 628 629 qup_i2c4_default: qup-i2c4-default-state { 630 pins = "gpio12", "gpio13"; 631 function = "qup4"; 632 drive-strength = <2>; 633 bias-pull-up; 634 }; 635 636 qup_i2c5_default: qup-i2c5-default-state { 637 pins = "gpio14", "gpio15"; 638 function = "qup5"; 639 drive-strength = <2>; 640 bias-pull-up; 641 }; 642 643 qup_spi0_default: qup-spi0-default-state { 644 pins = "gpio0", "gpio1","gpio2", "gpio3"; 645 function = "qup0"; 646 drive-strength = <2>; 647 bias-pull-up; 648 }; 649 650 qup_spi1_default: qup-spi1-default-state { 651 pins = "gpio4", "gpio5", "gpio69", "gpio70"; 652 function = "qup1"; 653 drive-strength = <2>; 654 bias-pull-up; 655 }; 656 657 qup_spi2_default: qup-spi2-default-state { 658 pins = "gpio6", "gpio7", "gpio71", "gpio80"; 659 function = "qup2"; 660 drive-strength = <2>; 661 bias-pull-up; 662 }; 663 664 qup_spi3_default: qup-spi3-default-state { 665 pins = "gpio8", "gpio9", "gpio10", "gpio11"; 666 function = "qup3"; 667 drive-strength = <2>; 668 bias-pull-up; 669 }; 670 671 qup_spi4_default: qup-spi4-default-state { 672 pins = "gpio12", "gpio13", "gpio96", "gpio97"; 673 function = "qup4"; 674 drive-strength = <2>; 675 bias-pull-up; 676 }; 677 678 qup_spi5_default: qup-spi5-default-state { 679 pins = "gpio14", "gpio15", "gpio16", "gpio17"; 680 function = "qup5"; 681 drive-strength = <2>; 682 bias-pull-up; 683 }; 684 685 sdc1_state_on: sdc1-on-state { 686 clk-pins { 687 pins = "sdc1_clk"; 688 bias-disable; 689 drive-strength = <16>; 690 }; 691 692 cmd-pins { 693 pins = "sdc1_cmd"; 694 bias-pull-up; 695 drive-strength = <10>; 696 }; 697 698 data-pins { 699 pins = "sdc1_data"; 700 bias-pull-up; 701 drive-strength = <10>; 702 }; 703 704 rclk-pins { 705 pins = "sdc1_rclk"; 706 bias-pull-down; 707 }; 708 }; 709 710 sdc1_state_off: sdc1-off-state { 711 clk-pins { 712 pins = "sdc1_clk"; 713 bias-disable; 714 drive-strength = <2>; 715 }; 716 717 cmd-pins { 718 pins = "sdc1_cmd"; 719 bias-pull-up; 720 drive-strength = <2>; 721 }; 722 723 data-pins { 724 pins = "sdc1_data"; 725 bias-pull-up; 726 drive-strength = <2>; 727 }; 728 729 rclk-pins { 730 pins = "sdc1_rclk"; 731 bias-pull-down; 732 }; 733 }; 734 735 sdc2_state_on: sdc2-on-state { 736 clk-pins { 737 pins = "sdc2_clk"; 738 bias-disable; 739 drive-strength = <16>; 740 }; 741 742 cmd-pins { 743 pins = "sdc2_cmd"; 744 bias-pull-up; 745 drive-strength = <10>; 746 }; 747 748 data-pins { 749 pins = "sdc2_data"; 750 bias-pull-up; 751 drive-strength = <10>; 752 }; 753 }; 754 755 sdc2_state_off: sdc2-off-state { 756 clk-pins { 757 pins = "sdc2_clk"; 758 bias-disable; 759 drive-strength = <2>; 760 }; 761 762 cmd-pins { 763 pins = "sdc2_cmd"; 764 bias-pull-up; 765 drive-strength = <2>; 766 }; 767 768 data-pins { 769 pins = "sdc2_data"; 770 bias-pull-up; 771 drive-strength = <2>; 772 }; 773 }; 774 }; 775 776 gcc: clock-controller@1400000 { 777 compatible = "qcom,gcc-sm6115"; 778 reg = <0x0 0x01400000 0x0 0x1f0000>; 779 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>; 780 clock-names = "bi_tcxo", "sleep_clk"; 781 #clock-cells = <1>; 782 #reset-cells = <1>; 783 #power-domain-cells = <1>; 784 }; 785 786 usb_hsphy: phy@1613000 { 787 compatible = "qcom,sm6115-qusb2-phy"; 788 reg = <0x0 0x01613000 0x0 0x180>; 789 #phy-cells = <0>; 790 791 clocks = <&gcc GCC_AHB2PHY_USB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>; 792 clock-names = "cfg_ahb", "ref"; 793 794 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 795 nvmem-cells = <&qusb2_hstx_trim>; 796 797 status = "disabled"; 798 }; 799 800 cryptobam: dma-controller@1b04000 { 801 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 802 reg = <0x0 0x01b04000 0x0 0x24000>; 803 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>; 804 clocks = <&rpmcc RPM_SMD_CE1_CLK>; 805 clock-names = "bam_clk"; 806 #dma-cells = <1>; 807 qcom,ee = <0>; 808 qcom,controlled-remotely; 809 iommus = <&apps_smmu 0x92 0>, 810 <&apps_smmu 0x94 0x11>, 811 <&apps_smmu 0x96 0x11>, 812 <&apps_smmu 0x98 0x1>, 813 <&apps_smmu 0x9F 0>; 814 }; 815 816 crypto: crypto@1b3a000 { 817 compatible = "qcom,sm6115-qce", "qcom,ipq4019-qce", "qcom,qce"; 818 reg = <0x0 0x01b3a000 0x0 0x6000>; 819 clocks = <&rpmcc RPM_SMD_CE1_CLK>; 820 clock-names = "core"; 821 822 dmas = <&cryptobam 6>, <&cryptobam 7>; 823 dma-names = "rx", "tx"; 824 iommus = <&apps_smmu 0x92 0>, 825 <&apps_smmu 0x94 0x11>, 826 <&apps_smmu 0x96 0x11>, 827 <&apps_smmu 0x98 0x1>, 828 <&apps_smmu 0x9F 0>; 829 }; 830 831 usb_qmpphy: phy@1615000 { 832 compatible = "qcom,sm6115-qmp-usb3-phy"; 833 reg = <0x0 0x01615000 0x0 0x1000>; 834 835 clocks = <&gcc GCC_AHB2PHY_USB_CLK>, 836 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 837 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 838 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 839 clock-names = "cfg_ahb", 840 "ref", 841 "com_aux", 842 "pipe"; 843 844 resets = <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>, 845 <&gcc GCC_USB3PHY_PHY_PRIM_SP0_BCR>; 846 reset-names = "phy", "phy_phy"; 847 848 #clock-cells = <0>; 849 clock-output-names = "usb3_phy_pipe_clk_src"; 850 851 #phy-cells = <0>; 852 853 status = "disabled"; 854 }; 855 856 qfprom@1b40000 { 857 compatible = "qcom,sm6115-qfprom", "qcom,qfprom"; 858 reg = <0x0 0x01b40000 0x0 0x7000>; 859 #address-cells = <1>; 860 #size-cells = <1>; 861 862 qusb2_hstx_trim: hstx-trim@25b { 863 reg = <0x25b 0x1>; 864 bits = <1 4>; 865 }; 866 }; 867 868 rng: rng@1b53000 { 869 compatible = "qcom,prng-ee"; 870 reg = <0x0 0x01b53000 0x0 0x1000>; 871 clocks = <&gcc GCC_PRNG_AHB_CLK>; 872 clock-names = "core"; 873 }; 874 875 spmi_bus: spmi@1c40000 { 876 compatible = "qcom,spmi-pmic-arb"; 877 reg = <0x0 0x01c40000 0x0 0x1100>, 878 <0x0 0x01e00000 0x0 0x2000000>, 879 <0x0 0x03e00000 0x0 0x100000>, 880 <0x0 0x03f00000 0x0 0xa0000>, 881 <0x0 0x01c0a000 0x0 0x26000>; 882 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 883 interrupt-names = "periph_irq"; 884 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 885 qcom,ee = <0>; 886 qcom,channel = <0>; 887 #address-cells = <2>; 888 #size-cells = <0>; 889 interrupt-controller; 890 #interrupt-cells = <4>; 891 }; 892 893 tsens0: thermal-sensor@4411000 { 894 compatible = "qcom,sm6115-tsens", "qcom,tsens-v2"; 895 reg = <0x0 0x04411000 0x0 0x1ff>, /* TM */ 896 <0x0 0x04410000 0x0 0x8>; /* SROT */ 897 #qcom,sensors = <16>; 898 interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 899 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 900 interrupt-names = "uplow", "critical"; 901 #thermal-sensor-cells = <1>; 902 }; 903 904 rpm_msg_ram: sram@45f0000 { 905 compatible = "qcom,rpm-msg-ram"; 906 reg = <0x0 0x045f0000 0x0 0x7000>; 907 }; 908 909 sram@4690000 { 910 compatible = "qcom,rpm-stats"; 911 reg = <0x0 0x04690000 0x0 0x10000>; 912 }; 913 914 sdhc_1: mmc@4744000 { 915 compatible = "qcom,sm6115-sdhci", "qcom,sdhci-msm-v5"; 916 reg = <0x0 0x04744000 0x0 0x1000>, 917 <0x0 0x04745000 0x0 0x1000>, 918 <0x0 0x04748000 0x0 0x8000>; 919 reg-names = "hc", "cqhci", "ice"; 920 921 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, 922 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 923 interrupt-names = "hc_irq", "pwr_irq"; 924 925 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 926 <&gcc GCC_SDCC1_APPS_CLK>, 927 <&rpmcc RPM_SMD_XO_CLK_SRC>, 928 <&gcc GCC_SDCC1_ICE_CORE_CLK>; 929 clock-names = "iface", "core", "xo", "ice"; 930 931 bus-width = <8>; 932 status = "disabled"; 933 }; 934 935 sdhc_2: mmc@4784000 { 936 compatible = "qcom,sm6115-sdhci", "qcom,sdhci-msm-v5"; 937 reg = <0x0 0x04784000 0x0 0x1000>; 938 reg-names = "hc"; 939 940 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 941 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 942 interrupt-names = "hc_irq", "pwr_irq"; 943 944 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 945 <&gcc GCC_SDCC2_APPS_CLK>, 946 <&rpmcc RPM_SMD_XO_CLK_SRC>; 947 clock-names = "iface", "core", "xo"; 948 949 power-domains = <&rpmpd SM6115_VDDCX>; 950 operating-points-v2 = <&sdhc2_opp_table>; 951 iommus = <&apps_smmu 0x00a0 0x0>; 952 resets = <&gcc GCC_SDCC2_BCR>; 953 954 bus-width = <4>; 955 qcom,dll-config = <0x0007642c>; 956 qcom,ddr-config = <0x80040868>; 957 status = "disabled"; 958 959 sdhc2_opp_table: opp-table { 960 compatible = "operating-points-v2"; 961 962 opp-100000000 { 963 opp-hz = /bits/ 64 <100000000>; 964 required-opps = <&rpmpd_opp_low_svs>; 965 }; 966 967 opp-202000000 { 968 opp-hz = /bits/ 64 <202000000>; 969 required-opps = <&rpmpd_opp_nom>; 970 }; 971 }; 972 }; 973 974 ufs_mem_hc: ufs@4804000 { 975 compatible = "qcom,sm6115-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; 976 reg = <0x0 0x04804000 0x0 0x3000>, <0x0 0x04810000 0x0 0x8000>; 977 reg-names = "std", "ice"; 978 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 979 phys = <&ufs_mem_phy_lanes>; 980 phy-names = "ufsphy"; 981 lanes-per-direction = <1>; 982 #reset-cells = <1>; 983 resets = <&gcc GCC_UFS_PHY_BCR>; 984 reset-names = "rst"; 985 986 power-domains = <&gcc GCC_UFS_PHY_GDSC>; 987 iommus = <&apps_smmu 0x100 0>; 988 989 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 990 <&gcc GCC_SYS_NOC_UFS_PHY_AXI_CLK>, 991 <&gcc GCC_UFS_PHY_AHB_CLK>, 992 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 993 <&rpmcc RPM_SMD_XO_CLK_SRC>, 994 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 995 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 996 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 997 clock-names = "core_clk", 998 "bus_aggr_clk", 999 "iface_clk", 1000 "core_clk_unipro", 1001 "ref_clk", 1002 "tx_lane0_sync_clk", 1003 "rx_lane0_sync_clk", 1004 "ice_core_clk"; 1005 1006 freq-table-hz = <50000000 200000000>, 1007 <0 0>, 1008 <0 0>, 1009 <37500000 150000000>, 1010 <0 0>, 1011 <0 0>, 1012 <0 0>, 1013 <75000000 300000000>; 1014 1015 status = "disabled"; 1016 }; 1017 1018 ufs_mem_phy: phy@4807000 { 1019 compatible = "qcom,sm6115-qmp-ufs-phy"; 1020 reg = <0x0 0x04807000 0x0 0x1c4>; 1021 #address-cells = <2>; 1022 #size-cells = <2>; 1023 ranges; 1024 1025 clocks = <&gcc GCC_UFS_CLKREF_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 1026 clock-names = "ref", "ref_aux"; 1027 1028 resets = <&ufs_mem_hc 0>; 1029 reset-names = "ufsphy"; 1030 status = "disabled"; 1031 1032 ufs_mem_phy_lanes: phy@4807400 { 1033 reg = <0x0 0x04807400 0x0 0x098>, 1034 <0x0 0x04807600 0x0 0x130>, 1035 <0x0 0x04807c00 0x0 0x16c>; 1036 #phy-cells = <0>; 1037 }; 1038 }; 1039 1040 gpi_dma0: dma-controller@4a00000 { 1041 compatible = "qcom,sm6115-gpi-dma", "qcom,sm6350-gpi-dma"; 1042 reg = <0x0 0x04a00000 0x0 0x60000>; 1043 interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 1044 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 1045 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 1046 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 1047 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 1048 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 1049 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 1050 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 1051 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 1052 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; 1053 dma-channels = <10>; 1054 dma-channel-mask = <0xf>; 1055 iommus = <&apps_smmu 0xf6 0x0>; 1056 #dma-cells = <3>; 1057 status = "disabled"; 1058 }; 1059 1060 qupv3_id_0: geniqup@4ac0000 { 1061 compatible = "qcom,geni-se-qup"; 1062 reg = <0x0 0x04ac0000 0x0 0x2000>; 1063 clock-names = "m-ahb", "s-ahb"; 1064 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1065 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1066 #address-cells = <2>; 1067 #size-cells = <2>; 1068 iommus = <&apps_smmu 0xe3 0x0>; 1069 ranges; 1070 status = "disabled"; 1071 1072 i2c0: i2c@4a80000 { 1073 compatible = "qcom,geni-i2c"; 1074 reg = <0x0 0x04a80000 0x0 0x4000>; 1075 clock-names = "se"; 1076 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1077 pinctrl-names = "default"; 1078 pinctrl-0 = <&qup_i2c0_default>; 1079 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 1080 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1081 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1082 dma-names = "tx", "rx"; 1083 #address-cells = <1>; 1084 #size-cells = <0>; 1085 status = "disabled"; 1086 }; 1087 1088 spi0: spi@4a80000 { 1089 compatible = "qcom,geni-spi"; 1090 reg = <0x0 0x04a80000 0x0 0x4000>; 1091 clock-names = "se"; 1092 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1093 pinctrl-names = "default"; 1094 pinctrl-0 = <&qup_spi0_default>; 1095 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 1096 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1097 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1098 dma-names = "tx", "rx"; 1099 #address-cells = <1>; 1100 #size-cells = <0>; 1101 status = "disabled"; 1102 }; 1103 1104 i2c1: i2c@4a84000 { 1105 compatible = "qcom,geni-i2c"; 1106 reg = <0x0 0x04a84000 0x0 0x4000>; 1107 clock-names = "se"; 1108 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1109 pinctrl-names = "default"; 1110 pinctrl-0 = <&qup_i2c1_default>; 1111 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 1112 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1113 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1114 dma-names = "tx", "rx"; 1115 #address-cells = <1>; 1116 #size-cells = <0>; 1117 status = "disabled"; 1118 }; 1119 1120 spi1: spi@4a84000 { 1121 compatible = "qcom,geni-spi"; 1122 reg = <0x0 0x04a84000 0x0 0x4000>; 1123 clock-names = "se"; 1124 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1125 pinctrl-names = "default"; 1126 pinctrl-0 = <&qup_spi1_default>; 1127 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 1128 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1129 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1130 dma-names = "tx", "rx"; 1131 #address-cells = <1>; 1132 #size-cells = <0>; 1133 status = "disabled"; 1134 }; 1135 1136 i2c2: i2c@4a88000 { 1137 compatible = "qcom,geni-i2c"; 1138 reg = <0x0 0x04a88000 0x0 0x4000>; 1139 clock-names = "se"; 1140 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1141 pinctrl-names = "default"; 1142 pinctrl-0 = <&qup_i2c2_default>; 1143 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; 1144 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1145 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1146 dma-names = "tx", "rx"; 1147 #address-cells = <1>; 1148 #size-cells = <0>; 1149 status = "disabled"; 1150 }; 1151 1152 spi2: spi@4a88000 { 1153 compatible = "qcom,geni-spi"; 1154 reg = <0x0 0x04a88000 0x0 0x4000>; 1155 clock-names = "se"; 1156 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1157 pinctrl-names = "default"; 1158 pinctrl-0 = <&qup_spi2_default>; 1159 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; 1160 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1161 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1162 dma-names = "tx", "rx"; 1163 #address-cells = <1>; 1164 #size-cells = <0>; 1165 status = "disabled"; 1166 }; 1167 1168 i2c3: i2c@4a8c000 { 1169 compatible = "qcom,geni-i2c"; 1170 reg = <0x0 0x04a8c000 0x0 0x4000>; 1171 clock-names = "se"; 1172 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1173 pinctrl-names = "default"; 1174 pinctrl-0 = <&qup_i2c3_default>; 1175 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 1176 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1177 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1178 dma-names = "tx", "rx"; 1179 #address-cells = <1>; 1180 #size-cells = <0>; 1181 status = "disabled"; 1182 }; 1183 1184 spi3: spi@4a8c000 { 1185 compatible = "qcom,geni-spi"; 1186 reg = <0x0 0x04a8c000 0x0 0x4000>; 1187 clock-names = "se"; 1188 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1189 pinctrl-names = "default"; 1190 pinctrl-0 = <&qup_spi3_default>; 1191 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 1192 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1193 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1194 dma-names = "tx", "rx"; 1195 #address-cells = <1>; 1196 #size-cells = <0>; 1197 status = "disabled"; 1198 }; 1199 1200 i2c4: i2c@4a90000 { 1201 compatible = "qcom,geni-i2c"; 1202 reg = <0x0 0x04a90000 0x0 0x4000>; 1203 clock-names = "se"; 1204 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1205 pinctrl-names = "default"; 1206 pinctrl-0 = <&qup_i2c4_default>; 1207 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 1208 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1209 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1210 dma-names = "tx", "rx"; 1211 #address-cells = <1>; 1212 #size-cells = <0>; 1213 status = "disabled"; 1214 }; 1215 1216 spi4: spi@4a90000 { 1217 compatible = "qcom,geni-spi"; 1218 reg = <0x0 0x04a90000 0x0 0x4000>; 1219 clock-names = "se"; 1220 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1221 pinctrl-names = "default"; 1222 pinctrl-0 = <&qup_spi4_default>; 1223 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 1224 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1225 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1226 dma-names = "tx", "rx"; 1227 #address-cells = <1>; 1228 #size-cells = <0>; 1229 status = "disabled"; 1230 }; 1231 1232 uart4: serial@4a90000 { 1233 compatible = "qcom,geni-debug-uart"; 1234 reg = <0x0 0x04a90000 0x0 0x4000>; 1235 clock-names = "se"; 1236 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1237 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 1238 status = "disabled"; 1239 }; 1240 1241 i2c5: i2c@4a94000 { 1242 compatible = "qcom,geni-i2c"; 1243 reg = <0x0 0x04a94000 0x0 0x4000>; 1244 clock-names = "se"; 1245 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1246 pinctrl-names = "default"; 1247 pinctrl-0 = <&qup_i2c5_default>; 1248 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; 1249 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1250 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1251 dma-names = "tx", "rx"; 1252 #address-cells = <1>; 1253 #size-cells = <0>; 1254 status = "disabled"; 1255 }; 1256 1257 spi5: spi@4a94000 { 1258 compatible = "qcom,geni-spi"; 1259 reg = <0x0 0x04a94000 0x0 0x4000>; 1260 clock-names = "se"; 1261 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1262 pinctrl-names = "default"; 1263 pinctrl-0 = <&qup_spi5_default>; 1264 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; 1265 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1266 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1267 dma-names = "tx", "rx"; 1268 #address-cells = <1>; 1269 #size-cells = <0>; 1270 status = "disabled"; 1271 }; 1272 }; 1273 1274 usb: usb@4ef8800 { 1275 compatible = "qcom,sm6115-dwc3", "qcom,dwc3"; 1276 reg = <0x0 0x04ef8800 0x0 0x400>; 1277 #address-cells = <2>; 1278 #size-cells = <2>; 1279 ranges; 1280 1281 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 1282 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 1283 <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>, 1284 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 1285 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1286 <&gcc GCC_USB3_PRIM_CLKREF_CLK>; 1287 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", "xo"; 1288 1289 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1290 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 1291 assigned-clock-rates = <19200000>, <66666667>; 1292 1293 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 1294 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>; 1295 interrupt-names = "hs_phy_irq", "ss_phy_irq"; 1296 1297 resets = <&gcc GCC_USB30_PRIM_BCR>; 1298 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 1299 qcom,select-utmi-as-pipe-clk; 1300 status = "disabled"; 1301 1302 usb_dwc3: usb@4e00000 { 1303 compatible = "snps,dwc3"; 1304 reg = <0x0 0x04e00000 0x0 0xcd00>; 1305 interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 1306 phys = <&usb_hsphy>, <&usb_qmpphy>; 1307 phy-names = "usb2-phy", "usb3-phy"; 1308 iommus = <&apps_smmu 0x120 0x0>; 1309 snps,dis_u2_susphy_quirk; 1310 snps,dis_enblslpm_quirk; 1311 snps,has-lpm-erratum; 1312 snps,hird-threshold = /bits/ 8 <0x10>; 1313 snps,usb3_lpm_capable; 1314 }; 1315 }; 1316 1317 gpucc: clock-controller@5990000 { 1318 compatible = "qcom,sm6115-gpucc"; 1319 reg = <0x0 0x05990000 0x0 0x9000>; 1320 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 1321 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 1322 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 1323 #clock-cells = <1>; 1324 #reset-cells = <1>; 1325 #power-domain-cells = <1>; 1326 }; 1327 1328 adreno_smmu: iommu@59a0000 { 1329 compatible = "qcom,sm6115-smmu-500", "qcom,adreno-smmu", 1330 "qcom,smmu-500", "arm,mmu-500"; 1331 reg = <0x0 0x059a0000 0x0 0x10000>; 1332 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 1333 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 1334 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 1335 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 1336 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1337 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 1338 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, 1339 <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, 1340 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1341 1342 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1343 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 1344 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 1345 clock-names = "mem", 1346 "hlos", 1347 "iface"; 1348 power-domains = <&gpucc GPU_CX_GDSC>; 1349 1350 #global-interrupts = <1>; 1351 #iommu-cells = <2>; 1352 }; 1353 1354 mdss: display-subsystem@5e00000 { 1355 compatible = "qcom,sm6115-mdss"; 1356 reg = <0x0 0x05e00000 0x0 0x1000>; 1357 reg-names = "mdss"; 1358 1359 power-domains = <&dispcc MDSS_GDSC>; 1360 1361 clocks = <&gcc GCC_DISP_AHB_CLK>, 1362 <&gcc GCC_DISP_HF_AXI_CLK>, 1363 <&dispcc DISP_CC_MDSS_MDP_CLK>; 1364 1365 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 1366 interrupt-controller; 1367 #interrupt-cells = <1>; 1368 1369 iommus = <&apps_smmu 0x420 0x2>, 1370 <&apps_smmu 0x421 0x0>; 1371 1372 #address-cells = <2>; 1373 #size-cells = <2>; 1374 ranges; 1375 1376 status = "disabled"; 1377 1378 mdp: display-controller@5e01000 { 1379 compatible = "qcom,sm6115-dpu"; 1380 reg = <0x0 0x05e01000 0x0 0x8f000>, 1381 <0x0 0x05eb0000 0x0 0x2008>; 1382 reg-names = "mdp", "vbif"; 1383 1384 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 1385 <&dispcc DISP_CC_MDSS_AHB_CLK>, 1386 <&dispcc DISP_CC_MDSS_MDP_CLK>, 1387 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 1388 <&dispcc DISP_CC_MDSS_ROT_CLK>, 1389 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 1390 clock-names = "bus", 1391 "iface", 1392 "core", 1393 "lut", 1394 "rot", 1395 "vsync"; 1396 1397 operating-points-v2 = <&mdp_opp_table>; 1398 power-domains = <&rpmpd SM6115_VDDCX>; 1399 1400 interrupt-parent = <&mdss>; 1401 interrupts = <0>; 1402 1403 ports { 1404 #address-cells = <1>; 1405 #size-cells = <0>; 1406 1407 port@0 { 1408 reg = <0>; 1409 dpu_intf1_out: endpoint { 1410 remote-endpoint = <&mdss_dsi0_in>; 1411 }; 1412 }; 1413 }; 1414 1415 mdp_opp_table: opp-table { 1416 compatible = "operating-points-v2"; 1417 1418 opp-19200000 { 1419 opp-hz = /bits/ 64 <19200000>; 1420 required-opps = <&rpmpd_opp_min_svs>; 1421 }; 1422 1423 opp-192000000 { 1424 opp-hz = /bits/ 64 <192000000>; 1425 required-opps = <&rpmpd_opp_low_svs>; 1426 }; 1427 1428 opp-256000000 { 1429 opp-hz = /bits/ 64 <256000000>; 1430 required-opps = <&rpmpd_opp_svs>; 1431 }; 1432 1433 opp-307200000 { 1434 opp-hz = /bits/ 64 <307200000>; 1435 required-opps = <&rpmpd_opp_svs_plus>; 1436 }; 1437 1438 opp-384000000 { 1439 opp-hz = /bits/ 64 <384000000>; 1440 required-opps = <&rpmpd_opp_nom>; 1441 }; 1442 }; 1443 }; 1444 1445 mdss_dsi0: dsi@5e94000 { 1446 compatible = "qcom,sm6115-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 1447 reg = <0x0 0x05e94000 0x0 0x400>; 1448 reg-names = "dsi_ctrl"; 1449 1450 interrupt-parent = <&mdss>; 1451 interrupts = <4>; 1452 1453 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 1454 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 1455 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 1456 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 1457 <&dispcc DISP_CC_MDSS_AHB_CLK>, 1458 <&gcc GCC_DISP_HF_AXI_CLK>; 1459 clock-names = "byte", 1460 "byte_intf", 1461 "pixel", 1462 "core", 1463 "iface", 1464 "bus"; 1465 1466 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 1467 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 1468 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; 1469 1470 operating-points-v2 = <&dsi_opp_table>; 1471 power-domains = <&rpmpd SM6115_VDDCX>; 1472 phys = <&mdss_dsi0_phy>; 1473 1474 #address-cells = <1>; 1475 #size-cells = <0>; 1476 1477 status = "disabled"; 1478 1479 ports { 1480 #address-cells = <1>; 1481 #size-cells = <0>; 1482 1483 port@0 { 1484 reg = <0>; 1485 mdss_dsi0_in: endpoint { 1486 remote-endpoint = <&dpu_intf1_out>; 1487 }; 1488 }; 1489 1490 port@1 { 1491 reg = <1>; 1492 mdss_dsi0_out: endpoint { 1493 }; 1494 }; 1495 }; 1496 1497 dsi_opp_table: opp-table { 1498 compatible = "operating-points-v2"; 1499 1500 opp-19200000 { 1501 opp-hz = /bits/ 64 <19200000>; 1502 required-opps = <&rpmpd_opp_min_svs>; 1503 }; 1504 1505 opp-164000000 { 1506 opp-hz = /bits/ 64 <164000000>; 1507 required-opps = <&rpmpd_opp_low_svs>; 1508 }; 1509 1510 opp-187500000 { 1511 opp-hz = /bits/ 64 <187500000>; 1512 required-opps = <&rpmpd_opp_svs>; 1513 }; 1514 }; 1515 }; 1516 1517 mdss_dsi0_phy: phy@5e94400 { 1518 compatible = "qcom,dsi-phy-14nm-2290"; 1519 reg = <0x0 0x05e94400 0x0 0x100>, 1520 <0x0 0x05e94500 0x0 0x300>, 1521 <0x0 0x05e94800 0x0 0x188>; 1522 reg-names = "dsi_phy", 1523 "dsi_phy_lane", 1524 "dsi_pll"; 1525 1526 #clock-cells = <1>; 1527 #phy-cells = <0>; 1528 1529 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 1530 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1531 clock-names = "iface", "ref"; 1532 1533 status = "disabled"; 1534 }; 1535 }; 1536 1537 dispcc: clock-controller@5f00000 { 1538 compatible = "qcom,sm6115-dispcc"; 1539 reg = <0x0 0x05f00000 0 0x20000>; 1540 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 1541 <&sleep_clk>, 1542 <&mdss_dsi0_phy 0>, 1543 <&mdss_dsi0_phy 1>, 1544 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>; 1545 #clock-cells = <1>; 1546 #reset-cells = <1>; 1547 #power-domain-cells = <1>; 1548 }; 1549 1550 remoteproc_mpss: remoteproc@6080000 { 1551 compatible = "qcom,sm6115-mpss-pas"; 1552 reg = <0x0 0x06080000 0x0 0x100>; 1553 1554 interrupts-extended = <&intc GIC_SPI 307 IRQ_TYPE_EDGE_RISING>, 1555 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1556 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1557 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1558 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 1559 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 1560 interrupt-names = "wdog", "fatal", "ready", "handover", 1561 "stop-ack", "shutdown-ack"; 1562 1563 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 1564 clock-names = "xo"; 1565 1566 power-domains = <&rpmpd SM6115_VDDCX>; 1567 1568 memory-region = <&pil_modem_mem>; 1569 1570 qcom,smem-states = <&modem_smp2p_out 0>; 1571 qcom,smem-state-names = "stop"; 1572 1573 status = "disabled"; 1574 1575 glink-edge { 1576 interrupts = <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>; 1577 label = "mpss"; 1578 qcom,remote-pid = <1>; 1579 mboxes = <&apcs_glb 12>; 1580 }; 1581 }; 1582 1583 stm@8002000 { 1584 compatible = "arm,coresight-stm", "arm,primecell"; 1585 reg = <0x0 0x08002000 0x0 0x1000>, 1586 <0x0 0x0e280000 0x0 0x180000>; 1587 reg-names = "stm-base", "stm-stimulus-base"; 1588 1589 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1590 clock-names = "apb_pclk"; 1591 1592 status = "disabled"; 1593 1594 out-ports { 1595 port { 1596 stm_out: endpoint { 1597 remote-endpoint = <&funnel_in0_in>; 1598 }; 1599 }; 1600 }; 1601 }; 1602 1603 cti0: cti@8010000 { 1604 compatible = "arm,coresight-cti", "arm,primecell"; 1605 reg = <0x0 0x08010000 0x0 0x1000>; 1606 1607 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1608 clock-names = "apb_pclk"; 1609 1610 status = "disabled"; 1611 }; 1612 1613 cti1: cti@8011000 { 1614 compatible = "arm,coresight-cti", "arm,primecell"; 1615 reg = <0x0 0x08011000 0x0 0x1000>; 1616 1617 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1618 clock-names = "apb_pclk"; 1619 1620 status = "disabled"; 1621 }; 1622 1623 cti2: cti@8012000 { 1624 compatible = "arm,coresight-cti", "arm,primecell"; 1625 reg = <0x0 0x08012000 0x0 0x1000>; 1626 1627 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1628 clock-names = "apb_pclk"; 1629 1630 status = "disabled"; 1631 }; 1632 1633 cti3: cti@8013000 { 1634 compatible = "arm,coresight-cti", "arm,primecell"; 1635 reg = <0x0 0x08013000 0x0 0x1000>; 1636 1637 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1638 clock-names = "apb_pclk"; 1639 1640 status = "disabled"; 1641 }; 1642 1643 cti4: cti@8014000 { 1644 compatible = "arm,coresight-cti", "arm,primecell"; 1645 reg = <0x0 0x08014000 0x0 0x1000>; 1646 1647 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1648 clock-names = "apb_pclk"; 1649 1650 status = "disabled"; 1651 }; 1652 1653 cti5: cti@8015000 { 1654 compatible = "arm,coresight-cti", "arm,primecell"; 1655 reg = <0x0 0x08015000 0x0 0x1000>; 1656 1657 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1658 clock-names = "apb_pclk"; 1659 1660 status = "disabled"; 1661 }; 1662 1663 cti6: cti@8016000 { 1664 compatible = "arm,coresight-cti", "arm,primecell"; 1665 reg = <0x0 0x08016000 0x0 0x1000>; 1666 1667 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1668 clock-names = "apb_pclk"; 1669 1670 status = "disabled"; 1671 }; 1672 1673 cti7: cti@8017000 { 1674 compatible = "arm,coresight-cti", "arm,primecell"; 1675 reg = <0x0 0x08017000 0x0 0x1000>; 1676 1677 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1678 clock-names = "apb_pclk"; 1679 1680 status = "disabled"; 1681 }; 1682 1683 cti8: cti@8018000 { 1684 compatible = "arm,coresight-cti", "arm,primecell"; 1685 reg = <0x0 0x08018000 0x0 0x1000>; 1686 1687 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1688 clock-names = "apb_pclk"; 1689 1690 status = "disabled"; 1691 }; 1692 1693 cti9: cti@8019000 { 1694 compatible = "arm,coresight-cti", "arm,primecell"; 1695 reg = <0x0 0x08019000 0x0 0x1000>; 1696 1697 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1698 clock-names = "apb_pclk"; 1699 1700 status = "disabled"; 1701 }; 1702 1703 cti10: cti@801a000 { 1704 compatible = "arm,coresight-cti", "arm,primecell"; 1705 reg = <0x0 0x0801a000 0x0 0x1000>; 1706 1707 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1708 clock-names = "apb_pclk"; 1709 1710 status = "disabled"; 1711 }; 1712 1713 cti11: cti@801b000 { 1714 compatible = "arm,coresight-cti", "arm,primecell"; 1715 reg = <0x0 0x0801b000 0x0 0x1000>; 1716 1717 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1718 clock-names = "apb_pclk"; 1719 1720 status = "disabled"; 1721 }; 1722 1723 cti12: cti@801c000 { 1724 compatible = "arm,coresight-cti", "arm,primecell"; 1725 reg = <0x0 0x0801c000 0x0 0x1000>; 1726 1727 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1728 clock-names = "apb_pclk"; 1729 1730 status = "disabled"; 1731 }; 1732 1733 cti13: cti@801d000 { 1734 compatible = "arm,coresight-cti", "arm,primecell"; 1735 reg = <0x0 0x0801d000 0x0 0x1000>; 1736 1737 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1738 clock-names = "apb_pclk"; 1739 1740 status = "disabled"; 1741 }; 1742 1743 cti14: cti@801e000 { 1744 compatible = "arm,coresight-cti", "arm,primecell"; 1745 reg = <0x0 0x0801e000 0x0 0x1000>; 1746 1747 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1748 clock-names = "apb_pclk"; 1749 1750 status = "disabled"; 1751 }; 1752 1753 cti15: cti@801f000 { 1754 compatible = "arm,coresight-cti", "arm,primecell"; 1755 reg = <0x0 0x0801f000 0x0 0x1000>; 1756 1757 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1758 clock-names = "apb_pclk"; 1759 1760 status = "disabled"; 1761 }; 1762 1763 replicator@8046000 { 1764 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 1765 reg = <0x0 0x08046000 0x0 0x1000>; 1766 1767 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1768 clock-names = "apb_pclk"; 1769 1770 status = "disabled"; 1771 1772 out-ports { 1773 port { 1774 replicator_out: endpoint { 1775 remote-endpoint = <&etr_in>; 1776 }; 1777 }; 1778 }; 1779 1780 in-ports { 1781 port { 1782 replicator_in: endpoint { 1783 remote-endpoint = <&etf_out>; 1784 }; 1785 }; 1786 }; 1787 }; 1788 1789 etf@8047000 { 1790 compatible = "arm,coresight-tmc", "arm,primecell"; 1791 reg = <0x0 0x08047000 0x0 0x1000>; 1792 1793 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1794 clock-names = "apb_pclk"; 1795 1796 status = "disabled"; 1797 1798 in-ports { 1799 port { 1800 etf_in: endpoint { 1801 remote-endpoint = <&merge_funnel_out>; 1802 }; 1803 }; 1804 }; 1805 1806 out-ports { 1807 port { 1808 etf_out: endpoint { 1809 remote-endpoint = <&replicator_in>; 1810 }; 1811 }; 1812 }; 1813 }; 1814 1815 etr@8048000 { 1816 compatible = "arm,coresight-tmc", "arm,primecell"; 1817 reg = <0x0 0x08048000 0x0 0x1000>; 1818 1819 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1820 clock-names = "apb_pclk"; 1821 1822 status = "disabled"; 1823 1824 in-ports { 1825 port { 1826 etr_in: endpoint { 1827 remote-endpoint = <&replicator_out>; 1828 }; 1829 }; 1830 }; 1831 }; 1832 1833 funnel@8041000 { 1834 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1835 reg = <0x0 0x08041000 0x0 0x1000>; 1836 1837 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1838 clock-names = "apb_pclk"; 1839 1840 status = "disabled"; 1841 1842 out-ports { 1843 port { 1844 funnel_in0_out: endpoint { 1845 remote-endpoint = <&merge_funnel_in0>; 1846 }; 1847 }; 1848 }; 1849 1850 in-ports { 1851 port { 1852 funnel_in0_in: endpoint { 1853 remote-endpoint = <&stm_out>; 1854 }; 1855 }; 1856 }; 1857 }; 1858 1859 funnel@8042000 { 1860 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1861 reg = <0x0 0x08042000 0x0 0x1000>; 1862 1863 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1864 clock-names = "apb_pclk"; 1865 1866 status = "disabled"; 1867 1868 out-ports { 1869 port { 1870 funnel_in1_out: endpoint { 1871 remote-endpoint = <&merge_funnel_in1>; 1872 }; 1873 }; 1874 }; 1875 1876 in-ports { 1877 port { 1878 funnel_in1_in: endpoint { 1879 remote-endpoint = <&funnel_apss1_out>; 1880 }; 1881 }; 1882 }; 1883 }; 1884 1885 funnel@8045000 { 1886 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1887 reg = <0x0 0x08045000 0x0 0x1000>; 1888 1889 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1890 clock-names = "apb_pclk"; 1891 1892 status = "disabled"; 1893 1894 out-ports { 1895 port { 1896 merge_funnel_out: endpoint { 1897 remote-endpoint = <&etf_in>; 1898 }; 1899 }; 1900 }; 1901 1902 in-ports { 1903 #address-cells = <1>; 1904 #size-cells = <0>; 1905 1906 port@0 { 1907 reg = <0>; 1908 merge_funnel_in0: endpoint { 1909 remote-endpoint = <&funnel_in0_out>; 1910 }; 1911 }; 1912 1913 port@1 { 1914 reg = <1>; 1915 merge_funnel_in1: endpoint { 1916 remote-endpoint = <&funnel_in1_out>; 1917 }; 1918 }; 1919 }; 1920 }; 1921 1922 etm@9040000 { 1923 compatible = "arm,coresight-etm4x", "arm,primecell"; 1924 reg = <0x0 0x09040000 0x0 0x1000>; 1925 1926 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1927 clock-names = "apb_pclk"; 1928 arm,coresight-loses-context-with-cpu; 1929 1930 cpu = <&CPU0>; 1931 1932 status = "disabled"; 1933 1934 out-ports { 1935 port { 1936 etm0_out: endpoint { 1937 remote-endpoint = <&funnel_apss0_in0>; 1938 }; 1939 }; 1940 }; 1941 }; 1942 1943 etm@9140000 { 1944 compatible = "arm,coresight-etm4x", "arm,primecell"; 1945 reg = <0x0 0x09140000 0x0 0x1000>; 1946 1947 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1948 clock-names = "apb_pclk"; 1949 arm,coresight-loses-context-with-cpu; 1950 1951 cpu = <&CPU1>; 1952 1953 status = "disabled"; 1954 1955 out-ports { 1956 port { 1957 etm1_out: endpoint { 1958 remote-endpoint = <&funnel_apss0_in1>; 1959 }; 1960 }; 1961 }; 1962 }; 1963 1964 etm@9240000 { 1965 compatible = "arm,coresight-etm4x", "arm,primecell"; 1966 reg = <0x0 0x09240000 0x0 0x1000>; 1967 1968 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1969 clock-names = "apb_pclk"; 1970 arm,coresight-loses-context-with-cpu; 1971 1972 cpu = <&CPU2>; 1973 1974 status = "disabled"; 1975 1976 out-ports { 1977 port { 1978 etm2_out: endpoint { 1979 remote-endpoint = <&funnel_apss0_in2>; 1980 }; 1981 }; 1982 }; 1983 }; 1984 1985 etm@9340000 { 1986 compatible = "arm,coresight-etm4x", "arm,primecell"; 1987 reg = <0x0 0x09340000 0x0 0x1000>; 1988 1989 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1990 clock-names = "apb_pclk"; 1991 arm,coresight-loses-context-with-cpu; 1992 1993 cpu = <&CPU3>; 1994 1995 status = "disabled"; 1996 1997 out-ports { 1998 port { 1999 etm3_out: endpoint { 2000 remote-endpoint = <&funnel_apss0_in3>; 2001 }; 2002 }; 2003 }; 2004 }; 2005 2006 etm@9440000 { 2007 compatible = "arm,coresight-etm4x", "arm,primecell"; 2008 reg = <0x0 0x09440000 0x0 0x1000>; 2009 2010 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2011 clock-names = "apb_pclk"; 2012 arm,coresight-loses-context-with-cpu; 2013 2014 cpu = <&CPU4>; 2015 2016 status = "disabled"; 2017 2018 out-ports { 2019 port { 2020 etm4_out: endpoint { 2021 remote-endpoint = <&funnel_apss0_in4>; 2022 }; 2023 }; 2024 }; 2025 }; 2026 2027 etm@9540000 { 2028 compatible = "arm,coresight-etm4x", "arm,primecell"; 2029 reg = <0x0 0x09540000 0x0 0x1000>; 2030 2031 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2032 clock-names = "apb_pclk"; 2033 arm,coresight-loses-context-with-cpu; 2034 2035 cpu = <&CPU5>; 2036 2037 status = "disabled"; 2038 2039 out-ports { 2040 port { 2041 etm5_out: endpoint { 2042 remote-endpoint = <&funnel_apss0_in5>; 2043 }; 2044 }; 2045 }; 2046 }; 2047 2048 etm@9640000 { 2049 compatible = "arm,coresight-etm4x", "arm,primecell"; 2050 reg = <0x0 0x09640000 0x0 0x1000>; 2051 2052 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2053 clock-names = "apb_pclk"; 2054 arm,coresight-loses-context-with-cpu; 2055 2056 cpu = <&CPU6>; 2057 2058 status = "disabled"; 2059 2060 out-ports { 2061 port { 2062 etm6_out: endpoint { 2063 remote-endpoint = <&funnel_apss0_in6>; 2064 }; 2065 }; 2066 }; 2067 }; 2068 2069 etm@9740000 { 2070 compatible = "arm,coresight-etm4x", "arm,primecell"; 2071 reg = <0x0 0x09740000 0x0 0x1000>; 2072 2073 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2074 clock-names = "apb_pclk"; 2075 arm,coresight-loses-context-with-cpu; 2076 2077 cpu = <&CPU7>; 2078 2079 status = "disabled"; 2080 2081 out-ports { 2082 port { 2083 etm7_out: endpoint { 2084 remote-endpoint = <&funnel_apss0_in7>; 2085 }; 2086 }; 2087 }; 2088 }; 2089 2090 funnel@9800000 { 2091 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2092 reg = <0x0 0x09800000 0x0 0x1000>; 2093 2094 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2095 clock-names = "apb_pclk"; 2096 2097 status = "disabled"; 2098 2099 out-ports { 2100 port { 2101 funnel_apss0_out: endpoint { 2102 remote-endpoint = <&funnel_apss1_in>; 2103 }; 2104 }; 2105 }; 2106 2107 in-ports { 2108 #address-cells = <1>; 2109 #size-cells = <0>; 2110 2111 port@0 { 2112 reg = <0>; 2113 funnel_apss0_in0: endpoint { 2114 remote-endpoint = <&etm0_out>; 2115 }; 2116 }; 2117 2118 port@1 { 2119 reg = <1>; 2120 funnel_apss0_in1: endpoint { 2121 remote-endpoint = <&etm1_out>; 2122 }; 2123 }; 2124 2125 port@2 { 2126 reg = <2>; 2127 funnel_apss0_in2: endpoint { 2128 remote-endpoint = <&etm2_out>; 2129 }; 2130 }; 2131 2132 port@3 { 2133 reg = <3>; 2134 funnel_apss0_in3: endpoint { 2135 remote-endpoint = <&etm3_out>; 2136 }; 2137 }; 2138 2139 port@4 { 2140 reg = <4>; 2141 funnel_apss0_in4: endpoint { 2142 remote-endpoint = <&etm4_out>; 2143 }; 2144 }; 2145 2146 port@5 { 2147 reg = <5>; 2148 funnel_apss0_in5: endpoint { 2149 remote-endpoint = <&etm5_out>; 2150 }; 2151 }; 2152 2153 port@6 { 2154 reg = <6>; 2155 funnel_apss0_in6: endpoint { 2156 remote-endpoint = <&etm6_out>; 2157 }; 2158 }; 2159 2160 port@7 { 2161 reg = <7>; 2162 funnel_apss0_in7: endpoint { 2163 remote-endpoint = <&etm7_out>; 2164 }; 2165 }; 2166 }; 2167 }; 2168 2169 funnel@9810000 { 2170 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2171 reg = <0x0 0x09810000 0x0 0x1000>; 2172 2173 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2174 clock-names = "apb_pclk"; 2175 2176 status = "disabled"; 2177 2178 out-ports { 2179 port { 2180 funnel_apss1_out: endpoint { 2181 remote-endpoint = <&funnel_in1_in>; 2182 }; 2183 }; 2184 }; 2185 2186 in-ports { 2187 port { 2188 funnel_apss1_in: endpoint { 2189 remote-endpoint = <&funnel_apss0_out>; 2190 }; 2191 }; 2192 }; 2193 }; 2194 2195 remoteproc_adsp: remoteproc@ab00000 { 2196 compatible = "qcom,sm6115-adsp-pas"; 2197 reg = <0x0 0x0ab00000 0x0 0x100>; 2198 2199 interrupts-extended = <&intc GIC_SPI 282 IRQ_TYPE_EDGE_RISING>, 2200 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2201 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2202 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2203 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2204 interrupt-names = "wdog", "fatal", "ready", 2205 "handover", "stop-ack"; 2206 2207 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 2208 clock-names = "xo"; 2209 2210 power-domains = <&rpmpd SM6115_VDD_LPI_CX>, 2211 <&rpmpd SM6115_VDD_LPI_MX>; 2212 2213 memory-region = <&pil_adsp_mem>; 2214 2215 qcom,smem-states = <&adsp_smp2p_out 0>; 2216 qcom,smem-state-names = "stop"; 2217 2218 status = "disabled"; 2219 2220 glink-edge { 2221 interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>; 2222 label = "lpass"; 2223 qcom,remote-pid = <2>; 2224 mboxes = <&apcs_glb 8>; 2225 2226 fastrpc { 2227 compatible = "qcom,fastrpc"; 2228 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2229 label = "adsp"; 2230 qcom,non-secure-domain; 2231 #address-cells = <1>; 2232 #size-cells = <0>; 2233 2234 compute-cb@3 { 2235 compatible = "qcom,fastrpc-compute-cb"; 2236 reg = <3>; 2237 iommus = <&apps_smmu 0x01c3 0x0>; 2238 }; 2239 2240 compute-cb@4 { 2241 compatible = "qcom,fastrpc-compute-cb"; 2242 reg = <4>; 2243 iommus = <&apps_smmu 0x01c4 0x0>; 2244 }; 2245 2246 compute-cb@5 { 2247 compatible = "qcom,fastrpc-compute-cb"; 2248 reg = <5>; 2249 iommus = <&apps_smmu 0x01c5 0x0>; 2250 }; 2251 2252 compute-cb@6 { 2253 compatible = "qcom,fastrpc-compute-cb"; 2254 reg = <6>; 2255 iommus = <&apps_smmu 0x01c6 0x0>; 2256 }; 2257 2258 compute-cb@7 { 2259 compatible = "qcom,fastrpc-compute-cb"; 2260 reg = <7>; 2261 iommus = <&apps_smmu 0x01c7 0x0>; 2262 }; 2263 }; 2264 }; 2265 }; 2266 2267 remoteproc_cdsp: remoteproc@b300000 { 2268 compatible = "qcom,sm6115-cdsp-pas"; 2269 reg = <0x0 0x0b300000 0x0 0x100000>; 2270 2271 interrupts-extended = <&intc GIC_SPI 265 IRQ_TYPE_EDGE_RISING>, 2272 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2273 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2274 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2275 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2276 interrupt-names = "wdog", "fatal", "ready", 2277 "handover", "stop-ack"; 2278 2279 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 2280 clock-names = "xo"; 2281 2282 power-domains = <&rpmpd SM6115_VDDCX>; 2283 2284 memory-region = <&pil_cdsp_mem>; 2285 2286 qcom,smem-states = <&cdsp_smp2p_out 0>; 2287 qcom,smem-state-names = "stop"; 2288 2289 status = "disabled"; 2290 2291 glink-edge { 2292 interrupts = <GIC_SPI 261 IRQ_TYPE_EDGE_RISING>; 2293 label = "cdsp"; 2294 qcom,remote-pid = <5>; 2295 mboxes = <&apcs_glb 28>; 2296 2297 fastrpc { 2298 compatible = "qcom,fastrpc"; 2299 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2300 label = "cdsp"; 2301 qcom,non-secure-domain; 2302 #address-cells = <1>; 2303 #size-cells = <0>; 2304 2305 compute-cb@1 { 2306 compatible = "qcom,fastrpc-compute-cb"; 2307 reg = <1>; 2308 iommus = <&apps_smmu 0x0c01 0x0>; 2309 }; 2310 2311 compute-cb@2 { 2312 compatible = "qcom,fastrpc-compute-cb"; 2313 reg = <2>; 2314 iommus = <&apps_smmu 0x0c02 0x0>; 2315 }; 2316 2317 compute-cb@3 { 2318 compatible = "qcom,fastrpc-compute-cb"; 2319 reg = <3>; 2320 iommus = <&apps_smmu 0x0c03 0x0>; 2321 }; 2322 2323 compute-cb@4 { 2324 compatible = "qcom,fastrpc-compute-cb"; 2325 reg = <4>; 2326 iommus = <&apps_smmu 0x0c04 0x0>; 2327 }; 2328 2329 compute-cb@5 { 2330 compatible = "qcom,fastrpc-compute-cb"; 2331 reg = <5>; 2332 iommus = <&apps_smmu 0x0c05 0x0>; 2333 }; 2334 2335 compute-cb@6 { 2336 compatible = "qcom,fastrpc-compute-cb"; 2337 reg = <6>; 2338 iommus = <&apps_smmu 0x0c06 0x0>; 2339 }; 2340 2341 /* note: secure cb9 in downstream */ 2342 }; 2343 }; 2344 }; 2345 2346 apps_smmu: iommu@c600000 { 2347 compatible = "qcom,sm6115-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 2348 reg = <0x0 0x0c600000 0x0 0x80000>; 2349 #iommu-cells = <2>; 2350 #global-interrupts = <1>; 2351 2352 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 2353 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 2354 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 2355 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 2356 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 2357 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 2358 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 2359 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 2360 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 2361 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 2362 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 2363 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 2364 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 2365 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 2366 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 2367 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 2368 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 2369 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 2370 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 2371 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 2372 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 2373 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 2374 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 2375 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 2376 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 2377 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 2378 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 2379 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 2380 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 2381 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 2382 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 2383 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 2384 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 2385 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 2386 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 2387 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 2388 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 2389 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 2390 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 2391 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 2392 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 2393 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 2394 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 2395 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 2396 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 2397 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 2398 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 2399 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 2400 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 2401 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 2402 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 2403 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 2404 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 2405 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 2406 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 2407 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 2408 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 2409 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 2410 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 2411 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 2412 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 2413 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 2414 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 2415 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 2416 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 2417 }; 2418 2419 wifi: wifi@c800000 { 2420 compatible = "qcom,wcn3990-wifi"; 2421 reg = <0x0 0x0c800000 0x0 0x800000>; 2422 reg-names = "membase"; 2423 memory-region = <&wlan_msa_mem>; 2424 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, 2425 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, 2426 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, 2427 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>, 2428 <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>, 2429 <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>, 2430 <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>, 2431 <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>, 2432 <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>, 2433 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>, 2434 <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, 2435 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 2436 iommus = <&apps_smmu 0x1a0 0x1>; 2437 qcom,msa-fixed-perm; 2438 status = "disabled"; 2439 }; 2440 2441 watchdog@f017000 { 2442 compatible = "qcom,apss-wdt-sm6115", "qcom,kpss-wdt"; 2443 reg = <0x0 0x0f017000 0x0 0x1000>; 2444 clocks = <&sleep_clk>; 2445 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 2446 }; 2447 2448 apcs_glb: mailbox@f111000 { 2449 compatible = "qcom,sm6115-apcs-hmss-global", 2450 "qcom,msm8994-apcs-kpss-global"; 2451 reg = <0x0 0x0f111000 0x0 0x1000>; 2452 2453 #mbox-cells = <1>; 2454 }; 2455 2456 timer@f120000 { 2457 compatible = "arm,armv7-timer-mem"; 2458 reg = <0x0 0x0f120000 0x0 0x1000>; 2459 #address-cells = <2>; 2460 #size-cells = <2>; 2461 ranges; 2462 clock-frequency = <19200000>; 2463 2464 frame@f121000 { 2465 reg = <0x0 0x0f121000 0x0 0x1000>, <0x0 0x0f122000 0x0 0x1000>; 2466 frame-number = <0>; 2467 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 2468 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 2469 }; 2470 2471 frame@f123000 { 2472 reg = <0x0 0x0f123000 0x0 0x1000>; 2473 frame-number = <1>; 2474 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 2475 status = "disabled"; 2476 }; 2477 2478 frame@f124000 { 2479 reg = <0x0 0x0f124000 0x0 0x1000>; 2480 frame-number = <2>; 2481 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 2482 status = "disabled"; 2483 }; 2484 2485 frame@f125000 { 2486 reg = <0x0 0x0f125000 0x0 0x1000>; 2487 frame-number = <3>; 2488 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 2489 status = "disabled"; 2490 }; 2491 2492 frame@f126000 { 2493 reg = <0x0 0x0f126000 0x0 0x1000>; 2494 frame-number = <4>; 2495 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 2496 status = "disabled"; 2497 }; 2498 2499 frame@f127000 { 2500 reg = <0x0 0x0f127000 0x0 0x1000>; 2501 frame-number = <5>; 2502 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 2503 status = "disabled"; 2504 }; 2505 2506 frame@f128000 { 2507 reg = <0x0 0x0f128000 0x0 0x1000>; 2508 frame-number = <6>; 2509 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 2510 status = "disabled"; 2511 }; 2512 }; 2513 2514 intc: interrupt-controller@f200000 { 2515 compatible = "arm,gic-v3"; 2516 reg = <0x0 0x0f200000 0x0 0x10000>, 2517 <0x0 0x0f300000 0x0 0x100000>; 2518 #interrupt-cells = <3>; 2519 interrupt-controller; 2520 interrupt-parent = <&intc>; 2521 #redistributor-regions = <1>; 2522 redistributor-stride = <0x0 0x20000>; 2523 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 2524 }; 2525 2526 cpufreq_hw: cpufreq@f521000 { 2527 compatible = "qcom,sm6115-cpufreq-hw", "qcom,cpufreq-hw"; 2528 reg = <0x0 0x0f521000 0x0 0x1000>, 2529 <0x0 0x0f523000 0x0 0x1000>; 2530 2531 reg-names = "freq-domain0", "freq-domain1"; 2532 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>; 2533 clock-names = "xo", "alternate"; 2534 2535 #freq-domain-cells = <1>; 2536 #clock-cells = <1>; 2537 }; 2538 }; 2539 2540 thermal-zones { 2541 mapss-thermal { 2542 polling-delay-passive = <0>; 2543 polling-delay = <0>; 2544 thermal-sensors = <&tsens0 0>; 2545 2546 trips { 2547 trip-point0 { 2548 temperature = <115000>; 2549 hysteresis = <5000>; 2550 type = "passive"; 2551 }; 2552 2553 trip-point1 { 2554 temperature = <125000>; 2555 hysteresis = <1000>; 2556 type = "passive"; 2557 }; 2558 }; 2559 }; 2560 2561 cdsp-hvx-thermal { 2562 polling-delay-passive = <0>; 2563 polling-delay = <0>; 2564 thermal-sensors = <&tsens0 1>; 2565 2566 trips { 2567 trip-point0 { 2568 temperature = <115000>; 2569 hysteresis = <5000>; 2570 type = "passive"; 2571 }; 2572 2573 trip-point1 { 2574 temperature = <125000>; 2575 hysteresis = <1000>; 2576 type = "passive"; 2577 }; 2578 }; 2579 }; 2580 2581 wlan-thermal { 2582 polling-delay-passive = <0>; 2583 polling-delay = <0>; 2584 thermal-sensors = <&tsens0 2>; 2585 2586 trips { 2587 trip-point0 { 2588 temperature = <115000>; 2589 hysteresis = <5000>; 2590 type = "passive"; 2591 }; 2592 2593 trip-point1 { 2594 temperature = <125000>; 2595 hysteresis = <1000>; 2596 type = "passive"; 2597 }; 2598 }; 2599 }; 2600 2601 camera-thermal { 2602 polling-delay-passive = <0>; 2603 polling-delay = <0>; 2604 thermal-sensors = <&tsens0 3>; 2605 2606 trips { 2607 trip-point0 { 2608 temperature = <115000>; 2609 hysteresis = <5000>; 2610 type = "passive"; 2611 }; 2612 2613 trip-point1 { 2614 temperature = <125000>; 2615 hysteresis = <1000>; 2616 type = "passive"; 2617 }; 2618 }; 2619 }; 2620 2621 video-thermal { 2622 polling-delay-passive = <0>; 2623 polling-delay = <0>; 2624 thermal-sensors = <&tsens0 4>; 2625 2626 trips { 2627 trip-point0 { 2628 temperature = <115000>; 2629 hysteresis = <5000>; 2630 type = "passive"; 2631 }; 2632 2633 trip-point1 { 2634 temperature = <125000>; 2635 hysteresis = <1000>; 2636 type = "passive"; 2637 }; 2638 }; 2639 }; 2640 2641 modem1-thermal { 2642 polling-delay-passive = <0>; 2643 polling-delay = <0>; 2644 thermal-sensors = <&tsens0 5>; 2645 2646 trips { 2647 trip-point0 { 2648 temperature = <115000>; 2649 hysteresis = <5000>; 2650 type = "passive"; 2651 }; 2652 2653 trip-point1 { 2654 temperature = <125000>; 2655 hysteresis = <1000>; 2656 type = "passive"; 2657 }; 2658 }; 2659 }; 2660 2661 cpu4-thermal { 2662 polling-delay-passive = <0>; 2663 polling-delay = <0>; 2664 thermal-sensors = <&tsens0 6>; 2665 2666 trips { 2667 cpu4_alert0: trip-point0 { 2668 temperature = <90000>; 2669 hysteresis = <2000>; 2670 type = "passive"; 2671 }; 2672 2673 cpu4_alert1: trip-point1 { 2674 temperature = <95000>; 2675 hysteresis = <2000>; 2676 type = "passive"; 2677 }; 2678 2679 cpu4_crit: cpu_crit { 2680 temperature = <110000>; 2681 hysteresis = <1000>; 2682 type = "critical"; 2683 }; 2684 }; 2685 }; 2686 2687 cpu5-thermal { 2688 polling-delay-passive = <0>; 2689 polling-delay = <0>; 2690 thermal-sensors = <&tsens0 7>; 2691 2692 trips { 2693 cpu5_alert0: trip-point0 { 2694 temperature = <90000>; 2695 hysteresis = <2000>; 2696 type = "passive"; 2697 }; 2698 2699 cpu5_alert1: trip-point1 { 2700 temperature = <95000>; 2701 hysteresis = <2000>; 2702 type = "passive"; 2703 }; 2704 2705 cpu5_crit: cpu_crit { 2706 temperature = <110000>; 2707 hysteresis = <1000>; 2708 type = "critical"; 2709 }; 2710 }; 2711 }; 2712 2713 cpu6-thermal { 2714 polling-delay-passive = <0>; 2715 polling-delay = <0>; 2716 thermal-sensors = <&tsens0 8>; 2717 2718 trips { 2719 cpu6_alert0: trip-point0 { 2720 temperature = <90000>; 2721 hysteresis = <2000>; 2722 type = "passive"; 2723 }; 2724 2725 cpu6_alert1: trip-point1 { 2726 temperature = <95000>; 2727 hysteresis = <2000>; 2728 type = "passive"; 2729 }; 2730 2731 cpu6_crit: cpu_crit { 2732 temperature = <110000>; 2733 hysteresis = <1000>; 2734 type = "critical"; 2735 }; 2736 }; 2737 }; 2738 2739 cpu7-thermal { 2740 polling-delay-passive = <0>; 2741 polling-delay = <0>; 2742 thermal-sensors = <&tsens0 9>; 2743 2744 trips { 2745 cpu7_alert0: trip-point0 { 2746 temperature = <90000>; 2747 hysteresis = <2000>; 2748 type = "passive"; 2749 }; 2750 2751 cpu7_alert1: trip-point1 { 2752 temperature = <95000>; 2753 hysteresis = <2000>; 2754 type = "passive"; 2755 }; 2756 2757 cpu7_crit: cpu_crit { 2758 temperature = <110000>; 2759 hysteresis = <1000>; 2760 type = "critical"; 2761 }; 2762 }; 2763 }; 2764 2765 cpu45-thermal { 2766 polling-delay-passive = <0>; 2767 polling-delay = <0>; 2768 thermal-sensors = <&tsens0 10>; 2769 2770 trips { 2771 cpu45_alert0: trip-point0 { 2772 temperature = <90000>; 2773 hysteresis = <2000>; 2774 type = "passive"; 2775 }; 2776 2777 cpu45_alert1: trip-point1 { 2778 temperature = <95000>; 2779 hysteresis = <2000>; 2780 type = "passive"; 2781 }; 2782 2783 cpu45_crit: cpu_crit { 2784 temperature = <110000>; 2785 hysteresis = <1000>; 2786 type = "critical"; 2787 }; 2788 }; 2789 }; 2790 2791 cpu67-thermal { 2792 polling-delay-passive = <0>; 2793 polling-delay = <0>; 2794 thermal-sensors = <&tsens0 11>; 2795 2796 trips { 2797 cpu67_alert0: trip-point0 { 2798 temperature = <90000>; 2799 hysteresis = <2000>; 2800 type = "passive"; 2801 }; 2802 2803 cpu67_alert1: trip-point1 { 2804 temperature = <95000>; 2805 hysteresis = <2000>; 2806 type = "passive"; 2807 }; 2808 2809 cpu67_crit: cpu_crit { 2810 temperature = <110000>; 2811 hysteresis = <1000>; 2812 type = "critical"; 2813 }; 2814 }; 2815 }; 2816 2817 cpu0123-thermal { 2818 polling-delay-passive = <0>; 2819 polling-delay = <0>; 2820 thermal-sensors = <&tsens0 12>; 2821 2822 trips { 2823 cpu0123_alert0: trip-point0 { 2824 temperature = <90000>; 2825 hysteresis = <2000>; 2826 type = "passive"; 2827 }; 2828 2829 cpu0123_alert1: trip-point1 { 2830 temperature = <95000>; 2831 hysteresis = <2000>; 2832 type = "passive"; 2833 }; 2834 2835 cpu0123_crit: cpu_crit { 2836 temperature = <110000>; 2837 hysteresis = <1000>; 2838 type = "critical"; 2839 }; 2840 }; 2841 }; 2842 2843 modem0-thermal { 2844 polling-delay-passive = <0>; 2845 polling-delay = <0>; 2846 thermal-sensors = <&tsens0 13>; 2847 2848 trips { 2849 trip-point0 { 2850 temperature = <115000>; 2851 hysteresis = <5000>; 2852 type = "passive"; 2853 }; 2854 2855 trip-point1 { 2856 temperature = <125000>; 2857 hysteresis = <1000>; 2858 type = "passive"; 2859 }; 2860 }; 2861 }; 2862 2863 display-thermal { 2864 polling-delay-passive = <0>; 2865 polling-delay = <0>; 2866 thermal-sensors = <&tsens0 14>; 2867 2868 trips { 2869 trip-point0 { 2870 temperature = <115000>; 2871 hysteresis = <5000>; 2872 type = "passive"; 2873 }; 2874 2875 trip-point1 { 2876 temperature = <125000>; 2877 hysteresis = <1000>; 2878 type = "passive"; 2879 }; 2880 }; 2881 }; 2882 2883 gpu-thermal { 2884 polling-delay-passive = <0>; 2885 polling-delay = <0>; 2886 thermal-sensors = <&tsens0 15>; 2887 2888 trips { 2889 trip-point0 { 2890 temperature = <115000>; 2891 hysteresis = <5000>; 2892 type = "passive"; 2893 }; 2894 2895 trip-point1 { 2896 temperature = <125000>; 2897 hysteresis = <1000>; 2898 type = "passive"; 2899 }; 2900 }; 2901 }; 2902 }; 2903 2904 timer { 2905 compatible = "arm,armv8-timer"; 2906 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2907 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2908 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2909 <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 2910 }; 2911}; 2912