1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright (c) 2021, Iskren Chernev <iskren.chernev@gmail.com> 4 */ 5 6#include <dt-bindings/clock/qcom,gcc-sm6115.h> 7#include <dt-bindings/clock/qcom,sm6115-dispcc.h> 8#include <dt-bindings/clock/qcom,rpmcc.h> 9#include <dt-bindings/dma/qcom-gpi.h> 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/power/qcom-rpmpd.h> 13 14/ { 15 interrupt-parent = <&intc>; 16 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 chosen { }; 21 22 clocks { 23 xo_board: xo-board { 24 compatible = "fixed-clock"; 25 #clock-cells = <0>; 26 }; 27 28 sleep_clk: sleep-clk { 29 compatible = "fixed-clock"; 30 #clock-cells = <0>; 31 }; 32 }; 33 34 cpus { 35 #address-cells = <2>; 36 #size-cells = <0>; 37 38 CPU0: cpu@0 { 39 device_type = "cpu"; 40 compatible = "qcom,kryo260"; 41 reg = <0x0 0x0>; 42 capacity-dmips-mhz = <1024>; 43 dynamic-power-coefficient = <100>; 44 enable-method = "psci"; 45 next-level-cache = <&L2_0>; 46 qcom,freq-domain = <&cpufreq_hw 0>; 47 L2_0: l2-cache { 48 compatible = "cache"; 49 cache-level = <2>; 50 }; 51 }; 52 53 CPU1: cpu@1 { 54 device_type = "cpu"; 55 compatible = "qcom,kryo260"; 56 reg = <0x0 0x1>; 57 capacity-dmips-mhz = <1024>; 58 dynamic-power-coefficient = <100>; 59 enable-method = "psci"; 60 next-level-cache = <&L2_0>; 61 qcom,freq-domain = <&cpufreq_hw 0>; 62 }; 63 64 CPU2: cpu@2 { 65 device_type = "cpu"; 66 compatible = "qcom,kryo260"; 67 reg = <0x0 0x2>; 68 capacity-dmips-mhz = <1024>; 69 dynamic-power-coefficient = <100>; 70 enable-method = "psci"; 71 next-level-cache = <&L2_0>; 72 qcom,freq-domain = <&cpufreq_hw 0>; 73 }; 74 75 CPU3: cpu@3 { 76 device_type = "cpu"; 77 compatible = "qcom,kryo260"; 78 reg = <0x0 0x3>; 79 capacity-dmips-mhz = <1024>; 80 dynamic-power-coefficient = <100>; 81 enable-method = "psci"; 82 next-level-cache = <&L2_0>; 83 qcom,freq-domain = <&cpufreq_hw 0>; 84 }; 85 86 CPU4: cpu@100 { 87 device_type = "cpu"; 88 compatible = "qcom,kryo260"; 89 reg = <0x0 0x100>; 90 enable-method = "psci"; 91 capacity-dmips-mhz = <1638>; 92 dynamic-power-coefficient = <282>; 93 next-level-cache = <&L2_1>; 94 qcom,freq-domain = <&cpufreq_hw 1>; 95 L2_1: l2-cache { 96 compatible = "cache"; 97 cache-level = <2>; 98 }; 99 }; 100 101 CPU5: cpu@101 { 102 device_type = "cpu"; 103 compatible = "qcom,kryo260"; 104 reg = <0x0 0x101>; 105 capacity-dmips-mhz = <1638>; 106 dynamic-power-coefficient = <282>; 107 enable-method = "psci"; 108 next-level-cache = <&L2_1>; 109 qcom,freq-domain = <&cpufreq_hw 1>; 110 }; 111 112 CPU6: cpu@102 { 113 device_type = "cpu"; 114 compatible = "qcom,kryo260"; 115 reg = <0x0 0x102>; 116 capacity-dmips-mhz = <1638>; 117 dynamic-power-coefficient = <282>; 118 enable-method = "psci"; 119 next-level-cache = <&L2_1>; 120 qcom,freq-domain = <&cpufreq_hw 1>; 121 }; 122 123 CPU7: cpu@103 { 124 device_type = "cpu"; 125 compatible = "qcom,kryo260"; 126 reg = <0x0 0x103>; 127 capacity-dmips-mhz = <1638>; 128 dynamic-power-coefficient = <282>; 129 enable-method = "psci"; 130 next-level-cache = <&L2_1>; 131 qcom,freq-domain = <&cpufreq_hw 1>; 132 }; 133 134 cpu-map { 135 cluster0 { 136 core0 { 137 cpu = <&CPU0>; 138 }; 139 140 core1 { 141 cpu = <&CPU1>; 142 }; 143 144 core2 { 145 cpu = <&CPU2>; 146 }; 147 148 core3 { 149 cpu = <&CPU3>; 150 }; 151 }; 152 153 cluster1 { 154 core0 { 155 cpu = <&CPU4>; 156 }; 157 158 core1 { 159 cpu = <&CPU5>; 160 }; 161 162 core2 { 163 cpu = <&CPU6>; 164 }; 165 166 core3 { 167 cpu = <&CPU7>; 168 }; 169 }; 170 }; 171 }; 172 173 firmware { 174 scm: scm { 175 compatible = "qcom,scm-sm6115", "qcom,scm"; 176 #reset-cells = <1>; 177 }; 178 }; 179 180 memory@80000000 { 181 device_type = "memory"; 182 /* We expect the bootloader to fill in the size */ 183 reg = <0 0x80000000 0 0>; 184 }; 185 186 pmu { 187 compatible = "arm,armv8-pmuv3"; 188 interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>; 189 }; 190 191 psci { 192 compatible = "arm,psci-1.0"; 193 method = "smc"; 194 }; 195 196 reserved_memory: reserved-memory { 197 #address-cells = <2>; 198 #size-cells = <2>; 199 ranges; 200 201 hyp_mem: memory@45700000 { 202 reg = <0x0 0x45700000 0x0 0x600000>; 203 no-map; 204 }; 205 206 xbl_aop_mem: memory@45e00000 { 207 reg = <0x0 0x45e00000 0x0 0x140000>; 208 no-map; 209 }; 210 211 sec_apps_mem: memory@45fff000 { 212 reg = <0x0 0x45fff000 0x0 0x1000>; 213 no-map; 214 }; 215 216 smem_mem: memory@46000000 { 217 compatible = "qcom,smem"; 218 reg = <0x0 0x46000000 0x0 0x200000>; 219 no-map; 220 221 hwlocks = <&tcsr_mutex 3>; 222 qcom,rpm-msg-ram = <&rpm_msg_ram>; 223 }; 224 225 cdsp_sec_mem: memory@46200000 { 226 reg = <0x0 0x46200000 0x0 0x1e00000>; 227 no-map; 228 }; 229 230 pil_modem_mem: memory@4ab00000 { 231 reg = <0x0 0x4ab00000 0x0 0x6900000>; 232 no-map; 233 }; 234 235 pil_video_mem: memory@51400000 { 236 reg = <0x0 0x51400000 0x0 0x500000>; 237 no-map; 238 }; 239 240 wlan_msa_mem: memory@51900000 { 241 reg = <0x0 0x51900000 0x0 0x100000>; 242 no-map; 243 }; 244 245 pil_cdsp_mem: memory@51a00000 { 246 reg = <0x0 0x51a00000 0x0 0x1e00000>; 247 no-map; 248 }; 249 250 pil_adsp_mem: memory@53800000 { 251 reg = <0x0 0x53800000 0x0 0x2800000>; 252 no-map; 253 }; 254 255 pil_ipa_fw_mem: memory@56100000 { 256 reg = <0x0 0x56100000 0x0 0x10000>; 257 no-map; 258 }; 259 260 pil_ipa_gsi_mem: memory@56110000 { 261 reg = <0x0 0x56110000 0x0 0x5000>; 262 no-map; 263 }; 264 265 pil_gpu_mem: memory@56115000 { 266 reg = <0x0 0x56115000 0x0 0x2000>; 267 no-map; 268 }; 269 270 cont_splash_memory: memory@5c000000 { 271 reg = <0x0 0x5c000000 0x0 0x00f00000>; 272 no-map; 273 }; 274 275 dfps_data_memory: memory@5cf00000 { 276 reg = <0x0 0x5cf00000 0x0 0x0100000>; 277 no-map; 278 }; 279 280 removed_mem: memory@60000000 { 281 reg = <0x0 0x60000000 0x0 0x3900000>; 282 no-map; 283 }; 284 }; 285 286 rpm-glink { 287 compatible = "qcom,glink-rpm"; 288 289 interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>; 290 qcom,rpm-msg-ram = <&rpm_msg_ram>; 291 mboxes = <&apcs_glb 0>; 292 293 rpm_requests: rpm-requests { 294 compatible = "qcom,rpm-sm6115"; 295 qcom,glink-channels = "rpm_requests"; 296 297 rpmcc: clock-controller { 298 compatible = "qcom,rpmcc-sm6115", "qcom,rpmcc"; 299 clocks = <&xo_board>; 300 clock-names = "xo"; 301 #clock-cells = <1>; 302 }; 303 304 rpmpd: power-controller { 305 compatible = "qcom,sm6115-rpmpd"; 306 #power-domain-cells = <1>; 307 operating-points-v2 = <&rpmpd_opp_table>; 308 309 rpmpd_opp_table: opp-table { 310 compatible = "operating-points-v2"; 311 312 rpmpd_opp_min_svs: opp1 { 313 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 314 }; 315 316 rpmpd_opp_low_svs: opp2 { 317 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 318 }; 319 320 rpmpd_opp_svs: opp3 { 321 opp-level = <RPM_SMD_LEVEL_SVS>; 322 }; 323 324 rpmpd_opp_svs_plus: opp4 { 325 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 326 }; 327 328 rpmpd_opp_nom: opp5 { 329 opp-level = <RPM_SMD_LEVEL_NOM>; 330 }; 331 332 rpmpd_opp_nom_plus: opp6 { 333 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 334 }; 335 336 rpmpd_opp_turbo: opp7 { 337 opp-level = <RPM_SMD_LEVEL_TURBO>; 338 }; 339 340 rpmpd_opp_turbo_plus: opp8 { 341 opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>; 342 }; 343 }; 344 }; 345 }; 346 }; 347 348 soc: soc@0 { 349 compatible = "simple-bus"; 350 #address-cells = <1>; 351 #size-cells = <1>; 352 ranges = <0 0 0 0xffffffff>; 353 354 tcsr_mutex: hwlock@340000 { 355 compatible = "qcom,tcsr-mutex"; 356 reg = <0x00340000 0x20000>; 357 #hwlock-cells = <1>; 358 }; 359 360 tlmm: pinctrl@500000 { 361 compatible = "qcom,sm6115-tlmm"; 362 reg = <0x00500000 0x400000>, <0x00900000 0x400000>, <0x00d00000 0x400000>; 363 reg-names = "west", "south", "east"; 364 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 365 gpio-controller; 366 gpio-ranges = <&tlmm 0 0 121>; 367 #gpio-cells = <2>; 368 interrupt-controller; 369 #interrupt-cells = <2>; 370 371 qup_i2c0_default: qup-i2c0-default-state { 372 pins = "gpio0", "gpio1"; 373 function = "qup0"; 374 drive-strength = <2>; 375 bias-pull-up; 376 }; 377 378 qup_i2c1_default: qup-i2c1-default-state { 379 pins = "gpio4", "gpio5"; 380 function = "qup1"; 381 drive-strength = <2>; 382 bias-pull-up; 383 }; 384 385 qup_i2c2_default: qup-i2c2-default-state { 386 pins = "gpio6", "gpio7"; 387 function = "qup2"; 388 drive-strength = <2>; 389 bias-pull-up; 390 }; 391 392 qup_i2c3_default: qup-i2c3-default-state { 393 pins = "gpio8", "gpio9"; 394 function = "qup3"; 395 drive-strength = <2>; 396 bias-pull-up; 397 }; 398 399 qup_i2c4_default: qup-i2c4-default-state { 400 pins = "gpio12", "gpio13"; 401 function = "qup4"; 402 drive-strength = <2>; 403 bias-pull-up; 404 }; 405 406 qup_i2c5_default: qup-i2c5-default-state { 407 pins = "gpio14", "gpio15"; 408 function = "qup5"; 409 drive-strength = <2>; 410 bias-pull-up; 411 }; 412 413 qup_spi0_default: qup-spi0-default-state { 414 pins = "gpio0", "gpio1","gpio2", "gpio3"; 415 function = "qup0"; 416 drive-strength = <2>; 417 bias-pull-up; 418 }; 419 420 qup_spi1_default: qup-spi1-default-state { 421 pins = "gpio4", "gpio5", "gpio69", "gpio70"; 422 function = "qup1"; 423 drive-strength = <2>; 424 bias-pull-up; 425 }; 426 427 qup_spi2_default: qup-spi2-default-state { 428 pins = "gpio6", "gpio7", "gpio71", "gpio80"; 429 function = "qup2"; 430 drive-strength = <2>; 431 bias-pull-up; 432 }; 433 434 qup_spi3_default: qup-spi3-default-state { 435 pins = "gpio8", "gpio9", "gpio10", "gpio11"; 436 function = "qup3"; 437 drive-strength = <2>; 438 bias-pull-up; 439 }; 440 441 qup_spi4_default: qup-spi4-default-state { 442 pins = "gpio12", "gpio13", "gpio96", "gpio97"; 443 function = "qup4"; 444 drive-strength = <2>; 445 bias-pull-up; 446 }; 447 448 qup_spi5_default: qup-spi5-default-state { 449 pins = "gpio14", "gpio15", "gpio16", "gpio17"; 450 function = "qup5"; 451 drive-strength = <2>; 452 bias-pull-up; 453 }; 454 455 sdc1_state_on: sdc1-on-state { 456 clk-pins { 457 pins = "sdc1_clk"; 458 bias-disable; 459 drive-strength = <16>; 460 }; 461 462 cmd-pins { 463 pins = "sdc1_cmd"; 464 bias-pull-up; 465 drive-strength = <10>; 466 }; 467 468 data-pins { 469 pins = "sdc1_data"; 470 bias-pull-up; 471 drive-strength = <10>; 472 }; 473 474 rclk-pins { 475 pins = "sdc1_rclk"; 476 bias-pull-down; 477 }; 478 }; 479 480 sdc1_state_off: sdc1-off-state { 481 clk-pins { 482 pins = "sdc1_clk"; 483 bias-disable; 484 drive-strength = <2>; 485 }; 486 487 cmd-pins { 488 pins = "sdc1_cmd"; 489 bias-pull-up; 490 drive-strength = <2>; 491 }; 492 493 data-pins { 494 pins = "sdc1_data"; 495 bias-pull-up; 496 drive-strength = <2>; 497 }; 498 499 rclk-pins { 500 pins = "sdc1_rclk"; 501 bias-pull-down; 502 }; 503 }; 504 505 sdc2_state_on: sdc2-on-state { 506 clk-pins { 507 pins = "sdc2_clk"; 508 bias-disable; 509 drive-strength = <16>; 510 }; 511 512 cmd-pins { 513 pins = "sdc2_cmd"; 514 bias-pull-up; 515 drive-strength = <10>; 516 }; 517 518 data-pins { 519 pins = "sdc2_data"; 520 bias-pull-up; 521 drive-strength = <10>; 522 }; 523 524 sd-cd-pins { 525 pins = "gpio88"; 526 function = "gpio"; 527 bias-pull-up; 528 drive-strength = <2>; 529 }; 530 }; 531 532 sdc2_state_off: sdc2-off-state { 533 clk-pins { 534 pins = "sdc2_clk"; 535 bias-disable; 536 drive-strength = <2>; 537 }; 538 539 cmd-pins { 540 pins = "sdc2_cmd"; 541 bias-pull-up; 542 drive-strength = <2>; 543 }; 544 545 data-pins { 546 pins = "sdc2_data"; 547 bias-pull-up; 548 drive-strength = <2>; 549 }; 550 551 sd-cd-pins { 552 pins = "gpio88"; 553 function = "gpio"; 554 bias-disable; 555 drive-strength = <2>; 556 }; 557 }; 558 }; 559 560 gcc: clock-controller@1400000 { 561 compatible = "qcom,gcc-sm6115"; 562 reg = <0x01400000 0x1f0000>; 563 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>; 564 clock-names = "bi_tcxo", "sleep_clk"; 565 #clock-cells = <1>; 566 #reset-cells = <1>; 567 #power-domain-cells = <1>; 568 }; 569 570 usb_1_hsphy: phy@1613000 { 571 compatible = "qcom,sm6115-qusb2-phy"; 572 reg = <0x01613000 0x180>; 573 #phy-cells = <0>; 574 575 clocks = <&gcc GCC_AHB2PHY_USB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>; 576 clock-names = "cfg_ahb", "ref"; 577 578 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 579 nvmem-cells = <&qusb2_hstx_trim>; 580 581 status = "disabled"; 582 }; 583 584 qfprom@1b40000 { 585 compatible = "qcom,sm6115-qfprom", "qcom,qfprom"; 586 reg = <0x01b40000 0x7000>; 587 #address-cells = <1>; 588 #size-cells = <1>; 589 590 qusb2_hstx_trim: hstx-trim@25b { 591 reg = <0x25b 0x1>; 592 bits = <1 4>; 593 }; 594 }; 595 596 rng: rng@1b53000 { 597 compatible = "qcom,prng-ee"; 598 reg = <0x01b53000 0x1000>; 599 clocks = <&gcc GCC_PRNG_AHB_CLK>; 600 clock-names = "core"; 601 }; 602 603 spmi_bus: spmi@1c40000 { 604 compatible = "qcom,spmi-pmic-arb"; 605 reg = <0x01c40000 0x1100>, 606 <0x01e00000 0x2000000>, 607 <0x03e00000 0x100000>, 608 <0x03f00000 0xa0000>, 609 <0x01c0a000 0x26000>; 610 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 611 interrupt-names = "periph_irq"; 612 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 613 qcom,ee = <0>; 614 qcom,channel = <0>; 615 #address-cells = <2>; 616 #size-cells = <0>; 617 interrupt-controller; 618 #interrupt-cells = <4>; 619 }; 620 621 tsens0: thermal-sensor@4410000 { 622 compatible = "qcom,sm6115-tsens", "qcom,tsens-v2"; 623 reg = <0x04411000 0x1ff>, /* TM */ 624 <0x04410000 0x8>; /* SROT */ 625 #qcom,sensors = <16>; 626 interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 627 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 628 interrupt-names = "uplow", "critical"; 629 #thermal-sensor-cells = <1>; 630 }; 631 632 rpm_msg_ram: sram@45f0000 { 633 compatible = "qcom,rpm-msg-ram"; 634 reg = <0x045f0000 0x7000>; 635 }; 636 637 sram@4690000 { 638 compatible = "qcom,rpm-stats"; 639 reg = <0x04690000 0x10000>; 640 }; 641 642 sdhc_1: mmc@4744000 { 643 compatible = "qcom,sm6115-sdhci", "qcom,sdhci-msm-v5"; 644 reg = <0x04744000 0x1000>, <0x04745000 0x1000>, <0x04748000 0x8000>; 645 reg-names = "hc", "cqhci", "ice"; 646 647 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, 648 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 649 interrupt-names = "hc_irq", "pwr_irq"; 650 651 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 652 <&gcc GCC_SDCC1_APPS_CLK>, 653 <&rpmcc RPM_SMD_XO_CLK_SRC>, 654 <&gcc GCC_SDCC1_ICE_CORE_CLK>; 655 clock-names = "iface", "core", "xo", "ice"; 656 657 pinctrl-0 = <&sdc1_state_on>; 658 pinctrl-1 = <&sdc1_state_off>; 659 pinctrl-names = "default", "sleep"; 660 661 bus-width = <8>; 662 status = "disabled"; 663 }; 664 665 sdhc_2: mmc@4784000 { 666 compatible = "qcom,sm6115-sdhci", "qcom,sdhci-msm-v5"; 667 reg = <0x04784000 0x1000>; 668 reg-names = "hc"; 669 670 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 671 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 672 interrupt-names = "hc_irq", "pwr_irq"; 673 674 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 675 <&gcc GCC_SDCC2_APPS_CLK>, 676 <&rpmcc RPM_SMD_XO_CLK_SRC>; 677 clock-names = "iface", "core", "xo"; 678 679 pinctrl-0 = <&sdc2_state_on>; 680 pinctrl-1 = <&sdc2_state_off>; 681 pinctrl-names = "default", "sleep"; 682 683 power-domains = <&rpmpd SM6115_VDDCX>; 684 operating-points-v2 = <&sdhc2_opp_table>; 685 iommus = <&apps_smmu 0x00a0 0x0>; 686 resets = <&gcc GCC_SDCC2_BCR>; 687 688 bus-width = <4>; 689 qcom,dll-config = <0x0007642c>; 690 qcom,ddr-config = <0x80040868>; 691 status = "disabled"; 692 693 sdhc2_opp_table: opp-table { 694 compatible = "operating-points-v2"; 695 696 opp-100000000 { 697 opp-hz = /bits/ 64 <100000000>; 698 required-opps = <&rpmpd_opp_low_svs>; 699 }; 700 701 opp-202000000 { 702 opp-hz = /bits/ 64 <202000000>; 703 required-opps = <&rpmpd_opp_nom>; 704 }; 705 }; 706 }; 707 708 ufs_mem_hc: ufs@4804000 { 709 compatible = "qcom,sm6115-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; 710 reg = <0x04804000 0x3000>, <0x04810000 0x8000>; 711 reg-names = "std", "ice"; 712 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 713 phys = <&ufs_mem_phy_lanes>; 714 phy-names = "ufsphy"; 715 lanes-per-direction = <1>; 716 #reset-cells = <1>; 717 resets = <&gcc GCC_UFS_PHY_BCR>; 718 reset-names = "rst"; 719 720 power-domains = <&gcc GCC_UFS_PHY_GDSC>; 721 iommus = <&apps_smmu 0x100 0>; 722 723 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 724 <&gcc GCC_SYS_NOC_UFS_PHY_AXI_CLK>, 725 <&gcc GCC_UFS_PHY_AHB_CLK>, 726 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 727 <&rpmcc RPM_SMD_XO_CLK_SRC>, 728 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 729 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 730 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 731 clock-names = "core_clk", 732 "bus_aggr_clk", 733 "iface_clk", 734 "core_clk_unipro", 735 "ref_clk", 736 "tx_lane0_sync_clk", 737 "rx_lane0_sync_clk", 738 "ice_core_clk"; 739 740 freq-table-hz = <50000000 200000000>, 741 <0 0>, 742 <0 0>, 743 <37500000 150000000>, 744 <0 0>, 745 <0 0>, 746 <0 0>, 747 <75000000 300000000>; 748 749 status = "disabled"; 750 }; 751 752 ufs_mem_phy: phy@4807000 { 753 compatible = "qcom,sm6115-qmp-ufs-phy"; 754 reg = <0x04807000 0x1c4>; 755 #address-cells = <1>; 756 #size-cells = <1>; 757 ranges; 758 759 clocks = <&gcc GCC_UFS_CLKREF_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 760 clock-names = "ref", "ref_aux"; 761 762 resets = <&ufs_mem_hc 0>; 763 reset-names = "ufsphy"; 764 status = "disabled"; 765 766 ufs_mem_phy_lanes: phy@4807400 { 767 reg = <0x04807400 0x098>, 768 <0x04807600 0x130>, 769 <0x04807c00 0x16c>; 770 #phy-cells = <0>; 771 }; 772 }; 773 774 gpi_dma0: dma-controller@4a00000 { 775 compatible = "qcom,sm6115-gpi-dma", "qcom,sm6350-gpi-dma"; 776 reg = <0x04a00000 0x60000>; 777 interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 778 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 779 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 780 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 781 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 782 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 783 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 784 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 785 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 786 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; 787 dma-channels = <10>; 788 dma-channel-mask = <0xf>; 789 iommus = <&apps_smmu 0xf6 0x0>; 790 #dma-cells = <3>; 791 status = "disabled"; 792 }; 793 794 qupv3_id_0: geniqup@4ac0000 { 795 compatible = "qcom,geni-se-qup"; 796 reg = <0x04ac0000 0x2000>; 797 clock-names = "m-ahb", "s-ahb"; 798 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 799 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 800 #address-cells = <1>; 801 #size-cells = <1>; 802 iommus = <&apps_smmu 0xe3 0x0>; 803 ranges; 804 status = "disabled"; 805 806 i2c0: i2c@4a80000 { 807 compatible = "qcom,geni-i2c"; 808 reg = <0x04a80000 0x4000>; 809 clock-names = "se"; 810 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 811 pinctrl-names = "default"; 812 pinctrl-0 = <&qup_i2c0_default>; 813 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 814 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 815 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 816 dma-names = "tx", "rx"; 817 #address-cells = <1>; 818 #size-cells = <0>; 819 status = "disabled"; 820 }; 821 822 spi0: spi@4a80000 { 823 compatible = "qcom,geni-spi"; 824 reg = <0x04a80000 0x4000>; 825 clock-names = "se"; 826 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 827 pinctrl-names = "default"; 828 pinctrl-0 = <&qup_spi0_default>; 829 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 830 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 831 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 832 dma-names = "tx", "rx"; 833 #address-cells = <1>; 834 #size-cells = <0>; 835 status = "disabled"; 836 }; 837 838 i2c1: i2c@4a84000 { 839 compatible = "qcom,geni-i2c"; 840 reg = <0x04a84000 0x4000>; 841 clock-names = "se"; 842 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 843 pinctrl-names = "default"; 844 pinctrl-0 = <&qup_i2c1_default>; 845 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 846 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 847 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 848 dma-names = "tx", "rx"; 849 #address-cells = <1>; 850 #size-cells = <0>; 851 status = "disabled"; 852 }; 853 854 spi1: spi@4a84000 { 855 compatible = "qcom,geni-spi"; 856 reg = <0x04a84000 0x4000>; 857 clock-names = "se"; 858 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 859 pinctrl-names = "default"; 860 pinctrl-0 = <&qup_spi1_default>; 861 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 862 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 863 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 864 dma-names = "tx", "rx"; 865 #address-cells = <1>; 866 #size-cells = <0>; 867 status = "disabled"; 868 }; 869 870 i2c2: i2c@4a88000 { 871 compatible = "qcom,geni-i2c"; 872 reg = <0x04a88000 0x4000>; 873 clock-names = "se"; 874 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 875 pinctrl-names = "default"; 876 pinctrl-0 = <&qup_i2c2_default>; 877 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; 878 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 879 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 880 dma-names = "tx", "rx"; 881 #address-cells = <1>; 882 #size-cells = <0>; 883 status = "disabled"; 884 }; 885 886 spi2: spi@4a88000 { 887 compatible = "qcom,geni-spi"; 888 reg = <0x04a88000 0x4000>; 889 clock-names = "se"; 890 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 891 pinctrl-names = "default"; 892 pinctrl-0 = <&qup_spi2_default>; 893 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; 894 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 895 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 896 dma-names = "tx", "rx"; 897 #address-cells = <1>; 898 #size-cells = <0>; 899 status = "disabled"; 900 }; 901 902 i2c3: i2c@4a8c000 { 903 compatible = "qcom,geni-i2c"; 904 reg = <0x04a8c000 0x4000>; 905 clock-names = "se"; 906 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 907 pinctrl-names = "default"; 908 pinctrl-0 = <&qup_i2c3_default>; 909 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 910 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 911 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 912 dma-names = "tx", "rx"; 913 #address-cells = <1>; 914 #size-cells = <0>; 915 status = "disabled"; 916 }; 917 918 spi3: spi@4a8c000 { 919 compatible = "qcom,geni-spi"; 920 reg = <0x04a8c000 0x4000>; 921 clock-names = "se"; 922 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 923 pinctrl-names = "default"; 924 pinctrl-0 = <&qup_spi3_default>; 925 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 926 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 927 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 928 dma-names = "tx", "rx"; 929 #address-cells = <1>; 930 #size-cells = <0>; 931 status = "disabled"; 932 }; 933 934 i2c4: i2c@4a90000 { 935 compatible = "qcom,geni-i2c"; 936 reg = <0x04a90000 0x4000>; 937 clock-names = "se"; 938 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 939 pinctrl-names = "default"; 940 pinctrl-0 = <&qup_i2c4_default>; 941 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 942 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 943 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 944 dma-names = "tx", "rx"; 945 #address-cells = <1>; 946 #size-cells = <0>; 947 status = "disabled"; 948 }; 949 950 spi4: spi@4a90000 { 951 compatible = "qcom,geni-spi"; 952 reg = <0x04a90000 0x4000>; 953 clock-names = "se"; 954 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 955 pinctrl-names = "default"; 956 pinctrl-0 = <&qup_spi4_default>; 957 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 958 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 959 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 960 dma-names = "tx", "rx"; 961 #address-cells = <1>; 962 #size-cells = <0>; 963 status = "disabled"; 964 }; 965 966 i2c5: i2c@4a94000 { 967 compatible = "qcom,geni-i2c"; 968 reg = <0x04a94000 0x4000>; 969 clock-names = "se"; 970 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 971 pinctrl-names = "default"; 972 pinctrl-0 = <&qup_i2c5_default>; 973 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; 974 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 975 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 976 dma-names = "tx", "rx"; 977 #address-cells = <1>; 978 #size-cells = <0>; 979 status = "disabled"; 980 }; 981 982 spi5: spi@4a94000 { 983 compatible = "qcom,geni-spi"; 984 reg = <0x04a94000 0x4000>; 985 clock-names = "se"; 986 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 987 pinctrl-names = "default"; 988 pinctrl-0 = <&qup_spi5_default>; 989 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; 990 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 991 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 992 dma-names = "tx", "rx"; 993 #address-cells = <1>; 994 #size-cells = <0>; 995 status = "disabled"; 996 }; 997 }; 998 999 usb_1: usb@4ef8800 { 1000 compatible = "qcom,sm6115-dwc3", "qcom,dwc3"; 1001 reg = <0x04ef8800 0x400>; 1002 #address-cells = <1>; 1003 #size-cells = <1>; 1004 ranges; 1005 1006 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 1007 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 1008 <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>, 1009 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 1010 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1011 <&gcc GCC_USB3_PRIM_CLKREF_CLK>; 1012 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", "xo"; 1013 1014 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1015 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 1016 assigned-clock-rates = <19200000>, <66666667>; 1017 1018 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 1019 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>; 1020 interrupt-names = "hs_phy_irq", "ss_phy_irq"; 1021 1022 resets = <&gcc GCC_USB30_PRIM_BCR>; 1023 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 1024 qcom,select-utmi-as-pipe-clk; 1025 status = "disabled"; 1026 1027 usb_1_dwc3: usb@4e00000 { 1028 compatible = "snps,dwc3"; 1029 reg = <0x04e00000 0xcd00>; 1030 interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 1031 phys = <&usb_1_hsphy>; 1032 phy-names = "usb2-phy"; 1033 iommus = <&apps_smmu 0x120 0x0>; 1034 snps,dis_u2_susphy_quirk; 1035 snps,dis_enblslpm_quirk; 1036 snps,has-lpm-erratum; 1037 snps,hird-threshold = /bits/ 8 <0x10>; 1038 snps,usb3_lpm_capable; 1039 maximum-speed = "high-speed"; 1040 dr_mode = "peripheral"; 1041 }; 1042 }; 1043 1044 mdss: display-subsystem@5e00000 { 1045 compatible = "qcom,sm6115-mdss"; 1046 reg = <0x05e00000 0x1000>; 1047 reg-names = "mdss"; 1048 1049 power-domains = <&dispcc MDSS_GDSC>; 1050 1051 clocks = <&gcc GCC_DISP_AHB_CLK>, 1052 <&gcc GCC_DISP_HF_AXI_CLK>, 1053 <&dispcc DISP_CC_MDSS_MDP_CLK>; 1054 1055 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 1056 interrupt-controller; 1057 #interrupt-cells = <1>; 1058 1059 iommus = <&apps_smmu 0x420 0x2>, 1060 <&apps_smmu 0x421 0x0>; 1061 1062 #address-cells = <1>; 1063 #size-cells = <1>; 1064 ranges; 1065 1066 status = "disabled"; 1067 1068 mdp: display-controller@5e01000 { 1069 compatible = "qcom,sm6115-dpu"; 1070 reg = <0x05e01000 0x8f000>, 1071 <0x05eb0000 0x2008>; 1072 reg-names = "mdp", "vbif"; 1073 1074 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 1075 <&dispcc DISP_CC_MDSS_AHB_CLK>, 1076 <&dispcc DISP_CC_MDSS_MDP_CLK>, 1077 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 1078 <&dispcc DISP_CC_MDSS_ROT_CLK>, 1079 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 1080 clock-names = "bus", 1081 "iface", 1082 "core", 1083 "lut", 1084 "rot", 1085 "vsync"; 1086 1087 operating-points-v2 = <&mdp_opp_table>; 1088 power-domains = <&rpmpd SM6115_VDDCX>; 1089 1090 interrupt-parent = <&mdss>; 1091 interrupts = <0>; 1092 1093 ports { 1094 #address-cells = <1>; 1095 #size-cells = <0>; 1096 1097 port@0 { 1098 reg = <0>; 1099 dpu_intf1_out: endpoint { 1100 remote-endpoint = <&dsi0_in>; 1101 }; 1102 }; 1103 }; 1104 1105 mdp_opp_table: opp-table { 1106 compatible = "operating-points-v2"; 1107 1108 opp-19200000 { 1109 opp-hz = /bits/ 64 <19200000>; 1110 required-opps = <&rpmpd_opp_min_svs>; 1111 }; 1112 1113 opp-192000000 { 1114 opp-hz = /bits/ 64 <192000000>; 1115 required-opps = <&rpmpd_opp_low_svs>; 1116 }; 1117 1118 opp-256000000 { 1119 opp-hz = /bits/ 64 <256000000>; 1120 required-opps = <&rpmpd_opp_svs>; 1121 }; 1122 1123 opp-307200000 { 1124 opp-hz = /bits/ 64 <307200000>; 1125 required-opps = <&rpmpd_opp_svs_plus>; 1126 }; 1127 1128 opp-384000000 { 1129 opp-hz = /bits/ 64 <384000000>; 1130 required-opps = <&rpmpd_opp_nom>; 1131 }; 1132 }; 1133 }; 1134 1135 dsi0: dsi@5e94000 { 1136 compatible = "qcom,dsi-ctrl-6g-qcm2290"; 1137 reg = <0x05e94000 0x400>; 1138 reg-names = "dsi_ctrl"; 1139 1140 interrupt-parent = <&mdss>; 1141 interrupts = <4>; 1142 1143 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 1144 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 1145 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 1146 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 1147 <&dispcc DISP_CC_MDSS_AHB_CLK>, 1148 <&gcc GCC_DISP_HF_AXI_CLK>; 1149 clock-names = "byte", 1150 "byte_intf", 1151 "pixel", 1152 "core", 1153 "iface", 1154 "bus"; 1155 1156 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 1157 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 1158 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; 1159 1160 operating-points-v2 = <&dsi_opp_table>; 1161 power-domains = <&rpmpd SM6115_VDDCX>; 1162 phys = <&dsi0_phy>; 1163 1164 #address-cells = <1>; 1165 #size-cells = <0>; 1166 1167 status = "disabled"; 1168 1169 ports { 1170 #address-cells = <1>; 1171 #size-cells = <0>; 1172 1173 port@0 { 1174 reg = <0>; 1175 dsi0_in: endpoint { 1176 remote-endpoint = <&dpu_intf1_out>; 1177 }; 1178 }; 1179 1180 port@1 { 1181 reg = <1>; 1182 dsi0_out: endpoint { 1183 }; 1184 }; 1185 }; 1186 1187 dsi_opp_table: opp-table { 1188 compatible = "operating-points-v2"; 1189 1190 opp-19200000 { 1191 opp-hz = /bits/ 64 <19200000>; 1192 required-opps = <&rpmpd_opp_min_svs>; 1193 }; 1194 1195 opp-164000000 { 1196 opp-hz = /bits/ 64 <164000000>; 1197 required-opps = <&rpmpd_opp_low_svs>; 1198 }; 1199 1200 opp-187500000 { 1201 opp-hz = /bits/ 64 <187500000>; 1202 required-opps = <&rpmpd_opp_svs>; 1203 }; 1204 }; 1205 }; 1206 1207 dsi0_phy: phy@5e94400 { 1208 compatible = "qcom,dsi-phy-14nm-2290"; 1209 reg = <0x05e94400 0x100>, 1210 <0x05e94500 0x300>, 1211 <0x05e94800 0x188>; 1212 reg-names = "dsi_phy", 1213 "dsi_phy_lane", 1214 "dsi_pll"; 1215 1216 #clock-cells = <1>; 1217 #phy-cells = <0>; 1218 1219 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 1220 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1221 clock-names = "iface", "ref"; 1222 1223 status = "disabled"; 1224 }; 1225 }; 1226 1227 dispcc: clock-controller@5f00000 { 1228 compatible = "qcom,sm6115-dispcc"; 1229 reg = <0x05f00000 0x20000>; 1230 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 1231 <&sleep_clk>, 1232 <&dsi0_phy 0>, 1233 <&dsi0_phy 1>, 1234 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>; 1235 #clock-cells = <1>; 1236 #reset-cells = <1>; 1237 #power-domain-cells = <1>; 1238 }; 1239 1240 stm@8002000 { 1241 compatible = "arm,coresight-stm", "arm,primecell"; 1242 reg = <0x08002000 0x1000>, 1243 <0x0e280000 0x180000>; 1244 reg-names = "stm-base", "stm-stimulus-base"; 1245 1246 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1247 clock-names = "apb_pclk"; 1248 1249 status = "disabled"; 1250 1251 out-ports { 1252 port { 1253 stm_out: endpoint { 1254 remote-endpoint = <&funnel_in0_in>; 1255 }; 1256 }; 1257 }; 1258 }; 1259 1260 cti0: cti@8010000 { 1261 compatible = "arm,coresight-cti", "arm,primecell"; 1262 reg = <0x08010000 0x1000>; 1263 1264 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1265 clock-names = "apb_pclk"; 1266 1267 status = "disabled"; 1268 }; 1269 1270 cti1: cti@8011000 { 1271 compatible = "arm,coresight-cti", "arm,primecell"; 1272 reg = <0x08011000 0x1000>; 1273 1274 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1275 clock-names = "apb_pclk"; 1276 1277 status = "disabled"; 1278 }; 1279 1280 cti2: cti@8012000 { 1281 compatible = "arm,coresight-cti", "arm,primecell"; 1282 reg = <0x08012000 0x1000>; 1283 1284 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1285 clock-names = "apb_pclk"; 1286 1287 status = "disabled"; 1288 }; 1289 1290 cti3: cti@8013000 { 1291 compatible = "arm,coresight-cti", "arm,primecell"; 1292 reg = <0x08013000 0x1000>; 1293 1294 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1295 clock-names = "apb_pclk"; 1296 1297 status = "disabled"; 1298 }; 1299 1300 cti4: cti@8014000 { 1301 compatible = "arm,coresight-cti", "arm,primecell"; 1302 reg = <0x08014000 0x1000>; 1303 1304 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1305 clock-names = "apb_pclk"; 1306 1307 status = "disabled"; 1308 }; 1309 1310 cti5: cti@8015000 { 1311 compatible = "arm,coresight-cti", "arm,primecell"; 1312 reg = <0x08015000 0x1000>; 1313 1314 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1315 clock-names = "apb_pclk"; 1316 1317 status = "disabled"; 1318 }; 1319 1320 cti6: cti@8016000 { 1321 compatible = "arm,coresight-cti", "arm,primecell"; 1322 reg = <0x08016000 0x1000>; 1323 1324 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1325 clock-names = "apb_pclk"; 1326 1327 status = "disabled"; 1328 }; 1329 1330 cti7: cti@8017000 { 1331 compatible = "arm,coresight-cti", "arm,primecell"; 1332 reg = <0x08017000 0x1000>; 1333 1334 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1335 clock-names = "apb_pclk"; 1336 1337 status = "disabled"; 1338 }; 1339 1340 cti8: cti@8018000 { 1341 compatible = "arm,coresight-cti", "arm,primecell"; 1342 reg = <0x08018000 0x1000>; 1343 1344 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1345 clock-names = "apb_pclk"; 1346 1347 status = "disabled"; 1348 }; 1349 1350 cti9: cti@8019000 { 1351 compatible = "arm,coresight-cti", "arm,primecell"; 1352 reg = <0x08019000 0x1000>; 1353 1354 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1355 clock-names = "apb_pclk"; 1356 1357 status = "disabled"; 1358 }; 1359 1360 cti10: cti@801a000 { 1361 compatible = "arm,coresight-cti", "arm,primecell"; 1362 reg = <0x0801a000 0x1000>; 1363 1364 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1365 clock-names = "apb_pclk"; 1366 1367 status = "disabled"; 1368 }; 1369 1370 cti11: cti@801b000 { 1371 compatible = "arm,coresight-cti", "arm,primecell"; 1372 reg = <0x0801b000 0x1000>; 1373 1374 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1375 clock-names = "apb_pclk"; 1376 1377 status = "disabled"; 1378 }; 1379 1380 cti12: cti@801c000 { 1381 compatible = "arm,coresight-cti", "arm,primecell"; 1382 reg = <0x0801c000 0x1000>; 1383 1384 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1385 clock-names = "apb_pclk"; 1386 1387 status = "disabled"; 1388 }; 1389 1390 cti13: cti@801d000 { 1391 compatible = "arm,coresight-cti", "arm,primecell"; 1392 reg = <0x0801d000 0x1000>; 1393 1394 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1395 clock-names = "apb_pclk"; 1396 1397 status = "disabled"; 1398 }; 1399 1400 cti14: cti@801e000 { 1401 compatible = "arm,coresight-cti", "arm,primecell"; 1402 reg = <0x0801e000 0x1000>; 1403 1404 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1405 clock-names = "apb_pclk"; 1406 1407 status = "disabled"; 1408 }; 1409 1410 cti15: cti@801f000 { 1411 compatible = "arm,coresight-cti", "arm,primecell"; 1412 reg = <0x0801f000 0x1000>; 1413 1414 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1415 clock-names = "apb_pclk"; 1416 1417 status = "disabled"; 1418 }; 1419 1420 replicator@8046000 { 1421 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 1422 reg = <0x08046000 0x1000>; 1423 1424 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1425 clock-names = "apb_pclk"; 1426 1427 status = "disabled"; 1428 1429 out-ports { 1430 port { 1431 replicator_out: endpoint { 1432 remote-endpoint = <&etr_in>; 1433 }; 1434 }; 1435 }; 1436 1437 in-ports { 1438 port { 1439 replicator_in: endpoint { 1440 remote-endpoint = <&etf_out>; 1441 }; 1442 }; 1443 }; 1444 }; 1445 1446 etf@8047000 { 1447 compatible = "arm,coresight-tmc", "arm,primecell"; 1448 reg = <0x08047000 0x1000>; 1449 1450 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1451 clock-names = "apb_pclk"; 1452 1453 status = "disabled"; 1454 1455 in-ports { 1456 port { 1457 etf_in: endpoint { 1458 remote-endpoint = <&merge_funnel_out>; 1459 }; 1460 }; 1461 }; 1462 1463 out-ports { 1464 port { 1465 etf_out: endpoint { 1466 remote-endpoint = <&replicator_in>; 1467 }; 1468 }; 1469 }; 1470 }; 1471 1472 etr@8048000 { 1473 compatible = "arm,coresight-tmc", "arm,primecell"; 1474 reg = <0x08048000 0x1000>; 1475 1476 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1477 clock-names = "apb_pclk"; 1478 1479 status = "disabled"; 1480 1481 in-ports { 1482 port { 1483 etr_in: endpoint { 1484 remote-endpoint = <&replicator_out>; 1485 }; 1486 }; 1487 }; 1488 }; 1489 1490 funnel@8041000 { 1491 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1492 reg = <0x08041000 0x1000>; 1493 1494 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1495 clock-names = "apb_pclk"; 1496 1497 status = "disabled"; 1498 1499 out-ports { 1500 port { 1501 funnel_in0_out: endpoint { 1502 remote-endpoint = <&merge_funnel_in0>; 1503 }; 1504 }; 1505 }; 1506 1507 in-ports { 1508 port { 1509 funnel_in0_in: endpoint { 1510 remote-endpoint = <&stm_out>; 1511 }; 1512 }; 1513 }; 1514 }; 1515 1516 funnel@8042000 { 1517 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1518 reg = <0x08042000 0x1000>; 1519 1520 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1521 clock-names = "apb_pclk"; 1522 1523 status = "disabled"; 1524 1525 out-ports { 1526 port { 1527 funnel_in1_out: endpoint { 1528 remote-endpoint = <&merge_funnel_in1>; 1529 }; 1530 }; 1531 }; 1532 1533 in-ports { 1534 port { 1535 funnel_in1_in: endpoint { 1536 remote-endpoint = <&funnel_apss1_out>; 1537 }; 1538 }; 1539 }; 1540 }; 1541 1542 funnel@8045000 { 1543 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1544 reg = <0x08045000 0x1000>; 1545 1546 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1547 clock-names = "apb_pclk"; 1548 1549 status = "disabled"; 1550 1551 out-ports { 1552 port { 1553 merge_funnel_out: endpoint { 1554 remote-endpoint = <&etf_in>; 1555 }; 1556 }; 1557 }; 1558 1559 in-ports { 1560 #address-cells = <1>; 1561 #size-cells = <0>; 1562 1563 port@0 { 1564 reg = <0>; 1565 merge_funnel_in0: endpoint { 1566 remote-endpoint = <&funnel_in0_out>; 1567 }; 1568 }; 1569 1570 port@1 { 1571 reg = <1>; 1572 merge_funnel_in1: endpoint { 1573 remote-endpoint = <&funnel_in1_out>; 1574 }; 1575 }; 1576 }; 1577 }; 1578 1579 etm@9040000 { 1580 compatible = "arm,coresight-etm4x", "arm,primecell"; 1581 reg = <0x09040000 0x1000>; 1582 1583 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1584 clock-names = "apb_pclk"; 1585 arm,coresight-loses-context-with-cpu; 1586 1587 cpu = <&CPU0>; 1588 1589 status = "disabled"; 1590 1591 out-ports { 1592 port { 1593 etm0_out: endpoint { 1594 remote-endpoint = <&funnel_apss0_in0>; 1595 }; 1596 }; 1597 }; 1598 }; 1599 1600 etm@9140000 { 1601 compatible = "arm,coresight-etm4x", "arm,primecell"; 1602 reg = <0x09140000 0x1000>; 1603 1604 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1605 clock-names = "apb_pclk"; 1606 arm,coresight-loses-context-with-cpu; 1607 1608 cpu = <&CPU1>; 1609 1610 status = "disabled"; 1611 1612 out-ports { 1613 port { 1614 etm1_out: endpoint { 1615 remote-endpoint = <&funnel_apss0_in1>; 1616 }; 1617 }; 1618 }; 1619 }; 1620 1621 etm@9240000 { 1622 compatible = "arm,coresight-etm4x", "arm,primecell"; 1623 reg = <0x09240000 0x1000>; 1624 1625 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1626 clock-names = "apb_pclk"; 1627 arm,coresight-loses-context-with-cpu; 1628 1629 cpu = <&CPU2>; 1630 1631 status = "disabled"; 1632 1633 out-ports { 1634 port { 1635 etm2_out: endpoint { 1636 remote-endpoint = <&funnel_apss0_in2>; 1637 }; 1638 }; 1639 }; 1640 }; 1641 1642 etm@9340000 { 1643 compatible = "arm,coresight-etm4x", "arm,primecell"; 1644 reg = <0x09340000 0x1000>; 1645 1646 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1647 clock-names = "apb_pclk"; 1648 arm,coresight-loses-context-with-cpu; 1649 1650 cpu = <&CPU3>; 1651 1652 status = "disabled"; 1653 1654 out-ports { 1655 port { 1656 etm3_out: endpoint { 1657 remote-endpoint = <&funnel_apss0_in3>; 1658 }; 1659 }; 1660 }; 1661 }; 1662 1663 etm@9440000 { 1664 compatible = "arm,coresight-etm4x", "arm,primecell"; 1665 reg = <0x09440000 0x1000>; 1666 1667 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1668 clock-names = "apb_pclk"; 1669 arm,coresight-loses-context-with-cpu; 1670 1671 cpu = <&CPU4>; 1672 1673 status = "disabled"; 1674 1675 out-ports { 1676 port { 1677 etm4_out: endpoint { 1678 remote-endpoint = <&funnel_apss0_in4>; 1679 }; 1680 }; 1681 }; 1682 }; 1683 1684 etm@9540000 { 1685 compatible = "arm,coresight-etm4x", "arm,primecell"; 1686 reg = <0x09540000 0x1000>; 1687 1688 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1689 clock-names = "apb_pclk"; 1690 arm,coresight-loses-context-with-cpu; 1691 1692 cpu = <&CPU5>; 1693 1694 status = "disabled"; 1695 1696 out-ports { 1697 port { 1698 etm5_out: endpoint { 1699 remote-endpoint = <&funnel_apss0_in5>; 1700 }; 1701 }; 1702 }; 1703 }; 1704 1705 etm@9640000 { 1706 compatible = "arm,coresight-etm4x", "arm,primecell"; 1707 reg = <0x09640000 0x1000>; 1708 1709 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1710 clock-names = "apb_pclk"; 1711 arm,coresight-loses-context-with-cpu; 1712 1713 cpu = <&CPU6>; 1714 1715 status = "disabled"; 1716 1717 out-ports { 1718 port { 1719 etm6_out: endpoint { 1720 remote-endpoint = <&funnel_apss0_in6>; 1721 }; 1722 }; 1723 }; 1724 }; 1725 1726 etm@9740000 { 1727 compatible = "arm,coresight-etm4x", "arm,primecell"; 1728 reg = <0x09740000 0x1000>; 1729 1730 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1731 clock-names = "apb_pclk"; 1732 arm,coresight-loses-context-with-cpu; 1733 1734 cpu = <&CPU7>; 1735 1736 status = "disabled"; 1737 1738 out-ports { 1739 port { 1740 etm7_out: endpoint { 1741 remote-endpoint = <&funnel_apss0_in7>; 1742 }; 1743 }; 1744 }; 1745 }; 1746 1747 funnel@9800000 { 1748 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1749 reg = <0x09800000 0x1000>; 1750 1751 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1752 clock-names = "apb_pclk"; 1753 1754 status = "disabled"; 1755 1756 out-ports { 1757 port { 1758 funnel_apss0_out: endpoint { 1759 remote-endpoint = <&funnel_apss1_in>; 1760 }; 1761 }; 1762 }; 1763 1764 in-ports { 1765 #address-cells = <1>; 1766 #size-cells = <0>; 1767 1768 port@0 { 1769 reg = <0>; 1770 funnel_apss0_in0: endpoint { 1771 remote-endpoint = <&etm0_out>; 1772 }; 1773 }; 1774 1775 port@1 { 1776 reg = <1>; 1777 funnel_apss0_in1: endpoint { 1778 remote-endpoint = <&etm1_out>; 1779 }; 1780 }; 1781 1782 port@2 { 1783 reg = <2>; 1784 funnel_apss0_in2: endpoint { 1785 remote-endpoint = <&etm2_out>; 1786 }; 1787 }; 1788 1789 port@3 { 1790 reg = <3>; 1791 funnel_apss0_in3: endpoint { 1792 remote-endpoint = <&etm3_out>; 1793 }; 1794 }; 1795 1796 port@4 { 1797 reg = <4>; 1798 funnel_apss0_in4: endpoint { 1799 remote-endpoint = <&etm4_out>; 1800 }; 1801 }; 1802 1803 port@5 { 1804 reg = <5>; 1805 funnel_apss0_in5: endpoint { 1806 remote-endpoint = <&etm5_out>; 1807 }; 1808 }; 1809 1810 port@6 { 1811 reg = <6>; 1812 funnel_apss0_in6: endpoint { 1813 remote-endpoint = <&etm6_out>; 1814 }; 1815 }; 1816 1817 port@7 { 1818 reg = <7>; 1819 funnel_apss0_in7: endpoint { 1820 remote-endpoint = <&etm7_out>; 1821 }; 1822 }; 1823 }; 1824 }; 1825 1826 funnel@9810000 { 1827 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1828 reg = <0x09810000 0x1000>; 1829 1830 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1831 clock-names = "apb_pclk"; 1832 1833 status = "disabled"; 1834 1835 out-ports { 1836 port { 1837 funnel_apss1_out: endpoint { 1838 remote-endpoint = <&funnel_in1_in>; 1839 }; 1840 }; 1841 }; 1842 1843 in-ports { 1844 port { 1845 funnel_apss1_in: endpoint { 1846 remote-endpoint = <&funnel_apss0_out>; 1847 }; 1848 }; 1849 }; 1850 }; 1851 1852 apps_smmu: iommu@c600000 { 1853 compatible = "qcom,sm6115-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 1854 reg = <0x0c600000 0x80000>; 1855 #iommu-cells = <2>; 1856 #global-interrupts = <1>; 1857 1858 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 1859 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 1860 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 1861 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 1862 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 1863 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 1864 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 1865 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 1866 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 1867 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 1868 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 1869 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 1870 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 1871 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 1872 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 1873 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 1874 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 1875 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 1876 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 1877 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 1878 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 1879 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 1880 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 1881 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1882 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 1883 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 1884 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 1885 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 1886 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 1887 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1888 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1889 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1890 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 1891 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1892 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1893 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1894 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1895 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1896 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1897 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1898 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 1899 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 1900 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 1901 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 1902 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 1903 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 1904 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1905 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 1906 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1907 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 1908 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 1909 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 1910 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 1911 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 1912 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 1913 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1914 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 1915 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1916 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1917 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1918 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1919 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 1920 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 1921 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 1922 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 1923 }; 1924 1925 wifi: wifi@c800000 { 1926 compatible = "qcom,wcn3990-wifi"; 1927 reg = <0x0c800000 0x800000>; 1928 reg-names = "membase"; 1929 memory-region = <&wlan_msa_mem>; 1930 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, 1931 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, 1932 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, 1933 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>, 1934 <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>, 1935 <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>, 1936 <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>, 1937 <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>, 1938 <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>, 1939 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>, 1940 <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, 1941 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1942 iommus = <&apps_smmu 0x1a0 0x1>; 1943 qcom,msa-fixed-perm; 1944 status = "disabled"; 1945 }; 1946 1947 apcs_glb: mailbox@f111000 { 1948 compatible = "qcom,sm6115-apcs-hmss-global"; 1949 reg = <0x0f111000 0x1000>; 1950 1951 #mbox-cells = <1>; 1952 }; 1953 1954 timer@f120000 { 1955 compatible = "arm,armv7-timer-mem"; 1956 reg = <0x0f120000 0x1000>; 1957 #address-cells = <1>; 1958 #size-cells = <1>; 1959 ranges; 1960 clock-frequency = <19200000>; 1961 1962 frame@f121000 { 1963 reg = <0x0f121000 0x1000>, <0x0f122000 0x1000>; 1964 frame-number = <0>; 1965 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1966 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 1967 }; 1968 1969 frame@f123000 { 1970 reg = <0x0f123000 0x1000>; 1971 frame-number = <1>; 1972 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1973 status = "disabled"; 1974 }; 1975 1976 frame@f124000 { 1977 reg = <0x0f124000 0x1000>; 1978 frame-number = <2>; 1979 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1980 status = "disabled"; 1981 }; 1982 1983 frame@f125000 { 1984 reg = <0x0f125000 0x1000>; 1985 frame-number = <3>; 1986 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1987 status = "disabled"; 1988 }; 1989 1990 frame@f126000 { 1991 reg = <0x0f126000 0x1000>; 1992 frame-number = <4>; 1993 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1994 status = "disabled"; 1995 }; 1996 1997 frame@f127000 { 1998 reg = <0x0f127000 0x1000>; 1999 frame-number = <5>; 2000 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 2001 status = "disabled"; 2002 }; 2003 2004 frame@f128000 { 2005 reg = <0x0f128000 0x1000>; 2006 frame-number = <6>; 2007 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 2008 status = "disabled"; 2009 }; 2010 }; 2011 2012 intc: interrupt-controller@f200000 { 2013 compatible = "arm,gic-v3"; 2014 reg = <0x0f200000 0x10000>, <0x0f300000 0x100000>; 2015 #interrupt-cells = <3>; 2016 interrupt-controller; 2017 interrupt-parent = <&intc>; 2018 #redistributor-regions = <1>; 2019 redistributor-stride = <0x0 0x20000>; 2020 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 2021 }; 2022 2023 cpufreq_hw: cpufreq@f521000 { 2024 compatible = "qcom,cpufreq-hw"; 2025 reg = <0x0f521000 0x1000>, <0x0f523000 0x1000>; 2026 2027 reg-names = "freq-domain0", "freq-domain1"; 2028 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>; 2029 clock-names = "xo", "alternate"; 2030 2031 #freq-domain-cells = <1>; 2032 }; 2033 }; 2034 2035 thermal-zones { 2036 mapss-thermal { 2037 polling-delay-passive = <0>; 2038 polling-delay = <0>; 2039 thermal-sensors = <&tsens0 0>; 2040 2041 trips { 2042 trip-point0 { 2043 temperature = <115000>; 2044 hysteresis = <5000>; 2045 type = "passive"; 2046 }; 2047 2048 trip-point1 { 2049 temperature = <125000>; 2050 hysteresis = <1000>; 2051 type = "passive"; 2052 }; 2053 }; 2054 }; 2055 2056 cdsp-hvx-thermal { 2057 polling-delay-passive = <0>; 2058 polling-delay = <0>; 2059 thermal-sensors = <&tsens0 1>; 2060 2061 trips { 2062 trip-point0 { 2063 temperature = <115000>; 2064 hysteresis = <5000>; 2065 type = "passive"; 2066 }; 2067 2068 trip-point1 { 2069 temperature = <125000>; 2070 hysteresis = <1000>; 2071 type = "passive"; 2072 }; 2073 }; 2074 }; 2075 2076 wlan-thermal { 2077 polling-delay-passive = <0>; 2078 polling-delay = <0>; 2079 thermal-sensors = <&tsens0 2>; 2080 2081 trips { 2082 trip-point0 { 2083 temperature = <115000>; 2084 hysteresis = <5000>; 2085 type = "passive"; 2086 }; 2087 2088 trip-point1 { 2089 temperature = <125000>; 2090 hysteresis = <1000>; 2091 type = "passive"; 2092 }; 2093 }; 2094 }; 2095 2096 camera-thermal { 2097 polling-delay-passive = <0>; 2098 polling-delay = <0>; 2099 thermal-sensors = <&tsens0 3>; 2100 2101 trips { 2102 trip-point0 { 2103 temperature = <115000>; 2104 hysteresis = <5000>; 2105 type = "passive"; 2106 }; 2107 2108 trip-point1 { 2109 temperature = <125000>; 2110 hysteresis = <1000>; 2111 type = "passive"; 2112 }; 2113 }; 2114 }; 2115 2116 video-thermal { 2117 polling-delay-passive = <0>; 2118 polling-delay = <0>; 2119 thermal-sensors = <&tsens0 4>; 2120 2121 trips { 2122 trip-point0 { 2123 temperature = <115000>; 2124 hysteresis = <5000>; 2125 type = "passive"; 2126 }; 2127 2128 trip-point1 { 2129 temperature = <125000>; 2130 hysteresis = <1000>; 2131 type = "passive"; 2132 }; 2133 }; 2134 }; 2135 2136 modem1-thermal { 2137 polling-delay-passive = <0>; 2138 polling-delay = <0>; 2139 thermal-sensors = <&tsens0 5>; 2140 2141 trips { 2142 trip-point0 { 2143 temperature = <115000>; 2144 hysteresis = <5000>; 2145 type = "passive"; 2146 }; 2147 2148 trip-point1 { 2149 temperature = <125000>; 2150 hysteresis = <1000>; 2151 type = "passive"; 2152 }; 2153 }; 2154 }; 2155 2156 cpu4-thermal { 2157 polling-delay-passive = <0>; 2158 polling-delay = <0>; 2159 thermal-sensors = <&tsens0 6>; 2160 2161 trips { 2162 cpu4_alert0: trip-point0 { 2163 temperature = <90000>; 2164 hysteresis = <2000>; 2165 type = "passive"; 2166 }; 2167 2168 cpu4_alert1: trip-point1 { 2169 temperature = <95000>; 2170 hysteresis = <2000>; 2171 type = "passive"; 2172 }; 2173 2174 cpu4_crit: cpu_crit { 2175 temperature = <110000>; 2176 hysteresis = <1000>; 2177 type = "critical"; 2178 }; 2179 }; 2180 }; 2181 2182 cpu5-thermal { 2183 polling-delay-passive = <0>; 2184 polling-delay = <0>; 2185 thermal-sensors = <&tsens0 7>; 2186 2187 trips { 2188 cpu5_alert0: trip-point0 { 2189 temperature = <90000>; 2190 hysteresis = <2000>; 2191 type = "passive"; 2192 }; 2193 2194 cpu5_alert1: trip-point1 { 2195 temperature = <95000>; 2196 hysteresis = <2000>; 2197 type = "passive"; 2198 }; 2199 2200 cpu5_crit: cpu_crit { 2201 temperature = <110000>; 2202 hysteresis = <1000>; 2203 type = "critical"; 2204 }; 2205 }; 2206 }; 2207 2208 cpu6-thermal { 2209 polling-delay-passive = <0>; 2210 polling-delay = <0>; 2211 thermal-sensors = <&tsens0 8>; 2212 2213 trips { 2214 cpu6_alert0: trip-point0 { 2215 temperature = <90000>; 2216 hysteresis = <2000>; 2217 type = "passive"; 2218 }; 2219 2220 cpu6_alert1: trip-point1 { 2221 temperature = <95000>; 2222 hysteresis = <2000>; 2223 type = "passive"; 2224 }; 2225 2226 cpu6_crit: cpu_crit { 2227 temperature = <110000>; 2228 hysteresis = <1000>; 2229 type = "critical"; 2230 }; 2231 }; 2232 }; 2233 2234 cpu7-thermal { 2235 polling-delay-passive = <0>; 2236 polling-delay = <0>; 2237 thermal-sensors = <&tsens0 9>; 2238 2239 trips { 2240 cpu7_alert0: trip-point0 { 2241 temperature = <90000>; 2242 hysteresis = <2000>; 2243 type = "passive"; 2244 }; 2245 2246 cpu7_alert1: trip-point1 { 2247 temperature = <95000>; 2248 hysteresis = <2000>; 2249 type = "passive"; 2250 }; 2251 2252 cpu7_crit: cpu_crit { 2253 temperature = <110000>; 2254 hysteresis = <1000>; 2255 type = "critical"; 2256 }; 2257 }; 2258 }; 2259 2260 cpu45-thermal { 2261 polling-delay-passive = <0>; 2262 polling-delay = <0>; 2263 thermal-sensors = <&tsens0 10>; 2264 2265 trips { 2266 cpu45_alert0: trip-point0 { 2267 temperature = <90000>; 2268 hysteresis = <2000>; 2269 type = "passive"; 2270 }; 2271 2272 cpu45_alert1: trip-point1 { 2273 temperature = <95000>; 2274 hysteresis = <2000>; 2275 type = "passive"; 2276 }; 2277 2278 cpu45_crit: cpu_crit { 2279 temperature = <110000>; 2280 hysteresis = <1000>; 2281 type = "critical"; 2282 }; 2283 }; 2284 }; 2285 2286 cpu67-thermal { 2287 polling-delay-passive = <0>; 2288 polling-delay = <0>; 2289 thermal-sensors = <&tsens0 11>; 2290 2291 trips { 2292 cpu67_alert0: trip-point0 { 2293 temperature = <90000>; 2294 hysteresis = <2000>; 2295 type = "passive"; 2296 }; 2297 2298 cpu67_alert1: trip-point1 { 2299 temperature = <95000>; 2300 hysteresis = <2000>; 2301 type = "passive"; 2302 }; 2303 2304 cpu67_crit: cpu_crit { 2305 temperature = <110000>; 2306 hysteresis = <1000>; 2307 type = "critical"; 2308 }; 2309 }; 2310 }; 2311 2312 cpu0123-thermal { 2313 polling-delay-passive = <0>; 2314 polling-delay = <0>; 2315 thermal-sensors = <&tsens0 12>; 2316 2317 trips { 2318 cpu0123_alert0: trip-point0 { 2319 temperature = <90000>; 2320 hysteresis = <2000>; 2321 type = "passive"; 2322 }; 2323 2324 cpu0123_alert1: trip-point1 { 2325 temperature = <95000>; 2326 hysteresis = <2000>; 2327 type = "passive"; 2328 }; 2329 2330 cpu0123_crit: cpu_crit { 2331 temperature = <110000>; 2332 hysteresis = <1000>; 2333 type = "critical"; 2334 }; 2335 }; 2336 }; 2337 2338 modem0-thermal { 2339 polling-delay-passive = <0>; 2340 polling-delay = <0>; 2341 thermal-sensors = <&tsens0 13>; 2342 2343 trips { 2344 trip-point0 { 2345 temperature = <115000>; 2346 hysteresis = <5000>; 2347 type = "passive"; 2348 }; 2349 2350 trip-point1 { 2351 temperature = <125000>; 2352 hysteresis = <1000>; 2353 type = "passive"; 2354 }; 2355 }; 2356 }; 2357 2358 display-thermal { 2359 polling-delay-passive = <0>; 2360 polling-delay = <0>; 2361 thermal-sensors = <&tsens0 14>; 2362 2363 trips { 2364 trip-point0 { 2365 temperature = <115000>; 2366 hysteresis = <5000>; 2367 type = "passive"; 2368 }; 2369 2370 trip-point1 { 2371 temperature = <125000>; 2372 hysteresis = <1000>; 2373 type = "passive"; 2374 }; 2375 }; 2376 }; 2377 2378 gpu-thermal { 2379 polling-delay-passive = <0>; 2380 polling-delay = <0>; 2381 thermal-sensors = <&tsens0 15>; 2382 2383 trips { 2384 trip-point0 { 2385 temperature = <115000>; 2386 hysteresis = <5000>; 2387 type = "passive"; 2388 }; 2389 2390 trip-point1 { 2391 temperature = <125000>; 2392 hysteresis = <1000>; 2393 type = "passive"; 2394 }; 2395 }; 2396 }; 2397 }; 2398 2399 timer { 2400 compatible = "arm,armv8-timer"; 2401 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2402 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2403 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2404 <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 2405 }; 2406}; 2407