1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright (c) 2021, Iskren Chernev <iskren.chernev@gmail.com> 4 */ 5 6#include <dt-bindings/clock/qcom,gcc-sm6115.h> 7#include <dt-bindings/clock/qcom,sm6115-dispcc.h> 8#include <dt-bindings/clock/qcom,rpmcc.h> 9#include <dt-bindings/dma/qcom-gpi.h> 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/power/qcom-rpmpd.h> 13 14/ { 15 interrupt-parent = <&intc>; 16 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 chosen { }; 21 22 clocks { 23 xo_board: xo-board { 24 compatible = "fixed-clock"; 25 #clock-cells = <0>; 26 }; 27 28 sleep_clk: sleep-clk { 29 compatible = "fixed-clock"; 30 #clock-cells = <0>; 31 }; 32 }; 33 34 cpus { 35 #address-cells = <2>; 36 #size-cells = <0>; 37 38 CPU0: cpu@0 { 39 device_type = "cpu"; 40 compatible = "qcom,kryo260"; 41 reg = <0x0 0x0>; 42 capacity-dmips-mhz = <1024>; 43 dynamic-power-coefficient = <100>; 44 enable-method = "psci"; 45 next-level-cache = <&L2_0>; 46 qcom,freq-domain = <&cpufreq_hw 0>; 47 L2_0: l2-cache { 48 compatible = "cache"; 49 cache-level = <2>; 50 }; 51 }; 52 53 CPU1: cpu@1 { 54 device_type = "cpu"; 55 compatible = "qcom,kryo260"; 56 reg = <0x0 0x1>; 57 capacity-dmips-mhz = <1024>; 58 dynamic-power-coefficient = <100>; 59 enable-method = "psci"; 60 next-level-cache = <&L2_0>; 61 qcom,freq-domain = <&cpufreq_hw 0>; 62 }; 63 64 CPU2: cpu@2 { 65 device_type = "cpu"; 66 compatible = "qcom,kryo260"; 67 reg = <0x0 0x2>; 68 capacity-dmips-mhz = <1024>; 69 dynamic-power-coefficient = <100>; 70 enable-method = "psci"; 71 next-level-cache = <&L2_0>; 72 qcom,freq-domain = <&cpufreq_hw 0>; 73 }; 74 75 CPU3: cpu@3 { 76 device_type = "cpu"; 77 compatible = "qcom,kryo260"; 78 reg = <0x0 0x3>; 79 capacity-dmips-mhz = <1024>; 80 dynamic-power-coefficient = <100>; 81 enable-method = "psci"; 82 next-level-cache = <&L2_0>; 83 qcom,freq-domain = <&cpufreq_hw 0>; 84 }; 85 86 CPU4: cpu@100 { 87 device_type = "cpu"; 88 compatible = "qcom,kryo260"; 89 reg = <0x0 0x100>; 90 enable-method = "psci"; 91 capacity-dmips-mhz = <1638>; 92 dynamic-power-coefficient = <282>; 93 next-level-cache = <&L2_1>; 94 qcom,freq-domain = <&cpufreq_hw 1>; 95 L2_1: l2-cache { 96 compatible = "cache"; 97 cache-level = <2>; 98 }; 99 }; 100 101 CPU5: cpu@101 { 102 device_type = "cpu"; 103 compatible = "qcom,kryo260"; 104 reg = <0x0 0x101>; 105 capacity-dmips-mhz = <1638>; 106 dynamic-power-coefficient = <282>; 107 enable-method = "psci"; 108 next-level-cache = <&L2_1>; 109 qcom,freq-domain = <&cpufreq_hw 1>; 110 }; 111 112 CPU6: cpu@102 { 113 device_type = "cpu"; 114 compatible = "qcom,kryo260"; 115 reg = <0x0 0x102>; 116 capacity-dmips-mhz = <1638>; 117 dynamic-power-coefficient = <282>; 118 enable-method = "psci"; 119 next-level-cache = <&L2_1>; 120 qcom,freq-domain = <&cpufreq_hw 1>; 121 }; 122 123 CPU7: cpu@103 { 124 device_type = "cpu"; 125 compatible = "qcom,kryo260"; 126 reg = <0x0 0x103>; 127 capacity-dmips-mhz = <1638>; 128 dynamic-power-coefficient = <282>; 129 enable-method = "psci"; 130 next-level-cache = <&L2_1>; 131 qcom,freq-domain = <&cpufreq_hw 1>; 132 }; 133 134 cpu-map { 135 cluster0 { 136 core0 { 137 cpu = <&CPU0>; 138 }; 139 140 core1 { 141 cpu = <&CPU1>; 142 }; 143 144 core2 { 145 cpu = <&CPU2>; 146 }; 147 148 core3 { 149 cpu = <&CPU3>; 150 }; 151 }; 152 153 cluster1 { 154 core0 { 155 cpu = <&CPU4>; 156 }; 157 158 core1 { 159 cpu = <&CPU5>; 160 }; 161 162 core2 { 163 cpu = <&CPU6>; 164 }; 165 166 core3 { 167 cpu = <&CPU7>; 168 }; 169 }; 170 }; 171 }; 172 173 firmware { 174 scm: scm { 175 compatible = "qcom,scm-sm6115", "qcom,scm"; 176 #reset-cells = <1>; 177 }; 178 }; 179 180 memory@80000000 { 181 device_type = "memory"; 182 /* We expect the bootloader to fill in the size */ 183 reg = <0 0x80000000 0 0>; 184 }; 185 186 pmu { 187 compatible = "arm,armv8-pmuv3"; 188 interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>; 189 }; 190 191 psci { 192 compatible = "arm,psci-1.0"; 193 method = "smc"; 194 }; 195 196 reserved_memory: reserved-memory { 197 #address-cells = <2>; 198 #size-cells = <2>; 199 ranges; 200 201 hyp_mem: memory@45700000 { 202 reg = <0x0 0x45700000 0x0 0x600000>; 203 no-map; 204 }; 205 206 xbl_aop_mem: memory@45e00000 { 207 reg = <0x0 0x45e00000 0x0 0x140000>; 208 no-map; 209 }; 210 211 sec_apps_mem: memory@45fff000 { 212 reg = <0x0 0x45fff000 0x0 0x1000>; 213 no-map; 214 }; 215 216 smem_mem: memory@46000000 { 217 compatible = "qcom,smem"; 218 reg = <0x0 0x46000000 0x0 0x200000>; 219 no-map; 220 221 hwlocks = <&tcsr_mutex 3>; 222 qcom,rpm-msg-ram = <&rpm_msg_ram>; 223 }; 224 225 cdsp_sec_mem: memory@46200000 { 226 reg = <0x0 0x46200000 0x0 0x1e00000>; 227 no-map; 228 }; 229 230 pil_modem_mem: memory@4ab00000 { 231 reg = <0x0 0x4ab00000 0x0 0x6900000>; 232 no-map; 233 }; 234 235 pil_video_mem: memory@51400000 { 236 reg = <0x0 0x51400000 0x0 0x500000>; 237 no-map; 238 }; 239 240 wlan_msa_mem: memory@51900000 { 241 reg = <0x0 0x51900000 0x0 0x100000>; 242 no-map; 243 }; 244 245 pil_cdsp_mem: memory@51a00000 { 246 reg = <0x0 0x51a00000 0x0 0x1e00000>; 247 no-map; 248 }; 249 250 pil_adsp_mem: memory@53800000 { 251 reg = <0x0 0x53800000 0x0 0x2800000>; 252 no-map; 253 }; 254 255 pil_ipa_fw_mem: memory@56100000 { 256 reg = <0x0 0x56100000 0x0 0x10000>; 257 no-map; 258 }; 259 260 pil_ipa_gsi_mem: memory@56110000 { 261 reg = <0x0 0x56110000 0x0 0x5000>; 262 no-map; 263 }; 264 265 pil_gpu_mem: memory@56115000 { 266 reg = <0x0 0x56115000 0x0 0x2000>; 267 no-map; 268 }; 269 270 cont_splash_memory: memory@5c000000 { 271 reg = <0x0 0x5c000000 0x0 0x00f00000>; 272 no-map; 273 }; 274 275 dfps_data_memory: memory@5cf00000 { 276 reg = <0x0 0x5cf00000 0x0 0x0100000>; 277 no-map; 278 }; 279 280 removed_mem: memory@60000000 { 281 reg = <0x0 0x60000000 0x0 0x3900000>; 282 no-map; 283 }; 284 }; 285 286 rpm-glink { 287 compatible = "qcom,glink-rpm"; 288 289 interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>; 290 qcom,rpm-msg-ram = <&rpm_msg_ram>; 291 mboxes = <&apcs_glb 0>; 292 293 rpm_requests: rpm-requests { 294 compatible = "qcom,rpm-sm6115"; 295 qcom,glink-channels = "rpm_requests"; 296 297 rpmcc: clock-controller { 298 compatible = "qcom,rpmcc-sm6115", "qcom,rpmcc"; 299 clocks = <&xo_board>; 300 clock-names = "xo"; 301 #clock-cells = <1>; 302 }; 303 304 rpmpd: power-controller { 305 compatible = "qcom,sm6115-rpmpd"; 306 #power-domain-cells = <1>; 307 operating-points-v2 = <&rpmpd_opp_table>; 308 309 rpmpd_opp_table: opp-table { 310 compatible = "operating-points-v2"; 311 312 rpmpd_opp_min_svs: opp1 { 313 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 314 }; 315 316 rpmpd_opp_low_svs: opp2 { 317 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 318 }; 319 320 rpmpd_opp_svs: opp3 { 321 opp-level = <RPM_SMD_LEVEL_SVS>; 322 }; 323 324 rpmpd_opp_svs_plus: opp4 { 325 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 326 }; 327 328 rpmpd_opp_nom: opp5 { 329 opp-level = <RPM_SMD_LEVEL_NOM>; 330 }; 331 332 rpmpd_opp_nom_plus: opp6 { 333 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 334 }; 335 336 rpmpd_opp_turbo: opp7 { 337 opp-level = <RPM_SMD_LEVEL_TURBO>; 338 }; 339 340 rpmpd_opp_turbo_plus: opp8 { 341 opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>; 342 }; 343 }; 344 }; 345 }; 346 }; 347 348 smp2p-adsp { 349 compatible = "qcom,smp2p"; 350 qcom,smem = <443>, <429>; 351 352 interrupts = <GIC_SPI 279 IRQ_TYPE_EDGE_RISING>; 353 354 mboxes = <&apcs_glb 10>; 355 356 qcom,local-pid = <0>; 357 qcom,remote-pid = <2>; 358 359 adsp_smp2p_out: master-kernel { 360 qcom,entry-name = "master-kernel"; 361 #qcom,smem-state-cells = <1>; 362 }; 363 364 adsp_smp2p_in: slave-kernel { 365 qcom,entry-name = "slave-kernel"; 366 367 interrupt-controller; 368 #interrupt-cells = <2>; 369 }; 370 }; 371 372 smp2p-cdsp { 373 compatible = "qcom,smp2p"; 374 qcom,smem = <94>, <432>; 375 376 interrupts = <GIC_SPI 263 IRQ_TYPE_EDGE_RISING>; 377 378 mboxes = <&apcs_glb 30>; 379 380 qcom,local-pid = <0>; 381 qcom,remote-pid = <5>; 382 383 cdsp_smp2p_out: master-kernel { 384 qcom,entry-name = "master-kernel"; 385 #qcom,smem-state-cells = <1>; 386 }; 387 388 cdsp_smp2p_in: slave-kernel { 389 qcom,entry-name = "slave-kernel"; 390 391 interrupt-controller; 392 #interrupt-cells = <2>; 393 }; 394 }; 395 396 smp2p-mpss { 397 compatible = "qcom,smp2p"; 398 qcom,smem = <435>, <428>; 399 400 interrupts = <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>; 401 402 mboxes = <&apcs_glb 14>; 403 404 qcom,local-pid = <0>; 405 qcom,remote-pid = <1>; 406 407 modem_smp2p_out: master-kernel { 408 qcom,entry-name = "master-kernel"; 409 #qcom,smem-state-cells = <1>; 410 }; 411 412 modem_smp2p_in: slave-kernel { 413 qcom,entry-name = "slave-kernel"; 414 415 interrupt-controller; 416 #interrupt-cells = <2>; 417 }; 418 }; 419 420 soc: soc@0 { 421 compatible = "simple-bus"; 422 #address-cells = <2>; 423 #size-cells = <2>; 424 ranges = <0 0 0 0 0x10 0>; 425 dma-ranges = <0 0 0 0 0x10 0>; 426 427 tcsr_mutex: hwlock@340000 { 428 compatible = "qcom,tcsr-mutex"; 429 reg = <0x0 0x00340000 0x0 0x20000>; 430 #hwlock-cells = <1>; 431 }; 432 433 tlmm: pinctrl@500000 { 434 compatible = "qcom,sm6115-tlmm"; 435 reg = <0x0 0x00500000 0x0 0x400000>, 436 <0x0 0x00900000 0x0 0x400000>, 437 <0x0 0x00d00000 0x0 0x400000>; 438 reg-names = "west", "south", "east"; 439 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 440 gpio-controller; 441 gpio-ranges = <&tlmm 0 0 114>; /* GPIOs + ufs_reset */ 442 #gpio-cells = <2>; 443 interrupt-controller; 444 #interrupt-cells = <2>; 445 446 qup_i2c0_default: qup-i2c0-default-state { 447 pins = "gpio0", "gpio1"; 448 function = "qup0"; 449 drive-strength = <2>; 450 bias-pull-up; 451 }; 452 453 qup_i2c1_default: qup-i2c1-default-state { 454 pins = "gpio4", "gpio5"; 455 function = "qup1"; 456 drive-strength = <2>; 457 bias-pull-up; 458 }; 459 460 qup_i2c2_default: qup-i2c2-default-state { 461 pins = "gpio6", "gpio7"; 462 function = "qup2"; 463 drive-strength = <2>; 464 bias-pull-up; 465 }; 466 467 qup_i2c3_default: qup-i2c3-default-state { 468 pins = "gpio8", "gpio9"; 469 function = "qup3"; 470 drive-strength = <2>; 471 bias-pull-up; 472 }; 473 474 qup_i2c4_default: qup-i2c4-default-state { 475 pins = "gpio12", "gpio13"; 476 function = "qup4"; 477 drive-strength = <2>; 478 bias-pull-up; 479 }; 480 481 qup_i2c5_default: qup-i2c5-default-state { 482 pins = "gpio14", "gpio15"; 483 function = "qup5"; 484 drive-strength = <2>; 485 bias-pull-up; 486 }; 487 488 qup_spi0_default: qup-spi0-default-state { 489 pins = "gpio0", "gpio1","gpio2", "gpio3"; 490 function = "qup0"; 491 drive-strength = <2>; 492 bias-pull-up; 493 }; 494 495 qup_spi1_default: qup-spi1-default-state { 496 pins = "gpio4", "gpio5", "gpio69", "gpio70"; 497 function = "qup1"; 498 drive-strength = <2>; 499 bias-pull-up; 500 }; 501 502 qup_spi2_default: qup-spi2-default-state { 503 pins = "gpio6", "gpio7", "gpio71", "gpio80"; 504 function = "qup2"; 505 drive-strength = <2>; 506 bias-pull-up; 507 }; 508 509 qup_spi3_default: qup-spi3-default-state { 510 pins = "gpio8", "gpio9", "gpio10", "gpio11"; 511 function = "qup3"; 512 drive-strength = <2>; 513 bias-pull-up; 514 }; 515 516 qup_spi4_default: qup-spi4-default-state { 517 pins = "gpio12", "gpio13", "gpio96", "gpio97"; 518 function = "qup4"; 519 drive-strength = <2>; 520 bias-pull-up; 521 }; 522 523 qup_spi5_default: qup-spi5-default-state { 524 pins = "gpio14", "gpio15", "gpio16", "gpio17"; 525 function = "qup5"; 526 drive-strength = <2>; 527 bias-pull-up; 528 }; 529 530 sdc1_state_on: sdc1-on-state { 531 clk-pins { 532 pins = "sdc1_clk"; 533 bias-disable; 534 drive-strength = <16>; 535 }; 536 537 cmd-pins { 538 pins = "sdc1_cmd"; 539 bias-pull-up; 540 drive-strength = <10>; 541 }; 542 543 data-pins { 544 pins = "sdc1_data"; 545 bias-pull-up; 546 drive-strength = <10>; 547 }; 548 549 rclk-pins { 550 pins = "sdc1_rclk"; 551 bias-pull-down; 552 }; 553 }; 554 555 sdc1_state_off: sdc1-off-state { 556 clk-pins { 557 pins = "sdc1_clk"; 558 bias-disable; 559 drive-strength = <2>; 560 }; 561 562 cmd-pins { 563 pins = "sdc1_cmd"; 564 bias-pull-up; 565 drive-strength = <2>; 566 }; 567 568 data-pins { 569 pins = "sdc1_data"; 570 bias-pull-up; 571 drive-strength = <2>; 572 }; 573 574 rclk-pins { 575 pins = "sdc1_rclk"; 576 bias-pull-down; 577 }; 578 }; 579 580 sdc2_state_on: sdc2-on-state { 581 clk-pins { 582 pins = "sdc2_clk"; 583 bias-disable; 584 drive-strength = <16>; 585 }; 586 587 cmd-pins { 588 pins = "sdc2_cmd"; 589 bias-pull-up; 590 drive-strength = <10>; 591 }; 592 593 data-pins { 594 pins = "sdc2_data"; 595 bias-pull-up; 596 drive-strength = <10>; 597 }; 598 599 sd-cd-pins { 600 pins = "gpio88"; 601 function = "gpio"; 602 bias-pull-up; 603 drive-strength = <2>; 604 }; 605 }; 606 607 sdc2_state_off: sdc2-off-state { 608 clk-pins { 609 pins = "sdc2_clk"; 610 bias-disable; 611 drive-strength = <2>; 612 }; 613 614 cmd-pins { 615 pins = "sdc2_cmd"; 616 bias-pull-up; 617 drive-strength = <2>; 618 }; 619 620 data-pins { 621 pins = "sdc2_data"; 622 bias-pull-up; 623 drive-strength = <2>; 624 }; 625 626 sd-cd-pins { 627 pins = "gpio88"; 628 function = "gpio"; 629 bias-disable; 630 drive-strength = <2>; 631 }; 632 }; 633 }; 634 635 gcc: clock-controller@1400000 { 636 compatible = "qcom,gcc-sm6115"; 637 reg = <0x0 0x01400000 0x0 0x1f0000>; 638 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>; 639 clock-names = "bi_tcxo", "sleep_clk"; 640 #clock-cells = <1>; 641 #reset-cells = <1>; 642 #power-domain-cells = <1>; 643 }; 644 645 usb_1_hsphy: phy@1613000 { 646 compatible = "qcom,sm6115-qusb2-phy"; 647 reg = <0x0 0x01613000 0x0 0x180>; 648 #phy-cells = <0>; 649 650 clocks = <&gcc GCC_AHB2PHY_USB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>; 651 clock-names = "cfg_ahb", "ref"; 652 653 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 654 nvmem-cells = <&qusb2_hstx_trim>; 655 656 status = "disabled"; 657 }; 658 659 qfprom@1b40000 { 660 compatible = "qcom,sm6115-qfprom", "qcom,qfprom"; 661 reg = <0x0 0x01b40000 0x0 0x7000>; 662 #address-cells = <1>; 663 #size-cells = <1>; 664 665 qusb2_hstx_trim: hstx-trim@25b { 666 reg = <0x25b 0x1>; 667 bits = <1 4>; 668 }; 669 }; 670 671 rng: rng@1b53000 { 672 compatible = "qcom,prng-ee"; 673 reg = <0x0 0x01b53000 0x0 0x1000>; 674 clocks = <&gcc GCC_PRNG_AHB_CLK>; 675 clock-names = "core"; 676 }; 677 678 spmi_bus: spmi@1c40000 { 679 compatible = "qcom,spmi-pmic-arb"; 680 reg = <0x0 0x01c40000 0x0 0x1100>, 681 <0x0 0x01e00000 0x0 0x2000000>, 682 <0x0 0x03e00000 0x0 0x100000>, 683 <0x0 0x03f00000 0x0 0xa0000>, 684 <0x0 0x01c0a000 0x0 0x26000>; 685 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 686 interrupt-names = "periph_irq"; 687 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 688 qcom,ee = <0>; 689 qcom,channel = <0>; 690 #address-cells = <2>; 691 #size-cells = <0>; 692 interrupt-controller; 693 #interrupt-cells = <4>; 694 }; 695 696 tsens0: thermal-sensor@4410000 { 697 compatible = "qcom,sm6115-tsens", "qcom,tsens-v2"; 698 reg = <0x0 0x04411000 0x0 0x1ff>, /* TM */ 699 <0x0 0x04410000 0x0 0x8>; /* SROT */ 700 #qcom,sensors = <16>; 701 interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 702 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 703 interrupt-names = "uplow", "critical"; 704 #thermal-sensor-cells = <1>; 705 }; 706 707 rpm_msg_ram: sram@45f0000 { 708 compatible = "qcom,rpm-msg-ram"; 709 reg = <0x0 0x045f0000 0x0 0x7000>; 710 }; 711 712 sram@4690000 { 713 compatible = "qcom,rpm-stats"; 714 reg = <0x0 0x04690000 0x0 0x10000>; 715 }; 716 717 sdhc_1: mmc@4744000 { 718 compatible = "qcom,sm6115-sdhci", "qcom,sdhci-msm-v5"; 719 reg = <0x0 0x04744000 0x0 0x1000>, 720 <0x0 0x04745000 0x0 0x1000>, 721 <0x0 0x04748000 0x0 0x8000>; 722 reg-names = "hc", "cqhci", "ice"; 723 724 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, 725 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 726 interrupt-names = "hc_irq", "pwr_irq"; 727 728 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 729 <&gcc GCC_SDCC1_APPS_CLK>, 730 <&rpmcc RPM_SMD_XO_CLK_SRC>, 731 <&gcc GCC_SDCC1_ICE_CORE_CLK>; 732 clock-names = "iface", "core", "xo", "ice"; 733 734 pinctrl-0 = <&sdc1_state_on>; 735 pinctrl-1 = <&sdc1_state_off>; 736 pinctrl-names = "default", "sleep"; 737 738 bus-width = <8>; 739 status = "disabled"; 740 }; 741 742 sdhc_2: mmc@4784000 { 743 compatible = "qcom,sm6115-sdhci", "qcom,sdhci-msm-v5"; 744 reg = <0x0 0x04784000 0x0 0x1000>; 745 reg-names = "hc"; 746 747 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 748 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 749 interrupt-names = "hc_irq", "pwr_irq"; 750 751 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 752 <&gcc GCC_SDCC2_APPS_CLK>, 753 <&rpmcc RPM_SMD_XO_CLK_SRC>; 754 clock-names = "iface", "core", "xo"; 755 756 pinctrl-0 = <&sdc2_state_on>; 757 pinctrl-1 = <&sdc2_state_off>; 758 pinctrl-names = "default", "sleep"; 759 760 power-domains = <&rpmpd SM6115_VDDCX>; 761 operating-points-v2 = <&sdhc2_opp_table>; 762 iommus = <&apps_smmu 0x00a0 0x0>; 763 resets = <&gcc GCC_SDCC2_BCR>; 764 765 bus-width = <4>; 766 qcom,dll-config = <0x0007642c>; 767 qcom,ddr-config = <0x80040868>; 768 status = "disabled"; 769 770 sdhc2_opp_table: opp-table { 771 compatible = "operating-points-v2"; 772 773 opp-100000000 { 774 opp-hz = /bits/ 64 <100000000>; 775 required-opps = <&rpmpd_opp_low_svs>; 776 }; 777 778 opp-202000000 { 779 opp-hz = /bits/ 64 <202000000>; 780 required-opps = <&rpmpd_opp_nom>; 781 }; 782 }; 783 }; 784 785 ufs_mem_hc: ufs@4804000 { 786 compatible = "qcom,sm6115-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; 787 reg = <0x0 0x04804000 0x0 0x3000>, <0x0 0x04810000 0x0 0x8000>; 788 reg-names = "std", "ice"; 789 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 790 phys = <&ufs_mem_phy_lanes>; 791 phy-names = "ufsphy"; 792 lanes-per-direction = <1>; 793 #reset-cells = <1>; 794 resets = <&gcc GCC_UFS_PHY_BCR>; 795 reset-names = "rst"; 796 797 power-domains = <&gcc GCC_UFS_PHY_GDSC>; 798 iommus = <&apps_smmu 0x100 0>; 799 800 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 801 <&gcc GCC_SYS_NOC_UFS_PHY_AXI_CLK>, 802 <&gcc GCC_UFS_PHY_AHB_CLK>, 803 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 804 <&rpmcc RPM_SMD_XO_CLK_SRC>, 805 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 806 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 807 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 808 clock-names = "core_clk", 809 "bus_aggr_clk", 810 "iface_clk", 811 "core_clk_unipro", 812 "ref_clk", 813 "tx_lane0_sync_clk", 814 "rx_lane0_sync_clk", 815 "ice_core_clk"; 816 817 freq-table-hz = <50000000 200000000>, 818 <0 0>, 819 <0 0>, 820 <37500000 150000000>, 821 <0 0>, 822 <0 0>, 823 <0 0>, 824 <75000000 300000000>; 825 826 status = "disabled"; 827 }; 828 829 ufs_mem_phy: phy@4807000 { 830 compatible = "qcom,sm6115-qmp-ufs-phy"; 831 reg = <0x0 0x04807000 0x0 0x1c4>; 832 #address-cells = <2>; 833 #size-cells = <2>; 834 ranges; 835 836 clocks = <&gcc GCC_UFS_CLKREF_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 837 clock-names = "ref", "ref_aux"; 838 839 resets = <&ufs_mem_hc 0>; 840 reset-names = "ufsphy"; 841 status = "disabled"; 842 843 ufs_mem_phy_lanes: phy@4807400 { 844 reg = <0x0 0x04807400 0x0 0x098>, 845 <0x0 0x04807600 0x0 0x130>, 846 <0x0 0x04807c00 0x0 0x16c>; 847 #phy-cells = <0>; 848 }; 849 }; 850 851 gpi_dma0: dma-controller@4a00000 { 852 compatible = "qcom,sm6115-gpi-dma", "qcom,sm6350-gpi-dma"; 853 reg = <0x0 0x04a00000 0x0 0x60000>; 854 interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 855 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 856 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 857 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 858 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 859 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 860 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 861 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 862 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 863 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; 864 dma-channels = <10>; 865 dma-channel-mask = <0xf>; 866 iommus = <&apps_smmu 0xf6 0x0>; 867 #dma-cells = <3>; 868 status = "disabled"; 869 }; 870 871 qupv3_id_0: geniqup@4ac0000 { 872 compatible = "qcom,geni-se-qup"; 873 reg = <0x0 0x04ac0000 0x0 0x2000>; 874 clock-names = "m-ahb", "s-ahb"; 875 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 876 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 877 #address-cells = <2>; 878 #size-cells = <2>; 879 iommus = <&apps_smmu 0xe3 0x0>; 880 ranges; 881 status = "disabled"; 882 883 i2c0: i2c@4a80000 { 884 compatible = "qcom,geni-i2c"; 885 reg = <0x0 0x04a80000 0x0 0x4000>; 886 clock-names = "se"; 887 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 888 pinctrl-names = "default"; 889 pinctrl-0 = <&qup_i2c0_default>; 890 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 891 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 892 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 893 dma-names = "tx", "rx"; 894 #address-cells = <1>; 895 #size-cells = <0>; 896 status = "disabled"; 897 }; 898 899 spi0: spi@4a80000 { 900 compatible = "qcom,geni-spi"; 901 reg = <0x0 0x04a80000 0x0 0x4000>; 902 clock-names = "se"; 903 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 904 pinctrl-names = "default"; 905 pinctrl-0 = <&qup_spi0_default>; 906 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 907 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 908 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 909 dma-names = "tx", "rx"; 910 #address-cells = <1>; 911 #size-cells = <0>; 912 status = "disabled"; 913 }; 914 915 i2c1: i2c@4a84000 { 916 compatible = "qcom,geni-i2c"; 917 reg = <0x0 0x04a84000 0x0 0x4000>; 918 clock-names = "se"; 919 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 920 pinctrl-names = "default"; 921 pinctrl-0 = <&qup_i2c1_default>; 922 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 923 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 924 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 925 dma-names = "tx", "rx"; 926 #address-cells = <1>; 927 #size-cells = <0>; 928 status = "disabled"; 929 }; 930 931 spi1: spi@4a84000 { 932 compatible = "qcom,geni-spi"; 933 reg = <0x0 0x04a84000 0x0 0x4000>; 934 clock-names = "se"; 935 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 936 pinctrl-names = "default"; 937 pinctrl-0 = <&qup_spi1_default>; 938 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 939 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 940 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 941 dma-names = "tx", "rx"; 942 #address-cells = <1>; 943 #size-cells = <0>; 944 status = "disabled"; 945 }; 946 947 i2c2: i2c@4a88000 { 948 compatible = "qcom,geni-i2c"; 949 reg = <0x0 0x04a88000 0x0 0x4000>; 950 clock-names = "se"; 951 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 952 pinctrl-names = "default"; 953 pinctrl-0 = <&qup_i2c2_default>; 954 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; 955 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 956 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 957 dma-names = "tx", "rx"; 958 #address-cells = <1>; 959 #size-cells = <0>; 960 status = "disabled"; 961 }; 962 963 spi2: spi@4a88000 { 964 compatible = "qcom,geni-spi"; 965 reg = <0x0 0x04a88000 0x0 0x4000>; 966 clock-names = "se"; 967 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 968 pinctrl-names = "default"; 969 pinctrl-0 = <&qup_spi2_default>; 970 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; 971 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 972 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 973 dma-names = "tx", "rx"; 974 #address-cells = <1>; 975 #size-cells = <0>; 976 status = "disabled"; 977 }; 978 979 i2c3: i2c@4a8c000 { 980 compatible = "qcom,geni-i2c"; 981 reg = <0x0 0x04a8c000 0x0 0x4000>; 982 clock-names = "se"; 983 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 984 pinctrl-names = "default"; 985 pinctrl-0 = <&qup_i2c3_default>; 986 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 987 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 988 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 989 dma-names = "tx", "rx"; 990 #address-cells = <1>; 991 #size-cells = <0>; 992 status = "disabled"; 993 }; 994 995 spi3: spi@4a8c000 { 996 compatible = "qcom,geni-spi"; 997 reg = <0x0 0x04a8c000 0x0 0x4000>; 998 clock-names = "se"; 999 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1000 pinctrl-names = "default"; 1001 pinctrl-0 = <&qup_spi3_default>; 1002 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 1003 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1004 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1005 dma-names = "tx", "rx"; 1006 #address-cells = <1>; 1007 #size-cells = <0>; 1008 status = "disabled"; 1009 }; 1010 1011 i2c4: i2c@4a90000 { 1012 compatible = "qcom,geni-i2c"; 1013 reg = <0x0 0x04a90000 0x0 0x4000>; 1014 clock-names = "se"; 1015 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1016 pinctrl-names = "default"; 1017 pinctrl-0 = <&qup_i2c4_default>; 1018 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 1019 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1020 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1021 dma-names = "tx", "rx"; 1022 #address-cells = <1>; 1023 #size-cells = <0>; 1024 status = "disabled"; 1025 }; 1026 1027 spi4: spi@4a90000 { 1028 compatible = "qcom,geni-spi"; 1029 reg = <0x0 0x04a90000 0x0 0x4000>; 1030 clock-names = "se"; 1031 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1032 pinctrl-names = "default"; 1033 pinctrl-0 = <&qup_spi4_default>; 1034 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 1035 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1036 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1037 dma-names = "tx", "rx"; 1038 #address-cells = <1>; 1039 #size-cells = <0>; 1040 status = "disabled"; 1041 }; 1042 1043 uart4: serial@4a90000 { 1044 compatible = "qcom,geni-debug-uart"; 1045 reg = <0x0 0x04a90000 0x0 0x4000>; 1046 clock-names = "se"; 1047 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1048 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 1049 status = "disabled"; 1050 }; 1051 1052 i2c5: i2c@4a94000 { 1053 compatible = "qcom,geni-i2c"; 1054 reg = <0x0 0x04a94000 0x0 0x4000>; 1055 clock-names = "se"; 1056 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1057 pinctrl-names = "default"; 1058 pinctrl-0 = <&qup_i2c5_default>; 1059 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; 1060 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1061 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1062 dma-names = "tx", "rx"; 1063 #address-cells = <1>; 1064 #size-cells = <0>; 1065 status = "disabled"; 1066 }; 1067 1068 spi5: spi@4a94000 { 1069 compatible = "qcom,geni-spi"; 1070 reg = <0x0 0x04a94000 0x0 0x4000>; 1071 clock-names = "se"; 1072 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1073 pinctrl-names = "default"; 1074 pinctrl-0 = <&qup_spi5_default>; 1075 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; 1076 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1077 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1078 dma-names = "tx", "rx"; 1079 #address-cells = <1>; 1080 #size-cells = <0>; 1081 status = "disabled"; 1082 }; 1083 }; 1084 1085 usb_1: usb@4ef8800 { 1086 compatible = "qcom,sm6115-dwc3", "qcom,dwc3"; 1087 reg = <0x0 0x04ef8800 0x0 0x400>; 1088 #address-cells = <2>; 1089 #size-cells = <2>; 1090 ranges; 1091 1092 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 1093 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 1094 <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>, 1095 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 1096 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1097 <&gcc GCC_USB3_PRIM_CLKREF_CLK>; 1098 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", "xo"; 1099 1100 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1101 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 1102 assigned-clock-rates = <19200000>, <66666667>; 1103 1104 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 1105 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>; 1106 interrupt-names = "hs_phy_irq", "ss_phy_irq"; 1107 1108 resets = <&gcc GCC_USB30_PRIM_BCR>; 1109 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 1110 qcom,select-utmi-as-pipe-clk; 1111 status = "disabled"; 1112 1113 usb_1_dwc3: usb@4e00000 { 1114 compatible = "snps,dwc3"; 1115 reg = <0x0 0x04e00000 0x0 0xcd00>; 1116 interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 1117 phys = <&usb_1_hsphy>; 1118 phy-names = "usb2-phy"; 1119 iommus = <&apps_smmu 0x120 0x0>; 1120 snps,dis_u2_susphy_quirk; 1121 snps,dis_enblslpm_quirk; 1122 snps,has-lpm-erratum; 1123 snps,hird-threshold = /bits/ 8 <0x10>; 1124 snps,usb3_lpm_capable; 1125 maximum-speed = "high-speed"; 1126 dr_mode = "peripheral"; 1127 }; 1128 }; 1129 1130 mdss: display-subsystem@5e00000 { 1131 compatible = "qcom,sm6115-mdss"; 1132 reg = <0x0 0x05e00000 0x0 0x1000>; 1133 reg-names = "mdss"; 1134 1135 power-domains = <&dispcc MDSS_GDSC>; 1136 1137 clocks = <&gcc GCC_DISP_AHB_CLK>, 1138 <&gcc GCC_DISP_HF_AXI_CLK>, 1139 <&dispcc DISP_CC_MDSS_MDP_CLK>; 1140 1141 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 1142 interrupt-controller; 1143 #interrupt-cells = <1>; 1144 1145 iommus = <&apps_smmu 0x420 0x2>, 1146 <&apps_smmu 0x421 0x0>; 1147 1148 #address-cells = <2>; 1149 #size-cells = <2>; 1150 ranges; 1151 1152 status = "disabled"; 1153 1154 mdp: display-controller@5e01000 { 1155 compatible = "qcom,sm6115-dpu"; 1156 reg = <0x0 0x05e01000 0x0 0x8f000>, 1157 <0x0 0x05eb0000 0x0 0x2008>; 1158 reg-names = "mdp", "vbif"; 1159 1160 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 1161 <&dispcc DISP_CC_MDSS_AHB_CLK>, 1162 <&dispcc DISP_CC_MDSS_MDP_CLK>, 1163 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 1164 <&dispcc DISP_CC_MDSS_ROT_CLK>, 1165 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 1166 clock-names = "bus", 1167 "iface", 1168 "core", 1169 "lut", 1170 "rot", 1171 "vsync"; 1172 1173 operating-points-v2 = <&mdp_opp_table>; 1174 power-domains = <&rpmpd SM6115_VDDCX>; 1175 1176 interrupt-parent = <&mdss>; 1177 interrupts = <0>; 1178 1179 ports { 1180 #address-cells = <1>; 1181 #size-cells = <0>; 1182 1183 port@0 { 1184 reg = <0>; 1185 dpu_intf1_out: endpoint { 1186 remote-endpoint = <&mdss_dsi0_in>; 1187 }; 1188 }; 1189 }; 1190 1191 mdp_opp_table: opp-table { 1192 compatible = "operating-points-v2"; 1193 1194 opp-19200000 { 1195 opp-hz = /bits/ 64 <19200000>; 1196 required-opps = <&rpmpd_opp_min_svs>; 1197 }; 1198 1199 opp-192000000 { 1200 opp-hz = /bits/ 64 <192000000>; 1201 required-opps = <&rpmpd_opp_low_svs>; 1202 }; 1203 1204 opp-256000000 { 1205 opp-hz = /bits/ 64 <256000000>; 1206 required-opps = <&rpmpd_opp_svs>; 1207 }; 1208 1209 opp-307200000 { 1210 opp-hz = /bits/ 64 <307200000>; 1211 required-opps = <&rpmpd_opp_svs_plus>; 1212 }; 1213 1214 opp-384000000 { 1215 opp-hz = /bits/ 64 <384000000>; 1216 required-opps = <&rpmpd_opp_nom>; 1217 }; 1218 }; 1219 }; 1220 1221 mdss_dsi0: dsi@5e94000 { 1222 compatible = "qcom,dsi-ctrl-6g-qcm2290"; 1223 reg = <0x0 0x05e94000 0x0 0x400>; 1224 reg-names = "dsi_ctrl"; 1225 1226 interrupt-parent = <&mdss>; 1227 interrupts = <4>; 1228 1229 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 1230 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 1231 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 1232 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 1233 <&dispcc DISP_CC_MDSS_AHB_CLK>, 1234 <&gcc GCC_DISP_HF_AXI_CLK>; 1235 clock-names = "byte", 1236 "byte_intf", 1237 "pixel", 1238 "core", 1239 "iface", 1240 "bus"; 1241 1242 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 1243 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 1244 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; 1245 1246 operating-points-v2 = <&dsi_opp_table>; 1247 power-domains = <&rpmpd SM6115_VDDCX>; 1248 phys = <&mdss_dsi0_phy>; 1249 1250 #address-cells = <1>; 1251 #size-cells = <0>; 1252 1253 status = "disabled"; 1254 1255 ports { 1256 #address-cells = <1>; 1257 #size-cells = <0>; 1258 1259 port@0 { 1260 reg = <0>; 1261 mdss_dsi0_in: endpoint { 1262 remote-endpoint = <&dpu_intf1_out>; 1263 }; 1264 }; 1265 1266 port@1 { 1267 reg = <1>; 1268 mdss_dsi0_out: endpoint { 1269 }; 1270 }; 1271 }; 1272 1273 dsi_opp_table: opp-table { 1274 compatible = "operating-points-v2"; 1275 1276 opp-19200000 { 1277 opp-hz = /bits/ 64 <19200000>; 1278 required-opps = <&rpmpd_opp_min_svs>; 1279 }; 1280 1281 opp-164000000 { 1282 opp-hz = /bits/ 64 <164000000>; 1283 required-opps = <&rpmpd_opp_low_svs>; 1284 }; 1285 1286 opp-187500000 { 1287 opp-hz = /bits/ 64 <187500000>; 1288 required-opps = <&rpmpd_opp_svs>; 1289 }; 1290 }; 1291 }; 1292 1293 mdss_dsi0_phy: phy@5e94400 { 1294 compatible = "qcom,dsi-phy-14nm-2290"; 1295 reg = <0x0 0x05e94400 0x0 0x100>, 1296 <0x0 0x05e94500 0x0 0x300>, 1297 <0x0 0x05e94800 0x0 0x188>; 1298 reg-names = "dsi_phy", 1299 "dsi_phy_lane", 1300 "dsi_pll"; 1301 1302 #clock-cells = <1>; 1303 #phy-cells = <0>; 1304 1305 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 1306 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1307 clock-names = "iface", "ref"; 1308 1309 status = "disabled"; 1310 }; 1311 }; 1312 1313 dispcc: clock-controller@5f00000 { 1314 compatible = "qcom,sm6115-dispcc"; 1315 reg = <0x0 0x05f00000 0 0x20000>; 1316 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 1317 <&sleep_clk>, 1318 <&mdss_dsi0_phy 0>, 1319 <&mdss_dsi0_phy 1>, 1320 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>; 1321 #clock-cells = <1>; 1322 #reset-cells = <1>; 1323 #power-domain-cells = <1>; 1324 }; 1325 1326 stm@8002000 { 1327 compatible = "arm,coresight-stm", "arm,primecell"; 1328 reg = <0x0 0x08002000 0x0 0x1000>, 1329 <0x0 0x0e280000 0x0 0x180000>; 1330 reg-names = "stm-base", "stm-stimulus-base"; 1331 1332 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1333 clock-names = "apb_pclk"; 1334 1335 status = "disabled"; 1336 1337 out-ports { 1338 port { 1339 stm_out: endpoint { 1340 remote-endpoint = <&funnel_in0_in>; 1341 }; 1342 }; 1343 }; 1344 }; 1345 1346 cti0: cti@8010000 { 1347 compatible = "arm,coresight-cti", "arm,primecell"; 1348 reg = <0x0 0x08010000 0x0 0x1000>; 1349 1350 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1351 clock-names = "apb_pclk"; 1352 1353 status = "disabled"; 1354 }; 1355 1356 cti1: cti@8011000 { 1357 compatible = "arm,coresight-cti", "arm,primecell"; 1358 reg = <0x0 0x08011000 0x0 0x1000>; 1359 1360 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1361 clock-names = "apb_pclk"; 1362 1363 status = "disabled"; 1364 }; 1365 1366 cti2: cti@8012000 { 1367 compatible = "arm,coresight-cti", "arm,primecell"; 1368 reg = <0x0 0x08012000 0x0 0x1000>; 1369 1370 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1371 clock-names = "apb_pclk"; 1372 1373 status = "disabled"; 1374 }; 1375 1376 cti3: cti@8013000 { 1377 compatible = "arm,coresight-cti", "arm,primecell"; 1378 reg = <0x0 0x08013000 0x0 0x1000>; 1379 1380 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1381 clock-names = "apb_pclk"; 1382 1383 status = "disabled"; 1384 }; 1385 1386 cti4: cti@8014000 { 1387 compatible = "arm,coresight-cti", "arm,primecell"; 1388 reg = <0x0 0x08014000 0x0 0x1000>; 1389 1390 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1391 clock-names = "apb_pclk"; 1392 1393 status = "disabled"; 1394 }; 1395 1396 cti5: cti@8015000 { 1397 compatible = "arm,coresight-cti", "arm,primecell"; 1398 reg = <0x0 0x08015000 0x0 0x1000>; 1399 1400 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1401 clock-names = "apb_pclk"; 1402 1403 status = "disabled"; 1404 }; 1405 1406 cti6: cti@8016000 { 1407 compatible = "arm,coresight-cti", "arm,primecell"; 1408 reg = <0x0 0x08016000 0x0 0x1000>; 1409 1410 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1411 clock-names = "apb_pclk"; 1412 1413 status = "disabled"; 1414 }; 1415 1416 cti7: cti@8017000 { 1417 compatible = "arm,coresight-cti", "arm,primecell"; 1418 reg = <0x0 0x08017000 0x0 0x1000>; 1419 1420 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1421 clock-names = "apb_pclk"; 1422 1423 status = "disabled"; 1424 }; 1425 1426 cti8: cti@8018000 { 1427 compatible = "arm,coresight-cti", "arm,primecell"; 1428 reg = <0x0 0x08018000 0x0 0x1000>; 1429 1430 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1431 clock-names = "apb_pclk"; 1432 1433 status = "disabled"; 1434 }; 1435 1436 cti9: cti@8019000 { 1437 compatible = "arm,coresight-cti", "arm,primecell"; 1438 reg = <0x0 0x08019000 0x0 0x1000>; 1439 1440 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1441 clock-names = "apb_pclk"; 1442 1443 status = "disabled"; 1444 }; 1445 1446 cti10: cti@801a000 { 1447 compatible = "arm,coresight-cti", "arm,primecell"; 1448 reg = <0x0 0x0801a000 0x0 0x1000>; 1449 1450 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1451 clock-names = "apb_pclk"; 1452 1453 status = "disabled"; 1454 }; 1455 1456 cti11: cti@801b000 { 1457 compatible = "arm,coresight-cti", "arm,primecell"; 1458 reg = <0x0 0x0801b000 0x0 0x1000>; 1459 1460 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1461 clock-names = "apb_pclk"; 1462 1463 status = "disabled"; 1464 }; 1465 1466 cti12: cti@801c000 { 1467 compatible = "arm,coresight-cti", "arm,primecell"; 1468 reg = <0x0 0x0801c000 0x0 0x1000>; 1469 1470 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1471 clock-names = "apb_pclk"; 1472 1473 status = "disabled"; 1474 }; 1475 1476 cti13: cti@801d000 { 1477 compatible = "arm,coresight-cti", "arm,primecell"; 1478 reg = <0x0 0x0801d000 0x0 0x1000>; 1479 1480 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1481 clock-names = "apb_pclk"; 1482 1483 status = "disabled"; 1484 }; 1485 1486 cti14: cti@801e000 { 1487 compatible = "arm,coresight-cti", "arm,primecell"; 1488 reg = <0x0 0x0801e000 0x0 0x1000>; 1489 1490 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1491 clock-names = "apb_pclk"; 1492 1493 status = "disabled"; 1494 }; 1495 1496 cti15: cti@801f000 { 1497 compatible = "arm,coresight-cti", "arm,primecell"; 1498 reg = <0x0 0x0801f000 0x0 0x1000>; 1499 1500 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1501 clock-names = "apb_pclk"; 1502 1503 status = "disabled"; 1504 }; 1505 1506 replicator@8046000 { 1507 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 1508 reg = <0x0 0x08046000 0x0 0x1000>; 1509 1510 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1511 clock-names = "apb_pclk"; 1512 1513 status = "disabled"; 1514 1515 out-ports { 1516 port { 1517 replicator_out: endpoint { 1518 remote-endpoint = <&etr_in>; 1519 }; 1520 }; 1521 }; 1522 1523 in-ports { 1524 port { 1525 replicator_in: endpoint { 1526 remote-endpoint = <&etf_out>; 1527 }; 1528 }; 1529 }; 1530 }; 1531 1532 etf@8047000 { 1533 compatible = "arm,coresight-tmc", "arm,primecell"; 1534 reg = <0x0 0x08047000 0x0 0x1000>; 1535 1536 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1537 clock-names = "apb_pclk"; 1538 1539 status = "disabled"; 1540 1541 in-ports { 1542 port { 1543 etf_in: endpoint { 1544 remote-endpoint = <&merge_funnel_out>; 1545 }; 1546 }; 1547 }; 1548 1549 out-ports { 1550 port { 1551 etf_out: endpoint { 1552 remote-endpoint = <&replicator_in>; 1553 }; 1554 }; 1555 }; 1556 }; 1557 1558 etr@8048000 { 1559 compatible = "arm,coresight-tmc", "arm,primecell"; 1560 reg = <0x0 0x08048000 0x0 0x1000>; 1561 1562 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1563 clock-names = "apb_pclk"; 1564 1565 status = "disabled"; 1566 1567 in-ports { 1568 port { 1569 etr_in: endpoint { 1570 remote-endpoint = <&replicator_out>; 1571 }; 1572 }; 1573 }; 1574 }; 1575 1576 funnel@8041000 { 1577 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1578 reg = <0x0 0x08041000 0x0 0x1000>; 1579 1580 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1581 clock-names = "apb_pclk"; 1582 1583 status = "disabled"; 1584 1585 out-ports { 1586 port { 1587 funnel_in0_out: endpoint { 1588 remote-endpoint = <&merge_funnel_in0>; 1589 }; 1590 }; 1591 }; 1592 1593 in-ports { 1594 port { 1595 funnel_in0_in: endpoint { 1596 remote-endpoint = <&stm_out>; 1597 }; 1598 }; 1599 }; 1600 }; 1601 1602 funnel@8042000 { 1603 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1604 reg = <0x0 0x08042000 0x0 0x1000>; 1605 1606 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1607 clock-names = "apb_pclk"; 1608 1609 status = "disabled"; 1610 1611 out-ports { 1612 port { 1613 funnel_in1_out: endpoint { 1614 remote-endpoint = <&merge_funnel_in1>; 1615 }; 1616 }; 1617 }; 1618 1619 in-ports { 1620 port { 1621 funnel_in1_in: endpoint { 1622 remote-endpoint = <&funnel_apss1_out>; 1623 }; 1624 }; 1625 }; 1626 }; 1627 1628 funnel@8045000 { 1629 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1630 reg = <0x0 0x08045000 0x0 0x1000>; 1631 1632 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1633 clock-names = "apb_pclk"; 1634 1635 status = "disabled"; 1636 1637 out-ports { 1638 port { 1639 merge_funnel_out: endpoint { 1640 remote-endpoint = <&etf_in>; 1641 }; 1642 }; 1643 }; 1644 1645 in-ports { 1646 #address-cells = <1>; 1647 #size-cells = <0>; 1648 1649 port@0 { 1650 reg = <0>; 1651 merge_funnel_in0: endpoint { 1652 remote-endpoint = <&funnel_in0_out>; 1653 }; 1654 }; 1655 1656 port@1 { 1657 reg = <1>; 1658 merge_funnel_in1: endpoint { 1659 remote-endpoint = <&funnel_in1_out>; 1660 }; 1661 }; 1662 }; 1663 }; 1664 1665 etm@9040000 { 1666 compatible = "arm,coresight-etm4x", "arm,primecell"; 1667 reg = <0x0 0x09040000 0x0 0x1000>; 1668 1669 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1670 clock-names = "apb_pclk"; 1671 arm,coresight-loses-context-with-cpu; 1672 1673 cpu = <&CPU0>; 1674 1675 status = "disabled"; 1676 1677 out-ports { 1678 port { 1679 etm0_out: endpoint { 1680 remote-endpoint = <&funnel_apss0_in0>; 1681 }; 1682 }; 1683 }; 1684 }; 1685 1686 etm@9140000 { 1687 compatible = "arm,coresight-etm4x", "arm,primecell"; 1688 reg = <0x0 0x09140000 0x0 0x1000>; 1689 1690 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1691 clock-names = "apb_pclk"; 1692 arm,coresight-loses-context-with-cpu; 1693 1694 cpu = <&CPU1>; 1695 1696 status = "disabled"; 1697 1698 out-ports { 1699 port { 1700 etm1_out: endpoint { 1701 remote-endpoint = <&funnel_apss0_in1>; 1702 }; 1703 }; 1704 }; 1705 }; 1706 1707 etm@9240000 { 1708 compatible = "arm,coresight-etm4x", "arm,primecell"; 1709 reg = <0x0 0x09240000 0x0 0x1000>; 1710 1711 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1712 clock-names = "apb_pclk"; 1713 arm,coresight-loses-context-with-cpu; 1714 1715 cpu = <&CPU2>; 1716 1717 status = "disabled"; 1718 1719 out-ports { 1720 port { 1721 etm2_out: endpoint { 1722 remote-endpoint = <&funnel_apss0_in2>; 1723 }; 1724 }; 1725 }; 1726 }; 1727 1728 etm@9340000 { 1729 compatible = "arm,coresight-etm4x", "arm,primecell"; 1730 reg = <0x0 0x09340000 0x0 0x1000>; 1731 1732 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1733 clock-names = "apb_pclk"; 1734 arm,coresight-loses-context-with-cpu; 1735 1736 cpu = <&CPU3>; 1737 1738 status = "disabled"; 1739 1740 out-ports { 1741 port { 1742 etm3_out: endpoint { 1743 remote-endpoint = <&funnel_apss0_in3>; 1744 }; 1745 }; 1746 }; 1747 }; 1748 1749 etm@9440000 { 1750 compatible = "arm,coresight-etm4x", "arm,primecell"; 1751 reg = <0x0 0x09440000 0x0 0x1000>; 1752 1753 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1754 clock-names = "apb_pclk"; 1755 arm,coresight-loses-context-with-cpu; 1756 1757 cpu = <&CPU4>; 1758 1759 status = "disabled"; 1760 1761 out-ports { 1762 port { 1763 etm4_out: endpoint { 1764 remote-endpoint = <&funnel_apss0_in4>; 1765 }; 1766 }; 1767 }; 1768 }; 1769 1770 etm@9540000 { 1771 compatible = "arm,coresight-etm4x", "arm,primecell"; 1772 reg = <0x0 0x09540000 0x0 0x1000>; 1773 1774 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1775 clock-names = "apb_pclk"; 1776 arm,coresight-loses-context-with-cpu; 1777 1778 cpu = <&CPU5>; 1779 1780 status = "disabled"; 1781 1782 out-ports { 1783 port { 1784 etm5_out: endpoint { 1785 remote-endpoint = <&funnel_apss0_in5>; 1786 }; 1787 }; 1788 }; 1789 }; 1790 1791 etm@9640000 { 1792 compatible = "arm,coresight-etm4x", "arm,primecell"; 1793 reg = <0x0 0x09640000 0x0 0x1000>; 1794 1795 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1796 clock-names = "apb_pclk"; 1797 arm,coresight-loses-context-with-cpu; 1798 1799 cpu = <&CPU6>; 1800 1801 status = "disabled"; 1802 1803 out-ports { 1804 port { 1805 etm6_out: endpoint { 1806 remote-endpoint = <&funnel_apss0_in6>; 1807 }; 1808 }; 1809 }; 1810 }; 1811 1812 etm@9740000 { 1813 compatible = "arm,coresight-etm4x", "arm,primecell"; 1814 reg = <0x0 0x09740000 0x0 0x1000>; 1815 1816 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1817 clock-names = "apb_pclk"; 1818 arm,coresight-loses-context-with-cpu; 1819 1820 cpu = <&CPU7>; 1821 1822 status = "disabled"; 1823 1824 out-ports { 1825 port { 1826 etm7_out: endpoint { 1827 remote-endpoint = <&funnel_apss0_in7>; 1828 }; 1829 }; 1830 }; 1831 }; 1832 1833 funnel@9800000 { 1834 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1835 reg = <0x0 0x09800000 0x0 0x1000>; 1836 1837 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1838 clock-names = "apb_pclk"; 1839 1840 status = "disabled"; 1841 1842 out-ports { 1843 port { 1844 funnel_apss0_out: endpoint { 1845 remote-endpoint = <&funnel_apss1_in>; 1846 }; 1847 }; 1848 }; 1849 1850 in-ports { 1851 #address-cells = <1>; 1852 #size-cells = <0>; 1853 1854 port@0 { 1855 reg = <0>; 1856 funnel_apss0_in0: endpoint { 1857 remote-endpoint = <&etm0_out>; 1858 }; 1859 }; 1860 1861 port@1 { 1862 reg = <1>; 1863 funnel_apss0_in1: endpoint { 1864 remote-endpoint = <&etm1_out>; 1865 }; 1866 }; 1867 1868 port@2 { 1869 reg = <2>; 1870 funnel_apss0_in2: endpoint { 1871 remote-endpoint = <&etm2_out>; 1872 }; 1873 }; 1874 1875 port@3 { 1876 reg = <3>; 1877 funnel_apss0_in3: endpoint { 1878 remote-endpoint = <&etm3_out>; 1879 }; 1880 }; 1881 1882 port@4 { 1883 reg = <4>; 1884 funnel_apss0_in4: endpoint { 1885 remote-endpoint = <&etm4_out>; 1886 }; 1887 }; 1888 1889 port@5 { 1890 reg = <5>; 1891 funnel_apss0_in5: endpoint { 1892 remote-endpoint = <&etm5_out>; 1893 }; 1894 }; 1895 1896 port@6 { 1897 reg = <6>; 1898 funnel_apss0_in6: endpoint { 1899 remote-endpoint = <&etm6_out>; 1900 }; 1901 }; 1902 1903 port@7 { 1904 reg = <7>; 1905 funnel_apss0_in7: endpoint { 1906 remote-endpoint = <&etm7_out>; 1907 }; 1908 }; 1909 }; 1910 }; 1911 1912 funnel@9810000 { 1913 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1914 reg = <0x0 0x09810000 0x0 0x1000>; 1915 1916 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 1917 clock-names = "apb_pclk"; 1918 1919 status = "disabled"; 1920 1921 out-ports { 1922 port { 1923 funnel_apss1_out: endpoint { 1924 remote-endpoint = <&funnel_in1_in>; 1925 }; 1926 }; 1927 }; 1928 1929 in-ports { 1930 port { 1931 funnel_apss1_in: endpoint { 1932 remote-endpoint = <&funnel_apss0_out>; 1933 }; 1934 }; 1935 }; 1936 }; 1937 1938 apps_smmu: iommu@c600000 { 1939 compatible = "qcom,sm6115-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 1940 reg = <0x0 0x0c600000 0x0 0x80000>; 1941 #iommu-cells = <2>; 1942 #global-interrupts = <1>; 1943 1944 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 1945 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 1946 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 1947 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 1948 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 1949 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 1950 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 1951 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 1952 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 1953 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 1954 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 1955 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 1956 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 1957 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 1958 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 1959 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 1960 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 1961 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 1962 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 1963 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 1964 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 1965 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 1966 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 1967 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1968 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 1969 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 1970 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 1971 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 1972 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 1973 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1974 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1975 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1976 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 1977 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1978 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1979 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1980 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1981 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1982 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1983 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1984 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 1985 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 1986 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 1987 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 1988 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 1989 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 1990 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1991 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 1992 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1993 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 1994 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 1995 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 1996 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 1997 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 1998 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 1999 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 2000 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 2001 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 2002 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 2003 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 2004 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 2005 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 2006 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 2007 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 2008 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 2009 }; 2010 2011 wifi: wifi@c800000 { 2012 compatible = "qcom,wcn3990-wifi"; 2013 reg = <0x0 0x0c800000 0x0 0x800000>; 2014 reg-names = "membase"; 2015 memory-region = <&wlan_msa_mem>; 2016 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, 2017 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, 2018 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, 2019 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>, 2020 <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>, 2021 <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>, 2022 <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>, 2023 <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>, 2024 <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>, 2025 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>, 2026 <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, 2027 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 2028 iommus = <&apps_smmu 0x1a0 0x1>; 2029 qcom,msa-fixed-perm; 2030 status = "disabled"; 2031 }; 2032 2033 watchdog@f017000 { 2034 compatible = "qcom,apss-wdt-sm6115", "qcom,kpss-wdt"; 2035 reg = <0x0 0x0f017000 0x0 0x1000>; 2036 clocks = <&sleep_clk>; 2037 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 2038 }; 2039 2040 apcs_glb: mailbox@f111000 { 2041 compatible = "qcom,sm6115-apcs-hmss-global"; 2042 reg = <0x0 0x0f111000 0x0 0x1000>; 2043 2044 #mbox-cells = <1>; 2045 }; 2046 2047 timer@f120000 { 2048 compatible = "arm,armv7-timer-mem"; 2049 reg = <0x0 0x0f120000 0x0 0x1000>; 2050 #address-cells = <2>; 2051 #size-cells = <2>; 2052 ranges; 2053 clock-frequency = <19200000>; 2054 2055 frame@f121000 { 2056 reg = <0x0 0x0f121000 0x0 0x1000>, <0x0 0x0f122000 0x0 0x1000>; 2057 frame-number = <0>; 2058 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 2059 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 2060 }; 2061 2062 frame@f123000 { 2063 reg = <0x0 0x0f123000 0x0 0x1000>; 2064 frame-number = <1>; 2065 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 2066 status = "disabled"; 2067 }; 2068 2069 frame@f124000 { 2070 reg = <0x0 0x0f124000 0x0 0x1000>; 2071 frame-number = <2>; 2072 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 2073 status = "disabled"; 2074 }; 2075 2076 frame@f125000 { 2077 reg = <0x0 0x0f125000 0x0 0x1000>; 2078 frame-number = <3>; 2079 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 2080 status = "disabled"; 2081 }; 2082 2083 frame@f126000 { 2084 reg = <0x0 0x0f126000 0x0 0x1000>; 2085 frame-number = <4>; 2086 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 2087 status = "disabled"; 2088 }; 2089 2090 frame@f127000 { 2091 reg = <0x0 0x0f127000 0x0 0x1000>; 2092 frame-number = <5>; 2093 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 2094 status = "disabled"; 2095 }; 2096 2097 frame@f128000 { 2098 reg = <0x0 0x0f128000 0x0 0x1000>; 2099 frame-number = <6>; 2100 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 2101 status = "disabled"; 2102 }; 2103 }; 2104 2105 intc: interrupt-controller@f200000 { 2106 compatible = "arm,gic-v3"; 2107 reg = <0x0 0x0f200000 0x0 0x10000>, 2108 <0x0 0x0f300000 0x0 0x100000>; 2109 #interrupt-cells = <3>; 2110 interrupt-controller; 2111 interrupt-parent = <&intc>; 2112 #redistributor-regions = <1>; 2113 redistributor-stride = <0x0 0x20000>; 2114 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 2115 }; 2116 2117 cpufreq_hw: cpufreq@f521000 { 2118 compatible = "qcom,cpufreq-hw"; 2119 reg = <0x0 0x0f521000 0x0 0x1000>, 2120 <0x0 0x0f523000 0x0 0x1000>; 2121 2122 reg-names = "freq-domain0", "freq-domain1"; 2123 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>; 2124 clock-names = "xo", "alternate"; 2125 2126 #freq-domain-cells = <1>; 2127 }; 2128 }; 2129 2130 thermal-zones { 2131 mapss-thermal { 2132 polling-delay-passive = <0>; 2133 polling-delay = <0>; 2134 thermal-sensors = <&tsens0 0>; 2135 2136 trips { 2137 trip-point0 { 2138 temperature = <115000>; 2139 hysteresis = <5000>; 2140 type = "passive"; 2141 }; 2142 2143 trip-point1 { 2144 temperature = <125000>; 2145 hysteresis = <1000>; 2146 type = "passive"; 2147 }; 2148 }; 2149 }; 2150 2151 cdsp-hvx-thermal { 2152 polling-delay-passive = <0>; 2153 polling-delay = <0>; 2154 thermal-sensors = <&tsens0 1>; 2155 2156 trips { 2157 trip-point0 { 2158 temperature = <115000>; 2159 hysteresis = <5000>; 2160 type = "passive"; 2161 }; 2162 2163 trip-point1 { 2164 temperature = <125000>; 2165 hysteresis = <1000>; 2166 type = "passive"; 2167 }; 2168 }; 2169 }; 2170 2171 wlan-thermal { 2172 polling-delay-passive = <0>; 2173 polling-delay = <0>; 2174 thermal-sensors = <&tsens0 2>; 2175 2176 trips { 2177 trip-point0 { 2178 temperature = <115000>; 2179 hysteresis = <5000>; 2180 type = "passive"; 2181 }; 2182 2183 trip-point1 { 2184 temperature = <125000>; 2185 hysteresis = <1000>; 2186 type = "passive"; 2187 }; 2188 }; 2189 }; 2190 2191 camera-thermal { 2192 polling-delay-passive = <0>; 2193 polling-delay = <0>; 2194 thermal-sensors = <&tsens0 3>; 2195 2196 trips { 2197 trip-point0 { 2198 temperature = <115000>; 2199 hysteresis = <5000>; 2200 type = "passive"; 2201 }; 2202 2203 trip-point1 { 2204 temperature = <125000>; 2205 hysteresis = <1000>; 2206 type = "passive"; 2207 }; 2208 }; 2209 }; 2210 2211 video-thermal { 2212 polling-delay-passive = <0>; 2213 polling-delay = <0>; 2214 thermal-sensors = <&tsens0 4>; 2215 2216 trips { 2217 trip-point0 { 2218 temperature = <115000>; 2219 hysteresis = <5000>; 2220 type = "passive"; 2221 }; 2222 2223 trip-point1 { 2224 temperature = <125000>; 2225 hysteresis = <1000>; 2226 type = "passive"; 2227 }; 2228 }; 2229 }; 2230 2231 modem1-thermal { 2232 polling-delay-passive = <0>; 2233 polling-delay = <0>; 2234 thermal-sensors = <&tsens0 5>; 2235 2236 trips { 2237 trip-point0 { 2238 temperature = <115000>; 2239 hysteresis = <5000>; 2240 type = "passive"; 2241 }; 2242 2243 trip-point1 { 2244 temperature = <125000>; 2245 hysteresis = <1000>; 2246 type = "passive"; 2247 }; 2248 }; 2249 }; 2250 2251 cpu4-thermal { 2252 polling-delay-passive = <0>; 2253 polling-delay = <0>; 2254 thermal-sensors = <&tsens0 6>; 2255 2256 trips { 2257 cpu4_alert0: trip-point0 { 2258 temperature = <90000>; 2259 hysteresis = <2000>; 2260 type = "passive"; 2261 }; 2262 2263 cpu4_alert1: trip-point1 { 2264 temperature = <95000>; 2265 hysteresis = <2000>; 2266 type = "passive"; 2267 }; 2268 2269 cpu4_crit: cpu_crit { 2270 temperature = <110000>; 2271 hysteresis = <1000>; 2272 type = "critical"; 2273 }; 2274 }; 2275 }; 2276 2277 cpu5-thermal { 2278 polling-delay-passive = <0>; 2279 polling-delay = <0>; 2280 thermal-sensors = <&tsens0 7>; 2281 2282 trips { 2283 cpu5_alert0: trip-point0 { 2284 temperature = <90000>; 2285 hysteresis = <2000>; 2286 type = "passive"; 2287 }; 2288 2289 cpu5_alert1: trip-point1 { 2290 temperature = <95000>; 2291 hysteresis = <2000>; 2292 type = "passive"; 2293 }; 2294 2295 cpu5_crit: cpu_crit { 2296 temperature = <110000>; 2297 hysteresis = <1000>; 2298 type = "critical"; 2299 }; 2300 }; 2301 }; 2302 2303 cpu6-thermal { 2304 polling-delay-passive = <0>; 2305 polling-delay = <0>; 2306 thermal-sensors = <&tsens0 8>; 2307 2308 trips { 2309 cpu6_alert0: trip-point0 { 2310 temperature = <90000>; 2311 hysteresis = <2000>; 2312 type = "passive"; 2313 }; 2314 2315 cpu6_alert1: trip-point1 { 2316 temperature = <95000>; 2317 hysteresis = <2000>; 2318 type = "passive"; 2319 }; 2320 2321 cpu6_crit: cpu_crit { 2322 temperature = <110000>; 2323 hysteresis = <1000>; 2324 type = "critical"; 2325 }; 2326 }; 2327 }; 2328 2329 cpu7-thermal { 2330 polling-delay-passive = <0>; 2331 polling-delay = <0>; 2332 thermal-sensors = <&tsens0 9>; 2333 2334 trips { 2335 cpu7_alert0: trip-point0 { 2336 temperature = <90000>; 2337 hysteresis = <2000>; 2338 type = "passive"; 2339 }; 2340 2341 cpu7_alert1: trip-point1 { 2342 temperature = <95000>; 2343 hysteresis = <2000>; 2344 type = "passive"; 2345 }; 2346 2347 cpu7_crit: cpu_crit { 2348 temperature = <110000>; 2349 hysteresis = <1000>; 2350 type = "critical"; 2351 }; 2352 }; 2353 }; 2354 2355 cpu45-thermal { 2356 polling-delay-passive = <0>; 2357 polling-delay = <0>; 2358 thermal-sensors = <&tsens0 10>; 2359 2360 trips { 2361 cpu45_alert0: trip-point0 { 2362 temperature = <90000>; 2363 hysteresis = <2000>; 2364 type = "passive"; 2365 }; 2366 2367 cpu45_alert1: trip-point1 { 2368 temperature = <95000>; 2369 hysteresis = <2000>; 2370 type = "passive"; 2371 }; 2372 2373 cpu45_crit: cpu_crit { 2374 temperature = <110000>; 2375 hysteresis = <1000>; 2376 type = "critical"; 2377 }; 2378 }; 2379 }; 2380 2381 cpu67-thermal { 2382 polling-delay-passive = <0>; 2383 polling-delay = <0>; 2384 thermal-sensors = <&tsens0 11>; 2385 2386 trips { 2387 cpu67_alert0: trip-point0 { 2388 temperature = <90000>; 2389 hysteresis = <2000>; 2390 type = "passive"; 2391 }; 2392 2393 cpu67_alert1: trip-point1 { 2394 temperature = <95000>; 2395 hysteresis = <2000>; 2396 type = "passive"; 2397 }; 2398 2399 cpu67_crit: cpu_crit { 2400 temperature = <110000>; 2401 hysteresis = <1000>; 2402 type = "critical"; 2403 }; 2404 }; 2405 }; 2406 2407 cpu0123-thermal { 2408 polling-delay-passive = <0>; 2409 polling-delay = <0>; 2410 thermal-sensors = <&tsens0 12>; 2411 2412 trips { 2413 cpu0123_alert0: trip-point0 { 2414 temperature = <90000>; 2415 hysteresis = <2000>; 2416 type = "passive"; 2417 }; 2418 2419 cpu0123_alert1: trip-point1 { 2420 temperature = <95000>; 2421 hysteresis = <2000>; 2422 type = "passive"; 2423 }; 2424 2425 cpu0123_crit: cpu_crit { 2426 temperature = <110000>; 2427 hysteresis = <1000>; 2428 type = "critical"; 2429 }; 2430 }; 2431 }; 2432 2433 modem0-thermal { 2434 polling-delay-passive = <0>; 2435 polling-delay = <0>; 2436 thermal-sensors = <&tsens0 13>; 2437 2438 trips { 2439 trip-point0 { 2440 temperature = <115000>; 2441 hysteresis = <5000>; 2442 type = "passive"; 2443 }; 2444 2445 trip-point1 { 2446 temperature = <125000>; 2447 hysteresis = <1000>; 2448 type = "passive"; 2449 }; 2450 }; 2451 }; 2452 2453 display-thermal { 2454 polling-delay-passive = <0>; 2455 polling-delay = <0>; 2456 thermal-sensors = <&tsens0 14>; 2457 2458 trips { 2459 trip-point0 { 2460 temperature = <115000>; 2461 hysteresis = <5000>; 2462 type = "passive"; 2463 }; 2464 2465 trip-point1 { 2466 temperature = <125000>; 2467 hysteresis = <1000>; 2468 type = "passive"; 2469 }; 2470 }; 2471 }; 2472 2473 gpu-thermal { 2474 polling-delay-passive = <0>; 2475 polling-delay = <0>; 2476 thermal-sensors = <&tsens0 15>; 2477 2478 trips { 2479 trip-point0 { 2480 temperature = <115000>; 2481 hysteresis = <5000>; 2482 type = "passive"; 2483 }; 2484 2485 trip-point1 { 2486 temperature = <125000>; 2487 hysteresis = <1000>; 2488 type = "passive"; 2489 }; 2490 }; 2491 }; 2492 }; 2493 2494 timer { 2495 compatible = "arm,armv8-timer"; 2496 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2497 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2498 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2499 <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 2500 }; 2501}; 2502