1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright (c) 2021, Iskren Chernev <iskren.chernev@gmail.com> 4 */ 5 6#include <dt-bindings/clock/qcom,gcc-sm6115.h> 7#include <dt-bindings/clock/qcom,sm6115-dispcc.h> 8#include <dt-bindings/clock/qcom,rpmcc.h> 9#include <dt-bindings/dma/qcom-gpi.h> 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/power/qcom-rpmpd.h> 13 14/ { 15 interrupt-parent = <&intc>; 16 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 chosen { }; 21 22 clocks { 23 xo_board: xo-board { 24 compatible = "fixed-clock"; 25 #clock-cells = <0>; 26 }; 27 28 sleep_clk: sleep-clk { 29 compatible = "fixed-clock"; 30 #clock-cells = <0>; 31 }; 32 }; 33 34 cpus { 35 #address-cells = <2>; 36 #size-cells = <0>; 37 38 CPU0: cpu@0 { 39 device_type = "cpu"; 40 compatible = "qcom,kryo260"; 41 reg = <0x0 0x0>; 42 capacity-dmips-mhz = <1024>; 43 dynamic-power-coefficient = <100>; 44 enable-method = "psci"; 45 next-level-cache = <&L2_0>; 46 qcom,freq-domain = <&cpufreq_hw 0>; 47 L2_0: l2-cache { 48 compatible = "cache"; 49 cache-level = <2>; 50 }; 51 }; 52 53 CPU1: cpu@1 { 54 device_type = "cpu"; 55 compatible = "qcom,kryo260"; 56 reg = <0x0 0x1>; 57 capacity-dmips-mhz = <1024>; 58 dynamic-power-coefficient = <100>; 59 enable-method = "psci"; 60 next-level-cache = <&L2_0>; 61 qcom,freq-domain = <&cpufreq_hw 0>; 62 }; 63 64 CPU2: cpu@2 { 65 device_type = "cpu"; 66 compatible = "qcom,kryo260"; 67 reg = <0x0 0x2>; 68 capacity-dmips-mhz = <1024>; 69 dynamic-power-coefficient = <100>; 70 enable-method = "psci"; 71 next-level-cache = <&L2_0>; 72 qcom,freq-domain = <&cpufreq_hw 0>; 73 }; 74 75 CPU3: cpu@3 { 76 device_type = "cpu"; 77 compatible = "qcom,kryo260"; 78 reg = <0x0 0x3>; 79 capacity-dmips-mhz = <1024>; 80 dynamic-power-coefficient = <100>; 81 enable-method = "psci"; 82 next-level-cache = <&L2_0>; 83 qcom,freq-domain = <&cpufreq_hw 0>; 84 }; 85 86 CPU4: cpu@100 { 87 device_type = "cpu"; 88 compatible = "qcom,kryo260"; 89 reg = <0x0 0x100>; 90 enable-method = "psci"; 91 capacity-dmips-mhz = <1638>; 92 dynamic-power-coefficient = <282>; 93 next-level-cache = <&L2_1>; 94 qcom,freq-domain = <&cpufreq_hw 1>; 95 L2_1: l2-cache { 96 compatible = "cache"; 97 cache-level = <2>; 98 }; 99 }; 100 101 CPU5: cpu@101 { 102 device_type = "cpu"; 103 compatible = "qcom,kryo260"; 104 reg = <0x0 0x101>; 105 capacity-dmips-mhz = <1638>; 106 dynamic-power-coefficient = <282>; 107 enable-method = "psci"; 108 next-level-cache = <&L2_1>; 109 qcom,freq-domain = <&cpufreq_hw 1>; 110 }; 111 112 CPU6: cpu@102 { 113 device_type = "cpu"; 114 compatible = "qcom,kryo260"; 115 reg = <0x0 0x102>; 116 capacity-dmips-mhz = <1638>; 117 dynamic-power-coefficient = <282>; 118 enable-method = "psci"; 119 next-level-cache = <&L2_1>; 120 qcom,freq-domain = <&cpufreq_hw 1>; 121 }; 122 123 CPU7: cpu@103 { 124 device_type = "cpu"; 125 compatible = "qcom,kryo260"; 126 reg = <0x0 0x103>; 127 capacity-dmips-mhz = <1638>; 128 dynamic-power-coefficient = <282>; 129 enable-method = "psci"; 130 next-level-cache = <&L2_1>; 131 qcom,freq-domain = <&cpufreq_hw 1>; 132 }; 133 134 cpu-map { 135 cluster0 { 136 core0 { 137 cpu = <&CPU0>; 138 }; 139 140 core1 { 141 cpu = <&CPU1>; 142 }; 143 144 core2 { 145 cpu = <&CPU2>; 146 }; 147 148 core3 { 149 cpu = <&CPU3>; 150 }; 151 }; 152 153 cluster1 { 154 core0 { 155 cpu = <&CPU4>; 156 }; 157 158 core1 { 159 cpu = <&CPU5>; 160 }; 161 162 core2 { 163 cpu = <&CPU6>; 164 }; 165 166 core3 { 167 cpu = <&CPU7>; 168 }; 169 }; 170 }; 171 }; 172 173 firmware { 174 scm: scm { 175 compatible = "qcom,scm-sm6115", "qcom,scm"; 176 #reset-cells = <1>; 177 }; 178 }; 179 180 memory@80000000 { 181 device_type = "memory"; 182 /* We expect the bootloader to fill in the size */ 183 reg = <0 0x80000000 0 0>; 184 }; 185 186 pmu { 187 compatible = "arm,armv8-pmuv3"; 188 interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>; 189 }; 190 191 psci { 192 compatible = "arm,psci-1.0"; 193 method = "smc"; 194 }; 195 196 reserved_memory: reserved-memory { 197 #address-cells = <2>; 198 #size-cells = <2>; 199 ranges; 200 201 hyp_mem: memory@45700000 { 202 reg = <0x0 0x45700000 0x0 0x600000>; 203 no-map; 204 }; 205 206 xbl_aop_mem: memory@45e00000 { 207 reg = <0x0 0x45e00000 0x0 0x140000>; 208 no-map; 209 }; 210 211 sec_apps_mem: memory@45fff000 { 212 reg = <0x0 0x45fff000 0x0 0x1000>; 213 no-map; 214 }; 215 216 smem_mem: memory@46000000 { 217 compatible = "qcom,smem"; 218 reg = <0x0 0x46000000 0x0 0x200000>; 219 no-map; 220 221 hwlocks = <&tcsr_mutex 3>; 222 qcom,rpm-msg-ram = <&rpm_msg_ram>; 223 }; 224 225 cdsp_sec_mem: memory@46200000 { 226 reg = <0x0 0x46200000 0x0 0x1e00000>; 227 no-map; 228 }; 229 230 pil_modem_mem: memory@4ab00000 { 231 reg = <0x0 0x4ab00000 0x0 0x6900000>; 232 no-map; 233 }; 234 235 pil_video_mem: memory@51400000 { 236 reg = <0x0 0x51400000 0x0 0x500000>; 237 no-map; 238 }; 239 240 wlan_msa_mem: memory@51900000 { 241 reg = <0x0 0x51900000 0x0 0x100000>; 242 no-map; 243 }; 244 245 pil_cdsp_mem: memory@51a00000 { 246 reg = <0x0 0x51a00000 0x0 0x1e00000>; 247 no-map; 248 }; 249 250 pil_adsp_mem: memory@53800000 { 251 reg = <0x0 0x53800000 0x0 0x2800000>; 252 no-map; 253 }; 254 255 pil_ipa_fw_mem: memory@56100000 { 256 reg = <0x0 0x56100000 0x0 0x10000>; 257 no-map; 258 }; 259 260 pil_ipa_gsi_mem: memory@56110000 { 261 reg = <0x0 0x56110000 0x0 0x5000>; 262 no-map; 263 }; 264 265 pil_gpu_mem: memory@56115000 { 266 reg = <0x0 0x56115000 0x0 0x2000>; 267 no-map; 268 }; 269 270 cont_splash_memory: memory@5c000000 { 271 reg = <0x0 0x5c000000 0x0 0x00f00000>; 272 no-map; 273 }; 274 275 dfps_data_memory: memory@5cf00000 { 276 reg = <0x0 0x5cf00000 0x0 0x0100000>; 277 no-map; 278 }; 279 280 removed_mem: memory@60000000 { 281 reg = <0x0 0x60000000 0x0 0x3900000>; 282 no-map; 283 }; 284 }; 285 286 rpm-glink { 287 compatible = "qcom,glink-rpm"; 288 289 interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>; 290 qcom,rpm-msg-ram = <&rpm_msg_ram>; 291 mboxes = <&apcs_glb 0>; 292 293 rpm_requests: rpm-requests { 294 compatible = "qcom,rpm-sm6115"; 295 qcom,glink-channels = "rpm_requests"; 296 297 rpmcc: clock-controller { 298 compatible = "qcom,rpmcc-sm6115", "qcom,rpmcc"; 299 #clock-cells = <1>; 300 }; 301 302 rpmpd: power-controller { 303 compatible = "qcom,sm6115-rpmpd"; 304 #power-domain-cells = <1>; 305 operating-points-v2 = <&rpmpd_opp_table>; 306 307 rpmpd_opp_table: opp-table { 308 compatible = "operating-points-v2"; 309 310 rpmpd_opp_min_svs: opp1 { 311 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 312 }; 313 314 rpmpd_opp_low_svs: opp2 { 315 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 316 }; 317 318 rpmpd_opp_svs: opp3 { 319 opp-level = <RPM_SMD_LEVEL_SVS>; 320 }; 321 322 rpmpd_opp_svs_plus: opp4 { 323 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 324 }; 325 326 rpmpd_opp_nom: opp5 { 327 opp-level = <RPM_SMD_LEVEL_NOM>; 328 }; 329 330 rpmpd_opp_nom_plus: opp6 { 331 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 332 }; 333 334 rpmpd_opp_turbo: opp7 { 335 opp-level = <RPM_SMD_LEVEL_TURBO>; 336 }; 337 338 rpmpd_opp_turbo_plus: opp8 { 339 opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>; 340 }; 341 }; 342 }; 343 }; 344 }; 345 346 soc: soc@0 { 347 compatible = "simple-bus"; 348 #address-cells = <1>; 349 #size-cells = <1>; 350 ranges = <0 0 0 0xffffffff>; 351 352 tcsr_mutex: hwlock@340000 { 353 compatible = "qcom,tcsr-mutex"; 354 reg = <0x00340000 0x20000>; 355 #hwlock-cells = <1>; 356 }; 357 358 tlmm: pinctrl@500000 { 359 compatible = "qcom,sm6115-tlmm"; 360 reg = <0x00500000 0x400000>, <0x00900000 0x400000>, <0x00d00000 0x400000>; 361 reg-names = "west", "south", "east"; 362 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 363 gpio-controller; 364 gpio-ranges = <&tlmm 0 0 121>; 365 #gpio-cells = <2>; 366 interrupt-controller; 367 #interrupt-cells = <2>; 368 369 qup_i2c0_default: qup-i2c0-default-state { 370 pins = "gpio0", "gpio1"; 371 function = "qup0"; 372 drive-strength = <2>; 373 bias-pull-up; 374 }; 375 376 qup_i2c1_default: qup-i2c1-default-state { 377 pins = "gpio4", "gpio5"; 378 function = "qup1"; 379 drive-strength = <2>; 380 bias-pull-up; 381 }; 382 383 qup_i2c2_default: qup-i2c2-default-state { 384 pins = "gpio6", "gpio7"; 385 function = "qup2"; 386 drive-strength = <2>; 387 bias-pull-up; 388 }; 389 390 qup_i2c3_default: qup-i2c3-default-state { 391 pins = "gpio8", "gpio9"; 392 function = "qup3"; 393 drive-strength = <2>; 394 bias-pull-up; 395 }; 396 397 qup_i2c4_default: qup-i2c4-default-state { 398 pins = "gpio12", "gpio13"; 399 function = "qup4"; 400 drive-strength = <2>; 401 bias-pull-up; 402 }; 403 404 qup_i2c5_default: qup-i2c5-default-state { 405 pins = "gpio14", "gpio15"; 406 function = "qup5"; 407 drive-strength = <2>; 408 bias-pull-up; 409 }; 410 411 qup_spi0_default: qup-spi0-default-state { 412 pins = "gpio0", "gpio1","gpio2", "gpio3"; 413 function = "qup0"; 414 drive-strength = <2>; 415 bias-pull-up; 416 }; 417 418 qup_spi1_default: qup-spi1-default-state { 419 pins = "gpio4", "gpio5", "gpio69", "gpio70"; 420 function = "qup1"; 421 drive-strength = <2>; 422 bias-pull-up; 423 }; 424 425 qup_spi2_default: qup-spi2-default-state { 426 pins = "gpio6", "gpio7", "gpio71", "gpio80"; 427 function = "qup2"; 428 drive-strength = <2>; 429 bias-pull-up; 430 }; 431 432 qup_spi3_default: qup-spi3-default-state { 433 pins = "gpio8", "gpio9", "gpio10", "gpio11"; 434 function = "qup3"; 435 drive-strength = <2>; 436 bias-pull-up; 437 }; 438 439 qup_spi4_default: qup-spi4-default-state { 440 pins = "gpio12", "gpio13", "gpio96", "gpio97"; 441 function = "qup4"; 442 drive-strength = <2>; 443 bias-pull-up; 444 }; 445 446 qup_spi5_default: qup-spi5-default-state { 447 pins = "gpio14", "gpio15", "gpio16", "gpio17"; 448 function = "qup5"; 449 drive-strength = <2>; 450 bias-pull-up; 451 }; 452 453 sdc1_state_on: sdc1-on-state { 454 clk-pins { 455 pins = "sdc1_clk"; 456 bias-disable; 457 drive-strength = <16>; 458 }; 459 460 cmd-pins { 461 pins = "sdc1_cmd"; 462 bias-pull-up; 463 drive-strength = <10>; 464 }; 465 466 data-pins { 467 pins = "sdc1_data"; 468 bias-pull-up; 469 drive-strength = <10>; 470 }; 471 472 rclk-pins { 473 pins = "sdc1_rclk"; 474 bias-pull-down; 475 }; 476 }; 477 478 sdc1_state_off: sdc1-off-state { 479 clk-pins { 480 pins = "sdc1_clk"; 481 bias-disable; 482 drive-strength = <2>; 483 }; 484 485 cmd-pins { 486 pins = "sdc1_cmd"; 487 bias-pull-up; 488 drive-strength = <2>; 489 }; 490 491 data-pins { 492 pins = "sdc1_data"; 493 bias-pull-up; 494 drive-strength = <2>; 495 }; 496 497 rclk-pins { 498 pins = "sdc1_rclk"; 499 bias-pull-down; 500 }; 501 }; 502 503 sdc2_state_on: sdc2-on-state { 504 clk-pins { 505 pins = "sdc2_clk"; 506 bias-disable; 507 drive-strength = <16>; 508 }; 509 510 cmd-pins { 511 pins = "sdc2_cmd"; 512 bias-pull-up; 513 drive-strength = <10>; 514 }; 515 516 data-pins { 517 pins = "sdc2_data"; 518 bias-pull-up; 519 drive-strength = <10>; 520 }; 521 522 sd-cd-pins { 523 pins = "gpio88"; 524 function = "gpio"; 525 bias-pull-up; 526 drive-strength = <2>; 527 }; 528 }; 529 530 sdc2_state_off: sdc2-off-state { 531 clk-pins { 532 pins = "sdc2_clk"; 533 bias-disable; 534 drive-strength = <2>; 535 }; 536 537 cmd-pins { 538 pins = "sdc2_cmd"; 539 bias-pull-up; 540 drive-strength = <2>; 541 }; 542 543 data-pins { 544 pins = "sdc2_data"; 545 bias-pull-up; 546 drive-strength = <2>; 547 }; 548 549 sd-cd-pins { 550 pins = "gpio88"; 551 function = "gpio"; 552 bias-disable; 553 drive-strength = <2>; 554 }; 555 }; 556 }; 557 558 gcc: clock-controller@1400000 { 559 compatible = "qcom,gcc-sm6115"; 560 reg = <0x01400000 0x1f0000>; 561 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>; 562 clock-names = "bi_tcxo", "sleep_clk"; 563 #clock-cells = <1>; 564 #reset-cells = <1>; 565 #power-domain-cells = <1>; 566 }; 567 568 usb_1_hsphy: phy@1613000 { 569 compatible = "qcom,sm6115-qusb2-phy"; 570 reg = <0x01613000 0x180>; 571 #phy-cells = <0>; 572 573 clocks = <&gcc GCC_AHB2PHY_USB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>; 574 clock-names = "cfg_ahb", "ref"; 575 576 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 577 nvmem-cells = <&qusb2_hstx_trim>; 578 579 status = "disabled"; 580 }; 581 582 qfprom@1b40000 { 583 compatible = "qcom,sm6115-qfprom", "qcom,qfprom"; 584 reg = <0x01b40000 0x7000>; 585 #address-cells = <1>; 586 #size-cells = <1>; 587 588 qusb2_hstx_trim: hstx-trim@25b { 589 reg = <0x25b 0x1>; 590 bits = <1 4>; 591 }; 592 }; 593 594 rng: rng@1b53000 { 595 compatible = "qcom,prng-ee"; 596 reg = <0x01b53000 0x1000>; 597 clocks = <&gcc GCC_PRNG_AHB_CLK>; 598 clock-names = "core"; 599 }; 600 601 spmi_bus: spmi@1c40000 { 602 compatible = "qcom,spmi-pmic-arb"; 603 reg = <0x01c40000 0x1100>, 604 <0x01e00000 0x2000000>, 605 <0x03e00000 0x100000>, 606 <0x03f00000 0xa0000>, 607 <0x01c0a000 0x26000>; 608 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 609 interrupt-names = "periph_irq"; 610 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 611 qcom,ee = <0>; 612 qcom,channel = <0>; 613 #address-cells = <2>; 614 #size-cells = <0>; 615 interrupt-controller; 616 #interrupt-cells = <4>; 617 }; 618 619 tsens0: thermal-sensor@4410000 { 620 compatible = "qcom,sm6115-tsens", "qcom,tsens-v2"; 621 reg = <0x04411000 0x1ff>, /* TM */ 622 <0x04410000 0x8>; /* SROT */ 623 #qcom,sensors = <16>; 624 interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 625 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 626 interrupt-names = "uplow", "critical"; 627 #thermal-sensor-cells = <1>; 628 }; 629 630 rpm_msg_ram: sram@45f0000 { 631 compatible = "qcom,rpm-msg-ram"; 632 reg = <0x045f0000 0x7000>; 633 }; 634 635 sram@4690000 { 636 compatible = "qcom,rpm-stats"; 637 reg = <0x04690000 0x10000>; 638 }; 639 640 sdhc_1: mmc@4744000 { 641 compatible = "qcom,sm6115-sdhci", "qcom,sdhci-msm-v5"; 642 reg = <0x04744000 0x1000>, <0x04745000 0x1000>, <0x04748000 0x8000>; 643 reg-names = "hc", "cqhci", "ice"; 644 645 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, 646 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 647 interrupt-names = "hc_irq", "pwr_irq"; 648 649 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 650 <&gcc GCC_SDCC1_APPS_CLK>, 651 <&xo_board>, 652 <&gcc GCC_SDCC1_ICE_CORE_CLK>; 653 clock-names = "iface", "core", "xo", "ice"; 654 655 pinctrl-0 = <&sdc1_state_on>; 656 pinctrl-1 = <&sdc1_state_off>; 657 pinctrl-names = "default", "sleep"; 658 659 bus-width = <8>; 660 status = "disabled"; 661 }; 662 663 sdhc_2: mmc@4784000 { 664 compatible = "qcom,sm6115-sdhci", "qcom,sdhci-msm-v5"; 665 reg = <0x04784000 0x1000>; 666 reg-names = "hc"; 667 668 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 669 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 670 interrupt-names = "hc_irq", "pwr_irq"; 671 672 clocks = <&gcc GCC_SDCC2_AHB_CLK>, <&gcc GCC_SDCC2_APPS_CLK>, <&xo_board>; 673 clock-names = "iface", "core", "xo"; 674 675 pinctrl-0 = <&sdc2_state_on>; 676 pinctrl-1 = <&sdc2_state_off>; 677 pinctrl-names = "default", "sleep"; 678 679 power-domains = <&rpmpd SM6115_VDDCX>; 680 operating-points-v2 = <&sdhc2_opp_table>; 681 iommus = <&apps_smmu 0x00a0 0x0>; 682 resets = <&gcc GCC_SDCC2_BCR>; 683 684 bus-width = <4>; 685 qcom,dll-config = <0x0007642c>; 686 qcom,ddr-config = <0x80040868>; 687 status = "disabled"; 688 689 sdhc2_opp_table: opp-table { 690 compatible = "operating-points-v2"; 691 692 opp-100000000 { 693 opp-hz = /bits/ 64 <100000000>; 694 required-opps = <&rpmpd_opp_low_svs>; 695 }; 696 697 opp-202000000 { 698 opp-hz = /bits/ 64 <202000000>; 699 required-opps = <&rpmpd_opp_nom>; 700 }; 701 }; 702 }; 703 704 ufs_mem_hc: ufs@4804000 { 705 compatible = "qcom,sm6115-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; 706 reg = <0x04804000 0x3000>, <0x04810000 0x8000>; 707 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 708 phys = <&ufs_mem_phy_lanes>; 709 phy-names = "ufsphy"; 710 lanes-per-direction = <1>; 711 #reset-cells = <1>; 712 resets = <&gcc GCC_UFS_PHY_BCR>; 713 reset-names = "rst"; 714 715 power-domains = <&gcc GCC_UFS_PHY_GDSC>; 716 iommus = <&apps_smmu 0x100 0>; 717 718 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 719 <&gcc GCC_SYS_NOC_UFS_PHY_AXI_CLK>, 720 <&gcc GCC_UFS_PHY_AHB_CLK>, 721 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 722 <&rpmcc RPM_SMD_XO_CLK_SRC>, 723 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 724 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 725 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 726 clock-names = "core_clk", 727 "bus_aggr_clk", 728 "iface_clk", 729 "core_clk_unipro", 730 "ref_clk", 731 "tx_lane0_sync_clk", 732 "rx_lane0_sync_clk", 733 "ice_core_clk"; 734 735 freq-table-hz = <50000000 200000000>, 736 <0 0>, 737 <0 0>, 738 <37500000 150000000>, 739 <75000000 300000000>, 740 <0 0>, 741 <0 0>, 742 <0 0>; 743 744 status = "disabled"; 745 }; 746 747 ufs_mem_phy: phy@4807000 { 748 compatible = "qcom,sm6115-qmp-ufs-phy"; 749 reg = <0x04807000 0x1c4>; 750 #address-cells = <1>; 751 #size-cells = <1>; 752 ranges; 753 754 clocks = <&gcc GCC_UFS_CLKREF_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 755 clock-names = "ref", "ref_aux"; 756 757 resets = <&ufs_mem_hc 0>; 758 reset-names = "ufsphy"; 759 status = "disabled"; 760 761 ufs_mem_phy_lanes: phy@4807400 { 762 reg = <0x4807400 0x098>, 763 <0x4807600 0x130>, 764 <0x4807c00 0x16c>; 765 #phy-cells = <0>; 766 }; 767 }; 768 769 gpi_dma0: dma-controller@4a00000 { 770 compatible = "qcom,sm6115-gpi-dma", "qcom,sm6350-gpi-dma"; 771 reg = <0x04a00000 0x60000>; 772 interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 773 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 774 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 775 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 776 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 777 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 778 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 779 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 780 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 781 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; 782 dma-channels = <10>; 783 dma-channel-mask = <0xf>; 784 iommus = <&apps_smmu 0xf6 0x0>; 785 #dma-cells = <3>; 786 status = "disabled"; 787 }; 788 789 qupv3_id_0: geniqup@4ac0000 { 790 compatible = "qcom,geni-se-qup"; 791 reg = <0x04ac0000 0x2000>; 792 clock-names = "m-ahb", "s-ahb"; 793 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 794 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 795 #address-cells = <1>; 796 #size-cells = <1>; 797 iommus = <&apps_smmu 0xe3 0x0>; 798 ranges; 799 status = "disabled"; 800 801 i2c0: i2c@4a80000 { 802 compatible = "qcom,geni-i2c"; 803 reg = <0x04a80000 0x4000>; 804 clock-names = "se"; 805 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 806 pinctrl-names = "default"; 807 pinctrl-0 = <&qup_i2c0_default>; 808 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 809 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 810 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 811 dma-names = "tx", "rx"; 812 #address-cells = <1>; 813 #size-cells = <0>; 814 status = "disabled"; 815 }; 816 817 spi0: spi@4a80000 { 818 compatible = "qcom,geni-spi"; 819 reg = <0x04a80000 0x4000>; 820 clock-names = "se"; 821 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 822 pinctrl-names = "default"; 823 pinctrl-0 = <&qup_spi0_default>; 824 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 825 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 826 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 827 dma-names = "tx", "rx"; 828 #address-cells = <1>; 829 #size-cells = <0>; 830 status = "disabled"; 831 }; 832 833 i2c1: i2c@4a84000 { 834 compatible = "qcom,geni-i2c"; 835 reg = <0x04a84000 0x4000>; 836 clock-names = "se"; 837 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 838 pinctrl-names = "default"; 839 pinctrl-0 = <&qup_i2c1_default>; 840 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 841 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 842 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 843 dma-names = "tx", "rx"; 844 #address-cells = <1>; 845 #size-cells = <0>; 846 status = "disabled"; 847 }; 848 849 spi1: spi@4a84000 { 850 compatible = "qcom,geni-spi"; 851 reg = <0x04a84000 0x4000>; 852 clock-names = "se"; 853 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 854 pinctrl-names = "default"; 855 pinctrl-0 = <&qup_spi1_default>; 856 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 857 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 858 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 859 dma-names = "tx", "rx"; 860 #address-cells = <1>; 861 #size-cells = <0>; 862 status = "disabled"; 863 }; 864 865 i2c2: i2c@4a88000 { 866 compatible = "qcom,geni-i2c"; 867 reg = <0x04a88000 0x4000>; 868 clock-names = "se"; 869 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 870 pinctrl-names = "default"; 871 pinctrl-0 = <&qup_i2c2_default>; 872 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; 873 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 874 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 875 dma-names = "tx", "rx"; 876 #address-cells = <1>; 877 #size-cells = <0>; 878 status = "disabled"; 879 }; 880 881 spi2: spi@4a88000 { 882 compatible = "qcom,geni-spi"; 883 reg = <0x04a88000 0x4000>; 884 clock-names = "se"; 885 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 886 pinctrl-names = "default"; 887 pinctrl-0 = <&qup_spi2_default>; 888 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; 889 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 890 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 891 dma-names = "tx", "rx"; 892 #address-cells = <1>; 893 #size-cells = <0>; 894 status = "disabled"; 895 }; 896 897 i2c3: i2c@4a8c000 { 898 compatible = "qcom,geni-i2c"; 899 reg = <0x04a8c000 0x4000>; 900 clock-names = "se"; 901 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 902 pinctrl-names = "default"; 903 pinctrl-0 = <&qup_i2c3_default>; 904 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 905 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 906 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 907 dma-names = "tx", "rx"; 908 #address-cells = <1>; 909 #size-cells = <0>; 910 status = "disabled"; 911 }; 912 913 spi3: spi@4a8c000 { 914 compatible = "qcom,geni-spi"; 915 reg = <0x04a8c000 0x4000>; 916 clock-names = "se"; 917 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 918 pinctrl-names = "default"; 919 pinctrl-0 = <&qup_spi3_default>; 920 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 921 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 922 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 923 dma-names = "tx", "rx"; 924 #address-cells = <1>; 925 #size-cells = <0>; 926 status = "disabled"; 927 }; 928 929 i2c4: i2c@4a90000 { 930 compatible = "qcom,geni-i2c"; 931 reg = <0x04a90000 0x4000>; 932 clock-names = "se"; 933 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 934 pinctrl-names = "default"; 935 pinctrl-0 = <&qup_i2c4_default>; 936 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 937 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 938 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 939 dma-names = "tx", "rx"; 940 #address-cells = <1>; 941 #size-cells = <0>; 942 status = "disabled"; 943 }; 944 945 spi4: spi@4a90000 { 946 compatible = "qcom,geni-spi"; 947 reg = <0x04a90000 0x4000>; 948 clock-names = "se"; 949 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 950 pinctrl-names = "default"; 951 pinctrl-0 = <&qup_spi4_default>; 952 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 953 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 954 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 955 dma-names = "tx", "rx"; 956 #address-cells = <1>; 957 #size-cells = <0>; 958 status = "disabled"; 959 }; 960 961 i2c5: i2c@4a94000 { 962 compatible = "qcom,geni-i2c"; 963 reg = <0x04a94000 0x4000>; 964 clock-names = "se"; 965 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 966 pinctrl-names = "default"; 967 pinctrl-0 = <&qup_i2c5_default>; 968 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; 969 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 970 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 971 dma-names = "tx", "rx"; 972 #address-cells = <1>; 973 #size-cells = <0>; 974 status = "disabled"; 975 }; 976 977 spi5: spi@4a94000 { 978 compatible = "qcom,geni-spi"; 979 reg = <0x04a94000 0x4000>; 980 clock-names = "se"; 981 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 982 pinctrl-names = "default"; 983 pinctrl-0 = <&qup_spi5_default>; 984 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; 985 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 986 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 987 dma-names = "tx", "rx"; 988 #address-cells = <1>; 989 #size-cells = <0>; 990 status = "disabled"; 991 }; 992 }; 993 994 usb_1: usb@4ef8800 { 995 compatible = "qcom,sm6115-dwc3", "qcom,dwc3"; 996 reg = <0x04ef8800 0x400>; 997 #address-cells = <1>; 998 #size-cells = <1>; 999 ranges; 1000 1001 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 1002 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 1003 <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>, 1004 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 1005 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1006 <&gcc GCC_USB3_PRIM_CLKREF_CLK>; 1007 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", "xo"; 1008 1009 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1010 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 1011 assigned-clock-rates = <19200000>, <66666667>; 1012 1013 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 1014 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>; 1015 interrupt-names = "hs_phy_irq", "ss_phy_irq"; 1016 1017 resets = <&gcc GCC_USB30_PRIM_BCR>; 1018 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 1019 qcom,select-utmi-as-pipe-clk; 1020 status = "disabled"; 1021 1022 usb_1_dwc3: usb@4e00000 { 1023 compatible = "snps,dwc3"; 1024 reg = <0x04e00000 0xcd00>; 1025 interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 1026 phys = <&usb_1_hsphy>; 1027 phy-names = "usb2-phy"; 1028 iommus = <&apps_smmu 0x120 0x0>; 1029 snps,dis_u2_susphy_quirk; 1030 snps,dis_enblslpm_quirk; 1031 snps,has-lpm-erratum; 1032 snps,hird-threshold = /bits/ 8 <0x10>; 1033 snps,usb3_lpm_capable; 1034 maximum-speed = "high-speed"; 1035 dr_mode = "peripheral"; 1036 }; 1037 }; 1038 1039 mdss: display-subsystem@5e00000 { 1040 compatible = "qcom,sm6115-mdss"; 1041 reg = <0x05e00000 0x1000>; 1042 reg-names = "mdss"; 1043 1044 power-domains = <&dispcc MDSS_GDSC>; 1045 1046 clocks = <&gcc GCC_DISP_AHB_CLK>, 1047 <&gcc GCC_DISP_HF_AXI_CLK>, 1048 <&dispcc DISP_CC_MDSS_MDP_CLK>; 1049 1050 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 1051 interrupt-controller; 1052 #interrupt-cells = <1>; 1053 1054 iommus = <&apps_smmu 0x420 0x2>, 1055 <&apps_smmu 0x421 0x0>; 1056 1057 #address-cells = <1>; 1058 #size-cells = <1>; 1059 ranges; 1060 1061 status = "disabled"; 1062 1063 mdp: display-controller@5e01000 { 1064 compatible = "qcom,sm6115-dpu"; 1065 reg = <0x05e01000 0x8f000>, 1066 <0x05eb0000 0x2008>; 1067 reg-names = "mdp", "vbif"; 1068 1069 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 1070 <&dispcc DISP_CC_MDSS_AHB_CLK>, 1071 <&dispcc DISP_CC_MDSS_MDP_CLK>, 1072 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 1073 <&dispcc DISP_CC_MDSS_ROT_CLK>, 1074 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 1075 clock-names = "bus", 1076 "iface", 1077 "core", 1078 "lut", 1079 "rot", 1080 "vsync"; 1081 1082 operating-points-v2 = <&mdp_opp_table>; 1083 power-domains = <&rpmpd SM6115_VDDCX>; 1084 1085 interrupt-parent = <&mdss>; 1086 interrupts = <0>; 1087 1088 ports { 1089 #address-cells = <1>; 1090 #size-cells = <0>; 1091 1092 port@0 { 1093 reg = <0>; 1094 dpu_intf1_out: endpoint { 1095 remote-endpoint = <&dsi0_in>; 1096 }; 1097 }; 1098 }; 1099 1100 mdp_opp_table: opp-table { 1101 compatible = "operating-points-v2"; 1102 1103 opp-19200000 { 1104 opp-hz = /bits/ 64 <19200000>; 1105 required-opps = <&rpmpd_opp_min_svs>; 1106 }; 1107 1108 opp-192000000 { 1109 opp-hz = /bits/ 64 <192000000>; 1110 required-opps = <&rpmpd_opp_low_svs>; 1111 }; 1112 1113 opp-256000000 { 1114 opp-hz = /bits/ 64 <256000000>; 1115 required-opps = <&rpmpd_opp_svs>; 1116 }; 1117 1118 opp-307200000 { 1119 opp-hz = /bits/ 64 <307200000>; 1120 required-opps = <&rpmpd_opp_svs_plus>; 1121 }; 1122 1123 opp-384000000 { 1124 opp-hz = /bits/ 64 <384000000>; 1125 required-opps = <&rpmpd_opp_nom>; 1126 }; 1127 }; 1128 }; 1129 1130 dsi0: dsi@5e94000 { 1131 compatible = "qcom,dsi-ctrl-6g-qcm2290"; 1132 reg = <0x05e94000 0x400>; 1133 reg-names = "dsi_ctrl"; 1134 1135 interrupt-parent = <&mdss>; 1136 interrupts = <4>; 1137 1138 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 1139 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 1140 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 1141 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 1142 <&dispcc DISP_CC_MDSS_AHB_CLK>, 1143 <&gcc GCC_DISP_HF_AXI_CLK>; 1144 clock-names = "byte", 1145 "byte_intf", 1146 "pixel", 1147 "core", 1148 "iface", 1149 "bus"; 1150 1151 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 1152 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 1153 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; 1154 1155 operating-points-v2 = <&dsi_opp_table>; 1156 power-domains = <&rpmpd SM6115_VDDCX>; 1157 phys = <&dsi0_phy>; 1158 1159 #address-cells = <1>; 1160 #size-cells = <0>; 1161 1162 status = "disabled"; 1163 1164 ports { 1165 #address-cells = <1>; 1166 #size-cells = <0>; 1167 1168 port@0 { 1169 reg = <0>; 1170 dsi0_in: endpoint { 1171 remote-endpoint = <&dpu_intf1_out>; 1172 }; 1173 }; 1174 1175 port@1 { 1176 reg = <1>; 1177 dsi0_out: endpoint { 1178 }; 1179 }; 1180 }; 1181 1182 dsi_opp_table: opp-table { 1183 compatible = "operating-points-v2"; 1184 1185 opp-19200000 { 1186 opp-hz = /bits/ 64 <19200000>; 1187 required-opps = <&rpmpd_opp_min_svs>; 1188 }; 1189 1190 opp-164000000 { 1191 opp-hz = /bits/ 64 <164000000>; 1192 required-opps = <&rpmpd_opp_low_svs>; 1193 }; 1194 1195 opp-187500000 { 1196 opp-hz = /bits/ 64 <187500000>; 1197 required-opps = <&rpmpd_opp_svs>; 1198 }; 1199 }; 1200 }; 1201 1202 dsi0_phy: phy@5e94400 { 1203 compatible = "qcom,dsi-phy-14nm-2290"; 1204 reg = <0x05e94400 0x100>, 1205 <0x05e94500 0x300>, 1206 <0x05e94800 0x188>; 1207 reg-names = "dsi_phy", 1208 "dsi_phy_lane", 1209 "dsi_pll"; 1210 1211 #clock-cells = <1>; 1212 #phy-cells = <0>; 1213 1214 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 1215 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1216 clock-names = "iface", "ref"; 1217 1218 status = "disabled"; 1219 }; 1220 }; 1221 1222 dispcc: clock-controller@5f00000 { 1223 compatible = "qcom,sm6115-dispcc"; 1224 reg = <0x05f00000 0x20000>; 1225 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 1226 <&sleep_clk>, 1227 <&dsi0_phy 0>, 1228 <&dsi0_phy 1>, 1229 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>; 1230 #clock-cells = <1>; 1231 #reset-cells = <1>; 1232 #power-domain-cells = <1>; 1233 }; 1234 1235 apps_smmu: iommu@c600000 { 1236 compatible = "qcom,sm6115-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 1237 reg = <0x0c600000 0x80000>; 1238 #iommu-cells = <2>; 1239 #global-interrupts = <1>; 1240 1241 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 1242 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 1243 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 1244 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 1245 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 1246 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 1247 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 1248 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 1249 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 1250 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 1251 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 1252 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 1253 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 1254 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 1255 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 1256 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 1257 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 1258 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 1259 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 1260 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 1261 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 1262 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 1263 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 1264 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1265 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 1266 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 1267 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 1268 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 1269 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 1270 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1271 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1272 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1273 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 1274 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1275 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1276 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1277 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1278 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1279 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1280 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1281 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 1282 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 1283 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 1284 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 1285 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 1286 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 1287 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1288 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 1289 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1290 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 1291 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 1292 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 1293 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 1294 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 1295 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 1296 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1297 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 1298 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1299 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1300 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1301 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1302 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 1303 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 1304 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 1305 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 1306 }; 1307 1308 wifi: wifi@c800000 { 1309 compatible = "qcom,wcn3990-wifi"; 1310 reg = <0x0c800000 0x800000>; 1311 reg-names = "membase"; 1312 memory-region = <&wlan_msa_mem>; 1313 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, 1314 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, 1315 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, 1316 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>, 1317 <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>, 1318 <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>, 1319 <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>, 1320 <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>, 1321 <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>, 1322 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>, 1323 <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, 1324 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1325 iommus = <&apps_smmu 0x1a0 0x1>; 1326 qcom,msa-fixed-perm; 1327 status = "disabled"; 1328 }; 1329 1330 apcs_glb: mailbox@f111000 { 1331 compatible = "qcom,sm6115-apcs-hmss-global"; 1332 reg = <0x0f111000 0x1000>; 1333 1334 #mbox-cells = <1>; 1335 }; 1336 1337 timer@f120000 { 1338 compatible = "arm,armv7-timer-mem"; 1339 reg = <0x0f120000 0x1000>; 1340 #address-cells = <1>; 1341 #size-cells = <1>; 1342 ranges; 1343 clock-frequency = <19200000>; 1344 1345 frame@f121000 { 1346 reg = <0x0f121000 0x1000>, <0x0f122000 0x1000>; 1347 frame-number = <0>; 1348 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1349 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 1350 }; 1351 1352 frame@f123000 { 1353 reg = <0x0f123000 0x1000>; 1354 frame-number = <1>; 1355 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1356 status = "disabled"; 1357 }; 1358 1359 frame@f124000 { 1360 reg = <0x0f124000 0x1000>; 1361 frame-number = <2>; 1362 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1363 status = "disabled"; 1364 }; 1365 1366 frame@f125000 { 1367 reg = <0x0f125000 0x1000>; 1368 frame-number = <3>; 1369 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1370 status = "disabled"; 1371 }; 1372 1373 frame@f126000 { 1374 reg = <0x0f126000 0x1000>; 1375 frame-number = <4>; 1376 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1377 status = "disabled"; 1378 }; 1379 1380 frame@f127000 { 1381 reg = <0x0f127000 0x1000>; 1382 frame-number = <5>; 1383 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1384 status = "disabled"; 1385 }; 1386 1387 frame@f128000 { 1388 reg = <0x0f128000 0x1000>; 1389 frame-number = <6>; 1390 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1391 status = "disabled"; 1392 }; 1393 }; 1394 1395 intc: interrupt-controller@f200000 { 1396 compatible = "arm,gic-v3"; 1397 reg = <0x0f200000 0x10000>, <0x0f300000 0x100000>; 1398 #interrupt-cells = <3>; 1399 interrupt-controller; 1400 interrupt-parent = <&intc>; 1401 #redistributor-regions = <1>; 1402 redistributor-stride = <0x0 0x20000>; 1403 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 1404 }; 1405 1406 cpufreq_hw: cpufreq@f521000 { 1407 compatible = "qcom,cpufreq-hw"; 1408 reg = <0x0f521000 0x1000>, <0x0f523000 0x1000>; 1409 1410 reg-names = "freq-domain0", "freq-domain1"; 1411 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>; 1412 clock-names = "xo", "alternate"; 1413 1414 #freq-domain-cells = <1>; 1415 }; 1416 }; 1417 1418 timer { 1419 compatible = "arm,armv8-timer"; 1420 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1421 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1422 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1423 <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 1424 }; 1425}; 1426