1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * SDX75 SoC device tree source 4 * 5 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 6 * 7 */ 8 9#include <dt-bindings/clock/qcom,rpmh.h> 10#include <dt-bindings/clock/qcom,sdx75-gcc.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/soc/qcom,rpmh-rsc.h> 13 14/ { 15 #address-cells = <2>; 16 #size-cells = <2>; 17 interrupt-parent = <&intc>; 18 19 chosen: chosen { }; 20 21 clocks { 22 xo_board: xo-board { 23 compatible = "fixed-clock"; 24 clock-frequency = <76800000>; 25 #clock-cells = <0>; 26 }; 27 28 sleep_clk: sleep-clk { 29 compatible = "fixed-clock"; 30 clock-frequency = <32000>; 31 #clock-cells = <0>; 32 }; 33 }; 34 35 cpus { 36 #address-cells = <2>; 37 #size-cells = <0>; 38 39 CPU0: cpu@0 { 40 device_type = "cpu"; 41 compatible = "arm,cortex-a55"; 42 reg = <0x0 0x0>; 43 clocks = <&cpufreq_hw 0>; 44 enable-method = "psci"; 45 power-domains = <&CPU_PD0>; 46 power-domain-names = "psci"; 47 qcom,freq-domain = <&cpufreq_hw 0>; 48 capacity-dmips-mhz = <1024>; 49 dynamic-power-coefficient = <100>; 50 next-level-cache = <&L2_0>; 51 52 L2_0: l2-cache { 53 compatible = "cache"; 54 cache-level = <2>; 55 cache-unified; 56 next-level-cache = <&L3_0>; 57 L3_0: l3-cache { 58 compatible = "cache"; 59 cache-level = <3>; 60 cache-unified; 61 }; 62 }; 63 }; 64 65 CPU1: cpu@100 { 66 device_type = "cpu"; 67 compatible = "arm,cortex-a55"; 68 reg = <0x0 0x100>; 69 clocks = <&cpufreq_hw 0>; 70 enable-method = "psci"; 71 power-domains = <&CPU_PD1>; 72 power-domain-names = "psci"; 73 qcom,freq-domain = <&cpufreq_hw 0>; 74 capacity-dmips-mhz = <1024>; 75 dynamic-power-coefficient = <100>; 76 next-level-cache = <&L2_100>; 77 78 L2_100: l2-cache { 79 compatible = "cache"; 80 cache-level = <2>; 81 cache-unified; 82 next-level-cache = <&L3_0>; 83 }; 84 }; 85 86 CPU2: cpu@200 { 87 device_type = "cpu"; 88 compatible = "arm,cortex-a55"; 89 reg = <0x0 0x200>; 90 clocks = <&cpufreq_hw 0>; 91 enable-method = "psci"; 92 power-domains = <&CPU_PD2>; 93 power-domain-names = "psci"; 94 qcom,freq-domain = <&cpufreq_hw 0>; 95 capacity-dmips-mhz = <1024>; 96 dynamic-power-coefficient = <100>; 97 next-level-cache = <&L2_200>; 98 99 L2_200: l2-cache { 100 compatible = "cache"; 101 cache-level = <2>; 102 cache-unified; 103 next-level-cache = <&L3_0>; 104 }; 105 }; 106 107 CPU3: cpu@300 { 108 device_type = "cpu"; 109 compatible = "arm,cortex-a55"; 110 reg = <0x0 0x300>; 111 clocks = <&cpufreq_hw 0>; 112 enable-method = "psci"; 113 power-domains = <&CPU_PD3>; 114 power-domain-names = "psci"; 115 qcom,freq-domain = <&cpufreq_hw 0>; 116 capacity-dmips-mhz = <1024>; 117 dynamic-power-coefficient = <100>; 118 next-level-cache = <&L2_300>; 119 120 L2_300: l2-cache { 121 compatible = "cache"; 122 cache-level = <2>; 123 cache-unified; 124 next-level-cache = <&L3_0>; 125 }; 126 }; 127 128 cpu-map { 129 cluster0 { 130 core0 { 131 cpu = <&CPU0>; 132 }; 133 134 core1 { 135 cpu = <&CPU1>; 136 }; 137 138 core2 { 139 cpu = <&CPU2>; 140 }; 141 142 core3 { 143 cpu = <&CPU3>; 144 }; 145 }; 146 }; 147 148 idle-states { 149 entry-method = "psci"; 150 151 CPU_OFF: cpu-sleep-0 { 152 compatible = "arm,idle-state"; 153 entry-latency-us = <235>; 154 exit-latency-us = <428>; 155 min-residency-us = <1774>; 156 arm,psci-suspend-param = <0x40000003>; 157 local-timer-stop; 158 }; 159 160 CPU_RAIL_OFF: cpu-rail-sleep-1 { 161 compatible = "arm,idle-state"; 162 entry-latency-us = <800>; 163 exit-latency-us = <750>; 164 min-residency-us = <4090>; 165 arm,psci-suspend-param = <0x40000004>; 166 local-timer-stop; 167 }; 168 169 }; 170 171 domain-idle-states { 172 CLUSTER_SLEEP_0: cluster-sleep-0 { 173 compatible = "domain-idle-state"; 174 arm,psci-suspend-param = <0x41000044>; 175 entry-latency-us = <1050>; 176 exit-latency-us = <2500>; 177 min-residency-us = <5309>; 178 }; 179 180 CLUSTER_SLEEP_1: cluster-sleep-1 { 181 compatible = "domain-idle-state"; 182 arm,psci-suspend-param = <0x41001344>; 183 entry-latency-us = <2761>; 184 exit-latency-us = <3964>; 185 min-residency-us = <8467>; 186 }; 187 188 CLUSTER_SLEEP_2: cluster-sleep-2 { 189 compatible = "domain-idle-state"; 190 arm,psci-suspend-param = <0x4100b344>; 191 entry-latency-us = <2793>; 192 exit-latency-us = <4023>; 193 min-residency-us = <9826>; 194 }; 195 }; 196 }; 197 198 firmware { 199 scm: scm { 200 compatible = "qcom,scm-sdx75", "qcom,scm"; 201 }; 202 }; 203 204 memory@80000000 { 205 device_type = "memory"; 206 reg = <0x0 0x80000000 0x0 0x0>; 207 }; 208 209 pmu { 210 compatible = "arm,armv8-pmuv3"; 211 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 212 }; 213 214 psci { 215 compatible = "arm,psci-1.0"; 216 method = "smc"; 217 218 CPU_PD0: power-domain-cpu0 { 219 #power-domain-cells = <0>; 220 power-domains = <&CLUSTER_PD>; 221 domain-idle-states = <&CPU_OFF &CPU_RAIL_OFF>; 222 }; 223 224 CPU_PD1: power-domain-cpu1 { 225 #power-domain-cells = <0>; 226 power-domains = <&CLUSTER_PD>; 227 domain-idle-states = <&CPU_OFF &CPU_RAIL_OFF>; 228 }; 229 230 CPU_PD2: power-domain-cpu2 { 231 #power-domain-cells = <0>; 232 power-domains = <&CLUSTER_PD>; 233 domain-idle-states = <&CPU_OFF &CPU_RAIL_OFF>; 234 }; 235 236 CPU_PD3: power-domain-cpu3 { 237 #power-domain-cells = <0>; 238 power-domains = <&CLUSTER_PD>; 239 domain-idle-states = <&CPU_OFF &CPU_RAIL_OFF>; 240 }; 241 242 CLUSTER_PD: power-domain-cpu-cluster0 { 243 #power-domain-cells = <0>; 244 domain-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_1 &CLUSTER_SLEEP_2>; 245 }; 246 }; 247 248 reserved-memory { 249 #address-cells = <2>; 250 #size-cells = <2>; 251 ranges; 252 253 gunyah_hyp_mem: gunyah-hyp@80000000 { 254 reg = <0x0 0x80000000 0x0 0x800000>; 255 no-map; 256 }; 257 258 hyp_elf_package_mem: hyp-elf-package@80800000 { 259 reg = <0x0 0x80800000 0x0 0x200000>; 260 no-map; 261 }; 262 263 access_control_db_mem: access-control-db@81380000 { 264 reg = <0x0 0x81380000 0x0 0x80000>; 265 no-map; 266 }; 267 268 qteetz_mem: qteetz@814e0000 { 269 reg = <0x0 0x814e0000 0x0 0x2a0000>; 270 no-map; 271 }; 272 273 trusted_apps_mem: trusted-apps@81780000 { 274 reg = <0x0 0x81780000 0x0 0xa00000>; 275 no-map; 276 }; 277 278 xbl_ramdump_mem: xbl-ramdump@87a00000 { 279 reg = <0x0 0x87a00000 0x0 0x1c0000>; 280 no-map; 281 }; 282 283 cpucp_fw_mem: cpucp-fw@87c00000 { 284 reg = <0x0 0x87c00000 0x0 0x100000>; 285 no-map; 286 }; 287 288 xbl_dtlog_mem: xbl-dtlog@87d00000 { 289 reg = <0x0 0x87d00000 0x0 0x40000>; 290 no-map; 291 }; 292 293 xbl_sc_mem: xbl-sc@87d40000 { 294 reg = <0x0 0x87d40000 0x0 0x40000>; 295 no-map; 296 }; 297 298 modem_efs_shared_mem: modem-efs-shared@87d80000 { 299 reg = <0x0 0x87d80000 0x0 0x10000>; 300 no-map; 301 }; 302 303 aop_image_mem: aop-image@87e00000 { 304 reg = <0x0 0x87e00000 0x0 0x20000>; 305 no-map; 306 }; 307 308 smem_mem: smem@87e20000 { 309 reg = <0x0 0x87e20000 0x0 0xc0000>; 310 no-map; 311 }; 312 313 aop_cmd_db_mem: aop-cmd-db@87ee0000 { 314 compatible = "qcom,cmd-db"; 315 reg = <0x0 0x87ee0000 0x0 0x20000>; 316 no-map; 317 }; 318 319 aop_config_mem: aop-config@87f00000 { 320 reg = <0x0 0x87f00000 0x0 0x20000>; 321 no-map; 322 }; 323 324 ipa_fw_mem: ipa-fw@87f20000 { 325 reg = <0x0 0x87f20000 0x0 0x10000>; 326 no-map; 327 }; 328 329 secdata_mem: secdata@87f30000 { 330 reg = <0x0 0x87f30000 0x0 0x1000>; 331 no-map; 332 }; 333 334 tme_crashdump_mem: tme-crashdump@87f31000 { 335 reg = <0x0 0x87f31000 0x0 0x40000>; 336 no-map; 337 }; 338 339 tme_log_mem: tme-log@87f71000 { 340 reg = <0x0 0x87f71000 0x0 0x4000>; 341 no-map; 342 }; 343 344 uefi_log_mem: uefi-log@87f75000 { 345 reg = <0x0 0x87f75000 0x0 0x10000>; 346 no-map; 347 }; 348 349 qdss_mem: qdss@88800000 { 350 reg = <0x0 0x88800000 0x0 0x300000>; 351 no-map; 352 }; 353 354 audio_heap_mem: audio-heap@88b00000 { 355 compatible = "shared-dma-pool"; 356 reg = <0x0 0x88b00000 0x0 0x400000>; 357 no-map; 358 }; 359 360 mpss_dsmharq_mem: mpss-dsmharq@88f00000 { 361 reg = <0x0 0x88f00000 0x0 0x5080000>; 362 no-map; 363 }; 364 365 q6_mpss_dtb_mem: q6-mpss-dtb@8df80000 { 366 reg = <0x0 0x8df80000 0x0 0x80000>; 367 no-map; 368 }; 369 370 mpssadsp_mem: mpssadsp@8e000000 { 371 reg = <0x0 0x8e000000 0x0 0xf400000>; 372 no-map; 373 }; 374 375 gunyah_trace_buffer_mem: gunyah-trace-buffer@bdb00000 { 376 reg = <0x0 0xbdb00000 0x0 0x2000000>; 377 no-map; 378 }; 379 380 smmu_debug_buf_mem: smmu-debug-buf@bfb00000 { 381 reg = <0x0 0xbfb00000 0x0 0x100000>; 382 no-map; 383 }; 384 385 hyp_smmu_s2_pt_mem: hyp-smmu-s2-pt@bfc00000 { 386 reg = <0x0 0xbfc00000 0x0 0x400000>; 387 no-map; 388 }; 389 }; 390 391 smem: qcom,smem { 392 compatible = "qcom,smem"; 393 memory-region = <&smem_mem>; 394 hwlocks = <&tcsr_mutex 3>; 395 }; 396 397 soc: soc { 398 compatible = "simple-bus"; 399 #address-cells = <2>; 400 #size-cells = <2>; 401 ranges = <0 0 0 0 0x10 0>; 402 dma-ranges = <0 0 0 0 0x10 0>; 403 404 gcc: clock-controller@80000 { 405 compatible = "qcom,sdx75-gcc"; 406 reg = <0x0 0x0080000 0x0 0x1f7400>; 407 clocks = <&rpmhcc RPMH_CXO_CLK>, 408 <&sleep_clk>, 409 <0>, 410 <0>, 411 <0>, 412 <0>, 413 <0>, 414 <0>, 415 <0>, 416 <0>, 417 <0>, 418 <0>, 419 <0>, 420 <0>, 421 <0>; 422 #clock-cells = <1>; 423 #reset-cells = <1>; 424 #power-domain-cells = <1>; 425 }; 426 427 qupv3_id_0: geniqup@9c0000 { 428 compatible = "qcom,geni-se-qup"; 429 reg = <0x0 0x009c0000 0x0 0x2000>; 430 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 431 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 432 clock-names = "m-ahb", 433 "s-ahb"; 434 iommus = <&apps_smmu 0xe3 0x0>; 435 #address-cells = <2>; 436 #size-cells = <2>; 437 ranges; 438 status = "disabled"; 439 440 uart1: serial@984000 { 441 compatible = "qcom,geni-debug-uart"; 442 reg = <0x0 0x00984000 0x0 0x4000>; 443 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 444 clock-names = "se"; 445 interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>; 446 pinctrl-0 = <&qupv3_se1_2uart_active>; 447 pinctrl-1 = <&qupv3_se1_2uart_sleep>; 448 pinctrl-names = "default", 449 "sleep"; 450 status = "disabled"; 451 }; 452 }; 453 454 tcsr_mutex: hwlock@1f40000 { 455 compatible = "qcom,tcsr-mutex"; 456 reg = <0x0 0x01f40000 0x0 0x40000>; 457 #hwlock-cells = <1>; 458 }; 459 460 pdc: interrupt-controller@b220000 { 461 compatible = "qcom,sdx75-pdc", "qcom,pdc"; 462 reg = <0x0 0xb220000 0x0 0x30000>, 463 <0x0 0x174000f0 0x0 0x64>; 464 qcom,pdc-ranges = <0 147 52>, 465 <52 266 32>, 466 <84 500 59>; 467 #interrupt-cells = <2>; 468 interrupt-parent = <&intc>; 469 interrupt-controller; 470 }; 471 472 tlmm: pinctrl@f000000 { 473 compatible = "qcom,sdx75-tlmm"; 474 reg = <0x0 0x0f000000 0x0 0x400000>; 475 interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>; 476 gpio-controller; 477 #gpio-cells = <2>; 478 gpio-ranges = <&tlmm 0 0 133>; 479 interrupt-controller; 480 #interrupt-cells = <2>; 481 wakeup-parent = <&pdc>; 482 483 qupv3_se1_2uart_active: qupv3-se1-2uart-active-state { 484 tx-pins { 485 pins = "gpio12"; 486 function = "qup_se1_l2_mira"; 487 drive-strength= <2>; 488 bias-disable; 489 }; 490 491 rx-pins { 492 pins = "gpio13"; 493 function = "qup_se1_l3_mira"; 494 drive-strength= <2>; 495 bias-disable; 496 }; 497 }; 498 499 qupv3_se1_2uart_sleep: qupv3-se1-2uart-sleep-state { 500 pins = "gpio12", "gpio13"; 501 function = "gpio"; 502 drive-strength = <2>; 503 bias-pull-down; 504 }; 505 }; 506 507 apps_smmu: iommu@15000000 { 508 compatible = "qcom,sdx75-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 509 reg = <0x0 0x15000000 0x0 0x40000>; 510 #iommu-cells = <2>; 511 #global-interrupts = <2>; 512 dma-coherent; 513 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 514 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 515 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 516 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 517 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, 518 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 519 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 520 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 521 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 522 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 523 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 524 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 525 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 526 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 527 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 528 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 529 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 530 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 531 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 532 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 533 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 534 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 535 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 536 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 537 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 538 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, 539 <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, 540 <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 541 <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 542 <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 543 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 544 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, 545 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 546 }; 547 548 intc: interrupt-controller@17200000 { 549 compatible = "arm,gic-v3"; 550 #interrupt-cells = <3>; 551 interrupt-controller; 552 #redistributor-regions = <1>; 553 redistributor-stride = <0x0 0x20000>; 554 reg = <0x0 0x17200000 0x0 0x10000>, 555 <0x0 0x17260000 0x0 0x80000>; 556 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 557 }; 558 559 timer@17420000 { 560 compatible = "arm,armv7-timer-mem"; 561 reg = <0x0 0x17420000 0x0 0x1000>; 562 #address-cells = <1>; 563 #size-cells = <1>; 564 ranges = <0 0 0 0x20000000>; 565 566 frame@17421000 { 567 reg = <0x17421000 0x1000>, 568 <0x17422000 0x1000>; 569 frame-number = <0>; 570 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 571 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 572 }; 573 574 frame@17423000 { 575 reg = <0x17423000 0x1000>; 576 frame-number = <1>; 577 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 578 status = "disabled"; 579 }; 580 581 frame@17425000 { 582 reg = <0x17425000 0x1000>; 583 frame-number = <2>; 584 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 585 status = "disabled"; 586 }; 587 588 frame@17427000 { 589 reg = <0x17427000 0x1000>; 590 frame-number = <3>; 591 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 592 status = "disabled"; 593 }; 594 595 frame@17429000 { 596 reg = <0x17429000 0x1000>; 597 frame-number = <4>; 598 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 599 status = "disabled"; 600 }; 601 602 frame@1742b000 { 603 reg = <0x1742b000 0x1000>; 604 frame-number = <5>; 605 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 606 status = "disabled"; 607 }; 608 609 frame@1742d000 { 610 reg = <0x1742d000 0x1000>; 611 frame-number = <6>; 612 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 613 status = "disabled"; 614 }; 615 }; 616 617 apps_rsc: rsc@17a00000 { 618 label = "apps_rsc"; 619 compatible = "qcom,rpmh-rsc"; 620 reg = <0x0 0x17a00000 0x0 0x10000>, 621 <0x0 0x17a10000 0x0 0x10000>, 622 <0x0 0x17a20000 0x0 0x10000>; 623 reg-names = "drv-0", "drv-1", "drv-2"; 624 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 625 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 626 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 627 628 power-domains = <&CLUSTER_PD>; 629 qcom,tcs-offset = <0xd00>; 630 qcom,drv-id = <2>; 631 qcom,tcs-config = <ACTIVE_TCS 3>, 632 <SLEEP_TCS 2>, 633 <WAKE_TCS 2>, 634 <CONTROL_TCS 0>; 635 636 apps_bcm_voter: bcm-voter { 637 compatible = "qcom,bcm-voter"; 638 }; 639 640 rpmhcc: clock-controller { 641 compatible = "qcom,sdx75-rpmh-clk"; 642 clocks = <&xo_board>; 643 clock-names = "xo"; 644 #clock-cells = <1>; 645 }; 646 }; 647 648 cpufreq_hw: cpufreq@17d91000 { 649 compatible = "qcom,sdx75-cpufreq-epss", "qcom,cpufreq-epss"; 650 reg = <0x0 0x17d91000 0x0 0x1000>; 651 reg-names = "freq-domain0"; 652 clocks = <&rpmhcc RPMH_CXO_CLK>, 653 <&gcc GPLL0>; 654 clock-names = "xo", 655 "alternate"; 656 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 657 interrupt-names = "dcvsh-irq-0"; 658 #freq-domain-cells = <1>; 659 #clock-cells = <1>; 660 }; 661 }; 662 663 timer { 664 compatible = "arm,armv8-timer"; 665 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 666 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 667 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 668 <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 669 }; 670}; 671