1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * SDX75 SoC device tree source 4 * 5 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 6 * 7 */ 8 9#include <dt-bindings/clock/qcom,rpmh.h> 10#include <dt-bindings/clock/qcom,sdx75-gcc.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/power/qcom,rpmhpd.h> 13#include <dt-bindings/power/qcom-rpmpd.h> 14#include <dt-bindings/soc/qcom,rpmh-rsc.h> 15 16/ { 17 #address-cells = <2>; 18 #size-cells = <2>; 19 interrupt-parent = <&intc>; 20 21 chosen: chosen { }; 22 23 clocks { 24 xo_board: xo-board { 25 compatible = "fixed-clock"; 26 clock-frequency = <76800000>; 27 #clock-cells = <0>; 28 }; 29 30 sleep_clk: sleep-clk { 31 compatible = "fixed-clock"; 32 clock-frequency = <32000>; 33 #clock-cells = <0>; 34 }; 35 }; 36 37 cpus { 38 #address-cells = <2>; 39 #size-cells = <0>; 40 41 CPU0: cpu@0 { 42 device_type = "cpu"; 43 compatible = "arm,cortex-a55"; 44 reg = <0x0 0x0>; 45 clocks = <&cpufreq_hw 0>; 46 enable-method = "psci"; 47 power-domains = <&CPU_PD0>; 48 power-domain-names = "psci"; 49 qcom,freq-domain = <&cpufreq_hw 0>; 50 capacity-dmips-mhz = <1024>; 51 dynamic-power-coefficient = <100>; 52 next-level-cache = <&L2_0>; 53 54 L2_0: l2-cache { 55 compatible = "cache"; 56 cache-level = <2>; 57 cache-unified; 58 next-level-cache = <&L3_0>; 59 L3_0: l3-cache { 60 compatible = "cache"; 61 cache-level = <3>; 62 cache-unified; 63 }; 64 }; 65 }; 66 67 CPU1: cpu@100 { 68 device_type = "cpu"; 69 compatible = "arm,cortex-a55"; 70 reg = <0x0 0x100>; 71 clocks = <&cpufreq_hw 0>; 72 enable-method = "psci"; 73 power-domains = <&CPU_PD1>; 74 power-domain-names = "psci"; 75 qcom,freq-domain = <&cpufreq_hw 0>; 76 capacity-dmips-mhz = <1024>; 77 dynamic-power-coefficient = <100>; 78 next-level-cache = <&L2_100>; 79 80 L2_100: l2-cache { 81 compatible = "cache"; 82 cache-level = <2>; 83 cache-unified; 84 next-level-cache = <&L3_0>; 85 }; 86 }; 87 88 CPU2: cpu@200 { 89 device_type = "cpu"; 90 compatible = "arm,cortex-a55"; 91 reg = <0x0 0x200>; 92 clocks = <&cpufreq_hw 0>; 93 enable-method = "psci"; 94 power-domains = <&CPU_PD2>; 95 power-domain-names = "psci"; 96 qcom,freq-domain = <&cpufreq_hw 0>; 97 capacity-dmips-mhz = <1024>; 98 dynamic-power-coefficient = <100>; 99 next-level-cache = <&L2_200>; 100 101 L2_200: l2-cache { 102 compatible = "cache"; 103 cache-level = <2>; 104 cache-unified; 105 next-level-cache = <&L3_0>; 106 }; 107 }; 108 109 CPU3: cpu@300 { 110 device_type = "cpu"; 111 compatible = "arm,cortex-a55"; 112 reg = <0x0 0x300>; 113 clocks = <&cpufreq_hw 0>; 114 enable-method = "psci"; 115 power-domains = <&CPU_PD3>; 116 power-domain-names = "psci"; 117 qcom,freq-domain = <&cpufreq_hw 0>; 118 capacity-dmips-mhz = <1024>; 119 dynamic-power-coefficient = <100>; 120 next-level-cache = <&L2_300>; 121 122 L2_300: l2-cache { 123 compatible = "cache"; 124 cache-level = <2>; 125 cache-unified; 126 next-level-cache = <&L3_0>; 127 }; 128 }; 129 130 cpu-map { 131 cluster0 { 132 core0 { 133 cpu = <&CPU0>; 134 }; 135 136 core1 { 137 cpu = <&CPU1>; 138 }; 139 140 core2 { 141 cpu = <&CPU2>; 142 }; 143 144 core3 { 145 cpu = <&CPU3>; 146 }; 147 }; 148 }; 149 150 idle-states { 151 entry-method = "psci"; 152 153 CPU_OFF: cpu-sleep-0 { 154 compatible = "arm,idle-state"; 155 entry-latency-us = <235>; 156 exit-latency-us = <428>; 157 min-residency-us = <1774>; 158 arm,psci-suspend-param = <0x40000003>; 159 local-timer-stop; 160 }; 161 162 CPU_RAIL_OFF: cpu-rail-sleep-1 { 163 compatible = "arm,idle-state"; 164 entry-latency-us = <800>; 165 exit-latency-us = <750>; 166 min-residency-us = <4090>; 167 arm,psci-suspend-param = <0x40000004>; 168 local-timer-stop; 169 }; 170 171 }; 172 173 domain-idle-states { 174 CLUSTER_SLEEP_0: cluster-sleep-0 { 175 compatible = "domain-idle-state"; 176 arm,psci-suspend-param = <0x41000044>; 177 entry-latency-us = <1050>; 178 exit-latency-us = <2500>; 179 min-residency-us = <5309>; 180 }; 181 182 CLUSTER_SLEEP_1: cluster-sleep-1 { 183 compatible = "domain-idle-state"; 184 arm,psci-suspend-param = <0x41001344>; 185 entry-latency-us = <2761>; 186 exit-latency-us = <3964>; 187 min-residency-us = <8467>; 188 }; 189 190 CLUSTER_SLEEP_2: cluster-sleep-2 { 191 compatible = "domain-idle-state"; 192 arm,psci-suspend-param = <0x4100b344>; 193 entry-latency-us = <2793>; 194 exit-latency-us = <4023>; 195 min-residency-us = <9826>; 196 }; 197 }; 198 }; 199 200 firmware { 201 scm: scm { 202 compatible = "qcom,scm-sdx75", "qcom,scm"; 203 }; 204 }; 205 206 memory@80000000 { 207 device_type = "memory"; 208 reg = <0x0 0x80000000 0x0 0x0>; 209 }; 210 211 pmu { 212 compatible = "arm,armv8-pmuv3"; 213 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 214 }; 215 216 psci { 217 compatible = "arm,psci-1.0"; 218 method = "smc"; 219 220 CPU_PD0: power-domain-cpu0 { 221 #power-domain-cells = <0>; 222 power-domains = <&CLUSTER_PD>; 223 domain-idle-states = <&CPU_OFF &CPU_RAIL_OFF>; 224 }; 225 226 CPU_PD1: power-domain-cpu1 { 227 #power-domain-cells = <0>; 228 power-domains = <&CLUSTER_PD>; 229 domain-idle-states = <&CPU_OFF &CPU_RAIL_OFF>; 230 }; 231 232 CPU_PD2: power-domain-cpu2 { 233 #power-domain-cells = <0>; 234 power-domains = <&CLUSTER_PD>; 235 domain-idle-states = <&CPU_OFF &CPU_RAIL_OFF>; 236 }; 237 238 CPU_PD3: power-domain-cpu3 { 239 #power-domain-cells = <0>; 240 power-domains = <&CLUSTER_PD>; 241 domain-idle-states = <&CPU_OFF &CPU_RAIL_OFF>; 242 }; 243 244 CLUSTER_PD: power-domain-cpu-cluster0 { 245 #power-domain-cells = <0>; 246 domain-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_1 &CLUSTER_SLEEP_2>; 247 }; 248 }; 249 250 reserved-memory { 251 #address-cells = <2>; 252 #size-cells = <2>; 253 ranges; 254 255 gunyah_hyp_mem: gunyah-hyp@80000000 { 256 reg = <0x0 0x80000000 0x0 0x800000>; 257 no-map; 258 }; 259 260 hyp_elf_package_mem: hyp-elf-package@80800000 { 261 reg = <0x0 0x80800000 0x0 0x200000>; 262 no-map; 263 }; 264 265 access_control_db_mem: access-control-db@81380000 { 266 reg = <0x0 0x81380000 0x0 0x80000>; 267 no-map; 268 }; 269 270 qteetz_mem: qteetz@814e0000 { 271 reg = <0x0 0x814e0000 0x0 0x2a0000>; 272 no-map; 273 }; 274 275 trusted_apps_mem: trusted-apps@81780000 { 276 reg = <0x0 0x81780000 0x0 0xa00000>; 277 no-map; 278 }; 279 280 xbl_ramdump_mem: xbl-ramdump@87a00000 { 281 reg = <0x0 0x87a00000 0x0 0x1c0000>; 282 no-map; 283 }; 284 285 cpucp_fw_mem: cpucp-fw@87c00000 { 286 reg = <0x0 0x87c00000 0x0 0x100000>; 287 no-map; 288 }; 289 290 xbl_dtlog_mem: xbl-dtlog@87d00000 { 291 reg = <0x0 0x87d00000 0x0 0x40000>; 292 no-map; 293 }; 294 295 xbl_sc_mem: xbl-sc@87d40000 { 296 reg = <0x0 0x87d40000 0x0 0x40000>; 297 no-map; 298 }; 299 300 modem_efs_shared_mem: modem-efs-shared@87d80000 { 301 reg = <0x0 0x87d80000 0x0 0x10000>; 302 no-map; 303 }; 304 305 aop_image_mem: aop-image@87e00000 { 306 reg = <0x0 0x87e00000 0x0 0x20000>; 307 no-map; 308 }; 309 310 smem_mem: smem@87e20000 { 311 reg = <0x0 0x87e20000 0x0 0xc0000>; 312 no-map; 313 }; 314 315 aop_cmd_db_mem: aop-cmd-db@87ee0000 { 316 compatible = "qcom,cmd-db"; 317 reg = <0x0 0x87ee0000 0x0 0x20000>; 318 no-map; 319 }; 320 321 aop_config_mem: aop-config@87f00000 { 322 reg = <0x0 0x87f00000 0x0 0x20000>; 323 no-map; 324 }; 325 326 ipa_fw_mem: ipa-fw@87f20000 { 327 reg = <0x0 0x87f20000 0x0 0x10000>; 328 no-map; 329 }; 330 331 secdata_mem: secdata@87f30000 { 332 reg = <0x0 0x87f30000 0x0 0x1000>; 333 no-map; 334 }; 335 336 tme_crashdump_mem: tme-crashdump@87f31000 { 337 reg = <0x0 0x87f31000 0x0 0x40000>; 338 no-map; 339 }; 340 341 tme_log_mem: tme-log@87f71000 { 342 reg = <0x0 0x87f71000 0x0 0x4000>; 343 no-map; 344 }; 345 346 uefi_log_mem: uefi-log@87f75000 { 347 reg = <0x0 0x87f75000 0x0 0x10000>; 348 no-map; 349 }; 350 351 qdss_mem: qdss@88800000 { 352 reg = <0x0 0x88800000 0x0 0x300000>; 353 no-map; 354 }; 355 356 audio_heap_mem: audio-heap@88b00000 { 357 compatible = "shared-dma-pool"; 358 reg = <0x0 0x88b00000 0x0 0x400000>; 359 no-map; 360 }; 361 362 mpss_dsmharq_mem: mpss-dsmharq@88f00000 { 363 reg = <0x0 0x88f00000 0x0 0x5080000>; 364 no-map; 365 }; 366 367 q6_mpss_dtb_mem: q6-mpss-dtb@8df80000 { 368 reg = <0x0 0x8df80000 0x0 0x80000>; 369 no-map; 370 }; 371 372 mpssadsp_mem: mpssadsp@8e000000 { 373 reg = <0x0 0x8e000000 0x0 0xf400000>; 374 no-map; 375 }; 376 377 gunyah_trace_buffer_mem: gunyah-trace-buffer@bdb00000 { 378 reg = <0x0 0xbdb00000 0x0 0x2000000>; 379 no-map; 380 }; 381 382 smmu_debug_buf_mem: smmu-debug-buf@bfb00000 { 383 reg = <0x0 0xbfb00000 0x0 0x100000>; 384 no-map; 385 }; 386 387 hyp_smmu_s2_pt_mem: hyp-smmu-s2-pt@bfc00000 { 388 reg = <0x0 0xbfc00000 0x0 0x400000>; 389 no-map; 390 }; 391 }; 392 393 smem: qcom,smem { 394 compatible = "qcom,smem"; 395 memory-region = <&smem_mem>; 396 hwlocks = <&tcsr_mutex 3>; 397 }; 398 399 soc: soc { 400 compatible = "simple-bus"; 401 #address-cells = <2>; 402 #size-cells = <2>; 403 ranges = <0 0 0 0 0x10 0>; 404 dma-ranges = <0 0 0 0 0x10 0>; 405 406 gcc: clock-controller@80000 { 407 compatible = "qcom,sdx75-gcc"; 408 reg = <0x0 0x0080000 0x0 0x1f7400>; 409 clocks = <&rpmhcc RPMH_CXO_CLK>, 410 <&sleep_clk>, 411 <0>, 412 <0>, 413 <0>, 414 <0>, 415 <0>, 416 <0>, 417 <0>, 418 <0>, 419 <0>, 420 <0>, 421 <0>, 422 <0>, 423 <0>; 424 #clock-cells = <1>; 425 #reset-cells = <1>; 426 #power-domain-cells = <1>; 427 }; 428 429 qupv3_id_0: geniqup@9c0000 { 430 compatible = "qcom,geni-se-qup"; 431 reg = <0x0 0x009c0000 0x0 0x2000>; 432 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 433 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 434 clock-names = "m-ahb", 435 "s-ahb"; 436 iommus = <&apps_smmu 0xe3 0x0>; 437 #address-cells = <2>; 438 #size-cells = <2>; 439 ranges; 440 status = "disabled"; 441 442 uart1: serial@984000 { 443 compatible = "qcom,geni-debug-uart"; 444 reg = <0x0 0x00984000 0x0 0x4000>; 445 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 446 clock-names = "se"; 447 interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>; 448 pinctrl-0 = <&qupv3_se1_2uart_active>; 449 pinctrl-1 = <&qupv3_se1_2uart_sleep>; 450 pinctrl-names = "default", 451 "sleep"; 452 status = "disabled"; 453 }; 454 }; 455 456 tcsr_mutex: hwlock@1f40000 { 457 compatible = "qcom,tcsr-mutex"; 458 reg = <0x0 0x01f40000 0x0 0x40000>; 459 #hwlock-cells = <1>; 460 }; 461 462 pdc: interrupt-controller@b220000 { 463 compatible = "qcom,sdx75-pdc", "qcom,pdc"; 464 reg = <0x0 0xb220000 0x0 0x30000>, 465 <0x0 0x174000f0 0x0 0x64>; 466 qcom,pdc-ranges = <0 147 52>, 467 <52 266 32>, 468 <84 500 59>; 469 #interrupt-cells = <2>; 470 interrupt-parent = <&intc>; 471 interrupt-controller; 472 }; 473 474 spmi_bus: spmi@c400000 { 475 compatible = "qcom,spmi-pmic-arb"; 476 reg = <0x0 0x0c400000 0x0 0x3000>, 477 <0x0 0x0c500000 0x0 0x400000>, 478 <0x0 0x0c440000 0x0 0x80000>, 479 <0x0 0x0c4c0000 0x0 0x10000>, 480 <0x0 0x0c42d000 0x0 0x4000>; 481 reg-names = "core", 482 "chnls", 483 "obsrvr", 484 "intr", 485 "cnfg"; 486 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 487 interrupt-names = "periph_irq"; 488 qcom,ee = <0>; 489 qcom,channel = <0>; 490 qcom,bus-id = <0>; 491 #address-cells = <2>; 492 #size-cells = <0>; 493 interrupt-controller; 494 #interrupt-cells = <4>; 495 }; 496 497 tlmm: pinctrl@f000000 { 498 compatible = "qcom,sdx75-tlmm"; 499 reg = <0x0 0x0f000000 0x0 0x400000>; 500 interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>; 501 gpio-controller; 502 #gpio-cells = <2>; 503 gpio-ranges = <&tlmm 0 0 133>; 504 interrupt-controller; 505 #interrupt-cells = <2>; 506 wakeup-parent = <&pdc>; 507 508 qupv3_se1_2uart_active: qupv3-se1-2uart-active-state { 509 tx-pins { 510 pins = "gpio12"; 511 function = "qup_se1_l2_mira"; 512 drive-strength = <2>; 513 bias-disable; 514 }; 515 516 rx-pins { 517 pins = "gpio13"; 518 function = "qup_se1_l3_mira"; 519 drive-strength = <2>; 520 bias-disable; 521 }; 522 }; 523 524 qupv3_se1_2uart_sleep: qupv3-se1-2uart-sleep-state { 525 pins = "gpio12", "gpio13"; 526 function = "gpio"; 527 drive-strength = <2>; 528 bias-pull-down; 529 }; 530 }; 531 532 apps_smmu: iommu@15000000 { 533 compatible = "qcom,sdx75-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 534 reg = <0x0 0x15000000 0x0 0x40000>; 535 #iommu-cells = <2>; 536 #global-interrupts = <2>; 537 dma-coherent; 538 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 539 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 540 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 541 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 542 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, 543 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 544 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 545 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 546 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 547 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 548 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 549 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 550 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 551 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 552 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 553 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 554 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 555 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 556 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 557 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 558 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 559 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 560 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 561 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 562 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 563 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, 564 <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, 565 <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 566 <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 567 <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 568 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 569 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, 570 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 571 }; 572 573 intc: interrupt-controller@17200000 { 574 compatible = "arm,gic-v3"; 575 #interrupt-cells = <3>; 576 interrupt-controller; 577 #redistributor-regions = <1>; 578 redistributor-stride = <0x0 0x20000>; 579 reg = <0x0 0x17200000 0x0 0x10000>, 580 <0x0 0x17260000 0x0 0x80000>; 581 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 582 }; 583 584 timer@17420000 { 585 compatible = "arm,armv7-timer-mem"; 586 reg = <0x0 0x17420000 0x0 0x1000>; 587 #address-cells = <1>; 588 #size-cells = <1>; 589 ranges = <0 0 0 0x20000000>; 590 591 frame@17421000 { 592 reg = <0x17421000 0x1000>, 593 <0x17422000 0x1000>; 594 frame-number = <0>; 595 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 596 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 597 }; 598 599 frame@17423000 { 600 reg = <0x17423000 0x1000>; 601 frame-number = <1>; 602 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 603 status = "disabled"; 604 }; 605 606 frame@17425000 { 607 reg = <0x17425000 0x1000>; 608 frame-number = <2>; 609 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 610 status = "disabled"; 611 }; 612 613 frame@17427000 { 614 reg = <0x17427000 0x1000>; 615 frame-number = <3>; 616 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 617 status = "disabled"; 618 }; 619 620 frame@17429000 { 621 reg = <0x17429000 0x1000>; 622 frame-number = <4>; 623 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 624 status = "disabled"; 625 }; 626 627 frame@1742b000 { 628 reg = <0x1742b000 0x1000>; 629 frame-number = <5>; 630 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 631 status = "disabled"; 632 }; 633 634 frame@1742d000 { 635 reg = <0x1742d000 0x1000>; 636 frame-number = <6>; 637 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 638 status = "disabled"; 639 }; 640 }; 641 642 apps_rsc: rsc@17a00000 { 643 label = "apps_rsc"; 644 compatible = "qcom,rpmh-rsc"; 645 reg = <0x0 0x17a00000 0x0 0x10000>, 646 <0x0 0x17a10000 0x0 0x10000>, 647 <0x0 0x17a20000 0x0 0x10000>; 648 reg-names = "drv-0", "drv-1", "drv-2"; 649 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 650 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 651 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 652 653 power-domains = <&CLUSTER_PD>; 654 qcom,tcs-offset = <0xd00>; 655 qcom,drv-id = <2>; 656 qcom,tcs-config = <ACTIVE_TCS 3>, 657 <SLEEP_TCS 2>, 658 <WAKE_TCS 2>, 659 <CONTROL_TCS 0>; 660 661 apps_bcm_voter: bcm-voter { 662 compatible = "qcom,bcm-voter"; 663 }; 664 665 rpmhcc: clock-controller { 666 compatible = "qcom,sdx75-rpmh-clk"; 667 clocks = <&xo_board>; 668 clock-names = "xo"; 669 #clock-cells = <1>; 670 }; 671 672 rpmhpd: power-controller { 673 compatible = "qcom,sdx75-rpmhpd"; 674 #power-domain-cells = <1>; 675 operating-points-v2 = <&rpmhpd_opp_table>; 676 677 rpmhpd_opp_table: opp-table { 678 compatible = "operating-points-v2"; 679 680 rpmhpd_opp_ret: opp-16 { 681 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 682 }; 683 684 rpmhpd_opp_min_svs: opp-48 { 685 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 686 }; 687 688 rpmhpd_opp_low_svs: opp-64 { 689 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 690 }; 691 692 rpmhpd_opp_svs: opp-128 { 693 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 694 }; 695 696 rpmhpd_opp_svs_l1: opp-192 { 697 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 698 }; 699 700 rpmhpd_opp_nom: opp-256 { 701 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 702 }; 703 704 rpmhpd_opp_nom_l1: opp-320 { 705 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 706 }; 707 708 rpmhpd_opp_nom_l2: opp-336 { 709 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 710 }; 711 712 rpmhpd_opp_turbo: opp-384 { 713 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 714 }; 715 716 rpmhpd_opp_turbo_l1: opp-416 { 717 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 718 }; 719 }; 720 }; 721 }; 722 723 cpufreq_hw: cpufreq@17d91000 { 724 compatible = "qcom,sdx75-cpufreq-epss", "qcom,cpufreq-epss"; 725 reg = <0x0 0x17d91000 0x0 0x1000>; 726 reg-names = "freq-domain0"; 727 clocks = <&rpmhcc RPMH_CXO_CLK>, 728 <&gcc GPLL0>; 729 clock-names = "xo", 730 "alternate"; 731 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 732 interrupt-names = "dcvsh-irq-0"; 733 #freq-domain-cells = <1>; 734 #clock-cells = <1>; 735 }; 736 }; 737 738 timer { 739 compatible = "arm,armv8-timer"; 740 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 741 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 742 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 743 <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 744 }; 745}; 746