1// SPDX-License-Identifier: GPL-2.0 2/* 3 * SDM845 SoC device tree source 4 * 5 * Copyright (c) 2018, The Linux Foundation. All rights reserved. 6 */ 7 8#include <dt-bindings/clock/qcom,dispcc-sdm845.h> 9#include <dt-bindings/clock/qcom,gcc-sdm845.h> 10#include <dt-bindings/clock/qcom,gpucc-sdm845.h> 11#include <dt-bindings/clock/qcom,lpass-sdm845.h> 12#include <dt-bindings/clock/qcom,rpmh.h> 13#include <dt-bindings/clock/qcom,videocc-sdm845.h> 14#include <dt-bindings/interconnect/qcom,sdm845.h> 15#include <dt-bindings/interrupt-controller/arm-gic.h> 16#include <dt-bindings/phy/phy-qcom-qusb2.h> 17#include <dt-bindings/power/qcom-rpmpd.h> 18#include <dt-bindings/reset/qcom,sdm845-aoss.h> 19#include <dt-bindings/reset/qcom,sdm845-pdc.h> 20#include <dt-bindings/soc/qcom,rpmh-rsc.h> 21#include <dt-bindings/clock/qcom,gcc-sdm845.h> 22#include <dt-bindings/thermal/thermal.h> 23 24/ { 25 interrupt-parent = <&intc>; 26 27 #address-cells = <2>; 28 #size-cells = <2>; 29 30 aliases { 31 i2c0 = &i2c0; 32 i2c1 = &i2c1; 33 i2c2 = &i2c2; 34 i2c3 = &i2c3; 35 i2c4 = &i2c4; 36 i2c5 = &i2c5; 37 i2c6 = &i2c6; 38 i2c7 = &i2c7; 39 i2c8 = &i2c8; 40 i2c9 = &i2c9; 41 i2c10 = &i2c10; 42 i2c11 = &i2c11; 43 i2c12 = &i2c12; 44 i2c13 = &i2c13; 45 i2c14 = &i2c14; 46 i2c15 = &i2c15; 47 spi0 = &spi0; 48 spi1 = &spi1; 49 spi2 = &spi2; 50 spi3 = &spi3; 51 spi4 = &spi4; 52 spi5 = &spi5; 53 spi6 = &spi6; 54 spi7 = &spi7; 55 spi8 = &spi8; 56 spi9 = &spi9; 57 spi10 = &spi10; 58 spi11 = &spi11; 59 spi12 = &spi12; 60 spi13 = &spi13; 61 spi14 = &spi14; 62 spi15 = &spi15; 63 }; 64 65 chosen { }; 66 67 memory@80000000 { 68 device_type = "memory"; 69 /* We expect the bootloader to fill in the size */ 70 reg = <0 0x80000000 0 0>; 71 }; 72 73 reserved-memory { 74 #address-cells = <2>; 75 #size-cells = <2>; 76 ranges; 77 78 hyp_mem: memory@85700000 { 79 reg = <0 0x85700000 0 0x600000>; 80 no-map; 81 }; 82 83 xbl_mem: memory@85e00000 { 84 reg = <0 0x85e00000 0 0x100000>; 85 no-map; 86 }; 87 88 aop_mem: memory@85fc0000 { 89 reg = <0 0x85fc0000 0 0x20000>; 90 no-map; 91 }; 92 93 aop_cmd_db_mem: memory@85fe0000 { 94 compatible = "qcom,cmd-db"; 95 reg = <0x0 0x85fe0000 0 0x20000>; 96 no-map; 97 }; 98 99 smem_mem: memory@86000000 { 100 reg = <0x0 0x86000000 0 0x200000>; 101 no-map; 102 }; 103 104 tz_mem: memory@86200000 { 105 reg = <0 0x86200000 0 0x2d00000>; 106 no-map; 107 }; 108 109 rmtfs_mem: memory@88f00000 { 110 compatible = "qcom,rmtfs-mem"; 111 reg = <0 0x88f00000 0 0x200000>; 112 no-map; 113 114 qcom,client-id = <1>; 115 qcom,vmid = <15>; 116 }; 117 118 qseecom_mem: memory@8ab00000 { 119 reg = <0 0x8ab00000 0 0x1400000>; 120 no-map; 121 }; 122 123 camera_mem: memory@8bf00000 { 124 reg = <0 0x8bf00000 0 0x500000>; 125 no-map; 126 }; 127 128 ipa_fw_mem: memory@8c400000 { 129 reg = <0 0x8c400000 0 0x10000>; 130 no-map; 131 }; 132 133 ipa_gsi_mem: memory@8c410000 { 134 reg = <0 0x8c410000 0 0x5000>; 135 no-map; 136 }; 137 138 gpu_mem: memory@8c415000 { 139 reg = <0 0x8c415000 0 0x2000>; 140 no-map; 141 }; 142 143 adsp_mem: memory@8c500000 { 144 reg = <0 0x8c500000 0 0x1a00000>; 145 no-map; 146 }; 147 148 wlan_msa_mem: memory@8df00000 { 149 reg = <0 0x8df00000 0 0x100000>; 150 no-map; 151 }; 152 153 mpss_region: memory@8e000000 { 154 reg = <0 0x8e000000 0 0x7800000>; 155 no-map; 156 }; 157 158 venus_mem: memory@95800000 { 159 reg = <0 0x95800000 0 0x500000>; 160 no-map; 161 }; 162 163 cdsp_mem: memory@95d00000 { 164 reg = <0 0x95d00000 0 0x800000>; 165 no-map; 166 }; 167 168 mba_region: memory@96500000 { 169 reg = <0 0x96500000 0 0x200000>; 170 no-map; 171 }; 172 173 slpi_mem: memory@96700000 { 174 reg = <0 0x96700000 0 0x1400000>; 175 no-map; 176 }; 177 178 spss_mem: memory@97b00000 { 179 reg = <0 0x97b00000 0 0x100000>; 180 no-map; 181 }; 182 }; 183 184 cpus { 185 #address-cells = <2>; 186 #size-cells = <0>; 187 188 CPU0: cpu@0 { 189 device_type = "cpu"; 190 compatible = "qcom,kryo385"; 191 reg = <0x0 0x0>; 192 enable-method = "psci"; 193 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 194 &LITTLE_CPU_SLEEP_1 195 &CLUSTER_SLEEP_0>; 196 capacity-dmips-mhz = <607>; 197 dynamic-power-coefficient = <100>; 198 qcom,freq-domain = <&cpufreq_hw 0>; 199 #cooling-cells = <2>; 200 next-level-cache = <&L2_0>; 201 L2_0: l2-cache { 202 compatible = "cache"; 203 next-level-cache = <&L3_0>; 204 L3_0: l3-cache { 205 compatible = "cache"; 206 }; 207 }; 208 }; 209 210 CPU1: cpu@100 { 211 device_type = "cpu"; 212 compatible = "qcom,kryo385"; 213 reg = <0x0 0x100>; 214 enable-method = "psci"; 215 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 216 &LITTLE_CPU_SLEEP_1 217 &CLUSTER_SLEEP_0>; 218 capacity-dmips-mhz = <607>; 219 dynamic-power-coefficient = <100>; 220 qcom,freq-domain = <&cpufreq_hw 0>; 221 #cooling-cells = <2>; 222 next-level-cache = <&L2_100>; 223 L2_100: l2-cache { 224 compatible = "cache"; 225 next-level-cache = <&L3_0>; 226 }; 227 }; 228 229 CPU2: cpu@200 { 230 device_type = "cpu"; 231 compatible = "qcom,kryo385"; 232 reg = <0x0 0x200>; 233 enable-method = "psci"; 234 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 235 &LITTLE_CPU_SLEEP_1 236 &CLUSTER_SLEEP_0>; 237 capacity-dmips-mhz = <607>; 238 dynamic-power-coefficient = <100>; 239 qcom,freq-domain = <&cpufreq_hw 0>; 240 #cooling-cells = <2>; 241 next-level-cache = <&L2_200>; 242 L2_200: l2-cache { 243 compatible = "cache"; 244 next-level-cache = <&L3_0>; 245 }; 246 }; 247 248 CPU3: cpu@300 { 249 device_type = "cpu"; 250 compatible = "qcom,kryo385"; 251 reg = <0x0 0x300>; 252 enable-method = "psci"; 253 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 254 &LITTLE_CPU_SLEEP_1 255 &CLUSTER_SLEEP_0>; 256 capacity-dmips-mhz = <607>; 257 dynamic-power-coefficient = <100>; 258 qcom,freq-domain = <&cpufreq_hw 0>; 259 #cooling-cells = <2>; 260 next-level-cache = <&L2_300>; 261 L2_300: l2-cache { 262 compatible = "cache"; 263 next-level-cache = <&L3_0>; 264 }; 265 }; 266 267 CPU4: cpu@400 { 268 device_type = "cpu"; 269 compatible = "qcom,kryo385"; 270 reg = <0x0 0x400>; 271 enable-method = "psci"; 272 capacity-dmips-mhz = <1024>; 273 cpu-idle-states = <&BIG_CPU_SLEEP_0 274 &BIG_CPU_SLEEP_1 275 &CLUSTER_SLEEP_0>; 276 dynamic-power-coefficient = <396>; 277 qcom,freq-domain = <&cpufreq_hw 1>; 278 #cooling-cells = <2>; 279 next-level-cache = <&L2_400>; 280 L2_400: l2-cache { 281 compatible = "cache"; 282 next-level-cache = <&L3_0>; 283 }; 284 }; 285 286 CPU5: cpu@500 { 287 device_type = "cpu"; 288 compatible = "qcom,kryo385"; 289 reg = <0x0 0x500>; 290 enable-method = "psci"; 291 capacity-dmips-mhz = <1024>; 292 cpu-idle-states = <&BIG_CPU_SLEEP_0 293 &BIG_CPU_SLEEP_1 294 &CLUSTER_SLEEP_0>; 295 dynamic-power-coefficient = <396>; 296 qcom,freq-domain = <&cpufreq_hw 1>; 297 #cooling-cells = <2>; 298 next-level-cache = <&L2_500>; 299 L2_500: l2-cache { 300 compatible = "cache"; 301 next-level-cache = <&L3_0>; 302 }; 303 }; 304 305 CPU6: cpu@600 { 306 device_type = "cpu"; 307 compatible = "qcom,kryo385"; 308 reg = <0x0 0x600>; 309 enable-method = "psci"; 310 capacity-dmips-mhz = <1024>; 311 cpu-idle-states = <&BIG_CPU_SLEEP_0 312 &BIG_CPU_SLEEP_1 313 &CLUSTER_SLEEP_0>; 314 dynamic-power-coefficient = <396>; 315 qcom,freq-domain = <&cpufreq_hw 1>; 316 #cooling-cells = <2>; 317 next-level-cache = <&L2_600>; 318 L2_600: l2-cache { 319 compatible = "cache"; 320 next-level-cache = <&L3_0>; 321 }; 322 }; 323 324 CPU7: cpu@700 { 325 device_type = "cpu"; 326 compatible = "qcom,kryo385"; 327 reg = <0x0 0x700>; 328 enable-method = "psci"; 329 capacity-dmips-mhz = <1024>; 330 cpu-idle-states = <&BIG_CPU_SLEEP_0 331 &BIG_CPU_SLEEP_1 332 &CLUSTER_SLEEP_0>; 333 dynamic-power-coefficient = <396>; 334 qcom,freq-domain = <&cpufreq_hw 1>; 335 #cooling-cells = <2>; 336 next-level-cache = <&L2_700>; 337 L2_700: l2-cache { 338 compatible = "cache"; 339 next-level-cache = <&L3_0>; 340 }; 341 }; 342 343 cpu-map { 344 cluster0 { 345 core0 { 346 cpu = <&CPU0>; 347 }; 348 349 core1 { 350 cpu = <&CPU1>; 351 }; 352 353 core2 { 354 cpu = <&CPU2>; 355 }; 356 357 core3 { 358 cpu = <&CPU3>; 359 }; 360 361 core4 { 362 cpu = <&CPU4>; 363 }; 364 365 core5 { 366 cpu = <&CPU5>; 367 }; 368 369 core6 { 370 cpu = <&CPU6>; 371 }; 372 373 core7 { 374 cpu = <&CPU7>; 375 }; 376 }; 377 }; 378 379 idle-states { 380 entry-method = "psci"; 381 382 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 383 compatible = "arm,idle-state"; 384 idle-state-name = "little-power-down"; 385 arm,psci-suspend-param = <0x40000003>; 386 entry-latency-us = <350>; 387 exit-latency-us = <461>; 388 min-residency-us = <1890>; 389 local-timer-stop; 390 }; 391 392 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 393 compatible = "arm,idle-state"; 394 idle-state-name = "little-rail-power-down"; 395 arm,psci-suspend-param = <0x40000004>; 396 entry-latency-us = <360>; 397 exit-latency-us = <531>; 398 min-residency-us = <3934>; 399 local-timer-stop; 400 }; 401 402 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 403 compatible = "arm,idle-state"; 404 idle-state-name = "big-power-down"; 405 arm,psci-suspend-param = <0x40000003>; 406 entry-latency-us = <264>; 407 exit-latency-us = <621>; 408 min-residency-us = <952>; 409 local-timer-stop; 410 }; 411 412 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 413 compatible = "arm,idle-state"; 414 idle-state-name = "big-rail-power-down"; 415 arm,psci-suspend-param = <0x40000004>; 416 entry-latency-us = <702>; 417 exit-latency-us = <1061>; 418 min-residency-us = <4488>; 419 local-timer-stop; 420 }; 421 422 CLUSTER_SLEEP_0: cluster-sleep-0 { 423 compatible = "arm,idle-state"; 424 idle-state-name = "cluster-power-down"; 425 arm,psci-suspend-param = <0x400000F4>; 426 entry-latency-us = <3263>; 427 exit-latency-us = <6562>; 428 min-residency-us = <9987>; 429 local-timer-stop; 430 }; 431 }; 432 }; 433 434 pmu { 435 compatible = "arm,armv8-pmuv3"; 436 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; 437 }; 438 439 timer { 440 compatible = "arm,armv8-timer"; 441 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 442 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 443 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 444 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 445 }; 446 447 clocks { 448 xo_board: xo-board { 449 compatible = "fixed-clock"; 450 #clock-cells = <0>; 451 clock-frequency = <38400000>; 452 clock-output-names = "xo_board"; 453 }; 454 455 sleep_clk: sleep-clk { 456 compatible = "fixed-clock"; 457 #clock-cells = <0>; 458 clock-frequency = <32764>; 459 }; 460 }; 461 462 firmware { 463 scm { 464 compatible = "qcom,scm-sdm845", "qcom,scm"; 465 }; 466 }; 467 468 adsp_pas: remoteproc-adsp { 469 compatible = "qcom,sdm845-adsp-pas"; 470 471 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 472 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 473 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 474 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 475 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 476 interrupt-names = "wdog", "fatal", "ready", 477 "handover", "stop-ack"; 478 479 clocks = <&rpmhcc RPMH_CXO_CLK>; 480 clock-names = "xo"; 481 482 memory-region = <&adsp_mem>; 483 484 qcom,smem-states = <&adsp_smp2p_out 0>; 485 qcom,smem-state-names = "stop"; 486 487 status = "disabled"; 488 489 glink-edge { 490 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 491 label = "lpass"; 492 qcom,remote-pid = <2>; 493 mboxes = <&apss_shared 8>; 494 fastrpc { 495 compatible = "qcom,fastrpc"; 496 qcom,glink-channels = "fastrpcglink-apps-dsp"; 497 label = "adsp"; 498 #address-cells = <1>; 499 #size-cells = <0>; 500 501 compute-cb@3 { 502 compatible = "qcom,fastrpc-compute-cb"; 503 reg = <3>; 504 iommus = <&apps_smmu 0x1823 0x0>; 505 }; 506 507 compute-cb@4 { 508 compatible = "qcom,fastrpc-compute-cb"; 509 reg = <4>; 510 iommus = <&apps_smmu 0x1824 0x0>; 511 }; 512 }; 513 }; 514 }; 515 516 cdsp_pas: remoteproc-cdsp { 517 compatible = "qcom,sdm845-cdsp-pas"; 518 519 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 520 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 521 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 522 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 523 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 524 interrupt-names = "wdog", "fatal", "ready", 525 "handover", "stop-ack"; 526 527 clocks = <&rpmhcc RPMH_CXO_CLK>; 528 clock-names = "xo"; 529 530 memory-region = <&cdsp_mem>; 531 532 qcom,smem-states = <&cdsp_smp2p_out 0>; 533 qcom,smem-state-names = "stop"; 534 535 status = "disabled"; 536 537 glink-edge { 538 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>; 539 label = "turing"; 540 qcom,remote-pid = <5>; 541 mboxes = <&apss_shared 4>; 542 fastrpc { 543 compatible = "qcom,fastrpc"; 544 qcom,glink-channels = "fastrpcglink-apps-dsp"; 545 label = "cdsp"; 546 #address-cells = <1>; 547 #size-cells = <0>; 548 549 compute-cb@1 { 550 compatible = "qcom,fastrpc-compute-cb"; 551 reg = <1>; 552 iommus = <&apps_smmu 0x1401 0x30>; 553 }; 554 555 compute-cb@2 { 556 compatible = "qcom,fastrpc-compute-cb"; 557 reg = <2>; 558 iommus = <&apps_smmu 0x1402 0x30>; 559 }; 560 561 compute-cb@3 { 562 compatible = "qcom,fastrpc-compute-cb"; 563 reg = <3>; 564 iommus = <&apps_smmu 0x1403 0x30>; 565 }; 566 567 compute-cb@4 { 568 compatible = "qcom,fastrpc-compute-cb"; 569 reg = <4>; 570 iommus = <&apps_smmu 0x1404 0x30>; 571 }; 572 573 compute-cb@5 { 574 compatible = "qcom,fastrpc-compute-cb"; 575 reg = <5>; 576 iommus = <&apps_smmu 0x1405 0x30>; 577 }; 578 579 compute-cb@6 { 580 compatible = "qcom,fastrpc-compute-cb"; 581 reg = <6>; 582 iommus = <&apps_smmu 0x1406 0x30>; 583 }; 584 585 compute-cb@7 { 586 compatible = "qcom,fastrpc-compute-cb"; 587 reg = <7>; 588 iommus = <&apps_smmu 0x1407 0x30>; 589 }; 590 591 compute-cb@8 { 592 compatible = "qcom,fastrpc-compute-cb"; 593 reg = <8>; 594 iommus = <&apps_smmu 0x1408 0x30>; 595 }; 596 }; 597 }; 598 }; 599 600 tcsr_mutex: hwlock { 601 compatible = "qcom,tcsr-mutex"; 602 syscon = <&tcsr_mutex_regs 0 0x1000>; 603 #hwlock-cells = <1>; 604 }; 605 606 smem { 607 compatible = "qcom,smem"; 608 memory-region = <&smem_mem>; 609 hwlocks = <&tcsr_mutex 3>; 610 }; 611 612 smp2p-cdsp { 613 compatible = "qcom,smp2p"; 614 qcom,smem = <94>, <432>; 615 616 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; 617 618 mboxes = <&apss_shared 6>; 619 620 qcom,local-pid = <0>; 621 qcom,remote-pid = <5>; 622 623 cdsp_smp2p_out: master-kernel { 624 qcom,entry-name = "master-kernel"; 625 #qcom,smem-state-cells = <1>; 626 }; 627 628 cdsp_smp2p_in: slave-kernel { 629 qcom,entry-name = "slave-kernel"; 630 631 interrupt-controller; 632 #interrupt-cells = <2>; 633 }; 634 }; 635 636 smp2p-lpass { 637 compatible = "qcom,smp2p"; 638 qcom,smem = <443>, <429>; 639 640 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 641 642 mboxes = <&apss_shared 10>; 643 644 qcom,local-pid = <0>; 645 qcom,remote-pid = <2>; 646 647 adsp_smp2p_out: master-kernel { 648 qcom,entry-name = "master-kernel"; 649 #qcom,smem-state-cells = <1>; 650 }; 651 652 adsp_smp2p_in: slave-kernel { 653 qcom,entry-name = "slave-kernel"; 654 655 interrupt-controller; 656 #interrupt-cells = <2>; 657 }; 658 }; 659 660 smp2p-mpss { 661 compatible = "qcom,smp2p"; 662 qcom,smem = <435>, <428>; 663 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 664 mboxes = <&apss_shared 14>; 665 qcom,local-pid = <0>; 666 qcom,remote-pid = <1>; 667 668 modem_smp2p_out: master-kernel { 669 qcom,entry-name = "master-kernel"; 670 #qcom,smem-state-cells = <1>; 671 }; 672 673 modem_smp2p_in: slave-kernel { 674 qcom,entry-name = "slave-kernel"; 675 interrupt-controller; 676 #interrupt-cells = <2>; 677 }; 678 }; 679 680 smp2p-slpi { 681 compatible = "qcom,smp2p"; 682 qcom,smem = <481>, <430>; 683 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>; 684 mboxes = <&apss_shared 26>; 685 qcom,local-pid = <0>; 686 qcom,remote-pid = <3>; 687 688 slpi_smp2p_out: master-kernel { 689 qcom,entry-name = "master-kernel"; 690 #qcom,smem-state-cells = <1>; 691 }; 692 693 slpi_smp2p_in: slave-kernel { 694 qcom,entry-name = "slave-kernel"; 695 interrupt-controller; 696 #interrupt-cells = <2>; 697 }; 698 }; 699 700 psci { 701 compatible = "arm,psci-1.0"; 702 method = "smc"; 703 }; 704 705 soc: soc@0 { 706 #address-cells = <2>; 707 #size-cells = <2>; 708 ranges = <0 0 0 0 0x10 0>; 709 dma-ranges = <0 0 0 0 0x10 0>; 710 compatible = "simple-bus"; 711 712 gcc: clock-controller@100000 { 713 compatible = "qcom,gcc-sdm845"; 714 reg = <0 0x00100000 0 0x1f0000>; 715 #clock-cells = <1>; 716 #reset-cells = <1>; 717 #power-domain-cells = <1>; 718 }; 719 720 qfprom@784000 { 721 compatible = "qcom,qfprom"; 722 reg = <0 0x00784000 0 0x8ff>; 723 #address-cells = <1>; 724 #size-cells = <1>; 725 726 qusb2p_hstx_trim: hstx-trim-primary@1eb { 727 reg = <0x1eb 0x1>; 728 bits = <1 4>; 729 }; 730 731 qusb2s_hstx_trim: hstx-trim-secondary@1eb { 732 reg = <0x1eb 0x2>; 733 bits = <6 4>; 734 }; 735 }; 736 737 rng: rng@793000 { 738 compatible = "qcom,prng-ee"; 739 reg = <0 0x00793000 0 0x1000>; 740 clocks = <&gcc GCC_PRNG_AHB_CLK>; 741 clock-names = "core"; 742 }; 743 744 qupv3_id_0: geniqup@8c0000 { 745 compatible = "qcom,geni-se-qup"; 746 reg = <0 0x008c0000 0 0x6000>; 747 clock-names = "m-ahb", "s-ahb"; 748 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 749 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 750 #address-cells = <2>; 751 #size-cells = <2>; 752 ranges; 753 status = "disabled"; 754 755 i2c0: i2c@880000 { 756 compatible = "qcom,geni-i2c"; 757 reg = <0 0x00880000 0 0x4000>; 758 clock-names = "se"; 759 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 760 pinctrl-names = "default"; 761 pinctrl-0 = <&qup_i2c0_default>; 762 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 763 #address-cells = <1>; 764 #size-cells = <0>; 765 status = "disabled"; 766 }; 767 768 spi0: spi@880000 { 769 compatible = "qcom,geni-spi"; 770 reg = <0 0x00880000 0 0x4000>; 771 clock-names = "se"; 772 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 773 pinctrl-names = "default"; 774 pinctrl-0 = <&qup_spi0_default>; 775 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 776 #address-cells = <1>; 777 #size-cells = <0>; 778 status = "disabled"; 779 }; 780 781 uart0: serial@880000 { 782 compatible = "qcom,geni-uart"; 783 reg = <0 0x00880000 0 0x4000>; 784 clock-names = "se"; 785 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 786 pinctrl-names = "default"; 787 pinctrl-0 = <&qup_uart0_default>; 788 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 789 status = "disabled"; 790 }; 791 792 i2c1: i2c@884000 { 793 compatible = "qcom,geni-i2c"; 794 reg = <0 0x00884000 0 0x4000>; 795 clock-names = "se"; 796 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 797 pinctrl-names = "default"; 798 pinctrl-0 = <&qup_i2c1_default>; 799 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 800 #address-cells = <1>; 801 #size-cells = <0>; 802 status = "disabled"; 803 }; 804 805 spi1: spi@884000 { 806 compatible = "qcom,geni-spi"; 807 reg = <0 0x00884000 0 0x4000>; 808 clock-names = "se"; 809 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 810 pinctrl-names = "default"; 811 pinctrl-0 = <&qup_spi1_default>; 812 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 813 #address-cells = <1>; 814 #size-cells = <0>; 815 status = "disabled"; 816 }; 817 818 uart1: serial@884000 { 819 compatible = "qcom,geni-uart"; 820 reg = <0 0x00884000 0 0x4000>; 821 clock-names = "se"; 822 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 823 pinctrl-names = "default"; 824 pinctrl-0 = <&qup_uart1_default>; 825 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 826 status = "disabled"; 827 }; 828 829 i2c2: i2c@888000 { 830 compatible = "qcom,geni-i2c"; 831 reg = <0 0x00888000 0 0x4000>; 832 clock-names = "se"; 833 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 834 pinctrl-names = "default"; 835 pinctrl-0 = <&qup_i2c2_default>; 836 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 837 #address-cells = <1>; 838 #size-cells = <0>; 839 status = "disabled"; 840 }; 841 842 spi2: spi@888000 { 843 compatible = "qcom,geni-spi"; 844 reg = <0 0x00888000 0 0x4000>; 845 clock-names = "se"; 846 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 847 pinctrl-names = "default"; 848 pinctrl-0 = <&qup_spi2_default>; 849 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 850 #address-cells = <1>; 851 #size-cells = <0>; 852 status = "disabled"; 853 }; 854 855 uart2: serial@888000 { 856 compatible = "qcom,geni-uart"; 857 reg = <0 0x00888000 0 0x4000>; 858 clock-names = "se"; 859 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 860 pinctrl-names = "default"; 861 pinctrl-0 = <&qup_uart2_default>; 862 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 863 status = "disabled"; 864 }; 865 866 i2c3: i2c@88c000 { 867 compatible = "qcom,geni-i2c"; 868 reg = <0 0x0088c000 0 0x4000>; 869 clock-names = "se"; 870 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 871 pinctrl-names = "default"; 872 pinctrl-0 = <&qup_i2c3_default>; 873 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 874 #address-cells = <1>; 875 #size-cells = <0>; 876 status = "disabled"; 877 }; 878 879 spi3: spi@88c000 { 880 compatible = "qcom,geni-spi"; 881 reg = <0 0x0088c000 0 0x4000>; 882 clock-names = "se"; 883 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 884 pinctrl-names = "default"; 885 pinctrl-0 = <&qup_spi3_default>; 886 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 887 #address-cells = <1>; 888 #size-cells = <0>; 889 status = "disabled"; 890 }; 891 892 uart3: serial@88c000 { 893 compatible = "qcom,geni-uart"; 894 reg = <0 0x0088c000 0 0x4000>; 895 clock-names = "se"; 896 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 897 pinctrl-names = "default"; 898 pinctrl-0 = <&qup_uart3_default>; 899 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 900 status = "disabled"; 901 }; 902 903 i2c4: i2c@890000 { 904 compatible = "qcom,geni-i2c"; 905 reg = <0 0x00890000 0 0x4000>; 906 clock-names = "se"; 907 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 908 pinctrl-names = "default"; 909 pinctrl-0 = <&qup_i2c4_default>; 910 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 911 #address-cells = <1>; 912 #size-cells = <0>; 913 status = "disabled"; 914 }; 915 916 spi4: spi@890000 { 917 compatible = "qcom,geni-spi"; 918 reg = <0 0x00890000 0 0x4000>; 919 clock-names = "se"; 920 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 921 pinctrl-names = "default"; 922 pinctrl-0 = <&qup_spi4_default>; 923 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 924 #address-cells = <1>; 925 #size-cells = <0>; 926 status = "disabled"; 927 }; 928 929 uart4: serial@890000 { 930 compatible = "qcom,geni-uart"; 931 reg = <0 0x00890000 0 0x4000>; 932 clock-names = "se"; 933 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 934 pinctrl-names = "default"; 935 pinctrl-0 = <&qup_uart4_default>; 936 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 937 status = "disabled"; 938 }; 939 940 i2c5: i2c@894000 { 941 compatible = "qcom,geni-i2c"; 942 reg = <0 0x00894000 0 0x4000>; 943 clock-names = "se"; 944 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 945 pinctrl-names = "default"; 946 pinctrl-0 = <&qup_i2c5_default>; 947 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 948 #address-cells = <1>; 949 #size-cells = <0>; 950 status = "disabled"; 951 }; 952 953 spi5: spi@894000 { 954 compatible = "qcom,geni-spi"; 955 reg = <0 0x00894000 0 0x4000>; 956 clock-names = "se"; 957 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 958 pinctrl-names = "default"; 959 pinctrl-0 = <&qup_spi5_default>; 960 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 961 #address-cells = <1>; 962 #size-cells = <0>; 963 status = "disabled"; 964 }; 965 966 uart5: serial@894000 { 967 compatible = "qcom,geni-uart"; 968 reg = <0 0x00894000 0 0x4000>; 969 clock-names = "se"; 970 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 971 pinctrl-names = "default"; 972 pinctrl-0 = <&qup_uart5_default>; 973 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 974 status = "disabled"; 975 }; 976 977 i2c6: i2c@898000 { 978 compatible = "qcom,geni-i2c"; 979 reg = <0 0x00898000 0 0x4000>; 980 clock-names = "se"; 981 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 982 pinctrl-names = "default"; 983 pinctrl-0 = <&qup_i2c6_default>; 984 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 985 #address-cells = <1>; 986 #size-cells = <0>; 987 status = "disabled"; 988 }; 989 990 spi6: spi@898000 { 991 compatible = "qcom,geni-spi"; 992 reg = <0 0x00898000 0 0x4000>; 993 clock-names = "se"; 994 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 995 pinctrl-names = "default"; 996 pinctrl-0 = <&qup_spi6_default>; 997 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 998 #address-cells = <1>; 999 #size-cells = <0>; 1000 status = "disabled"; 1001 }; 1002 1003 uart6: serial@898000 { 1004 compatible = "qcom,geni-uart"; 1005 reg = <0 0x00898000 0 0x4000>; 1006 clock-names = "se"; 1007 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1008 pinctrl-names = "default"; 1009 pinctrl-0 = <&qup_uart6_default>; 1010 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1011 status = "disabled"; 1012 }; 1013 1014 i2c7: i2c@89c000 { 1015 compatible = "qcom,geni-i2c"; 1016 reg = <0 0x0089c000 0 0x4000>; 1017 clock-names = "se"; 1018 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1019 pinctrl-names = "default"; 1020 pinctrl-0 = <&qup_i2c7_default>; 1021 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1022 #address-cells = <1>; 1023 #size-cells = <0>; 1024 status = "disabled"; 1025 }; 1026 1027 spi7: spi@89c000 { 1028 compatible = "qcom,geni-spi"; 1029 reg = <0 0x0089c000 0 0x4000>; 1030 clock-names = "se"; 1031 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1032 pinctrl-names = "default"; 1033 pinctrl-0 = <&qup_spi7_default>; 1034 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1035 #address-cells = <1>; 1036 #size-cells = <0>; 1037 status = "disabled"; 1038 }; 1039 1040 uart7: serial@89c000 { 1041 compatible = "qcom,geni-uart"; 1042 reg = <0 0x0089c000 0 0x4000>; 1043 clock-names = "se"; 1044 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1045 pinctrl-names = "default"; 1046 pinctrl-0 = <&qup_uart7_default>; 1047 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1048 status = "disabled"; 1049 }; 1050 }; 1051 1052 qupv3_id_1: geniqup@ac0000 { 1053 compatible = "qcom,geni-se-qup"; 1054 reg = <0 0x00ac0000 0 0x6000>; 1055 clock-names = "m-ahb", "s-ahb"; 1056 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1057 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1058 #address-cells = <2>; 1059 #size-cells = <2>; 1060 ranges; 1061 status = "disabled"; 1062 1063 i2c8: i2c@a80000 { 1064 compatible = "qcom,geni-i2c"; 1065 reg = <0 0x00a80000 0 0x4000>; 1066 clock-names = "se"; 1067 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1068 pinctrl-names = "default"; 1069 pinctrl-0 = <&qup_i2c8_default>; 1070 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1071 #address-cells = <1>; 1072 #size-cells = <0>; 1073 status = "disabled"; 1074 }; 1075 1076 spi8: spi@a80000 { 1077 compatible = "qcom,geni-spi"; 1078 reg = <0 0x00a80000 0 0x4000>; 1079 clock-names = "se"; 1080 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1081 pinctrl-names = "default"; 1082 pinctrl-0 = <&qup_spi8_default>; 1083 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1084 #address-cells = <1>; 1085 #size-cells = <0>; 1086 status = "disabled"; 1087 }; 1088 1089 uart8: serial@a80000 { 1090 compatible = "qcom,geni-uart"; 1091 reg = <0 0x00a80000 0 0x4000>; 1092 clock-names = "se"; 1093 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1094 pinctrl-names = "default"; 1095 pinctrl-0 = <&qup_uart8_default>; 1096 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1097 status = "disabled"; 1098 }; 1099 1100 i2c9: i2c@a84000 { 1101 compatible = "qcom,geni-i2c"; 1102 reg = <0 0x00a84000 0 0x4000>; 1103 clock-names = "se"; 1104 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1105 pinctrl-names = "default"; 1106 pinctrl-0 = <&qup_i2c9_default>; 1107 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1108 #address-cells = <1>; 1109 #size-cells = <0>; 1110 status = "disabled"; 1111 }; 1112 1113 spi9: spi@a84000 { 1114 compatible = "qcom,geni-spi"; 1115 reg = <0 0x00a84000 0 0x4000>; 1116 clock-names = "se"; 1117 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1118 pinctrl-names = "default"; 1119 pinctrl-0 = <&qup_spi9_default>; 1120 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1121 #address-cells = <1>; 1122 #size-cells = <0>; 1123 status = "disabled"; 1124 }; 1125 1126 uart9: serial@a84000 { 1127 compatible = "qcom,geni-debug-uart"; 1128 reg = <0 0x00a84000 0 0x4000>; 1129 clock-names = "se"; 1130 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1131 pinctrl-names = "default"; 1132 pinctrl-0 = <&qup_uart9_default>; 1133 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1134 status = "disabled"; 1135 }; 1136 1137 i2c10: i2c@a88000 { 1138 compatible = "qcom,geni-i2c"; 1139 reg = <0 0x00a88000 0 0x4000>; 1140 clock-names = "se"; 1141 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1142 pinctrl-names = "default"; 1143 pinctrl-0 = <&qup_i2c10_default>; 1144 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1145 #address-cells = <1>; 1146 #size-cells = <0>; 1147 status = "disabled"; 1148 }; 1149 1150 spi10: spi@a88000 { 1151 compatible = "qcom,geni-spi"; 1152 reg = <0 0x00a88000 0 0x4000>; 1153 clock-names = "se"; 1154 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1155 pinctrl-names = "default"; 1156 pinctrl-0 = <&qup_spi10_default>; 1157 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1158 #address-cells = <1>; 1159 #size-cells = <0>; 1160 status = "disabled"; 1161 }; 1162 1163 uart10: serial@a88000 { 1164 compatible = "qcom,geni-uart"; 1165 reg = <0 0x00a88000 0 0x4000>; 1166 clock-names = "se"; 1167 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1168 pinctrl-names = "default"; 1169 pinctrl-0 = <&qup_uart10_default>; 1170 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1171 status = "disabled"; 1172 }; 1173 1174 i2c11: i2c@a8c000 { 1175 compatible = "qcom,geni-i2c"; 1176 reg = <0 0x00a8c000 0 0x4000>; 1177 clock-names = "se"; 1178 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1179 pinctrl-names = "default"; 1180 pinctrl-0 = <&qup_i2c11_default>; 1181 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1182 #address-cells = <1>; 1183 #size-cells = <0>; 1184 status = "disabled"; 1185 }; 1186 1187 spi11: spi@a8c000 { 1188 compatible = "qcom,geni-spi"; 1189 reg = <0 0x00a8c000 0 0x4000>; 1190 clock-names = "se"; 1191 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1192 pinctrl-names = "default"; 1193 pinctrl-0 = <&qup_spi11_default>; 1194 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1195 #address-cells = <1>; 1196 #size-cells = <0>; 1197 status = "disabled"; 1198 }; 1199 1200 uart11: serial@a8c000 { 1201 compatible = "qcom,geni-uart"; 1202 reg = <0 0x00a8c000 0 0x4000>; 1203 clock-names = "se"; 1204 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1205 pinctrl-names = "default"; 1206 pinctrl-0 = <&qup_uart11_default>; 1207 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1208 status = "disabled"; 1209 }; 1210 1211 i2c12: i2c@a90000 { 1212 compatible = "qcom,geni-i2c"; 1213 reg = <0 0x00a90000 0 0x4000>; 1214 clock-names = "se"; 1215 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1216 pinctrl-names = "default"; 1217 pinctrl-0 = <&qup_i2c12_default>; 1218 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1219 #address-cells = <1>; 1220 #size-cells = <0>; 1221 status = "disabled"; 1222 }; 1223 1224 spi12: spi@a90000 { 1225 compatible = "qcom,geni-spi"; 1226 reg = <0 0x00a90000 0 0x4000>; 1227 clock-names = "se"; 1228 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1229 pinctrl-names = "default"; 1230 pinctrl-0 = <&qup_spi12_default>; 1231 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1232 #address-cells = <1>; 1233 #size-cells = <0>; 1234 status = "disabled"; 1235 }; 1236 1237 uart12: serial@a90000 { 1238 compatible = "qcom,geni-uart"; 1239 reg = <0 0x00a90000 0 0x4000>; 1240 clock-names = "se"; 1241 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1242 pinctrl-names = "default"; 1243 pinctrl-0 = <&qup_uart12_default>; 1244 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1245 status = "disabled"; 1246 }; 1247 1248 i2c13: i2c@a94000 { 1249 compatible = "qcom,geni-i2c"; 1250 reg = <0 0x00a94000 0 0x4000>; 1251 clock-names = "se"; 1252 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1253 pinctrl-names = "default"; 1254 pinctrl-0 = <&qup_i2c13_default>; 1255 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1256 #address-cells = <1>; 1257 #size-cells = <0>; 1258 status = "disabled"; 1259 }; 1260 1261 spi13: spi@a94000 { 1262 compatible = "qcom,geni-spi"; 1263 reg = <0 0x00a94000 0 0x4000>; 1264 clock-names = "se"; 1265 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1266 pinctrl-names = "default"; 1267 pinctrl-0 = <&qup_spi13_default>; 1268 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1269 #address-cells = <1>; 1270 #size-cells = <0>; 1271 status = "disabled"; 1272 }; 1273 1274 uart13: serial@a94000 { 1275 compatible = "qcom,geni-uart"; 1276 reg = <0 0x00a94000 0 0x4000>; 1277 clock-names = "se"; 1278 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1279 pinctrl-names = "default"; 1280 pinctrl-0 = <&qup_uart13_default>; 1281 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1282 status = "disabled"; 1283 }; 1284 1285 i2c14: i2c@a98000 { 1286 compatible = "qcom,geni-i2c"; 1287 reg = <0 0x00a98000 0 0x4000>; 1288 clock-names = "se"; 1289 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1290 pinctrl-names = "default"; 1291 pinctrl-0 = <&qup_i2c14_default>; 1292 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 1293 #address-cells = <1>; 1294 #size-cells = <0>; 1295 status = "disabled"; 1296 }; 1297 1298 spi14: spi@a98000 { 1299 compatible = "qcom,geni-spi"; 1300 reg = <0 0x00a98000 0 0x4000>; 1301 clock-names = "se"; 1302 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1303 pinctrl-names = "default"; 1304 pinctrl-0 = <&qup_spi14_default>; 1305 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 1306 #address-cells = <1>; 1307 #size-cells = <0>; 1308 status = "disabled"; 1309 }; 1310 1311 uart14: serial@a98000 { 1312 compatible = "qcom,geni-uart"; 1313 reg = <0 0x00a98000 0 0x4000>; 1314 clock-names = "se"; 1315 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1316 pinctrl-names = "default"; 1317 pinctrl-0 = <&qup_uart14_default>; 1318 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 1319 status = "disabled"; 1320 }; 1321 1322 i2c15: i2c@a9c000 { 1323 compatible = "qcom,geni-i2c"; 1324 reg = <0 0x00a9c000 0 0x4000>; 1325 clock-names = "se"; 1326 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1327 pinctrl-names = "default"; 1328 pinctrl-0 = <&qup_i2c15_default>; 1329 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1330 #address-cells = <1>; 1331 #size-cells = <0>; 1332 status = "disabled"; 1333 }; 1334 1335 spi15: spi@a9c000 { 1336 compatible = "qcom,geni-spi"; 1337 reg = <0 0x00a9c000 0 0x4000>; 1338 clock-names = "se"; 1339 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1340 pinctrl-names = "default"; 1341 pinctrl-0 = <&qup_spi15_default>; 1342 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1343 #address-cells = <1>; 1344 #size-cells = <0>; 1345 status = "disabled"; 1346 }; 1347 1348 uart15: serial@a9c000 { 1349 compatible = "qcom,geni-uart"; 1350 reg = <0 0x00a9c000 0 0x4000>; 1351 clock-names = "se"; 1352 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1353 pinctrl-names = "default"; 1354 pinctrl-0 = <&qup_uart15_default>; 1355 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1356 status = "disabled"; 1357 }; 1358 }; 1359 1360 cache-controller@1100000 { 1361 compatible = "qcom,sdm845-llcc"; 1362 reg = <0 0x01100000 0 0x200000>, <0 0x01300000 0 0x50000>; 1363 reg-names = "llcc_base", "llcc_broadcast_base"; 1364 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 1365 }; 1366 1367 ufs_mem_hc: ufshc@1d84000 { 1368 compatible = "qcom,sdm845-ufshc", "qcom,ufshc", 1369 "jedec,ufs-2.0"; 1370 reg = <0 0x01d84000 0 0x2500>; 1371 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 1372 phys = <&ufs_mem_phy_lanes>; 1373 phy-names = "ufsphy"; 1374 lanes-per-direction = <2>; 1375 power-domains = <&gcc UFS_PHY_GDSC>; 1376 #reset-cells = <1>; 1377 1378 iommus = <&apps_smmu 0x100 0xf>; 1379 1380 clock-names = 1381 "core_clk", 1382 "bus_aggr_clk", 1383 "iface_clk", 1384 "core_clk_unipro", 1385 "ref_clk", 1386 "tx_lane0_sync_clk", 1387 "rx_lane0_sync_clk", 1388 "rx_lane1_sync_clk"; 1389 clocks = 1390 <&gcc GCC_UFS_PHY_AXI_CLK>, 1391 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1392 <&gcc GCC_UFS_PHY_AHB_CLK>, 1393 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 1394 <&rpmhcc RPMH_CXO_CLK>, 1395 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 1396 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 1397 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 1398 freq-table-hz = 1399 <50000000 200000000>, 1400 <0 0>, 1401 <0 0>, 1402 <37500000 150000000>, 1403 <0 0>, 1404 <0 0>, 1405 <0 0>, 1406 <0 0>; 1407 1408 status = "disabled"; 1409 }; 1410 1411 ufs_mem_phy: phy@1d87000 { 1412 compatible = "qcom,sdm845-qmp-ufs-phy"; 1413 reg = <0 0x01d87000 0 0x18c>; 1414 #address-cells = <2>; 1415 #size-cells = <2>; 1416 ranges; 1417 clock-names = "ref", 1418 "ref_aux"; 1419 clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, 1420 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 1421 1422 resets = <&ufs_mem_hc 0>; 1423 reset-names = "ufsphy"; 1424 status = "disabled"; 1425 1426 ufs_mem_phy_lanes: lanes@1d87400 { 1427 reg = <0 0x01d87400 0 0x108>, 1428 <0 0x01d87600 0 0x1e0>, 1429 <0 0x01d87c00 0 0x1dc>, 1430 <0 0x01d87800 0 0x108>, 1431 <0 0x01d87a00 0 0x1e0>; 1432 #phy-cells = <0>; 1433 }; 1434 }; 1435 1436 tcsr_mutex_regs: syscon@1f40000 { 1437 compatible = "syscon"; 1438 reg = <0 0x01f40000 0 0x40000>; 1439 }; 1440 1441 tlmm: pinctrl@3400000 { 1442 compatible = "qcom,sdm845-pinctrl"; 1443 reg = <0 0x03400000 0 0xc00000>; 1444 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1445 gpio-controller; 1446 #gpio-cells = <2>; 1447 interrupt-controller; 1448 #interrupt-cells = <2>; 1449 gpio-ranges = <&tlmm 0 0 150>; 1450 1451 qspi_clk: qspi-clk { 1452 pinmux { 1453 pins = "gpio95"; 1454 function = "qspi_clk"; 1455 }; 1456 }; 1457 1458 qspi_cs0: qspi-cs0 { 1459 pinmux { 1460 pins = "gpio90"; 1461 function = "qspi_cs"; 1462 }; 1463 }; 1464 1465 qspi_cs1: qspi-cs1 { 1466 pinmux { 1467 pins = "gpio89"; 1468 function = "qspi_cs"; 1469 }; 1470 }; 1471 1472 qspi_data01: qspi-data01 { 1473 pinmux-data { 1474 pins = "gpio91", "gpio92"; 1475 function = "qspi_data"; 1476 }; 1477 }; 1478 1479 qspi_data12: qspi-data12 { 1480 pinmux-data { 1481 pins = "gpio93", "gpio94"; 1482 function = "qspi_data"; 1483 }; 1484 }; 1485 1486 qup_i2c0_default: qup-i2c0-default { 1487 pinmux { 1488 pins = "gpio0", "gpio1"; 1489 function = "qup0"; 1490 }; 1491 }; 1492 1493 qup_i2c1_default: qup-i2c1-default { 1494 pinmux { 1495 pins = "gpio17", "gpio18"; 1496 function = "qup1"; 1497 }; 1498 }; 1499 1500 qup_i2c2_default: qup-i2c2-default { 1501 pinmux { 1502 pins = "gpio27", "gpio28"; 1503 function = "qup2"; 1504 }; 1505 }; 1506 1507 qup_i2c3_default: qup-i2c3-default { 1508 pinmux { 1509 pins = "gpio41", "gpio42"; 1510 function = "qup3"; 1511 }; 1512 }; 1513 1514 qup_i2c4_default: qup-i2c4-default { 1515 pinmux { 1516 pins = "gpio89", "gpio90"; 1517 function = "qup4"; 1518 }; 1519 }; 1520 1521 qup_i2c5_default: qup-i2c5-default { 1522 pinmux { 1523 pins = "gpio85", "gpio86"; 1524 function = "qup5"; 1525 }; 1526 }; 1527 1528 qup_i2c6_default: qup-i2c6-default { 1529 pinmux { 1530 pins = "gpio45", "gpio46"; 1531 function = "qup6"; 1532 }; 1533 }; 1534 1535 qup_i2c7_default: qup-i2c7-default { 1536 pinmux { 1537 pins = "gpio93", "gpio94"; 1538 function = "qup7"; 1539 }; 1540 }; 1541 1542 qup_i2c8_default: qup-i2c8-default { 1543 pinmux { 1544 pins = "gpio65", "gpio66"; 1545 function = "qup8"; 1546 }; 1547 }; 1548 1549 qup_i2c9_default: qup-i2c9-default { 1550 pinmux { 1551 pins = "gpio6", "gpio7"; 1552 function = "qup9"; 1553 }; 1554 }; 1555 1556 qup_i2c10_default: qup-i2c10-default { 1557 pinmux { 1558 pins = "gpio55", "gpio56"; 1559 function = "qup10"; 1560 }; 1561 }; 1562 1563 qup_i2c11_default: qup-i2c11-default { 1564 pinmux { 1565 pins = "gpio31", "gpio32"; 1566 function = "qup11"; 1567 }; 1568 }; 1569 1570 qup_i2c12_default: qup-i2c12-default { 1571 pinmux { 1572 pins = "gpio49", "gpio50"; 1573 function = "qup12"; 1574 }; 1575 }; 1576 1577 qup_i2c13_default: qup-i2c13-default { 1578 pinmux { 1579 pins = "gpio105", "gpio106"; 1580 function = "qup13"; 1581 }; 1582 }; 1583 1584 qup_i2c14_default: qup-i2c14-default { 1585 pinmux { 1586 pins = "gpio33", "gpio34"; 1587 function = "qup14"; 1588 }; 1589 }; 1590 1591 qup_i2c15_default: qup-i2c15-default { 1592 pinmux { 1593 pins = "gpio81", "gpio82"; 1594 function = "qup15"; 1595 }; 1596 }; 1597 1598 qup_spi0_default: qup-spi0-default { 1599 pinmux { 1600 pins = "gpio0", "gpio1", 1601 "gpio2", "gpio3"; 1602 function = "qup0"; 1603 }; 1604 }; 1605 1606 qup_spi1_default: qup-spi1-default { 1607 pinmux { 1608 pins = "gpio17", "gpio18", 1609 "gpio19", "gpio20"; 1610 function = "qup1"; 1611 }; 1612 }; 1613 1614 qup_spi2_default: qup-spi2-default { 1615 pinmux { 1616 pins = "gpio27", "gpio28", 1617 "gpio29", "gpio30"; 1618 function = "qup2"; 1619 }; 1620 }; 1621 1622 qup_spi3_default: qup-spi3-default { 1623 pinmux { 1624 pins = "gpio41", "gpio42", 1625 "gpio43", "gpio44"; 1626 function = "qup3"; 1627 }; 1628 }; 1629 1630 qup_spi4_default: qup-spi4-default { 1631 pinmux { 1632 pins = "gpio89", "gpio90", 1633 "gpio91", "gpio92"; 1634 function = "qup4"; 1635 }; 1636 }; 1637 1638 qup_spi5_default: qup-spi5-default { 1639 pinmux { 1640 pins = "gpio85", "gpio86", 1641 "gpio87", "gpio88"; 1642 function = "qup5"; 1643 }; 1644 }; 1645 1646 qup_spi6_default: qup-spi6-default { 1647 pinmux { 1648 pins = "gpio45", "gpio46", 1649 "gpio47", "gpio48"; 1650 function = "qup6"; 1651 }; 1652 }; 1653 1654 qup_spi7_default: qup-spi7-default { 1655 pinmux { 1656 pins = "gpio93", "gpio94", 1657 "gpio95", "gpio96"; 1658 function = "qup7"; 1659 }; 1660 }; 1661 1662 qup_spi8_default: qup-spi8-default { 1663 pinmux { 1664 pins = "gpio65", "gpio66", 1665 "gpio67", "gpio68"; 1666 function = "qup8"; 1667 }; 1668 }; 1669 1670 qup_spi9_default: qup-spi9-default { 1671 pinmux { 1672 pins = "gpio6", "gpio7", 1673 "gpio4", "gpio5"; 1674 function = "qup9"; 1675 }; 1676 }; 1677 1678 qup_spi10_default: qup-spi10-default { 1679 pinmux { 1680 pins = "gpio55", "gpio56", 1681 "gpio53", "gpio54"; 1682 function = "qup10"; 1683 }; 1684 }; 1685 1686 qup_spi11_default: qup-spi11-default { 1687 pinmux { 1688 pins = "gpio31", "gpio32", 1689 "gpio33", "gpio34"; 1690 function = "qup11"; 1691 }; 1692 }; 1693 1694 qup_spi12_default: qup-spi12-default { 1695 pinmux { 1696 pins = "gpio49", "gpio50", 1697 "gpio51", "gpio52"; 1698 function = "qup12"; 1699 }; 1700 }; 1701 1702 qup_spi13_default: qup-spi13-default { 1703 pinmux { 1704 pins = "gpio105", "gpio106", 1705 "gpio107", "gpio108"; 1706 function = "qup13"; 1707 }; 1708 }; 1709 1710 qup_spi14_default: qup-spi14-default { 1711 pinmux { 1712 pins = "gpio33", "gpio34", 1713 "gpio31", "gpio32"; 1714 function = "qup14"; 1715 }; 1716 }; 1717 1718 qup_spi15_default: qup-spi15-default { 1719 pinmux { 1720 pins = "gpio81", "gpio82", 1721 "gpio83", "gpio84"; 1722 function = "qup15"; 1723 }; 1724 }; 1725 1726 qup_uart0_default: qup-uart0-default { 1727 pinmux { 1728 pins = "gpio2", "gpio3"; 1729 function = "qup0"; 1730 }; 1731 }; 1732 1733 qup_uart1_default: qup-uart1-default { 1734 pinmux { 1735 pins = "gpio19", "gpio20"; 1736 function = "qup1"; 1737 }; 1738 }; 1739 1740 qup_uart2_default: qup-uart2-default { 1741 pinmux { 1742 pins = "gpio29", "gpio30"; 1743 function = "qup2"; 1744 }; 1745 }; 1746 1747 qup_uart3_default: qup-uart3-default { 1748 pinmux { 1749 pins = "gpio43", "gpio44"; 1750 function = "qup3"; 1751 }; 1752 }; 1753 1754 qup_uart4_default: qup-uart4-default { 1755 pinmux { 1756 pins = "gpio91", "gpio92"; 1757 function = "qup4"; 1758 }; 1759 }; 1760 1761 qup_uart5_default: qup-uart5-default { 1762 pinmux { 1763 pins = "gpio87", "gpio88"; 1764 function = "qup5"; 1765 }; 1766 }; 1767 1768 qup_uart6_default: qup-uart6-default { 1769 pinmux { 1770 pins = "gpio47", "gpio48"; 1771 function = "qup6"; 1772 }; 1773 }; 1774 1775 qup_uart7_default: qup-uart7-default { 1776 pinmux { 1777 pins = "gpio95", "gpio96"; 1778 function = "qup7"; 1779 }; 1780 }; 1781 1782 qup_uart8_default: qup-uart8-default { 1783 pinmux { 1784 pins = "gpio67", "gpio68"; 1785 function = "qup8"; 1786 }; 1787 }; 1788 1789 qup_uart9_default: qup-uart9-default { 1790 pinmux { 1791 pins = "gpio4", "gpio5"; 1792 function = "qup9"; 1793 }; 1794 }; 1795 1796 qup_uart10_default: qup-uart10-default { 1797 pinmux { 1798 pins = "gpio53", "gpio54"; 1799 function = "qup10"; 1800 }; 1801 }; 1802 1803 qup_uart11_default: qup-uart11-default { 1804 pinmux { 1805 pins = "gpio33", "gpio34"; 1806 function = "qup11"; 1807 }; 1808 }; 1809 1810 qup_uart12_default: qup-uart12-default { 1811 pinmux { 1812 pins = "gpio51", "gpio52"; 1813 function = "qup12"; 1814 }; 1815 }; 1816 1817 qup_uart13_default: qup-uart13-default { 1818 pinmux { 1819 pins = "gpio107", "gpio108"; 1820 function = "qup13"; 1821 }; 1822 }; 1823 1824 qup_uart14_default: qup-uart14-default { 1825 pinmux { 1826 pins = "gpio31", "gpio32"; 1827 function = "qup14"; 1828 }; 1829 }; 1830 1831 qup_uart15_default: qup-uart15-default { 1832 pinmux { 1833 pins = "gpio83", "gpio84"; 1834 function = "qup15"; 1835 }; 1836 }; 1837 }; 1838 1839 mss_pil: remoteproc@4080000 { 1840 compatible = "qcom,sdm845-mss-pil"; 1841 reg = <0 0x04080000 0 0x408>, <0 0x04180000 0 0x48>; 1842 reg-names = "qdsp6", "rmb"; 1843 1844 interrupts-extended = 1845 <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, 1846 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1847 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1848 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1849 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 1850 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 1851 interrupt-names = "wdog", "fatal", "ready", 1852 "handover", "stop-ack", 1853 "shutdown-ack"; 1854 1855 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 1856 <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>, 1857 <&gcc GCC_BOOT_ROM_AHB_CLK>, 1858 <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>, 1859 <&gcc GCC_MSS_SNOC_AXI_CLK>, 1860 <&gcc GCC_MSS_MFAB_AXIS_CLK>, 1861 <&gcc GCC_PRNG_AHB_CLK>, 1862 <&rpmhcc RPMH_CXO_CLK>; 1863 clock-names = "iface", "bus", "mem", "gpll0_mss", 1864 "snoc_axi", "mnoc_axi", "prng", "xo"; 1865 1866 qcom,smem-states = <&modem_smp2p_out 0>; 1867 qcom,smem-state-names = "stop"; 1868 1869 resets = <&aoss_reset AOSS_CC_MSS_RESTART>, 1870 <&pdc_reset PDC_MODEM_SYNC_RESET>; 1871 reset-names = "mss_restart", "pdc_reset"; 1872 1873 qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>; 1874 1875 power-domains = <&aoss_qmp 2>, 1876 <&rpmhpd SDM845_CX>, 1877 <&rpmhpd SDM845_MX>, 1878 <&rpmhpd SDM845_MSS>; 1879 power-domain-names = "load_state", "cx", "mx", "mss"; 1880 1881 mba { 1882 memory-region = <&mba_region>; 1883 }; 1884 1885 mpss { 1886 memory-region = <&mpss_region>; 1887 }; 1888 1889 glink-edge { 1890 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 1891 label = "modem"; 1892 qcom,remote-pid = <1>; 1893 mboxes = <&apss_shared 12>; 1894 }; 1895 }; 1896 1897 gpucc: clock-controller@5090000 { 1898 compatible = "qcom,sdm845-gpucc"; 1899 reg = <0 0x05090000 0 0x9000>; 1900 #clock-cells = <1>; 1901 #reset-cells = <1>; 1902 #power-domain-cells = <1>; 1903 clocks = <&rpmhcc RPMH_CXO_CLK>; 1904 clock-names = "xo"; 1905 }; 1906 1907 stm@6002000 { 1908 compatible = "arm,coresight-stm", "arm,primecell"; 1909 reg = <0 0x06002000 0 0x1000>, 1910 <0 0x16280000 0 0x180000>; 1911 reg-names = "stm-base", "stm-stimulus-base"; 1912 1913 clocks = <&aoss_qmp>; 1914 clock-names = "apb_pclk"; 1915 1916 out-ports { 1917 port { 1918 stm_out: endpoint { 1919 remote-endpoint = 1920 <&funnel0_in7>; 1921 }; 1922 }; 1923 }; 1924 }; 1925 1926 funnel@6041000 { 1927 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1928 reg = <0 0x06041000 0 0x1000>; 1929 1930 clocks = <&aoss_qmp>; 1931 clock-names = "apb_pclk"; 1932 1933 out-ports { 1934 port { 1935 funnel0_out: endpoint { 1936 remote-endpoint = 1937 <&merge_funnel_in0>; 1938 }; 1939 }; 1940 }; 1941 1942 in-ports { 1943 #address-cells = <1>; 1944 #size-cells = <0>; 1945 1946 port@7 { 1947 reg = <7>; 1948 funnel0_in7: endpoint { 1949 remote-endpoint = <&stm_out>; 1950 }; 1951 }; 1952 }; 1953 }; 1954 1955 funnel@6043000 { 1956 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1957 reg = <0 0x06043000 0 0x1000>; 1958 1959 clocks = <&aoss_qmp>; 1960 clock-names = "apb_pclk"; 1961 1962 out-ports { 1963 port { 1964 funnel2_out: endpoint { 1965 remote-endpoint = 1966 <&merge_funnel_in2>; 1967 }; 1968 }; 1969 }; 1970 1971 in-ports { 1972 #address-cells = <1>; 1973 #size-cells = <0>; 1974 1975 port@5 { 1976 reg = <5>; 1977 funnel2_in5: endpoint { 1978 remote-endpoint = 1979 <&apss_merge_funnel_out>; 1980 }; 1981 }; 1982 }; 1983 }; 1984 1985 funnel@6045000 { 1986 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1987 reg = <0 0x06045000 0 0x1000>; 1988 1989 clocks = <&aoss_qmp>; 1990 clock-names = "apb_pclk"; 1991 1992 out-ports { 1993 port { 1994 merge_funnel_out: endpoint { 1995 remote-endpoint = <&etf_in>; 1996 }; 1997 }; 1998 }; 1999 2000 in-ports { 2001 #address-cells = <1>; 2002 #size-cells = <0>; 2003 2004 port@0 { 2005 reg = <0>; 2006 merge_funnel_in0: endpoint { 2007 remote-endpoint = 2008 <&funnel0_out>; 2009 }; 2010 }; 2011 2012 port@2 { 2013 reg = <2>; 2014 merge_funnel_in2: endpoint { 2015 remote-endpoint = 2016 <&funnel2_out>; 2017 }; 2018 }; 2019 }; 2020 }; 2021 2022 replicator@6046000 { 2023 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2024 reg = <0 0x06046000 0 0x1000>; 2025 2026 clocks = <&aoss_qmp>; 2027 clock-names = "apb_pclk"; 2028 2029 out-ports { 2030 port { 2031 replicator_out: endpoint { 2032 remote-endpoint = <&etr_in>; 2033 }; 2034 }; 2035 }; 2036 2037 in-ports { 2038 port { 2039 replicator_in: endpoint { 2040 remote-endpoint = <&etf_out>; 2041 }; 2042 }; 2043 }; 2044 }; 2045 2046 etf@6047000 { 2047 compatible = "arm,coresight-tmc", "arm,primecell"; 2048 reg = <0 0x06047000 0 0x1000>; 2049 2050 clocks = <&aoss_qmp>; 2051 clock-names = "apb_pclk"; 2052 2053 out-ports { 2054 port { 2055 etf_out: endpoint { 2056 remote-endpoint = 2057 <&replicator_in>; 2058 }; 2059 }; 2060 }; 2061 2062 in-ports { 2063 #address-cells = <1>; 2064 #size-cells = <0>; 2065 2066 port@1 { 2067 reg = <1>; 2068 etf_in: endpoint { 2069 remote-endpoint = 2070 <&merge_funnel_out>; 2071 }; 2072 }; 2073 }; 2074 }; 2075 2076 etr@6048000 { 2077 compatible = "arm,coresight-tmc", "arm,primecell"; 2078 reg = <0 0x06048000 0 0x1000>; 2079 2080 clocks = <&aoss_qmp>; 2081 clock-names = "apb_pclk"; 2082 arm,scatter-gather; 2083 2084 in-ports { 2085 port { 2086 etr_in: endpoint { 2087 remote-endpoint = 2088 <&replicator_out>; 2089 }; 2090 }; 2091 }; 2092 }; 2093 2094 etm@7040000 { 2095 compatible = "arm,coresight-etm4x", "arm,primecell"; 2096 reg = <0 0x07040000 0 0x1000>; 2097 2098 cpu = <&CPU0>; 2099 2100 clocks = <&aoss_qmp>; 2101 clock-names = "apb_pclk"; 2102 2103 out-ports { 2104 port { 2105 etm0_out: endpoint { 2106 remote-endpoint = 2107 <&apss_funnel_in0>; 2108 }; 2109 }; 2110 }; 2111 }; 2112 2113 etm@7140000 { 2114 compatible = "arm,coresight-etm4x", "arm,primecell"; 2115 reg = <0 0x07140000 0 0x1000>; 2116 2117 cpu = <&CPU1>; 2118 2119 clocks = <&aoss_qmp>; 2120 clock-names = "apb_pclk"; 2121 2122 out-ports { 2123 port { 2124 etm1_out: endpoint { 2125 remote-endpoint = 2126 <&apss_funnel_in1>; 2127 }; 2128 }; 2129 }; 2130 }; 2131 2132 etm@7240000 { 2133 compatible = "arm,coresight-etm4x", "arm,primecell"; 2134 reg = <0 0x07240000 0 0x1000>; 2135 2136 cpu = <&CPU2>; 2137 2138 clocks = <&aoss_qmp>; 2139 clock-names = "apb_pclk"; 2140 2141 out-ports { 2142 port { 2143 etm2_out: endpoint { 2144 remote-endpoint = 2145 <&apss_funnel_in2>; 2146 }; 2147 }; 2148 }; 2149 }; 2150 2151 etm@7340000 { 2152 compatible = "arm,coresight-etm4x", "arm,primecell"; 2153 reg = <0 0x07340000 0 0x1000>; 2154 2155 cpu = <&CPU3>; 2156 2157 clocks = <&aoss_qmp>; 2158 clock-names = "apb_pclk"; 2159 2160 out-ports { 2161 port { 2162 etm3_out: endpoint { 2163 remote-endpoint = 2164 <&apss_funnel_in3>; 2165 }; 2166 }; 2167 }; 2168 }; 2169 2170 etm@7440000 { 2171 compatible = "arm,coresight-etm4x", "arm,primecell"; 2172 reg = <0 0x07440000 0 0x1000>; 2173 2174 cpu = <&CPU4>; 2175 2176 clocks = <&aoss_qmp>; 2177 clock-names = "apb_pclk"; 2178 2179 out-ports { 2180 port { 2181 etm4_out: endpoint { 2182 remote-endpoint = 2183 <&apss_funnel_in4>; 2184 }; 2185 }; 2186 }; 2187 }; 2188 2189 etm@7540000 { 2190 compatible = "arm,coresight-etm4x", "arm,primecell"; 2191 reg = <0 0x07540000 0 0x1000>; 2192 2193 cpu = <&CPU5>; 2194 2195 clocks = <&aoss_qmp>; 2196 clock-names = "apb_pclk"; 2197 2198 out-ports { 2199 port { 2200 etm5_out: endpoint { 2201 remote-endpoint = 2202 <&apss_funnel_in5>; 2203 }; 2204 }; 2205 }; 2206 }; 2207 2208 etm@7640000 { 2209 compatible = "arm,coresight-etm4x", "arm,primecell"; 2210 reg = <0 0x07640000 0 0x1000>; 2211 2212 cpu = <&CPU6>; 2213 2214 clocks = <&aoss_qmp>; 2215 clock-names = "apb_pclk"; 2216 2217 out-ports { 2218 port { 2219 etm6_out: endpoint { 2220 remote-endpoint = 2221 <&apss_funnel_in6>; 2222 }; 2223 }; 2224 }; 2225 }; 2226 2227 etm@7740000 { 2228 compatible = "arm,coresight-etm4x", "arm,primecell"; 2229 reg = <0 0x07740000 0 0x1000>; 2230 2231 cpu = <&CPU7>; 2232 2233 clocks = <&aoss_qmp>; 2234 clock-names = "apb_pclk"; 2235 2236 out-ports { 2237 port { 2238 etm7_out: endpoint { 2239 remote-endpoint = 2240 <&apss_funnel_in7>; 2241 }; 2242 }; 2243 }; 2244 }; 2245 2246 funnel@7800000 { /* APSS Funnel */ 2247 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2248 reg = <0 0x07800000 0 0x1000>; 2249 2250 clocks = <&aoss_qmp>; 2251 clock-names = "apb_pclk"; 2252 2253 out-ports { 2254 port { 2255 apss_funnel_out: endpoint { 2256 remote-endpoint = 2257 <&apss_merge_funnel_in>; 2258 }; 2259 }; 2260 }; 2261 2262 in-ports { 2263 #address-cells = <1>; 2264 #size-cells = <0>; 2265 2266 port@0 { 2267 reg = <0>; 2268 apss_funnel_in0: endpoint { 2269 remote-endpoint = 2270 <&etm0_out>; 2271 }; 2272 }; 2273 2274 port@1 { 2275 reg = <1>; 2276 apss_funnel_in1: endpoint { 2277 remote-endpoint = 2278 <&etm1_out>; 2279 }; 2280 }; 2281 2282 port@2 { 2283 reg = <2>; 2284 apss_funnel_in2: endpoint { 2285 remote-endpoint = 2286 <&etm2_out>; 2287 }; 2288 }; 2289 2290 port@3 { 2291 reg = <3>; 2292 apss_funnel_in3: endpoint { 2293 remote-endpoint = 2294 <&etm3_out>; 2295 }; 2296 }; 2297 2298 port@4 { 2299 reg = <4>; 2300 apss_funnel_in4: endpoint { 2301 remote-endpoint = 2302 <&etm4_out>; 2303 }; 2304 }; 2305 2306 port@5 { 2307 reg = <5>; 2308 apss_funnel_in5: endpoint { 2309 remote-endpoint = 2310 <&etm5_out>; 2311 }; 2312 }; 2313 2314 port@6 { 2315 reg = <6>; 2316 apss_funnel_in6: endpoint { 2317 remote-endpoint = 2318 <&etm6_out>; 2319 }; 2320 }; 2321 2322 port@7 { 2323 reg = <7>; 2324 apss_funnel_in7: endpoint { 2325 remote-endpoint = 2326 <&etm7_out>; 2327 }; 2328 }; 2329 }; 2330 }; 2331 2332 funnel@7810000 { 2333 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2334 reg = <0 0x07810000 0 0x1000>; 2335 2336 clocks = <&aoss_qmp>; 2337 clock-names = "apb_pclk"; 2338 2339 out-ports { 2340 port { 2341 apss_merge_funnel_out: endpoint { 2342 remote-endpoint = 2343 <&funnel2_in5>; 2344 }; 2345 }; 2346 }; 2347 2348 in-ports { 2349 port { 2350 apss_merge_funnel_in: endpoint { 2351 remote-endpoint = 2352 <&apss_funnel_out>; 2353 }; 2354 }; 2355 }; 2356 }; 2357 2358 sdhc_2: sdhci@8804000 { 2359 compatible = "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5"; 2360 reg = <0 0x08804000 0 0x1000>; 2361 2362 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 2363 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 2364 interrupt-names = "hc_irq", "pwr_irq"; 2365 2366 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 2367 <&gcc GCC_SDCC2_APPS_CLK>; 2368 clock-names = "iface", "core"; 2369 iommus = <&apps_smmu 0xa0 0xf>; 2370 2371 status = "disabled"; 2372 }; 2373 2374 qspi: spi@88df000 { 2375 compatible = "qcom,sdm845-qspi", "qcom,qspi-v1"; 2376 reg = <0 0x088df000 0 0x600>; 2377 #address-cells = <1>; 2378 #size-cells = <0>; 2379 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 2380 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 2381 <&gcc GCC_QSPI_CORE_CLK>; 2382 clock-names = "iface", "core"; 2383 status = "disabled"; 2384 }; 2385 2386 usb_1_hsphy: phy@88e2000 { 2387 compatible = "qcom,sdm845-qusb2-phy"; 2388 reg = <0 0x088e2000 0 0x400>; 2389 status = "disabled"; 2390 #phy-cells = <0>; 2391 2392 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 2393 <&rpmhcc RPMH_CXO_CLK>; 2394 clock-names = "cfg_ahb", "ref"; 2395 2396 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2397 2398 nvmem-cells = <&qusb2p_hstx_trim>; 2399 }; 2400 2401 usb_2_hsphy: phy@88e3000 { 2402 compatible = "qcom,sdm845-qusb2-phy"; 2403 reg = <0 0x088e3000 0 0x400>; 2404 status = "disabled"; 2405 #phy-cells = <0>; 2406 2407 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 2408 <&rpmhcc RPMH_CXO_CLK>; 2409 clock-names = "cfg_ahb", "ref"; 2410 2411 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 2412 2413 nvmem-cells = <&qusb2s_hstx_trim>; 2414 }; 2415 2416 usb_1_qmpphy: phy@88e9000 { 2417 compatible = "qcom,sdm845-qmp-usb3-phy"; 2418 reg = <0 0x088e9000 0 0x18c>, 2419 <0 0x088e8000 0 0x10>; 2420 reg-names = "reg-base", "dp_com"; 2421 status = "disabled"; 2422 #clock-cells = <1>; 2423 #address-cells = <2>; 2424 #size-cells = <2>; 2425 ranges; 2426 2427 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2428 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 2429 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 2430 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 2431 clock-names = "aux", "cfg_ahb", "ref", "com_aux"; 2432 2433 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 2434 <&gcc GCC_USB3_PHY_PRIM_BCR>; 2435 reset-names = "phy", "common"; 2436 2437 usb_1_ssphy: lanes@88e9200 { 2438 reg = <0 0x088e9200 0 0x128>, 2439 <0 0x088e9400 0 0x200>, 2440 <0 0x088e9c00 0 0x218>, 2441 <0 0x088e9600 0 0x128>, 2442 <0 0x088e9800 0 0x200>, 2443 <0 0x088e9a00 0 0x100>; 2444 #phy-cells = <0>; 2445 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2446 clock-names = "pipe0"; 2447 clock-output-names = "usb3_phy_pipe_clk_src"; 2448 }; 2449 }; 2450 2451 usb_2_qmpphy: phy@88eb000 { 2452 compatible = "qcom,sdm845-qmp-usb3-uni-phy"; 2453 reg = <0 0x088eb000 0 0x18c>; 2454 status = "disabled"; 2455 #clock-cells = <1>; 2456 #address-cells = <2>; 2457 #size-cells = <2>; 2458 ranges; 2459 2460 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 2461 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 2462 <&gcc GCC_USB3_SEC_CLKREF_CLK>, 2463 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; 2464 clock-names = "aux", "cfg_ahb", "ref", "com_aux"; 2465 2466 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, 2467 <&gcc GCC_USB3_PHY_SEC_BCR>; 2468 reset-names = "phy", "common"; 2469 2470 usb_2_ssphy: lane@88eb200 { 2471 reg = <0 0x088eb200 0 0x128>, 2472 <0 0x088eb400 0 0x1fc>, 2473 <0 0x088eb800 0 0x218>, 2474 <0 0x088eb600 0 0x70>; 2475 #phy-cells = <0>; 2476 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 2477 clock-names = "pipe0"; 2478 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 2479 }; 2480 }; 2481 2482 usb_1: usb@a6f8800 { 2483 compatible = "qcom,sdm845-dwc3", "qcom,dwc3"; 2484 reg = <0 0x0a6f8800 0 0x400>; 2485 status = "disabled"; 2486 #address-cells = <2>; 2487 #size-cells = <2>; 2488 ranges; 2489 dma-ranges; 2490 2491 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 2492 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 2493 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2494 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2495 <&gcc GCC_USB30_PRIM_SLEEP_CLK>; 2496 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 2497 "sleep"; 2498 2499 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2500 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 2501 assigned-clock-rates = <19200000>, <150000000>; 2502 2503 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 2504 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>, 2505 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>, 2506 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>; 2507 interrupt-names = "hs_phy_irq", "ss_phy_irq", 2508 "dm_hs_phy_irq", "dp_hs_phy_irq"; 2509 2510 power-domains = <&gcc USB30_PRIM_GDSC>; 2511 2512 resets = <&gcc GCC_USB30_PRIM_BCR>; 2513 2514 usb_1_dwc3: dwc3@a600000 { 2515 compatible = "snps,dwc3"; 2516 reg = <0 0x0a600000 0 0xcd00>; 2517 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 2518 iommus = <&apps_smmu 0x740 0>; 2519 snps,dis_u2_susphy_quirk; 2520 snps,dis_enblslpm_quirk; 2521 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 2522 phy-names = "usb2-phy", "usb3-phy"; 2523 }; 2524 }; 2525 2526 usb_2: usb@a8f8800 { 2527 compatible = "qcom,sdm845-dwc3", "qcom,dwc3"; 2528 reg = <0 0x0a8f8800 0 0x400>; 2529 status = "disabled"; 2530 #address-cells = <2>; 2531 #size-cells = <2>; 2532 ranges; 2533 dma-ranges; 2534 2535 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 2536 <&gcc GCC_USB30_SEC_MASTER_CLK>, 2537 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 2538 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2539 <&gcc GCC_USB30_SEC_SLEEP_CLK>; 2540 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 2541 "sleep"; 2542 2543 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2544 <&gcc GCC_USB30_SEC_MASTER_CLK>; 2545 assigned-clock-rates = <19200000>, <150000000>; 2546 2547 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 2548 <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>, 2549 <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>, 2550 <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>; 2551 interrupt-names = "hs_phy_irq", "ss_phy_irq", 2552 "dm_hs_phy_irq", "dp_hs_phy_irq"; 2553 2554 power-domains = <&gcc USB30_SEC_GDSC>; 2555 2556 resets = <&gcc GCC_USB30_SEC_BCR>; 2557 2558 usb_2_dwc3: dwc3@a800000 { 2559 compatible = "snps,dwc3"; 2560 reg = <0 0x0a800000 0 0xcd00>; 2561 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 2562 iommus = <&apps_smmu 0x760 0>; 2563 snps,dis_u2_susphy_quirk; 2564 snps,dis_enblslpm_quirk; 2565 phys = <&usb_2_hsphy>, <&usb_2_ssphy>; 2566 phy-names = "usb2-phy", "usb3-phy"; 2567 }; 2568 }; 2569 2570 video-codec@aa00000 { 2571 compatible = "qcom,sdm845-venus"; 2572 reg = <0 0x0aa00000 0 0xff000>; 2573 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 2574 power-domains = <&videocc VENUS_GDSC>; 2575 clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>, 2576 <&videocc VIDEO_CC_VENUS_AHB_CLK>, 2577 <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>; 2578 clock-names = "core", "iface", "bus"; 2579 iommus = <&apps_smmu 0x10a0 0x8>, 2580 <&apps_smmu 0x10b0 0x0>; 2581 memory-region = <&venus_mem>; 2582 2583 video-core0 { 2584 compatible = "venus-decoder"; 2585 clocks = <&videocc VIDEO_CC_VCODEC0_CORE_CLK>, 2586 <&videocc VIDEO_CC_VCODEC0_AXI_CLK>; 2587 clock-names = "core", "bus"; 2588 power-domains = <&videocc VCODEC0_GDSC>; 2589 }; 2590 2591 video-core1 { 2592 compatible = "venus-encoder"; 2593 clocks = <&videocc VIDEO_CC_VCODEC1_CORE_CLK>, 2594 <&videocc VIDEO_CC_VCODEC1_AXI_CLK>; 2595 clock-names = "core", "bus"; 2596 power-domains = <&videocc VCODEC1_GDSC>; 2597 }; 2598 }; 2599 2600 videocc: clock-controller@ab00000 { 2601 compatible = "qcom,sdm845-videocc"; 2602 reg = <0 0x0ab00000 0 0x10000>; 2603 #clock-cells = <1>; 2604 #power-domain-cells = <1>; 2605 #reset-cells = <1>; 2606 }; 2607 2608 mdss: mdss@ae00000 { 2609 compatible = "qcom,sdm845-mdss"; 2610 reg = <0 0x0ae00000 0 0x1000>; 2611 reg-names = "mdss"; 2612 2613 power-domains = <&dispcc MDSS_GDSC>; 2614 2615 clocks = <&gcc GCC_DISP_AHB_CLK>, 2616 <&gcc GCC_DISP_AXI_CLK>, 2617 <&dispcc DISP_CC_MDSS_MDP_CLK>; 2618 clock-names = "iface", "bus", "core"; 2619 2620 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; 2621 assigned-clock-rates = <300000000>; 2622 2623 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2624 interrupt-controller; 2625 #interrupt-cells = <1>; 2626 2627 iommus = <&apps_smmu 0x880 0x8>, 2628 <&apps_smmu 0xc80 0x8>; 2629 2630 status = "disabled"; 2631 2632 #address-cells = <2>; 2633 #size-cells = <2>; 2634 ranges; 2635 2636 mdss_mdp: mdp@ae01000 { 2637 compatible = "qcom,sdm845-dpu"; 2638 reg = <0 0x0ae01000 0 0x8f000>, 2639 <0 0x0aeb0000 0 0x2008>; 2640 reg-names = "mdp", "vbif"; 2641 2642 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2643 <&dispcc DISP_CC_MDSS_AXI_CLK>, 2644 <&dispcc DISP_CC_MDSS_MDP_CLK>, 2645 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2646 clock-names = "iface", "bus", "core", "vsync"; 2647 2648 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, 2649 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2650 assigned-clock-rates = <300000000>, 2651 <19200000>; 2652 2653 interrupt-parent = <&mdss>; 2654 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; 2655 2656 status = "disabled"; 2657 2658 ports { 2659 #address-cells = <1>; 2660 #size-cells = <0>; 2661 2662 port@0 { 2663 reg = <0>; 2664 dpu_intf1_out: endpoint { 2665 remote-endpoint = <&dsi0_in>; 2666 }; 2667 }; 2668 2669 port@1 { 2670 reg = <1>; 2671 dpu_intf2_out: endpoint { 2672 remote-endpoint = <&dsi1_in>; 2673 }; 2674 }; 2675 }; 2676 }; 2677 2678 dsi0: dsi@ae94000 { 2679 compatible = "qcom,mdss-dsi-ctrl"; 2680 reg = <0 0x0ae94000 0 0x400>; 2681 reg-names = "dsi_ctrl"; 2682 2683 interrupt-parent = <&mdss>; 2684 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; 2685 2686 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 2687 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 2688 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 2689 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 2690 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2691 <&dispcc DISP_CC_MDSS_AXI_CLK>; 2692 clock-names = "byte", 2693 "byte_intf", 2694 "pixel", 2695 "core", 2696 "iface", 2697 "bus"; 2698 2699 phys = <&dsi0_phy>; 2700 phy-names = "dsi"; 2701 2702 status = "disabled"; 2703 2704 ports { 2705 #address-cells = <1>; 2706 #size-cells = <0>; 2707 2708 port@0 { 2709 reg = <0>; 2710 dsi0_in: endpoint { 2711 remote-endpoint = <&dpu_intf1_out>; 2712 }; 2713 }; 2714 2715 port@1 { 2716 reg = <1>; 2717 dsi0_out: endpoint { 2718 }; 2719 }; 2720 }; 2721 }; 2722 2723 dsi0_phy: dsi-phy@ae94400 { 2724 compatible = "qcom,dsi-phy-10nm"; 2725 reg = <0 0x0ae94400 0 0x200>, 2726 <0 0x0ae94600 0 0x280>, 2727 <0 0x0ae94a00 0 0x1e0>; 2728 reg-names = "dsi_phy", 2729 "dsi_phy_lane", 2730 "dsi_pll"; 2731 2732 #clock-cells = <1>; 2733 #phy-cells = <0>; 2734 2735 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2736 <&rpmhcc RPMH_CXO_CLK>; 2737 clock-names = "iface", "ref"; 2738 2739 status = "disabled"; 2740 }; 2741 2742 dsi1: dsi@ae96000 { 2743 compatible = "qcom,mdss-dsi-ctrl"; 2744 reg = <0 0x0ae96000 0 0x400>; 2745 reg-names = "dsi_ctrl"; 2746 2747 interrupt-parent = <&mdss>; 2748 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; 2749 2750 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 2751 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 2752 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 2753 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 2754 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2755 <&dispcc DISP_CC_MDSS_AXI_CLK>; 2756 clock-names = "byte", 2757 "byte_intf", 2758 "pixel", 2759 "core", 2760 "iface", 2761 "bus"; 2762 2763 phys = <&dsi1_phy>; 2764 phy-names = "dsi"; 2765 2766 status = "disabled"; 2767 2768 ports { 2769 #address-cells = <1>; 2770 #size-cells = <0>; 2771 2772 port@0 { 2773 reg = <0>; 2774 dsi1_in: endpoint { 2775 remote-endpoint = <&dpu_intf2_out>; 2776 }; 2777 }; 2778 2779 port@1 { 2780 reg = <1>; 2781 dsi1_out: endpoint { 2782 }; 2783 }; 2784 }; 2785 }; 2786 2787 dsi1_phy: dsi-phy@ae96400 { 2788 compatible = "qcom,dsi-phy-10nm"; 2789 reg = <0 0x0ae96400 0 0x200>, 2790 <0 0x0ae96600 0 0x280>, 2791 <0 0x0ae96a00 0 0x10e>; 2792 reg-names = "dsi_phy", 2793 "dsi_phy_lane", 2794 "dsi_pll"; 2795 2796 #clock-cells = <1>; 2797 #phy-cells = <0>; 2798 2799 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2800 <&rpmhcc RPMH_CXO_CLK>; 2801 clock-names = "iface", "ref"; 2802 2803 status = "disabled"; 2804 }; 2805 }; 2806 2807 gpu@5000000 { 2808 compatible = "qcom,adreno-630.2", "qcom,adreno"; 2809 #stream-id-cells = <16>; 2810 2811 reg = <0 0x5000000 0 0x40000>, <0 0x509e000 0 0x10>; 2812 reg-names = "kgsl_3d0_reg_memory", "cx_mem"; 2813 2814 /* 2815 * Look ma, no clocks! The GPU clocks and power are 2816 * controlled entirely by the GMU 2817 */ 2818 2819 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2820 2821 iommus = <&adreno_smmu 0>; 2822 2823 operating-points-v2 = <&gpu_opp_table>; 2824 2825 qcom,gmu = <&gmu>; 2826 2827 zap_shader: zap-shader { 2828 memory-region = <&gpu_mem>; 2829 }; 2830 2831 gpu_opp_table: opp-table { 2832 compatible = "operating-points-v2"; 2833 2834 opp-710000000 { 2835 opp-hz = /bits/ 64 <710000000>; 2836 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 2837 }; 2838 2839 opp-675000000 { 2840 opp-hz = /bits/ 64 <675000000>; 2841 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2842 }; 2843 2844 opp-596000000 { 2845 opp-hz = /bits/ 64 <596000000>; 2846 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2847 }; 2848 2849 opp-520000000 { 2850 opp-hz = /bits/ 64 <520000000>; 2851 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2852 }; 2853 2854 opp-414000000 { 2855 opp-hz = /bits/ 64 <414000000>; 2856 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2857 }; 2858 2859 opp-342000000 { 2860 opp-hz = /bits/ 64 <342000000>; 2861 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2862 }; 2863 2864 opp-257000000 { 2865 opp-hz = /bits/ 64 <257000000>; 2866 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2867 }; 2868 }; 2869 }; 2870 2871 adreno_smmu: iommu@5040000 { 2872 compatible = "qcom,sdm845-smmu-v2", "qcom,smmu-v2"; 2873 reg = <0 0x5040000 0 0x10000>; 2874 #iommu-cells = <1>; 2875 #global-interrupts = <2>; 2876 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 2877 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 2878 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, 2879 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, 2880 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>, 2881 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>, 2882 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>, 2883 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>, 2884 <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>, 2885 <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>; 2886 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2887 <&gcc GCC_GPU_CFG_AHB_CLK>; 2888 clock-names = "bus", "iface"; 2889 2890 power-domains = <&gpucc GPU_CX_GDSC>; 2891 }; 2892 2893 gmu: gmu@506a000 { 2894 compatible="qcom,adreno-gmu-630.2", "qcom,adreno-gmu"; 2895 2896 reg = <0 0x506a000 0 0x30000>, 2897 <0 0xb280000 0 0x10000>, 2898 <0 0xb480000 0 0x10000>; 2899 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; 2900 2901 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2902 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2903 interrupt-names = "hfi", "gmu"; 2904 2905 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 2906 <&gpucc GPU_CC_CXO_CLK>, 2907 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2908 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 2909 clock-names = "gmu", "cxo", "axi", "memnoc"; 2910 2911 power-domains = <&gpucc GPU_CX_GDSC>, 2912 <&gpucc GPU_GX_GDSC>; 2913 power-domain-names = "cx", "gx"; 2914 2915 iommus = <&adreno_smmu 5>; 2916 2917 operating-points-v2 = <&gmu_opp_table>; 2918 2919 gmu_opp_table: opp-table { 2920 compatible = "operating-points-v2"; 2921 2922 opp-400000000 { 2923 opp-hz = /bits/ 64 <400000000>; 2924 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2925 }; 2926 2927 opp-200000000 { 2928 opp-hz = /bits/ 64 <200000000>; 2929 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2930 }; 2931 }; 2932 }; 2933 2934 dispcc: clock-controller@af00000 { 2935 compatible = "qcom,sdm845-dispcc"; 2936 reg = <0 0x0af00000 0 0x10000>; 2937 #clock-cells = <1>; 2938 #reset-cells = <1>; 2939 #power-domain-cells = <1>; 2940 }; 2941 2942 pdc_reset: reset-controller@b2e0000 { 2943 compatible = "qcom,sdm845-pdc-global"; 2944 reg = <0 0x0b2e0000 0 0x20000>; 2945 #reset-cells = <1>; 2946 }; 2947 2948 tsens0: thermal-sensor@c263000 { 2949 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; 2950 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 2951 <0 0x0c222000 0 0x1ff>; /* SROT */ 2952 #qcom,sensors = <13>; 2953 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>; 2954 interrupt-names = "uplow"; 2955 #thermal-sensor-cells = <1>; 2956 }; 2957 2958 tsens1: thermal-sensor@c265000 { 2959 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; 2960 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 2961 <0 0x0c223000 0 0x1ff>; /* SROT */ 2962 #qcom,sensors = <8>; 2963 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>; 2964 interrupt-names = "uplow"; 2965 #thermal-sensor-cells = <1>; 2966 }; 2967 2968 aoss_reset: reset-controller@c2a0000 { 2969 compatible = "qcom,sdm845-aoss-cc"; 2970 reg = <0 0x0c2a0000 0 0x31000>; 2971 #reset-cells = <1>; 2972 }; 2973 2974 aoss_qmp: qmp@c300000 { 2975 compatible = "qcom,sdm845-aoss-qmp"; 2976 reg = <0 0x0c300000 0 0x100000>; 2977 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; 2978 mboxes = <&apss_shared 0>; 2979 2980 #clock-cells = <0>; 2981 #power-domain-cells = <1>; 2982 2983 cx_cdev: cx { 2984 #cooling-cells = <2>; 2985 }; 2986 2987 ebi_cdev: ebi { 2988 #cooling-cells = <2>; 2989 }; 2990 }; 2991 2992 spmi_bus: spmi@c440000 { 2993 compatible = "qcom,spmi-pmic-arb"; 2994 reg = <0 0x0c440000 0 0x1100>, 2995 <0 0x0c600000 0 0x2000000>, 2996 <0 0x0e600000 0 0x100000>, 2997 <0 0x0e700000 0 0xa0000>, 2998 <0 0x0c40a000 0 0x26000>; 2999 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 3000 interrupt-names = "periph_irq"; 3001 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>; 3002 qcom,ee = <0>; 3003 qcom,channel = <0>; 3004 #address-cells = <2>; 3005 #size-cells = <0>; 3006 interrupt-controller; 3007 #interrupt-cells = <4>; 3008 cell-index = <0>; 3009 }; 3010 3011 apps_smmu: iommu@15000000 { 3012 compatible = "qcom,sdm845-smmu-500", "arm,mmu-500"; 3013 reg = <0 0x15000000 0 0x80000>; 3014 #iommu-cells = <2>; 3015 #global-interrupts = <1>; 3016 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3017 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 3018 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3019 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3020 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3021 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3022 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3023 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3024 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3025 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3026 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3027 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3028 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3029 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3030 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3031 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3032 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3033 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3034 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3035 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3036 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3037 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3038 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3039 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3040 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3041 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3042 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3043 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3044 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3045 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3046 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3047 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3048 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3049 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3050 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3051 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3052 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3053 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3054 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3055 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3056 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3057 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3058 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3059 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3060 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3061 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3062 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3063 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3064 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3065 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3066 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3067 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3068 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3069 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3070 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3071 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3072 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3073 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3074 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3075 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3076 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3077 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3078 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3079 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3080 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>; 3081 }; 3082 3083 lpasscc: clock-controller@17014000 { 3084 compatible = "qcom,sdm845-lpasscc"; 3085 reg = <0 0x17014000 0 0x1f004>, <0 0x17300000 0 0x200>; 3086 reg-names = "cc", "qdsp6ss"; 3087 #clock-cells = <1>; 3088 status = "disabled"; 3089 }; 3090 3091 watchdog@17980000 { 3092 compatible = "qcom,apss-wdt-sdm845", "qcom,kpss-wdt"; 3093 reg = <0 0x17980000 0 0x1000>; 3094 clocks = <&sleep_clk>; 3095 }; 3096 3097 apss_shared: mailbox@17990000 { 3098 compatible = "qcom,sdm845-apss-shared"; 3099 reg = <0 0x17990000 0 0x1000>; 3100 #mbox-cells = <1>; 3101 }; 3102 3103 apps_rsc: rsc@179c0000 { 3104 label = "apps_rsc"; 3105 compatible = "qcom,rpmh-rsc"; 3106 reg = <0 0x179c0000 0 0x10000>, 3107 <0 0x179d0000 0 0x10000>, 3108 <0 0x179e0000 0 0x10000>; 3109 reg-names = "drv-0", "drv-1", "drv-2"; 3110 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3111 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3112 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3113 qcom,tcs-offset = <0xd00>; 3114 qcom,drv-id = <2>; 3115 qcom,tcs-config = <ACTIVE_TCS 2>, 3116 <SLEEP_TCS 3>, 3117 <WAKE_TCS 3>, 3118 <CONTROL_TCS 1>; 3119 3120 rpmhcc: clock-controller { 3121 compatible = "qcom,sdm845-rpmh-clk"; 3122 #clock-cells = <1>; 3123 clock-names = "xo"; 3124 clocks = <&xo_board>; 3125 }; 3126 3127 rpmhpd: power-controller { 3128 compatible = "qcom,sdm845-rpmhpd"; 3129 #power-domain-cells = <1>; 3130 operating-points-v2 = <&rpmhpd_opp_table>; 3131 3132 rpmhpd_opp_table: opp-table { 3133 compatible = "operating-points-v2"; 3134 3135 rpmhpd_opp_ret: opp1 { 3136 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3137 }; 3138 3139 rpmhpd_opp_min_svs: opp2 { 3140 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3141 }; 3142 3143 rpmhpd_opp_low_svs: opp3 { 3144 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3145 }; 3146 3147 rpmhpd_opp_svs: opp4 { 3148 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3149 }; 3150 3151 rpmhpd_opp_svs_l1: opp5 { 3152 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3153 }; 3154 3155 rpmhpd_opp_nom: opp6 { 3156 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3157 }; 3158 3159 rpmhpd_opp_nom_l1: opp7 { 3160 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3161 }; 3162 3163 rpmhpd_opp_nom_l2: opp8 { 3164 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 3165 }; 3166 3167 rpmhpd_opp_turbo: opp9 { 3168 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3169 }; 3170 3171 rpmhpd_opp_turbo_l1: opp10 { 3172 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3173 }; 3174 }; 3175 }; 3176 3177 rsc_hlos: interconnect { 3178 compatible = "qcom,sdm845-rsc-hlos"; 3179 #interconnect-cells = <1>; 3180 }; 3181 }; 3182 3183 intc: interrupt-controller@17a00000 { 3184 compatible = "arm,gic-v3"; 3185 #address-cells = <2>; 3186 #size-cells = <2>; 3187 ranges; 3188 #interrupt-cells = <3>; 3189 interrupt-controller; 3190 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 3191 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 3192 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3193 3194 gic-its@17a40000 { 3195 compatible = "arm,gic-v3-its"; 3196 msi-controller; 3197 #msi-cells = <1>; 3198 reg = <0 0x17a40000 0 0x20000>; 3199 status = "disabled"; 3200 }; 3201 }; 3202 3203 timer@17c90000 { 3204 #address-cells = <2>; 3205 #size-cells = <2>; 3206 ranges; 3207 compatible = "arm,armv7-timer-mem"; 3208 reg = <0 0x17c90000 0 0x1000>; 3209 3210 frame@17ca0000 { 3211 frame-number = <0>; 3212 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 3213 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3214 reg = <0 0x17ca0000 0 0x1000>, 3215 <0 0x17cb0000 0 0x1000>; 3216 }; 3217 3218 frame@17cc0000 { 3219 frame-number = <1>; 3220 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 3221 reg = <0 0x17cc0000 0 0x1000>; 3222 status = "disabled"; 3223 }; 3224 3225 frame@17cd0000 { 3226 frame-number = <2>; 3227 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3228 reg = <0 0x17cd0000 0 0x1000>; 3229 status = "disabled"; 3230 }; 3231 3232 frame@17ce0000 { 3233 frame-number = <3>; 3234 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3235 reg = <0 0x17ce0000 0 0x1000>; 3236 status = "disabled"; 3237 }; 3238 3239 frame@17cf0000 { 3240 frame-number = <4>; 3241 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3242 reg = <0 0x17cf0000 0 0x1000>; 3243 status = "disabled"; 3244 }; 3245 3246 frame@17d00000 { 3247 frame-number = <5>; 3248 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3249 reg = <0 0x17d00000 0 0x1000>; 3250 status = "disabled"; 3251 }; 3252 3253 frame@17d10000 { 3254 frame-number = <6>; 3255 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3256 reg = <0 0x17d10000 0 0x1000>; 3257 status = "disabled"; 3258 }; 3259 }; 3260 3261 cpufreq_hw: cpufreq@17d43000 { 3262 compatible = "qcom,cpufreq-hw"; 3263 reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>; 3264 reg-names = "freq-domain0", "freq-domain1"; 3265 3266 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 3267 clock-names = "xo", "alternate"; 3268 3269 #freq-domain-cells = <1>; 3270 }; 3271 3272 wifi: wifi@18800000 { 3273 compatible = "qcom,wcn3990-wifi"; 3274 status = "disabled"; 3275 reg = <0 0x18800000 0 0x800000>; 3276 reg-names = "membase"; 3277 memory-region = <&wlan_msa_mem>; 3278 clock-names = "cxo_ref_clk_pin"; 3279 clocks = <&rpmhcc RPMH_RF_CLK2>; 3280 interrupts = 3281 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 3282 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 3283 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 3284 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 3285 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 3286 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 3287 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 3288 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 3289 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 3290 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 3291 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 3292 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 3293 iommus = <&apps_smmu 0x0040 0x1>; 3294 }; 3295 }; 3296 3297 thermal-zones { 3298 cpu0-thermal { 3299 polling-delay-passive = <250>; 3300 polling-delay = <1000>; 3301 3302 thermal-sensors = <&tsens0 1>; 3303 3304 trips { 3305 cpu0_alert0: trip-point0 { 3306 temperature = <90000>; 3307 hysteresis = <2000>; 3308 type = "passive"; 3309 }; 3310 3311 cpu0_alert1: trip-point1 { 3312 temperature = <95000>; 3313 hysteresis = <2000>; 3314 type = "passive"; 3315 }; 3316 3317 cpu0_crit: cpu_crit { 3318 temperature = <110000>; 3319 hysteresis = <1000>; 3320 type = "critical"; 3321 }; 3322 }; 3323 3324 cooling-maps { 3325 map0 { 3326 trip = <&cpu0_alert0>; 3327 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3328 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3329 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3330 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3331 }; 3332 map1 { 3333 trip = <&cpu0_alert1>; 3334 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3335 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3336 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3337 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3338 }; 3339 }; 3340 }; 3341 3342 cpu1-thermal { 3343 polling-delay-passive = <250>; 3344 polling-delay = <1000>; 3345 3346 thermal-sensors = <&tsens0 2>; 3347 3348 trips { 3349 cpu1_alert0: trip-point0 { 3350 temperature = <90000>; 3351 hysteresis = <2000>; 3352 type = "passive"; 3353 }; 3354 3355 cpu1_alert1: trip-point1 { 3356 temperature = <95000>; 3357 hysteresis = <2000>; 3358 type = "passive"; 3359 }; 3360 3361 cpu1_crit: cpu_crit { 3362 temperature = <110000>; 3363 hysteresis = <1000>; 3364 type = "critical"; 3365 }; 3366 }; 3367 3368 cooling-maps { 3369 map0 { 3370 trip = <&cpu1_alert0>; 3371 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3372 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3373 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3374 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3375 }; 3376 map1 { 3377 trip = <&cpu1_alert1>; 3378 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3379 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3380 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3381 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3382 }; 3383 }; 3384 }; 3385 3386 cpu2-thermal { 3387 polling-delay-passive = <250>; 3388 polling-delay = <1000>; 3389 3390 thermal-sensors = <&tsens0 3>; 3391 3392 trips { 3393 cpu2_alert0: trip-point0 { 3394 temperature = <90000>; 3395 hysteresis = <2000>; 3396 type = "passive"; 3397 }; 3398 3399 cpu2_alert1: trip-point1 { 3400 temperature = <95000>; 3401 hysteresis = <2000>; 3402 type = "passive"; 3403 }; 3404 3405 cpu2_crit: cpu_crit { 3406 temperature = <110000>; 3407 hysteresis = <1000>; 3408 type = "critical"; 3409 }; 3410 }; 3411 3412 cooling-maps { 3413 map0 { 3414 trip = <&cpu2_alert0>; 3415 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3416 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3417 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3418 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3419 }; 3420 map1 { 3421 trip = <&cpu2_alert1>; 3422 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3423 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3424 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3425 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3426 }; 3427 }; 3428 }; 3429 3430 cpu3-thermal { 3431 polling-delay-passive = <250>; 3432 polling-delay = <1000>; 3433 3434 thermal-sensors = <&tsens0 4>; 3435 3436 trips { 3437 cpu3_alert0: trip-point0 { 3438 temperature = <90000>; 3439 hysteresis = <2000>; 3440 type = "passive"; 3441 }; 3442 3443 cpu3_alert1: trip-point1 { 3444 temperature = <95000>; 3445 hysteresis = <2000>; 3446 type = "passive"; 3447 }; 3448 3449 cpu3_crit: cpu_crit { 3450 temperature = <110000>; 3451 hysteresis = <1000>; 3452 type = "critical"; 3453 }; 3454 }; 3455 3456 cooling-maps { 3457 map0 { 3458 trip = <&cpu3_alert0>; 3459 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3460 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3461 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3462 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3463 }; 3464 map1 { 3465 trip = <&cpu3_alert1>; 3466 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3467 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3468 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3469 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3470 }; 3471 }; 3472 }; 3473 3474 cpu4-thermal { 3475 polling-delay-passive = <250>; 3476 polling-delay = <1000>; 3477 3478 thermal-sensors = <&tsens0 7>; 3479 3480 trips { 3481 cpu4_alert0: trip-point0 { 3482 temperature = <90000>; 3483 hysteresis = <2000>; 3484 type = "passive"; 3485 }; 3486 3487 cpu4_alert1: trip-point1 { 3488 temperature = <95000>; 3489 hysteresis = <2000>; 3490 type = "passive"; 3491 }; 3492 3493 cpu4_crit: cpu_crit { 3494 temperature = <110000>; 3495 hysteresis = <1000>; 3496 type = "critical"; 3497 }; 3498 }; 3499 3500 cooling-maps { 3501 map0 { 3502 trip = <&cpu4_alert0>; 3503 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3504 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3505 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3506 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3507 }; 3508 map1 { 3509 trip = <&cpu4_alert1>; 3510 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3511 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3512 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3513 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3514 }; 3515 }; 3516 }; 3517 3518 cpu5-thermal { 3519 polling-delay-passive = <250>; 3520 polling-delay = <1000>; 3521 3522 thermal-sensors = <&tsens0 8>; 3523 3524 trips { 3525 cpu5_alert0: trip-point0 { 3526 temperature = <90000>; 3527 hysteresis = <2000>; 3528 type = "passive"; 3529 }; 3530 3531 cpu5_alert1: trip-point1 { 3532 temperature = <95000>; 3533 hysteresis = <2000>; 3534 type = "passive"; 3535 }; 3536 3537 cpu5_crit: cpu_crit { 3538 temperature = <110000>; 3539 hysteresis = <1000>; 3540 type = "critical"; 3541 }; 3542 }; 3543 3544 cooling-maps { 3545 map0 { 3546 trip = <&cpu5_alert0>; 3547 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3548 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3549 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3550 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3551 }; 3552 map1 { 3553 trip = <&cpu5_alert1>; 3554 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3555 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3556 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3557 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3558 }; 3559 }; 3560 }; 3561 3562 cpu6-thermal { 3563 polling-delay-passive = <250>; 3564 polling-delay = <1000>; 3565 3566 thermal-sensors = <&tsens0 9>; 3567 3568 trips { 3569 cpu6_alert0: trip-point0 { 3570 temperature = <90000>; 3571 hysteresis = <2000>; 3572 type = "passive"; 3573 }; 3574 3575 cpu6_alert1: trip-point1 { 3576 temperature = <95000>; 3577 hysteresis = <2000>; 3578 type = "passive"; 3579 }; 3580 3581 cpu6_crit: cpu_crit { 3582 temperature = <110000>; 3583 hysteresis = <1000>; 3584 type = "critical"; 3585 }; 3586 }; 3587 3588 cooling-maps { 3589 map0 { 3590 trip = <&cpu6_alert0>; 3591 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3592 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3593 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3594 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3595 }; 3596 map1 { 3597 trip = <&cpu6_alert1>; 3598 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3599 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3600 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3601 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3602 }; 3603 }; 3604 }; 3605 3606 cpu7-thermal { 3607 polling-delay-passive = <250>; 3608 polling-delay = <1000>; 3609 3610 thermal-sensors = <&tsens0 10>; 3611 3612 trips { 3613 cpu7_alert0: trip-point0 { 3614 temperature = <90000>; 3615 hysteresis = <2000>; 3616 type = "passive"; 3617 }; 3618 3619 cpu7_alert1: trip-point1 { 3620 temperature = <95000>; 3621 hysteresis = <2000>; 3622 type = "passive"; 3623 }; 3624 3625 cpu7_crit: cpu_crit { 3626 temperature = <110000>; 3627 hysteresis = <1000>; 3628 type = "critical"; 3629 }; 3630 }; 3631 3632 cooling-maps { 3633 map0 { 3634 trip = <&cpu7_alert0>; 3635 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3636 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3637 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3638 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3639 }; 3640 map1 { 3641 trip = <&cpu7_alert1>; 3642 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3643 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3644 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3645 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3646 }; 3647 }; 3648 }; 3649 3650 aoss0-thermal { 3651 polling-delay-passive = <250>; 3652 polling-delay = <1000>; 3653 3654 thermal-sensors = <&tsens0 0>; 3655 3656 trips { 3657 aoss0_alert0: trip-point0 { 3658 temperature = <90000>; 3659 hysteresis = <2000>; 3660 type = "hot"; 3661 }; 3662 }; 3663 }; 3664 3665 cluster0-thermal { 3666 polling-delay-passive = <250>; 3667 polling-delay = <1000>; 3668 3669 thermal-sensors = <&tsens0 5>; 3670 3671 trips { 3672 cluster0_alert0: trip-point0 { 3673 temperature = <90000>; 3674 hysteresis = <2000>; 3675 type = "hot"; 3676 }; 3677 cluster0_crit: cluster0_crit { 3678 temperature = <110000>; 3679 hysteresis = <2000>; 3680 type = "critical"; 3681 }; 3682 }; 3683 }; 3684 3685 cluster1-thermal { 3686 polling-delay-passive = <250>; 3687 polling-delay = <1000>; 3688 3689 thermal-sensors = <&tsens0 6>; 3690 3691 trips { 3692 cluster1_alert0: trip-point0 { 3693 temperature = <90000>; 3694 hysteresis = <2000>; 3695 type = "hot"; 3696 }; 3697 cluster1_crit: cluster1_crit { 3698 temperature = <110000>; 3699 hysteresis = <2000>; 3700 type = "critical"; 3701 }; 3702 }; 3703 }; 3704 3705 gpu-thermal-top { 3706 polling-delay-passive = <250>; 3707 polling-delay = <1000>; 3708 3709 thermal-sensors = <&tsens0 11>; 3710 3711 trips { 3712 gpu1_alert0: trip-point0 { 3713 temperature = <90000>; 3714 hysteresis = <2000>; 3715 type = "hot"; 3716 }; 3717 }; 3718 }; 3719 3720 gpu-thermal-bottom { 3721 polling-delay-passive = <250>; 3722 polling-delay = <1000>; 3723 3724 thermal-sensors = <&tsens0 12>; 3725 3726 trips { 3727 gpu2_alert0: trip-point0 { 3728 temperature = <90000>; 3729 hysteresis = <2000>; 3730 type = "hot"; 3731 }; 3732 }; 3733 }; 3734 3735 aoss1-thermal { 3736 polling-delay-passive = <250>; 3737 polling-delay = <1000>; 3738 3739 thermal-sensors = <&tsens1 0>; 3740 3741 trips { 3742 aoss1_alert0: trip-point0 { 3743 temperature = <90000>; 3744 hysteresis = <2000>; 3745 type = "hot"; 3746 }; 3747 }; 3748 }; 3749 3750 q6-modem-thermal { 3751 polling-delay-passive = <250>; 3752 polling-delay = <1000>; 3753 3754 thermal-sensors = <&tsens1 1>; 3755 3756 trips { 3757 q6_modem_alert0: trip-point0 { 3758 temperature = <90000>; 3759 hysteresis = <2000>; 3760 type = "hot"; 3761 }; 3762 }; 3763 }; 3764 3765 mem-thermal { 3766 polling-delay-passive = <250>; 3767 polling-delay = <1000>; 3768 3769 thermal-sensors = <&tsens1 2>; 3770 3771 trips { 3772 mem_alert0: trip-point0 { 3773 temperature = <90000>; 3774 hysteresis = <2000>; 3775 type = "hot"; 3776 }; 3777 }; 3778 }; 3779 3780 wlan-thermal { 3781 polling-delay-passive = <250>; 3782 polling-delay = <1000>; 3783 3784 thermal-sensors = <&tsens1 3>; 3785 3786 trips { 3787 wlan_alert0: trip-point0 { 3788 temperature = <90000>; 3789 hysteresis = <2000>; 3790 type = "hot"; 3791 }; 3792 }; 3793 }; 3794 3795 q6-hvx-thermal { 3796 polling-delay-passive = <250>; 3797 polling-delay = <1000>; 3798 3799 thermal-sensors = <&tsens1 4>; 3800 3801 trips { 3802 q6_hvx_alert0: trip-point0 { 3803 temperature = <90000>; 3804 hysteresis = <2000>; 3805 type = "hot"; 3806 }; 3807 }; 3808 }; 3809 3810 camera-thermal { 3811 polling-delay-passive = <250>; 3812 polling-delay = <1000>; 3813 3814 thermal-sensors = <&tsens1 5>; 3815 3816 trips { 3817 camera_alert0: trip-point0 { 3818 temperature = <90000>; 3819 hysteresis = <2000>; 3820 type = "hot"; 3821 }; 3822 }; 3823 }; 3824 3825 video-thermal { 3826 polling-delay-passive = <250>; 3827 polling-delay = <1000>; 3828 3829 thermal-sensors = <&tsens1 6>; 3830 3831 trips { 3832 video_alert0: trip-point0 { 3833 temperature = <90000>; 3834 hysteresis = <2000>; 3835 type = "hot"; 3836 }; 3837 }; 3838 }; 3839 3840 modem-thermal { 3841 polling-delay-passive = <250>; 3842 polling-delay = <1000>; 3843 3844 thermal-sensors = <&tsens1 7>; 3845 3846 trips { 3847 modem_alert0: trip-point0 { 3848 temperature = <90000>; 3849 hysteresis = <2000>; 3850 type = "hot"; 3851 }; 3852 }; 3853 }; 3854 }; 3855}; 3856