1// SPDX-License-Identifier: GPL-2.0 2/* 3 * SDM845 SoC device tree source 4 * 5 * Copyright (c) 2018, The Linux Foundation. All rights reserved. 6 */ 7 8#include <dt-bindings/clock/qcom,camcc-sdm845.h> 9#include <dt-bindings/clock/qcom,dispcc-sdm845.h> 10#include <dt-bindings/clock/qcom,gcc-sdm845.h> 11#include <dt-bindings/clock/qcom,gpucc-sdm845.h> 12#include <dt-bindings/clock/qcom,lpass-sdm845.h> 13#include <dt-bindings/clock/qcom,rpmh.h> 14#include <dt-bindings/clock/qcom,videocc-sdm845.h> 15#include <dt-bindings/interconnect/qcom,osm-l3.h> 16#include <dt-bindings/interconnect/qcom,sdm845.h> 17#include <dt-bindings/interrupt-controller/arm-gic.h> 18#include <dt-bindings/phy/phy-qcom-qusb2.h> 19#include <dt-bindings/power/qcom-rpmpd.h> 20#include <dt-bindings/reset/qcom,sdm845-aoss.h> 21#include <dt-bindings/reset/qcom,sdm845-pdc.h> 22#include <dt-bindings/soc/qcom,apr.h> 23#include <dt-bindings/soc/qcom,rpmh-rsc.h> 24#include <dt-bindings/clock/qcom,gcc-sdm845.h> 25#include <dt-bindings/thermal/thermal.h> 26 27/ { 28 interrupt-parent = <&intc>; 29 30 #address-cells = <2>; 31 #size-cells = <2>; 32 33 aliases { 34 i2c0 = &i2c0; 35 i2c1 = &i2c1; 36 i2c2 = &i2c2; 37 i2c3 = &i2c3; 38 i2c4 = &i2c4; 39 i2c5 = &i2c5; 40 i2c6 = &i2c6; 41 i2c7 = &i2c7; 42 i2c8 = &i2c8; 43 i2c9 = &i2c9; 44 i2c10 = &i2c10; 45 i2c11 = &i2c11; 46 i2c12 = &i2c12; 47 i2c13 = &i2c13; 48 i2c14 = &i2c14; 49 i2c15 = &i2c15; 50 spi0 = &spi0; 51 spi1 = &spi1; 52 spi2 = &spi2; 53 spi3 = &spi3; 54 spi4 = &spi4; 55 spi5 = &spi5; 56 spi6 = &spi6; 57 spi7 = &spi7; 58 spi8 = &spi8; 59 spi9 = &spi9; 60 spi10 = &spi10; 61 spi11 = &spi11; 62 spi12 = &spi12; 63 spi13 = &spi13; 64 spi14 = &spi14; 65 spi15 = &spi15; 66 }; 67 68 chosen { }; 69 70 memory@80000000 { 71 device_type = "memory"; 72 /* We expect the bootloader to fill in the size */ 73 reg = <0 0x80000000 0 0>; 74 }; 75 76 reserved-memory { 77 #address-cells = <2>; 78 #size-cells = <2>; 79 ranges; 80 81 hyp_mem: memory@85700000 { 82 reg = <0 0x85700000 0 0x600000>; 83 no-map; 84 }; 85 86 xbl_mem: memory@85e00000 { 87 reg = <0 0x85e00000 0 0x100000>; 88 no-map; 89 }; 90 91 aop_mem: memory@85fc0000 { 92 reg = <0 0x85fc0000 0 0x20000>; 93 no-map; 94 }; 95 96 aop_cmd_db_mem: memory@85fe0000 { 97 compatible = "qcom,cmd-db"; 98 reg = <0x0 0x85fe0000 0 0x20000>; 99 no-map; 100 }; 101 102 smem_mem: memory@86000000 { 103 reg = <0x0 0x86000000 0 0x200000>; 104 no-map; 105 }; 106 107 tz_mem: memory@86200000 { 108 reg = <0 0x86200000 0 0x2d00000>; 109 no-map; 110 }; 111 112 rmtfs_mem: memory@88f00000 { 113 compatible = "qcom,rmtfs-mem"; 114 reg = <0 0x88f00000 0 0x200000>; 115 no-map; 116 117 qcom,client-id = <1>; 118 qcom,vmid = <15>; 119 }; 120 121 qseecom_mem: memory@8ab00000 { 122 reg = <0 0x8ab00000 0 0x1400000>; 123 no-map; 124 }; 125 126 camera_mem: memory@8bf00000 { 127 reg = <0 0x8bf00000 0 0x500000>; 128 no-map; 129 }; 130 131 ipa_fw_mem: memory@8c400000 { 132 reg = <0 0x8c400000 0 0x10000>; 133 no-map; 134 }; 135 136 ipa_gsi_mem: memory@8c410000 { 137 reg = <0 0x8c410000 0 0x5000>; 138 no-map; 139 }; 140 141 gpu_mem: memory@8c415000 { 142 reg = <0 0x8c415000 0 0x2000>; 143 no-map; 144 }; 145 146 adsp_mem: memory@8c500000 { 147 reg = <0 0x8c500000 0 0x1a00000>; 148 no-map; 149 }; 150 151 wlan_msa_mem: memory@8df00000 { 152 reg = <0 0x8df00000 0 0x100000>; 153 no-map; 154 }; 155 156 mpss_region: memory@8e000000 { 157 reg = <0 0x8e000000 0 0x7800000>; 158 no-map; 159 }; 160 161 venus_mem: memory@95800000 { 162 reg = <0 0x95800000 0 0x500000>; 163 no-map; 164 }; 165 166 cdsp_mem: memory@95d00000 { 167 reg = <0 0x95d00000 0 0x800000>; 168 no-map; 169 }; 170 171 mba_region: memory@96500000 { 172 reg = <0 0x96500000 0 0x200000>; 173 no-map; 174 }; 175 176 slpi_mem: memory@96700000 { 177 reg = <0 0x96700000 0 0x1400000>; 178 no-map; 179 }; 180 181 spss_mem: memory@97b00000 { 182 reg = <0 0x97b00000 0 0x100000>; 183 no-map; 184 }; 185 }; 186 187 cpus { 188 #address-cells = <2>; 189 #size-cells = <0>; 190 191 CPU0: cpu@0 { 192 device_type = "cpu"; 193 compatible = "qcom,kryo385"; 194 reg = <0x0 0x0>; 195 enable-method = "psci"; 196 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 197 &LITTLE_CPU_SLEEP_1 198 &CLUSTER_SLEEP_0>; 199 capacity-dmips-mhz = <607>; 200 dynamic-power-coefficient = <100>; 201 qcom,freq-domain = <&cpufreq_hw 0>; 202 operating-points-v2 = <&cpu0_opp_table>; 203 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 204 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 205 #cooling-cells = <2>; 206 next-level-cache = <&L2_0>; 207 L2_0: l2-cache { 208 compatible = "cache"; 209 next-level-cache = <&L3_0>; 210 L3_0: l3-cache { 211 compatible = "cache"; 212 }; 213 }; 214 }; 215 216 CPU1: cpu@100 { 217 device_type = "cpu"; 218 compatible = "qcom,kryo385"; 219 reg = <0x0 0x100>; 220 enable-method = "psci"; 221 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 222 &LITTLE_CPU_SLEEP_1 223 &CLUSTER_SLEEP_0>; 224 capacity-dmips-mhz = <607>; 225 dynamic-power-coefficient = <100>; 226 qcom,freq-domain = <&cpufreq_hw 0>; 227 operating-points-v2 = <&cpu0_opp_table>; 228 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 229 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 230 #cooling-cells = <2>; 231 next-level-cache = <&L2_100>; 232 L2_100: l2-cache { 233 compatible = "cache"; 234 next-level-cache = <&L3_0>; 235 }; 236 }; 237 238 CPU2: cpu@200 { 239 device_type = "cpu"; 240 compatible = "qcom,kryo385"; 241 reg = <0x0 0x200>; 242 enable-method = "psci"; 243 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 244 &LITTLE_CPU_SLEEP_1 245 &CLUSTER_SLEEP_0>; 246 capacity-dmips-mhz = <607>; 247 dynamic-power-coefficient = <100>; 248 qcom,freq-domain = <&cpufreq_hw 0>; 249 operating-points-v2 = <&cpu0_opp_table>; 250 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 251 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 252 #cooling-cells = <2>; 253 next-level-cache = <&L2_200>; 254 L2_200: l2-cache { 255 compatible = "cache"; 256 next-level-cache = <&L3_0>; 257 }; 258 }; 259 260 CPU3: cpu@300 { 261 device_type = "cpu"; 262 compatible = "qcom,kryo385"; 263 reg = <0x0 0x300>; 264 enable-method = "psci"; 265 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 266 &LITTLE_CPU_SLEEP_1 267 &CLUSTER_SLEEP_0>; 268 capacity-dmips-mhz = <607>; 269 dynamic-power-coefficient = <100>; 270 qcom,freq-domain = <&cpufreq_hw 0>; 271 operating-points-v2 = <&cpu0_opp_table>; 272 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 273 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 274 #cooling-cells = <2>; 275 next-level-cache = <&L2_300>; 276 L2_300: l2-cache { 277 compatible = "cache"; 278 next-level-cache = <&L3_0>; 279 }; 280 }; 281 282 CPU4: cpu@400 { 283 device_type = "cpu"; 284 compatible = "qcom,kryo385"; 285 reg = <0x0 0x400>; 286 enable-method = "psci"; 287 capacity-dmips-mhz = <1024>; 288 cpu-idle-states = <&BIG_CPU_SLEEP_0 289 &BIG_CPU_SLEEP_1 290 &CLUSTER_SLEEP_0>; 291 dynamic-power-coefficient = <396>; 292 qcom,freq-domain = <&cpufreq_hw 1>; 293 operating-points-v2 = <&cpu4_opp_table>; 294 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 295 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 296 #cooling-cells = <2>; 297 next-level-cache = <&L2_400>; 298 L2_400: l2-cache { 299 compatible = "cache"; 300 next-level-cache = <&L3_0>; 301 }; 302 }; 303 304 CPU5: cpu@500 { 305 device_type = "cpu"; 306 compatible = "qcom,kryo385"; 307 reg = <0x0 0x500>; 308 enable-method = "psci"; 309 capacity-dmips-mhz = <1024>; 310 cpu-idle-states = <&BIG_CPU_SLEEP_0 311 &BIG_CPU_SLEEP_1 312 &CLUSTER_SLEEP_0>; 313 dynamic-power-coefficient = <396>; 314 qcom,freq-domain = <&cpufreq_hw 1>; 315 operating-points-v2 = <&cpu4_opp_table>; 316 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 317 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 318 #cooling-cells = <2>; 319 next-level-cache = <&L2_500>; 320 L2_500: l2-cache { 321 compatible = "cache"; 322 next-level-cache = <&L3_0>; 323 }; 324 }; 325 326 CPU6: cpu@600 { 327 device_type = "cpu"; 328 compatible = "qcom,kryo385"; 329 reg = <0x0 0x600>; 330 enable-method = "psci"; 331 capacity-dmips-mhz = <1024>; 332 cpu-idle-states = <&BIG_CPU_SLEEP_0 333 &BIG_CPU_SLEEP_1 334 &CLUSTER_SLEEP_0>; 335 dynamic-power-coefficient = <396>; 336 qcom,freq-domain = <&cpufreq_hw 1>; 337 operating-points-v2 = <&cpu4_opp_table>; 338 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 339 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 340 #cooling-cells = <2>; 341 next-level-cache = <&L2_600>; 342 L2_600: l2-cache { 343 compatible = "cache"; 344 next-level-cache = <&L3_0>; 345 }; 346 }; 347 348 CPU7: cpu@700 { 349 device_type = "cpu"; 350 compatible = "qcom,kryo385"; 351 reg = <0x0 0x700>; 352 enable-method = "psci"; 353 capacity-dmips-mhz = <1024>; 354 cpu-idle-states = <&BIG_CPU_SLEEP_0 355 &BIG_CPU_SLEEP_1 356 &CLUSTER_SLEEP_0>; 357 dynamic-power-coefficient = <396>; 358 qcom,freq-domain = <&cpufreq_hw 1>; 359 operating-points-v2 = <&cpu4_opp_table>; 360 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 361 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 362 #cooling-cells = <2>; 363 next-level-cache = <&L2_700>; 364 L2_700: l2-cache { 365 compatible = "cache"; 366 next-level-cache = <&L3_0>; 367 }; 368 }; 369 370 cpu-map { 371 cluster0 { 372 core0 { 373 cpu = <&CPU0>; 374 }; 375 376 core1 { 377 cpu = <&CPU1>; 378 }; 379 380 core2 { 381 cpu = <&CPU2>; 382 }; 383 384 core3 { 385 cpu = <&CPU3>; 386 }; 387 388 core4 { 389 cpu = <&CPU4>; 390 }; 391 392 core5 { 393 cpu = <&CPU5>; 394 }; 395 396 core6 { 397 cpu = <&CPU6>; 398 }; 399 400 core7 { 401 cpu = <&CPU7>; 402 }; 403 }; 404 }; 405 406 idle-states { 407 entry-method = "psci"; 408 409 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 410 compatible = "arm,idle-state"; 411 idle-state-name = "little-power-down"; 412 arm,psci-suspend-param = <0x40000003>; 413 entry-latency-us = <350>; 414 exit-latency-us = <461>; 415 min-residency-us = <1890>; 416 local-timer-stop; 417 }; 418 419 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 420 compatible = "arm,idle-state"; 421 idle-state-name = "little-rail-power-down"; 422 arm,psci-suspend-param = <0x40000004>; 423 entry-latency-us = <360>; 424 exit-latency-us = <531>; 425 min-residency-us = <3934>; 426 local-timer-stop; 427 }; 428 429 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 430 compatible = "arm,idle-state"; 431 idle-state-name = "big-power-down"; 432 arm,psci-suspend-param = <0x40000003>; 433 entry-latency-us = <264>; 434 exit-latency-us = <621>; 435 min-residency-us = <952>; 436 local-timer-stop; 437 }; 438 439 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 440 compatible = "arm,idle-state"; 441 idle-state-name = "big-rail-power-down"; 442 arm,psci-suspend-param = <0x40000004>; 443 entry-latency-us = <702>; 444 exit-latency-us = <1061>; 445 min-residency-us = <4488>; 446 local-timer-stop; 447 }; 448 449 CLUSTER_SLEEP_0: cluster-sleep-0 { 450 compatible = "arm,idle-state"; 451 idle-state-name = "cluster-power-down"; 452 arm,psci-suspend-param = <0x400000F4>; 453 entry-latency-us = <3263>; 454 exit-latency-us = <6562>; 455 min-residency-us = <9987>; 456 local-timer-stop; 457 }; 458 }; 459 }; 460 461 cpu0_opp_table: cpu0_opp_table { 462 compatible = "operating-points-v2"; 463 opp-shared; 464 465 cpu0_opp1: opp-300000000 { 466 opp-hz = /bits/ 64 <300000000>; 467 opp-peak-kBps = <800000 4800000>; 468 }; 469 470 cpu0_opp2: opp-403200000 { 471 opp-hz = /bits/ 64 <403200000>; 472 opp-peak-kBps = <800000 4800000>; 473 }; 474 475 cpu0_opp3: opp-480000000 { 476 opp-hz = /bits/ 64 <480000000>; 477 opp-peak-kBps = <800000 6451200>; 478 }; 479 480 cpu0_opp4: opp-576000000 { 481 opp-hz = /bits/ 64 <576000000>; 482 opp-peak-kBps = <800000 6451200>; 483 }; 484 485 cpu0_opp5: opp-652800000 { 486 opp-hz = /bits/ 64 <652800000>; 487 opp-peak-kBps = <800000 7680000>; 488 }; 489 490 cpu0_opp6: opp-748800000 { 491 opp-hz = /bits/ 64 <748800000>; 492 opp-peak-kBps = <1804000 9216000>; 493 }; 494 495 cpu0_opp7: opp-825600000 { 496 opp-hz = /bits/ 64 <825600000>; 497 opp-peak-kBps = <1804000 9216000>; 498 }; 499 500 cpu0_opp8: opp-902400000 { 501 opp-hz = /bits/ 64 <902400000>; 502 opp-peak-kBps = <1804000 10444800>; 503 }; 504 505 cpu0_opp9: opp-979200000 { 506 opp-hz = /bits/ 64 <979200000>; 507 opp-peak-kBps = <1804000 11980800>; 508 }; 509 510 cpu0_opp10: opp-1056000000 { 511 opp-hz = /bits/ 64 <1056000000>; 512 opp-peak-kBps = <1804000 11980800>; 513 }; 514 515 cpu0_opp11: opp-1132800000 { 516 opp-hz = /bits/ 64 <1132800000>; 517 opp-peak-kBps = <2188000 13516800>; 518 }; 519 520 cpu0_opp12: opp-1228800000 { 521 opp-hz = /bits/ 64 <1228800000>; 522 opp-peak-kBps = <2188000 15052800>; 523 }; 524 525 cpu0_opp13: opp-1324800000 { 526 opp-hz = /bits/ 64 <1324800000>; 527 opp-peak-kBps = <2188000 16588800>; 528 }; 529 530 cpu0_opp14: opp-1420800000 { 531 opp-hz = /bits/ 64 <1420800000>; 532 opp-peak-kBps = <3072000 18124800>; 533 }; 534 535 cpu0_opp15: opp-1516800000 { 536 opp-hz = /bits/ 64 <1516800000>; 537 opp-peak-kBps = <3072000 19353600>; 538 }; 539 540 cpu0_opp16: opp-1612800000 { 541 opp-hz = /bits/ 64 <1612800000>; 542 opp-peak-kBps = <4068000 19353600>; 543 }; 544 545 cpu0_opp17: opp-1689600000 { 546 opp-hz = /bits/ 64 <1689600000>; 547 opp-peak-kBps = <4068000 20889600>; 548 }; 549 550 cpu0_opp18: opp-1766400000 { 551 opp-hz = /bits/ 64 <1766400000>; 552 opp-peak-kBps = <4068000 22425600>; 553 }; 554 }; 555 556 cpu4_opp_table: cpu4_opp_table { 557 compatible = "operating-points-v2"; 558 opp-shared; 559 560 cpu4_opp1: opp-300000000 { 561 opp-hz = /bits/ 64 <300000000>; 562 opp-peak-kBps = <800000 4800000>; 563 }; 564 565 cpu4_opp2: opp-403200000 { 566 opp-hz = /bits/ 64 <403200000>; 567 opp-peak-kBps = <800000 4800000>; 568 }; 569 570 cpu4_opp3: opp-480000000 { 571 opp-hz = /bits/ 64 <480000000>; 572 opp-peak-kBps = <1804000 4800000>; 573 }; 574 575 cpu4_opp4: opp-576000000 { 576 opp-hz = /bits/ 64 <576000000>; 577 opp-peak-kBps = <1804000 4800000>; 578 }; 579 580 cpu4_opp5: opp-652800000 { 581 opp-hz = /bits/ 64 <652800000>; 582 opp-peak-kBps = <1804000 4800000>; 583 }; 584 585 cpu4_opp6: opp-748800000 { 586 opp-hz = /bits/ 64 <748800000>; 587 opp-peak-kBps = <1804000 4800000>; 588 }; 589 590 cpu4_opp7: opp-825600000 { 591 opp-hz = /bits/ 64 <825600000>; 592 opp-peak-kBps = <2188000 9216000>; 593 }; 594 595 cpu4_opp8: opp-902400000 { 596 opp-hz = /bits/ 64 <902400000>; 597 opp-peak-kBps = <2188000 9216000>; 598 }; 599 600 cpu4_opp9: opp-979200000 { 601 opp-hz = /bits/ 64 <979200000>; 602 opp-peak-kBps = <2188000 9216000>; 603 }; 604 605 cpu4_opp10: opp-1056000000 { 606 opp-hz = /bits/ 64 <1056000000>; 607 opp-peak-kBps = <3072000 9216000>; 608 }; 609 610 cpu4_opp11: opp-1132800000 { 611 opp-hz = /bits/ 64 <1132800000>; 612 opp-peak-kBps = <3072000 11980800>; 613 }; 614 615 cpu4_opp12: opp-1209600000 { 616 opp-hz = /bits/ 64 <1209600000>; 617 opp-peak-kBps = <4068000 11980800>; 618 }; 619 620 cpu4_opp13: opp-1286400000 { 621 opp-hz = /bits/ 64 <1286400000>; 622 opp-peak-kBps = <4068000 11980800>; 623 }; 624 625 cpu4_opp14: opp-1363200000 { 626 opp-hz = /bits/ 64 <1363200000>; 627 opp-peak-kBps = <4068000 15052800>; 628 }; 629 630 cpu4_opp15: opp-1459200000 { 631 opp-hz = /bits/ 64 <1459200000>; 632 opp-peak-kBps = <4068000 15052800>; 633 }; 634 635 cpu4_opp16: opp-1536000000 { 636 opp-hz = /bits/ 64 <1536000000>; 637 opp-peak-kBps = <5412000 15052800>; 638 }; 639 640 cpu4_opp17: opp-1612800000 { 641 opp-hz = /bits/ 64 <1612800000>; 642 opp-peak-kBps = <5412000 15052800>; 643 }; 644 645 cpu4_opp18: opp-1689600000 { 646 opp-hz = /bits/ 64 <1689600000>; 647 opp-peak-kBps = <5412000 19353600>; 648 }; 649 650 cpu4_opp19: opp-1766400000 { 651 opp-hz = /bits/ 64 <1766400000>; 652 opp-peak-kBps = <6220000 19353600>; 653 }; 654 655 cpu4_opp20: opp-1843200000 { 656 opp-hz = /bits/ 64 <1843200000>; 657 opp-peak-kBps = <6220000 19353600>; 658 }; 659 660 cpu4_opp21: opp-1920000000 { 661 opp-hz = /bits/ 64 <1920000000>; 662 opp-peak-kBps = <7216000 19353600>; 663 }; 664 665 cpu4_opp22: opp-1996800000 { 666 opp-hz = /bits/ 64 <1996800000>; 667 opp-peak-kBps = <7216000 20889600>; 668 }; 669 670 cpu4_opp23: opp-2092800000 { 671 opp-hz = /bits/ 64 <2092800000>; 672 opp-peak-kBps = <7216000 20889600>; 673 }; 674 675 cpu4_opp24: opp-2169600000 { 676 opp-hz = /bits/ 64 <2169600000>; 677 opp-peak-kBps = <7216000 20889600>; 678 }; 679 680 cpu4_opp25: opp-2246400000 { 681 opp-hz = /bits/ 64 <2246400000>; 682 opp-peak-kBps = <7216000 20889600>; 683 }; 684 685 cpu4_opp26: opp-2323200000 { 686 opp-hz = /bits/ 64 <2323200000>; 687 opp-peak-kBps = <7216000 20889600>; 688 }; 689 690 cpu4_opp27: opp-2400000000 { 691 opp-hz = /bits/ 64 <2400000000>; 692 opp-peak-kBps = <7216000 22425600>; 693 }; 694 695 cpu4_opp28: opp-2476800000 { 696 opp-hz = /bits/ 64 <2476800000>; 697 opp-peak-kBps = <7216000 22425600>; 698 }; 699 700 cpu4_opp29: opp-2553600000 { 701 opp-hz = /bits/ 64 <2553600000>; 702 opp-peak-kBps = <7216000 22425600>; 703 }; 704 705 cpu4_opp30: opp-2649600000 { 706 opp-hz = /bits/ 64 <2649600000>; 707 opp-peak-kBps = <7216000 22425600>; 708 }; 709 710 cpu4_opp31: opp-2745600000 { 711 opp-hz = /bits/ 64 <2745600000>; 712 opp-peak-kBps = <7216000 25497600>; 713 }; 714 715 cpu4_opp32: opp-2803200000 { 716 opp-hz = /bits/ 64 <2803200000>; 717 opp-peak-kBps = <7216000 25497600>; 718 }; 719 }; 720 721 pmu { 722 compatible = "arm,armv8-pmuv3"; 723 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; 724 }; 725 726 timer { 727 compatible = "arm,armv8-timer"; 728 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 729 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 730 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 731 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 732 }; 733 734 clocks { 735 xo_board: xo-board { 736 compatible = "fixed-clock"; 737 #clock-cells = <0>; 738 clock-frequency = <38400000>; 739 clock-output-names = "xo_board"; 740 }; 741 742 sleep_clk: sleep-clk { 743 compatible = "fixed-clock"; 744 #clock-cells = <0>; 745 clock-frequency = <32764>; 746 }; 747 }; 748 749 firmware { 750 scm { 751 compatible = "qcom,scm-sdm845", "qcom,scm"; 752 }; 753 }; 754 755 adsp_pas: remoteproc-adsp { 756 compatible = "qcom,sdm845-adsp-pas"; 757 758 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 759 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 760 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 761 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 762 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 763 interrupt-names = "wdog", "fatal", "ready", 764 "handover", "stop-ack"; 765 766 clocks = <&rpmhcc RPMH_CXO_CLK>; 767 clock-names = "xo"; 768 769 memory-region = <&adsp_mem>; 770 771 qcom,smem-states = <&adsp_smp2p_out 0>; 772 qcom,smem-state-names = "stop"; 773 774 status = "disabled"; 775 776 glink-edge { 777 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 778 label = "lpass"; 779 qcom,remote-pid = <2>; 780 mboxes = <&apss_shared 8>; 781 782 apr { 783 compatible = "qcom,apr-v2"; 784 qcom,glink-channels = "apr_audio_svc"; 785 qcom,apr-domain = <APR_DOMAIN_ADSP>; 786 #address-cells = <1>; 787 #size-cells = <0>; 788 qcom,intents = <512 20>; 789 790 apr-service@3 { 791 reg = <APR_SVC_ADSP_CORE>; 792 compatible = "qcom,q6core"; 793 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 794 }; 795 796 q6afe: apr-service@4 { 797 compatible = "qcom,q6afe"; 798 reg = <APR_SVC_AFE>; 799 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 800 q6afedai: dais { 801 compatible = "qcom,q6afe-dais"; 802 #address-cells = <1>; 803 #size-cells = <0>; 804 #sound-dai-cells = <1>; 805 }; 806 }; 807 808 q6asm: apr-service@7 { 809 compatible = "qcom,q6asm"; 810 reg = <APR_SVC_ASM>; 811 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 812 q6asmdai: dais { 813 compatible = "qcom,q6asm-dais"; 814 #address-cells = <1>; 815 #size-cells = <0>; 816 #sound-dai-cells = <1>; 817 iommus = <&apps_smmu 0x1821 0x0>; 818 }; 819 }; 820 821 q6adm: apr-service@8 { 822 compatible = "qcom,q6adm"; 823 reg = <APR_SVC_ADM>; 824 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 825 q6routing: routing { 826 compatible = "qcom,q6adm-routing"; 827 #sound-dai-cells = <0>; 828 }; 829 }; 830 }; 831 832 fastrpc { 833 compatible = "qcom,fastrpc"; 834 qcom,glink-channels = "fastrpcglink-apps-dsp"; 835 label = "adsp"; 836 #address-cells = <1>; 837 #size-cells = <0>; 838 839 compute-cb@3 { 840 compatible = "qcom,fastrpc-compute-cb"; 841 reg = <3>; 842 iommus = <&apps_smmu 0x1823 0x0>; 843 }; 844 845 compute-cb@4 { 846 compatible = "qcom,fastrpc-compute-cb"; 847 reg = <4>; 848 iommus = <&apps_smmu 0x1824 0x0>; 849 }; 850 }; 851 }; 852 }; 853 854 cdsp_pas: remoteproc-cdsp { 855 compatible = "qcom,sdm845-cdsp-pas"; 856 857 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 858 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 859 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 860 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 861 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 862 interrupt-names = "wdog", "fatal", "ready", 863 "handover", "stop-ack"; 864 865 clocks = <&rpmhcc RPMH_CXO_CLK>; 866 clock-names = "xo"; 867 868 memory-region = <&cdsp_mem>; 869 870 qcom,smem-states = <&cdsp_smp2p_out 0>; 871 qcom,smem-state-names = "stop"; 872 873 status = "disabled"; 874 875 glink-edge { 876 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>; 877 label = "turing"; 878 qcom,remote-pid = <5>; 879 mboxes = <&apss_shared 4>; 880 fastrpc { 881 compatible = "qcom,fastrpc"; 882 qcom,glink-channels = "fastrpcglink-apps-dsp"; 883 label = "cdsp"; 884 #address-cells = <1>; 885 #size-cells = <0>; 886 887 compute-cb@1 { 888 compatible = "qcom,fastrpc-compute-cb"; 889 reg = <1>; 890 iommus = <&apps_smmu 0x1401 0x30>; 891 }; 892 893 compute-cb@2 { 894 compatible = "qcom,fastrpc-compute-cb"; 895 reg = <2>; 896 iommus = <&apps_smmu 0x1402 0x30>; 897 }; 898 899 compute-cb@3 { 900 compatible = "qcom,fastrpc-compute-cb"; 901 reg = <3>; 902 iommus = <&apps_smmu 0x1403 0x30>; 903 }; 904 905 compute-cb@4 { 906 compatible = "qcom,fastrpc-compute-cb"; 907 reg = <4>; 908 iommus = <&apps_smmu 0x1404 0x30>; 909 }; 910 911 compute-cb@5 { 912 compatible = "qcom,fastrpc-compute-cb"; 913 reg = <5>; 914 iommus = <&apps_smmu 0x1405 0x30>; 915 }; 916 917 compute-cb@6 { 918 compatible = "qcom,fastrpc-compute-cb"; 919 reg = <6>; 920 iommus = <&apps_smmu 0x1406 0x30>; 921 }; 922 923 compute-cb@7 { 924 compatible = "qcom,fastrpc-compute-cb"; 925 reg = <7>; 926 iommus = <&apps_smmu 0x1407 0x30>; 927 }; 928 929 compute-cb@8 { 930 compatible = "qcom,fastrpc-compute-cb"; 931 reg = <8>; 932 iommus = <&apps_smmu 0x1408 0x30>; 933 }; 934 }; 935 }; 936 }; 937 938 tcsr_mutex: hwlock { 939 compatible = "qcom,tcsr-mutex"; 940 syscon = <&tcsr_mutex_regs 0 0x1000>; 941 #hwlock-cells = <1>; 942 }; 943 944 smem { 945 compatible = "qcom,smem"; 946 memory-region = <&smem_mem>; 947 hwlocks = <&tcsr_mutex 3>; 948 }; 949 950 smp2p-cdsp { 951 compatible = "qcom,smp2p"; 952 qcom,smem = <94>, <432>; 953 954 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; 955 956 mboxes = <&apss_shared 6>; 957 958 qcom,local-pid = <0>; 959 qcom,remote-pid = <5>; 960 961 cdsp_smp2p_out: master-kernel { 962 qcom,entry-name = "master-kernel"; 963 #qcom,smem-state-cells = <1>; 964 }; 965 966 cdsp_smp2p_in: slave-kernel { 967 qcom,entry-name = "slave-kernel"; 968 969 interrupt-controller; 970 #interrupt-cells = <2>; 971 }; 972 }; 973 974 smp2p-lpass { 975 compatible = "qcom,smp2p"; 976 qcom,smem = <443>, <429>; 977 978 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 979 980 mboxes = <&apss_shared 10>; 981 982 qcom,local-pid = <0>; 983 qcom,remote-pid = <2>; 984 985 adsp_smp2p_out: master-kernel { 986 qcom,entry-name = "master-kernel"; 987 #qcom,smem-state-cells = <1>; 988 }; 989 990 adsp_smp2p_in: slave-kernel { 991 qcom,entry-name = "slave-kernel"; 992 993 interrupt-controller; 994 #interrupt-cells = <2>; 995 }; 996 }; 997 998 smp2p-mpss { 999 compatible = "qcom,smp2p"; 1000 qcom,smem = <435>, <428>; 1001 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 1002 mboxes = <&apss_shared 14>; 1003 qcom,local-pid = <0>; 1004 qcom,remote-pid = <1>; 1005 1006 modem_smp2p_out: master-kernel { 1007 qcom,entry-name = "master-kernel"; 1008 #qcom,smem-state-cells = <1>; 1009 }; 1010 1011 modem_smp2p_in: slave-kernel { 1012 qcom,entry-name = "slave-kernel"; 1013 interrupt-controller; 1014 #interrupt-cells = <2>; 1015 }; 1016 1017 ipa_smp2p_out: ipa-ap-to-modem { 1018 qcom,entry-name = "ipa"; 1019 #qcom,smem-state-cells = <1>; 1020 }; 1021 1022 ipa_smp2p_in: ipa-modem-to-ap { 1023 qcom,entry-name = "ipa"; 1024 interrupt-controller; 1025 #interrupt-cells = <2>; 1026 }; 1027 }; 1028 1029 smp2p-slpi { 1030 compatible = "qcom,smp2p"; 1031 qcom,smem = <481>, <430>; 1032 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>; 1033 mboxes = <&apss_shared 26>; 1034 qcom,local-pid = <0>; 1035 qcom,remote-pid = <3>; 1036 1037 slpi_smp2p_out: master-kernel { 1038 qcom,entry-name = "master-kernel"; 1039 #qcom,smem-state-cells = <1>; 1040 }; 1041 1042 slpi_smp2p_in: slave-kernel { 1043 qcom,entry-name = "slave-kernel"; 1044 interrupt-controller; 1045 #interrupt-cells = <2>; 1046 }; 1047 }; 1048 1049 psci { 1050 compatible = "arm,psci-1.0"; 1051 method = "smc"; 1052 }; 1053 1054 soc: soc@0 { 1055 #address-cells = <2>; 1056 #size-cells = <2>; 1057 ranges = <0 0 0 0 0x10 0>; 1058 dma-ranges = <0 0 0 0 0x10 0>; 1059 compatible = "simple-bus"; 1060 1061 gcc: clock-controller@100000 { 1062 compatible = "qcom,gcc-sdm845"; 1063 reg = <0 0x00100000 0 0x1f0000>; 1064 #clock-cells = <1>; 1065 #reset-cells = <1>; 1066 #power-domain-cells = <1>; 1067 }; 1068 1069 qfprom@784000 { 1070 compatible = "qcom,qfprom"; 1071 reg = <0 0x00784000 0 0x8ff>; 1072 #address-cells = <1>; 1073 #size-cells = <1>; 1074 1075 qusb2p_hstx_trim: hstx-trim-primary@1eb { 1076 reg = <0x1eb 0x1>; 1077 bits = <1 4>; 1078 }; 1079 1080 qusb2s_hstx_trim: hstx-trim-secondary@1eb { 1081 reg = <0x1eb 0x2>; 1082 bits = <6 4>; 1083 }; 1084 }; 1085 1086 rng: rng@793000 { 1087 compatible = "qcom,prng-ee"; 1088 reg = <0 0x00793000 0 0x1000>; 1089 clocks = <&gcc GCC_PRNG_AHB_CLK>; 1090 clock-names = "core"; 1091 }; 1092 1093 qup_opp_table: qup-opp-table { 1094 compatible = "operating-points-v2"; 1095 1096 opp-19200000 { 1097 opp-hz = /bits/ 64 <19200000>; 1098 required-opps = <&rpmhpd_opp_min_svs>; 1099 }; 1100 1101 opp-75000000 { 1102 opp-hz = /bits/ 64 <75000000>; 1103 required-opps = <&rpmhpd_opp_low_svs>; 1104 }; 1105 1106 opp-100000000 { 1107 opp-hz = /bits/ 64 <100000000>; 1108 required-opps = <&rpmhpd_opp_svs>; 1109 }; 1110 }; 1111 1112 qupv3_id_0: geniqup@8c0000 { 1113 compatible = "qcom,geni-se-qup"; 1114 reg = <0 0x008c0000 0 0x6000>; 1115 clock-names = "m-ahb", "s-ahb"; 1116 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1117 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1118 #address-cells = <2>; 1119 #size-cells = <2>; 1120 ranges; 1121 status = "disabled"; 1122 1123 i2c0: i2c@880000 { 1124 compatible = "qcom,geni-i2c"; 1125 reg = <0 0x00880000 0 0x4000>; 1126 clock-names = "se"; 1127 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1128 pinctrl-names = "default"; 1129 pinctrl-0 = <&qup_i2c0_default>; 1130 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1131 #address-cells = <1>; 1132 #size-cells = <0>; 1133 power-domains = <&rpmhpd SDM845_CX>; 1134 operating-points-v2 = <&qup_opp_table>; 1135 status = "disabled"; 1136 }; 1137 1138 spi0: spi@880000 { 1139 compatible = "qcom,geni-spi"; 1140 reg = <0 0x00880000 0 0x4000>; 1141 clock-names = "se"; 1142 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1143 pinctrl-names = "default"; 1144 pinctrl-0 = <&qup_spi0_default>; 1145 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1146 #address-cells = <1>; 1147 #size-cells = <0>; 1148 status = "disabled"; 1149 }; 1150 1151 uart0: serial@880000 { 1152 compatible = "qcom,geni-uart"; 1153 reg = <0 0x00880000 0 0x4000>; 1154 clock-names = "se"; 1155 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1156 pinctrl-names = "default"; 1157 pinctrl-0 = <&qup_uart0_default>; 1158 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1159 power-domains = <&rpmhpd SDM845_CX>; 1160 operating-points-v2 = <&qup_opp_table>; 1161 status = "disabled"; 1162 }; 1163 1164 i2c1: i2c@884000 { 1165 compatible = "qcom,geni-i2c"; 1166 reg = <0 0x00884000 0 0x4000>; 1167 clock-names = "se"; 1168 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1169 pinctrl-names = "default"; 1170 pinctrl-0 = <&qup_i2c1_default>; 1171 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1172 #address-cells = <1>; 1173 #size-cells = <0>; 1174 power-domains = <&rpmhpd SDM845_CX>; 1175 operating-points-v2 = <&qup_opp_table>; 1176 status = "disabled"; 1177 }; 1178 1179 spi1: spi@884000 { 1180 compatible = "qcom,geni-spi"; 1181 reg = <0 0x00884000 0 0x4000>; 1182 clock-names = "se"; 1183 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1184 pinctrl-names = "default"; 1185 pinctrl-0 = <&qup_spi1_default>; 1186 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1187 #address-cells = <1>; 1188 #size-cells = <0>; 1189 status = "disabled"; 1190 }; 1191 1192 uart1: serial@884000 { 1193 compatible = "qcom,geni-uart"; 1194 reg = <0 0x00884000 0 0x4000>; 1195 clock-names = "se"; 1196 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1197 pinctrl-names = "default"; 1198 pinctrl-0 = <&qup_uart1_default>; 1199 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1200 power-domains = <&rpmhpd SDM845_CX>; 1201 operating-points-v2 = <&qup_opp_table>; 1202 status = "disabled"; 1203 }; 1204 1205 i2c2: i2c@888000 { 1206 compatible = "qcom,geni-i2c"; 1207 reg = <0 0x00888000 0 0x4000>; 1208 clock-names = "se"; 1209 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1210 pinctrl-names = "default"; 1211 pinctrl-0 = <&qup_i2c2_default>; 1212 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1213 #address-cells = <1>; 1214 #size-cells = <0>; 1215 power-domains = <&rpmhpd SDM845_CX>; 1216 operating-points-v2 = <&qup_opp_table>; 1217 status = "disabled"; 1218 }; 1219 1220 spi2: spi@888000 { 1221 compatible = "qcom,geni-spi"; 1222 reg = <0 0x00888000 0 0x4000>; 1223 clock-names = "se"; 1224 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1225 pinctrl-names = "default"; 1226 pinctrl-0 = <&qup_spi2_default>; 1227 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1228 #address-cells = <1>; 1229 #size-cells = <0>; 1230 status = "disabled"; 1231 }; 1232 1233 uart2: serial@888000 { 1234 compatible = "qcom,geni-uart"; 1235 reg = <0 0x00888000 0 0x4000>; 1236 clock-names = "se"; 1237 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1238 pinctrl-names = "default"; 1239 pinctrl-0 = <&qup_uart2_default>; 1240 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1241 power-domains = <&rpmhpd SDM845_CX>; 1242 operating-points-v2 = <&qup_opp_table>; 1243 status = "disabled"; 1244 }; 1245 1246 i2c3: i2c@88c000 { 1247 compatible = "qcom,geni-i2c"; 1248 reg = <0 0x0088c000 0 0x4000>; 1249 clock-names = "se"; 1250 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1251 pinctrl-names = "default"; 1252 pinctrl-0 = <&qup_i2c3_default>; 1253 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1254 #address-cells = <1>; 1255 #size-cells = <0>; 1256 power-domains = <&rpmhpd SDM845_CX>; 1257 operating-points-v2 = <&qup_opp_table>; 1258 status = "disabled"; 1259 }; 1260 1261 spi3: spi@88c000 { 1262 compatible = "qcom,geni-spi"; 1263 reg = <0 0x0088c000 0 0x4000>; 1264 clock-names = "se"; 1265 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1266 pinctrl-names = "default"; 1267 pinctrl-0 = <&qup_spi3_default>; 1268 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1269 #address-cells = <1>; 1270 #size-cells = <0>; 1271 status = "disabled"; 1272 }; 1273 1274 uart3: serial@88c000 { 1275 compatible = "qcom,geni-uart"; 1276 reg = <0 0x0088c000 0 0x4000>; 1277 clock-names = "se"; 1278 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1279 pinctrl-names = "default"; 1280 pinctrl-0 = <&qup_uart3_default>; 1281 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1282 power-domains = <&rpmhpd SDM845_CX>; 1283 operating-points-v2 = <&qup_opp_table>; 1284 status = "disabled"; 1285 }; 1286 1287 i2c4: i2c@890000 { 1288 compatible = "qcom,geni-i2c"; 1289 reg = <0 0x00890000 0 0x4000>; 1290 clock-names = "se"; 1291 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1292 pinctrl-names = "default"; 1293 pinctrl-0 = <&qup_i2c4_default>; 1294 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1295 #address-cells = <1>; 1296 #size-cells = <0>; 1297 power-domains = <&rpmhpd SDM845_CX>; 1298 operating-points-v2 = <&qup_opp_table>; 1299 status = "disabled"; 1300 }; 1301 1302 spi4: spi@890000 { 1303 compatible = "qcom,geni-spi"; 1304 reg = <0 0x00890000 0 0x4000>; 1305 clock-names = "se"; 1306 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1307 pinctrl-names = "default"; 1308 pinctrl-0 = <&qup_spi4_default>; 1309 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1310 #address-cells = <1>; 1311 #size-cells = <0>; 1312 status = "disabled"; 1313 }; 1314 1315 uart4: serial@890000 { 1316 compatible = "qcom,geni-uart"; 1317 reg = <0 0x00890000 0 0x4000>; 1318 clock-names = "se"; 1319 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1320 pinctrl-names = "default"; 1321 pinctrl-0 = <&qup_uart4_default>; 1322 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1323 power-domains = <&rpmhpd SDM845_CX>; 1324 operating-points-v2 = <&qup_opp_table>; 1325 status = "disabled"; 1326 }; 1327 1328 i2c5: i2c@894000 { 1329 compatible = "qcom,geni-i2c"; 1330 reg = <0 0x00894000 0 0x4000>; 1331 clock-names = "se"; 1332 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1333 pinctrl-names = "default"; 1334 pinctrl-0 = <&qup_i2c5_default>; 1335 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1336 #address-cells = <1>; 1337 #size-cells = <0>; 1338 power-domains = <&rpmhpd SDM845_CX>; 1339 operating-points-v2 = <&qup_opp_table>; 1340 status = "disabled"; 1341 }; 1342 1343 spi5: spi@894000 { 1344 compatible = "qcom,geni-spi"; 1345 reg = <0 0x00894000 0 0x4000>; 1346 clock-names = "se"; 1347 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1348 pinctrl-names = "default"; 1349 pinctrl-0 = <&qup_spi5_default>; 1350 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1351 #address-cells = <1>; 1352 #size-cells = <0>; 1353 status = "disabled"; 1354 }; 1355 1356 uart5: serial@894000 { 1357 compatible = "qcom,geni-uart"; 1358 reg = <0 0x00894000 0 0x4000>; 1359 clock-names = "se"; 1360 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1361 pinctrl-names = "default"; 1362 pinctrl-0 = <&qup_uart5_default>; 1363 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1364 power-domains = <&rpmhpd SDM845_CX>; 1365 operating-points-v2 = <&qup_opp_table>; 1366 status = "disabled"; 1367 }; 1368 1369 i2c6: i2c@898000 { 1370 compatible = "qcom,geni-i2c"; 1371 reg = <0 0x00898000 0 0x4000>; 1372 clock-names = "se"; 1373 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1374 pinctrl-names = "default"; 1375 pinctrl-0 = <&qup_i2c6_default>; 1376 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1377 #address-cells = <1>; 1378 #size-cells = <0>; 1379 power-domains = <&rpmhpd SDM845_CX>; 1380 operating-points-v2 = <&qup_opp_table>; 1381 status = "disabled"; 1382 }; 1383 1384 spi6: spi@898000 { 1385 compatible = "qcom,geni-spi"; 1386 reg = <0 0x00898000 0 0x4000>; 1387 clock-names = "se"; 1388 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1389 pinctrl-names = "default"; 1390 pinctrl-0 = <&qup_spi6_default>; 1391 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1392 #address-cells = <1>; 1393 #size-cells = <0>; 1394 status = "disabled"; 1395 }; 1396 1397 uart6: serial@898000 { 1398 compatible = "qcom,geni-uart"; 1399 reg = <0 0x00898000 0 0x4000>; 1400 clock-names = "se"; 1401 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1402 pinctrl-names = "default"; 1403 pinctrl-0 = <&qup_uart6_default>; 1404 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1405 power-domains = <&rpmhpd SDM845_CX>; 1406 operating-points-v2 = <&qup_opp_table>; 1407 status = "disabled"; 1408 }; 1409 1410 i2c7: i2c@89c000 { 1411 compatible = "qcom,geni-i2c"; 1412 reg = <0 0x0089c000 0 0x4000>; 1413 clock-names = "se"; 1414 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1415 pinctrl-names = "default"; 1416 pinctrl-0 = <&qup_i2c7_default>; 1417 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1418 #address-cells = <1>; 1419 #size-cells = <0>; 1420 power-domains = <&rpmhpd SDM845_CX>; 1421 operating-points-v2 = <&qup_opp_table>; 1422 status = "disabled"; 1423 }; 1424 1425 spi7: spi@89c000 { 1426 compatible = "qcom,geni-spi"; 1427 reg = <0 0x0089c000 0 0x4000>; 1428 clock-names = "se"; 1429 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1430 pinctrl-names = "default"; 1431 pinctrl-0 = <&qup_spi7_default>; 1432 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1433 #address-cells = <1>; 1434 #size-cells = <0>; 1435 status = "disabled"; 1436 }; 1437 1438 uart7: serial@89c000 { 1439 compatible = "qcom,geni-uart"; 1440 reg = <0 0x0089c000 0 0x4000>; 1441 clock-names = "se"; 1442 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1443 pinctrl-names = "default"; 1444 pinctrl-0 = <&qup_uart7_default>; 1445 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1446 power-domains = <&rpmhpd SDM845_CX>; 1447 operating-points-v2 = <&qup_opp_table>; 1448 status = "disabled"; 1449 }; 1450 }; 1451 1452 qupv3_id_1: geniqup@ac0000 { 1453 compatible = "qcom,geni-se-qup"; 1454 reg = <0 0x00ac0000 0 0x6000>; 1455 clock-names = "m-ahb", "s-ahb"; 1456 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1457 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1458 #address-cells = <2>; 1459 #size-cells = <2>; 1460 ranges; 1461 status = "disabled"; 1462 1463 i2c8: i2c@a80000 { 1464 compatible = "qcom,geni-i2c"; 1465 reg = <0 0x00a80000 0 0x4000>; 1466 clock-names = "se"; 1467 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1468 pinctrl-names = "default"; 1469 pinctrl-0 = <&qup_i2c8_default>; 1470 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1471 #address-cells = <1>; 1472 #size-cells = <0>; 1473 power-domains = <&rpmhpd SDM845_CX>; 1474 operating-points-v2 = <&qup_opp_table>; 1475 status = "disabled"; 1476 }; 1477 1478 spi8: spi@a80000 { 1479 compatible = "qcom,geni-spi"; 1480 reg = <0 0x00a80000 0 0x4000>; 1481 clock-names = "se"; 1482 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1483 pinctrl-names = "default"; 1484 pinctrl-0 = <&qup_spi8_default>; 1485 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1486 #address-cells = <1>; 1487 #size-cells = <0>; 1488 status = "disabled"; 1489 }; 1490 1491 uart8: serial@a80000 { 1492 compatible = "qcom,geni-uart"; 1493 reg = <0 0x00a80000 0 0x4000>; 1494 clock-names = "se"; 1495 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1496 pinctrl-names = "default"; 1497 pinctrl-0 = <&qup_uart8_default>; 1498 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1499 power-domains = <&rpmhpd SDM845_CX>; 1500 operating-points-v2 = <&qup_opp_table>; 1501 status = "disabled"; 1502 }; 1503 1504 i2c9: i2c@a84000 { 1505 compatible = "qcom,geni-i2c"; 1506 reg = <0 0x00a84000 0 0x4000>; 1507 clock-names = "se"; 1508 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1509 pinctrl-names = "default"; 1510 pinctrl-0 = <&qup_i2c9_default>; 1511 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1512 #address-cells = <1>; 1513 #size-cells = <0>; 1514 power-domains = <&rpmhpd SDM845_CX>; 1515 operating-points-v2 = <&qup_opp_table>; 1516 status = "disabled"; 1517 }; 1518 1519 spi9: spi@a84000 { 1520 compatible = "qcom,geni-spi"; 1521 reg = <0 0x00a84000 0 0x4000>; 1522 clock-names = "se"; 1523 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1524 pinctrl-names = "default"; 1525 pinctrl-0 = <&qup_spi9_default>; 1526 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1527 #address-cells = <1>; 1528 #size-cells = <0>; 1529 status = "disabled"; 1530 }; 1531 1532 uart9: serial@a84000 { 1533 compatible = "qcom,geni-debug-uart"; 1534 reg = <0 0x00a84000 0 0x4000>; 1535 clock-names = "se"; 1536 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1537 pinctrl-names = "default"; 1538 pinctrl-0 = <&qup_uart9_default>; 1539 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1540 power-domains = <&rpmhpd SDM845_CX>; 1541 operating-points-v2 = <&qup_opp_table>; 1542 status = "disabled"; 1543 }; 1544 1545 i2c10: i2c@a88000 { 1546 compatible = "qcom,geni-i2c"; 1547 reg = <0 0x00a88000 0 0x4000>; 1548 clock-names = "se"; 1549 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1550 pinctrl-names = "default"; 1551 pinctrl-0 = <&qup_i2c10_default>; 1552 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1553 #address-cells = <1>; 1554 #size-cells = <0>; 1555 power-domains = <&rpmhpd SDM845_CX>; 1556 operating-points-v2 = <&qup_opp_table>; 1557 status = "disabled"; 1558 }; 1559 1560 spi10: spi@a88000 { 1561 compatible = "qcom,geni-spi"; 1562 reg = <0 0x00a88000 0 0x4000>; 1563 clock-names = "se"; 1564 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1565 pinctrl-names = "default"; 1566 pinctrl-0 = <&qup_spi10_default>; 1567 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1568 #address-cells = <1>; 1569 #size-cells = <0>; 1570 status = "disabled"; 1571 }; 1572 1573 uart10: serial@a88000 { 1574 compatible = "qcom,geni-uart"; 1575 reg = <0 0x00a88000 0 0x4000>; 1576 clock-names = "se"; 1577 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1578 pinctrl-names = "default"; 1579 pinctrl-0 = <&qup_uart10_default>; 1580 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1581 power-domains = <&rpmhpd SDM845_CX>; 1582 operating-points-v2 = <&qup_opp_table>; 1583 status = "disabled"; 1584 }; 1585 1586 i2c11: i2c@a8c000 { 1587 compatible = "qcom,geni-i2c"; 1588 reg = <0 0x00a8c000 0 0x4000>; 1589 clock-names = "se"; 1590 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1591 pinctrl-names = "default"; 1592 pinctrl-0 = <&qup_i2c11_default>; 1593 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1594 #address-cells = <1>; 1595 #size-cells = <0>; 1596 power-domains = <&rpmhpd SDM845_CX>; 1597 operating-points-v2 = <&qup_opp_table>; 1598 status = "disabled"; 1599 }; 1600 1601 spi11: spi@a8c000 { 1602 compatible = "qcom,geni-spi"; 1603 reg = <0 0x00a8c000 0 0x4000>; 1604 clock-names = "se"; 1605 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1606 pinctrl-names = "default"; 1607 pinctrl-0 = <&qup_spi11_default>; 1608 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1609 #address-cells = <1>; 1610 #size-cells = <0>; 1611 status = "disabled"; 1612 }; 1613 1614 uart11: serial@a8c000 { 1615 compatible = "qcom,geni-uart"; 1616 reg = <0 0x00a8c000 0 0x4000>; 1617 clock-names = "se"; 1618 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1619 pinctrl-names = "default"; 1620 pinctrl-0 = <&qup_uart11_default>; 1621 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1622 power-domains = <&rpmhpd SDM845_CX>; 1623 operating-points-v2 = <&qup_opp_table>; 1624 status = "disabled"; 1625 }; 1626 1627 i2c12: i2c@a90000 { 1628 compatible = "qcom,geni-i2c"; 1629 reg = <0 0x00a90000 0 0x4000>; 1630 clock-names = "se"; 1631 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1632 pinctrl-names = "default"; 1633 pinctrl-0 = <&qup_i2c12_default>; 1634 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1635 #address-cells = <1>; 1636 #size-cells = <0>; 1637 power-domains = <&rpmhpd SDM845_CX>; 1638 operating-points-v2 = <&qup_opp_table>; 1639 status = "disabled"; 1640 }; 1641 1642 spi12: spi@a90000 { 1643 compatible = "qcom,geni-spi"; 1644 reg = <0 0x00a90000 0 0x4000>; 1645 clock-names = "se"; 1646 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1647 pinctrl-names = "default"; 1648 pinctrl-0 = <&qup_spi12_default>; 1649 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1650 #address-cells = <1>; 1651 #size-cells = <0>; 1652 status = "disabled"; 1653 }; 1654 1655 uart12: serial@a90000 { 1656 compatible = "qcom,geni-uart"; 1657 reg = <0 0x00a90000 0 0x4000>; 1658 clock-names = "se"; 1659 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1660 pinctrl-names = "default"; 1661 pinctrl-0 = <&qup_uart12_default>; 1662 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1663 power-domains = <&rpmhpd SDM845_CX>; 1664 operating-points-v2 = <&qup_opp_table>; 1665 status = "disabled"; 1666 }; 1667 1668 i2c13: i2c@a94000 { 1669 compatible = "qcom,geni-i2c"; 1670 reg = <0 0x00a94000 0 0x4000>; 1671 clock-names = "se"; 1672 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1673 pinctrl-names = "default"; 1674 pinctrl-0 = <&qup_i2c13_default>; 1675 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1676 #address-cells = <1>; 1677 #size-cells = <0>; 1678 power-domains = <&rpmhpd SDM845_CX>; 1679 operating-points-v2 = <&qup_opp_table>; 1680 status = "disabled"; 1681 }; 1682 1683 spi13: spi@a94000 { 1684 compatible = "qcom,geni-spi"; 1685 reg = <0 0x00a94000 0 0x4000>; 1686 clock-names = "se"; 1687 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1688 pinctrl-names = "default"; 1689 pinctrl-0 = <&qup_spi13_default>; 1690 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1691 #address-cells = <1>; 1692 #size-cells = <0>; 1693 status = "disabled"; 1694 }; 1695 1696 uart13: serial@a94000 { 1697 compatible = "qcom,geni-uart"; 1698 reg = <0 0x00a94000 0 0x4000>; 1699 clock-names = "se"; 1700 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1701 pinctrl-names = "default"; 1702 pinctrl-0 = <&qup_uart13_default>; 1703 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1704 power-domains = <&rpmhpd SDM845_CX>; 1705 operating-points-v2 = <&qup_opp_table>; 1706 status = "disabled"; 1707 }; 1708 1709 i2c14: i2c@a98000 { 1710 compatible = "qcom,geni-i2c"; 1711 reg = <0 0x00a98000 0 0x4000>; 1712 clock-names = "se"; 1713 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1714 pinctrl-names = "default"; 1715 pinctrl-0 = <&qup_i2c14_default>; 1716 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 1717 #address-cells = <1>; 1718 #size-cells = <0>; 1719 power-domains = <&rpmhpd SDM845_CX>; 1720 operating-points-v2 = <&qup_opp_table>; 1721 status = "disabled"; 1722 }; 1723 1724 spi14: spi@a98000 { 1725 compatible = "qcom,geni-spi"; 1726 reg = <0 0x00a98000 0 0x4000>; 1727 clock-names = "se"; 1728 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1729 pinctrl-names = "default"; 1730 pinctrl-0 = <&qup_spi14_default>; 1731 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 1732 #address-cells = <1>; 1733 #size-cells = <0>; 1734 status = "disabled"; 1735 }; 1736 1737 uart14: serial@a98000 { 1738 compatible = "qcom,geni-uart"; 1739 reg = <0 0x00a98000 0 0x4000>; 1740 clock-names = "se"; 1741 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1742 pinctrl-names = "default"; 1743 pinctrl-0 = <&qup_uart14_default>; 1744 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 1745 power-domains = <&rpmhpd SDM845_CX>; 1746 operating-points-v2 = <&qup_opp_table>; 1747 status = "disabled"; 1748 }; 1749 1750 i2c15: i2c@a9c000 { 1751 compatible = "qcom,geni-i2c"; 1752 reg = <0 0x00a9c000 0 0x4000>; 1753 clock-names = "se"; 1754 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1755 pinctrl-names = "default"; 1756 pinctrl-0 = <&qup_i2c15_default>; 1757 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1758 #address-cells = <1>; 1759 #size-cells = <0>; 1760 power-domains = <&rpmhpd SDM845_CX>; 1761 operating-points-v2 = <&qup_opp_table>; 1762 status = "disabled"; 1763 }; 1764 1765 spi15: spi@a9c000 { 1766 compatible = "qcom,geni-spi"; 1767 reg = <0 0x00a9c000 0 0x4000>; 1768 clock-names = "se"; 1769 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1770 pinctrl-names = "default"; 1771 pinctrl-0 = <&qup_spi15_default>; 1772 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1773 #address-cells = <1>; 1774 #size-cells = <0>; 1775 status = "disabled"; 1776 }; 1777 1778 uart15: serial@a9c000 { 1779 compatible = "qcom,geni-uart"; 1780 reg = <0 0x00a9c000 0 0x4000>; 1781 clock-names = "se"; 1782 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1783 pinctrl-names = "default"; 1784 pinctrl-0 = <&qup_uart15_default>; 1785 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1786 power-domains = <&rpmhpd SDM845_CX>; 1787 operating-points-v2 = <&qup_opp_table>; 1788 status = "disabled"; 1789 }; 1790 }; 1791 1792 system-cache-controller@1100000 { 1793 compatible = "qcom,sdm845-llcc"; 1794 reg = <0 0x01100000 0 0x200000>, <0 0x01300000 0 0x50000>; 1795 reg-names = "llcc_base", "llcc_broadcast_base"; 1796 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 1797 }; 1798 1799 pcie0: pci@1c00000 { 1800 compatible = "qcom,pcie-sdm845", "snps,dw-pcie"; 1801 reg = <0 0x01c00000 0 0x2000>, 1802 <0 0x60000000 0 0xf1d>, 1803 <0 0x60000f20 0 0xa8>, 1804 <0 0x60100000 0 0x100000>; 1805 reg-names = "parf", "dbi", "elbi", "config"; 1806 device_type = "pci"; 1807 linux,pci-domain = <0>; 1808 bus-range = <0x00 0xff>; 1809 num-lanes = <1>; 1810 1811 #address-cells = <3>; 1812 #size-cells = <2>; 1813 1814 ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>, 1815 <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0xd00000>; 1816 1817 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 1818 interrupt-names = "msi"; 1819 #interrupt-cells = <1>; 1820 interrupt-map-mask = <0 0 0 0x7>; 1821 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1822 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1823 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1824 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1825 1826 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1827 <&gcc GCC_PCIE_0_AUX_CLK>, 1828 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1829 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1830 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1831 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1832 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; 1833 clock-names = "pipe", 1834 "aux", 1835 "cfg", 1836 "bus_master", 1837 "bus_slave", 1838 "slave_q2a", 1839 "tbu"; 1840 1841 iommus = <&apps_smmu 0x1c10 0xf>; 1842 iommu-map = <0x0 &apps_smmu 0x1c10 0x1>, 1843 <0x100 &apps_smmu 0x1c11 0x1>, 1844 <0x200 &apps_smmu 0x1c12 0x1>, 1845 <0x300 &apps_smmu 0x1c13 0x1>, 1846 <0x400 &apps_smmu 0x1c14 0x1>, 1847 <0x500 &apps_smmu 0x1c15 0x1>, 1848 <0x600 &apps_smmu 0x1c16 0x1>, 1849 <0x700 &apps_smmu 0x1c17 0x1>, 1850 <0x800 &apps_smmu 0x1c18 0x1>, 1851 <0x900 &apps_smmu 0x1c19 0x1>, 1852 <0xa00 &apps_smmu 0x1c1a 0x1>, 1853 <0xb00 &apps_smmu 0x1c1b 0x1>, 1854 <0xc00 &apps_smmu 0x1c1c 0x1>, 1855 <0xd00 &apps_smmu 0x1c1d 0x1>, 1856 <0xe00 &apps_smmu 0x1c1e 0x1>, 1857 <0xf00 &apps_smmu 0x1c1f 0x1>; 1858 1859 resets = <&gcc GCC_PCIE_0_BCR>; 1860 reset-names = "pci"; 1861 1862 power-domains = <&gcc PCIE_0_GDSC>; 1863 1864 phys = <&pcie0_lane>; 1865 phy-names = "pciephy"; 1866 1867 status = "disabled"; 1868 }; 1869 1870 pcie0_phy: phy@1c06000 { 1871 compatible = "qcom,sdm845-qmp-pcie-phy"; 1872 reg = <0 0x01c06000 0 0x18c>; 1873 #address-cells = <2>; 1874 #size-cells = <2>; 1875 ranges; 1876 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1877 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1878 <&gcc GCC_PCIE_0_CLKREF_CLK>, 1879 <&gcc GCC_PCIE_PHY_REFGEN_CLK>; 1880 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 1881 1882 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1883 reset-names = "phy"; 1884 1885 assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>; 1886 assigned-clock-rates = <100000000>; 1887 1888 status = "disabled"; 1889 1890 pcie0_lane: lanes@1c06200 { 1891 reg = <0 0x01c06200 0 0x128>, 1892 <0 0x01c06400 0 0x1fc>, 1893 <0 0x01c06800 0 0x218>, 1894 <0 0x01c06600 0 0x70>; 1895 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 1896 clock-names = "pipe0"; 1897 1898 #phy-cells = <0>; 1899 clock-output-names = "pcie_0_pipe_clk"; 1900 }; 1901 }; 1902 1903 pcie1: pci@1c08000 { 1904 compatible = "qcom,pcie-sdm845", "snps,dw-pcie"; 1905 reg = <0 0x01c08000 0 0x2000>, 1906 <0 0x40000000 0 0xf1d>, 1907 <0 0x40000f20 0 0xa8>, 1908 <0 0x40100000 0 0x100000>; 1909 reg-names = "parf", "dbi", "elbi", "config"; 1910 device_type = "pci"; 1911 linux,pci-domain = <1>; 1912 bus-range = <0x00 0xff>; 1913 num-lanes = <1>; 1914 1915 #address-cells = <3>; 1916 #size-cells = <2>; 1917 1918 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, 1919 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1920 1921 interrupts = <GIC_SPI 307 IRQ_TYPE_EDGE_RISING>; 1922 interrupt-names = "msi"; 1923 #interrupt-cells = <1>; 1924 interrupt-map-mask = <0 0 0 0x7>; 1925 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1926 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1927 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1928 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1929 1930 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1931 <&gcc GCC_PCIE_1_AUX_CLK>, 1932 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1933 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1934 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1935 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1936 <&gcc GCC_PCIE_1_CLKREF_CLK>, 1937 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; 1938 clock-names = "pipe", 1939 "aux", 1940 "cfg", 1941 "bus_master", 1942 "bus_slave", 1943 "slave_q2a", 1944 "ref", 1945 "tbu"; 1946 1947 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 1948 assigned-clock-rates = <19200000>; 1949 1950 iommus = <&apps_smmu 0x1c00 0xf>; 1951 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, 1952 <0x100 &apps_smmu 0x1c01 0x1>, 1953 <0x200 &apps_smmu 0x1c02 0x1>, 1954 <0x300 &apps_smmu 0x1c03 0x1>, 1955 <0x400 &apps_smmu 0x1c04 0x1>, 1956 <0x500 &apps_smmu 0x1c05 0x1>, 1957 <0x600 &apps_smmu 0x1c06 0x1>, 1958 <0x700 &apps_smmu 0x1c07 0x1>, 1959 <0x800 &apps_smmu 0x1c08 0x1>, 1960 <0x900 &apps_smmu 0x1c09 0x1>, 1961 <0xa00 &apps_smmu 0x1c0a 0x1>, 1962 <0xb00 &apps_smmu 0x1c0b 0x1>, 1963 <0xc00 &apps_smmu 0x1c0c 0x1>, 1964 <0xd00 &apps_smmu 0x1c0d 0x1>, 1965 <0xe00 &apps_smmu 0x1c0e 0x1>, 1966 <0xf00 &apps_smmu 0x1c0f 0x1>; 1967 1968 resets = <&gcc GCC_PCIE_1_BCR>; 1969 reset-names = "pci"; 1970 1971 power-domains = <&gcc PCIE_1_GDSC>; 1972 1973 phys = <&pcie1_lane>; 1974 phy-names = "pciephy"; 1975 1976 status = "disabled"; 1977 }; 1978 1979 pcie1_phy: phy@1c0a000 { 1980 compatible = "qcom,sdm845-qhp-pcie-phy"; 1981 reg = <0 0x01c0a000 0 0x800>; 1982 #address-cells = <2>; 1983 #size-cells = <2>; 1984 ranges; 1985 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1986 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1987 <&gcc GCC_PCIE_1_CLKREF_CLK>, 1988 <&gcc GCC_PCIE_PHY_REFGEN_CLK>; 1989 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 1990 1991 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 1992 reset-names = "phy"; 1993 1994 assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>; 1995 assigned-clock-rates = <100000000>; 1996 1997 status = "disabled"; 1998 1999 pcie1_lane: lanes@1c06200 { 2000 reg = <0 0x01c0a800 0 0x800>, 2001 <0 0x01c0a800 0 0x800>, 2002 <0 0x01c0b800 0 0x400>; 2003 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 2004 clock-names = "pipe0"; 2005 2006 #phy-cells = <0>; 2007 clock-output-names = "pcie_1_pipe_clk"; 2008 }; 2009 }; 2010 2011 mem_noc: interconnect@1380000 { 2012 compatible = "qcom,sdm845-mem-noc"; 2013 reg = <0 0x01380000 0 0x27200>; 2014 #interconnect-cells = <2>; 2015 qcom,bcm-voters = <&apps_bcm_voter>; 2016 }; 2017 2018 dc_noc: interconnect@14e0000 { 2019 compatible = "qcom,sdm845-dc-noc"; 2020 reg = <0 0x014e0000 0 0x400>; 2021 #interconnect-cells = <2>; 2022 qcom,bcm-voters = <&apps_bcm_voter>; 2023 }; 2024 2025 config_noc: interconnect@1500000 { 2026 compatible = "qcom,sdm845-config-noc"; 2027 reg = <0 0x01500000 0 0x5080>; 2028 #interconnect-cells = <2>; 2029 qcom,bcm-voters = <&apps_bcm_voter>; 2030 }; 2031 2032 system_noc: interconnect@1620000 { 2033 compatible = "qcom,sdm845-system-noc"; 2034 reg = <0 0x01620000 0 0x18080>; 2035 #interconnect-cells = <2>; 2036 qcom,bcm-voters = <&apps_bcm_voter>; 2037 }; 2038 2039 aggre1_noc: interconnect@16e0000 { 2040 compatible = "qcom,sdm845-aggre1-noc"; 2041 reg = <0 0x016e0000 0 0x15080>; 2042 #interconnect-cells = <2>; 2043 qcom,bcm-voters = <&apps_bcm_voter>; 2044 }; 2045 2046 aggre2_noc: interconnect@1700000 { 2047 compatible = "qcom,sdm845-aggre2-noc"; 2048 reg = <0 0x01700000 0 0x1f300>; 2049 #interconnect-cells = <2>; 2050 qcom,bcm-voters = <&apps_bcm_voter>; 2051 }; 2052 2053 mmss_noc: interconnect@1740000 { 2054 compatible = "qcom,sdm845-mmss-noc"; 2055 reg = <0 0x01740000 0 0x1c100>; 2056 #interconnect-cells = <2>; 2057 qcom,bcm-voters = <&apps_bcm_voter>; 2058 }; 2059 2060 ufs_mem_hc: ufshc@1d84000 { 2061 compatible = "qcom,sdm845-ufshc", "qcom,ufshc", 2062 "jedec,ufs-2.0"; 2063 reg = <0 0x01d84000 0 0x2500>, 2064 <0 0x01d90000 0 0x8000>; 2065 reg-names = "std", "ice"; 2066 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2067 phys = <&ufs_mem_phy_lanes>; 2068 phy-names = "ufsphy"; 2069 lanes-per-direction = <2>; 2070 power-domains = <&gcc UFS_PHY_GDSC>; 2071 #reset-cells = <1>; 2072 resets = <&gcc GCC_UFS_PHY_BCR>; 2073 reset-names = "rst"; 2074 2075 iommus = <&apps_smmu 0x100 0xf>; 2076 2077 clock-names = 2078 "core_clk", 2079 "bus_aggr_clk", 2080 "iface_clk", 2081 "core_clk_unipro", 2082 "ref_clk", 2083 "tx_lane0_sync_clk", 2084 "rx_lane0_sync_clk", 2085 "rx_lane1_sync_clk", 2086 "ice_core_clk"; 2087 clocks = 2088 <&gcc GCC_UFS_PHY_AXI_CLK>, 2089 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2090 <&gcc GCC_UFS_PHY_AHB_CLK>, 2091 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2092 <&rpmhcc RPMH_CXO_CLK>, 2093 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2094 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2095 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, 2096 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 2097 freq-table-hz = 2098 <50000000 200000000>, 2099 <0 0>, 2100 <0 0>, 2101 <37500000 150000000>, 2102 <0 0>, 2103 <0 0>, 2104 <0 0>, 2105 <0 0>, 2106 <0 300000000>; 2107 2108 status = "disabled"; 2109 }; 2110 2111 ufs_mem_phy: phy@1d87000 { 2112 compatible = "qcom,sdm845-qmp-ufs-phy"; 2113 reg = <0 0x01d87000 0 0x18c>; 2114 #address-cells = <2>; 2115 #size-cells = <2>; 2116 ranges; 2117 clock-names = "ref", 2118 "ref_aux"; 2119 clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, 2120 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 2121 2122 resets = <&ufs_mem_hc 0>; 2123 reset-names = "ufsphy"; 2124 status = "disabled"; 2125 2126 ufs_mem_phy_lanes: lanes@1d87400 { 2127 reg = <0 0x01d87400 0 0x108>, 2128 <0 0x01d87600 0 0x1e0>, 2129 <0 0x01d87c00 0 0x1dc>, 2130 <0 0x01d87800 0 0x108>, 2131 <0 0x01d87a00 0 0x1e0>; 2132 #phy-cells = <0>; 2133 }; 2134 }; 2135 2136 ipa: ipa@1e40000 { 2137 compatible = "qcom,sdm845-ipa"; 2138 2139 iommus = <&apps_smmu 0x720 0x3>; 2140 reg = <0 0x1e40000 0 0x7000>, 2141 <0 0x1e47000 0 0x2000>, 2142 <0 0x1e04000 0 0x2c000>; 2143 reg-names = "ipa-reg", 2144 "ipa-shared", 2145 "gsi"; 2146 2147 interrupts-extended = <&intc 0 311 IRQ_TYPE_EDGE_RISING>, 2148 <&intc 0 432 IRQ_TYPE_LEVEL_HIGH>, 2149 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2150 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 2151 interrupt-names = "ipa", 2152 "gsi", 2153 "ipa-clock-query", 2154 "ipa-setup-ready"; 2155 2156 clocks = <&rpmhcc RPMH_IPA_CLK>; 2157 clock-names = "core"; 2158 2159 interconnects = <&aggre2_noc MASTER_IPA 0 &mem_noc SLAVE_EBI1 0>, 2160 <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>, 2161 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>; 2162 interconnect-names = "memory", 2163 "imem", 2164 "config"; 2165 2166 qcom,smem-states = <&ipa_smp2p_out 0>, 2167 <&ipa_smp2p_out 1>; 2168 qcom,smem-state-names = "ipa-clock-enabled-valid", 2169 "ipa-clock-enabled"; 2170 2171 modem-remoteproc = <&mss_pil>; 2172 2173 status = "disabled"; 2174 }; 2175 2176 tcsr_mutex_regs: syscon@1f40000 { 2177 compatible = "syscon"; 2178 reg = <0 0x01f40000 0 0x40000>; 2179 }; 2180 2181 tlmm: pinctrl@3400000 { 2182 compatible = "qcom,sdm845-pinctrl"; 2183 reg = <0 0x03400000 0 0xc00000>; 2184 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 2185 gpio-controller; 2186 #gpio-cells = <2>; 2187 interrupt-controller; 2188 #interrupt-cells = <2>; 2189 gpio-ranges = <&tlmm 0 0 150>; 2190 wakeup-parent = <&pdc_intc>; 2191 2192 cci0_default: cci0-default { 2193 /* SDA, SCL */ 2194 pins = "gpio17", "gpio18"; 2195 function = "cci_i2c"; 2196 2197 bias-pull-up; 2198 drive-strength = <2>; /* 2 mA */ 2199 }; 2200 2201 cci0_sleep: cci0-sleep { 2202 /* SDA, SCL */ 2203 pins = "gpio17", "gpio18"; 2204 function = "cci_i2c"; 2205 2206 drive-strength = <2>; /* 2 mA */ 2207 bias-pull-down; 2208 }; 2209 2210 cci1_default: cci1-default { 2211 /* SDA, SCL */ 2212 pins = "gpio19", "gpio20"; 2213 function = "cci_i2c"; 2214 2215 bias-pull-up; 2216 drive-strength = <2>; /* 2 mA */ 2217 }; 2218 2219 cci1_sleep: cci1-sleep { 2220 /* SDA, SCL */ 2221 pins = "gpio19", "gpio20"; 2222 function = "cci_i2c"; 2223 2224 drive-strength = <2>; /* 2 mA */ 2225 bias-pull-down; 2226 }; 2227 2228 qspi_clk: qspi-clk { 2229 pinmux { 2230 pins = "gpio95"; 2231 function = "qspi_clk"; 2232 }; 2233 }; 2234 2235 qspi_cs0: qspi-cs0 { 2236 pinmux { 2237 pins = "gpio90"; 2238 function = "qspi_cs"; 2239 }; 2240 }; 2241 2242 qspi_cs1: qspi-cs1 { 2243 pinmux { 2244 pins = "gpio89"; 2245 function = "qspi_cs"; 2246 }; 2247 }; 2248 2249 qspi_data01: qspi-data01 { 2250 pinmux-data { 2251 pins = "gpio91", "gpio92"; 2252 function = "qspi_data"; 2253 }; 2254 }; 2255 2256 qspi_data12: qspi-data12 { 2257 pinmux-data { 2258 pins = "gpio93", "gpio94"; 2259 function = "qspi_data"; 2260 }; 2261 }; 2262 2263 qup_i2c0_default: qup-i2c0-default { 2264 pinmux { 2265 pins = "gpio0", "gpio1"; 2266 function = "qup0"; 2267 }; 2268 }; 2269 2270 qup_i2c1_default: qup-i2c1-default { 2271 pinmux { 2272 pins = "gpio17", "gpio18"; 2273 function = "qup1"; 2274 }; 2275 }; 2276 2277 qup_i2c2_default: qup-i2c2-default { 2278 pinmux { 2279 pins = "gpio27", "gpio28"; 2280 function = "qup2"; 2281 }; 2282 }; 2283 2284 qup_i2c3_default: qup-i2c3-default { 2285 pinmux { 2286 pins = "gpio41", "gpio42"; 2287 function = "qup3"; 2288 }; 2289 }; 2290 2291 qup_i2c4_default: qup-i2c4-default { 2292 pinmux { 2293 pins = "gpio89", "gpio90"; 2294 function = "qup4"; 2295 }; 2296 }; 2297 2298 qup_i2c5_default: qup-i2c5-default { 2299 pinmux { 2300 pins = "gpio85", "gpio86"; 2301 function = "qup5"; 2302 }; 2303 }; 2304 2305 qup_i2c6_default: qup-i2c6-default { 2306 pinmux { 2307 pins = "gpio45", "gpio46"; 2308 function = "qup6"; 2309 }; 2310 }; 2311 2312 qup_i2c7_default: qup-i2c7-default { 2313 pinmux { 2314 pins = "gpio93", "gpio94"; 2315 function = "qup7"; 2316 }; 2317 }; 2318 2319 qup_i2c8_default: qup-i2c8-default { 2320 pinmux { 2321 pins = "gpio65", "gpio66"; 2322 function = "qup8"; 2323 }; 2324 }; 2325 2326 qup_i2c9_default: qup-i2c9-default { 2327 pinmux { 2328 pins = "gpio6", "gpio7"; 2329 function = "qup9"; 2330 }; 2331 }; 2332 2333 qup_i2c10_default: qup-i2c10-default { 2334 pinmux { 2335 pins = "gpio55", "gpio56"; 2336 function = "qup10"; 2337 }; 2338 }; 2339 2340 qup_i2c11_default: qup-i2c11-default { 2341 pinmux { 2342 pins = "gpio31", "gpio32"; 2343 function = "qup11"; 2344 }; 2345 }; 2346 2347 qup_i2c12_default: qup-i2c12-default { 2348 pinmux { 2349 pins = "gpio49", "gpio50"; 2350 function = "qup12"; 2351 }; 2352 }; 2353 2354 qup_i2c13_default: qup-i2c13-default { 2355 pinmux { 2356 pins = "gpio105", "gpio106"; 2357 function = "qup13"; 2358 }; 2359 }; 2360 2361 qup_i2c14_default: qup-i2c14-default { 2362 pinmux { 2363 pins = "gpio33", "gpio34"; 2364 function = "qup14"; 2365 }; 2366 }; 2367 2368 qup_i2c15_default: qup-i2c15-default { 2369 pinmux { 2370 pins = "gpio81", "gpio82"; 2371 function = "qup15"; 2372 }; 2373 }; 2374 2375 qup_spi0_default: qup-spi0-default { 2376 pinmux { 2377 pins = "gpio0", "gpio1", 2378 "gpio2", "gpio3"; 2379 function = "qup0"; 2380 }; 2381 }; 2382 2383 qup_spi1_default: qup-spi1-default { 2384 pinmux { 2385 pins = "gpio17", "gpio18", 2386 "gpio19", "gpio20"; 2387 function = "qup1"; 2388 }; 2389 }; 2390 2391 qup_spi2_default: qup-spi2-default { 2392 pinmux { 2393 pins = "gpio27", "gpio28", 2394 "gpio29", "gpio30"; 2395 function = "qup2"; 2396 }; 2397 }; 2398 2399 qup_spi3_default: qup-spi3-default { 2400 pinmux { 2401 pins = "gpio41", "gpio42", 2402 "gpio43", "gpio44"; 2403 function = "qup3"; 2404 }; 2405 }; 2406 2407 qup_spi4_default: qup-spi4-default { 2408 pinmux { 2409 pins = "gpio89", "gpio90", 2410 "gpio91", "gpio92"; 2411 function = "qup4"; 2412 }; 2413 }; 2414 2415 qup_spi5_default: qup-spi5-default { 2416 pinmux { 2417 pins = "gpio85", "gpio86", 2418 "gpio87", "gpio88"; 2419 function = "qup5"; 2420 }; 2421 }; 2422 2423 qup_spi6_default: qup-spi6-default { 2424 pinmux { 2425 pins = "gpio45", "gpio46", 2426 "gpio47", "gpio48"; 2427 function = "qup6"; 2428 }; 2429 }; 2430 2431 qup_spi7_default: qup-spi7-default { 2432 pinmux { 2433 pins = "gpio93", "gpio94", 2434 "gpio95", "gpio96"; 2435 function = "qup7"; 2436 }; 2437 }; 2438 2439 qup_spi8_default: qup-spi8-default { 2440 pinmux { 2441 pins = "gpio65", "gpio66", 2442 "gpio67", "gpio68"; 2443 function = "qup8"; 2444 }; 2445 }; 2446 2447 qup_spi9_default: qup-spi9-default { 2448 pinmux { 2449 pins = "gpio6", "gpio7", 2450 "gpio4", "gpio5"; 2451 function = "qup9"; 2452 }; 2453 }; 2454 2455 qup_spi10_default: qup-spi10-default { 2456 pinmux { 2457 pins = "gpio55", "gpio56", 2458 "gpio53", "gpio54"; 2459 function = "qup10"; 2460 }; 2461 }; 2462 2463 qup_spi11_default: qup-spi11-default { 2464 pinmux { 2465 pins = "gpio31", "gpio32", 2466 "gpio33", "gpio34"; 2467 function = "qup11"; 2468 }; 2469 }; 2470 2471 qup_spi12_default: qup-spi12-default { 2472 pinmux { 2473 pins = "gpio49", "gpio50", 2474 "gpio51", "gpio52"; 2475 function = "qup12"; 2476 }; 2477 }; 2478 2479 qup_spi13_default: qup-spi13-default { 2480 pinmux { 2481 pins = "gpio105", "gpio106", 2482 "gpio107", "gpio108"; 2483 function = "qup13"; 2484 }; 2485 }; 2486 2487 qup_spi14_default: qup-spi14-default { 2488 pinmux { 2489 pins = "gpio33", "gpio34", 2490 "gpio31", "gpio32"; 2491 function = "qup14"; 2492 }; 2493 }; 2494 2495 qup_spi15_default: qup-spi15-default { 2496 pinmux { 2497 pins = "gpio81", "gpio82", 2498 "gpio83", "gpio84"; 2499 function = "qup15"; 2500 }; 2501 }; 2502 2503 qup_uart0_default: qup-uart0-default { 2504 pinmux { 2505 pins = "gpio2", "gpio3"; 2506 function = "qup0"; 2507 }; 2508 }; 2509 2510 qup_uart1_default: qup-uart1-default { 2511 pinmux { 2512 pins = "gpio19", "gpio20"; 2513 function = "qup1"; 2514 }; 2515 }; 2516 2517 qup_uart2_default: qup-uart2-default { 2518 pinmux { 2519 pins = "gpio29", "gpio30"; 2520 function = "qup2"; 2521 }; 2522 }; 2523 2524 qup_uart3_default: qup-uart3-default { 2525 pinmux { 2526 pins = "gpio43", "gpio44"; 2527 function = "qup3"; 2528 }; 2529 }; 2530 2531 qup_uart4_default: qup-uart4-default { 2532 pinmux { 2533 pins = "gpio91", "gpio92"; 2534 function = "qup4"; 2535 }; 2536 }; 2537 2538 qup_uart5_default: qup-uart5-default { 2539 pinmux { 2540 pins = "gpio87", "gpio88"; 2541 function = "qup5"; 2542 }; 2543 }; 2544 2545 qup_uart6_default: qup-uart6-default { 2546 pinmux { 2547 pins = "gpio47", "gpio48"; 2548 function = "qup6"; 2549 }; 2550 }; 2551 2552 qup_uart7_default: qup-uart7-default { 2553 pinmux { 2554 pins = "gpio95", "gpio96"; 2555 function = "qup7"; 2556 }; 2557 }; 2558 2559 qup_uart8_default: qup-uart8-default { 2560 pinmux { 2561 pins = "gpio67", "gpio68"; 2562 function = "qup8"; 2563 }; 2564 }; 2565 2566 qup_uart9_default: qup-uart9-default { 2567 pinmux { 2568 pins = "gpio4", "gpio5"; 2569 function = "qup9"; 2570 }; 2571 }; 2572 2573 qup_uart10_default: qup-uart10-default { 2574 pinmux { 2575 pins = "gpio53", "gpio54"; 2576 function = "qup10"; 2577 }; 2578 }; 2579 2580 qup_uart11_default: qup-uart11-default { 2581 pinmux { 2582 pins = "gpio33", "gpio34"; 2583 function = "qup11"; 2584 }; 2585 }; 2586 2587 qup_uart12_default: qup-uart12-default { 2588 pinmux { 2589 pins = "gpio51", "gpio52"; 2590 function = "qup12"; 2591 }; 2592 }; 2593 2594 qup_uart13_default: qup-uart13-default { 2595 pinmux { 2596 pins = "gpio107", "gpio108"; 2597 function = "qup13"; 2598 }; 2599 }; 2600 2601 qup_uart14_default: qup-uart14-default { 2602 pinmux { 2603 pins = "gpio31", "gpio32"; 2604 function = "qup14"; 2605 }; 2606 }; 2607 2608 qup_uart15_default: qup-uart15-default { 2609 pinmux { 2610 pins = "gpio83", "gpio84"; 2611 function = "qup15"; 2612 }; 2613 }; 2614 2615 quat_mi2s_sleep: quat_mi2s_sleep { 2616 mux { 2617 pins = "gpio58", "gpio59"; 2618 function = "gpio"; 2619 }; 2620 2621 config { 2622 pins = "gpio58", "gpio59"; 2623 drive-strength = <2>; 2624 bias-pull-down; 2625 input-enable; 2626 }; 2627 }; 2628 2629 quat_mi2s_active: quat_mi2s_active { 2630 mux { 2631 pins = "gpio58", "gpio59"; 2632 function = "qua_mi2s"; 2633 }; 2634 2635 config { 2636 pins = "gpio58", "gpio59"; 2637 drive-strength = <8>; 2638 bias-disable; 2639 output-high; 2640 }; 2641 }; 2642 2643 quat_mi2s_sd0_sleep: quat_mi2s_sd0_sleep { 2644 mux { 2645 pins = "gpio60"; 2646 function = "gpio"; 2647 }; 2648 2649 config { 2650 pins = "gpio60"; 2651 drive-strength = <2>; 2652 bias-pull-down; 2653 input-enable; 2654 }; 2655 }; 2656 2657 quat_mi2s_sd0_active: quat_mi2s_sd0_active { 2658 mux { 2659 pins = "gpio60"; 2660 function = "qua_mi2s"; 2661 }; 2662 2663 config { 2664 pins = "gpio60"; 2665 drive-strength = <8>; 2666 bias-disable; 2667 }; 2668 }; 2669 2670 quat_mi2s_sd1_sleep: quat_mi2s_sd1_sleep { 2671 mux { 2672 pins = "gpio61"; 2673 function = "gpio"; 2674 }; 2675 2676 config { 2677 pins = "gpio61"; 2678 drive-strength = <2>; 2679 bias-pull-down; 2680 input-enable; 2681 }; 2682 }; 2683 2684 quat_mi2s_sd1_active: quat_mi2s_sd1_active { 2685 mux { 2686 pins = "gpio61"; 2687 function = "qua_mi2s"; 2688 }; 2689 2690 config { 2691 pins = "gpio61"; 2692 drive-strength = <8>; 2693 bias-disable; 2694 }; 2695 }; 2696 2697 quat_mi2s_sd2_sleep: quat_mi2s_sd2_sleep { 2698 mux { 2699 pins = "gpio62"; 2700 function = "gpio"; 2701 }; 2702 2703 config { 2704 pins = "gpio62"; 2705 drive-strength = <2>; 2706 bias-pull-down; 2707 input-enable; 2708 }; 2709 }; 2710 2711 quat_mi2s_sd2_active: quat_mi2s_sd2_active { 2712 mux { 2713 pins = "gpio62"; 2714 function = "qua_mi2s"; 2715 }; 2716 2717 config { 2718 pins = "gpio62"; 2719 drive-strength = <8>; 2720 bias-disable; 2721 }; 2722 }; 2723 2724 quat_mi2s_sd3_sleep: quat_mi2s_sd3_sleep { 2725 mux { 2726 pins = "gpio63"; 2727 function = "gpio"; 2728 }; 2729 2730 config { 2731 pins = "gpio63"; 2732 drive-strength = <2>; 2733 bias-pull-down; 2734 input-enable; 2735 }; 2736 }; 2737 2738 quat_mi2s_sd3_active: quat_mi2s_sd3_active { 2739 mux { 2740 pins = "gpio63"; 2741 function = "qua_mi2s"; 2742 }; 2743 2744 config { 2745 pins = "gpio63"; 2746 drive-strength = <8>; 2747 bias-disable; 2748 }; 2749 }; 2750 }; 2751 2752 mss_pil: remoteproc@4080000 { 2753 compatible = "qcom,sdm845-mss-pil"; 2754 reg = <0 0x04080000 0 0x408>, <0 0x04180000 0 0x48>; 2755 reg-names = "qdsp6", "rmb"; 2756 2757 interrupts-extended = 2758 <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, 2759 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2760 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2761 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2762 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2763 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2764 interrupt-names = "wdog", "fatal", "ready", 2765 "handover", "stop-ack", 2766 "shutdown-ack"; 2767 2768 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 2769 <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>, 2770 <&gcc GCC_BOOT_ROM_AHB_CLK>, 2771 <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>, 2772 <&gcc GCC_MSS_SNOC_AXI_CLK>, 2773 <&gcc GCC_MSS_MFAB_AXIS_CLK>, 2774 <&gcc GCC_PRNG_AHB_CLK>, 2775 <&rpmhcc RPMH_CXO_CLK>; 2776 clock-names = "iface", "bus", "mem", "gpll0_mss", 2777 "snoc_axi", "mnoc_axi", "prng", "xo"; 2778 2779 qcom,smem-states = <&modem_smp2p_out 0>; 2780 qcom,smem-state-names = "stop"; 2781 2782 resets = <&aoss_reset AOSS_CC_MSS_RESTART>, 2783 <&pdc_reset PDC_MODEM_SYNC_RESET>; 2784 reset-names = "mss_restart", "pdc_reset"; 2785 2786 qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>; 2787 2788 power-domains = <&aoss_qmp 2>, 2789 <&rpmhpd SDM845_CX>, 2790 <&rpmhpd SDM845_MX>, 2791 <&rpmhpd SDM845_MSS>; 2792 power-domain-names = "load_state", "cx", "mx", "mss"; 2793 2794 mba { 2795 memory-region = <&mba_region>; 2796 }; 2797 2798 mpss { 2799 memory-region = <&mpss_region>; 2800 }; 2801 2802 glink-edge { 2803 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 2804 label = "modem"; 2805 qcom,remote-pid = <1>; 2806 mboxes = <&apss_shared 12>; 2807 }; 2808 }; 2809 2810 gpucc: clock-controller@5090000 { 2811 compatible = "qcom,sdm845-gpucc"; 2812 reg = <0 0x05090000 0 0x9000>; 2813 #clock-cells = <1>; 2814 #reset-cells = <1>; 2815 #power-domain-cells = <1>; 2816 clocks = <&rpmhcc RPMH_CXO_CLK>, 2817 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2818 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2819 clock-names = "bi_tcxo", 2820 "gcc_gpu_gpll0_clk_src", 2821 "gcc_gpu_gpll0_div_clk_src"; 2822 }; 2823 2824 stm@6002000 { 2825 compatible = "arm,coresight-stm", "arm,primecell"; 2826 reg = <0 0x06002000 0 0x1000>, 2827 <0 0x16280000 0 0x180000>; 2828 reg-names = "stm-base", "stm-stimulus-base"; 2829 2830 clocks = <&aoss_qmp>; 2831 clock-names = "apb_pclk"; 2832 2833 out-ports { 2834 port { 2835 stm_out: endpoint { 2836 remote-endpoint = 2837 <&funnel0_in7>; 2838 }; 2839 }; 2840 }; 2841 }; 2842 2843 funnel@6041000 { 2844 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2845 reg = <0 0x06041000 0 0x1000>; 2846 2847 clocks = <&aoss_qmp>; 2848 clock-names = "apb_pclk"; 2849 2850 out-ports { 2851 port { 2852 funnel0_out: endpoint { 2853 remote-endpoint = 2854 <&merge_funnel_in0>; 2855 }; 2856 }; 2857 }; 2858 2859 in-ports { 2860 #address-cells = <1>; 2861 #size-cells = <0>; 2862 2863 port@7 { 2864 reg = <7>; 2865 funnel0_in7: endpoint { 2866 remote-endpoint = <&stm_out>; 2867 }; 2868 }; 2869 }; 2870 }; 2871 2872 funnel@6043000 { 2873 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2874 reg = <0 0x06043000 0 0x1000>; 2875 2876 clocks = <&aoss_qmp>; 2877 clock-names = "apb_pclk"; 2878 2879 out-ports { 2880 port { 2881 funnel2_out: endpoint { 2882 remote-endpoint = 2883 <&merge_funnel_in2>; 2884 }; 2885 }; 2886 }; 2887 2888 in-ports { 2889 #address-cells = <1>; 2890 #size-cells = <0>; 2891 2892 port@5 { 2893 reg = <5>; 2894 funnel2_in5: endpoint { 2895 remote-endpoint = 2896 <&apss_merge_funnel_out>; 2897 }; 2898 }; 2899 }; 2900 }; 2901 2902 funnel@6045000 { 2903 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2904 reg = <0 0x06045000 0 0x1000>; 2905 2906 clocks = <&aoss_qmp>; 2907 clock-names = "apb_pclk"; 2908 2909 out-ports { 2910 port { 2911 merge_funnel_out: endpoint { 2912 remote-endpoint = <&etf_in>; 2913 }; 2914 }; 2915 }; 2916 2917 in-ports { 2918 #address-cells = <1>; 2919 #size-cells = <0>; 2920 2921 port@0 { 2922 reg = <0>; 2923 merge_funnel_in0: endpoint { 2924 remote-endpoint = 2925 <&funnel0_out>; 2926 }; 2927 }; 2928 2929 port@2 { 2930 reg = <2>; 2931 merge_funnel_in2: endpoint { 2932 remote-endpoint = 2933 <&funnel2_out>; 2934 }; 2935 }; 2936 }; 2937 }; 2938 2939 replicator@6046000 { 2940 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2941 reg = <0 0x06046000 0 0x1000>; 2942 2943 clocks = <&aoss_qmp>; 2944 clock-names = "apb_pclk"; 2945 2946 out-ports { 2947 port { 2948 replicator_out: endpoint { 2949 remote-endpoint = <&etr_in>; 2950 }; 2951 }; 2952 }; 2953 2954 in-ports { 2955 port { 2956 replicator_in: endpoint { 2957 remote-endpoint = <&etf_out>; 2958 }; 2959 }; 2960 }; 2961 }; 2962 2963 etf@6047000 { 2964 compatible = "arm,coresight-tmc", "arm,primecell"; 2965 reg = <0 0x06047000 0 0x1000>; 2966 2967 clocks = <&aoss_qmp>; 2968 clock-names = "apb_pclk"; 2969 2970 out-ports { 2971 port { 2972 etf_out: endpoint { 2973 remote-endpoint = 2974 <&replicator_in>; 2975 }; 2976 }; 2977 }; 2978 2979 in-ports { 2980 #address-cells = <1>; 2981 #size-cells = <0>; 2982 2983 port@1 { 2984 reg = <1>; 2985 etf_in: endpoint { 2986 remote-endpoint = 2987 <&merge_funnel_out>; 2988 }; 2989 }; 2990 }; 2991 }; 2992 2993 etr@6048000 { 2994 compatible = "arm,coresight-tmc", "arm,primecell"; 2995 reg = <0 0x06048000 0 0x1000>; 2996 2997 clocks = <&aoss_qmp>; 2998 clock-names = "apb_pclk"; 2999 arm,scatter-gather; 3000 3001 in-ports { 3002 port { 3003 etr_in: endpoint { 3004 remote-endpoint = 3005 <&replicator_out>; 3006 }; 3007 }; 3008 }; 3009 }; 3010 3011 etm@7040000 { 3012 compatible = "arm,coresight-etm4x", "arm,primecell"; 3013 reg = <0 0x07040000 0 0x1000>; 3014 3015 cpu = <&CPU0>; 3016 3017 clocks = <&aoss_qmp>; 3018 clock-names = "apb_pclk"; 3019 arm,coresight-loses-context-with-cpu; 3020 3021 out-ports { 3022 port { 3023 etm0_out: endpoint { 3024 remote-endpoint = 3025 <&apss_funnel_in0>; 3026 }; 3027 }; 3028 }; 3029 }; 3030 3031 etm@7140000 { 3032 compatible = "arm,coresight-etm4x", "arm,primecell"; 3033 reg = <0 0x07140000 0 0x1000>; 3034 3035 cpu = <&CPU1>; 3036 3037 clocks = <&aoss_qmp>; 3038 clock-names = "apb_pclk"; 3039 arm,coresight-loses-context-with-cpu; 3040 3041 out-ports { 3042 port { 3043 etm1_out: endpoint { 3044 remote-endpoint = 3045 <&apss_funnel_in1>; 3046 }; 3047 }; 3048 }; 3049 }; 3050 3051 etm@7240000 { 3052 compatible = "arm,coresight-etm4x", "arm,primecell"; 3053 reg = <0 0x07240000 0 0x1000>; 3054 3055 cpu = <&CPU2>; 3056 3057 clocks = <&aoss_qmp>; 3058 clock-names = "apb_pclk"; 3059 arm,coresight-loses-context-with-cpu; 3060 3061 out-ports { 3062 port { 3063 etm2_out: endpoint { 3064 remote-endpoint = 3065 <&apss_funnel_in2>; 3066 }; 3067 }; 3068 }; 3069 }; 3070 3071 etm@7340000 { 3072 compatible = "arm,coresight-etm4x", "arm,primecell"; 3073 reg = <0 0x07340000 0 0x1000>; 3074 3075 cpu = <&CPU3>; 3076 3077 clocks = <&aoss_qmp>; 3078 clock-names = "apb_pclk"; 3079 arm,coresight-loses-context-with-cpu; 3080 3081 out-ports { 3082 port { 3083 etm3_out: endpoint { 3084 remote-endpoint = 3085 <&apss_funnel_in3>; 3086 }; 3087 }; 3088 }; 3089 }; 3090 3091 etm@7440000 { 3092 compatible = "arm,coresight-etm4x", "arm,primecell"; 3093 reg = <0 0x07440000 0 0x1000>; 3094 3095 cpu = <&CPU4>; 3096 3097 clocks = <&aoss_qmp>; 3098 clock-names = "apb_pclk"; 3099 arm,coresight-loses-context-with-cpu; 3100 3101 out-ports { 3102 port { 3103 etm4_out: endpoint { 3104 remote-endpoint = 3105 <&apss_funnel_in4>; 3106 }; 3107 }; 3108 }; 3109 }; 3110 3111 etm@7540000 { 3112 compatible = "arm,coresight-etm4x", "arm,primecell"; 3113 reg = <0 0x07540000 0 0x1000>; 3114 3115 cpu = <&CPU5>; 3116 3117 clocks = <&aoss_qmp>; 3118 clock-names = "apb_pclk"; 3119 arm,coresight-loses-context-with-cpu; 3120 3121 out-ports { 3122 port { 3123 etm5_out: endpoint { 3124 remote-endpoint = 3125 <&apss_funnel_in5>; 3126 }; 3127 }; 3128 }; 3129 }; 3130 3131 etm@7640000 { 3132 compatible = "arm,coresight-etm4x", "arm,primecell"; 3133 reg = <0 0x07640000 0 0x1000>; 3134 3135 cpu = <&CPU6>; 3136 3137 clocks = <&aoss_qmp>; 3138 clock-names = "apb_pclk"; 3139 arm,coresight-loses-context-with-cpu; 3140 3141 out-ports { 3142 port { 3143 etm6_out: endpoint { 3144 remote-endpoint = 3145 <&apss_funnel_in6>; 3146 }; 3147 }; 3148 }; 3149 }; 3150 3151 etm@7740000 { 3152 compatible = "arm,coresight-etm4x", "arm,primecell"; 3153 reg = <0 0x07740000 0 0x1000>; 3154 3155 cpu = <&CPU7>; 3156 3157 clocks = <&aoss_qmp>; 3158 clock-names = "apb_pclk"; 3159 arm,coresight-loses-context-with-cpu; 3160 3161 out-ports { 3162 port { 3163 etm7_out: endpoint { 3164 remote-endpoint = 3165 <&apss_funnel_in7>; 3166 }; 3167 }; 3168 }; 3169 }; 3170 3171 funnel@7800000 { /* APSS Funnel */ 3172 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3173 reg = <0 0x07800000 0 0x1000>; 3174 3175 clocks = <&aoss_qmp>; 3176 clock-names = "apb_pclk"; 3177 3178 out-ports { 3179 port { 3180 apss_funnel_out: endpoint { 3181 remote-endpoint = 3182 <&apss_merge_funnel_in>; 3183 }; 3184 }; 3185 }; 3186 3187 in-ports { 3188 #address-cells = <1>; 3189 #size-cells = <0>; 3190 3191 port@0 { 3192 reg = <0>; 3193 apss_funnel_in0: endpoint { 3194 remote-endpoint = 3195 <&etm0_out>; 3196 }; 3197 }; 3198 3199 port@1 { 3200 reg = <1>; 3201 apss_funnel_in1: endpoint { 3202 remote-endpoint = 3203 <&etm1_out>; 3204 }; 3205 }; 3206 3207 port@2 { 3208 reg = <2>; 3209 apss_funnel_in2: endpoint { 3210 remote-endpoint = 3211 <&etm2_out>; 3212 }; 3213 }; 3214 3215 port@3 { 3216 reg = <3>; 3217 apss_funnel_in3: endpoint { 3218 remote-endpoint = 3219 <&etm3_out>; 3220 }; 3221 }; 3222 3223 port@4 { 3224 reg = <4>; 3225 apss_funnel_in4: endpoint { 3226 remote-endpoint = 3227 <&etm4_out>; 3228 }; 3229 }; 3230 3231 port@5 { 3232 reg = <5>; 3233 apss_funnel_in5: endpoint { 3234 remote-endpoint = 3235 <&etm5_out>; 3236 }; 3237 }; 3238 3239 port@6 { 3240 reg = <6>; 3241 apss_funnel_in6: endpoint { 3242 remote-endpoint = 3243 <&etm6_out>; 3244 }; 3245 }; 3246 3247 port@7 { 3248 reg = <7>; 3249 apss_funnel_in7: endpoint { 3250 remote-endpoint = 3251 <&etm7_out>; 3252 }; 3253 }; 3254 }; 3255 }; 3256 3257 funnel@7810000 { 3258 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3259 reg = <0 0x07810000 0 0x1000>; 3260 3261 clocks = <&aoss_qmp>; 3262 clock-names = "apb_pclk"; 3263 3264 out-ports { 3265 port { 3266 apss_merge_funnel_out: endpoint { 3267 remote-endpoint = 3268 <&funnel2_in5>; 3269 }; 3270 }; 3271 }; 3272 3273 in-ports { 3274 port { 3275 apss_merge_funnel_in: endpoint { 3276 remote-endpoint = 3277 <&apss_funnel_out>; 3278 }; 3279 }; 3280 }; 3281 }; 3282 3283 sdhc_2: sdhci@8804000 { 3284 compatible = "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5"; 3285 reg = <0 0x08804000 0 0x1000>; 3286 3287 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 3288 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 3289 interrupt-names = "hc_irq", "pwr_irq"; 3290 3291 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3292 <&gcc GCC_SDCC2_APPS_CLK>; 3293 clock-names = "iface", "core"; 3294 iommus = <&apps_smmu 0xa0 0xf>; 3295 power-domains = <&rpmhpd SDM845_CX>; 3296 operating-points-v2 = <&sdhc2_opp_table>; 3297 3298 status = "disabled"; 3299 3300 sdhc2_opp_table: sdhc2-opp-table { 3301 compatible = "operating-points-v2"; 3302 3303 opp-9600000 { 3304 opp-hz = /bits/ 64 <9600000>; 3305 required-opps = <&rpmhpd_opp_min_svs>; 3306 }; 3307 3308 opp-19200000 { 3309 opp-hz = /bits/ 64 <19200000>; 3310 required-opps = <&rpmhpd_opp_low_svs>; 3311 }; 3312 3313 opp-100000000 { 3314 opp-hz = /bits/ 64 <100000000>; 3315 required-opps = <&rpmhpd_opp_svs>; 3316 }; 3317 3318 opp-201500000 { 3319 opp-hz = /bits/ 64 <201500000>; 3320 required-opps = <&rpmhpd_opp_svs_l1>; 3321 }; 3322 }; 3323 }; 3324 3325 qspi_opp_table: qspi-opp-table { 3326 compatible = "operating-points-v2"; 3327 3328 opp-19200000 { 3329 opp-hz = /bits/ 64 <19200000>; 3330 required-opps = <&rpmhpd_opp_min_svs>; 3331 }; 3332 3333 opp-100000000 { 3334 opp-hz = /bits/ 64 <100000000>; 3335 required-opps = <&rpmhpd_opp_low_svs>; 3336 }; 3337 3338 opp-150000000 { 3339 opp-hz = /bits/ 64 <150000000>; 3340 required-opps = <&rpmhpd_opp_svs>; 3341 }; 3342 3343 opp-300000000 { 3344 opp-hz = /bits/ 64 <300000000>; 3345 required-opps = <&rpmhpd_opp_nom>; 3346 }; 3347 }; 3348 3349 qspi: spi@88df000 { 3350 compatible = "qcom,sdm845-qspi", "qcom,qspi-v1"; 3351 reg = <0 0x088df000 0 0x600>; 3352 #address-cells = <1>; 3353 #size-cells = <0>; 3354 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 3355 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 3356 <&gcc GCC_QSPI_CORE_CLK>; 3357 clock-names = "iface", "core"; 3358 power-domains = <&rpmhpd SDM845_CX>; 3359 operating-points-v2 = <&qspi_opp_table>; 3360 status = "disabled"; 3361 }; 3362 3363 slim: slim@171c0000 { 3364 compatible = "qcom,slim-ngd-v2.1.0"; 3365 reg = <0 0x171c0000 0 0x2c000>; 3366 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 3367 3368 qcom,apps-ch-pipes = <0x780000>; 3369 qcom,ea-pc = <0x270>; 3370 status = "okay"; 3371 dmas = <&slimbam 3>, <&slimbam 4>, 3372 <&slimbam 5>, <&slimbam 6>; 3373 dma-names = "rx", "tx", "tx2", "rx2"; 3374 3375 iommus = <&apps_smmu 0x1806 0x0>; 3376 #address-cells = <1>; 3377 #size-cells = <0>; 3378 3379 ngd@1 { 3380 reg = <1>; 3381 #address-cells = <2>; 3382 #size-cells = <0>; 3383 3384 wcd9340_ifd: ifd@0{ 3385 compatible = "slim217,250"; 3386 reg = <0 0>; 3387 }; 3388 3389 wcd9340: codec@1{ 3390 compatible = "slim217,250"; 3391 reg = <1 0>; 3392 slim-ifc-dev = <&wcd9340_ifd>; 3393 3394 #sound-dai-cells = <1>; 3395 3396 interrupts-extended = <&tlmm 54 IRQ_TYPE_LEVEL_HIGH>; 3397 interrupt-controller; 3398 #interrupt-cells = <1>; 3399 3400 #clock-cells = <0>; 3401 clock-frequency = <9600000>; 3402 clock-output-names = "mclk"; 3403 qcom,micbias1-millivolt = <1800>; 3404 qcom,micbias2-millivolt = <1800>; 3405 qcom,micbias3-millivolt = <1800>; 3406 qcom,micbias4-millivolt = <1800>; 3407 3408 #address-cells = <1>; 3409 #size-cells = <1>; 3410 3411 wcdgpio: gpio-controller@42 { 3412 compatible = "qcom,wcd9340-gpio"; 3413 gpio-controller; 3414 #gpio-cells = <2>; 3415 reg = <0x42 0x2>; 3416 }; 3417 3418 swm: swm@c85 { 3419 compatible = "qcom,soundwire-v1.3.0"; 3420 reg = <0xc85 0x40>; 3421 interrupts-extended = <&wcd9340 20>; 3422 3423 qcom,dout-ports = <6>; 3424 qcom,din-ports = <2>; 3425 qcom,ports-sinterval-low =/bits/ 8 <0x07 0x1F 0x3F 0x7 0x1F 0x3F 0x0F 0x0F>; 3426 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0C 0x6 0x12 0x0D 0x07 0x0A >; 3427 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x1F 0x00 0x00 0x1F 0x00 0x00>; 3428 3429 #sound-dai-cells = <1>; 3430 clocks = <&wcd9340>; 3431 clock-names = "iface"; 3432 #address-cells = <2>; 3433 #size-cells = <0>; 3434 3435 3436 }; 3437 }; 3438 }; 3439 }; 3440 3441 sound: sound { 3442 }; 3443 3444 usb_1_hsphy: phy@88e2000 { 3445 compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy"; 3446 reg = <0 0x088e2000 0 0x400>; 3447 status = "disabled"; 3448 #phy-cells = <0>; 3449 3450 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 3451 <&rpmhcc RPMH_CXO_CLK>; 3452 clock-names = "cfg_ahb", "ref"; 3453 3454 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3455 3456 nvmem-cells = <&qusb2p_hstx_trim>; 3457 }; 3458 3459 usb_2_hsphy: phy@88e3000 { 3460 compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy"; 3461 reg = <0 0x088e3000 0 0x400>; 3462 status = "disabled"; 3463 #phy-cells = <0>; 3464 3465 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 3466 <&rpmhcc RPMH_CXO_CLK>; 3467 clock-names = "cfg_ahb", "ref"; 3468 3469 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3470 3471 nvmem-cells = <&qusb2s_hstx_trim>; 3472 }; 3473 3474 usb_1_qmpphy: phy@88e9000 { 3475 compatible = "qcom,sdm845-qmp-usb3-phy"; 3476 reg = <0 0x088e9000 0 0x18c>, 3477 <0 0x088e8000 0 0x10>; 3478 reg-names = "reg-base", "dp_com"; 3479 status = "disabled"; 3480 #clock-cells = <1>; 3481 #address-cells = <2>; 3482 #size-cells = <2>; 3483 ranges; 3484 3485 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3486 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 3487 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 3488 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 3489 clock-names = "aux", "cfg_ahb", "ref", "com_aux"; 3490 3491 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 3492 <&gcc GCC_USB3_PHY_PRIM_BCR>; 3493 reset-names = "phy", "common"; 3494 3495 usb_1_ssphy: lanes@88e9200 { 3496 reg = <0 0x088e9200 0 0x128>, 3497 <0 0x088e9400 0 0x200>, 3498 <0 0x088e9c00 0 0x218>, 3499 <0 0x088e9600 0 0x128>, 3500 <0 0x088e9800 0 0x200>, 3501 <0 0x088e9a00 0 0x100>; 3502 #phy-cells = <0>; 3503 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3504 clock-names = "pipe0"; 3505 clock-output-names = "usb3_phy_pipe_clk_src"; 3506 }; 3507 }; 3508 3509 usb_2_qmpphy: phy@88eb000 { 3510 compatible = "qcom,sdm845-qmp-usb3-uni-phy"; 3511 reg = <0 0x088eb000 0 0x18c>; 3512 status = "disabled"; 3513 #clock-cells = <1>; 3514 #address-cells = <2>; 3515 #size-cells = <2>; 3516 ranges; 3517 3518 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 3519 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 3520 <&gcc GCC_USB3_SEC_CLKREF_CLK>, 3521 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; 3522 clock-names = "aux", "cfg_ahb", "ref", "com_aux"; 3523 3524 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, 3525 <&gcc GCC_USB3_PHY_SEC_BCR>; 3526 reset-names = "phy", "common"; 3527 3528 usb_2_ssphy: lane@88eb200 { 3529 reg = <0 0x088eb200 0 0x128>, 3530 <0 0x088eb400 0 0x1fc>, 3531 <0 0x088eb800 0 0x218>, 3532 <0 0x088eb600 0 0x70>; 3533 #phy-cells = <0>; 3534 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 3535 clock-names = "pipe0"; 3536 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 3537 }; 3538 }; 3539 3540 usb_1: usb@a6f8800 { 3541 compatible = "qcom,sdm845-dwc3", "qcom,dwc3"; 3542 reg = <0 0x0a6f8800 0 0x400>; 3543 status = "disabled"; 3544 #address-cells = <2>; 3545 #size-cells = <2>; 3546 ranges; 3547 dma-ranges; 3548 3549 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3550 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3551 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3552 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3553 <&gcc GCC_USB30_PRIM_SLEEP_CLK>; 3554 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 3555 "sleep"; 3556 3557 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3558 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3559 assigned-clock-rates = <19200000>, <150000000>; 3560 3561 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 3562 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>, 3563 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>, 3564 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>; 3565 interrupt-names = "hs_phy_irq", "ss_phy_irq", 3566 "dm_hs_phy_irq", "dp_hs_phy_irq"; 3567 3568 power-domains = <&gcc USB30_PRIM_GDSC>; 3569 3570 resets = <&gcc GCC_USB30_PRIM_BCR>; 3571 3572 interconnects = <&aggre2_noc MASTER_USB3_0 0 &mem_noc SLAVE_EBI1 0>, 3573 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; 3574 interconnect-names = "usb-ddr", "apps-usb"; 3575 3576 usb_1_dwc3: dwc3@a600000 { 3577 compatible = "snps,dwc3"; 3578 reg = <0 0x0a600000 0 0xcd00>; 3579 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 3580 iommus = <&apps_smmu 0x740 0>; 3581 snps,dis_u2_susphy_quirk; 3582 snps,dis_enblslpm_quirk; 3583 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 3584 phy-names = "usb2-phy", "usb3-phy"; 3585 }; 3586 }; 3587 3588 usb_2: usb@a8f8800 { 3589 compatible = "qcom,sdm845-dwc3", "qcom,dwc3"; 3590 reg = <0 0x0a8f8800 0 0x400>; 3591 status = "disabled"; 3592 #address-cells = <2>; 3593 #size-cells = <2>; 3594 ranges; 3595 dma-ranges; 3596 3597 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 3598 <&gcc GCC_USB30_SEC_MASTER_CLK>, 3599 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 3600 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3601 <&gcc GCC_USB30_SEC_SLEEP_CLK>; 3602 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 3603 "sleep"; 3604 3605 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3606 <&gcc GCC_USB30_SEC_MASTER_CLK>; 3607 assigned-clock-rates = <19200000>, <150000000>; 3608 3609 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 3610 <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>, 3611 <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>, 3612 <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>; 3613 interrupt-names = "hs_phy_irq", "ss_phy_irq", 3614 "dm_hs_phy_irq", "dp_hs_phy_irq"; 3615 3616 power-domains = <&gcc USB30_SEC_GDSC>; 3617 3618 resets = <&gcc GCC_USB30_SEC_BCR>; 3619 3620 interconnects = <&aggre2_noc MASTER_USB3_1 0 &mem_noc SLAVE_EBI1 0>, 3621 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>; 3622 interconnect-names = "usb-ddr", "apps-usb"; 3623 3624 usb_2_dwc3: dwc3@a800000 { 3625 compatible = "snps,dwc3"; 3626 reg = <0 0x0a800000 0 0xcd00>; 3627 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 3628 iommus = <&apps_smmu 0x760 0>; 3629 snps,dis_u2_susphy_quirk; 3630 snps,dis_enblslpm_quirk; 3631 phys = <&usb_2_hsphy>, <&usb_2_ssphy>; 3632 phy-names = "usb2-phy", "usb3-phy"; 3633 }; 3634 }; 3635 3636 venus: video-codec@aa00000 { 3637 compatible = "qcom,sdm845-venus-v2"; 3638 reg = <0 0x0aa00000 0 0xff000>; 3639 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 3640 power-domains = <&videocc VENUS_GDSC>, 3641 <&videocc VCODEC0_GDSC>, 3642 <&videocc VCODEC1_GDSC>, 3643 <&rpmhpd SDM845_CX>; 3644 power-domain-names = "venus", "vcodec0", "vcodec1", "cx"; 3645 operating-points-v2 = <&venus_opp_table>; 3646 clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>, 3647 <&videocc VIDEO_CC_VENUS_AHB_CLK>, 3648 <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>, 3649 <&videocc VIDEO_CC_VCODEC0_CORE_CLK>, 3650 <&videocc VIDEO_CC_VCODEC0_AXI_CLK>, 3651 <&videocc VIDEO_CC_VCODEC1_CORE_CLK>, 3652 <&videocc VIDEO_CC_VCODEC1_AXI_CLK>; 3653 clock-names = "core", "iface", "bus", 3654 "vcodec0_core", "vcodec0_bus", 3655 "vcodec1_core", "vcodec1_bus"; 3656 iommus = <&apps_smmu 0x10a0 0x8>, 3657 <&apps_smmu 0x10b0 0x0>; 3658 memory-region = <&venus_mem>; 3659 3660 video-core0 { 3661 compatible = "venus-decoder"; 3662 }; 3663 3664 video-core1 { 3665 compatible = "venus-encoder"; 3666 }; 3667 3668 venus_opp_table: venus-opp-table { 3669 compatible = "operating-points-v2"; 3670 3671 opp-100000000 { 3672 opp-hz = /bits/ 64 <100000000>; 3673 required-opps = <&rpmhpd_opp_min_svs>; 3674 }; 3675 3676 opp-200000000 { 3677 opp-hz = /bits/ 64 <200000000>; 3678 required-opps = <&rpmhpd_opp_low_svs>; 3679 }; 3680 3681 opp-320000000 { 3682 opp-hz = /bits/ 64 <320000000>; 3683 required-opps = <&rpmhpd_opp_svs>; 3684 }; 3685 3686 opp-380000000 { 3687 opp-hz = /bits/ 64 <380000000>; 3688 required-opps = <&rpmhpd_opp_svs_l1>; 3689 }; 3690 3691 opp-444000000 { 3692 opp-hz = /bits/ 64 <444000000>; 3693 required-opps = <&rpmhpd_opp_nom>; 3694 }; 3695 3696 opp-533000097 { 3697 opp-hz = /bits/ 64 <533000097>; 3698 required-opps = <&rpmhpd_opp_turbo>; 3699 }; 3700 }; 3701 }; 3702 3703 videocc: clock-controller@ab00000 { 3704 compatible = "qcom,sdm845-videocc"; 3705 reg = <0 0x0ab00000 0 0x10000>; 3706 clocks = <&rpmhcc RPMH_CXO_CLK>; 3707 clock-names = "bi_tcxo"; 3708 #clock-cells = <1>; 3709 #power-domain-cells = <1>; 3710 #reset-cells = <1>; 3711 }; 3712 3713 cci: cci@ac4a000 { 3714 compatible = "qcom,sdm845-cci"; 3715 #address-cells = <1>; 3716 #size-cells = <0>; 3717 3718 reg = <0 0x0ac4a000 0 0x4000>; 3719 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>; 3720 power-domains = <&clock_camcc TITAN_TOP_GDSC>; 3721 3722 clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, 3723 <&clock_camcc CAM_CC_SOC_AHB_CLK>, 3724 <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, 3725 <&clock_camcc CAM_CC_CPAS_AHB_CLK>, 3726 <&clock_camcc CAM_CC_CCI_CLK>, 3727 <&clock_camcc CAM_CC_CCI_CLK_SRC>; 3728 clock-names = "camnoc_axi", 3729 "soc_ahb", 3730 "slow_ahb_src", 3731 "cpas_ahb", 3732 "cci", 3733 "cci_src"; 3734 3735 assigned-clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, 3736 <&clock_camcc CAM_CC_CCI_CLK>; 3737 assigned-clock-rates = <80000000>, <37500000>; 3738 3739 pinctrl-names = "default", "sleep"; 3740 pinctrl-0 = <&cci0_default &cci1_default>; 3741 pinctrl-1 = <&cci0_sleep &cci1_sleep>; 3742 3743 status = "disabled"; 3744 3745 cci_i2c0: i2c-bus@0 { 3746 reg = <0>; 3747 clock-frequency = <1000000>; 3748 #address-cells = <1>; 3749 #size-cells = <0>; 3750 }; 3751 3752 cci_i2c1: i2c-bus@1 { 3753 reg = <1>; 3754 clock-frequency = <1000000>; 3755 #address-cells = <1>; 3756 #size-cells = <0>; 3757 }; 3758 }; 3759 3760 clock_camcc: clock-controller@ad00000 { 3761 compatible = "qcom,sdm845-camcc"; 3762 reg = <0 0x0ad00000 0 0x10000>; 3763 #clock-cells = <1>; 3764 #reset-cells = <1>; 3765 #power-domain-cells = <1>; 3766 }; 3767 3768 dsi_opp_table: dsi-opp-table { 3769 compatible = "operating-points-v2"; 3770 3771 opp-19200000 { 3772 opp-hz = /bits/ 64 <19200000>; 3773 required-opps = <&rpmhpd_opp_min_svs>; 3774 }; 3775 3776 opp-180000000 { 3777 opp-hz = /bits/ 64 <180000000>; 3778 required-opps = <&rpmhpd_opp_low_svs>; 3779 }; 3780 3781 opp-275000000 { 3782 opp-hz = /bits/ 64 <275000000>; 3783 required-opps = <&rpmhpd_opp_svs>; 3784 }; 3785 3786 opp-328580000 { 3787 opp-hz = /bits/ 64 <328580000>; 3788 required-opps = <&rpmhpd_opp_svs_l1>; 3789 }; 3790 3791 opp-358000000 { 3792 opp-hz = /bits/ 64 <358000000>; 3793 required-opps = <&rpmhpd_opp_nom>; 3794 }; 3795 }; 3796 3797 mdss: mdss@ae00000 { 3798 compatible = "qcom,sdm845-mdss"; 3799 reg = <0 0x0ae00000 0 0x1000>; 3800 reg-names = "mdss"; 3801 3802 power-domains = <&dispcc MDSS_GDSC>; 3803 3804 clocks = <&gcc GCC_DISP_AHB_CLK>, 3805 <&gcc GCC_DISP_AXI_CLK>, 3806 <&dispcc DISP_CC_MDSS_MDP_CLK>; 3807 clock-names = "iface", "bus", "core"; 3808 3809 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; 3810 assigned-clock-rates = <300000000>; 3811 3812 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 3813 interrupt-controller; 3814 #interrupt-cells = <1>; 3815 3816 interconnects = <&mmss_noc MASTER_MDP0 0 &mem_noc SLAVE_EBI1 0>, 3817 <&mmss_noc MASTER_MDP1 0 &mem_noc SLAVE_EBI1 0>; 3818 interconnect-names = "mdp0-mem", "mdp1-mem"; 3819 3820 iommus = <&apps_smmu 0x880 0x8>, 3821 <&apps_smmu 0xc80 0x8>; 3822 3823 status = "disabled"; 3824 3825 #address-cells = <2>; 3826 #size-cells = <2>; 3827 ranges; 3828 3829 mdss_mdp: mdp@ae01000 { 3830 compatible = "qcom,sdm845-dpu"; 3831 reg = <0 0x0ae01000 0 0x8f000>, 3832 <0 0x0aeb0000 0 0x2008>; 3833 reg-names = "mdp", "vbif"; 3834 3835 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3836 <&dispcc DISP_CC_MDSS_AXI_CLK>, 3837 <&dispcc DISP_CC_MDSS_MDP_CLK>, 3838 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3839 clock-names = "iface", "bus", "core", "vsync"; 3840 3841 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, 3842 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3843 assigned-clock-rates = <300000000>, 3844 <19200000>; 3845 operating-points-v2 = <&mdp_opp_table>; 3846 power-domains = <&rpmhpd SDM845_CX>; 3847 3848 interrupt-parent = <&mdss>; 3849 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; 3850 3851 status = "disabled"; 3852 3853 ports { 3854 #address-cells = <1>; 3855 #size-cells = <0>; 3856 3857 port@0 { 3858 reg = <0>; 3859 dpu_intf1_out: endpoint { 3860 remote-endpoint = <&dsi0_in>; 3861 }; 3862 }; 3863 3864 port@1 { 3865 reg = <1>; 3866 dpu_intf2_out: endpoint { 3867 remote-endpoint = <&dsi1_in>; 3868 }; 3869 }; 3870 }; 3871 3872 mdp_opp_table: mdp-opp-table { 3873 compatible = "operating-points-v2"; 3874 3875 opp-19200000 { 3876 opp-hz = /bits/ 64 <19200000>; 3877 required-opps = <&rpmhpd_opp_min_svs>; 3878 }; 3879 3880 opp-171428571 { 3881 opp-hz = /bits/ 64 <171428571>; 3882 required-opps = <&rpmhpd_opp_low_svs>; 3883 }; 3884 3885 opp-344000000 { 3886 opp-hz = /bits/ 64 <344000000>; 3887 required-opps = <&rpmhpd_opp_svs_l1>; 3888 }; 3889 3890 opp-430000000 { 3891 opp-hz = /bits/ 64 <430000000>; 3892 required-opps = <&rpmhpd_opp_nom>; 3893 }; 3894 }; 3895 }; 3896 3897 dsi0: dsi@ae94000 { 3898 compatible = "qcom,mdss-dsi-ctrl"; 3899 reg = <0 0x0ae94000 0 0x400>; 3900 reg-names = "dsi_ctrl"; 3901 3902 interrupt-parent = <&mdss>; 3903 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; 3904 3905 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 3906 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 3907 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 3908 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 3909 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3910 <&dispcc DISP_CC_MDSS_AXI_CLK>; 3911 clock-names = "byte", 3912 "byte_intf", 3913 "pixel", 3914 "core", 3915 "iface", 3916 "bus"; 3917 operating-points-v2 = <&dsi_opp_table>; 3918 power-domains = <&rpmhpd SDM845_CX>; 3919 3920 phys = <&dsi0_phy>; 3921 phy-names = "dsi"; 3922 3923 status = "disabled"; 3924 3925 ports { 3926 #address-cells = <1>; 3927 #size-cells = <0>; 3928 3929 port@0 { 3930 reg = <0>; 3931 dsi0_in: endpoint { 3932 remote-endpoint = <&dpu_intf1_out>; 3933 }; 3934 }; 3935 3936 port@1 { 3937 reg = <1>; 3938 dsi0_out: endpoint { 3939 }; 3940 }; 3941 }; 3942 }; 3943 3944 dsi0_phy: dsi-phy@ae94400 { 3945 compatible = "qcom,dsi-phy-10nm"; 3946 reg = <0 0x0ae94400 0 0x200>, 3947 <0 0x0ae94600 0 0x280>, 3948 <0 0x0ae94a00 0 0x1e0>; 3949 reg-names = "dsi_phy", 3950 "dsi_phy_lane", 3951 "dsi_pll"; 3952 3953 #clock-cells = <1>; 3954 #phy-cells = <0>; 3955 3956 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3957 <&rpmhcc RPMH_CXO_CLK>; 3958 clock-names = "iface", "ref"; 3959 3960 status = "disabled"; 3961 }; 3962 3963 dsi1: dsi@ae96000 { 3964 compatible = "qcom,mdss-dsi-ctrl"; 3965 reg = <0 0x0ae96000 0 0x400>; 3966 reg-names = "dsi_ctrl"; 3967 3968 interrupt-parent = <&mdss>; 3969 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; 3970 3971 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 3972 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 3973 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 3974 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 3975 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3976 <&dispcc DISP_CC_MDSS_AXI_CLK>; 3977 clock-names = "byte", 3978 "byte_intf", 3979 "pixel", 3980 "core", 3981 "iface", 3982 "bus"; 3983 operating-points-v2 = <&dsi_opp_table>; 3984 power-domains = <&rpmhpd SDM845_CX>; 3985 3986 phys = <&dsi1_phy>; 3987 phy-names = "dsi"; 3988 3989 status = "disabled"; 3990 3991 ports { 3992 #address-cells = <1>; 3993 #size-cells = <0>; 3994 3995 port@0 { 3996 reg = <0>; 3997 dsi1_in: endpoint { 3998 remote-endpoint = <&dpu_intf2_out>; 3999 }; 4000 }; 4001 4002 port@1 { 4003 reg = <1>; 4004 dsi1_out: endpoint { 4005 }; 4006 }; 4007 }; 4008 }; 4009 4010 dsi1_phy: dsi-phy@ae96400 { 4011 compatible = "qcom,dsi-phy-10nm"; 4012 reg = <0 0x0ae96400 0 0x200>, 4013 <0 0x0ae96600 0 0x280>, 4014 <0 0x0ae96a00 0 0x10e>; 4015 reg-names = "dsi_phy", 4016 "dsi_phy_lane", 4017 "dsi_pll"; 4018 4019 #clock-cells = <1>; 4020 #phy-cells = <0>; 4021 4022 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4023 <&rpmhcc RPMH_CXO_CLK>; 4024 clock-names = "iface", "ref"; 4025 4026 status = "disabled"; 4027 }; 4028 }; 4029 4030 gpu: gpu@5000000 { 4031 compatible = "qcom,adreno-630.2", "qcom,adreno"; 4032 #stream-id-cells = <16>; 4033 4034 reg = <0 0x5000000 0 0x40000>, <0 0x509e000 0 0x10>; 4035 reg-names = "kgsl_3d0_reg_memory", "cx_mem"; 4036 4037 /* 4038 * Look ma, no clocks! The GPU clocks and power are 4039 * controlled entirely by the GMU 4040 */ 4041 4042 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 4043 4044 iommus = <&adreno_smmu 0>; 4045 4046 operating-points-v2 = <&gpu_opp_table>; 4047 4048 qcom,gmu = <&gmu>; 4049 4050 interconnects = <&mem_noc MASTER_GFX3D 0 &mem_noc SLAVE_EBI1 0>; 4051 interconnect-names = "gfx-mem"; 4052 4053 gpu_opp_table: opp-table { 4054 compatible = "operating-points-v2"; 4055 4056 opp-710000000 { 4057 opp-hz = /bits/ 64 <710000000>; 4058 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4059 opp-peak-kBps = <7216000>; 4060 }; 4061 4062 opp-675000000 { 4063 opp-hz = /bits/ 64 <675000000>; 4064 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4065 opp-peak-kBps = <7216000>; 4066 }; 4067 4068 opp-596000000 { 4069 opp-hz = /bits/ 64 <596000000>; 4070 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4071 opp-peak-kBps = <6220000>; 4072 }; 4073 4074 opp-520000000 { 4075 opp-hz = /bits/ 64 <520000000>; 4076 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4077 opp-peak-kBps = <6220000>; 4078 }; 4079 4080 opp-414000000 { 4081 opp-hz = /bits/ 64 <414000000>; 4082 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4083 opp-peak-kBps = <4068000>; 4084 }; 4085 4086 opp-342000000 { 4087 opp-hz = /bits/ 64 <342000000>; 4088 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4089 opp-peak-kBps = <2724000>; 4090 }; 4091 4092 opp-257000000 { 4093 opp-hz = /bits/ 64 <257000000>; 4094 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4095 opp-peak-kBps = <1648000>; 4096 }; 4097 }; 4098 }; 4099 4100 adreno_smmu: iommu@5040000 { 4101 compatible = "qcom,sdm845-smmu-v2", "qcom,smmu-v2"; 4102 reg = <0 0x5040000 0 0x10000>; 4103 #iommu-cells = <1>; 4104 #global-interrupts = <2>; 4105 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 4106 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 4107 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, 4108 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, 4109 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>, 4110 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>, 4111 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>, 4112 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>, 4113 <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>, 4114 <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>; 4115 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 4116 <&gcc GCC_GPU_CFG_AHB_CLK>; 4117 clock-names = "bus", "iface"; 4118 4119 power-domains = <&gpucc GPU_CX_GDSC>; 4120 }; 4121 4122 gmu: gmu@506a000 { 4123 compatible="qcom,adreno-gmu-630.2", "qcom,adreno-gmu"; 4124 4125 reg = <0 0x506a000 0 0x30000>, 4126 <0 0xb280000 0 0x10000>, 4127 <0 0xb480000 0 0x10000>; 4128 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; 4129 4130 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 4131 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 4132 interrupt-names = "hfi", "gmu"; 4133 4134 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 4135 <&gpucc GPU_CC_CXO_CLK>, 4136 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 4137 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 4138 clock-names = "gmu", "cxo", "axi", "memnoc"; 4139 4140 power-domains = <&gpucc GPU_CX_GDSC>, 4141 <&gpucc GPU_GX_GDSC>; 4142 power-domain-names = "cx", "gx"; 4143 4144 iommus = <&adreno_smmu 5>; 4145 4146 operating-points-v2 = <&gmu_opp_table>; 4147 4148 gmu_opp_table: opp-table { 4149 compatible = "operating-points-v2"; 4150 4151 opp-400000000 { 4152 opp-hz = /bits/ 64 <400000000>; 4153 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4154 }; 4155 4156 opp-200000000 { 4157 opp-hz = /bits/ 64 <200000000>; 4158 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 4159 }; 4160 }; 4161 }; 4162 4163 dispcc: clock-controller@af00000 { 4164 compatible = "qcom,sdm845-dispcc"; 4165 reg = <0 0x0af00000 0 0x10000>; 4166 clocks = <&rpmhcc RPMH_CXO_CLK>, 4167 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 4168 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, 4169 <&dsi0_phy 0>, 4170 <&dsi0_phy 1>, 4171 <&dsi1_phy 0>, 4172 <&dsi1_phy 1>, 4173 <0>, 4174 <0>; 4175 clock-names = "bi_tcxo", 4176 "gcc_disp_gpll0_clk_src", 4177 "gcc_disp_gpll0_div_clk_src", 4178 "dsi0_phy_pll_out_byteclk", 4179 "dsi0_phy_pll_out_dsiclk", 4180 "dsi1_phy_pll_out_byteclk", 4181 "dsi1_phy_pll_out_dsiclk", 4182 "dp_link_clk_divsel_ten", 4183 "dp_vco_divided_clk_src_mux"; 4184 #clock-cells = <1>; 4185 #reset-cells = <1>; 4186 #power-domain-cells = <1>; 4187 }; 4188 4189 pdc_intc: interrupt-controller@b220000 { 4190 compatible = "qcom,sdm845-pdc", "qcom,pdc"; 4191 reg = <0 0x0b220000 0 0x30000>; 4192 qcom,pdc-ranges = <0 480 94>, <94 609 15>, <115 630 7>; 4193 #interrupt-cells = <2>; 4194 interrupt-parent = <&intc>; 4195 interrupt-controller; 4196 }; 4197 4198 pdc_reset: reset-controller@b2e0000 { 4199 compatible = "qcom,sdm845-pdc-global"; 4200 reg = <0 0x0b2e0000 0 0x20000>; 4201 #reset-cells = <1>; 4202 }; 4203 4204 tsens0: thermal-sensor@c263000 { 4205 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; 4206 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 4207 <0 0x0c222000 0 0x1ff>; /* SROT */ 4208 #qcom,sensors = <13>; 4209 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 4210 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 4211 interrupt-names = "uplow", "critical"; 4212 #thermal-sensor-cells = <1>; 4213 }; 4214 4215 tsens1: thermal-sensor@c265000 { 4216 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; 4217 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 4218 <0 0x0c223000 0 0x1ff>; /* SROT */ 4219 #qcom,sensors = <8>; 4220 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 4221 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 4222 interrupt-names = "uplow", "critical"; 4223 #thermal-sensor-cells = <1>; 4224 }; 4225 4226 aoss_reset: reset-controller@c2a0000 { 4227 compatible = "qcom,sdm845-aoss-cc"; 4228 reg = <0 0x0c2a0000 0 0x31000>; 4229 #reset-cells = <1>; 4230 }; 4231 4232 aoss_qmp: qmp@c300000 { 4233 compatible = "qcom,sdm845-aoss-qmp"; 4234 reg = <0 0x0c300000 0 0x100000>; 4235 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; 4236 mboxes = <&apss_shared 0>; 4237 4238 #clock-cells = <0>; 4239 #power-domain-cells = <1>; 4240 4241 cx_cdev: cx { 4242 #cooling-cells = <2>; 4243 }; 4244 4245 ebi_cdev: ebi { 4246 #cooling-cells = <2>; 4247 }; 4248 }; 4249 4250 spmi_bus: spmi@c440000 { 4251 compatible = "qcom,spmi-pmic-arb"; 4252 reg = <0 0x0c440000 0 0x1100>, 4253 <0 0x0c600000 0 0x2000000>, 4254 <0 0x0e600000 0 0x100000>, 4255 <0 0x0e700000 0 0xa0000>, 4256 <0 0x0c40a000 0 0x26000>; 4257 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 4258 interrupt-names = "periph_irq"; 4259 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>; 4260 qcom,ee = <0>; 4261 qcom,channel = <0>; 4262 #address-cells = <2>; 4263 #size-cells = <0>; 4264 interrupt-controller; 4265 #interrupt-cells = <4>; 4266 cell-index = <0>; 4267 }; 4268 4269 imem@146bf000 { 4270 compatible = "simple-mfd"; 4271 reg = <0 0x146bf000 0 0x1000>; 4272 4273 #address-cells = <1>; 4274 #size-cells = <1>; 4275 4276 ranges = <0 0 0x146bf000 0x1000>; 4277 4278 pil-reloc@94c { 4279 compatible = "qcom,pil-reloc-info"; 4280 reg = <0x94c 0xc8>; 4281 }; 4282 }; 4283 4284 apps_smmu: iommu@15000000 { 4285 compatible = "qcom,sdm845-smmu-500", "arm,mmu-500"; 4286 reg = <0 0x15000000 0 0x80000>; 4287 #iommu-cells = <2>; 4288 #global-interrupts = <1>; 4289 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 4290 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 4291 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 4292 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 4293 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 4294 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 4295 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 4296 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 4297 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 4298 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 4299 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 4300 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 4301 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 4302 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 4303 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 4304 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 4305 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 4306 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 4307 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 4308 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 4309 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 4310 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 4311 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 4312 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 4313 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 4314 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 4315 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 4316 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 4317 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 4318 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 4319 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 4320 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 4321 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 4322 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 4323 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 4324 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 4325 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 4326 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 4327 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 4328 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 4329 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 4330 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 4331 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 4332 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 4333 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 4334 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 4335 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 4336 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 4337 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 4338 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 4339 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 4340 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 4341 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 4342 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 4343 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 4344 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 4345 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 4346 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 4347 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 4348 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 4349 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 4350 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 4351 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 4352 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 4353 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>; 4354 }; 4355 4356 lpasscc: clock-controller@17014000 { 4357 compatible = "qcom,sdm845-lpasscc"; 4358 reg = <0 0x17014000 0 0x1f004>, <0 0x17300000 0 0x200>; 4359 reg-names = "cc", "qdsp6ss"; 4360 #clock-cells = <1>; 4361 status = "disabled"; 4362 }; 4363 4364 gladiator_noc: interconnect@17900000 { 4365 compatible = "qcom,sdm845-gladiator-noc"; 4366 reg = <0 0x17900000 0 0xd080>; 4367 #interconnect-cells = <2>; 4368 qcom,bcm-voters = <&apps_bcm_voter>; 4369 }; 4370 4371 watchdog@17980000 { 4372 compatible = "qcom,apss-wdt-sdm845", "qcom,kpss-wdt"; 4373 reg = <0 0x17980000 0 0x1000>; 4374 clocks = <&sleep_clk>; 4375 }; 4376 4377 apss_shared: mailbox@17990000 { 4378 compatible = "qcom,sdm845-apss-shared"; 4379 reg = <0 0x17990000 0 0x1000>; 4380 #mbox-cells = <1>; 4381 }; 4382 4383 apps_rsc: rsc@179c0000 { 4384 label = "apps_rsc"; 4385 compatible = "qcom,rpmh-rsc"; 4386 reg = <0 0x179c0000 0 0x10000>, 4387 <0 0x179d0000 0 0x10000>, 4388 <0 0x179e0000 0 0x10000>; 4389 reg-names = "drv-0", "drv-1", "drv-2"; 4390 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 4391 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 4392 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 4393 qcom,tcs-offset = <0xd00>; 4394 qcom,drv-id = <2>; 4395 qcom,tcs-config = <ACTIVE_TCS 2>, 4396 <SLEEP_TCS 3>, 4397 <WAKE_TCS 3>, 4398 <CONTROL_TCS 1>; 4399 4400 apps_bcm_voter: bcm-voter { 4401 compatible = "qcom,bcm-voter"; 4402 }; 4403 4404 rpmhcc: clock-controller { 4405 compatible = "qcom,sdm845-rpmh-clk"; 4406 #clock-cells = <1>; 4407 clock-names = "xo"; 4408 clocks = <&xo_board>; 4409 }; 4410 4411 rpmhpd: power-controller { 4412 compatible = "qcom,sdm845-rpmhpd"; 4413 #power-domain-cells = <1>; 4414 operating-points-v2 = <&rpmhpd_opp_table>; 4415 4416 rpmhpd_opp_table: opp-table { 4417 compatible = "operating-points-v2"; 4418 4419 rpmhpd_opp_ret: opp1 { 4420 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 4421 }; 4422 4423 rpmhpd_opp_min_svs: opp2 { 4424 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 4425 }; 4426 4427 rpmhpd_opp_low_svs: opp3 { 4428 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4429 }; 4430 4431 rpmhpd_opp_svs: opp4 { 4432 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4433 }; 4434 4435 rpmhpd_opp_svs_l1: opp5 { 4436 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4437 }; 4438 4439 rpmhpd_opp_nom: opp6 { 4440 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4441 }; 4442 4443 rpmhpd_opp_nom_l1: opp7 { 4444 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4445 }; 4446 4447 rpmhpd_opp_nom_l2: opp8 { 4448 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 4449 }; 4450 4451 rpmhpd_opp_turbo: opp9 { 4452 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4453 }; 4454 4455 rpmhpd_opp_turbo_l1: opp10 { 4456 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4457 }; 4458 }; 4459 }; 4460 }; 4461 4462 intc: interrupt-controller@17a00000 { 4463 compatible = "arm,gic-v3"; 4464 #address-cells = <2>; 4465 #size-cells = <2>; 4466 ranges; 4467 #interrupt-cells = <3>; 4468 interrupt-controller; 4469 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 4470 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 4471 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 4472 4473 msi-controller@17a40000 { 4474 compatible = "arm,gic-v3-its"; 4475 msi-controller; 4476 #msi-cells = <1>; 4477 reg = <0 0x17a40000 0 0x20000>; 4478 status = "disabled"; 4479 }; 4480 }; 4481 4482 slimbam: dma@17184000 { 4483 compatible = "qcom,bam-v1.7.0"; 4484 qcom,controlled-remotely; 4485 reg = <0 0x17184000 0 0x2a000>; 4486 num-channels = <31>; 4487 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 4488 #dma-cells = <1>; 4489 qcom,ee = <1>; 4490 qcom,num-ees = <2>; 4491 iommus = <&apps_smmu 0x1806 0x0>; 4492 }; 4493 4494 timer@17c90000 { 4495 #address-cells = <2>; 4496 #size-cells = <2>; 4497 ranges; 4498 compatible = "arm,armv7-timer-mem"; 4499 reg = <0 0x17c90000 0 0x1000>; 4500 4501 frame@17ca0000 { 4502 frame-number = <0>; 4503 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 4504 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 4505 reg = <0 0x17ca0000 0 0x1000>, 4506 <0 0x17cb0000 0 0x1000>; 4507 }; 4508 4509 frame@17cc0000 { 4510 frame-number = <1>; 4511 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 4512 reg = <0 0x17cc0000 0 0x1000>; 4513 status = "disabled"; 4514 }; 4515 4516 frame@17cd0000 { 4517 frame-number = <2>; 4518 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 4519 reg = <0 0x17cd0000 0 0x1000>; 4520 status = "disabled"; 4521 }; 4522 4523 frame@17ce0000 { 4524 frame-number = <3>; 4525 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 4526 reg = <0 0x17ce0000 0 0x1000>; 4527 status = "disabled"; 4528 }; 4529 4530 frame@17cf0000 { 4531 frame-number = <4>; 4532 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 4533 reg = <0 0x17cf0000 0 0x1000>; 4534 status = "disabled"; 4535 }; 4536 4537 frame@17d00000 { 4538 frame-number = <5>; 4539 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 4540 reg = <0 0x17d00000 0 0x1000>; 4541 status = "disabled"; 4542 }; 4543 4544 frame@17d10000 { 4545 frame-number = <6>; 4546 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 4547 reg = <0 0x17d10000 0 0x1000>; 4548 status = "disabled"; 4549 }; 4550 }; 4551 4552 osm_l3: interconnect@17d41000 { 4553 compatible = "qcom,sdm845-osm-l3"; 4554 reg = <0 0x17d41000 0 0x1400>; 4555 4556 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 4557 clock-names = "xo", "alternate"; 4558 4559 #interconnect-cells = <1>; 4560 }; 4561 4562 cpufreq_hw: cpufreq@17d43000 { 4563 compatible = "qcom,cpufreq-hw"; 4564 reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>; 4565 reg-names = "freq-domain0", "freq-domain1"; 4566 4567 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 4568 clock-names = "xo", "alternate"; 4569 4570 #freq-domain-cells = <1>; 4571 }; 4572 4573 wifi: wifi@18800000 { 4574 compatible = "qcom,wcn3990-wifi"; 4575 status = "disabled"; 4576 reg = <0 0x18800000 0 0x800000>; 4577 reg-names = "membase"; 4578 memory-region = <&wlan_msa_mem>; 4579 clock-names = "cxo_ref_clk_pin"; 4580 clocks = <&rpmhcc RPMH_RF_CLK2>; 4581 interrupts = 4582 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 4583 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 4584 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 4585 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 4586 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 4587 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 4588 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 4589 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 4590 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 4591 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 4592 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 4593 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 4594 iommus = <&apps_smmu 0x0040 0x1>; 4595 }; 4596 }; 4597 4598 thermal-zones { 4599 cpu0-thermal { 4600 polling-delay-passive = <250>; 4601 polling-delay = <1000>; 4602 4603 thermal-sensors = <&tsens0 1>; 4604 4605 trips { 4606 cpu0_alert0: trip-point0 { 4607 temperature = <90000>; 4608 hysteresis = <2000>; 4609 type = "passive"; 4610 }; 4611 4612 cpu0_alert1: trip-point1 { 4613 temperature = <95000>; 4614 hysteresis = <2000>; 4615 type = "passive"; 4616 }; 4617 4618 cpu0_crit: cpu_crit { 4619 temperature = <110000>; 4620 hysteresis = <1000>; 4621 type = "critical"; 4622 }; 4623 }; 4624 4625 cooling-maps { 4626 map0 { 4627 trip = <&cpu0_alert0>; 4628 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4629 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4630 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4631 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4632 }; 4633 map1 { 4634 trip = <&cpu0_alert1>; 4635 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4636 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4637 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4638 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4639 }; 4640 }; 4641 }; 4642 4643 cpu1-thermal { 4644 polling-delay-passive = <250>; 4645 polling-delay = <1000>; 4646 4647 thermal-sensors = <&tsens0 2>; 4648 4649 trips { 4650 cpu1_alert0: trip-point0 { 4651 temperature = <90000>; 4652 hysteresis = <2000>; 4653 type = "passive"; 4654 }; 4655 4656 cpu1_alert1: trip-point1 { 4657 temperature = <95000>; 4658 hysteresis = <2000>; 4659 type = "passive"; 4660 }; 4661 4662 cpu1_crit: cpu_crit { 4663 temperature = <110000>; 4664 hysteresis = <1000>; 4665 type = "critical"; 4666 }; 4667 }; 4668 4669 cooling-maps { 4670 map0 { 4671 trip = <&cpu1_alert0>; 4672 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4673 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4674 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4675 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4676 }; 4677 map1 { 4678 trip = <&cpu1_alert1>; 4679 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4680 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4681 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4682 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4683 }; 4684 }; 4685 }; 4686 4687 cpu2-thermal { 4688 polling-delay-passive = <250>; 4689 polling-delay = <1000>; 4690 4691 thermal-sensors = <&tsens0 3>; 4692 4693 trips { 4694 cpu2_alert0: trip-point0 { 4695 temperature = <90000>; 4696 hysteresis = <2000>; 4697 type = "passive"; 4698 }; 4699 4700 cpu2_alert1: trip-point1 { 4701 temperature = <95000>; 4702 hysteresis = <2000>; 4703 type = "passive"; 4704 }; 4705 4706 cpu2_crit: cpu_crit { 4707 temperature = <110000>; 4708 hysteresis = <1000>; 4709 type = "critical"; 4710 }; 4711 }; 4712 4713 cooling-maps { 4714 map0 { 4715 trip = <&cpu2_alert0>; 4716 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4717 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4718 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4719 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4720 }; 4721 map1 { 4722 trip = <&cpu2_alert1>; 4723 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4724 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4725 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4726 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4727 }; 4728 }; 4729 }; 4730 4731 cpu3-thermal { 4732 polling-delay-passive = <250>; 4733 polling-delay = <1000>; 4734 4735 thermal-sensors = <&tsens0 4>; 4736 4737 trips { 4738 cpu3_alert0: trip-point0 { 4739 temperature = <90000>; 4740 hysteresis = <2000>; 4741 type = "passive"; 4742 }; 4743 4744 cpu3_alert1: trip-point1 { 4745 temperature = <95000>; 4746 hysteresis = <2000>; 4747 type = "passive"; 4748 }; 4749 4750 cpu3_crit: cpu_crit { 4751 temperature = <110000>; 4752 hysteresis = <1000>; 4753 type = "critical"; 4754 }; 4755 }; 4756 4757 cooling-maps { 4758 map0 { 4759 trip = <&cpu3_alert0>; 4760 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4761 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4762 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4763 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4764 }; 4765 map1 { 4766 trip = <&cpu3_alert1>; 4767 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4768 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4769 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4770 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4771 }; 4772 }; 4773 }; 4774 4775 cpu4-thermal { 4776 polling-delay-passive = <250>; 4777 polling-delay = <1000>; 4778 4779 thermal-sensors = <&tsens0 7>; 4780 4781 trips { 4782 cpu4_alert0: trip-point0 { 4783 temperature = <90000>; 4784 hysteresis = <2000>; 4785 type = "passive"; 4786 }; 4787 4788 cpu4_alert1: trip-point1 { 4789 temperature = <95000>; 4790 hysteresis = <2000>; 4791 type = "passive"; 4792 }; 4793 4794 cpu4_crit: cpu_crit { 4795 temperature = <110000>; 4796 hysteresis = <1000>; 4797 type = "critical"; 4798 }; 4799 }; 4800 4801 cooling-maps { 4802 map0 { 4803 trip = <&cpu4_alert0>; 4804 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4805 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4806 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4807 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4808 }; 4809 map1 { 4810 trip = <&cpu4_alert1>; 4811 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4812 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4813 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4814 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4815 }; 4816 }; 4817 }; 4818 4819 cpu5-thermal { 4820 polling-delay-passive = <250>; 4821 polling-delay = <1000>; 4822 4823 thermal-sensors = <&tsens0 8>; 4824 4825 trips { 4826 cpu5_alert0: trip-point0 { 4827 temperature = <90000>; 4828 hysteresis = <2000>; 4829 type = "passive"; 4830 }; 4831 4832 cpu5_alert1: trip-point1 { 4833 temperature = <95000>; 4834 hysteresis = <2000>; 4835 type = "passive"; 4836 }; 4837 4838 cpu5_crit: cpu_crit { 4839 temperature = <110000>; 4840 hysteresis = <1000>; 4841 type = "critical"; 4842 }; 4843 }; 4844 4845 cooling-maps { 4846 map0 { 4847 trip = <&cpu5_alert0>; 4848 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4849 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4850 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4851 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4852 }; 4853 map1 { 4854 trip = <&cpu5_alert1>; 4855 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4856 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4857 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4858 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4859 }; 4860 }; 4861 }; 4862 4863 cpu6-thermal { 4864 polling-delay-passive = <250>; 4865 polling-delay = <1000>; 4866 4867 thermal-sensors = <&tsens0 9>; 4868 4869 trips { 4870 cpu6_alert0: trip-point0 { 4871 temperature = <90000>; 4872 hysteresis = <2000>; 4873 type = "passive"; 4874 }; 4875 4876 cpu6_alert1: trip-point1 { 4877 temperature = <95000>; 4878 hysteresis = <2000>; 4879 type = "passive"; 4880 }; 4881 4882 cpu6_crit: cpu_crit { 4883 temperature = <110000>; 4884 hysteresis = <1000>; 4885 type = "critical"; 4886 }; 4887 }; 4888 4889 cooling-maps { 4890 map0 { 4891 trip = <&cpu6_alert0>; 4892 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4893 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4894 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4895 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4896 }; 4897 map1 { 4898 trip = <&cpu6_alert1>; 4899 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4900 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4901 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4902 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4903 }; 4904 }; 4905 }; 4906 4907 cpu7-thermal { 4908 polling-delay-passive = <250>; 4909 polling-delay = <1000>; 4910 4911 thermal-sensors = <&tsens0 10>; 4912 4913 trips { 4914 cpu7_alert0: trip-point0 { 4915 temperature = <90000>; 4916 hysteresis = <2000>; 4917 type = "passive"; 4918 }; 4919 4920 cpu7_alert1: trip-point1 { 4921 temperature = <95000>; 4922 hysteresis = <2000>; 4923 type = "passive"; 4924 }; 4925 4926 cpu7_crit: cpu_crit { 4927 temperature = <110000>; 4928 hysteresis = <1000>; 4929 type = "critical"; 4930 }; 4931 }; 4932 4933 cooling-maps { 4934 map0 { 4935 trip = <&cpu7_alert0>; 4936 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4937 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4938 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4939 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4940 }; 4941 map1 { 4942 trip = <&cpu7_alert1>; 4943 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4944 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4945 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4946 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4947 }; 4948 }; 4949 }; 4950 4951 aoss0-thermal { 4952 polling-delay-passive = <250>; 4953 polling-delay = <1000>; 4954 4955 thermal-sensors = <&tsens0 0>; 4956 4957 trips { 4958 aoss0_alert0: trip-point0 { 4959 temperature = <90000>; 4960 hysteresis = <2000>; 4961 type = "hot"; 4962 }; 4963 }; 4964 }; 4965 4966 cluster0-thermal { 4967 polling-delay-passive = <250>; 4968 polling-delay = <1000>; 4969 4970 thermal-sensors = <&tsens0 5>; 4971 4972 trips { 4973 cluster0_alert0: trip-point0 { 4974 temperature = <90000>; 4975 hysteresis = <2000>; 4976 type = "hot"; 4977 }; 4978 cluster0_crit: cluster0_crit { 4979 temperature = <110000>; 4980 hysteresis = <2000>; 4981 type = "critical"; 4982 }; 4983 }; 4984 }; 4985 4986 cluster1-thermal { 4987 polling-delay-passive = <250>; 4988 polling-delay = <1000>; 4989 4990 thermal-sensors = <&tsens0 6>; 4991 4992 trips { 4993 cluster1_alert0: trip-point0 { 4994 temperature = <90000>; 4995 hysteresis = <2000>; 4996 type = "hot"; 4997 }; 4998 cluster1_crit: cluster1_crit { 4999 temperature = <110000>; 5000 hysteresis = <2000>; 5001 type = "critical"; 5002 }; 5003 }; 5004 }; 5005 5006 gpu-thermal-top { 5007 polling-delay-passive = <250>; 5008 polling-delay = <1000>; 5009 5010 thermal-sensors = <&tsens0 11>; 5011 5012 trips { 5013 gpu1_alert0: trip-point0 { 5014 temperature = <90000>; 5015 hysteresis = <2000>; 5016 type = "hot"; 5017 }; 5018 }; 5019 }; 5020 5021 gpu-thermal-bottom { 5022 polling-delay-passive = <250>; 5023 polling-delay = <1000>; 5024 5025 thermal-sensors = <&tsens0 12>; 5026 5027 trips { 5028 gpu2_alert0: trip-point0 { 5029 temperature = <90000>; 5030 hysteresis = <2000>; 5031 type = "hot"; 5032 }; 5033 }; 5034 }; 5035 5036 aoss1-thermal { 5037 polling-delay-passive = <250>; 5038 polling-delay = <1000>; 5039 5040 thermal-sensors = <&tsens1 0>; 5041 5042 trips { 5043 aoss1_alert0: trip-point0 { 5044 temperature = <90000>; 5045 hysteresis = <2000>; 5046 type = "hot"; 5047 }; 5048 }; 5049 }; 5050 5051 q6-modem-thermal { 5052 polling-delay-passive = <250>; 5053 polling-delay = <1000>; 5054 5055 thermal-sensors = <&tsens1 1>; 5056 5057 trips { 5058 q6_modem_alert0: trip-point0 { 5059 temperature = <90000>; 5060 hysteresis = <2000>; 5061 type = "hot"; 5062 }; 5063 }; 5064 }; 5065 5066 mem-thermal { 5067 polling-delay-passive = <250>; 5068 polling-delay = <1000>; 5069 5070 thermal-sensors = <&tsens1 2>; 5071 5072 trips { 5073 mem_alert0: trip-point0 { 5074 temperature = <90000>; 5075 hysteresis = <2000>; 5076 type = "hot"; 5077 }; 5078 }; 5079 }; 5080 5081 wlan-thermal { 5082 polling-delay-passive = <250>; 5083 polling-delay = <1000>; 5084 5085 thermal-sensors = <&tsens1 3>; 5086 5087 trips { 5088 wlan_alert0: trip-point0 { 5089 temperature = <90000>; 5090 hysteresis = <2000>; 5091 type = "hot"; 5092 }; 5093 }; 5094 }; 5095 5096 q6-hvx-thermal { 5097 polling-delay-passive = <250>; 5098 polling-delay = <1000>; 5099 5100 thermal-sensors = <&tsens1 4>; 5101 5102 trips { 5103 q6_hvx_alert0: trip-point0 { 5104 temperature = <90000>; 5105 hysteresis = <2000>; 5106 type = "hot"; 5107 }; 5108 }; 5109 }; 5110 5111 camera-thermal { 5112 polling-delay-passive = <250>; 5113 polling-delay = <1000>; 5114 5115 thermal-sensors = <&tsens1 5>; 5116 5117 trips { 5118 camera_alert0: trip-point0 { 5119 temperature = <90000>; 5120 hysteresis = <2000>; 5121 type = "hot"; 5122 }; 5123 }; 5124 }; 5125 5126 video-thermal { 5127 polling-delay-passive = <250>; 5128 polling-delay = <1000>; 5129 5130 thermal-sensors = <&tsens1 6>; 5131 5132 trips { 5133 video_alert0: trip-point0 { 5134 temperature = <90000>; 5135 hysteresis = <2000>; 5136 type = "hot"; 5137 }; 5138 }; 5139 }; 5140 5141 modem-thermal { 5142 polling-delay-passive = <250>; 5143 polling-delay = <1000>; 5144 5145 thermal-sensors = <&tsens1 7>; 5146 5147 trips { 5148 modem_alert0: trip-point0 { 5149 temperature = <90000>; 5150 hysteresis = <2000>; 5151 type = "hot"; 5152 }; 5153 }; 5154 }; 5155 }; 5156}; 5157