1// SPDX-License-Identifier: GPL-2.0 2/* 3 * SDM845 SoC device tree source 4 * 5 * Copyright (c) 2018, The Linux Foundation. All rights reserved. 6 */ 7 8#include <dt-bindings/clock/qcom,camcc-sdm845.h> 9#include <dt-bindings/clock/qcom,dispcc-sdm845.h> 10#include <dt-bindings/clock/qcom,gcc-sdm845.h> 11#include <dt-bindings/clock/qcom,gpucc-sdm845.h> 12#include <dt-bindings/clock/qcom,lpass-sdm845.h> 13#include <dt-bindings/clock/qcom,rpmh.h> 14#include <dt-bindings/clock/qcom,videocc-sdm845.h> 15#include <dt-bindings/dma/qcom-gpi.h> 16#include <dt-bindings/gpio/gpio.h> 17#include <dt-bindings/interconnect/qcom,osm-l3.h> 18#include <dt-bindings/interconnect/qcom,sdm845.h> 19#include <dt-bindings/interrupt-controller/arm-gic.h> 20#include <dt-bindings/phy/phy-qcom-qusb2.h> 21#include <dt-bindings/power/qcom-rpmpd.h> 22#include <dt-bindings/reset/qcom,sdm845-aoss.h> 23#include <dt-bindings/reset/qcom,sdm845-pdc.h> 24#include <dt-bindings/soc/qcom,apr.h> 25#include <dt-bindings/soc/qcom,rpmh-rsc.h> 26#include <dt-bindings/clock/qcom,gcc-sdm845.h> 27#include <dt-bindings/thermal/thermal.h> 28 29/ { 30 interrupt-parent = <&intc>; 31 32 #address-cells = <2>; 33 #size-cells = <2>; 34 35 aliases { 36 i2c0 = &i2c0; 37 i2c1 = &i2c1; 38 i2c2 = &i2c2; 39 i2c3 = &i2c3; 40 i2c4 = &i2c4; 41 i2c5 = &i2c5; 42 i2c6 = &i2c6; 43 i2c7 = &i2c7; 44 i2c8 = &i2c8; 45 i2c9 = &i2c9; 46 i2c10 = &i2c10; 47 i2c11 = &i2c11; 48 i2c12 = &i2c12; 49 i2c13 = &i2c13; 50 i2c14 = &i2c14; 51 i2c15 = &i2c15; 52 spi0 = &spi0; 53 spi1 = &spi1; 54 spi2 = &spi2; 55 spi3 = &spi3; 56 spi4 = &spi4; 57 spi5 = &spi5; 58 spi6 = &spi6; 59 spi7 = &spi7; 60 spi8 = &spi8; 61 spi9 = &spi9; 62 spi10 = &spi10; 63 spi11 = &spi11; 64 spi12 = &spi12; 65 spi13 = &spi13; 66 spi14 = &spi14; 67 spi15 = &spi15; 68 }; 69 70 chosen { }; 71 72 memory@80000000 { 73 device_type = "memory"; 74 /* We expect the bootloader to fill in the size */ 75 reg = <0 0x80000000 0 0>; 76 }; 77 78 reserved-memory { 79 #address-cells = <2>; 80 #size-cells = <2>; 81 ranges; 82 83 hyp_mem: hyp-mem@85700000 { 84 reg = <0 0x85700000 0 0x600000>; 85 no-map; 86 }; 87 88 xbl_mem: xbl-mem@85e00000 { 89 reg = <0 0x85e00000 0 0x100000>; 90 no-map; 91 }; 92 93 aop_mem: aop-mem@85fc0000 { 94 reg = <0 0x85fc0000 0 0x20000>; 95 no-map; 96 }; 97 98 aop_cmd_db_mem: aop-cmd-db-mem@85fe0000 { 99 compatible = "qcom,cmd-db"; 100 reg = <0x0 0x85fe0000 0 0x20000>; 101 no-map; 102 }; 103 104 smem@86000000 { 105 compatible = "qcom,smem"; 106 reg = <0x0 0x86000000 0 0x200000>; 107 no-map; 108 hwlocks = <&tcsr_mutex 3>; 109 }; 110 111 tz_mem: tz@86200000 { 112 reg = <0 0x86200000 0 0x2d00000>; 113 no-map; 114 }; 115 116 rmtfs_mem: rmtfs@88f00000 { 117 compatible = "qcom,rmtfs-mem"; 118 reg = <0 0x88f00000 0 0x200000>; 119 no-map; 120 121 qcom,client-id = <1>; 122 qcom,vmid = <15>; 123 }; 124 125 qseecom_mem: qseecom@8ab00000 { 126 reg = <0 0x8ab00000 0 0x1400000>; 127 no-map; 128 }; 129 130 camera_mem: camera-mem@8bf00000 { 131 reg = <0 0x8bf00000 0 0x500000>; 132 no-map; 133 }; 134 135 ipa_fw_mem: ipa-fw@8c400000 { 136 reg = <0 0x8c400000 0 0x10000>; 137 no-map; 138 }; 139 140 ipa_gsi_mem: ipa-gsi@8c410000 { 141 reg = <0 0x8c410000 0 0x5000>; 142 no-map; 143 }; 144 145 gpu_mem: gpu@8c415000 { 146 reg = <0 0x8c415000 0 0x2000>; 147 no-map; 148 }; 149 150 adsp_mem: adsp@8c500000 { 151 reg = <0 0x8c500000 0 0x1a00000>; 152 no-map; 153 }; 154 155 wlan_msa_mem: wlan-msa@8df00000 { 156 reg = <0 0x8df00000 0 0x100000>; 157 no-map; 158 }; 159 160 mpss_region: mpss@8e000000 { 161 reg = <0 0x8e000000 0 0x7800000>; 162 no-map; 163 }; 164 165 venus_mem: venus@95800000 { 166 reg = <0 0x95800000 0 0x500000>; 167 no-map; 168 }; 169 170 cdsp_mem: cdsp@95d00000 { 171 reg = <0 0x95d00000 0 0x800000>; 172 no-map; 173 }; 174 175 mba_region: mba@96500000 { 176 reg = <0 0x96500000 0 0x200000>; 177 no-map; 178 }; 179 180 slpi_mem: slpi@96700000 { 181 reg = <0 0x96700000 0 0x1400000>; 182 no-map; 183 }; 184 185 spss_mem: spss@97b00000 { 186 reg = <0 0x97b00000 0 0x100000>; 187 no-map; 188 }; 189 }; 190 191 cpus: cpus { 192 #address-cells = <2>; 193 #size-cells = <0>; 194 195 CPU0: cpu@0 { 196 device_type = "cpu"; 197 compatible = "qcom,kryo385"; 198 reg = <0x0 0x0>; 199 enable-method = "psci"; 200 capacity-dmips-mhz = <611>; 201 dynamic-power-coefficient = <290>; 202 qcom,freq-domain = <&cpufreq_hw 0>; 203 operating-points-v2 = <&cpu0_opp_table>; 204 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 205 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 206 power-domains = <&CPU_PD0>; 207 power-domain-names = "psci"; 208 #cooling-cells = <2>; 209 next-level-cache = <&L2_0>; 210 L2_0: l2-cache { 211 compatible = "cache"; 212 next-level-cache = <&L3_0>; 213 L3_0: l3-cache { 214 compatible = "cache"; 215 }; 216 }; 217 }; 218 219 CPU1: cpu@100 { 220 device_type = "cpu"; 221 compatible = "qcom,kryo385"; 222 reg = <0x0 0x100>; 223 enable-method = "psci"; 224 capacity-dmips-mhz = <611>; 225 dynamic-power-coefficient = <290>; 226 qcom,freq-domain = <&cpufreq_hw 0>; 227 operating-points-v2 = <&cpu0_opp_table>; 228 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 229 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 230 power-domains = <&CPU_PD1>; 231 power-domain-names = "psci"; 232 #cooling-cells = <2>; 233 next-level-cache = <&L2_100>; 234 L2_100: l2-cache { 235 compatible = "cache"; 236 next-level-cache = <&L3_0>; 237 }; 238 }; 239 240 CPU2: cpu@200 { 241 device_type = "cpu"; 242 compatible = "qcom,kryo385"; 243 reg = <0x0 0x200>; 244 enable-method = "psci"; 245 capacity-dmips-mhz = <611>; 246 dynamic-power-coefficient = <290>; 247 qcom,freq-domain = <&cpufreq_hw 0>; 248 operating-points-v2 = <&cpu0_opp_table>; 249 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 250 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 251 power-domains = <&CPU_PD2>; 252 power-domain-names = "psci"; 253 #cooling-cells = <2>; 254 next-level-cache = <&L2_200>; 255 L2_200: l2-cache { 256 compatible = "cache"; 257 next-level-cache = <&L3_0>; 258 }; 259 }; 260 261 CPU3: cpu@300 { 262 device_type = "cpu"; 263 compatible = "qcom,kryo385"; 264 reg = <0x0 0x300>; 265 enable-method = "psci"; 266 capacity-dmips-mhz = <611>; 267 dynamic-power-coefficient = <290>; 268 qcom,freq-domain = <&cpufreq_hw 0>; 269 operating-points-v2 = <&cpu0_opp_table>; 270 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 271 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 272 #cooling-cells = <2>; 273 power-domains = <&CPU_PD3>; 274 power-domain-names = "psci"; 275 next-level-cache = <&L2_300>; 276 L2_300: l2-cache { 277 compatible = "cache"; 278 next-level-cache = <&L3_0>; 279 }; 280 }; 281 282 CPU4: cpu@400 { 283 device_type = "cpu"; 284 compatible = "qcom,kryo385"; 285 reg = <0x0 0x400>; 286 enable-method = "psci"; 287 capacity-dmips-mhz = <1024>; 288 dynamic-power-coefficient = <442>; 289 qcom,freq-domain = <&cpufreq_hw 1>; 290 operating-points-v2 = <&cpu4_opp_table>; 291 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 292 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 293 power-domains = <&CPU_PD4>; 294 power-domain-names = "psci"; 295 #cooling-cells = <2>; 296 next-level-cache = <&L2_400>; 297 L2_400: l2-cache { 298 compatible = "cache"; 299 next-level-cache = <&L3_0>; 300 }; 301 }; 302 303 CPU5: cpu@500 { 304 device_type = "cpu"; 305 compatible = "qcom,kryo385"; 306 reg = <0x0 0x500>; 307 enable-method = "psci"; 308 capacity-dmips-mhz = <1024>; 309 dynamic-power-coefficient = <442>; 310 qcom,freq-domain = <&cpufreq_hw 1>; 311 operating-points-v2 = <&cpu4_opp_table>; 312 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 313 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 314 power-domains = <&CPU_PD5>; 315 power-domain-names = "psci"; 316 #cooling-cells = <2>; 317 next-level-cache = <&L2_500>; 318 L2_500: l2-cache { 319 compatible = "cache"; 320 next-level-cache = <&L3_0>; 321 }; 322 }; 323 324 CPU6: cpu@600 { 325 device_type = "cpu"; 326 compatible = "qcom,kryo385"; 327 reg = <0x0 0x600>; 328 enable-method = "psci"; 329 capacity-dmips-mhz = <1024>; 330 dynamic-power-coefficient = <442>; 331 qcom,freq-domain = <&cpufreq_hw 1>; 332 operating-points-v2 = <&cpu4_opp_table>; 333 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 334 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 335 power-domains = <&CPU_PD6>; 336 power-domain-names = "psci"; 337 #cooling-cells = <2>; 338 next-level-cache = <&L2_600>; 339 L2_600: l2-cache { 340 compatible = "cache"; 341 next-level-cache = <&L3_0>; 342 }; 343 }; 344 345 CPU7: cpu@700 { 346 device_type = "cpu"; 347 compatible = "qcom,kryo385"; 348 reg = <0x0 0x700>; 349 enable-method = "psci"; 350 capacity-dmips-mhz = <1024>; 351 dynamic-power-coefficient = <442>; 352 qcom,freq-domain = <&cpufreq_hw 1>; 353 operating-points-v2 = <&cpu4_opp_table>; 354 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 355 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 356 power-domains = <&CPU_PD7>; 357 power-domain-names = "psci"; 358 #cooling-cells = <2>; 359 next-level-cache = <&L2_700>; 360 L2_700: l2-cache { 361 compatible = "cache"; 362 next-level-cache = <&L3_0>; 363 }; 364 }; 365 366 cpu-map { 367 cluster0 { 368 core0 { 369 cpu = <&CPU0>; 370 }; 371 372 core1 { 373 cpu = <&CPU1>; 374 }; 375 376 core2 { 377 cpu = <&CPU2>; 378 }; 379 380 core3 { 381 cpu = <&CPU3>; 382 }; 383 384 core4 { 385 cpu = <&CPU4>; 386 }; 387 388 core5 { 389 cpu = <&CPU5>; 390 }; 391 392 core6 { 393 cpu = <&CPU6>; 394 }; 395 396 core7 { 397 cpu = <&CPU7>; 398 }; 399 }; 400 }; 401 402 cpu_idle_states: idle-states { 403 entry-method = "psci"; 404 405 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 406 compatible = "arm,idle-state"; 407 idle-state-name = "little-rail-power-collapse"; 408 arm,psci-suspend-param = <0x40000004>; 409 entry-latency-us = <350>; 410 exit-latency-us = <461>; 411 min-residency-us = <1890>; 412 local-timer-stop; 413 }; 414 415 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 416 compatible = "arm,idle-state"; 417 idle-state-name = "big-rail-power-collapse"; 418 arm,psci-suspend-param = <0x40000004>; 419 entry-latency-us = <264>; 420 exit-latency-us = <621>; 421 min-residency-us = <952>; 422 local-timer-stop; 423 }; 424 }; 425 426 domain-idle-states { 427 CLUSTER_SLEEP_0: cluster-sleep-0 { 428 compatible = "domain-idle-state"; 429 idle-state-name = "cluster-power-collapse"; 430 arm,psci-suspend-param = <0x4100c244>; 431 entry-latency-us = <3263>; 432 exit-latency-us = <6562>; 433 min-residency-us = <9987>; 434 local-timer-stop; 435 }; 436 }; 437 }; 438 439 cpu0_opp_table: opp-table-cpu0 { 440 compatible = "operating-points-v2"; 441 opp-shared; 442 443 cpu0_opp1: opp-300000000 { 444 opp-hz = /bits/ 64 <300000000>; 445 opp-peak-kBps = <800000 4800000>; 446 }; 447 448 cpu0_opp2: opp-403200000 { 449 opp-hz = /bits/ 64 <403200000>; 450 opp-peak-kBps = <800000 4800000>; 451 }; 452 453 cpu0_opp3: opp-480000000 { 454 opp-hz = /bits/ 64 <480000000>; 455 opp-peak-kBps = <800000 6451200>; 456 }; 457 458 cpu0_opp4: opp-576000000 { 459 opp-hz = /bits/ 64 <576000000>; 460 opp-peak-kBps = <800000 6451200>; 461 }; 462 463 cpu0_opp5: opp-652800000 { 464 opp-hz = /bits/ 64 <652800000>; 465 opp-peak-kBps = <800000 7680000>; 466 }; 467 468 cpu0_opp6: opp-748800000 { 469 opp-hz = /bits/ 64 <748800000>; 470 opp-peak-kBps = <1804000 9216000>; 471 }; 472 473 cpu0_opp7: opp-825600000 { 474 opp-hz = /bits/ 64 <825600000>; 475 opp-peak-kBps = <1804000 9216000>; 476 }; 477 478 cpu0_opp8: opp-902400000 { 479 opp-hz = /bits/ 64 <902400000>; 480 opp-peak-kBps = <1804000 10444800>; 481 }; 482 483 cpu0_opp9: opp-979200000 { 484 opp-hz = /bits/ 64 <979200000>; 485 opp-peak-kBps = <1804000 11980800>; 486 }; 487 488 cpu0_opp10: opp-1056000000 { 489 opp-hz = /bits/ 64 <1056000000>; 490 opp-peak-kBps = <1804000 11980800>; 491 }; 492 493 cpu0_opp11: opp-1132800000 { 494 opp-hz = /bits/ 64 <1132800000>; 495 opp-peak-kBps = <2188000 13516800>; 496 }; 497 498 cpu0_opp12: opp-1228800000 { 499 opp-hz = /bits/ 64 <1228800000>; 500 opp-peak-kBps = <2188000 15052800>; 501 }; 502 503 cpu0_opp13: opp-1324800000 { 504 opp-hz = /bits/ 64 <1324800000>; 505 opp-peak-kBps = <2188000 16588800>; 506 }; 507 508 cpu0_opp14: opp-1420800000 { 509 opp-hz = /bits/ 64 <1420800000>; 510 opp-peak-kBps = <3072000 18124800>; 511 }; 512 513 cpu0_opp15: opp-1516800000 { 514 opp-hz = /bits/ 64 <1516800000>; 515 opp-peak-kBps = <3072000 19353600>; 516 }; 517 518 cpu0_opp16: opp-1612800000 { 519 opp-hz = /bits/ 64 <1612800000>; 520 opp-peak-kBps = <4068000 19353600>; 521 }; 522 523 cpu0_opp17: opp-1689600000 { 524 opp-hz = /bits/ 64 <1689600000>; 525 opp-peak-kBps = <4068000 20889600>; 526 }; 527 528 cpu0_opp18: opp-1766400000 { 529 opp-hz = /bits/ 64 <1766400000>; 530 opp-peak-kBps = <4068000 22425600>; 531 }; 532 }; 533 534 cpu4_opp_table: opp-table-cpu4 { 535 compatible = "operating-points-v2"; 536 opp-shared; 537 538 cpu4_opp1: opp-300000000 { 539 opp-hz = /bits/ 64 <300000000>; 540 opp-peak-kBps = <800000 4800000>; 541 }; 542 543 cpu4_opp2: opp-403200000 { 544 opp-hz = /bits/ 64 <403200000>; 545 opp-peak-kBps = <800000 4800000>; 546 }; 547 548 cpu4_opp3: opp-480000000 { 549 opp-hz = /bits/ 64 <480000000>; 550 opp-peak-kBps = <1804000 4800000>; 551 }; 552 553 cpu4_opp4: opp-576000000 { 554 opp-hz = /bits/ 64 <576000000>; 555 opp-peak-kBps = <1804000 4800000>; 556 }; 557 558 cpu4_opp5: opp-652800000 { 559 opp-hz = /bits/ 64 <652800000>; 560 opp-peak-kBps = <1804000 4800000>; 561 }; 562 563 cpu4_opp6: opp-748800000 { 564 opp-hz = /bits/ 64 <748800000>; 565 opp-peak-kBps = <1804000 4800000>; 566 }; 567 568 cpu4_opp7: opp-825600000 { 569 opp-hz = /bits/ 64 <825600000>; 570 opp-peak-kBps = <2188000 9216000>; 571 }; 572 573 cpu4_opp8: opp-902400000 { 574 opp-hz = /bits/ 64 <902400000>; 575 opp-peak-kBps = <2188000 9216000>; 576 }; 577 578 cpu4_opp9: opp-979200000 { 579 opp-hz = /bits/ 64 <979200000>; 580 opp-peak-kBps = <2188000 9216000>; 581 }; 582 583 cpu4_opp10: opp-1056000000 { 584 opp-hz = /bits/ 64 <1056000000>; 585 opp-peak-kBps = <3072000 9216000>; 586 }; 587 588 cpu4_opp11: opp-1132800000 { 589 opp-hz = /bits/ 64 <1132800000>; 590 opp-peak-kBps = <3072000 11980800>; 591 }; 592 593 cpu4_opp12: opp-1209600000 { 594 opp-hz = /bits/ 64 <1209600000>; 595 opp-peak-kBps = <4068000 11980800>; 596 }; 597 598 cpu4_opp13: opp-1286400000 { 599 opp-hz = /bits/ 64 <1286400000>; 600 opp-peak-kBps = <4068000 11980800>; 601 }; 602 603 cpu4_opp14: opp-1363200000 { 604 opp-hz = /bits/ 64 <1363200000>; 605 opp-peak-kBps = <4068000 15052800>; 606 }; 607 608 cpu4_opp15: opp-1459200000 { 609 opp-hz = /bits/ 64 <1459200000>; 610 opp-peak-kBps = <4068000 15052800>; 611 }; 612 613 cpu4_opp16: opp-1536000000 { 614 opp-hz = /bits/ 64 <1536000000>; 615 opp-peak-kBps = <5412000 15052800>; 616 }; 617 618 cpu4_opp17: opp-1612800000 { 619 opp-hz = /bits/ 64 <1612800000>; 620 opp-peak-kBps = <5412000 15052800>; 621 }; 622 623 cpu4_opp18: opp-1689600000 { 624 opp-hz = /bits/ 64 <1689600000>; 625 opp-peak-kBps = <5412000 19353600>; 626 }; 627 628 cpu4_opp19: opp-1766400000 { 629 opp-hz = /bits/ 64 <1766400000>; 630 opp-peak-kBps = <6220000 19353600>; 631 }; 632 633 cpu4_opp20: opp-1843200000 { 634 opp-hz = /bits/ 64 <1843200000>; 635 opp-peak-kBps = <6220000 19353600>; 636 }; 637 638 cpu4_opp21: opp-1920000000 { 639 opp-hz = /bits/ 64 <1920000000>; 640 opp-peak-kBps = <7216000 19353600>; 641 }; 642 643 cpu4_opp22: opp-1996800000 { 644 opp-hz = /bits/ 64 <1996800000>; 645 opp-peak-kBps = <7216000 20889600>; 646 }; 647 648 cpu4_opp23: opp-2092800000 { 649 opp-hz = /bits/ 64 <2092800000>; 650 opp-peak-kBps = <7216000 20889600>; 651 }; 652 653 cpu4_opp24: opp-2169600000 { 654 opp-hz = /bits/ 64 <2169600000>; 655 opp-peak-kBps = <7216000 20889600>; 656 }; 657 658 cpu4_opp25: opp-2246400000 { 659 opp-hz = /bits/ 64 <2246400000>; 660 opp-peak-kBps = <7216000 20889600>; 661 }; 662 663 cpu4_opp26: opp-2323200000 { 664 opp-hz = /bits/ 64 <2323200000>; 665 opp-peak-kBps = <7216000 20889600>; 666 }; 667 668 cpu4_opp27: opp-2400000000 { 669 opp-hz = /bits/ 64 <2400000000>; 670 opp-peak-kBps = <7216000 22425600>; 671 }; 672 673 cpu4_opp28: opp-2476800000 { 674 opp-hz = /bits/ 64 <2476800000>; 675 opp-peak-kBps = <7216000 22425600>; 676 }; 677 678 cpu4_opp29: opp-2553600000 { 679 opp-hz = /bits/ 64 <2553600000>; 680 opp-peak-kBps = <7216000 22425600>; 681 }; 682 683 cpu4_opp30: opp-2649600000 { 684 opp-hz = /bits/ 64 <2649600000>; 685 opp-peak-kBps = <7216000 22425600>; 686 }; 687 688 cpu4_opp31: opp-2745600000 { 689 opp-hz = /bits/ 64 <2745600000>; 690 opp-peak-kBps = <7216000 25497600>; 691 }; 692 693 cpu4_opp32: opp-2803200000 { 694 opp-hz = /bits/ 64 <2803200000>; 695 opp-peak-kBps = <7216000 25497600>; 696 }; 697 }; 698 699 pmu { 700 compatible = "arm,armv8-pmuv3"; 701 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; 702 }; 703 704 timer { 705 compatible = "arm,armv8-timer"; 706 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 707 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 708 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 709 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 710 }; 711 712 clocks { 713 xo_board: xo-board { 714 compatible = "fixed-clock"; 715 #clock-cells = <0>; 716 clock-frequency = <38400000>; 717 clock-output-names = "xo_board"; 718 }; 719 720 sleep_clk: sleep-clk { 721 compatible = "fixed-clock"; 722 #clock-cells = <0>; 723 clock-frequency = <32764>; 724 }; 725 }; 726 727 firmware { 728 scm { 729 compatible = "qcom,scm-sdm845", "qcom,scm"; 730 }; 731 }; 732 733 adsp_pas: remoteproc-adsp { 734 compatible = "qcom,sdm845-adsp-pas"; 735 736 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 737 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 738 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 739 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 740 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 741 interrupt-names = "wdog", "fatal", "ready", 742 "handover", "stop-ack"; 743 744 clocks = <&rpmhcc RPMH_CXO_CLK>; 745 clock-names = "xo"; 746 747 memory-region = <&adsp_mem>; 748 749 qcom,qmp = <&aoss_qmp>; 750 751 qcom,smem-states = <&adsp_smp2p_out 0>; 752 qcom,smem-state-names = "stop"; 753 754 status = "disabled"; 755 756 glink-edge { 757 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 758 label = "lpass"; 759 qcom,remote-pid = <2>; 760 mboxes = <&apss_shared 8>; 761 762 apr { 763 compatible = "qcom,apr-v2"; 764 qcom,glink-channels = "apr_audio_svc"; 765 qcom,domain = <APR_DOMAIN_ADSP>; 766 #address-cells = <1>; 767 #size-cells = <0>; 768 qcom,intents = <512 20>; 769 770 service@3 { 771 reg = <APR_SVC_ADSP_CORE>; 772 compatible = "qcom,q6core"; 773 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 774 }; 775 776 q6afe: service@4 { 777 compatible = "qcom,q6afe"; 778 reg = <APR_SVC_AFE>; 779 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 780 q6afedai: dais { 781 compatible = "qcom,q6afe-dais"; 782 #address-cells = <1>; 783 #size-cells = <0>; 784 #sound-dai-cells = <1>; 785 }; 786 }; 787 788 q6asm: service@7 { 789 compatible = "qcom,q6asm"; 790 reg = <APR_SVC_ASM>; 791 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 792 q6asmdai: dais { 793 compatible = "qcom,q6asm-dais"; 794 #address-cells = <1>; 795 #size-cells = <0>; 796 #sound-dai-cells = <1>; 797 iommus = <&apps_smmu 0x1821 0x0>; 798 }; 799 }; 800 801 q6adm: service@8 { 802 compatible = "qcom,q6adm"; 803 reg = <APR_SVC_ADM>; 804 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 805 q6routing: routing { 806 compatible = "qcom,q6adm-routing"; 807 #sound-dai-cells = <0>; 808 }; 809 }; 810 }; 811 812 fastrpc { 813 compatible = "qcom,fastrpc"; 814 qcom,glink-channels = "fastrpcglink-apps-dsp"; 815 label = "adsp"; 816 qcom,non-secure-domain; 817 #address-cells = <1>; 818 #size-cells = <0>; 819 820 compute-cb@3 { 821 compatible = "qcom,fastrpc-compute-cb"; 822 reg = <3>; 823 iommus = <&apps_smmu 0x1823 0x0>; 824 }; 825 826 compute-cb@4 { 827 compatible = "qcom,fastrpc-compute-cb"; 828 reg = <4>; 829 iommus = <&apps_smmu 0x1824 0x0>; 830 }; 831 }; 832 }; 833 }; 834 835 cdsp_pas: remoteproc-cdsp { 836 compatible = "qcom,sdm845-cdsp-pas"; 837 838 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 839 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 840 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 841 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 842 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 843 interrupt-names = "wdog", "fatal", "ready", 844 "handover", "stop-ack"; 845 846 clocks = <&rpmhcc RPMH_CXO_CLK>; 847 clock-names = "xo"; 848 849 memory-region = <&cdsp_mem>; 850 851 qcom,qmp = <&aoss_qmp>; 852 853 qcom,smem-states = <&cdsp_smp2p_out 0>; 854 qcom,smem-state-names = "stop"; 855 856 status = "disabled"; 857 858 glink-edge { 859 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>; 860 label = "turing"; 861 qcom,remote-pid = <5>; 862 mboxes = <&apss_shared 4>; 863 fastrpc { 864 compatible = "qcom,fastrpc"; 865 qcom,glink-channels = "fastrpcglink-apps-dsp"; 866 label = "cdsp"; 867 qcom,non-secure-domain; 868 #address-cells = <1>; 869 #size-cells = <0>; 870 871 compute-cb@1 { 872 compatible = "qcom,fastrpc-compute-cb"; 873 reg = <1>; 874 iommus = <&apps_smmu 0x1401 0x30>; 875 }; 876 877 compute-cb@2 { 878 compatible = "qcom,fastrpc-compute-cb"; 879 reg = <2>; 880 iommus = <&apps_smmu 0x1402 0x30>; 881 }; 882 883 compute-cb@3 { 884 compatible = "qcom,fastrpc-compute-cb"; 885 reg = <3>; 886 iommus = <&apps_smmu 0x1403 0x30>; 887 }; 888 889 compute-cb@4 { 890 compatible = "qcom,fastrpc-compute-cb"; 891 reg = <4>; 892 iommus = <&apps_smmu 0x1404 0x30>; 893 }; 894 895 compute-cb@5 { 896 compatible = "qcom,fastrpc-compute-cb"; 897 reg = <5>; 898 iommus = <&apps_smmu 0x1405 0x30>; 899 }; 900 901 compute-cb@6 { 902 compatible = "qcom,fastrpc-compute-cb"; 903 reg = <6>; 904 iommus = <&apps_smmu 0x1406 0x30>; 905 }; 906 907 compute-cb@7 { 908 compatible = "qcom,fastrpc-compute-cb"; 909 reg = <7>; 910 iommus = <&apps_smmu 0x1407 0x30>; 911 }; 912 913 compute-cb@8 { 914 compatible = "qcom,fastrpc-compute-cb"; 915 reg = <8>; 916 iommus = <&apps_smmu 0x1408 0x30>; 917 }; 918 }; 919 }; 920 }; 921 922 smp2p-cdsp { 923 compatible = "qcom,smp2p"; 924 qcom,smem = <94>, <432>; 925 926 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; 927 928 mboxes = <&apss_shared 6>; 929 930 qcom,local-pid = <0>; 931 qcom,remote-pid = <5>; 932 933 cdsp_smp2p_out: master-kernel { 934 qcom,entry-name = "master-kernel"; 935 #qcom,smem-state-cells = <1>; 936 }; 937 938 cdsp_smp2p_in: slave-kernel { 939 qcom,entry-name = "slave-kernel"; 940 941 interrupt-controller; 942 #interrupt-cells = <2>; 943 }; 944 }; 945 946 smp2p-lpass { 947 compatible = "qcom,smp2p"; 948 qcom,smem = <443>, <429>; 949 950 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 951 952 mboxes = <&apss_shared 10>; 953 954 qcom,local-pid = <0>; 955 qcom,remote-pid = <2>; 956 957 adsp_smp2p_out: master-kernel { 958 qcom,entry-name = "master-kernel"; 959 #qcom,smem-state-cells = <1>; 960 }; 961 962 adsp_smp2p_in: slave-kernel { 963 qcom,entry-name = "slave-kernel"; 964 965 interrupt-controller; 966 #interrupt-cells = <2>; 967 }; 968 }; 969 970 smp2p-mpss { 971 compatible = "qcom,smp2p"; 972 qcom,smem = <435>, <428>; 973 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 974 mboxes = <&apss_shared 14>; 975 qcom,local-pid = <0>; 976 qcom,remote-pid = <1>; 977 978 modem_smp2p_out: master-kernel { 979 qcom,entry-name = "master-kernel"; 980 #qcom,smem-state-cells = <1>; 981 }; 982 983 modem_smp2p_in: slave-kernel { 984 qcom,entry-name = "slave-kernel"; 985 interrupt-controller; 986 #interrupt-cells = <2>; 987 }; 988 989 ipa_smp2p_out: ipa-ap-to-modem { 990 qcom,entry-name = "ipa"; 991 #qcom,smem-state-cells = <1>; 992 }; 993 994 ipa_smp2p_in: ipa-modem-to-ap { 995 qcom,entry-name = "ipa"; 996 interrupt-controller; 997 #interrupt-cells = <2>; 998 }; 999 }; 1000 1001 smp2p-slpi { 1002 compatible = "qcom,smp2p"; 1003 qcom,smem = <481>, <430>; 1004 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>; 1005 mboxes = <&apss_shared 26>; 1006 qcom,local-pid = <0>; 1007 qcom,remote-pid = <3>; 1008 1009 slpi_smp2p_out: master-kernel { 1010 qcom,entry-name = "master-kernel"; 1011 #qcom,smem-state-cells = <1>; 1012 }; 1013 1014 slpi_smp2p_in: slave-kernel { 1015 qcom,entry-name = "slave-kernel"; 1016 interrupt-controller; 1017 #interrupt-cells = <2>; 1018 }; 1019 }; 1020 1021 psci: psci { 1022 compatible = "arm,psci-1.0"; 1023 method = "smc"; 1024 1025 CPU_PD0: power-domain-cpu0 { 1026 #power-domain-cells = <0>; 1027 power-domains = <&CLUSTER_PD>; 1028 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 1029 }; 1030 1031 CPU_PD1: power-domain-cpu1 { 1032 #power-domain-cells = <0>; 1033 power-domains = <&CLUSTER_PD>; 1034 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 1035 }; 1036 1037 CPU_PD2: power-domain-cpu2 { 1038 #power-domain-cells = <0>; 1039 power-domains = <&CLUSTER_PD>; 1040 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 1041 }; 1042 1043 CPU_PD3: power-domain-cpu3 { 1044 #power-domain-cells = <0>; 1045 power-domains = <&CLUSTER_PD>; 1046 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 1047 }; 1048 1049 CPU_PD4: power-domain-cpu4 { 1050 #power-domain-cells = <0>; 1051 power-domains = <&CLUSTER_PD>; 1052 domain-idle-states = <&BIG_CPU_SLEEP_0>; 1053 }; 1054 1055 CPU_PD5: power-domain-cpu5 { 1056 #power-domain-cells = <0>; 1057 power-domains = <&CLUSTER_PD>; 1058 domain-idle-states = <&BIG_CPU_SLEEP_0>; 1059 }; 1060 1061 CPU_PD6: power-domain-cpu6 { 1062 #power-domain-cells = <0>; 1063 power-domains = <&CLUSTER_PD>; 1064 domain-idle-states = <&BIG_CPU_SLEEP_0>; 1065 }; 1066 1067 CPU_PD7: power-domain-cpu7 { 1068 #power-domain-cells = <0>; 1069 power-domains = <&CLUSTER_PD>; 1070 domain-idle-states = <&BIG_CPU_SLEEP_0>; 1071 }; 1072 1073 CLUSTER_PD: power-domain-cluster { 1074 #power-domain-cells = <0>; 1075 domain-idle-states = <&CLUSTER_SLEEP_0>; 1076 }; 1077 }; 1078 1079 soc: soc@0 { 1080 #address-cells = <2>; 1081 #size-cells = <2>; 1082 ranges = <0 0 0 0 0x10 0>; 1083 dma-ranges = <0 0 0 0 0x10 0>; 1084 compatible = "simple-bus"; 1085 1086 gcc: clock-controller@100000 { 1087 compatible = "qcom,gcc-sdm845"; 1088 reg = <0 0x00100000 0 0x1f0000>; 1089 clocks = <&rpmhcc RPMH_CXO_CLK>, 1090 <&rpmhcc RPMH_CXO_CLK_A>, 1091 <&sleep_clk>, 1092 <&pcie0_lane>, 1093 <&pcie1_lane>; 1094 clock-names = "bi_tcxo", 1095 "bi_tcxo_ao", 1096 "sleep_clk", 1097 "pcie_0_pipe_clk", 1098 "pcie_1_pipe_clk"; 1099 #clock-cells = <1>; 1100 #reset-cells = <1>; 1101 #power-domain-cells = <1>; 1102 }; 1103 1104 qfprom@784000 { 1105 compatible = "qcom,sdm845-qfprom", "qcom,qfprom"; 1106 reg = <0 0x00784000 0 0x8ff>; 1107 #address-cells = <1>; 1108 #size-cells = <1>; 1109 1110 qusb2p_hstx_trim: hstx-trim-primary@1eb { 1111 reg = <0x1eb 0x1>; 1112 bits = <1 4>; 1113 }; 1114 1115 qusb2s_hstx_trim: hstx-trim-secondary@1eb { 1116 reg = <0x1eb 0x2>; 1117 bits = <6 4>; 1118 }; 1119 }; 1120 1121 rng: rng@793000 { 1122 compatible = "qcom,prng-ee"; 1123 reg = <0 0x00793000 0 0x1000>; 1124 clocks = <&gcc GCC_PRNG_AHB_CLK>; 1125 clock-names = "core"; 1126 }; 1127 1128 qup_opp_table: opp-table-qup { 1129 compatible = "operating-points-v2"; 1130 1131 opp-50000000 { 1132 opp-hz = /bits/ 64 <50000000>; 1133 required-opps = <&rpmhpd_opp_min_svs>; 1134 }; 1135 1136 opp-75000000 { 1137 opp-hz = /bits/ 64 <75000000>; 1138 required-opps = <&rpmhpd_opp_low_svs>; 1139 }; 1140 1141 opp-100000000 { 1142 opp-hz = /bits/ 64 <100000000>; 1143 required-opps = <&rpmhpd_opp_svs>; 1144 }; 1145 1146 opp-128000000 { 1147 opp-hz = /bits/ 64 <128000000>; 1148 required-opps = <&rpmhpd_opp_nom>; 1149 }; 1150 }; 1151 1152 gpi_dma0: dma-controller@800000 { 1153 #dma-cells = <3>; 1154 compatible = "qcom,sdm845-gpi-dma"; 1155 reg = <0 0x00800000 0 0x60000>; 1156 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 1157 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 1158 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 1159 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 1160 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 1161 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 1162 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 1163 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 1164 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 1165 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 1166 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 1167 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 1168 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 1169 dma-channels = <13>; 1170 dma-channel-mask = <0xfa>; 1171 iommus = <&apps_smmu 0x0016 0x0>; 1172 status = "disabled"; 1173 }; 1174 1175 qupv3_id_0: geniqup@8c0000 { 1176 compatible = "qcom,geni-se-qup"; 1177 reg = <0 0x008c0000 0 0x6000>; 1178 clock-names = "m-ahb", "s-ahb"; 1179 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1180 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1181 iommus = <&apps_smmu 0x3 0x0>; 1182 #address-cells = <2>; 1183 #size-cells = <2>; 1184 ranges; 1185 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>; 1186 interconnect-names = "qup-core"; 1187 status = "disabled"; 1188 1189 i2c0: i2c@880000 { 1190 compatible = "qcom,geni-i2c"; 1191 reg = <0 0x00880000 0 0x4000>; 1192 clock-names = "se"; 1193 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1194 pinctrl-names = "default"; 1195 pinctrl-0 = <&qup_i2c0_default>; 1196 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1197 #address-cells = <1>; 1198 #size-cells = <0>; 1199 power-domains = <&rpmhpd SDM845_CX>; 1200 operating-points-v2 = <&qup_opp_table>; 1201 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1202 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, 1203 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; 1204 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1205 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1206 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1207 dma-names = "tx", "rx"; 1208 status = "disabled"; 1209 }; 1210 1211 spi0: spi@880000 { 1212 compatible = "qcom,geni-spi"; 1213 reg = <0 0x00880000 0 0x4000>; 1214 clock-names = "se"; 1215 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1216 pinctrl-names = "default"; 1217 pinctrl-0 = <&qup_spi0_default>; 1218 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1219 #address-cells = <1>; 1220 #size-cells = <0>; 1221 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1222 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1223 interconnect-names = "qup-core", "qup-config"; 1224 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1225 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1226 dma-names = "tx", "rx"; 1227 status = "disabled"; 1228 }; 1229 1230 uart0: serial@880000 { 1231 compatible = "qcom,geni-uart"; 1232 reg = <0 0x00880000 0 0x4000>; 1233 clock-names = "se"; 1234 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1235 pinctrl-names = "default"; 1236 pinctrl-0 = <&qup_uart0_default>; 1237 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1238 power-domains = <&rpmhpd SDM845_CX>; 1239 operating-points-v2 = <&qup_opp_table>; 1240 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1241 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1242 interconnect-names = "qup-core", "qup-config"; 1243 status = "disabled"; 1244 }; 1245 1246 i2c1: i2c@884000 { 1247 compatible = "qcom,geni-i2c"; 1248 reg = <0 0x00884000 0 0x4000>; 1249 clock-names = "se"; 1250 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1251 pinctrl-names = "default"; 1252 pinctrl-0 = <&qup_i2c1_default>; 1253 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1254 #address-cells = <1>; 1255 #size-cells = <0>; 1256 power-domains = <&rpmhpd SDM845_CX>; 1257 operating-points-v2 = <&qup_opp_table>; 1258 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1259 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, 1260 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; 1261 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1262 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1263 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1264 dma-names = "tx", "rx"; 1265 status = "disabled"; 1266 }; 1267 1268 spi1: spi@884000 { 1269 compatible = "qcom,geni-spi"; 1270 reg = <0 0x00884000 0 0x4000>; 1271 clock-names = "se"; 1272 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1273 pinctrl-names = "default"; 1274 pinctrl-0 = <&qup_spi1_default>; 1275 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1276 #address-cells = <1>; 1277 #size-cells = <0>; 1278 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1279 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1280 interconnect-names = "qup-core", "qup-config"; 1281 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1282 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1283 dma-names = "tx", "rx"; 1284 status = "disabled"; 1285 }; 1286 1287 uart1: serial@884000 { 1288 compatible = "qcom,geni-uart"; 1289 reg = <0 0x00884000 0 0x4000>; 1290 clock-names = "se"; 1291 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1292 pinctrl-names = "default"; 1293 pinctrl-0 = <&qup_uart1_default>; 1294 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1295 power-domains = <&rpmhpd SDM845_CX>; 1296 operating-points-v2 = <&qup_opp_table>; 1297 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1298 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1299 interconnect-names = "qup-core", "qup-config"; 1300 status = "disabled"; 1301 }; 1302 1303 i2c2: i2c@888000 { 1304 compatible = "qcom,geni-i2c"; 1305 reg = <0 0x00888000 0 0x4000>; 1306 clock-names = "se"; 1307 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1308 pinctrl-names = "default"; 1309 pinctrl-0 = <&qup_i2c2_default>; 1310 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1311 #address-cells = <1>; 1312 #size-cells = <0>; 1313 power-domains = <&rpmhpd SDM845_CX>; 1314 operating-points-v2 = <&qup_opp_table>; 1315 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1316 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, 1317 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; 1318 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1319 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1320 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1321 dma-names = "tx", "rx"; 1322 status = "disabled"; 1323 }; 1324 1325 spi2: spi@888000 { 1326 compatible = "qcom,geni-spi"; 1327 reg = <0 0x00888000 0 0x4000>; 1328 clock-names = "se"; 1329 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1330 pinctrl-names = "default"; 1331 pinctrl-0 = <&qup_spi2_default>; 1332 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1333 #address-cells = <1>; 1334 #size-cells = <0>; 1335 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1336 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1337 interconnect-names = "qup-core", "qup-config"; 1338 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1339 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1340 dma-names = "tx", "rx"; 1341 status = "disabled"; 1342 }; 1343 1344 uart2: serial@888000 { 1345 compatible = "qcom,geni-uart"; 1346 reg = <0 0x00888000 0 0x4000>; 1347 clock-names = "se"; 1348 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1349 pinctrl-names = "default"; 1350 pinctrl-0 = <&qup_uart2_default>; 1351 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1352 power-domains = <&rpmhpd SDM845_CX>; 1353 operating-points-v2 = <&qup_opp_table>; 1354 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1355 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1356 interconnect-names = "qup-core", "qup-config"; 1357 status = "disabled"; 1358 }; 1359 1360 i2c3: i2c@88c000 { 1361 compatible = "qcom,geni-i2c"; 1362 reg = <0 0x0088c000 0 0x4000>; 1363 clock-names = "se"; 1364 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1365 pinctrl-names = "default"; 1366 pinctrl-0 = <&qup_i2c3_default>; 1367 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1368 #address-cells = <1>; 1369 #size-cells = <0>; 1370 power-domains = <&rpmhpd SDM845_CX>; 1371 operating-points-v2 = <&qup_opp_table>; 1372 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1373 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, 1374 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; 1375 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1376 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1377 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1378 dma-names = "tx", "rx"; 1379 status = "disabled"; 1380 }; 1381 1382 spi3: spi@88c000 { 1383 compatible = "qcom,geni-spi"; 1384 reg = <0 0x0088c000 0 0x4000>; 1385 clock-names = "se"; 1386 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1387 pinctrl-names = "default"; 1388 pinctrl-0 = <&qup_spi3_default>; 1389 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1390 #address-cells = <1>; 1391 #size-cells = <0>; 1392 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1393 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1394 interconnect-names = "qup-core", "qup-config"; 1395 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1396 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1397 dma-names = "tx", "rx"; 1398 status = "disabled"; 1399 }; 1400 1401 uart3: serial@88c000 { 1402 compatible = "qcom,geni-uart"; 1403 reg = <0 0x0088c000 0 0x4000>; 1404 clock-names = "se"; 1405 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1406 pinctrl-names = "default"; 1407 pinctrl-0 = <&qup_uart3_default>; 1408 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1409 power-domains = <&rpmhpd SDM845_CX>; 1410 operating-points-v2 = <&qup_opp_table>; 1411 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1412 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1413 interconnect-names = "qup-core", "qup-config"; 1414 status = "disabled"; 1415 }; 1416 1417 i2c4: i2c@890000 { 1418 compatible = "qcom,geni-i2c"; 1419 reg = <0 0x00890000 0 0x4000>; 1420 clock-names = "se"; 1421 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1422 pinctrl-names = "default"; 1423 pinctrl-0 = <&qup_i2c4_default>; 1424 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1425 #address-cells = <1>; 1426 #size-cells = <0>; 1427 power-domains = <&rpmhpd SDM845_CX>; 1428 operating-points-v2 = <&qup_opp_table>; 1429 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1430 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, 1431 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; 1432 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1433 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1434 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1435 dma-names = "tx", "rx"; 1436 status = "disabled"; 1437 }; 1438 1439 spi4: spi@890000 { 1440 compatible = "qcom,geni-spi"; 1441 reg = <0 0x00890000 0 0x4000>; 1442 clock-names = "se"; 1443 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1444 pinctrl-names = "default"; 1445 pinctrl-0 = <&qup_spi4_default>; 1446 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1447 #address-cells = <1>; 1448 #size-cells = <0>; 1449 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1450 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1451 interconnect-names = "qup-core", "qup-config"; 1452 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1453 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1454 dma-names = "tx", "rx"; 1455 status = "disabled"; 1456 }; 1457 1458 uart4: serial@890000 { 1459 compatible = "qcom,geni-uart"; 1460 reg = <0 0x00890000 0 0x4000>; 1461 clock-names = "se"; 1462 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1463 pinctrl-names = "default"; 1464 pinctrl-0 = <&qup_uart4_default>; 1465 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1466 power-domains = <&rpmhpd SDM845_CX>; 1467 operating-points-v2 = <&qup_opp_table>; 1468 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1469 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1470 interconnect-names = "qup-core", "qup-config"; 1471 status = "disabled"; 1472 }; 1473 1474 i2c5: i2c@894000 { 1475 compatible = "qcom,geni-i2c"; 1476 reg = <0 0x00894000 0 0x4000>; 1477 clock-names = "se"; 1478 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1479 pinctrl-names = "default"; 1480 pinctrl-0 = <&qup_i2c5_default>; 1481 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1482 #address-cells = <1>; 1483 #size-cells = <0>; 1484 power-domains = <&rpmhpd SDM845_CX>; 1485 operating-points-v2 = <&qup_opp_table>; 1486 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1487 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, 1488 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; 1489 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1490 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1491 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1492 dma-names = "tx", "rx"; 1493 status = "disabled"; 1494 }; 1495 1496 spi5: spi@894000 { 1497 compatible = "qcom,geni-spi"; 1498 reg = <0 0x00894000 0 0x4000>; 1499 clock-names = "se"; 1500 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1501 pinctrl-names = "default"; 1502 pinctrl-0 = <&qup_spi5_default>; 1503 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1504 #address-cells = <1>; 1505 #size-cells = <0>; 1506 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1507 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1508 interconnect-names = "qup-core", "qup-config"; 1509 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1510 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1511 dma-names = "tx", "rx"; 1512 status = "disabled"; 1513 }; 1514 1515 uart5: serial@894000 { 1516 compatible = "qcom,geni-uart"; 1517 reg = <0 0x00894000 0 0x4000>; 1518 clock-names = "se"; 1519 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1520 pinctrl-names = "default"; 1521 pinctrl-0 = <&qup_uart5_default>; 1522 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1523 power-domains = <&rpmhpd SDM845_CX>; 1524 operating-points-v2 = <&qup_opp_table>; 1525 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1526 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1527 interconnect-names = "qup-core", "qup-config"; 1528 status = "disabled"; 1529 }; 1530 1531 i2c6: i2c@898000 { 1532 compatible = "qcom,geni-i2c"; 1533 reg = <0 0x00898000 0 0x4000>; 1534 clock-names = "se"; 1535 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1536 pinctrl-names = "default"; 1537 pinctrl-0 = <&qup_i2c6_default>; 1538 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1539 #address-cells = <1>; 1540 #size-cells = <0>; 1541 power-domains = <&rpmhpd SDM845_CX>; 1542 operating-points-v2 = <&qup_opp_table>; 1543 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1544 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, 1545 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; 1546 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1547 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1548 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1549 dma-names = "tx", "rx"; 1550 status = "disabled"; 1551 }; 1552 1553 spi6: spi@898000 { 1554 compatible = "qcom,geni-spi"; 1555 reg = <0 0x00898000 0 0x4000>; 1556 clock-names = "se"; 1557 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1558 pinctrl-names = "default"; 1559 pinctrl-0 = <&qup_spi6_default>; 1560 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1561 #address-cells = <1>; 1562 #size-cells = <0>; 1563 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1564 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1565 interconnect-names = "qup-core", "qup-config"; 1566 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1567 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1568 dma-names = "tx", "rx"; 1569 status = "disabled"; 1570 }; 1571 1572 uart6: serial@898000 { 1573 compatible = "qcom,geni-uart"; 1574 reg = <0 0x00898000 0 0x4000>; 1575 clock-names = "se"; 1576 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1577 pinctrl-names = "default"; 1578 pinctrl-0 = <&qup_uart6_default>; 1579 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1580 power-domains = <&rpmhpd SDM845_CX>; 1581 operating-points-v2 = <&qup_opp_table>; 1582 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1583 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1584 interconnect-names = "qup-core", "qup-config"; 1585 status = "disabled"; 1586 }; 1587 1588 i2c7: i2c@89c000 { 1589 compatible = "qcom,geni-i2c"; 1590 reg = <0 0x0089c000 0 0x4000>; 1591 clock-names = "se"; 1592 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1593 pinctrl-names = "default"; 1594 pinctrl-0 = <&qup_i2c7_default>; 1595 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1596 #address-cells = <1>; 1597 #size-cells = <0>; 1598 power-domains = <&rpmhpd SDM845_CX>; 1599 operating-points-v2 = <&qup_opp_table>; 1600 status = "disabled"; 1601 }; 1602 1603 spi7: spi@89c000 { 1604 compatible = "qcom,geni-spi"; 1605 reg = <0 0x0089c000 0 0x4000>; 1606 clock-names = "se"; 1607 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1608 pinctrl-names = "default"; 1609 pinctrl-0 = <&qup_spi7_default>; 1610 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1611 #address-cells = <1>; 1612 #size-cells = <0>; 1613 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1614 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1615 interconnect-names = "qup-core", "qup-config"; 1616 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1617 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1618 dma-names = "tx", "rx"; 1619 status = "disabled"; 1620 }; 1621 1622 uart7: serial@89c000 { 1623 compatible = "qcom,geni-uart"; 1624 reg = <0 0x0089c000 0 0x4000>; 1625 clock-names = "se"; 1626 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1627 pinctrl-names = "default"; 1628 pinctrl-0 = <&qup_uart7_default>; 1629 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1630 power-domains = <&rpmhpd SDM845_CX>; 1631 operating-points-v2 = <&qup_opp_table>; 1632 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1633 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1634 interconnect-names = "qup-core", "qup-config"; 1635 status = "disabled"; 1636 }; 1637 }; 1638 1639 gpi_dma1: dma-controller@0xa00000 { 1640 #dma-cells = <3>; 1641 compatible = "qcom,sdm845-gpi-dma"; 1642 reg = <0 0x00a00000 0 0x60000>; 1643 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1644 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1645 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1646 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1647 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1648 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1649 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1650 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1651 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1652 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1653 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1654 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 1655 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 1656 dma-channels = <13>; 1657 dma-channel-mask = <0xfa>; 1658 iommus = <&apps_smmu 0x06d6 0x0>; 1659 status = "disabled"; 1660 }; 1661 1662 qupv3_id_1: geniqup@ac0000 { 1663 compatible = "qcom,geni-se-qup"; 1664 reg = <0 0x00ac0000 0 0x6000>; 1665 clock-names = "m-ahb", "s-ahb"; 1666 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1667 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1668 iommus = <&apps_smmu 0x6c3 0x0>; 1669 #address-cells = <2>; 1670 #size-cells = <2>; 1671 ranges; 1672 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>; 1673 interconnect-names = "qup-core"; 1674 status = "disabled"; 1675 1676 i2c8: i2c@a80000 { 1677 compatible = "qcom,geni-i2c"; 1678 reg = <0 0x00a80000 0 0x4000>; 1679 clock-names = "se"; 1680 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1681 pinctrl-names = "default"; 1682 pinctrl-0 = <&qup_i2c8_default>; 1683 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1684 #address-cells = <1>; 1685 #size-cells = <0>; 1686 power-domains = <&rpmhpd SDM845_CX>; 1687 operating-points-v2 = <&qup_opp_table>; 1688 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1689 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 1690 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 1691 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1692 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1693 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1694 dma-names = "tx", "rx"; 1695 status = "disabled"; 1696 }; 1697 1698 spi8: spi@a80000 { 1699 compatible = "qcom,geni-spi"; 1700 reg = <0 0x00a80000 0 0x4000>; 1701 clock-names = "se"; 1702 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1703 pinctrl-names = "default"; 1704 pinctrl-0 = <&qup_spi8_default>; 1705 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1706 #address-cells = <1>; 1707 #size-cells = <0>; 1708 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1709 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1710 interconnect-names = "qup-core", "qup-config"; 1711 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1712 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1713 dma-names = "tx", "rx"; 1714 status = "disabled"; 1715 }; 1716 1717 uart8: serial@a80000 { 1718 compatible = "qcom,geni-uart"; 1719 reg = <0 0x00a80000 0 0x4000>; 1720 clock-names = "se"; 1721 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1722 pinctrl-names = "default"; 1723 pinctrl-0 = <&qup_uart8_default>; 1724 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1725 power-domains = <&rpmhpd SDM845_CX>; 1726 operating-points-v2 = <&qup_opp_table>; 1727 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1728 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1729 interconnect-names = "qup-core", "qup-config"; 1730 status = "disabled"; 1731 }; 1732 1733 i2c9: i2c@a84000 { 1734 compatible = "qcom,geni-i2c"; 1735 reg = <0 0x00a84000 0 0x4000>; 1736 clock-names = "se"; 1737 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1738 pinctrl-names = "default"; 1739 pinctrl-0 = <&qup_i2c9_default>; 1740 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1741 #address-cells = <1>; 1742 #size-cells = <0>; 1743 power-domains = <&rpmhpd SDM845_CX>; 1744 operating-points-v2 = <&qup_opp_table>; 1745 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1746 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 1747 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 1748 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1749 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1750 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1751 dma-names = "tx", "rx"; 1752 status = "disabled"; 1753 }; 1754 1755 spi9: spi@a84000 { 1756 compatible = "qcom,geni-spi"; 1757 reg = <0 0x00a84000 0 0x4000>; 1758 clock-names = "se"; 1759 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1760 pinctrl-names = "default"; 1761 pinctrl-0 = <&qup_spi9_default>; 1762 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1763 #address-cells = <1>; 1764 #size-cells = <0>; 1765 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1766 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1767 interconnect-names = "qup-core", "qup-config"; 1768 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1769 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1770 dma-names = "tx", "rx"; 1771 status = "disabled"; 1772 }; 1773 1774 uart9: serial@a84000 { 1775 compatible = "qcom,geni-debug-uart"; 1776 reg = <0 0x00a84000 0 0x4000>; 1777 clock-names = "se"; 1778 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1779 pinctrl-names = "default"; 1780 pinctrl-0 = <&qup_uart9_default>; 1781 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1782 power-domains = <&rpmhpd SDM845_CX>; 1783 operating-points-v2 = <&qup_opp_table>; 1784 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1785 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1786 interconnect-names = "qup-core", "qup-config"; 1787 status = "disabled"; 1788 }; 1789 1790 i2c10: i2c@a88000 { 1791 compatible = "qcom,geni-i2c"; 1792 reg = <0 0x00a88000 0 0x4000>; 1793 clock-names = "se"; 1794 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1795 pinctrl-names = "default"; 1796 pinctrl-0 = <&qup_i2c10_default>; 1797 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1798 #address-cells = <1>; 1799 #size-cells = <0>; 1800 power-domains = <&rpmhpd SDM845_CX>; 1801 operating-points-v2 = <&qup_opp_table>; 1802 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1803 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 1804 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 1805 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1806 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1807 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1808 dma-names = "tx", "rx"; 1809 status = "disabled"; 1810 }; 1811 1812 spi10: spi@a88000 { 1813 compatible = "qcom,geni-spi"; 1814 reg = <0 0x00a88000 0 0x4000>; 1815 clock-names = "se"; 1816 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1817 pinctrl-names = "default"; 1818 pinctrl-0 = <&qup_spi10_default>; 1819 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1820 #address-cells = <1>; 1821 #size-cells = <0>; 1822 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1823 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1824 interconnect-names = "qup-core", "qup-config"; 1825 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1826 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1827 dma-names = "tx", "rx"; 1828 status = "disabled"; 1829 }; 1830 1831 uart10: serial@a88000 { 1832 compatible = "qcom,geni-uart"; 1833 reg = <0 0x00a88000 0 0x4000>; 1834 clock-names = "se"; 1835 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1836 pinctrl-names = "default"; 1837 pinctrl-0 = <&qup_uart10_default>; 1838 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1839 power-domains = <&rpmhpd SDM845_CX>; 1840 operating-points-v2 = <&qup_opp_table>; 1841 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1842 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1843 interconnect-names = "qup-core", "qup-config"; 1844 status = "disabled"; 1845 }; 1846 1847 i2c11: i2c@a8c000 { 1848 compatible = "qcom,geni-i2c"; 1849 reg = <0 0x00a8c000 0 0x4000>; 1850 clock-names = "se"; 1851 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1852 pinctrl-names = "default"; 1853 pinctrl-0 = <&qup_i2c11_default>; 1854 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1855 #address-cells = <1>; 1856 #size-cells = <0>; 1857 power-domains = <&rpmhpd SDM845_CX>; 1858 operating-points-v2 = <&qup_opp_table>; 1859 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1860 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 1861 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 1862 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1863 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1864 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1865 dma-names = "tx", "rx"; 1866 status = "disabled"; 1867 }; 1868 1869 spi11: spi@a8c000 { 1870 compatible = "qcom,geni-spi"; 1871 reg = <0 0x00a8c000 0 0x4000>; 1872 clock-names = "se"; 1873 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1874 pinctrl-names = "default"; 1875 pinctrl-0 = <&qup_spi11_default>; 1876 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1877 #address-cells = <1>; 1878 #size-cells = <0>; 1879 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1880 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1881 interconnect-names = "qup-core", "qup-config"; 1882 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1883 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1884 dma-names = "tx", "rx"; 1885 status = "disabled"; 1886 }; 1887 1888 uart11: serial@a8c000 { 1889 compatible = "qcom,geni-uart"; 1890 reg = <0 0x00a8c000 0 0x4000>; 1891 clock-names = "se"; 1892 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1893 pinctrl-names = "default"; 1894 pinctrl-0 = <&qup_uart11_default>; 1895 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1896 power-domains = <&rpmhpd SDM845_CX>; 1897 operating-points-v2 = <&qup_opp_table>; 1898 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1899 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1900 interconnect-names = "qup-core", "qup-config"; 1901 status = "disabled"; 1902 }; 1903 1904 i2c12: i2c@a90000 { 1905 compatible = "qcom,geni-i2c"; 1906 reg = <0 0x00a90000 0 0x4000>; 1907 clock-names = "se"; 1908 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1909 pinctrl-names = "default"; 1910 pinctrl-0 = <&qup_i2c12_default>; 1911 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1912 #address-cells = <1>; 1913 #size-cells = <0>; 1914 power-domains = <&rpmhpd SDM845_CX>; 1915 operating-points-v2 = <&qup_opp_table>; 1916 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1917 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 1918 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 1919 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1920 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1921 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1922 dma-names = "tx", "rx"; 1923 status = "disabled"; 1924 }; 1925 1926 spi12: spi@a90000 { 1927 compatible = "qcom,geni-spi"; 1928 reg = <0 0x00a90000 0 0x4000>; 1929 clock-names = "se"; 1930 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1931 pinctrl-names = "default"; 1932 pinctrl-0 = <&qup_spi12_default>; 1933 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1934 #address-cells = <1>; 1935 #size-cells = <0>; 1936 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1937 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1938 interconnect-names = "qup-core", "qup-config"; 1939 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1940 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1941 dma-names = "tx", "rx"; 1942 status = "disabled"; 1943 }; 1944 1945 uart12: serial@a90000 { 1946 compatible = "qcom,geni-uart"; 1947 reg = <0 0x00a90000 0 0x4000>; 1948 clock-names = "se"; 1949 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1950 pinctrl-names = "default"; 1951 pinctrl-0 = <&qup_uart12_default>; 1952 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1953 power-domains = <&rpmhpd SDM845_CX>; 1954 operating-points-v2 = <&qup_opp_table>; 1955 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1956 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1957 interconnect-names = "qup-core", "qup-config"; 1958 status = "disabled"; 1959 }; 1960 1961 i2c13: i2c@a94000 { 1962 compatible = "qcom,geni-i2c"; 1963 reg = <0 0x00a94000 0 0x4000>; 1964 clock-names = "se"; 1965 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1966 pinctrl-names = "default"; 1967 pinctrl-0 = <&qup_i2c13_default>; 1968 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1969 #address-cells = <1>; 1970 #size-cells = <0>; 1971 power-domains = <&rpmhpd SDM845_CX>; 1972 operating-points-v2 = <&qup_opp_table>; 1973 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1974 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 1975 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 1976 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1977 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1978 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1979 dma-names = "tx", "rx"; 1980 status = "disabled"; 1981 }; 1982 1983 spi13: spi@a94000 { 1984 compatible = "qcom,geni-spi"; 1985 reg = <0 0x00a94000 0 0x4000>; 1986 clock-names = "se"; 1987 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1988 pinctrl-names = "default"; 1989 pinctrl-0 = <&qup_spi13_default>; 1990 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1991 #address-cells = <1>; 1992 #size-cells = <0>; 1993 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1994 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1995 interconnect-names = "qup-core", "qup-config"; 1996 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1997 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1998 dma-names = "tx", "rx"; 1999 status = "disabled"; 2000 }; 2001 2002 uart13: serial@a94000 { 2003 compatible = "qcom,geni-uart"; 2004 reg = <0 0x00a94000 0 0x4000>; 2005 clock-names = "se"; 2006 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 2007 pinctrl-names = "default"; 2008 pinctrl-0 = <&qup_uart13_default>; 2009 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 2010 power-domains = <&rpmhpd SDM845_CX>; 2011 operating-points-v2 = <&qup_opp_table>; 2012 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2013 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 2014 interconnect-names = "qup-core", "qup-config"; 2015 status = "disabled"; 2016 }; 2017 2018 i2c14: i2c@a98000 { 2019 compatible = "qcom,geni-i2c"; 2020 reg = <0 0x00a98000 0 0x4000>; 2021 clock-names = "se"; 2022 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2023 pinctrl-names = "default"; 2024 pinctrl-0 = <&qup_i2c14_default>; 2025 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 2026 #address-cells = <1>; 2027 #size-cells = <0>; 2028 power-domains = <&rpmhpd SDM845_CX>; 2029 operating-points-v2 = <&qup_opp_table>; 2030 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2031 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 2032 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 2033 interconnect-names = "qup-core", "qup-config", "qup-memory"; 2034 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 2035 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 2036 dma-names = "tx", "rx"; 2037 status = "disabled"; 2038 }; 2039 2040 spi14: spi@a98000 { 2041 compatible = "qcom,geni-spi"; 2042 reg = <0 0x00a98000 0 0x4000>; 2043 clock-names = "se"; 2044 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2045 pinctrl-names = "default"; 2046 pinctrl-0 = <&qup_spi14_default>; 2047 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 2048 #address-cells = <1>; 2049 #size-cells = <0>; 2050 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2051 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 2052 interconnect-names = "qup-core", "qup-config"; 2053 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 2054 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 2055 dma-names = "tx", "rx"; 2056 status = "disabled"; 2057 }; 2058 2059 uart14: serial@a98000 { 2060 compatible = "qcom,geni-uart"; 2061 reg = <0 0x00a98000 0 0x4000>; 2062 clock-names = "se"; 2063 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2064 pinctrl-names = "default"; 2065 pinctrl-0 = <&qup_uart14_default>; 2066 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 2067 power-domains = <&rpmhpd SDM845_CX>; 2068 operating-points-v2 = <&qup_opp_table>; 2069 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2070 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 2071 interconnect-names = "qup-core", "qup-config"; 2072 status = "disabled"; 2073 }; 2074 2075 i2c15: i2c@a9c000 { 2076 compatible = "qcom,geni-i2c"; 2077 reg = <0 0x00a9c000 0 0x4000>; 2078 clock-names = "se"; 2079 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2080 pinctrl-names = "default"; 2081 pinctrl-0 = <&qup_i2c15_default>; 2082 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 2083 #address-cells = <1>; 2084 #size-cells = <0>; 2085 power-domains = <&rpmhpd SDM845_CX>; 2086 operating-points-v2 = <&qup_opp_table>; 2087 status = "disabled"; 2088 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2089 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 2090 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 2091 interconnect-names = "qup-core", "qup-config", "qup-memory"; 2092 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, 2093 <&gpi_dma1 1 7 QCOM_GPI_I2C>; 2094 dma-names = "tx", "rx"; 2095 }; 2096 2097 spi15: spi@a9c000 { 2098 compatible = "qcom,geni-spi"; 2099 reg = <0 0x00a9c000 0 0x4000>; 2100 clock-names = "se"; 2101 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2102 pinctrl-names = "default"; 2103 pinctrl-0 = <&qup_spi15_default>; 2104 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 2105 #address-cells = <1>; 2106 #size-cells = <0>; 2107 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2108 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 2109 interconnect-names = "qup-core", "qup-config"; 2110 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, 2111 <&gpi_dma1 1 7 QCOM_GPI_SPI>; 2112 dma-names = "tx", "rx"; 2113 status = "disabled"; 2114 }; 2115 2116 uart15: serial@a9c000 { 2117 compatible = "qcom,geni-uart"; 2118 reg = <0 0x00a9c000 0 0x4000>; 2119 clock-names = "se"; 2120 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2121 pinctrl-names = "default"; 2122 pinctrl-0 = <&qup_uart15_default>; 2123 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 2124 power-domains = <&rpmhpd SDM845_CX>; 2125 operating-points-v2 = <&qup_opp_table>; 2126 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2127 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 2128 interconnect-names = "qup-core", "qup-config"; 2129 status = "disabled"; 2130 }; 2131 }; 2132 2133 llcc: system-cache-controller@1100000 { 2134 compatible = "qcom,sdm845-llcc"; 2135 reg = <0 0x01100000 0 0x31000>, <0 0x01300000 0 0x50000>; 2136 reg-names = "llcc_base", "llcc_broadcast_base"; 2137 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 2138 }; 2139 2140 pmu@114a000 { 2141 compatible = "qcom,sdm845-llcc-bwmon"; 2142 reg = <0 0x0114a000 0 0x1000>; 2143 interrupts = <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>; 2144 interconnects = <&mem_noc MASTER_LLCC 3 &mem_noc SLAVE_EBI1 3>; 2145 2146 operating-points-v2 = <&llcc_bwmon_opp_table>; 2147 2148 llcc_bwmon_opp_table: opp-table { 2149 compatible = "operating-points-v2"; 2150 2151 /* 2152 * The interconnect path bandwidth taken from 2153 * cpu4_opp_table bandwidth for gladiator_noc-mem_noc 2154 * interconnect. This also matches the 2155 * bandwidth table of qcom,llccbw (qcom,bw-tbl, 2156 * bus width: 4 bytes) from msm-4.9 downstream 2157 * kernel. 2158 */ 2159 opp-0 { 2160 opp-peak-kBps = <800000>; 2161 }; 2162 opp-1 { 2163 opp-peak-kBps = <1804000>; 2164 }; 2165 opp-2 { 2166 opp-peak-kBps = <3072000>; 2167 }; 2168 opp-3 { 2169 opp-peak-kBps = <5412000>; 2170 }; 2171 opp-4 { 2172 opp-peak-kBps = <7216000>; 2173 }; 2174 }; 2175 }; 2176 2177 pmu@1436400 { 2178 compatible = "qcom,sdm845-bwmon", "qcom,msm8998-bwmon"; 2179 reg = <0 0x01436400 0 0x600>; 2180 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 2181 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_LLCC 3>; 2182 2183 operating-points-v2 = <&cpu_bwmon_opp_table>; 2184 2185 cpu_bwmon_opp_table: opp-table { 2186 compatible = "operating-points-v2"; 2187 2188 /* 2189 * The interconnect path bandwidth taken from 2190 * cpu4_opp_table bandwidth for OSM L3 2191 * interconnect. This also matches the OSM L3 2192 * from bandwidth table of qcom,cpu4-l3lat-mon 2193 * (qcom,core-dev-table, bus width: 16 bytes) 2194 * from msm-4.9 downstream kernel. 2195 */ 2196 opp-0 { 2197 opp-peak-kBps = <4800000>; 2198 }; 2199 opp-1 { 2200 opp-peak-kBps = <9216000>; 2201 }; 2202 opp-2 { 2203 opp-peak-kBps = <15052800>; 2204 }; 2205 opp-3 { 2206 opp-peak-kBps = <20889600>; 2207 }; 2208 opp-4 { 2209 opp-peak-kBps = <25497600>; 2210 }; 2211 }; 2212 }; 2213 2214 pcie0: pci@1c00000 { 2215 compatible = "qcom,pcie-sdm845"; 2216 reg = <0 0x01c00000 0 0x2000>, 2217 <0 0x60000000 0 0xf1d>, 2218 <0 0x60000f20 0 0xa8>, 2219 <0 0x60100000 0 0x100000>; 2220 reg-names = "parf", "dbi", "elbi", "config"; 2221 device_type = "pci"; 2222 linux,pci-domain = <0>; 2223 bus-range = <0x00 0xff>; 2224 num-lanes = <1>; 2225 2226 #address-cells = <3>; 2227 #size-cells = <2>; 2228 2229 ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>, 2230 <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0xd00000>; 2231 2232 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 2233 interrupt-names = "msi"; 2234 #interrupt-cells = <1>; 2235 interrupt-map-mask = <0 0 0 0x7>; 2236 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 2237 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 2238 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 2239 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 2240 2241 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 2242 <&gcc GCC_PCIE_0_AUX_CLK>, 2243 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 2244 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 2245 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 2246 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 2247 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; 2248 clock-names = "pipe", 2249 "aux", 2250 "cfg", 2251 "bus_master", 2252 "bus_slave", 2253 "slave_q2a", 2254 "tbu"; 2255 2256 iommus = <&apps_smmu 0x1c10 0xf>; 2257 iommu-map = <0x0 &apps_smmu 0x1c10 0x1>, 2258 <0x100 &apps_smmu 0x1c11 0x1>, 2259 <0x200 &apps_smmu 0x1c12 0x1>, 2260 <0x300 &apps_smmu 0x1c13 0x1>, 2261 <0x400 &apps_smmu 0x1c14 0x1>, 2262 <0x500 &apps_smmu 0x1c15 0x1>, 2263 <0x600 &apps_smmu 0x1c16 0x1>, 2264 <0x700 &apps_smmu 0x1c17 0x1>, 2265 <0x800 &apps_smmu 0x1c18 0x1>, 2266 <0x900 &apps_smmu 0x1c19 0x1>, 2267 <0xa00 &apps_smmu 0x1c1a 0x1>, 2268 <0xb00 &apps_smmu 0x1c1b 0x1>, 2269 <0xc00 &apps_smmu 0x1c1c 0x1>, 2270 <0xd00 &apps_smmu 0x1c1d 0x1>, 2271 <0xe00 &apps_smmu 0x1c1e 0x1>, 2272 <0xf00 &apps_smmu 0x1c1f 0x1>; 2273 2274 resets = <&gcc GCC_PCIE_0_BCR>; 2275 reset-names = "pci"; 2276 2277 power-domains = <&gcc PCIE_0_GDSC>; 2278 2279 phys = <&pcie0_lane>; 2280 phy-names = "pciephy"; 2281 2282 status = "disabled"; 2283 }; 2284 2285 pcie0_phy: phy@1c06000 { 2286 compatible = "qcom,sdm845-qmp-pcie-phy"; 2287 reg = <0 0x01c06000 0 0x18c>; 2288 #address-cells = <2>; 2289 #size-cells = <2>; 2290 ranges; 2291 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 2292 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 2293 <&gcc GCC_PCIE_0_CLKREF_CLK>, 2294 <&gcc GCC_PCIE_PHY_REFGEN_CLK>; 2295 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 2296 2297 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 2298 reset-names = "phy"; 2299 2300 assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>; 2301 assigned-clock-rates = <100000000>; 2302 2303 status = "disabled"; 2304 2305 pcie0_lane: phy@1c06200 { 2306 reg = <0 0x01c06200 0 0x128>, 2307 <0 0x01c06400 0 0x1fc>, 2308 <0 0x01c06800 0 0x218>, 2309 <0 0x01c06600 0 0x70>; 2310 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 2311 clock-names = "pipe0"; 2312 2313 #clock-cells = <0>; 2314 #phy-cells = <0>; 2315 clock-output-names = "pcie_0_pipe_clk"; 2316 }; 2317 }; 2318 2319 pcie1: pci@1c08000 { 2320 compatible = "qcom,pcie-sdm845"; 2321 reg = <0 0x01c08000 0 0x2000>, 2322 <0 0x40000000 0 0xf1d>, 2323 <0 0x40000f20 0 0xa8>, 2324 <0 0x40100000 0 0x100000>; 2325 reg-names = "parf", "dbi", "elbi", "config"; 2326 device_type = "pci"; 2327 linux,pci-domain = <1>; 2328 bus-range = <0x00 0xff>; 2329 num-lanes = <1>; 2330 2331 #address-cells = <3>; 2332 #size-cells = <2>; 2333 2334 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, 2335 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 2336 2337 interrupts = <GIC_SPI 307 IRQ_TYPE_EDGE_RISING>; 2338 interrupt-names = "msi"; 2339 #interrupt-cells = <1>; 2340 interrupt-map-mask = <0 0 0 0x7>; 2341 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 2342 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 2343 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 2344 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 2345 2346 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 2347 <&gcc GCC_PCIE_1_AUX_CLK>, 2348 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2349 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 2350 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 2351 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 2352 <&gcc GCC_PCIE_1_CLKREF_CLK>, 2353 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; 2354 clock-names = "pipe", 2355 "aux", 2356 "cfg", 2357 "bus_master", 2358 "bus_slave", 2359 "slave_q2a", 2360 "ref", 2361 "tbu"; 2362 2363 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 2364 assigned-clock-rates = <19200000>; 2365 2366 iommus = <&apps_smmu 0x1c00 0xf>; 2367 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, 2368 <0x100 &apps_smmu 0x1c01 0x1>, 2369 <0x200 &apps_smmu 0x1c02 0x1>, 2370 <0x300 &apps_smmu 0x1c03 0x1>, 2371 <0x400 &apps_smmu 0x1c04 0x1>, 2372 <0x500 &apps_smmu 0x1c05 0x1>, 2373 <0x600 &apps_smmu 0x1c06 0x1>, 2374 <0x700 &apps_smmu 0x1c07 0x1>, 2375 <0x800 &apps_smmu 0x1c08 0x1>, 2376 <0x900 &apps_smmu 0x1c09 0x1>, 2377 <0xa00 &apps_smmu 0x1c0a 0x1>, 2378 <0xb00 &apps_smmu 0x1c0b 0x1>, 2379 <0xc00 &apps_smmu 0x1c0c 0x1>, 2380 <0xd00 &apps_smmu 0x1c0d 0x1>, 2381 <0xe00 &apps_smmu 0x1c0e 0x1>, 2382 <0xf00 &apps_smmu 0x1c0f 0x1>; 2383 2384 resets = <&gcc GCC_PCIE_1_BCR>; 2385 reset-names = "pci"; 2386 2387 power-domains = <&gcc PCIE_1_GDSC>; 2388 2389 phys = <&pcie1_lane>; 2390 phy-names = "pciephy"; 2391 2392 status = "disabled"; 2393 }; 2394 2395 pcie1_phy: phy@1c0a000 { 2396 compatible = "qcom,sdm845-qhp-pcie-phy"; 2397 reg = <0 0x01c0a000 0 0x800>; 2398 #address-cells = <2>; 2399 #size-cells = <2>; 2400 ranges; 2401 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 2402 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2403 <&gcc GCC_PCIE_1_CLKREF_CLK>, 2404 <&gcc GCC_PCIE_PHY_REFGEN_CLK>; 2405 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 2406 2407 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 2408 reset-names = "phy"; 2409 2410 assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>; 2411 assigned-clock-rates = <100000000>; 2412 2413 status = "disabled"; 2414 2415 pcie1_lane: phy@1c06200 { 2416 reg = <0 0x01c0a800 0 0x800>, 2417 <0 0x01c0a800 0 0x800>, 2418 <0 0x01c0b800 0 0x400>; 2419 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 2420 clock-names = "pipe0"; 2421 2422 #clock-cells = <0>; 2423 #phy-cells = <0>; 2424 clock-output-names = "pcie_1_pipe_clk"; 2425 }; 2426 }; 2427 2428 mem_noc: interconnect@1380000 { 2429 compatible = "qcom,sdm845-mem-noc"; 2430 reg = <0 0x01380000 0 0x27200>; 2431 #interconnect-cells = <2>; 2432 qcom,bcm-voters = <&apps_bcm_voter>; 2433 }; 2434 2435 dc_noc: interconnect@14e0000 { 2436 compatible = "qcom,sdm845-dc-noc"; 2437 reg = <0 0x014e0000 0 0x400>; 2438 #interconnect-cells = <2>; 2439 qcom,bcm-voters = <&apps_bcm_voter>; 2440 }; 2441 2442 config_noc: interconnect@1500000 { 2443 compatible = "qcom,sdm845-config-noc"; 2444 reg = <0 0x01500000 0 0x5080>; 2445 #interconnect-cells = <2>; 2446 qcom,bcm-voters = <&apps_bcm_voter>; 2447 }; 2448 2449 system_noc: interconnect@1620000 { 2450 compatible = "qcom,sdm845-system-noc"; 2451 reg = <0 0x01620000 0 0x18080>; 2452 #interconnect-cells = <2>; 2453 qcom,bcm-voters = <&apps_bcm_voter>; 2454 }; 2455 2456 aggre1_noc: interconnect@16e0000 { 2457 compatible = "qcom,sdm845-aggre1-noc"; 2458 reg = <0 0x016e0000 0 0x15080>; 2459 #interconnect-cells = <2>; 2460 qcom,bcm-voters = <&apps_bcm_voter>; 2461 }; 2462 2463 aggre2_noc: interconnect@1700000 { 2464 compatible = "qcom,sdm845-aggre2-noc"; 2465 reg = <0 0x01700000 0 0x1f300>; 2466 #interconnect-cells = <2>; 2467 qcom,bcm-voters = <&apps_bcm_voter>; 2468 }; 2469 2470 mmss_noc: interconnect@1740000 { 2471 compatible = "qcom,sdm845-mmss-noc"; 2472 reg = <0 0x01740000 0 0x1c100>; 2473 #interconnect-cells = <2>; 2474 qcom,bcm-voters = <&apps_bcm_voter>; 2475 }; 2476 2477 ufs_mem_hc: ufshc@1d84000 { 2478 compatible = "qcom,sdm845-ufshc", "qcom,ufshc", 2479 "jedec,ufs-2.0"; 2480 reg = <0 0x01d84000 0 0x2500>, 2481 <0 0x01d90000 0 0x8000>; 2482 reg-names = "std", "ice"; 2483 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2484 phys = <&ufs_mem_phy_lanes>; 2485 phy-names = "ufsphy"; 2486 lanes-per-direction = <2>; 2487 power-domains = <&gcc UFS_PHY_GDSC>; 2488 #reset-cells = <1>; 2489 resets = <&gcc GCC_UFS_PHY_BCR>; 2490 reset-names = "rst"; 2491 2492 iommus = <&apps_smmu 0x100 0xf>; 2493 2494 clock-names = 2495 "core_clk", 2496 "bus_aggr_clk", 2497 "iface_clk", 2498 "core_clk_unipro", 2499 "ref_clk", 2500 "tx_lane0_sync_clk", 2501 "rx_lane0_sync_clk", 2502 "rx_lane1_sync_clk", 2503 "ice_core_clk"; 2504 clocks = 2505 <&gcc GCC_UFS_PHY_AXI_CLK>, 2506 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2507 <&gcc GCC_UFS_PHY_AHB_CLK>, 2508 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2509 <&rpmhcc RPMH_CXO_CLK>, 2510 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2511 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2512 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, 2513 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 2514 freq-table-hz = 2515 <50000000 200000000>, 2516 <0 0>, 2517 <0 0>, 2518 <37500000 150000000>, 2519 <0 0>, 2520 <0 0>, 2521 <0 0>, 2522 <0 0>, 2523 <0 300000000>; 2524 2525 status = "disabled"; 2526 }; 2527 2528 ufs_mem_phy: phy@1d87000 { 2529 compatible = "qcom,sdm845-qmp-ufs-phy"; 2530 reg = <0 0x01d87000 0 0x18c>; 2531 #address-cells = <2>; 2532 #size-cells = <2>; 2533 ranges; 2534 clock-names = "ref", 2535 "ref_aux"; 2536 clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, 2537 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 2538 2539 resets = <&ufs_mem_hc 0>; 2540 reset-names = "ufsphy"; 2541 status = "disabled"; 2542 2543 ufs_mem_phy_lanes: phy@1d87400 { 2544 reg = <0 0x01d87400 0 0x108>, 2545 <0 0x01d87600 0 0x1e0>, 2546 <0 0x01d87c00 0 0x1dc>, 2547 <0 0x01d87800 0 0x108>, 2548 <0 0x01d87a00 0 0x1e0>; 2549 #phy-cells = <0>; 2550 }; 2551 }; 2552 2553 cryptobam: dma-controller@1dc4000 { 2554 compatible = "qcom,bam-v1.7.0"; 2555 reg = <0 0x01dc4000 0 0x24000>; 2556 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 2557 clocks = <&rpmhcc RPMH_CE_CLK>; 2558 clock-names = "bam_clk"; 2559 #dma-cells = <1>; 2560 qcom,ee = <0>; 2561 qcom,controlled-remotely; 2562 iommus = <&apps_smmu 0x704 0x1>, 2563 <&apps_smmu 0x706 0x1>, 2564 <&apps_smmu 0x714 0x1>, 2565 <&apps_smmu 0x716 0x1>; 2566 }; 2567 2568 crypto: crypto@1dfa000 { 2569 compatible = "qcom,crypto-v5.4"; 2570 reg = <0 0x01dfa000 0 0x6000>; 2571 clocks = <&gcc GCC_CE1_AHB_CLK>, 2572 <&gcc GCC_CE1_AXI_CLK>, 2573 <&rpmhcc RPMH_CE_CLK>; 2574 clock-names = "iface", "bus", "core"; 2575 dmas = <&cryptobam 6>, <&cryptobam 7>; 2576 dma-names = "rx", "tx"; 2577 iommus = <&apps_smmu 0x704 0x1>, 2578 <&apps_smmu 0x706 0x1>, 2579 <&apps_smmu 0x714 0x1>, 2580 <&apps_smmu 0x716 0x1>; 2581 }; 2582 2583 ipa: ipa@1e40000 { 2584 compatible = "qcom,sdm845-ipa"; 2585 2586 iommus = <&apps_smmu 0x720 0x0>, 2587 <&apps_smmu 0x722 0x0>; 2588 reg = <0 0x1e40000 0 0x7000>, 2589 <0 0x1e47000 0 0x2000>, 2590 <0 0x1e04000 0 0x2c000>; 2591 reg-names = "ipa-reg", 2592 "ipa-shared", 2593 "gsi"; 2594 2595 interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>, 2596 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 2597 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2598 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 2599 interrupt-names = "ipa", 2600 "gsi", 2601 "ipa-clock-query", 2602 "ipa-setup-ready"; 2603 2604 clocks = <&rpmhcc RPMH_IPA_CLK>; 2605 clock-names = "core"; 2606 2607 interconnects = <&aggre2_noc MASTER_IPA 0 &mem_noc SLAVE_EBI1 0>, 2608 <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>, 2609 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>; 2610 interconnect-names = "memory", 2611 "imem", 2612 "config"; 2613 2614 qcom,smem-states = <&ipa_smp2p_out 0>, 2615 <&ipa_smp2p_out 1>; 2616 qcom,smem-state-names = "ipa-clock-enabled-valid", 2617 "ipa-clock-enabled"; 2618 2619 status = "disabled"; 2620 }; 2621 2622 tcsr_mutex: hwlock@1f40000 { 2623 compatible = "qcom,tcsr-mutex"; 2624 reg = <0 0x01f40000 0 0x20000>; 2625 #hwlock-cells = <1>; 2626 }; 2627 2628 tcsr_regs_1: syscon@1f60000 { 2629 compatible = "qcom,sdm845-tcsr", "syscon"; 2630 reg = <0 0x01f60000 0 0x20000>; 2631 }; 2632 2633 tlmm: pinctrl@3400000 { 2634 compatible = "qcom,sdm845-pinctrl"; 2635 reg = <0 0x03400000 0 0xc00000>; 2636 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 2637 gpio-controller; 2638 #gpio-cells = <2>; 2639 interrupt-controller; 2640 #interrupt-cells = <2>; 2641 gpio-ranges = <&tlmm 0 0 151>; 2642 wakeup-parent = <&pdc_intc>; 2643 2644 cci0_default: cci0-default { 2645 /* SDA, SCL */ 2646 pins = "gpio17", "gpio18"; 2647 function = "cci_i2c"; 2648 2649 bias-pull-up; 2650 drive-strength = <2>; /* 2 mA */ 2651 }; 2652 2653 cci0_sleep: cci0-sleep { 2654 /* SDA, SCL */ 2655 pins = "gpio17", "gpio18"; 2656 function = "cci_i2c"; 2657 2658 drive-strength = <2>; /* 2 mA */ 2659 bias-pull-down; 2660 }; 2661 2662 cci1_default: cci1-default { 2663 /* SDA, SCL */ 2664 pins = "gpio19", "gpio20"; 2665 function = "cci_i2c"; 2666 2667 bias-pull-up; 2668 drive-strength = <2>; /* 2 mA */ 2669 }; 2670 2671 cci1_sleep: cci1-sleep { 2672 /* SDA, SCL */ 2673 pins = "gpio19", "gpio20"; 2674 function = "cci_i2c"; 2675 2676 drive-strength = <2>; /* 2 mA */ 2677 bias-pull-down; 2678 }; 2679 2680 qspi_clk: qspi-clk { 2681 pinmux { 2682 pins = "gpio95"; 2683 function = "qspi_clk"; 2684 }; 2685 }; 2686 2687 qspi_cs0: qspi-cs0 { 2688 pinmux { 2689 pins = "gpio90"; 2690 function = "qspi_cs"; 2691 }; 2692 }; 2693 2694 qspi_cs1: qspi-cs1 { 2695 pinmux { 2696 pins = "gpio89"; 2697 function = "qspi_cs"; 2698 }; 2699 }; 2700 2701 qspi_data01: qspi-data01 { 2702 pinmux-data { 2703 pins = "gpio91", "gpio92"; 2704 function = "qspi_data"; 2705 }; 2706 }; 2707 2708 qspi_data12: qspi-data12 { 2709 pinmux-data { 2710 pins = "gpio93", "gpio94"; 2711 function = "qspi_data"; 2712 }; 2713 }; 2714 2715 qup_i2c0_default: qup-i2c0-default { 2716 pinmux { 2717 pins = "gpio0", "gpio1"; 2718 function = "qup0"; 2719 }; 2720 }; 2721 2722 qup_i2c1_default: qup-i2c1-default { 2723 pinmux { 2724 pins = "gpio17", "gpio18"; 2725 function = "qup1"; 2726 }; 2727 }; 2728 2729 qup_i2c2_default: qup-i2c2-default { 2730 pinmux { 2731 pins = "gpio27", "gpio28"; 2732 function = "qup2"; 2733 }; 2734 }; 2735 2736 qup_i2c3_default: qup-i2c3-default { 2737 pinmux { 2738 pins = "gpio41", "gpio42"; 2739 function = "qup3"; 2740 }; 2741 }; 2742 2743 qup_i2c4_default: qup-i2c4-default { 2744 pinmux { 2745 pins = "gpio89", "gpio90"; 2746 function = "qup4"; 2747 }; 2748 }; 2749 2750 qup_i2c5_default: qup-i2c5-default { 2751 pinmux { 2752 pins = "gpio85", "gpio86"; 2753 function = "qup5"; 2754 }; 2755 }; 2756 2757 qup_i2c6_default: qup-i2c6-default { 2758 pinmux { 2759 pins = "gpio45", "gpio46"; 2760 function = "qup6"; 2761 }; 2762 }; 2763 2764 qup_i2c7_default: qup-i2c7-default { 2765 pinmux { 2766 pins = "gpio93", "gpio94"; 2767 function = "qup7"; 2768 }; 2769 }; 2770 2771 qup_i2c8_default: qup-i2c8-default { 2772 pinmux { 2773 pins = "gpio65", "gpio66"; 2774 function = "qup8"; 2775 }; 2776 }; 2777 2778 qup_i2c9_default: qup-i2c9-default { 2779 pinmux { 2780 pins = "gpio6", "gpio7"; 2781 function = "qup9"; 2782 }; 2783 }; 2784 2785 qup_i2c10_default: qup-i2c10-default { 2786 pinmux { 2787 pins = "gpio55", "gpio56"; 2788 function = "qup10"; 2789 }; 2790 }; 2791 2792 qup_i2c11_default: qup-i2c11-default { 2793 pinmux { 2794 pins = "gpio31", "gpio32"; 2795 function = "qup11"; 2796 }; 2797 }; 2798 2799 qup_i2c12_default: qup-i2c12-default { 2800 pinmux { 2801 pins = "gpio49", "gpio50"; 2802 function = "qup12"; 2803 }; 2804 }; 2805 2806 qup_i2c13_default: qup-i2c13-default { 2807 pinmux { 2808 pins = "gpio105", "gpio106"; 2809 function = "qup13"; 2810 }; 2811 }; 2812 2813 qup_i2c14_default: qup-i2c14-default { 2814 pinmux { 2815 pins = "gpio33", "gpio34"; 2816 function = "qup14"; 2817 }; 2818 }; 2819 2820 qup_i2c15_default: qup-i2c15-default { 2821 pinmux { 2822 pins = "gpio81", "gpio82"; 2823 function = "qup15"; 2824 }; 2825 }; 2826 2827 qup_spi0_default: qup-spi0-default { 2828 pinmux { 2829 pins = "gpio0", "gpio1", 2830 "gpio2", "gpio3"; 2831 function = "qup0"; 2832 }; 2833 2834 config { 2835 pins = "gpio0", "gpio1", 2836 "gpio2", "gpio3"; 2837 drive-strength = <6>; 2838 bias-disable; 2839 }; 2840 }; 2841 2842 qup_spi1_default: qup-spi1-default { 2843 pinmux { 2844 pins = "gpio17", "gpio18", 2845 "gpio19", "gpio20"; 2846 function = "qup1"; 2847 }; 2848 }; 2849 2850 qup_spi2_default: qup-spi2-default { 2851 pinmux { 2852 pins = "gpio27", "gpio28", 2853 "gpio29", "gpio30"; 2854 function = "qup2"; 2855 }; 2856 }; 2857 2858 qup_spi3_default: qup-spi3-default { 2859 pinmux { 2860 pins = "gpio41", "gpio42", 2861 "gpio43", "gpio44"; 2862 function = "qup3"; 2863 }; 2864 }; 2865 2866 qup_spi4_default: qup-spi4-default { 2867 pinmux { 2868 pins = "gpio89", "gpio90", 2869 "gpio91", "gpio92"; 2870 function = "qup4"; 2871 }; 2872 }; 2873 2874 qup_spi5_default: qup-spi5-default { 2875 pinmux { 2876 pins = "gpio85", "gpio86", 2877 "gpio87", "gpio88"; 2878 function = "qup5"; 2879 }; 2880 }; 2881 2882 qup_spi6_default: qup-spi6-default { 2883 pinmux { 2884 pins = "gpio45", "gpio46", 2885 "gpio47", "gpio48"; 2886 function = "qup6"; 2887 }; 2888 }; 2889 2890 qup_spi7_default: qup-spi7-default { 2891 pinmux { 2892 pins = "gpio93", "gpio94", 2893 "gpio95", "gpio96"; 2894 function = "qup7"; 2895 }; 2896 }; 2897 2898 qup_spi8_default: qup-spi8-default { 2899 pinmux { 2900 pins = "gpio65", "gpio66", 2901 "gpio67", "gpio68"; 2902 function = "qup8"; 2903 }; 2904 }; 2905 2906 qup_spi9_default: qup-spi9-default { 2907 pinmux { 2908 pins = "gpio6", "gpio7", 2909 "gpio4", "gpio5"; 2910 function = "qup9"; 2911 }; 2912 }; 2913 2914 qup_spi10_default: qup-spi10-default { 2915 pinmux { 2916 pins = "gpio55", "gpio56", 2917 "gpio53", "gpio54"; 2918 function = "qup10"; 2919 }; 2920 }; 2921 2922 qup_spi11_default: qup-spi11-default { 2923 pinmux { 2924 pins = "gpio31", "gpio32", 2925 "gpio33", "gpio34"; 2926 function = "qup11"; 2927 }; 2928 }; 2929 2930 qup_spi12_default: qup-spi12-default { 2931 pinmux { 2932 pins = "gpio49", "gpio50", 2933 "gpio51", "gpio52"; 2934 function = "qup12"; 2935 }; 2936 }; 2937 2938 qup_spi13_default: qup-spi13-default { 2939 pinmux { 2940 pins = "gpio105", "gpio106", 2941 "gpio107", "gpio108"; 2942 function = "qup13"; 2943 }; 2944 }; 2945 2946 qup_spi14_default: qup-spi14-default { 2947 pinmux { 2948 pins = "gpio33", "gpio34", 2949 "gpio31", "gpio32"; 2950 function = "qup14"; 2951 }; 2952 }; 2953 2954 qup_spi15_default: qup-spi15-default { 2955 pinmux { 2956 pins = "gpio81", "gpio82", 2957 "gpio83", "gpio84"; 2958 function = "qup15"; 2959 }; 2960 }; 2961 2962 qup_uart0_default: qup-uart0-default { 2963 pinmux { 2964 pins = "gpio2", "gpio3"; 2965 function = "qup0"; 2966 }; 2967 }; 2968 2969 qup_uart1_default: qup-uart1-default { 2970 pinmux { 2971 pins = "gpio19", "gpio20"; 2972 function = "qup1"; 2973 }; 2974 }; 2975 2976 qup_uart2_default: qup-uart2-default { 2977 pinmux { 2978 pins = "gpio29", "gpio30"; 2979 function = "qup2"; 2980 }; 2981 }; 2982 2983 qup_uart3_default: qup-uart3-default { 2984 pinmux { 2985 pins = "gpio43", "gpio44"; 2986 function = "qup3"; 2987 }; 2988 }; 2989 2990 qup_uart4_default: qup-uart4-default { 2991 pinmux { 2992 pins = "gpio91", "gpio92"; 2993 function = "qup4"; 2994 }; 2995 }; 2996 2997 qup_uart5_default: qup-uart5-default { 2998 pinmux { 2999 pins = "gpio87", "gpio88"; 3000 function = "qup5"; 3001 }; 3002 }; 3003 3004 qup_uart6_default: qup-uart6-default { 3005 pinmux { 3006 pins = "gpio47", "gpio48"; 3007 function = "qup6"; 3008 }; 3009 }; 3010 3011 qup_uart6_4pin: qup-uart6-4pin-state { 3012 3013 cts-pins { 3014 pins = "gpio45"; 3015 function = "qup6"; 3016 bias-pull-down; 3017 }; 3018 3019 rts-tx-pins { 3020 pins = "gpio46", "gpio47"; 3021 function = "qup6"; 3022 drive-strength = <2>; 3023 bias-disable; 3024 }; 3025 3026 rx-pins { 3027 pins = "gpio48"; 3028 function = "qup6"; 3029 bias-pull-up; 3030 }; 3031 }; 3032 3033 qup_uart7_default: qup-uart7-default { 3034 pinmux { 3035 pins = "gpio95", "gpio96"; 3036 function = "qup7"; 3037 }; 3038 }; 3039 3040 qup_uart8_default: qup-uart8-default { 3041 pinmux { 3042 pins = "gpio67", "gpio68"; 3043 function = "qup8"; 3044 }; 3045 }; 3046 3047 qup_uart9_default: qup-uart9-default { 3048 pinmux { 3049 pins = "gpio4", "gpio5"; 3050 function = "qup9"; 3051 }; 3052 }; 3053 3054 qup_uart10_default: qup-uart10-default { 3055 pinmux { 3056 pins = "gpio53", "gpio54"; 3057 function = "qup10"; 3058 }; 3059 }; 3060 3061 qup_uart11_default: qup-uart11-default { 3062 pinmux { 3063 pins = "gpio33", "gpio34"; 3064 function = "qup11"; 3065 }; 3066 }; 3067 3068 qup_uart12_default: qup-uart12-default { 3069 pinmux { 3070 pins = "gpio51", "gpio52"; 3071 function = "qup12"; 3072 }; 3073 }; 3074 3075 qup_uart13_default: qup-uart13-default { 3076 pinmux { 3077 pins = "gpio107", "gpio108"; 3078 function = "qup13"; 3079 }; 3080 }; 3081 3082 qup_uart14_default: qup-uart14-default { 3083 pinmux { 3084 pins = "gpio31", "gpio32"; 3085 function = "qup14"; 3086 }; 3087 }; 3088 3089 qup_uart15_default: qup-uart15-default { 3090 pinmux { 3091 pins = "gpio83", "gpio84"; 3092 function = "qup15"; 3093 }; 3094 }; 3095 3096 quat_mi2s_sleep: quat_mi2s_sleep { 3097 mux { 3098 pins = "gpio58", "gpio59"; 3099 function = "gpio"; 3100 }; 3101 3102 config { 3103 pins = "gpio58", "gpio59"; 3104 drive-strength = <2>; 3105 bias-pull-down; 3106 input-enable; 3107 }; 3108 }; 3109 3110 quat_mi2s_active: quat_mi2s_active { 3111 mux { 3112 pins = "gpio58", "gpio59"; 3113 function = "qua_mi2s"; 3114 }; 3115 3116 config { 3117 pins = "gpio58", "gpio59"; 3118 drive-strength = <8>; 3119 bias-disable; 3120 output-high; 3121 }; 3122 }; 3123 3124 quat_mi2s_sd0_sleep: quat_mi2s_sd0_sleep { 3125 mux { 3126 pins = "gpio60"; 3127 function = "gpio"; 3128 }; 3129 3130 config { 3131 pins = "gpio60"; 3132 drive-strength = <2>; 3133 bias-pull-down; 3134 input-enable; 3135 }; 3136 }; 3137 3138 quat_mi2s_sd0_active: quat_mi2s_sd0_active { 3139 mux { 3140 pins = "gpio60"; 3141 function = "qua_mi2s"; 3142 }; 3143 3144 config { 3145 pins = "gpio60"; 3146 drive-strength = <8>; 3147 bias-disable; 3148 }; 3149 }; 3150 3151 quat_mi2s_sd1_sleep: quat_mi2s_sd1_sleep { 3152 mux { 3153 pins = "gpio61"; 3154 function = "gpio"; 3155 }; 3156 3157 config { 3158 pins = "gpio61"; 3159 drive-strength = <2>; 3160 bias-pull-down; 3161 input-enable; 3162 }; 3163 }; 3164 3165 quat_mi2s_sd1_active: quat_mi2s_sd1_active { 3166 mux { 3167 pins = "gpio61"; 3168 function = "qua_mi2s"; 3169 }; 3170 3171 config { 3172 pins = "gpio61"; 3173 drive-strength = <8>; 3174 bias-disable; 3175 }; 3176 }; 3177 3178 quat_mi2s_sd2_sleep: quat_mi2s_sd2_sleep { 3179 mux { 3180 pins = "gpio62"; 3181 function = "gpio"; 3182 }; 3183 3184 config { 3185 pins = "gpio62"; 3186 drive-strength = <2>; 3187 bias-pull-down; 3188 input-enable; 3189 }; 3190 }; 3191 3192 quat_mi2s_sd2_active: quat_mi2s_sd2_active { 3193 mux { 3194 pins = "gpio62"; 3195 function = "qua_mi2s"; 3196 }; 3197 3198 config { 3199 pins = "gpio62"; 3200 drive-strength = <8>; 3201 bias-disable; 3202 }; 3203 }; 3204 3205 quat_mi2s_sd3_sleep: quat_mi2s_sd3_sleep { 3206 mux { 3207 pins = "gpio63"; 3208 function = "gpio"; 3209 }; 3210 3211 config { 3212 pins = "gpio63"; 3213 drive-strength = <2>; 3214 bias-pull-down; 3215 input-enable; 3216 }; 3217 }; 3218 3219 quat_mi2s_sd3_active: quat_mi2s_sd3_active { 3220 mux { 3221 pins = "gpio63"; 3222 function = "qua_mi2s"; 3223 }; 3224 3225 config { 3226 pins = "gpio63"; 3227 drive-strength = <8>; 3228 bias-disable; 3229 }; 3230 }; 3231 }; 3232 3233 mss_pil: remoteproc@4080000 { 3234 compatible = "qcom,sdm845-mss-pil"; 3235 reg = <0 0x04080000 0 0x408>, <0 0x04180000 0 0x48>; 3236 reg-names = "qdsp6", "rmb"; 3237 3238 interrupts-extended = 3239 <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, 3240 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3241 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3242 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3243 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 3244 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 3245 interrupt-names = "wdog", "fatal", "ready", 3246 "handover", "stop-ack", 3247 "shutdown-ack"; 3248 3249 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 3250 <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>, 3251 <&gcc GCC_BOOT_ROM_AHB_CLK>, 3252 <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>, 3253 <&gcc GCC_MSS_SNOC_AXI_CLK>, 3254 <&gcc GCC_MSS_MFAB_AXIS_CLK>, 3255 <&gcc GCC_PRNG_AHB_CLK>, 3256 <&rpmhcc RPMH_CXO_CLK>; 3257 clock-names = "iface", "bus", "mem", "gpll0_mss", 3258 "snoc_axi", "mnoc_axi", "prng", "xo"; 3259 3260 qcom,qmp = <&aoss_qmp>; 3261 3262 qcom,smem-states = <&modem_smp2p_out 0>; 3263 qcom,smem-state-names = "stop"; 3264 3265 resets = <&aoss_reset AOSS_CC_MSS_RESTART>, 3266 <&pdc_reset PDC_MODEM_SYNC_RESET>; 3267 reset-names = "mss_restart", "pdc_reset"; 3268 3269 qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>; 3270 3271 power-domains = <&rpmhpd SDM845_CX>, 3272 <&rpmhpd SDM845_MX>, 3273 <&rpmhpd SDM845_MSS>; 3274 power-domain-names = "cx", "mx", "mss"; 3275 3276 status = "disabled"; 3277 3278 mba { 3279 memory-region = <&mba_region>; 3280 }; 3281 3282 mpss { 3283 memory-region = <&mpss_region>; 3284 }; 3285 3286 glink-edge { 3287 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 3288 label = "modem"; 3289 qcom,remote-pid = <1>; 3290 mboxes = <&apss_shared 12>; 3291 }; 3292 }; 3293 3294 gpucc: clock-controller@5090000 { 3295 compatible = "qcom,sdm845-gpucc"; 3296 reg = <0 0x05090000 0 0x9000>; 3297 #clock-cells = <1>; 3298 #reset-cells = <1>; 3299 #power-domain-cells = <1>; 3300 clocks = <&rpmhcc RPMH_CXO_CLK>, 3301 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 3302 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 3303 clock-names = "bi_tcxo", 3304 "gcc_gpu_gpll0_clk_src", 3305 "gcc_gpu_gpll0_div_clk_src"; 3306 }; 3307 3308 stm@6002000 { 3309 compatible = "arm,coresight-stm", "arm,primecell"; 3310 reg = <0 0x06002000 0 0x1000>, 3311 <0 0x16280000 0 0x180000>; 3312 reg-names = "stm-base", "stm-stimulus-base"; 3313 3314 clocks = <&aoss_qmp>; 3315 clock-names = "apb_pclk"; 3316 3317 out-ports { 3318 port { 3319 stm_out: endpoint { 3320 remote-endpoint = 3321 <&funnel0_in7>; 3322 }; 3323 }; 3324 }; 3325 }; 3326 3327 funnel@6041000 { 3328 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3329 reg = <0 0x06041000 0 0x1000>; 3330 3331 clocks = <&aoss_qmp>; 3332 clock-names = "apb_pclk"; 3333 3334 out-ports { 3335 port { 3336 funnel0_out: endpoint { 3337 remote-endpoint = 3338 <&merge_funnel_in0>; 3339 }; 3340 }; 3341 }; 3342 3343 in-ports { 3344 #address-cells = <1>; 3345 #size-cells = <0>; 3346 3347 port@7 { 3348 reg = <7>; 3349 funnel0_in7: endpoint { 3350 remote-endpoint = <&stm_out>; 3351 }; 3352 }; 3353 }; 3354 }; 3355 3356 funnel@6043000 { 3357 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3358 reg = <0 0x06043000 0 0x1000>; 3359 3360 clocks = <&aoss_qmp>; 3361 clock-names = "apb_pclk"; 3362 3363 out-ports { 3364 port { 3365 funnel2_out: endpoint { 3366 remote-endpoint = 3367 <&merge_funnel_in2>; 3368 }; 3369 }; 3370 }; 3371 3372 in-ports { 3373 #address-cells = <1>; 3374 #size-cells = <0>; 3375 3376 port@5 { 3377 reg = <5>; 3378 funnel2_in5: endpoint { 3379 remote-endpoint = 3380 <&apss_merge_funnel_out>; 3381 }; 3382 }; 3383 }; 3384 }; 3385 3386 funnel@6045000 { 3387 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3388 reg = <0 0x06045000 0 0x1000>; 3389 3390 clocks = <&aoss_qmp>; 3391 clock-names = "apb_pclk"; 3392 3393 out-ports { 3394 port { 3395 merge_funnel_out: endpoint { 3396 remote-endpoint = <&etf_in>; 3397 }; 3398 }; 3399 }; 3400 3401 in-ports { 3402 #address-cells = <1>; 3403 #size-cells = <0>; 3404 3405 port@0 { 3406 reg = <0>; 3407 merge_funnel_in0: endpoint { 3408 remote-endpoint = 3409 <&funnel0_out>; 3410 }; 3411 }; 3412 3413 port@2 { 3414 reg = <2>; 3415 merge_funnel_in2: endpoint { 3416 remote-endpoint = 3417 <&funnel2_out>; 3418 }; 3419 }; 3420 }; 3421 }; 3422 3423 replicator@6046000 { 3424 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 3425 reg = <0 0x06046000 0 0x1000>; 3426 3427 clocks = <&aoss_qmp>; 3428 clock-names = "apb_pclk"; 3429 3430 out-ports { 3431 port { 3432 replicator_out: endpoint { 3433 remote-endpoint = <&etr_in>; 3434 }; 3435 }; 3436 }; 3437 3438 in-ports { 3439 port { 3440 replicator_in: endpoint { 3441 remote-endpoint = <&etf_out>; 3442 }; 3443 }; 3444 }; 3445 }; 3446 3447 etf@6047000 { 3448 compatible = "arm,coresight-tmc", "arm,primecell"; 3449 reg = <0 0x06047000 0 0x1000>; 3450 3451 clocks = <&aoss_qmp>; 3452 clock-names = "apb_pclk"; 3453 3454 out-ports { 3455 port { 3456 etf_out: endpoint { 3457 remote-endpoint = 3458 <&replicator_in>; 3459 }; 3460 }; 3461 }; 3462 3463 in-ports { 3464 #address-cells = <1>; 3465 #size-cells = <0>; 3466 3467 port@1 { 3468 reg = <1>; 3469 etf_in: endpoint { 3470 remote-endpoint = 3471 <&merge_funnel_out>; 3472 }; 3473 }; 3474 }; 3475 }; 3476 3477 etr@6048000 { 3478 compatible = "arm,coresight-tmc", "arm,primecell"; 3479 reg = <0 0x06048000 0 0x1000>; 3480 3481 clocks = <&aoss_qmp>; 3482 clock-names = "apb_pclk"; 3483 arm,scatter-gather; 3484 3485 in-ports { 3486 port { 3487 etr_in: endpoint { 3488 remote-endpoint = 3489 <&replicator_out>; 3490 }; 3491 }; 3492 }; 3493 }; 3494 3495 etm@7040000 { 3496 compatible = "arm,coresight-etm4x", "arm,primecell"; 3497 reg = <0 0x07040000 0 0x1000>; 3498 3499 cpu = <&CPU0>; 3500 3501 clocks = <&aoss_qmp>; 3502 clock-names = "apb_pclk"; 3503 arm,coresight-loses-context-with-cpu; 3504 3505 out-ports { 3506 port { 3507 etm0_out: endpoint { 3508 remote-endpoint = 3509 <&apss_funnel_in0>; 3510 }; 3511 }; 3512 }; 3513 }; 3514 3515 etm@7140000 { 3516 compatible = "arm,coresight-etm4x", "arm,primecell"; 3517 reg = <0 0x07140000 0 0x1000>; 3518 3519 cpu = <&CPU1>; 3520 3521 clocks = <&aoss_qmp>; 3522 clock-names = "apb_pclk"; 3523 arm,coresight-loses-context-with-cpu; 3524 3525 out-ports { 3526 port { 3527 etm1_out: endpoint { 3528 remote-endpoint = 3529 <&apss_funnel_in1>; 3530 }; 3531 }; 3532 }; 3533 }; 3534 3535 etm@7240000 { 3536 compatible = "arm,coresight-etm4x", "arm,primecell"; 3537 reg = <0 0x07240000 0 0x1000>; 3538 3539 cpu = <&CPU2>; 3540 3541 clocks = <&aoss_qmp>; 3542 clock-names = "apb_pclk"; 3543 arm,coresight-loses-context-with-cpu; 3544 3545 out-ports { 3546 port { 3547 etm2_out: endpoint { 3548 remote-endpoint = 3549 <&apss_funnel_in2>; 3550 }; 3551 }; 3552 }; 3553 }; 3554 3555 etm@7340000 { 3556 compatible = "arm,coresight-etm4x", "arm,primecell"; 3557 reg = <0 0x07340000 0 0x1000>; 3558 3559 cpu = <&CPU3>; 3560 3561 clocks = <&aoss_qmp>; 3562 clock-names = "apb_pclk"; 3563 arm,coresight-loses-context-with-cpu; 3564 3565 out-ports { 3566 port { 3567 etm3_out: endpoint { 3568 remote-endpoint = 3569 <&apss_funnel_in3>; 3570 }; 3571 }; 3572 }; 3573 }; 3574 3575 etm@7440000 { 3576 compatible = "arm,coresight-etm4x", "arm,primecell"; 3577 reg = <0 0x07440000 0 0x1000>; 3578 3579 cpu = <&CPU4>; 3580 3581 clocks = <&aoss_qmp>; 3582 clock-names = "apb_pclk"; 3583 arm,coresight-loses-context-with-cpu; 3584 3585 out-ports { 3586 port { 3587 etm4_out: endpoint { 3588 remote-endpoint = 3589 <&apss_funnel_in4>; 3590 }; 3591 }; 3592 }; 3593 }; 3594 3595 etm@7540000 { 3596 compatible = "arm,coresight-etm4x", "arm,primecell"; 3597 reg = <0 0x07540000 0 0x1000>; 3598 3599 cpu = <&CPU5>; 3600 3601 clocks = <&aoss_qmp>; 3602 clock-names = "apb_pclk"; 3603 arm,coresight-loses-context-with-cpu; 3604 3605 out-ports { 3606 port { 3607 etm5_out: endpoint { 3608 remote-endpoint = 3609 <&apss_funnel_in5>; 3610 }; 3611 }; 3612 }; 3613 }; 3614 3615 etm@7640000 { 3616 compatible = "arm,coresight-etm4x", "arm,primecell"; 3617 reg = <0 0x07640000 0 0x1000>; 3618 3619 cpu = <&CPU6>; 3620 3621 clocks = <&aoss_qmp>; 3622 clock-names = "apb_pclk"; 3623 arm,coresight-loses-context-with-cpu; 3624 3625 out-ports { 3626 port { 3627 etm6_out: endpoint { 3628 remote-endpoint = 3629 <&apss_funnel_in6>; 3630 }; 3631 }; 3632 }; 3633 }; 3634 3635 etm@7740000 { 3636 compatible = "arm,coresight-etm4x", "arm,primecell"; 3637 reg = <0 0x07740000 0 0x1000>; 3638 3639 cpu = <&CPU7>; 3640 3641 clocks = <&aoss_qmp>; 3642 clock-names = "apb_pclk"; 3643 arm,coresight-loses-context-with-cpu; 3644 3645 out-ports { 3646 port { 3647 etm7_out: endpoint { 3648 remote-endpoint = 3649 <&apss_funnel_in7>; 3650 }; 3651 }; 3652 }; 3653 }; 3654 3655 funnel@7800000 { /* APSS Funnel */ 3656 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3657 reg = <0 0x07800000 0 0x1000>; 3658 3659 clocks = <&aoss_qmp>; 3660 clock-names = "apb_pclk"; 3661 3662 out-ports { 3663 port { 3664 apss_funnel_out: endpoint { 3665 remote-endpoint = 3666 <&apss_merge_funnel_in>; 3667 }; 3668 }; 3669 }; 3670 3671 in-ports { 3672 #address-cells = <1>; 3673 #size-cells = <0>; 3674 3675 port@0 { 3676 reg = <0>; 3677 apss_funnel_in0: endpoint { 3678 remote-endpoint = 3679 <&etm0_out>; 3680 }; 3681 }; 3682 3683 port@1 { 3684 reg = <1>; 3685 apss_funnel_in1: endpoint { 3686 remote-endpoint = 3687 <&etm1_out>; 3688 }; 3689 }; 3690 3691 port@2 { 3692 reg = <2>; 3693 apss_funnel_in2: endpoint { 3694 remote-endpoint = 3695 <&etm2_out>; 3696 }; 3697 }; 3698 3699 port@3 { 3700 reg = <3>; 3701 apss_funnel_in3: endpoint { 3702 remote-endpoint = 3703 <&etm3_out>; 3704 }; 3705 }; 3706 3707 port@4 { 3708 reg = <4>; 3709 apss_funnel_in4: endpoint { 3710 remote-endpoint = 3711 <&etm4_out>; 3712 }; 3713 }; 3714 3715 port@5 { 3716 reg = <5>; 3717 apss_funnel_in5: endpoint { 3718 remote-endpoint = 3719 <&etm5_out>; 3720 }; 3721 }; 3722 3723 port@6 { 3724 reg = <6>; 3725 apss_funnel_in6: endpoint { 3726 remote-endpoint = 3727 <&etm6_out>; 3728 }; 3729 }; 3730 3731 port@7 { 3732 reg = <7>; 3733 apss_funnel_in7: endpoint { 3734 remote-endpoint = 3735 <&etm7_out>; 3736 }; 3737 }; 3738 }; 3739 }; 3740 3741 funnel@7810000 { 3742 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3743 reg = <0 0x07810000 0 0x1000>; 3744 3745 clocks = <&aoss_qmp>; 3746 clock-names = "apb_pclk"; 3747 3748 out-ports { 3749 port { 3750 apss_merge_funnel_out: endpoint { 3751 remote-endpoint = 3752 <&funnel2_in5>; 3753 }; 3754 }; 3755 }; 3756 3757 in-ports { 3758 port { 3759 apss_merge_funnel_in: endpoint { 3760 remote-endpoint = 3761 <&apss_funnel_out>; 3762 }; 3763 }; 3764 }; 3765 }; 3766 3767 sdhc_2: mmc@8804000 { 3768 compatible = "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5"; 3769 reg = <0 0x08804000 0 0x1000>; 3770 3771 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 3772 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 3773 interrupt-names = "hc_irq", "pwr_irq"; 3774 3775 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3776 <&gcc GCC_SDCC2_APPS_CLK>, 3777 <&rpmhcc RPMH_CXO_CLK>; 3778 clock-names = "iface", "core", "xo"; 3779 iommus = <&apps_smmu 0xa0 0xf>; 3780 power-domains = <&rpmhpd SDM845_CX>; 3781 operating-points-v2 = <&sdhc2_opp_table>; 3782 3783 status = "disabled"; 3784 3785 sdhc2_opp_table: opp-table { 3786 compatible = "operating-points-v2"; 3787 3788 opp-9600000 { 3789 opp-hz = /bits/ 64 <9600000>; 3790 required-opps = <&rpmhpd_opp_min_svs>; 3791 }; 3792 3793 opp-19200000 { 3794 opp-hz = /bits/ 64 <19200000>; 3795 required-opps = <&rpmhpd_opp_low_svs>; 3796 }; 3797 3798 opp-100000000 { 3799 opp-hz = /bits/ 64 <100000000>; 3800 required-opps = <&rpmhpd_opp_svs>; 3801 }; 3802 3803 opp-201500000 { 3804 opp-hz = /bits/ 64 <201500000>; 3805 required-opps = <&rpmhpd_opp_svs_l1>; 3806 }; 3807 }; 3808 }; 3809 3810 qspi_opp_table: opp-table-qspi { 3811 compatible = "operating-points-v2"; 3812 3813 opp-19200000 { 3814 opp-hz = /bits/ 64 <19200000>; 3815 required-opps = <&rpmhpd_opp_min_svs>; 3816 }; 3817 3818 opp-100000000 { 3819 opp-hz = /bits/ 64 <100000000>; 3820 required-opps = <&rpmhpd_opp_low_svs>; 3821 }; 3822 3823 opp-150000000 { 3824 opp-hz = /bits/ 64 <150000000>; 3825 required-opps = <&rpmhpd_opp_svs>; 3826 }; 3827 3828 opp-300000000 { 3829 opp-hz = /bits/ 64 <300000000>; 3830 required-opps = <&rpmhpd_opp_nom>; 3831 }; 3832 }; 3833 3834 qspi: spi@88df000 { 3835 compatible = "qcom,sdm845-qspi", "qcom,qspi-v1"; 3836 reg = <0 0x088df000 0 0x600>; 3837 #address-cells = <1>; 3838 #size-cells = <0>; 3839 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 3840 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 3841 <&gcc GCC_QSPI_CORE_CLK>; 3842 clock-names = "iface", "core"; 3843 power-domains = <&rpmhpd SDM845_CX>; 3844 operating-points-v2 = <&qspi_opp_table>; 3845 status = "disabled"; 3846 }; 3847 3848 slim: slim-ngd@171c0000 { 3849 compatible = "qcom,slim-ngd-v2.1.0"; 3850 reg = <0 0x171c0000 0 0x2c000>; 3851 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 3852 3853 dmas = <&slimbam 3>, <&slimbam 4>; 3854 dma-names = "rx", "tx"; 3855 3856 iommus = <&apps_smmu 0x1806 0x0>; 3857 #address-cells = <1>; 3858 #size-cells = <0>; 3859 3860 slim@1 { 3861 reg = <1>; 3862 #address-cells = <2>; 3863 #size-cells = <0>; 3864 3865 wcd9340_ifd: ifd@0,0 { 3866 compatible = "slim217,250"; 3867 reg = <0 0>; 3868 }; 3869 3870 wcd9340: codec@1,0 { 3871 compatible = "slim217,250"; 3872 reg = <1 0>; 3873 slim-ifc-dev = <&wcd9340_ifd>; 3874 3875 #sound-dai-cells = <1>; 3876 3877 interrupts-extended = <&tlmm 54 IRQ_TYPE_LEVEL_HIGH>; 3878 interrupt-controller; 3879 #interrupt-cells = <1>; 3880 3881 #clock-cells = <0>; 3882 clock-frequency = <9600000>; 3883 clock-output-names = "mclk"; 3884 qcom,micbias1-microvolt = <1800000>; 3885 qcom,micbias2-microvolt = <1800000>; 3886 qcom,micbias3-microvolt = <1800000>; 3887 qcom,micbias4-microvolt = <1800000>; 3888 3889 #address-cells = <1>; 3890 #size-cells = <1>; 3891 3892 wcdgpio: gpio-controller@42 { 3893 compatible = "qcom,wcd9340-gpio"; 3894 gpio-controller; 3895 #gpio-cells = <2>; 3896 reg = <0x42 0x2>; 3897 }; 3898 3899 swm: swm@c85 { 3900 compatible = "qcom,soundwire-v1.3.0"; 3901 reg = <0xc85 0x40>; 3902 interrupts-extended = <&wcd9340 20>; 3903 3904 qcom,dout-ports = <6>; 3905 qcom,din-ports = <2>; 3906 qcom,ports-sinterval-low =/bits/ 8 <0x07 0x1F 0x3F 0x7 0x1F 0x3F 0x0F 0x0F>; 3907 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0C 0x6 0x12 0x0D 0x07 0x0A >; 3908 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x1F 0x00 0x00 0x1F 0x00 0x00>; 3909 3910 #sound-dai-cells = <1>; 3911 clocks = <&wcd9340>; 3912 clock-names = "iface"; 3913 #address-cells = <2>; 3914 #size-cells = <0>; 3915 3916 3917 }; 3918 }; 3919 }; 3920 }; 3921 3922 lmh_cluster1: lmh@17d70800 { 3923 compatible = "qcom,sdm845-lmh"; 3924 reg = <0 0x17d70800 0 0x400>; 3925 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 3926 cpus = <&CPU4>; 3927 qcom,lmh-temp-arm-millicelsius = <65000>; 3928 qcom,lmh-temp-low-millicelsius = <94500>; 3929 qcom,lmh-temp-high-millicelsius = <95000>; 3930 interrupt-controller; 3931 #interrupt-cells = <1>; 3932 }; 3933 3934 lmh_cluster0: lmh@17d78800 { 3935 compatible = "qcom,sdm845-lmh"; 3936 reg = <0 0x17d78800 0 0x400>; 3937 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 3938 cpus = <&CPU0>; 3939 qcom,lmh-temp-arm-millicelsius = <65000>; 3940 qcom,lmh-temp-low-millicelsius = <94500>; 3941 qcom,lmh-temp-high-millicelsius = <95000>; 3942 interrupt-controller; 3943 #interrupt-cells = <1>; 3944 }; 3945 3946 sound: sound { 3947 }; 3948 3949 usb_1_hsphy: phy@88e2000 { 3950 compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy"; 3951 reg = <0 0x088e2000 0 0x400>; 3952 status = "disabled"; 3953 #phy-cells = <0>; 3954 3955 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 3956 <&rpmhcc RPMH_CXO_CLK>; 3957 clock-names = "cfg_ahb", "ref"; 3958 3959 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3960 3961 nvmem-cells = <&qusb2p_hstx_trim>; 3962 }; 3963 3964 usb_2_hsphy: phy@88e3000 { 3965 compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy"; 3966 reg = <0 0x088e3000 0 0x400>; 3967 status = "disabled"; 3968 #phy-cells = <0>; 3969 3970 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 3971 <&rpmhcc RPMH_CXO_CLK>; 3972 clock-names = "cfg_ahb", "ref"; 3973 3974 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3975 3976 nvmem-cells = <&qusb2s_hstx_trim>; 3977 }; 3978 3979 usb_1_qmpphy: phy@88e9000 { 3980 compatible = "qcom,sdm845-qmp-usb3-dp-phy"; 3981 reg = <0 0x088e9000 0 0x18c>, 3982 <0 0x088e8000 0 0x38>, 3983 <0 0x088ea000 0 0x40>; 3984 status = "disabled"; 3985 #address-cells = <2>; 3986 #size-cells = <2>; 3987 ranges; 3988 3989 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3990 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 3991 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 3992 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 3993 clock-names = "aux", "cfg_ahb", "ref", "com_aux"; 3994 3995 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 3996 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; 3997 reset-names = "phy", "common"; 3998 3999 usb_1_ssphy: usb3-phy@88e9200 { 4000 reg = <0 0x088e9200 0 0x128>, 4001 <0 0x088e9400 0 0x200>, 4002 <0 0x088e9c00 0 0x218>, 4003 <0 0x088e9600 0 0x128>, 4004 <0 0x088e9800 0 0x200>, 4005 <0 0x088e9a00 0 0x100>; 4006 #clock-cells = <0>; 4007 #phy-cells = <0>; 4008 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 4009 clock-names = "pipe0"; 4010 clock-output-names = "usb3_phy_pipe_clk_src"; 4011 }; 4012 4013 dp_phy: dp-phy@88ea200 { 4014 reg = <0 0x088ea200 0 0x200>, 4015 <0 0x088ea400 0 0x200>, 4016 <0 0x088eaa00 0 0x200>, 4017 <0 0x088ea600 0 0x200>, 4018 <0 0x088ea800 0 0x200>; 4019 #clock-cells = <1>; 4020 #phy-cells = <0>; 4021 }; 4022 }; 4023 4024 usb_2_qmpphy: phy@88eb000 { 4025 compatible = "qcom,sdm845-qmp-usb3-uni-phy"; 4026 reg = <0 0x088eb000 0 0x18c>; 4027 status = "disabled"; 4028 #address-cells = <2>; 4029 #size-cells = <2>; 4030 ranges; 4031 4032 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 4033 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 4034 <&gcc GCC_USB3_SEC_CLKREF_CLK>, 4035 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; 4036 clock-names = "aux", "cfg_ahb", "ref", "com_aux"; 4037 4038 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, 4039 <&gcc GCC_USB3_PHY_SEC_BCR>; 4040 reset-names = "phy", "common"; 4041 4042 usb_2_ssphy: phy@88eb200 { 4043 reg = <0 0x088eb200 0 0x128>, 4044 <0 0x088eb400 0 0x1fc>, 4045 <0 0x088eb800 0 0x218>, 4046 <0 0x088eb600 0 0x70>; 4047 #clock-cells = <0>; 4048 #phy-cells = <0>; 4049 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 4050 clock-names = "pipe0"; 4051 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 4052 }; 4053 }; 4054 4055 usb_1: usb@a6f8800 { 4056 compatible = "qcom,sdm845-dwc3", "qcom,dwc3"; 4057 reg = <0 0x0a6f8800 0 0x400>; 4058 status = "disabled"; 4059 #address-cells = <2>; 4060 #size-cells = <2>; 4061 ranges; 4062 dma-ranges; 4063 4064 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 4065 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 4066 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 4067 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 4068 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 4069 clock-names = "cfg_noc", 4070 "core", 4071 "iface", 4072 "sleep", 4073 "mock_utmi"; 4074 4075 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4076 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 4077 assigned-clock-rates = <19200000>, <150000000>; 4078 4079 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 4080 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>, 4081 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>, 4082 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>; 4083 interrupt-names = "hs_phy_irq", "ss_phy_irq", 4084 "dm_hs_phy_irq", "dp_hs_phy_irq"; 4085 4086 power-domains = <&gcc USB30_PRIM_GDSC>; 4087 4088 resets = <&gcc GCC_USB30_PRIM_BCR>; 4089 4090 interconnects = <&aggre2_noc MASTER_USB3_0 0 &mem_noc SLAVE_EBI1 0>, 4091 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; 4092 interconnect-names = "usb-ddr", "apps-usb"; 4093 4094 usb_1_dwc3: usb@a600000 { 4095 compatible = "snps,dwc3"; 4096 reg = <0 0x0a600000 0 0xcd00>; 4097 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 4098 iommus = <&apps_smmu 0x740 0>; 4099 snps,dis_u2_susphy_quirk; 4100 snps,dis_enblslpm_quirk; 4101 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 4102 phy-names = "usb2-phy", "usb3-phy"; 4103 }; 4104 }; 4105 4106 usb_2: usb@a8f8800 { 4107 compatible = "qcom,sdm845-dwc3", "qcom,dwc3"; 4108 reg = <0 0x0a8f8800 0 0x400>; 4109 status = "disabled"; 4110 #address-cells = <2>; 4111 #size-cells = <2>; 4112 ranges; 4113 dma-ranges; 4114 4115 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 4116 <&gcc GCC_USB30_SEC_MASTER_CLK>, 4117 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 4118 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 4119 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>; 4120 clock-names = "cfg_noc", 4121 "core", 4122 "iface", 4123 "sleep", 4124 "mock_utmi"; 4125 4126 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 4127 <&gcc GCC_USB30_SEC_MASTER_CLK>; 4128 assigned-clock-rates = <19200000>, <150000000>; 4129 4130 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 4131 <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>, 4132 <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>, 4133 <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>; 4134 interrupt-names = "hs_phy_irq", "ss_phy_irq", 4135 "dm_hs_phy_irq", "dp_hs_phy_irq"; 4136 4137 power-domains = <&gcc USB30_SEC_GDSC>; 4138 4139 resets = <&gcc GCC_USB30_SEC_BCR>; 4140 4141 interconnects = <&aggre2_noc MASTER_USB3_1 0 &mem_noc SLAVE_EBI1 0>, 4142 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>; 4143 interconnect-names = "usb-ddr", "apps-usb"; 4144 4145 usb_2_dwc3: usb@a800000 { 4146 compatible = "snps,dwc3"; 4147 reg = <0 0x0a800000 0 0xcd00>; 4148 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 4149 iommus = <&apps_smmu 0x760 0>; 4150 snps,dis_u2_susphy_quirk; 4151 snps,dis_enblslpm_quirk; 4152 phys = <&usb_2_hsphy>, <&usb_2_ssphy>; 4153 phy-names = "usb2-phy", "usb3-phy"; 4154 }; 4155 }; 4156 4157 venus: video-codec@aa00000 { 4158 compatible = "qcom,sdm845-venus-v2"; 4159 reg = <0 0x0aa00000 0 0xff000>; 4160 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 4161 power-domains = <&videocc VENUS_GDSC>, 4162 <&videocc VCODEC0_GDSC>, 4163 <&videocc VCODEC1_GDSC>, 4164 <&rpmhpd SDM845_CX>; 4165 power-domain-names = "venus", "vcodec0", "vcodec1", "cx"; 4166 operating-points-v2 = <&venus_opp_table>; 4167 clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>, 4168 <&videocc VIDEO_CC_VENUS_AHB_CLK>, 4169 <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>, 4170 <&videocc VIDEO_CC_VCODEC0_CORE_CLK>, 4171 <&videocc VIDEO_CC_VCODEC0_AXI_CLK>, 4172 <&videocc VIDEO_CC_VCODEC1_CORE_CLK>, 4173 <&videocc VIDEO_CC_VCODEC1_AXI_CLK>; 4174 clock-names = "core", "iface", "bus", 4175 "vcodec0_core", "vcodec0_bus", 4176 "vcodec1_core", "vcodec1_bus"; 4177 iommus = <&apps_smmu 0x10a0 0x8>, 4178 <&apps_smmu 0x10b0 0x0>; 4179 memory-region = <&venus_mem>; 4180 interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mem_noc SLAVE_EBI1 0>, 4181 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>; 4182 interconnect-names = "video-mem", "cpu-cfg"; 4183 4184 status = "disabled"; 4185 4186 video-core0 { 4187 compatible = "venus-decoder"; 4188 }; 4189 4190 video-core1 { 4191 compatible = "venus-encoder"; 4192 }; 4193 4194 venus_opp_table: opp-table { 4195 compatible = "operating-points-v2"; 4196 4197 opp-100000000 { 4198 opp-hz = /bits/ 64 <100000000>; 4199 required-opps = <&rpmhpd_opp_min_svs>; 4200 }; 4201 4202 opp-200000000 { 4203 opp-hz = /bits/ 64 <200000000>; 4204 required-opps = <&rpmhpd_opp_low_svs>; 4205 }; 4206 4207 opp-320000000 { 4208 opp-hz = /bits/ 64 <320000000>; 4209 required-opps = <&rpmhpd_opp_svs>; 4210 }; 4211 4212 opp-380000000 { 4213 opp-hz = /bits/ 64 <380000000>; 4214 required-opps = <&rpmhpd_opp_svs_l1>; 4215 }; 4216 4217 opp-444000000 { 4218 opp-hz = /bits/ 64 <444000000>; 4219 required-opps = <&rpmhpd_opp_nom>; 4220 }; 4221 4222 opp-533000097 { 4223 opp-hz = /bits/ 64 <533000097>; 4224 required-opps = <&rpmhpd_opp_turbo>; 4225 }; 4226 }; 4227 }; 4228 4229 videocc: clock-controller@ab00000 { 4230 compatible = "qcom,sdm845-videocc"; 4231 reg = <0 0x0ab00000 0 0x10000>; 4232 clocks = <&rpmhcc RPMH_CXO_CLK>; 4233 clock-names = "bi_tcxo"; 4234 #clock-cells = <1>; 4235 #power-domain-cells = <1>; 4236 #reset-cells = <1>; 4237 }; 4238 4239 camss: camss@a00000 { 4240 compatible = "qcom,sdm845-camss"; 4241 4242 reg = <0 0xacb3000 0 0x1000>, 4243 <0 0xacba000 0 0x1000>, 4244 <0 0xacc8000 0 0x1000>, 4245 <0 0xac65000 0 0x1000>, 4246 <0 0xac66000 0 0x1000>, 4247 <0 0xac67000 0 0x1000>, 4248 <0 0xac68000 0 0x1000>, 4249 <0 0xacaf000 0 0x4000>, 4250 <0 0xacb6000 0 0x4000>, 4251 <0 0xacc4000 0 0x4000>; 4252 reg-names = "csid0", 4253 "csid1", 4254 "csid2", 4255 "csiphy0", 4256 "csiphy1", 4257 "csiphy2", 4258 "csiphy3", 4259 "vfe0", 4260 "vfe1", 4261 "vfe_lite"; 4262 4263 interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>, 4264 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>, 4265 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>, 4266 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>, 4267 <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>, 4268 <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>, 4269 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, 4270 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>, 4271 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>, 4272 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>; 4273 interrupt-names = "csid0", 4274 "csid1", 4275 "csid2", 4276 "csiphy0", 4277 "csiphy1", 4278 "csiphy2", 4279 "csiphy3", 4280 "vfe0", 4281 "vfe1", 4282 "vfe_lite"; 4283 4284 power-domains = <&clock_camcc IFE_0_GDSC>, 4285 <&clock_camcc IFE_1_GDSC>, 4286 <&clock_camcc TITAN_TOP_GDSC>; 4287 4288 clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, 4289 <&clock_camcc CAM_CC_CPAS_AHB_CLK>, 4290 <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, 4291 <&clock_camcc CAM_CC_IFE_0_CSID_CLK>, 4292 <&clock_camcc CAM_CC_IFE_0_CSID_CLK_SRC>, 4293 <&clock_camcc CAM_CC_IFE_1_CSID_CLK>, 4294 <&clock_camcc CAM_CC_IFE_1_CSID_CLK_SRC>, 4295 <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK>, 4296 <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>, 4297 <&clock_camcc CAM_CC_CSIPHY0_CLK>, 4298 <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>, 4299 <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>, 4300 <&clock_camcc CAM_CC_CSIPHY1_CLK>, 4301 <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK>, 4302 <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>, 4303 <&clock_camcc CAM_CC_CSIPHY2_CLK>, 4304 <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK>, 4305 <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>, 4306 <&clock_camcc CAM_CC_CSIPHY3_CLK>, 4307 <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK>, 4308 <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>, 4309 <&gcc GCC_CAMERA_AHB_CLK>, 4310 <&gcc GCC_CAMERA_AXI_CLK>, 4311 <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, 4312 <&clock_camcc CAM_CC_SOC_AHB_CLK>, 4313 <&clock_camcc CAM_CC_IFE_0_AXI_CLK>, 4314 <&clock_camcc CAM_CC_IFE_0_CLK>, 4315 <&clock_camcc CAM_CC_IFE_0_CPHY_RX_CLK>, 4316 <&clock_camcc CAM_CC_IFE_0_CLK_SRC>, 4317 <&clock_camcc CAM_CC_IFE_1_AXI_CLK>, 4318 <&clock_camcc CAM_CC_IFE_1_CLK>, 4319 <&clock_camcc CAM_CC_IFE_1_CPHY_RX_CLK>, 4320 <&clock_camcc CAM_CC_IFE_1_CLK_SRC>, 4321 <&clock_camcc CAM_CC_IFE_LITE_CLK>, 4322 <&clock_camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, 4323 <&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>; 4324 clock-names = "camnoc_axi", 4325 "cpas_ahb", 4326 "cphy_rx_src", 4327 "csi0", 4328 "csi0_src", 4329 "csi1", 4330 "csi1_src", 4331 "csi2", 4332 "csi2_src", 4333 "csiphy0", 4334 "csiphy0_timer", 4335 "csiphy0_timer_src", 4336 "csiphy1", 4337 "csiphy1_timer", 4338 "csiphy1_timer_src", 4339 "csiphy2", 4340 "csiphy2_timer", 4341 "csiphy2_timer_src", 4342 "csiphy3", 4343 "csiphy3_timer", 4344 "csiphy3_timer_src", 4345 "gcc_camera_ahb", 4346 "gcc_camera_axi", 4347 "slow_ahb_src", 4348 "soc_ahb", 4349 "vfe0_axi", 4350 "vfe0", 4351 "vfe0_cphy_rx", 4352 "vfe0_src", 4353 "vfe1_axi", 4354 "vfe1", 4355 "vfe1_cphy_rx", 4356 "vfe1_src", 4357 "vfe_lite", 4358 "vfe_lite_cphy_rx", 4359 "vfe_lite_src"; 4360 4361 iommus = <&apps_smmu 0x0808 0x0>, 4362 <&apps_smmu 0x0810 0x8>, 4363 <&apps_smmu 0x0c08 0x0>, 4364 <&apps_smmu 0x0c10 0x8>; 4365 4366 status = "disabled"; 4367 4368 ports { 4369 #address-cells = <1>; 4370 #size-cells = <0>; 4371 4372 port@0 { 4373 reg = <0>; 4374 }; 4375 4376 port@1 { 4377 reg = <1>; 4378 }; 4379 4380 port@2 { 4381 reg = <2>; 4382 }; 4383 4384 port@3 { 4385 reg = <3>; 4386 }; 4387 }; 4388 }; 4389 4390 cci: cci@ac4a000 { 4391 compatible = "qcom,sdm845-cci"; 4392 #address-cells = <1>; 4393 #size-cells = <0>; 4394 4395 reg = <0 0x0ac4a000 0 0x4000>; 4396 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>; 4397 power-domains = <&clock_camcc TITAN_TOP_GDSC>; 4398 4399 clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, 4400 <&clock_camcc CAM_CC_SOC_AHB_CLK>, 4401 <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, 4402 <&clock_camcc CAM_CC_CPAS_AHB_CLK>, 4403 <&clock_camcc CAM_CC_CCI_CLK>, 4404 <&clock_camcc CAM_CC_CCI_CLK_SRC>; 4405 clock-names = "camnoc_axi", 4406 "soc_ahb", 4407 "slow_ahb_src", 4408 "cpas_ahb", 4409 "cci", 4410 "cci_src"; 4411 4412 assigned-clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, 4413 <&clock_camcc CAM_CC_CCI_CLK>; 4414 assigned-clock-rates = <80000000>, <37500000>; 4415 4416 pinctrl-names = "default", "sleep"; 4417 pinctrl-0 = <&cci0_default &cci1_default>; 4418 pinctrl-1 = <&cci0_sleep &cci1_sleep>; 4419 4420 status = "disabled"; 4421 4422 cci_i2c0: i2c-bus@0 { 4423 reg = <0>; 4424 clock-frequency = <1000000>; 4425 #address-cells = <1>; 4426 #size-cells = <0>; 4427 }; 4428 4429 cci_i2c1: i2c-bus@1 { 4430 reg = <1>; 4431 clock-frequency = <1000000>; 4432 #address-cells = <1>; 4433 #size-cells = <0>; 4434 }; 4435 }; 4436 4437 clock_camcc: clock-controller@ad00000 { 4438 compatible = "qcom,sdm845-camcc"; 4439 reg = <0 0x0ad00000 0 0x10000>; 4440 #clock-cells = <1>; 4441 #reset-cells = <1>; 4442 #power-domain-cells = <1>; 4443 clocks = <&rpmhcc RPMH_CXO_CLK>; 4444 clock-names = "bi_tcxo"; 4445 }; 4446 4447 dsi_opp_table: opp-table-dsi { 4448 compatible = "operating-points-v2"; 4449 4450 opp-19200000 { 4451 opp-hz = /bits/ 64 <19200000>; 4452 required-opps = <&rpmhpd_opp_min_svs>; 4453 }; 4454 4455 opp-180000000 { 4456 opp-hz = /bits/ 64 <180000000>; 4457 required-opps = <&rpmhpd_opp_low_svs>; 4458 }; 4459 4460 opp-275000000 { 4461 opp-hz = /bits/ 64 <275000000>; 4462 required-opps = <&rpmhpd_opp_svs>; 4463 }; 4464 4465 opp-328580000 { 4466 opp-hz = /bits/ 64 <328580000>; 4467 required-opps = <&rpmhpd_opp_svs_l1>; 4468 }; 4469 4470 opp-358000000 { 4471 opp-hz = /bits/ 64 <358000000>; 4472 required-opps = <&rpmhpd_opp_nom>; 4473 }; 4474 }; 4475 4476 mdss: mdss@ae00000 { 4477 compatible = "qcom,sdm845-mdss"; 4478 reg = <0 0x0ae00000 0 0x1000>; 4479 reg-names = "mdss"; 4480 4481 power-domains = <&dispcc MDSS_GDSC>; 4482 4483 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4484 <&dispcc DISP_CC_MDSS_MDP_CLK>; 4485 clock-names = "iface", "core"; 4486 4487 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 4488 interrupt-controller; 4489 #interrupt-cells = <1>; 4490 4491 interconnects = <&mmss_noc MASTER_MDP0 0 &mem_noc SLAVE_EBI1 0>, 4492 <&mmss_noc MASTER_MDP1 0 &mem_noc SLAVE_EBI1 0>; 4493 interconnect-names = "mdp0-mem", "mdp1-mem"; 4494 4495 iommus = <&apps_smmu 0x880 0x8>, 4496 <&apps_smmu 0xc80 0x8>; 4497 4498 status = "disabled"; 4499 4500 #address-cells = <2>; 4501 #size-cells = <2>; 4502 ranges; 4503 4504 mdss_mdp: display-controller@ae01000 { 4505 compatible = "qcom,sdm845-dpu"; 4506 reg = <0 0x0ae01000 0 0x8f000>, 4507 <0 0x0aeb0000 0 0x2008>; 4508 reg-names = "mdp", "vbif"; 4509 4510 clocks = <&gcc GCC_DISP_AXI_CLK>, 4511 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4512 <&dispcc DISP_CC_MDSS_AXI_CLK>, 4513 <&dispcc DISP_CC_MDSS_MDP_CLK>, 4514 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 4515 clock-names = "gcc-bus", "iface", "bus", "core", "vsync"; 4516 4517 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 4518 assigned-clock-rates = <19200000>; 4519 operating-points-v2 = <&mdp_opp_table>; 4520 power-domains = <&rpmhpd SDM845_CX>; 4521 4522 interrupt-parent = <&mdss>; 4523 interrupts = <0>; 4524 4525 ports { 4526 #address-cells = <1>; 4527 #size-cells = <0>; 4528 4529 port@0 { 4530 reg = <0>; 4531 dpu_intf0_out: endpoint { 4532 remote-endpoint = <&dp_in>; 4533 }; 4534 }; 4535 4536 port@1 { 4537 reg = <1>; 4538 dpu_intf1_out: endpoint { 4539 remote-endpoint = <&dsi0_in>; 4540 }; 4541 }; 4542 4543 port@2 { 4544 reg = <2>; 4545 dpu_intf2_out: endpoint { 4546 remote-endpoint = <&dsi1_in>; 4547 }; 4548 }; 4549 }; 4550 4551 mdp_opp_table: opp-table { 4552 compatible = "operating-points-v2"; 4553 4554 opp-19200000 { 4555 opp-hz = /bits/ 64 <19200000>; 4556 required-opps = <&rpmhpd_opp_min_svs>; 4557 }; 4558 4559 opp-171428571 { 4560 opp-hz = /bits/ 64 <171428571>; 4561 required-opps = <&rpmhpd_opp_low_svs>; 4562 }; 4563 4564 opp-344000000 { 4565 opp-hz = /bits/ 64 <344000000>; 4566 required-opps = <&rpmhpd_opp_svs_l1>; 4567 }; 4568 4569 opp-430000000 { 4570 opp-hz = /bits/ 64 <430000000>; 4571 required-opps = <&rpmhpd_opp_nom>; 4572 }; 4573 }; 4574 }; 4575 4576 mdss_dp: displayport-controller@ae90000 { 4577 status = "disabled"; 4578 compatible = "qcom,sdm845-dp"; 4579 4580 reg = <0 0xae90000 0 0x200>, 4581 <0 0xae90200 0 0x200>, 4582 <0 0xae90400 0 0x600>, 4583 <0 0xae90a00 0 0x600>, 4584 <0 0xae91000 0 0x600>; 4585 4586 interrupt-parent = <&mdss>; 4587 interrupts = <12>; 4588 4589 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4590 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 4591 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 4592 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 4593 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 4594 clock-names = "core_iface", "core_aux", "ctrl_link", 4595 "ctrl_link_iface", "stream_pixel"; 4596 #clock-cells = <1>; 4597 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 4598 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 4599 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>; 4600 phys = <&dp_phy>; 4601 phy-names = "dp"; 4602 4603 operating-points-v2 = <&dp_opp_table>; 4604 power-domains = <&rpmhpd SDM845_CX>; 4605 4606 ports { 4607 #address-cells = <1>; 4608 #size-cells = <0>; 4609 port@0 { 4610 reg = <0>; 4611 dp_in: endpoint { 4612 remote-endpoint = <&dpu_intf0_out>; 4613 }; 4614 }; 4615 4616 port@1 { 4617 reg = <1>; 4618 dp_out: endpoint { }; 4619 }; 4620 }; 4621 4622 dp_opp_table: dp-opp-table { 4623 compatible = "operating-points-v2"; 4624 4625 opp-162000000 { 4626 opp-hz = /bits/ 64 <162000000>; 4627 required-opps = <&rpmhpd_opp_low_svs>; 4628 }; 4629 4630 opp-270000000 { 4631 opp-hz = /bits/ 64 <270000000>; 4632 required-opps = <&rpmhpd_opp_svs>; 4633 }; 4634 4635 opp-540000000 { 4636 opp-hz = /bits/ 64 <540000000>; 4637 required-opps = <&rpmhpd_opp_svs_l1>; 4638 }; 4639 4640 opp-810000000 { 4641 opp-hz = /bits/ 64 <810000000>; 4642 required-opps = <&rpmhpd_opp_nom>; 4643 }; 4644 }; 4645 }; 4646 4647 dsi0: dsi@ae94000 { 4648 compatible = "qcom,mdss-dsi-ctrl"; 4649 reg = <0 0x0ae94000 0 0x400>; 4650 reg-names = "dsi_ctrl"; 4651 4652 interrupt-parent = <&mdss>; 4653 interrupts = <4>; 4654 4655 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 4656 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 4657 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 4658 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 4659 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4660 <&dispcc DISP_CC_MDSS_AXI_CLK>; 4661 clock-names = "byte", 4662 "byte_intf", 4663 "pixel", 4664 "core", 4665 "iface", 4666 "bus"; 4667 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 4668 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; 4669 4670 operating-points-v2 = <&dsi_opp_table>; 4671 power-domains = <&rpmhpd SDM845_CX>; 4672 4673 phys = <&dsi0_phy>; 4674 4675 status = "disabled"; 4676 4677 #address-cells = <1>; 4678 #size-cells = <0>; 4679 4680 ports { 4681 #address-cells = <1>; 4682 #size-cells = <0>; 4683 4684 port@0 { 4685 reg = <0>; 4686 dsi0_in: endpoint { 4687 remote-endpoint = <&dpu_intf1_out>; 4688 }; 4689 }; 4690 4691 port@1 { 4692 reg = <1>; 4693 dsi0_out: endpoint { 4694 }; 4695 }; 4696 }; 4697 }; 4698 4699 dsi0_phy: phy@ae94400 { 4700 compatible = "qcom,dsi-phy-10nm"; 4701 reg = <0 0x0ae94400 0 0x200>, 4702 <0 0x0ae94600 0 0x280>, 4703 <0 0x0ae94a00 0 0x1e0>; 4704 reg-names = "dsi_phy", 4705 "dsi_phy_lane", 4706 "dsi_pll"; 4707 4708 #clock-cells = <1>; 4709 #phy-cells = <0>; 4710 4711 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4712 <&rpmhcc RPMH_CXO_CLK>; 4713 clock-names = "iface", "ref"; 4714 4715 status = "disabled"; 4716 }; 4717 4718 dsi1: dsi@ae96000 { 4719 compatible = "qcom,mdss-dsi-ctrl"; 4720 reg = <0 0x0ae96000 0 0x400>; 4721 reg-names = "dsi_ctrl"; 4722 4723 interrupt-parent = <&mdss>; 4724 interrupts = <5>; 4725 4726 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 4727 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 4728 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 4729 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 4730 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4731 <&dispcc DISP_CC_MDSS_AXI_CLK>; 4732 clock-names = "byte", 4733 "byte_intf", 4734 "pixel", 4735 "core", 4736 "iface", 4737 "bus"; 4738 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 4739 assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>; 4740 4741 operating-points-v2 = <&dsi_opp_table>; 4742 power-domains = <&rpmhpd SDM845_CX>; 4743 4744 phys = <&dsi1_phy>; 4745 4746 status = "disabled"; 4747 4748 #address-cells = <1>; 4749 #size-cells = <0>; 4750 4751 ports { 4752 #address-cells = <1>; 4753 #size-cells = <0>; 4754 4755 port@0 { 4756 reg = <0>; 4757 dsi1_in: endpoint { 4758 remote-endpoint = <&dpu_intf2_out>; 4759 }; 4760 }; 4761 4762 port@1 { 4763 reg = <1>; 4764 dsi1_out: endpoint { 4765 }; 4766 }; 4767 }; 4768 }; 4769 4770 dsi1_phy: phy@ae96400 { 4771 compatible = "qcom,dsi-phy-10nm"; 4772 reg = <0 0x0ae96400 0 0x200>, 4773 <0 0x0ae96600 0 0x280>, 4774 <0 0x0ae96a00 0 0x10e>; 4775 reg-names = "dsi_phy", 4776 "dsi_phy_lane", 4777 "dsi_pll"; 4778 4779 #clock-cells = <1>; 4780 #phy-cells = <0>; 4781 4782 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4783 <&rpmhcc RPMH_CXO_CLK>; 4784 clock-names = "iface", "ref"; 4785 4786 status = "disabled"; 4787 }; 4788 }; 4789 4790 gpu: gpu@5000000 { 4791 compatible = "qcom,adreno-630.2", "qcom,adreno"; 4792 4793 reg = <0 0x5000000 0 0x40000>, <0 0x509e000 0 0x10>; 4794 reg-names = "kgsl_3d0_reg_memory", "cx_mem"; 4795 4796 /* 4797 * Look ma, no clocks! The GPU clocks and power are 4798 * controlled entirely by the GMU 4799 */ 4800 4801 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 4802 4803 iommus = <&adreno_smmu 0>; 4804 4805 operating-points-v2 = <&gpu_opp_table>; 4806 4807 qcom,gmu = <&gmu>; 4808 4809 interconnects = <&mem_noc MASTER_GFX3D 0 &mem_noc SLAVE_EBI1 0>; 4810 interconnect-names = "gfx-mem"; 4811 4812 status = "disabled"; 4813 4814 gpu_opp_table: opp-table { 4815 compatible = "operating-points-v2"; 4816 4817 opp-710000000 { 4818 opp-hz = /bits/ 64 <710000000>; 4819 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4820 opp-peak-kBps = <7216000>; 4821 }; 4822 4823 opp-675000000 { 4824 opp-hz = /bits/ 64 <675000000>; 4825 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4826 opp-peak-kBps = <7216000>; 4827 }; 4828 4829 opp-596000000 { 4830 opp-hz = /bits/ 64 <596000000>; 4831 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4832 opp-peak-kBps = <6220000>; 4833 }; 4834 4835 opp-520000000 { 4836 opp-hz = /bits/ 64 <520000000>; 4837 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4838 opp-peak-kBps = <6220000>; 4839 }; 4840 4841 opp-414000000 { 4842 opp-hz = /bits/ 64 <414000000>; 4843 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4844 opp-peak-kBps = <4068000>; 4845 }; 4846 4847 opp-342000000 { 4848 opp-hz = /bits/ 64 <342000000>; 4849 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4850 opp-peak-kBps = <2724000>; 4851 }; 4852 4853 opp-257000000 { 4854 opp-hz = /bits/ 64 <257000000>; 4855 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4856 opp-peak-kBps = <1648000>; 4857 }; 4858 }; 4859 }; 4860 4861 adreno_smmu: iommu@5040000 { 4862 compatible = "qcom,sdm845-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2"; 4863 reg = <0 0x5040000 0 0x10000>; 4864 #iommu-cells = <1>; 4865 #global-interrupts = <2>; 4866 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 4867 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 4868 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, 4869 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, 4870 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>, 4871 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>, 4872 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>, 4873 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>, 4874 <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>, 4875 <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>; 4876 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 4877 <&gcc GCC_GPU_CFG_AHB_CLK>; 4878 clock-names = "bus", "iface"; 4879 4880 power-domains = <&gpucc GPU_CX_GDSC>; 4881 }; 4882 4883 gmu: gmu@506a000 { 4884 compatible = "qcom,adreno-gmu-630.2", "qcom,adreno-gmu"; 4885 4886 reg = <0 0x506a000 0 0x30000>, 4887 <0 0xb280000 0 0x10000>, 4888 <0 0xb480000 0 0x10000>; 4889 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; 4890 4891 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 4892 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 4893 interrupt-names = "hfi", "gmu"; 4894 4895 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 4896 <&gpucc GPU_CC_CXO_CLK>, 4897 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 4898 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 4899 clock-names = "gmu", "cxo", "axi", "memnoc"; 4900 4901 power-domains = <&gpucc GPU_CX_GDSC>, 4902 <&gpucc GPU_GX_GDSC>; 4903 power-domain-names = "cx", "gx"; 4904 4905 iommus = <&adreno_smmu 5>; 4906 4907 operating-points-v2 = <&gmu_opp_table>; 4908 4909 status = "disabled"; 4910 4911 gmu_opp_table: opp-table { 4912 compatible = "operating-points-v2"; 4913 4914 opp-400000000 { 4915 opp-hz = /bits/ 64 <400000000>; 4916 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4917 }; 4918 4919 opp-200000000 { 4920 opp-hz = /bits/ 64 <200000000>; 4921 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 4922 }; 4923 }; 4924 }; 4925 4926 dispcc: clock-controller@af00000 { 4927 compatible = "qcom,sdm845-dispcc"; 4928 reg = <0 0x0af00000 0 0x10000>; 4929 clocks = <&rpmhcc RPMH_CXO_CLK>, 4930 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 4931 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, 4932 <&dsi0_phy 0>, 4933 <&dsi0_phy 1>, 4934 <&dsi1_phy 0>, 4935 <&dsi1_phy 1>, 4936 <&dp_phy 0>, 4937 <&dp_phy 1>; 4938 clock-names = "bi_tcxo", 4939 "gcc_disp_gpll0_clk_src", 4940 "gcc_disp_gpll0_div_clk_src", 4941 "dsi0_phy_pll_out_byteclk", 4942 "dsi0_phy_pll_out_dsiclk", 4943 "dsi1_phy_pll_out_byteclk", 4944 "dsi1_phy_pll_out_dsiclk", 4945 "dp_link_clk_divsel_ten", 4946 "dp_vco_divided_clk_src_mux"; 4947 #clock-cells = <1>; 4948 #reset-cells = <1>; 4949 #power-domain-cells = <1>; 4950 }; 4951 4952 pdc_intc: interrupt-controller@b220000 { 4953 compatible = "qcom,sdm845-pdc", "qcom,pdc"; 4954 reg = <0 0x0b220000 0 0x30000>; 4955 qcom,pdc-ranges = <0 480 94>, <94 609 15>, <115 630 7>; 4956 #interrupt-cells = <2>; 4957 interrupt-parent = <&intc>; 4958 interrupt-controller; 4959 }; 4960 4961 pdc_reset: reset-controller@b2e0000 { 4962 compatible = "qcom,sdm845-pdc-global"; 4963 reg = <0 0x0b2e0000 0 0x20000>; 4964 #reset-cells = <1>; 4965 }; 4966 4967 tsens0: thermal-sensor@c263000 { 4968 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; 4969 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 4970 <0 0x0c222000 0 0x1ff>; /* SROT */ 4971 #qcom,sensors = <13>; 4972 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 4973 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 4974 interrupt-names = "uplow", "critical"; 4975 #thermal-sensor-cells = <1>; 4976 }; 4977 4978 tsens1: thermal-sensor@c265000 { 4979 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; 4980 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 4981 <0 0x0c223000 0 0x1ff>; /* SROT */ 4982 #qcom,sensors = <8>; 4983 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 4984 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 4985 interrupt-names = "uplow", "critical"; 4986 #thermal-sensor-cells = <1>; 4987 }; 4988 4989 aoss_reset: reset-controller@c2a0000 { 4990 compatible = "qcom,sdm845-aoss-cc"; 4991 reg = <0 0x0c2a0000 0 0x31000>; 4992 #reset-cells = <1>; 4993 }; 4994 4995 aoss_qmp: power-controller@c300000 { 4996 compatible = "qcom,sdm845-aoss-qmp", "qcom,aoss-qmp"; 4997 reg = <0 0x0c300000 0 0x400>; 4998 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; 4999 mboxes = <&apss_shared 0>; 5000 5001 #clock-cells = <0>; 5002 5003 cx_cdev: cx { 5004 #cooling-cells = <2>; 5005 }; 5006 5007 ebi_cdev: ebi { 5008 #cooling-cells = <2>; 5009 }; 5010 }; 5011 5012 sram@c3f0000 { 5013 compatible = "qcom,sdm845-rpmh-stats"; 5014 reg = <0 0x0c3f0000 0 0x400>; 5015 }; 5016 5017 spmi_bus: spmi@c440000 { 5018 compatible = "qcom,spmi-pmic-arb"; 5019 reg = <0 0x0c440000 0 0x1100>, 5020 <0 0x0c600000 0 0x2000000>, 5021 <0 0x0e600000 0 0x100000>, 5022 <0 0x0e700000 0 0xa0000>, 5023 <0 0x0c40a000 0 0x26000>; 5024 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 5025 interrupt-names = "periph_irq"; 5026 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>; 5027 qcom,ee = <0>; 5028 qcom,channel = <0>; 5029 #address-cells = <2>; 5030 #size-cells = <0>; 5031 interrupt-controller; 5032 #interrupt-cells = <4>; 5033 cell-index = <0>; 5034 }; 5035 5036 sram@146bf000 { 5037 compatible = "qcom,sdm845-imem", "syscon", "simple-mfd"; 5038 reg = <0 0x146bf000 0 0x1000>; 5039 5040 #address-cells = <1>; 5041 #size-cells = <1>; 5042 5043 ranges = <0 0 0x146bf000 0x1000>; 5044 5045 pil-reloc@94c { 5046 compatible = "qcom,pil-reloc-info"; 5047 reg = <0x94c 0xc8>; 5048 }; 5049 }; 5050 5051 apps_smmu: iommu@15000000 { 5052 compatible = "qcom,sdm845-smmu-500", "arm,mmu-500"; 5053 reg = <0 0x15000000 0 0x80000>; 5054 #iommu-cells = <2>; 5055 #global-interrupts = <1>; 5056 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 5057 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 5058 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 5059 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 5060 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 5061 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 5062 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 5063 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 5064 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 5065 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 5066 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 5067 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 5068 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 5069 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 5070 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 5071 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 5072 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 5073 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 5074 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 5075 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 5076 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 5077 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 5078 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 5079 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 5080 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 5081 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 5082 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 5083 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 5084 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 5085 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 5086 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 5087 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 5088 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 5089 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 5090 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 5091 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 5092 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 5093 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 5094 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 5095 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 5096 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 5097 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 5098 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 5099 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 5100 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 5101 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 5102 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 5103 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 5104 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 5105 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 5106 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 5107 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 5108 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 5109 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 5110 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 5111 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 5112 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 5113 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 5114 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 5115 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 5116 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 5117 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 5118 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 5119 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 5120 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>; 5121 }; 5122 5123 lpasscc: clock-controller@17014000 { 5124 compatible = "qcom,sdm845-lpasscc"; 5125 reg = <0 0x17014000 0 0x1f004>, <0 0x17300000 0 0x200>; 5126 reg-names = "cc", "qdsp6ss"; 5127 #clock-cells = <1>; 5128 status = "disabled"; 5129 }; 5130 5131 gladiator_noc: interconnect@17900000 { 5132 compatible = "qcom,sdm845-gladiator-noc"; 5133 reg = <0 0x17900000 0 0xd080>; 5134 #interconnect-cells = <2>; 5135 qcom,bcm-voters = <&apps_bcm_voter>; 5136 }; 5137 5138 watchdog@17980000 { 5139 compatible = "qcom,apss-wdt-sdm845", "qcom,kpss-wdt"; 5140 reg = <0 0x17980000 0 0x1000>; 5141 clocks = <&sleep_clk>; 5142 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 5143 }; 5144 5145 apss_shared: mailbox@17990000 { 5146 compatible = "qcom,sdm845-apss-shared"; 5147 reg = <0 0x17990000 0 0x1000>; 5148 #mbox-cells = <1>; 5149 }; 5150 5151 apps_rsc: rsc@179c0000 { 5152 label = "apps_rsc"; 5153 compatible = "qcom,rpmh-rsc"; 5154 reg = <0 0x179c0000 0 0x10000>, 5155 <0 0x179d0000 0 0x10000>, 5156 <0 0x179e0000 0 0x10000>; 5157 reg-names = "drv-0", "drv-1", "drv-2"; 5158 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 5159 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 5160 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 5161 qcom,tcs-offset = <0xd00>; 5162 qcom,drv-id = <2>; 5163 qcom,tcs-config = <ACTIVE_TCS 2>, 5164 <SLEEP_TCS 3>, 5165 <WAKE_TCS 3>, 5166 <CONTROL_TCS 1>; 5167 5168 apps_bcm_voter: bcm-voter { 5169 compatible = "qcom,bcm-voter"; 5170 }; 5171 5172 rpmhcc: clock-controller { 5173 compatible = "qcom,sdm845-rpmh-clk"; 5174 #clock-cells = <1>; 5175 clock-names = "xo"; 5176 clocks = <&xo_board>; 5177 }; 5178 5179 rpmhpd: power-controller { 5180 compatible = "qcom,sdm845-rpmhpd"; 5181 #power-domain-cells = <1>; 5182 operating-points-v2 = <&rpmhpd_opp_table>; 5183 5184 rpmhpd_opp_table: opp-table { 5185 compatible = "operating-points-v2"; 5186 5187 rpmhpd_opp_ret: opp1 { 5188 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 5189 }; 5190 5191 rpmhpd_opp_min_svs: opp2 { 5192 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 5193 }; 5194 5195 rpmhpd_opp_low_svs: opp3 { 5196 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 5197 }; 5198 5199 rpmhpd_opp_svs: opp4 { 5200 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 5201 }; 5202 5203 rpmhpd_opp_svs_l1: opp5 { 5204 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 5205 }; 5206 5207 rpmhpd_opp_nom: opp6 { 5208 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 5209 }; 5210 5211 rpmhpd_opp_nom_l1: opp7 { 5212 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 5213 }; 5214 5215 rpmhpd_opp_nom_l2: opp8 { 5216 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 5217 }; 5218 5219 rpmhpd_opp_turbo: opp9 { 5220 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 5221 }; 5222 5223 rpmhpd_opp_turbo_l1: opp10 { 5224 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 5225 }; 5226 }; 5227 }; 5228 }; 5229 5230 intc: interrupt-controller@17a00000 { 5231 compatible = "arm,gic-v3"; 5232 #address-cells = <2>; 5233 #size-cells = <2>; 5234 ranges; 5235 #interrupt-cells = <3>; 5236 interrupt-controller; 5237 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 5238 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 5239 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 5240 5241 msi-controller@17a40000 { 5242 compatible = "arm,gic-v3-its"; 5243 msi-controller; 5244 #msi-cells = <1>; 5245 reg = <0 0x17a40000 0 0x20000>; 5246 status = "disabled"; 5247 }; 5248 }; 5249 5250 slimbam: dma-controller@17184000 { 5251 compatible = "qcom,bam-v1.7.0"; 5252 qcom,controlled-remotely; 5253 reg = <0 0x17184000 0 0x2a000>; 5254 num-channels = <31>; 5255 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 5256 #dma-cells = <1>; 5257 qcom,ee = <1>; 5258 qcom,num-ees = <2>; 5259 iommus = <&apps_smmu 0x1806 0x0>; 5260 }; 5261 5262 timer@17c90000 { 5263 #address-cells = <1>; 5264 #size-cells = <1>; 5265 ranges = <0 0 0 0x20000000>; 5266 compatible = "arm,armv7-timer-mem"; 5267 reg = <0 0x17c90000 0 0x1000>; 5268 5269 frame@17ca0000 { 5270 frame-number = <0>; 5271 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 5272 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 5273 reg = <0x17ca0000 0x1000>, 5274 <0x17cb0000 0x1000>; 5275 }; 5276 5277 frame@17cc0000 { 5278 frame-number = <1>; 5279 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 5280 reg = <0x17cc0000 0x1000>; 5281 status = "disabled"; 5282 }; 5283 5284 frame@17cd0000 { 5285 frame-number = <2>; 5286 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 5287 reg = <0x17cd0000 0x1000>; 5288 status = "disabled"; 5289 }; 5290 5291 frame@17ce0000 { 5292 frame-number = <3>; 5293 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 5294 reg = <0x17ce0000 0x1000>; 5295 status = "disabled"; 5296 }; 5297 5298 frame@17cf0000 { 5299 frame-number = <4>; 5300 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 5301 reg = <0x17cf0000 0x1000>; 5302 status = "disabled"; 5303 }; 5304 5305 frame@17d00000 { 5306 frame-number = <5>; 5307 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 5308 reg = <0x17d00000 0x1000>; 5309 status = "disabled"; 5310 }; 5311 5312 frame@17d10000 { 5313 frame-number = <6>; 5314 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 5315 reg = <0x17d10000 0x1000>; 5316 status = "disabled"; 5317 }; 5318 }; 5319 5320 osm_l3: interconnect@17d41000 { 5321 compatible = "qcom,sdm845-osm-l3", "qcom,osm-l3"; 5322 reg = <0 0x17d41000 0 0x1400>; 5323 5324 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 5325 clock-names = "xo", "alternate"; 5326 5327 #interconnect-cells = <1>; 5328 }; 5329 5330 cpufreq_hw: cpufreq@17d43000 { 5331 compatible = "qcom,cpufreq-hw"; 5332 reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>; 5333 reg-names = "freq-domain0", "freq-domain1"; 5334 5335 interrupts-extended = <&lmh_cluster0 0>, <&lmh_cluster1 0>; 5336 5337 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 5338 clock-names = "xo", "alternate"; 5339 5340 #freq-domain-cells = <1>; 5341 }; 5342 5343 wifi: wifi@18800000 { 5344 compatible = "qcom,wcn3990-wifi"; 5345 status = "disabled"; 5346 reg = <0 0x18800000 0 0x800000>; 5347 reg-names = "membase"; 5348 memory-region = <&wlan_msa_mem>; 5349 clock-names = "cxo_ref_clk_pin"; 5350 clocks = <&rpmhcc RPMH_RF_CLK2>; 5351 interrupts = 5352 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 5353 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 5354 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 5355 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 5356 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 5357 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 5358 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 5359 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 5360 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 5361 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 5362 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 5363 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 5364 iommus = <&apps_smmu 0x0040 0x1>; 5365 }; 5366 }; 5367 5368 thermal-zones { 5369 cpu0-thermal { 5370 polling-delay-passive = <250>; 5371 polling-delay = <1000>; 5372 5373 thermal-sensors = <&tsens0 1>; 5374 5375 trips { 5376 cpu0_alert0: trip-point0 { 5377 temperature = <90000>; 5378 hysteresis = <2000>; 5379 type = "passive"; 5380 }; 5381 5382 cpu0_alert1: trip-point1 { 5383 temperature = <95000>; 5384 hysteresis = <2000>; 5385 type = "passive"; 5386 }; 5387 5388 cpu0_crit: cpu_crit { 5389 temperature = <110000>; 5390 hysteresis = <1000>; 5391 type = "critical"; 5392 }; 5393 }; 5394 }; 5395 5396 cpu1-thermal { 5397 polling-delay-passive = <250>; 5398 polling-delay = <1000>; 5399 5400 thermal-sensors = <&tsens0 2>; 5401 5402 trips { 5403 cpu1_alert0: trip-point0 { 5404 temperature = <90000>; 5405 hysteresis = <2000>; 5406 type = "passive"; 5407 }; 5408 5409 cpu1_alert1: trip-point1 { 5410 temperature = <95000>; 5411 hysteresis = <2000>; 5412 type = "passive"; 5413 }; 5414 5415 cpu1_crit: cpu_crit { 5416 temperature = <110000>; 5417 hysteresis = <1000>; 5418 type = "critical"; 5419 }; 5420 }; 5421 }; 5422 5423 cpu2-thermal { 5424 polling-delay-passive = <250>; 5425 polling-delay = <1000>; 5426 5427 thermal-sensors = <&tsens0 3>; 5428 5429 trips { 5430 cpu2_alert0: trip-point0 { 5431 temperature = <90000>; 5432 hysteresis = <2000>; 5433 type = "passive"; 5434 }; 5435 5436 cpu2_alert1: trip-point1 { 5437 temperature = <95000>; 5438 hysteresis = <2000>; 5439 type = "passive"; 5440 }; 5441 5442 cpu2_crit: cpu_crit { 5443 temperature = <110000>; 5444 hysteresis = <1000>; 5445 type = "critical"; 5446 }; 5447 }; 5448 }; 5449 5450 cpu3-thermal { 5451 polling-delay-passive = <250>; 5452 polling-delay = <1000>; 5453 5454 thermal-sensors = <&tsens0 4>; 5455 5456 trips { 5457 cpu3_alert0: trip-point0 { 5458 temperature = <90000>; 5459 hysteresis = <2000>; 5460 type = "passive"; 5461 }; 5462 5463 cpu3_alert1: trip-point1 { 5464 temperature = <95000>; 5465 hysteresis = <2000>; 5466 type = "passive"; 5467 }; 5468 5469 cpu3_crit: cpu_crit { 5470 temperature = <110000>; 5471 hysteresis = <1000>; 5472 type = "critical"; 5473 }; 5474 }; 5475 }; 5476 5477 cpu4-thermal { 5478 polling-delay-passive = <250>; 5479 polling-delay = <1000>; 5480 5481 thermal-sensors = <&tsens0 7>; 5482 5483 trips { 5484 cpu4_alert0: trip-point0 { 5485 temperature = <90000>; 5486 hysteresis = <2000>; 5487 type = "passive"; 5488 }; 5489 5490 cpu4_alert1: trip-point1 { 5491 temperature = <95000>; 5492 hysteresis = <2000>; 5493 type = "passive"; 5494 }; 5495 5496 cpu4_crit: cpu_crit { 5497 temperature = <110000>; 5498 hysteresis = <1000>; 5499 type = "critical"; 5500 }; 5501 }; 5502 }; 5503 5504 cpu5-thermal { 5505 polling-delay-passive = <250>; 5506 polling-delay = <1000>; 5507 5508 thermal-sensors = <&tsens0 8>; 5509 5510 trips { 5511 cpu5_alert0: trip-point0 { 5512 temperature = <90000>; 5513 hysteresis = <2000>; 5514 type = "passive"; 5515 }; 5516 5517 cpu5_alert1: trip-point1 { 5518 temperature = <95000>; 5519 hysteresis = <2000>; 5520 type = "passive"; 5521 }; 5522 5523 cpu5_crit: cpu_crit { 5524 temperature = <110000>; 5525 hysteresis = <1000>; 5526 type = "critical"; 5527 }; 5528 }; 5529 }; 5530 5531 cpu6-thermal { 5532 polling-delay-passive = <250>; 5533 polling-delay = <1000>; 5534 5535 thermal-sensors = <&tsens0 9>; 5536 5537 trips { 5538 cpu6_alert0: trip-point0 { 5539 temperature = <90000>; 5540 hysteresis = <2000>; 5541 type = "passive"; 5542 }; 5543 5544 cpu6_alert1: trip-point1 { 5545 temperature = <95000>; 5546 hysteresis = <2000>; 5547 type = "passive"; 5548 }; 5549 5550 cpu6_crit: cpu_crit { 5551 temperature = <110000>; 5552 hysteresis = <1000>; 5553 type = "critical"; 5554 }; 5555 }; 5556 }; 5557 5558 cpu7-thermal { 5559 polling-delay-passive = <250>; 5560 polling-delay = <1000>; 5561 5562 thermal-sensors = <&tsens0 10>; 5563 5564 trips { 5565 cpu7_alert0: trip-point0 { 5566 temperature = <90000>; 5567 hysteresis = <2000>; 5568 type = "passive"; 5569 }; 5570 5571 cpu7_alert1: trip-point1 { 5572 temperature = <95000>; 5573 hysteresis = <2000>; 5574 type = "passive"; 5575 }; 5576 5577 cpu7_crit: cpu_crit { 5578 temperature = <110000>; 5579 hysteresis = <1000>; 5580 type = "critical"; 5581 }; 5582 }; 5583 }; 5584 5585 aoss0-thermal { 5586 polling-delay-passive = <250>; 5587 polling-delay = <1000>; 5588 5589 thermal-sensors = <&tsens0 0>; 5590 5591 trips { 5592 aoss0_alert0: trip-point0 { 5593 temperature = <90000>; 5594 hysteresis = <2000>; 5595 type = "hot"; 5596 }; 5597 }; 5598 }; 5599 5600 cluster0-thermal { 5601 polling-delay-passive = <250>; 5602 polling-delay = <1000>; 5603 5604 thermal-sensors = <&tsens0 5>; 5605 5606 trips { 5607 cluster0_alert0: trip-point0 { 5608 temperature = <90000>; 5609 hysteresis = <2000>; 5610 type = "hot"; 5611 }; 5612 cluster0_crit: cluster0_crit { 5613 temperature = <110000>; 5614 hysteresis = <2000>; 5615 type = "critical"; 5616 }; 5617 }; 5618 }; 5619 5620 cluster1-thermal { 5621 polling-delay-passive = <250>; 5622 polling-delay = <1000>; 5623 5624 thermal-sensors = <&tsens0 6>; 5625 5626 trips { 5627 cluster1_alert0: trip-point0 { 5628 temperature = <90000>; 5629 hysteresis = <2000>; 5630 type = "hot"; 5631 }; 5632 cluster1_crit: cluster1_crit { 5633 temperature = <110000>; 5634 hysteresis = <2000>; 5635 type = "critical"; 5636 }; 5637 }; 5638 }; 5639 5640 gpu-top-thermal { 5641 polling-delay-passive = <250>; 5642 polling-delay = <1000>; 5643 5644 thermal-sensors = <&tsens0 11>; 5645 5646 trips { 5647 gpu1_alert0: trip-point0 { 5648 temperature = <90000>; 5649 hysteresis = <2000>; 5650 type = "hot"; 5651 }; 5652 }; 5653 }; 5654 5655 gpu-bottom-thermal { 5656 polling-delay-passive = <250>; 5657 polling-delay = <1000>; 5658 5659 thermal-sensors = <&tsens0 12>; 5660 5661 trips { 5662 gpu2_alert0: trip-point0 { 5663 temperature = <90000>; 5664 hysteresis = <2000>; 5665 type = "hot"; 5666 }; 5667 }; 5668 }; 5669 5670 aoss1-thermal { 5671 polling-delay-passive = <250>; 5672 polling-delay = <1000>; 5673 5674 thermal-sensors = <&tsens1 0>; 5675 5676 trips { 5677 aoss1_alert0: trip-point0 { 5678 temperature = <90000>; 5679 hysteresis = <2000>; 5680 type = "hot"; 5681 }; 5682 }; 5683 }; 5684 5685 q6-modem-thermal { 5686 polling-delay-passive = <250>; 5687 polling-delay = <1000>; 5688 5689 thermal-sensors = <&tsens1 1>; 5690 5691 trips { 5692 q6_modem_alert0: trip-point0 { 5693 temperature = <90000>; 5694 hysteresis = <2000>; 5695 type = "hot"; 5696 }; 5697 }; 5698 }; 5699 5700 mem-thermal { 5701 polling-delay-passive = <250>; 5702 polling-delay = <1000>; 5703 5704 thermal-sensors = <&tsens1 2>; 5705 5706 trips { 5707 mem_alert0: trip-point0 { 5708 temperature = <90000>; 5709 hysteresis = <2000>; 5710 type = "hot"; 5711 }; 5712 }; 5713 }; 5714 5715 wlan-thermal { 5716 polling-delay-passive = <250>; 5717 polling-delay = <1000>; 5718 5719 thermal-sensors = <&tsens1 3>; 5720 5721 trips { 5722 wlan_alert0: trip-point0 { 5723 temperature = <90000>; 5724 hysteresis = <2000>; 5725 type = "hot"; 5726 }; 5727 }; 5728 }; 5729 5730 q6-hvx-thermal { 5731 polling-delay-passive = <250>; 5732 polling-delay = <1000>; 5733 5734 thermal-sensors = <&tsens1 4>; 5735 5736 trips { 5737 q6_hvx_alert0: trip-point0 { 5738 temperature = <90000>; 5739 hysteresis = <2000>; 5740 type = "hot"; 5741 }; 5742 }; 5743 }; 5744 5745 camera-thermal { 5746 polling-delay-passive = <250>; 5747 polling-delay = <1000>; 5748 5749 thermal-sensors = <&tsens1 5>; 5750 5751 trips { 5752 camera_alert0: trip-point0 { 5753 temperature = <90000>; 5754 hysteresis = <2000>; 5755 type = "hot"; 5756 }; 5757 }; 5758 }; 5759 5760 video-thermal { 5761 polling-delay-passive = <250>; 5762 polling-delay = <1000>; 5763 5764 thermal-sensors = <&tsens1 6>; 5765 5766 trips { 5767 video_alert0: trip-point0 { 5768 temperature = <90000>; 5769 hysteresis = <2000>; 5770 type = "hot"; 5771 }; 5772 }; 5773 }; 5774 5775 modem-thermal { 5776 polling-delay-passive = <250>; 5777 polling-delay = <1000>; 5778 5779 thermal-sensors = <&tsens1 7>; 5780 5781 trips { 5782 modem_alert0: trip-point0 { 5783 temperature = <90000>; 5784 hysteresis = <2000>; 5785 type = "hot"; 5786 }; 5787 }; 5788 }; 5789 }; 5790}; 5791