1// SPDX-License-Identifier: GPL-2.0 2/* 3 * SDM845 SoC device tree source 4 * 5 * Copyright (c) 2018, The Linux Foundation. All rights reserved. 6 */ 7 8#include <dt-bindings/clock/qcom,camcc-sdm845.h> 9#include <dt-bindings/clock/qcom,dispcc-sdm845.h> 10#include <dt-bindings/clock/qcom,gcc-sdm845.h> 11#include <dt-bindings/clock/qcom,gpucc-sdm845.h> 12#include <dt-bindings/clock/qcom,lpass-sdm845.h> 13#include <dt-bindings/clock/qcom,rpmh.h> 14#include <dt-bindings/clock/qcom,videocc-sdm845.h> 15#include <dt-bindings/dma/qcom-gpi.h> 16#include <dt-bindings/firmware/qcom,scm.h> 17#include <dt-bindings/gpio/gpio.h> 18#include <dt-bindings/interconnect/qcom,osm-l3.h> 19#include <dt-bindings/interconnect/qcom,sdm845.h> 20#include <dt-bindings/interrupt-controller/arm-gic.h> 21#include <dt-bindings/phy/phy-qcom-qusb2.h> 22#include <dt-bindings/power/qcom-rpmpd.h> 23#include <dt-bindings/reset/qcom,sdm845-aoss.h> 24#include <dt-bindings/reset/qcom,sdm845-pdc.h> 25#include <dt-bindings/soc/qcom,apr.h> 26#include <dt-bindings/soc/qcom,rpmh-rsc.h> 27#include <dt-bindings/clock/qcom,gcc-sdm845.h> 28#include <dt-bindings/thermal/thermal.h> 29 30/ { 31 interrupt-parent = <&intc>; 32 33 #address-cells = <2>; 34 #size-cells = <2>; 35 36 aliases { 37 i2c0 = &i2c0; 38 i2c1 = &i2c1; 39 i2c2 = &i2c2; 40 i2c3 = &i2c3; 41 i2c4 = &i2c4; 42 i2c5 = &i2c5; 43 i2c6 = &i2c6; 44 i2c7 = &i2c7; 45 i2c8 = &i2c8; 46 i2c9 = &i2c9; 47 i2c10 = &i2c10; 48 i2c11 = &i2c11; 49 i2c12 = &i2c12; 50 i2c13 = &i2c13; 51 i2c14 = &i2c14; 52 i2c15 = &i2c15; 53 spi0 = &spi0; 54 spi1 = &spi1; 55 spi2 = &spi2; 56 spi3 = &spi3; 57 spi4 = &spi4; 58 spi5 = &spi5; 59 spi6 = &spi6; 60 spi7 = &spi7; 61 spi8 = &spi8; 62 spi9 = &spi9; 63 spi10 = &spi10; 64 spi11 = &spi11; 65 spi12 = &spi12; 66 spi13 = &spi13; 67 spi14 = &spi14; 68 spi15 = &spi15; 69 }; 70 71 chosen { }; 72 73 clocks { 74 xo_board: xo-board { 75 compatible = "fixed-clock"; 76 #clock-cells = <0>; 77 clock-frequency = <38400000>; 78 clock-output-names = "xo_board"; 79 }; 80 81 sleep_clk: sleep-clk { 82 compatible = "fixed-clock"; 83 #clock-cells = <0>; 84 clock-frequency = <32764>; 85 }; 86 }; 87 88 cpus: cpus { 89 #address-cells = <2>; 90 #size-cells = <0>; 91 92 CPU0: cpu@0 { 93 device_type = "cpu"; 94 compatible = "qcom,kryo385"; 95 reg = <0x0 0x0>; 96 clocks = <&cpufreq_hw 0>; 97 enable-method = "psci"; 98 capacity-dmips-mhz = <611>; 99 dynamic-power-coefficient = <154>; 100 qcom,freq-domain = <&cpufreq_hw 0>; 101 operating-points-v2 = <&cpu0_opp_table>; 102 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 103 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 104 power-domains = <&CPU_PD0>; 105 power-domain-names = "psci"; 106 #cooling-cells = <2>; 107 next-level-cache = <&L2_0>; 108 L2_0: l2-cache { 109 compatible = "cache"; 110 cache-level = <2>; 111 cache-unified; 112 next-level-cache = <&L3_0>; 113 L3_0: l3-cache { 114 compatible = "cache"; 115 cache-level = <3>; 116 cache-unified; 117 }; 118 }; 119 }; 120 121 CPU1: cpu@100 { 122 device_type = "cpu"; 123 compatible = "qcom,kryo385"; 124 reg = <0x0 0x100>; 125 clocks = <&cpufreq_hw 0>; 126 enable-method = "psci"; 127 capacity-dmips-mhz = <611>; 128 dynamic-power-coefficient = <154>; 129 qcom,freq-domain = <&cpufreq_hw 0>; 130 operating-points-v2 = <&cpu0_opp_table>; 131 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 132 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 133 power-domains = <&CPU_PD1>; 134 power-domain-names = "psci"; 135 #cooling-cells = <2>; 136 next-level-cache = <&L2_100>; 137 L2_100: l2-cache { 138 compatible = "cache"; 139 cache-level = <2>; 140 cache-unified; 141 next-level-cache = <&L3_0>; 142 }; 143 }; 144 145 CPU2: cpu@200 { 146 device_type = "cpu"; 147 compatible = "qcom,kryo385"; 148 reg = <0x0 0x200>; 149 clocks = <&cpufreq_hw 0>; 150 enable-method = "psci"; 151 capacity-dmips-mhz = <611>; 152 dynamic-power-coefficient = <154>; 153 qcom,freq-domain = <&cpufreq_hw 0>; 154 operating-points-v2 = <&cpu0_opp_table>; 155 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 156 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 157 power-domains = <&CPU_PD2>; 158 power-domain-names = "psci"; 159 #cooling-cells = <2>; 160 next-level-cache = <&L2_200>; 161 L2_200: l2-cache { 162 compatible = "cache"; 163 cache-level = <2>; 164 cache-unified; 165 next-level-cache = <&L3_0>; 166 }; 167 }; 168 169 CPU3: cpu@300 { 170 device_type = "cpu"; 171 compatible = "qcom,kryo385"; 172 reg = <0x0 0x300>; 173 clocks = <&cpufreq_hw 0>; 174 enable-method = "psci"; 175 capacity-dmips-mhz = <611>; 176 dynamic-power-coefficient = <154>; 177 qcom,freq-domain = <&cpufreq_hw 0>; 178 operating-points-v2 = <&cpu0_opp_table>; 179 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 180 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 181 #cooling-cells = <2>; 182 power-domains = <&CPU_PD3>; 183 power-domain-names = "psci"; 184 next-level-cache = <&L2_300>; 185 L2_300: l2-cache { 186 compatible = "cache"; 187 cache-level = <2>; 188 cache-unified; 189 next-level-cache = <&L3_0>; 190 }; 191 }; 192 193 CPU4: cpu@400 { 194 device_type = "cpu"; 195 compatible = "qcom,kryo385"; 196 reg = <0x0 0x400>; 197 clocks = <&cpufreq_hw 1>; 198 enable-method = "psci"; 199 capacity-dmips-mhz = <1024>; 200 dynamic-power-coefficient = <442>; 201 qcom,freq-domain = <&cpufreq_hw 1>; 202 operating-points-v2 = <&cpu4_opp_table>; 203 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 204 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 205 power-domains = <&CPU_PD4>; 206 power-domain-names = "psci"; 207 #cooling-cells = <2>; 208 next-level-cache = <&L2_400>; 209 L2_400: l2-cache { 210 compatible = "cache"; 211 cache-level = <2>; 212 cache-unified; 213 next-level-cache = <&L3_0>; 214 }; 215 }; 216 217 CPU5: cpu@500 { 218 device_type = "cpu"; 219 compatible = "qcom,kryo385"; 220 reg = <0x0 0x500>; 221 clocks = <&cpufreq_hw 1>; 222 enable-method = "psci"; 223 capacity-dmips-mhz = <1024>; 224 dynamic-power-coefficient = <442>; 225 qcom,freq-domain = <&cpufreq_hw 1>; 226 operating-points-v2 = <&cpu4_opp_table>; 227 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 228 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 229 power-domains = <&CPU_PD5>; 230 power-domain-names = "psci"; 231 #cooling-cells = <2>; 232 next-level-cache = <&L2_500>; 233 L2_500: l2-cache { 234 compatible = "cache"; 235 cache-level = <2>; 236 cache-unified; 237 next-level-cache = <&L3_0>; 238 }; 239 }; 240 241 CPU6: cpu@600 { 242 device_type = "cpu"; 243 compatible = "qcom,kryo385"; 244 reg = <0x0 0x600>; 245 clocks = <&cpufreq_hw 1>; 246 enable-method = "psci"; 247 capacity-dmips-mhz = <1024>; 248 dynamic-power-coefficient = <442>; 249 qcom,freq-domain = <&cpufreq_hw 1>; 250 operating-points-v2 = <&cpu4_opp_table>; 251 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 252 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 253 power-domains = <&CPU_PD6>; 254 power-domain-names = "psci"; 255 #cooling-cells = <2>; 256 next-level-cache = <&L2_600>; 257 L2_600: l2-cache { 258 compatible = "cache"; 259 cache-level = <2>; 260 cache-unified; 261 next-level-cache = <&L3_0>; 262 }; 263 }; 264 265 CPU7: cpu@700 { 266 device_type = "cpu"; 267 compatible = "qcom,kryo385"; 268 reg = <0x0 0x700>; 269 clocks = <&cpufreq_hw 1>; 270 enable-method = "psci"; 271 capacity-dmips-mhz = <1024>; 272 dynamic-power-coefficient = <442>; 273 qcom,freq-domain = <&cpufreq_hw 1>; 274 operating-points-v2 = <&cpu4_opp_table>; 275 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 276 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 277 power-domains = <&CPU_PD7>; 278 power-domain-names = "psci"; 279 #cooling-cells = <2>; 280 next-level-cache = <&L2_700>; 281 L2_700: l2-cache { 282 compatible = "cache"; 283 cache-level = <2>; 284 cache-unified; 285 next-level-cache = <&L3_0>; 286 }; 287 }; 288 289 cpu-map { 290 cluster0 { 291 core0 { 292 cpu = <&CPU0>; 293 }; 294 295 core1 { 296 cpu = <&CPU1>; 297 }; 298 299 core2 { 300 cpu = <&CPU2>; 301 }; 302 303 core3 { 304 cpu = <&CPU3>; 305 }; 306 307 core4 { 308 cpu = <&CPU4>; 309 }; 310 311 core5 { 312 cpu = <&CPU5>; 313 }; 314 315 core6 { 316 cpu = <&CPU6>; 317 }; 318 319 core7 { 320 cpu = <&CPU7>; 321 }; 322 }; 323 }; 324 325 cpu_idle_states: idle-states { 326 entry-method = "psci"; 327 328 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 329 compatible = "arm,idle-state"; 330 idle-state-name = "little-rail-power-collapse"; 331 arm,psci-suspend-param = <0x40000004>; 332 entry-latency-us = <350>; 333 exit-latency-us = <461>; 334 min-residency-us = <1890>; 335 local-timer-stop; 336 }; 337 338 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 339 compatible = "arm,idle-state"; 340 idle-state-name = "big-rail-power-collapse"; 341 arm,psci-suspend-param = <0x40000004>; 342 entry-latency-us = <264>; 343 exit-latency-us = <621>; 344 min-residency-us = <952>; 345 local-timer-stop; 346 }; 347 }; 348 349 domain-idle-states { 350 CLUSTER_SLEEP_0: cluster-sleep-0 { 351 compatible = "domain-idle-state"; 352 arm,psci-suspend-param = <0x4100c244>; 353 entry-latency-us = <3263>; 354 exit-latency-us = <6562>; 355 min-residency-us = <9987>; 356 }; 357 }; 358 }; 359 360 firmware { 361 scm { 362 compatible = "qcom,scm-sdm845", "qcom,scm"; 363 }; 364 }; 365 366 memory@80000000 { 367 device_type = "memory"; 368 /* We expect the bootloader to fill in the size */ 369 reg = <0 0x80000000 0 0>; 370 }; 371 372 cpu0_opp_table: opp-table-cpu0 { 373 compatible = "operating-points-v2"; 374 opp-shared; 375 376 cpu0_opp1: opp-300000000 { 377 opp-hz = /bits/ 64 <300000000>; 378 opp-peak-kBps = <800000 4800000>; 379 }; 380 381 cpu0_opp2: opp-403200000 { 382 opp-hz = /bits/ 64 <403200000>; 383 opp-peak-kBps = <800000 4800000>; 384 }; 385 386 cpu0_opp3: opp-480000000 { 387 opp-hz = /bits/ 64 <480000000>; 388 opp-peak-kBps = <800000 6451200>; 389 }; 390 391 cpu0_opp4: opp-576000000 { 392 opp-hz = /bits/ 64 <576000000>; 393 opp-peak-kBps = <800000 6451200>; 394 }; 395 396 cpu0_opp5: opp-652800000 { 397 opp-hz = /bits/ 64 <652800000>; 398 opp-peak-kBps = <800000 7680000>; 399 }; 400 401 cpu0_opp6: opp-748800000 { 402 opp-hz = /bits/ 64 <748800000>; 403 opp-peak-kBps = <1804000 9216000>; 404 }; 405 406 cpu0_opp7: opp-825600000 { 407 opp-hz = /bits/ 64 <825600000>; 408 opp-peak-kBps = <1804000 9216000>; 409 }; 410 411 cpu0_opp8: opp-902400000 { 412 opp-hz = /bits/ 64 <902400000>; 413 opp-peak-kBps = <1804000 10444800>; 414 }; 415 416 cpu0_opp9: opp-979200000 { 417 opp-hz = /bits/ 64 <979200000>; 418 opp-peak-kBps = <1804000 11980800>; 419 }; 420 421 cpu0_opp10: opp-1056000000 { 422 opp-hz = /bits/ 64 <1056000000>; 423 opp-peak-kBps = <1804000 11980800>; 424 }; 425 426 cpu0_opp11: opp-1132800000 { 427 opp-hz = /bits/ 64 <1132800000>; 428 opp-peak-kBps = <2188000 13516800>; 429 }; 430 431 cpu0_opp12: opp-1228800000 { 432 opp-hz = /bits/ 64 <1228800000>; 433 opp-peak-kBps = <2188000 15052800>; 434 }; 435 436 cpu0_opp13: opp-1324800000 { 437 opp-hz = /bits/ 64 <1324800000>; 438 opp-peak-kBps = <2188000 16588800>; 439 }; 440 441 cpu0_opp14: opp-1420800000 { 442 opp-hz = /bits/ 64 <1420800000>; 443 opp-peak-kBps = <3072000 18124800>; 444 }; 445 446 cpu0_opp15: opp-1516800000 { 447 opp-hz = /bits/ 64 <1516800000>; 448 opp-peak-kBps = <3072000 19353600>; 449 }; 450 451 cpu0_opp16: opp-1612800000 { 452 opp-hz = /bits/ 64 <1612800000>; 453 opp-peak-kBps = <4068000 19353600>; 454 }; 455 456 cpu0_opp17: opp-1689600000 { 457 opp-hz = /bits/ 64 <1689600000>; 458 opp-peak-kBps = <4068000 20889600>; 459 }; 460 461 cpu0_opp18: opp-1766400000 { 462 opp-hz = /bits/ 64 <1766400000>; 463 opp-peak-kBps = <4068000 22425600>; 464 }; 465 }; 466 467 cpu4_opp_table: opp-table-cpu4 { 468 compatible = "operating-points-v2"; 469 opp-shared; 470 471 cpu4_opp1: opp-300000000 { 472 opp-hz = /bits/ 64 <300000000>; 473 opp-peak-kBps = <800000 4800000>; 474 }; 475 476 cpu4_opp2: opp-403200000 { 477 opp-hz = /bits/ 64 <403200000>; 478 opp-peak-kBps = <800000 4800000>; 479 }; 480 481 cpu4_opp3: opp-480000000 { 482 opp-hz = /bits/ 64 <480000000>; 483 opp-peak-kBps = <1804000 4800000>; 484 }; 485 486 cpu4_opp4: opp-576000000 { 487 opp-hz = /bits/ 64 <576000000>; 488 opp-peak-kBps = <1804000 4800000>; 489 }; 490 491 cpu4_opp5: opp-652800000 { 492 opp-hz = /bits/ 64 <652800000>; 493 opp-peak-kBps = <1804000 4800000>; 494 }; 495 496 cpu4_opp6: opp-748800000 { 497 opp-hz = /bits/ 64 <748800000>; 498 opp-peak-kBps = <1804000 4800000>; 499 }; 500 501 cpu4_opp7: opp-825600000 { 502 opp-hz = /bits/ 64 <825600000>; 503 opp-peak-kBps = <2188000 9216000>; 504 }; 505 506 cpu4_opp8: opp-902400000 { 507 opp-hz = /bits/ 64 <902400000>; 508 opp-peak-kBps = <2188000 9216000>; 509 }; 510 511 cpu4_opp9: opp-979200000 { 512 opp-hz = /bits/ 64 <979200000>; 513 opp-peak-kBps = <2188000 9216000>; 514 }; 515 516 cpu4_opp10: opp-1056000000 { 517 opp-hz = /bits/ 64 <1056000000>; 518 opp-peak-kBps = <3072000 9216000>; 519 }; 520 521 cpu4_opp11: opp-1132800000 { 522 opp-hz = /bits/ 64 <1132800000>; 523 opp-peak-kBps = <3072000 11980800>; 524 }; 525 526 cpu4_opp12: opp-1209600000 { 527 opp-hz = /bits/ 64 <1209600000>; 528 opp-peak-kBps = <4068000 11980800>; 529 }; 530 531 cpu4_opp13: opp-1286400000 { 532 opp-hz = /bits/ 64 <1286400000>; 533 opp-peak-kBps = <4068000 11980800>; 534 }; 535 536 cpu4_opp14: opp-1363200000 { 537 opp-hz = /bits/ 64 <1363200000>; 538 opp-peak-kBps = <4068000 15052800>; 539 }; 540 541 cpu4_opp15: opp-1459200000 { 542 opp-hz = /bits/ 64 <1459200000>; 543 opp-peak-kBps = <4068000 15052800>; 544 }; 545 546 cpu4_opp16: opp-1536000000 { 547 opp-hz = /bits/ 64 <1536000000>; 548 opp-peak-kBps = <5412000 15052800>; 549 }; 550 551 cpu4_opp17: opp-1612800000 { 552 opp-hz = /bits/ 64 <1612800000>; 553 opp-peak-kBps = <5412000 15052800>; 554 }; 555 556 cpu4_opp18: opp-1689600000 { 557 opp-hz = /bits/ 64 <1689600000>; 558 opp-peak-kBps = <5412000 19353600>; 559 }; 560 561 cpu4_opp19: opp-1766400000 { 562 opp-hz = /bits/ 64 <1766400000>; 563 opp-peak-kBps = <6220000 19353600>; 564 }; 565 566 cpu4_opp20: opp-1843200000 { 567 opp-hz = /bits/ 64 <1843200000>; 568 opp-peak-kBps = <6220000 19353600>; 569 }; 570 571 cpu4_opp21: opp-1920000000 { 572 opp-hz = /bits/ 64 <1920000000>; 573 opp-peak-kBps = <7216000 19353600>; 574 }; 575 576 cpu4_opp22: opp-1996800000 { 577 opp-hz = /bits/ 64 <1996800000>; 578 opp-peak-kBps = <7216000 20889600>; 579 }; 580 581 cpu4_opp23: opp-2092800000 { 582 opp-hz = /bits/ 64 <2092800000>; 583 opp-peak-kBps = <7216000 20889600>; 584 }; 585 586 cpu4_opp24: opp-2169600000 { 587 opp-hz = /bits/ 64 <2169600000>; 588 opp-peak-kBps = <7216000 20889600>; 589 }; 590 591 cpu4_opp25: opp-2246400000 { 592 opp-hz = /bits/ 64 <2246400000>; 593 opp-peak-kBps = <7216000 20889600>; 594 }; 595 596 cpu4_opp26: opp-2323200000 { 597 opp-hz = /bits/ 64 <2323200000>; 598 opp-peak-kBps = <7216000 20889600>; 599 }; 600 601 cpu4_opp27: opp-2400000000 { 602 opp-hz = /bits/ 64 <2400000000>; 603 opp-peak-kBps = <7216000 22425600>; 604 }; 605 606 cpu4_opp28: opp-2476800000 { 607 opp-hz = /bits/ 64 <2476800000>; 608 opp-peak-kBps = <7216000 22425600>; 609 }; 610 611 cpu4_opp29: opp-2553600000 { 612 opp-hz = /bits/ 64 <2553600000>; 613 opp-peak-kBps = <7216000 22425600>; 614 }; 615 616 cpu4_opp30: opp-2649600000 { 617 opp-hz = /bits/ 64 <2649600000>; 618 opp-peak-kBps = <7216000 22425600>; 619 }; 620 621 cpu4_opp31: opp-2745600000 { 622 opp-hz = /bits/ 64 <2745600000>; 623 opp-peak-kBps = <7216000 25497600>; 624 }; 625 626 cpu4_opp32: opp-2803200000 { 627 opp-hz = /bits/ 64 <2803200000>; 628 opp-peak-kBps = <7216000 25497600>; 629 }; 630 }; 631 632 dsi_opp_table: opp-table-dsi { 633 compatible = "operating-points-v2"; 634 635 opp-19200000 { 636 opp-hz = /bits/ 64 <19200000>; 637 required-opps = <&rpmhpd_opp_min_svs>; 638 }; 639 640 opp-180000000 { 641 opp-hz = /bits/ 64 <180000000>; 642 required-opps = <&rpmhpd_opp_low_svs>; 643 }; 644 645 opp-275000000 { 646 opp-hz = /bits/ 64 <275000000>; 647 required-opps = <&rpmhpd_opp_svs>; 648 }; 649 650 opp-328580000 { 651 opp-hz = /bits/ 64 <328580000>; 652 required-opps = <&rpmhpd_opp_svs_l1>; 653 }; 654 655 opp-358000000 { 656 opp-hz = /bits/ 64 <358000000>; 657 required-opps = <&rpmhpd_opp_nom>; 658 }; 659 }; 660 661 qspi_opp_table: opp-table-qspi { 662 compatible = "operating-points-v2"; 663 664 opp-19200000 { 665 opp-hz = /bits/ 64 <19200000>; 666 required-opps = <&rpmhpd_opp_min_svs>; 667 }; 668 669 opp-100000000 { 670 opp-hz = /bits/ 64 <100000000>; 671 required-opps = <&rpmhpd_opp_low_svs>; 672 }; 673 674 opp-150000000 { 675 opp-hz = /bits/ 64 <150000000>; 676 required-opps = <&rpmhpd_opp_svs>; 677 }; 678 679 opp-300000000 { 680 opp-hz = /bits/ 64 <300000000>; 681 required-opps = <&rpmhpd_opp_nom>; 682 }; 683 }; 684 685 qup_opp_table: opp-table-qup { 686 compatible = "operating-points-v2"; 687 688 opp-50000000 { 689 opp-hz = /bits/ 64 <50000000>; 690 required-opps = <&rpmhpd_opp_min_svs>; 691 }; 692 693 opp-75000000 { 694 opp-hz = /bits/ 64 <75000000>; 695 required-opps = <&rpmhpd_opp_low_svs>; 696 }; 697 698 opp-100000000 { 699 opp-hz = /bits/ 64 <100000000>; 700 required-opps = <&rpmhpd_opp_svs>; 701 }; 702 703 opp-128000000 { 704 opp-hz = /bits/ 64 <128000000>; 705 required-opps = <&rpmhpd_opp_nom>; 706 }; 707 }; 708 709 pmu { 710 compatible = "arm,armv8-pmuv3"; 711 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; 712 }; 713 714 psci: psci { 715 compatible = "arm,psci-1.0"; 716 method = "smc"; 717 718 CPU_PD0: power-domain-cpu0 { 719 #power-domain-cells = <0>; 720 power-domains = <&CLUSTER_PD>; 721 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 722 }; 723 724 CPU_PD1: power-domain-cpu1 { 725 #power-domain-cells = <0>; 726 power-domains = <&CLUSTER_PD>; 727 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 728 }; 729 730 CPU_PD2: power-domain-cpu2 { 731 #power-domain-cells = <0>; 732 power-domains = <&CLUSTER_PD>; 733 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 734 }; 735 736 CPU_PD3: power-domain-cpu3 { 737 #power-domain-cells = <0>; 738 power-domains = <&CLUSTER_PD>; 739 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 740 }; 741 742 CPU_PD4: power-domain-cpu4 { 743 #power-domain-cells = <0>; 744 power-domains = <&CLUSTER_PD>; 745 domain-idle-states = <&BIG_CPU_SLEEP_0>; 746 }; 747 748 CPU_PD5: power-domain-cpu5 { 749 #power-domain-cells = <0>; 750 power-domains = <&CLUSTER_PD>; 751 domain-idle-states = <&BIG_CPU_SLEEP_0>; 752 }; 753 754 CPU_PD6: power-domain-cpu6 { 755 #power-domain-cells = <0>; 756 power-domains = <&CLUSTER_PD>; 757 domain-idle-states = <&BIG_CPU_SLEEP_0>; 758 }; 759 760 CPU_PD7: power-domain-cpu7 { 761 #power-domain-cells = <0>; 762 power-domains = <&CLUSTER_PD>; 763 domain-idle-states = <&BIG_CPU_SLEEP_0>; 764 }; 765 766 CLUSTER_PD: power-domain-cluster { 767 #power-domain-cells = <0>; 768 domain-idle-states = <&CLUSTER_SLEEP_0>; 769 }; 770 }; 771 772 reserved-memory { 773 #address-cells = <2>; 774 #size-cells = <2>; 775 ranges; 776 777 hyp_mem: hyp-mem@85700000 { 778 reg = <0 0x85700000 0 0x600000>; 779 no-map; 780 }; 781 782 xbl_mem: xbl-mem@85e00000 { 783 reg = <0 0x85e00000 0 0x100000>; 784 no-map; 785 }; 786 787 aop_mem: aop-mem@85fc0000 { 788 reg = <0 0x85fc0000 0 0x20000>; 789 no-map; 790 }; 791 792 aop_cmd_db_mem: aop-cmd-db-mem@85fe0000 { 793 compatible = "qcom,cmd-db"; 794 reg = <0x0 0x85fe0000 0 0x20000>; 795 no-map; 796 }; 797 798 smem@86000000 { 799 compatible = "qcom,smem"; 800 reg = <0x0 0x86000000 0 0x200000>; 801 no-map; 802 hwlocks = <&tcsr_mutex 3>; 803 }; 804 805 tz_mem: tz@86200000 { 806 reg = <0 0x86200000 0 0x2d00000>; 807 no-map; 808 }; 809 810 rmtfs_mem: rmtfs@88f00000 { 811 compatible = "qcom,rmtfs-mem"; 812 reg = <0 0x88f00000 0 0x200000>; 813 no-map; 814 815 qcom,client-id = <1>; 816 qcom,vmid = <15>; 817 }; 818 819 qseecom_mem: qseecom@8ab00000 { 820 reg = <0 0x8ab00000 0 0x1400000>; 821 no-map; 822 }; 823 824 camera_mem: camera-mem@8bf00000 { 825 reg = <0 0x8bf00000 0 0x500000>; 826 no-map; 827 }; 828 829 ipa_fw_mem: ipa-fw@8c400000 { 830 reg = <0 0x8c400000 0 0x10000>; 831 no-map; 832 }; 833 834 ipa_gsi_mem: ipa-gsi@8c410000 { 835 reg = <0 0x8c410000 0 0x5000>; 836 no-map; 837 }; 838 839 gpu_mem: gpu@8c415000 { 840 reg = <0 0x8c415000 0 0x2000>; 841 no-map; 842 }; 843 844 adsp_mem: adsp@8c500000 { 845 reg = <0 0x8c500000 0 0x1a00000>; 846 no-map; 847 }; 848 849 wlan_msa_mem: wlan-msa@8df00000 { 850 reg = <0 0x8df00000 0 0x100000>; 851 no-map; 852 }; 853 854 mpss_region: mpss@8e000000 { 855 reg = <0 0x8e000000 0 0x7800000>; 856 no-map; 857 }; 858 859 venus_mem: venus@95800000 { 860 reg = <0 0x95800000 0 0x500000>; 861 no-map; 862 }; 863 864 cdsp_mem: cdsp@95d00000 { 865 reg = <0 0x95d00000 0 0x800000>; 866 no-map; 867 }; 868 869 mba_region: mba@96500000 { 870 reg = <0 0x96500000 0 0x200000>; 871 no-map; 872 }; 873 874 slpi_mem: slpi@96700000 { 875 reg = <0 0x96700000 0 0x1400000>; 876 no-map; 877 }; 878 879 spss_mem: spss@97b00000 { 880 reg = <0 0x97b00000 0 0x100000>; 881 no-map; 882 }; 883 884 mdata_mem: mpss-metadata { 885 alloc-ranges = <0 0xa0000000 0 0x20000000>; 886 size = <0 0x4000>; 887 no-map; 888 }; 889 890 fastrpc_mem: fastrpc { 891 compatible = "shared-dma-pool"; 892 alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; 893 alignment = <0x0 0x400000>; 894 size = <0x0 0x1000000>; 895 reusable; 896 }; 897 }; 898 899 adsp_pas: remoteproc-adsp { 900 compatible = "qcom,sdm845-adsp-pas"; 901 902 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 903 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 904 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 905 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 906 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 907 interrupt-names = "wdog", "fatal", "ready", 908 "handover", "stop-ack"; 909 910 clocks = <&rpmhcc RPMH_CXO_CLK>; 911 clock-names = "xo"; 912 913 memory-region = <&adsp_mem>; 914 915 qcom,qmp = <&aoss_qmp>; 916 917 qcom,smem-states = <&adsp_smp2p_out 0>; 918 qcom,smem-state-names = "stop"; 919 920 status = "disabled"; 921 922 glink-edge { 923 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 924 label = "lpass"; 925 qcom,remote-pid = <2>; 926 mboxes = <&apss_shared 8>; 927 928 apr { 929 compatible = "qcom,apr-v2"; 930 qcom,glink-channels = "apr_audio_svc"; 931 qcom,domain = <APR_DOMAIN_ADSP>; 932 #address-cells = <1>; 933 #size-cells = <0>; 934 qcom,intents = <512 20>; 935 936 service@3 { 937 reg = <APR_SVC_ADSP_CORE>; 938 compatible = "qcom,q6core"; 939 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 940 }; 941 942 q6afe: service@4 { 943 compatible = "qcom,q6afe"; 944 reg = <APR_SVC_AFE>; 945 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 946 q6afedai: dais { 947 compatible = "qcom,q6afe-dais"; 948 #address-cells = <1>; 949 #size-cells = <0>; 950 #sound-dai-cells = <1>; 951 }; 952 }; 953 954 q6asm: service@7 { 955 compatible = "qcom,q6asm"; 956 reg = <APR_SVC_ASM>; 957 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 958 q6asmdai: dais { 959 compatible = "qcom,q6asm-dais"; 960 #address-cells = <1>; 961 #size-cells = <0>; 962 #sound-dai-cells = <1>; 963 iommus = <&apps_smmu 0x1821 0x0>; 964 }; 965 }; 966 967 q6adm: service@8 { 968 compatible = "qcom,q6adm"; 969 reg = <APR_SVC_ADM>; 970 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 971 q6routing: routing { 972 compatible = "qcom,q6adm-routing"; 973 #sound-dai-cells = <0>; 974 }; 975 }; 976 }; 977 978 fastrpc { 979 compatible = "qcom,fastrpc"; 980 qcom,glink-channels = "fastrpcglink-apps-dsp"; 981 label = "adsp"; 982 qcom,non-secure-domain; 983 #address-cells = <1>; 984 #size-cells = <0>; 985 986 compute-cb@3 { 987 compatible = "qcom,fastrpc-compute-cb"; 988 reg = <3>; 989 iommus = <&apps_smmu 0x1823 0x0>; 990 }; 991 992 compute-cb@4 { 993 compatible = "qcom,fastrpc-compute-cb"; 994 reg = <4>; 995 iommus = <&apps_smmu 0x1824 0x0>; 996 }; 997 }; 998 }; 999 }; 1000 1001 cdsp_pas: remoteproc-cdsp { 1002 compatible = "qcom,sdm845-cdsp-pas"; 1003 1004 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 1005 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1006 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1007 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1008 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 1009 interrupt-names = "wdog", "fatal", "ready", 1010 "handover", "stop-ack"; 1011 1012 clocks = <&rpmhcc RPMH_CXO_CLK>; 1013 clock-names = "xo"; 1014 1015 memory-region = <&cdsp_mem>; 1016 1017 qcom,qmp = <&aoss_qmp>; 1018 1019 qcom,smem-states = <&cdsp_smp2p_out 0>; 1020 qcom,smem-state-names = "stop"; 1021 1022 status = "disabled"; 1023 1024 glink-edge { 1025 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>; 1026 label = "turing"; 1027 qcom,remote-pid = <5>; 1028 mboxes = <&apss_shared 4>; 1029 fastrpc { 1030 compatible = "qcom,fastrpc"; 1031 qcom,glink-channels = "fastrpcglink-apps-dsp"; 1032 label = "cdsp"; 1033 qcom,non-secure-domain; 1034 #address-cells = <1>; 1035 #size-cells = <0>; 1036 1037 compute-cb@1 { 1038 compatible = "qcom,fastrpc-compute-cb"; 1039 reg = <1>; 1040 iommus = <&apps_smmu 0x1401 0x30>; 1041 }; 1042 1043 compute-cb@2 { 1044 compatible = "qcom,fastrpc-compute-cb"; 1045 reg = <2>; 1046 iommus = <&apps_smmu 0x1402 0x30>; 1047 }; 1048 1049 compute-cb@3 { 1050 compatible = "qcom,fastrpc-compute-cb"; 1051 reg = <3>; 1052 iommus = <&apps_smmu 0x1403 0x30>; 1053 }; 1054 1055 compute-cb@4 { 1056 compatible = "qcom,fastrpc-compute-cb"; 1057 reg = <4>; 1058 iommus = <&apps_smmu 0x1404 0x30>; 1059 }; 1060 1061 compute-cb@5 { 1062 compatible = "qcom,fastrpc-compute-cb"; 1063 reg = <5>; 1064 iommus = <&apps_smmu 0x1405 0x30>; 1065 }; 1066 1067 compute-cb@6 { 1068 compatible = "qcom,fastrpc-compute-cb"; 1069 reg = <6>; 1070 iommus = <&apps_smmu 0x1406 0x30>; 1071 }; 1072 1073 compute-cb@7 { 1074 compatible = "qcom,fastrpc-compute-cb"; 1075 reg = <7>; 1076 iommus = <&apps_smmu 0x1407 0x30>; 1077 }; 1078 1079 compute-cb@8 { 1080 compatible = "qcom,fastrpc-compute-cb"; 1081 reg = <8>; 1082 iommus = <&apps_smmu 0x1408 0x30>; 1083 }; 1084 }; 1085 }; 1086 }; 1087 1088 smp2p-cdsp { 1089 compatible = "qcom,smp2p"; 1090 qcom,smem = <94>, <432>; 1091 1092 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; 1093 1094 mboxes = <&apss_shared 6>; 1095 1096 qcom,local-pid = <0>; 1097 qcom,remote-pid = <5>; 1098 1099 cdsp_smp2p_out: master-kernel { 1100 qcom,entry-name = "master-kernel"; 1101 #qcom,smem-state-cells = <1>; 1102 }; 1103 1104 cdsp_smp2p_in: slave-kernel { 1105 qcom,entry-name = "slave-kernel"; 1106 1107 interrupt-controller; 1108 #interrupt-cells = <2>; 1109 }; 1110 }; 1111 1112 smp2p-lpass { 1113 compatible = "qcom,smp2p"; 1114 qcom,smem = <443>, <429>; 1115 1116 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 1117 1118 mboxes = <&apss_shared 10>; 1119 1120 qcom,local-pid = <0>; 1121 qcom,remote-pid = <2>; 1122 1123 adsp_smp2p_out: master-kernel { 1124 qcom,entry-name = "master-kernel"; 1125 #qcom,smem-state-cells = <1>; 1126 }; 1127 1128 adsp_smp2p_in: slave-kernel { 1129 qcom,entry-name = "slave-kernel"; 1130 1131 interrupt-controller; 1132 #interrupt-cells = <2>; 1133 }; 1134 }; 1135 1136 smp2p-mpss { 1137 compatible = "qcom,smp2p"; 1138 qcom,smem = <435>, <428>; 1139 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 1140 mboxes = <&apss_shared 14>; 1141 qcom,local-pid = <0>; 1142 qcom,remote-pid = <1>; 1143 1144 modem_smp2p_out: master-kernel { 1145 qcom,entry-name = "master-kernel"; 1146 #qcom,smem-state-cells = <1>; 1147 }; 1148 1149 modem_smp2p_in: slave-kernel { 1150 qcom,entry-name = "slave-kernel"; 1151 interrupt-controller; 1152 #interrupt-cells = <2>; 1153 }; 1154 1155 ipa_smp2p_out: ipa-ap-to-modem { 1156 qcom,entry-name = "ipa"; 1157 #qcom,smem-state-cells = <1>; 1158 }; 1159 1160 ipa_smp2p_in: ipa-modem-to-ap { 1161 qcom,entry-name = "ipa"; 1162 interrupt-controller; 1163 #interrupt-cells = <2>; 1164 }; 1165 }; 1166 1167 smp2p-slpi { 1168 compatible = "qcom,smp2p"; 1169 qcom,smem = <481>, <430>; 1170 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>; 1171 mboxes = <&apss_shared 26>; 1172 qcom,local-pid = <0>; 1173 qcom,remote-pid = <3>; 1174 1175 slpi_smp2p_out: master-kernel { 1176 qcom,entry-name = "master-kernel"; 1177 #qcom,smem-state-cells = <1>; 1178 }; 1179 1180 slpi_smp2p_in: slave-kernel { 1181 qcom,entry-name = "slave-kernel"; 1182 interrupt-controller; 1183 #interrupt-cells = <2>; 1184 }; 1185 }; 1186 1187 soc: soc@0 { 1188 #address-cells = <2>; 1189 #size-cells = <2>; 1190 ranges = <0 0 0 0 0x10 0>; 1191 dma-ranges = <0 0 0 0 0x10 0>; 1192 compatible = "simple-bus"; 1193 1194 gcc: clock-controller@100000 { 1195 compatible = "qcom,gcc-sdm845"; 1196 reg = <0 0x00100000 0 0x1f0000>; 1197 clocks = <&rpmhcc RPMH_CXO_CLK>, 1198 <&rpmhcc RPMH_CXO_CLK_A>, 1199 <&sleep_clk>, 1200 <&pcie0_lane>, 1201 <&pcie1_lane>; 1202 clock-names = "bi_tcxo", 1203 "bi_tcxo_ao", 1204 "sleep_clk", 1205 "pcie_0_pipe_clk", 1206 "pcie_1_pipe_clk"; 1207 #clock-cells = <1>; 1208 #reset-cells = <1>; 1209 #power-domain-cells = <1>; 1210 power-domains = <&rpmhpd SDM845_CX>; 1211 }; 1212 1213 qfprom@784000 { 1214 compatible = "qcom,sdm845-qfprom", "qcom,qfprom"; 1215 reg = <0 0x00784000 0 0x8ff>; 1216 #address-cells = <1>; 1217 #size-cells = <1>; 1218 1219 qusb2p_hstx_trim: hstx-trim-primary@1eb { 1220 reg = <0x1eb 0x1>; 1221 bits = <1 4>; 1222 }; 1223 1224 qusb2s_hstx_trim: hstx-trim-secondary@1eb { 1225 reg = <0x1eb 0x2>; 1226 bits = <6 4>; 1227 }; 1228 }; 1229 1230 rng: rng@793000 { 1231 compatible = "qcom,prng-ee"; 1232 reg = <0 0x00793000 0 0x1000>; 1233 clocks = <&gcc GCC_PRNG_AHB_CLK>; 1234 clock-names = "core"; 1235 }; 1236 1237 gpi_dma0: dma-controller@800000 { 1238 #dma-cells = <3>; 1239 compatible = "qcom,sdm845-gpi-dma"; 1240 reg = <0 0x00800000 0 0x60000>; 1241 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 1242 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 1243 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 1244 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 1245 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 1246 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 1247 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 1248 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 1249 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 1250 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 1251 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 1252 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 1253 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 1254 dma-channels = <13>; 1255 dma-channel-mask = <0xfa>; 1256 iommus = <&apps_smmu 0x0016 0x0>; 1257 status = "disabled"; 1258 }; 1259 1260 qupv3_id_0: geniqup@8c0000 { 1261 compatible = "qcom,geni-se-qup"; 1262 reg = <0 0x008c0000 0 0x6000>; 1263 clock-names = "m-ahb", "s-ahb"; 1264 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1265 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1266 iommus = <&apps_smmu 0x3 0x0>; 1267 #address-cells = <2>; 1268 #size-cells = <2>; 1269 ranges; 1270 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>; 1271 interconnect-names = "qup-core"; 1272 status = "disabled"; 1273 1274 i2c0: i2c@880000 { 1275 compatible = "qcom,geni-i2c"; 1276 reg = <0 0x00880000 0 0x4000>; 1277 clock-names = "se"; 1278 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1279 pinctrl-names = "default"; 1280 pinctrl-0 = <&qup_i2c0_default>; 1281 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1282 #address-cells = <1>; 1283 #size-cells = <0>; 1284 power-domains = <&rpmhpd SDM845_CX>; 1285 operating-points-v2 = <&qup_opp_table>; 1286 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1287 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, 1288 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; 1289 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1290 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1291 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1292 dma-names = "tx", "rx"; 1293 status = "disabled"; 1294 }; 1295 1296 spi0: spi@880000 { 1297 compatible = "qcom,geni-spi"; 1298 reg = <0 0x00880000 0 0x4000>; 1299 clock-names = "se"; 1300 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1301 pinctrl-names = "default"; 1302 pinctrl-0 = <&qup_spi0_default>; 1303 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1304 #address-cells = <1>; 1305 #size-cells = <0>; 1306 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1307 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1308 interconnect-names = "qup-core", "qup-config"; 1309 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1310 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1311 dma-names = "tx", "rx"; 1312 status = "disabled"; 1313 }; 1314 1315 uart0: serial@880000 { 1316 compatible = "qcom,geni-uart"; 1317 reg = <0 0x00880000 0 0x4000>; 1318 clock-names = "se"; 1319 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1320 pinctrl-names = "default"; 1321 pinctrl-0 = <&qup_uart0_default>; 1322 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1323 power-domains = <&rpmhpd SDM845_CX>; 1324 operating-points-v2 = <&qup_opp_table>; 1325 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1326 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1327 interconnect-names = "qup-core", "qup-config"; 1328 status = "disabled"; 1329 }; 1330 1331 i2c1: i2c@884000 { 1332 compatible = "qcom,geni-i2c"; 1333 reg = <0 0x00884000 0 0x4000>; 1334 clock-names = "se"; 1335 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1336 pinctrl-names = "default"; 1337 pinctrl-0 = <&qup_i2c1_default>; 1338 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1339 #address-cells = <1>; 1340 #size-cells = <0>; 1341 power-domains = <&rpmhpd SDM845_CX>; 1342 operating-points-v2 = <&qup_opp_table>; 1343 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1344 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, 1345 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; 1346 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1347 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1348 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1349 dma-names = "tx", "rx"; 1350 status = "disabled"; 1351 }; 1352 1353 spi1: spi@884000 { 1354 compatible = "qcom,geni-spi"; 1355 reg = <0 0x00884000 0 0x4000>; 1356 clock-names = "se"; 1357 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1358 pinctrl-names = "default"; 1359 pinctrl-0 = <&qup_spi1_default>; 1360 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1361 #address-cells = <1>; 1362 #size-cells = <0>; 1363 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1364 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1365 interconnect-names = "qup-core", "qup-config"; 1366 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1367 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1368 dma-names = "tx", "rx"; 1369 status = "disabled"; 1370 }; 1371 1372 uart1: serial@884000 { 1373 compatible = "qcom,geni-uart"; 1374 reg = <0 0x00884000 0 0x4000>; 1375 clock-names = "se"; 1376 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1377 pinctrl-names = "default"; 1378 pinctrl-0 = <&qup_uart1_default>; 1379 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1380 power-domains = <&rpmhpd SDM845_CX>; 1381 operating-points-v2 = <&qup_opp_table>; 1382 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1383 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1384 interconnect-names = "qup-core", "qup-config"; 1385 status = "disabled"; 1386 }; 1387 1388 i2c2: i2c@888000 { 1389 compatible = "qcom,geni-i2c"; 1390 reg = <0 0x00888000 0 0x4000>; 1391 clock-names = "se"; 1392 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1393 pinctrl-names = "default"; 1394 pinctrl-0 = <&qup_i2c2_default>; 1395 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1396 #address-cells = <1>; 1397 #size-cells = <0>; 1398 power-domains = <&rpmhpd SDM845_CX>; 1399 operating-points-v2 = <&qup_opp_table>; 1400 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1401 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, 1402 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; 1403 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1404 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1405 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1406 dma-names = "tx", "rx"; 1407 status = "disabled"; 1408 }; 1409 1410 spi2: spi@888000 { 1411 compatible = "qcom,geni-spi"; 1412 reg = <0 0x00888000 0 0x4000>; 1413 clock-names = "se"; 1414 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1415 pinctrl-names = "default"; 1416 pinctrl-0 = <&qup_spi2_default>; 1417 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1418 #address-cells = <1>; 1419 #size-cells = <0>; 1420 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1421 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1422 interconnect-names = "qup-core", "qup-config"; 1423 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1424 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1425 dma-names = "tx", "rx"; 1426 status = "disabled"; 1427 }; 1428 1429 uart2: serial@888000 { 1430 compatible = "qcom,geni-uart"; 1431 reg = <0 0x00888000 0 0x4000>; 1432 clock-names = "se"; 1433 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1434 pinctrl-names = "default"; 1435 pinctrl-0 = <&qup_uart2_default>; 1436 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1437 power-domains = <&rpmhpd SDM845_CX>; 1438 operating-points-v2 = <&qup_opp_table>; 1439 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1440 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1441 interconnect-names = "qup-core", "qup-config"; 1442 status = "disabled"; 1443 }; 1444 1445 i2c3: i2c@88c000 { 1446 compatible = "qcom,geni-i2c"; 1447 reg = <0 0x0088c000 0 0x4000>; 1448 clock-names = "se"; 1449 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1450 pinctrl-names = "default"; 1451 pinctrl-0 = <&qup_i2c3_default>; 1452 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1453 #address-cells = <1>; 1454 #size-cells = <0>; 1455 power-domains = <&rpmhpd SDM845_CX>; 1456 operating-points-v2 = <&qup_opp_table>; 1457 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1458 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, 1459 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; 1460 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1461 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1462 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1463 dma-names = "tx", "rx"; 1464 status = "disabled"; 1465 }; 1466 1467 spi3: spi@88c000 { 1468 compatible = "qcom,geni-spi"; 1469 reg = <0 0x0088c000 0 0x4000>; 1470 clock-names = "se"; 1471 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1472 pinctrl-names = "default"; 1473 pinctrl-0 = <&qup_spi3_default>; 1474 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1475 #address-cells = <1>; 1476 #size-cells = <0>; 1477 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1478 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1479 interconnect-names = "qup-core", "qup-config"; 1480 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1481 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1482 dma-names = "tx", "rx"; 1483 status = "disabled"; 1484 }; 1485 1486 uart3: serial@88c000 { 1487 compatible = "qcom,geni-uart"; 1488 reg = <0 0x0088c000 0 0x4000>; 1489 clock-names = "se"; 1490 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1491 pinctrl-names = "default"; 1492 pinctrl-0 = <&qup_uart3_default>; 1493 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1494 power-domains = <&rpmhpd SDM845_CX>; 1495 operating-points-v2 = <&qup_opp_table>; 1496 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1497 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1498 interconnect-names = "qup-core", "qup-config"; 1499 status = "disabled"; 1500 }; 1501 1502 i2c4: i2c@890000 { 1503 compatible = "qcom,geni-i2c"; 1504 reg = <0 0x00890000 0 0x4000>; 1505 clock-names = "se"; 1506 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1507 pinctrl-names = "default"; 1508 pinctrl-0 = <&qup_i2c4_default>; 1509 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1510 #address-cells = <1>; 1511 #size-cells = <0>; 1512 power-domains = <&rpmhpd SDM845_CX>; 1513 operating-points-v2 = <&qup_opp_table>; 1514 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1515 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, 1516 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; 1517 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1518 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1519 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1520 dma-names = "tx", "rx"; 1521 status = "disabled"; 1522 }; 1523 1524 spi4: spi@890000 { 1525 compatible = "qcom,geni-spi"; 1526 reg = <0 0x00890000 0 0x4000>; 1527 clock-names = "se"; 1528 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1529 pinctrl-names = "default"; 1530 pinctrl-0 = <&qup_spi4_default>; 1531 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1532 #address-cells = <1>; 1533 #size-cells = <0>; 1534 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1535 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1536 interconnect-names = "qup-core", "qup-config"; 1537 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1538 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1539 dma-names = "tx", "rx"; 1540 status = "disabled"; 1541 }; 1542 1543 uart4: serial@890000 { 1544 compatible = "qcom,geni-uart"; 1545 reg = <0 0x00890000 0 0x4000>; 1546 clock-names = "se"; 1547 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1548 pinctrl-names = "default"; 1549 pinctrl-0 = <&qup_uart4_default>; 1550 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1551 power-domains = <&rpmhpd SDM845_CX>; 1552 operating-points-v2 = <&qup_opp_table>; 1553 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1554 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1555 interconnect-names = "qup-core", "qup-config"; 1556 status = "disabled"; 1557 }; 1558 1559 i2c5: i2c@894000 { 1560 compatible = "qcom,geni-i2c"; 1561 reg = <0 0x00894000 0 0x4000>; 1562 clock-names = "se"; 1563 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1564 pinctrl-names = "default"; 1565 pinctrl-0 = <&qup_i2c5_default>; 1566 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1567 #address-cells = <1>; 1568 #size-cells = <0>; 1569 power-domains = <&rpmhpd SDM845_CX>; 1570 operating-points-v2 = <&qup_opp_table>; 1571 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1572 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, 1573 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; 1574 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1575 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1576 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1577 dma-names = "tx", "rx"; 1578 status = "disabled"; 1579 }; 1580 1581 spi5: spi@894000 { 1582 compatible = "qcom,geni-spi"; 1583 reg = <0 0x00894000 0 0x4000>; 1584 clock-names = "se"; 1585 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1586 pinctrl-names = "default"; 1587 pinctrl-0 = <&qup_spi5_default>; 1588 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1589 #address-cells = <1>; 1590 #size-cells = <0>; 1591 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1592 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1593 interconnect-names = "qup-core", "qup-config"; 1594 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1595 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1596 dma-names = "tx", "rx"; 1597 status = "disabled"; 1598 }; 1599 1600 uart5: serial@894000 { 1601 compatible = "qcom,geni-uart"; 1602 reg = <0 0x00894000 0 0x4000>; 1603 clock-names = "se"; 1604 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1605 pinctrl-names = "default"; 1606 pinctrl-0 = <&qup_uart5_default>; 1607 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1608 power-domains = <&rpmhpd SDM845_CX>; 1609 operating-points-v2 = <&qup_opp_table>; 1610 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1611 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1612 interconnect-names = "qup-core", "qup-config"; 1613 status = "disabled"; 1614 }; 1615 1616 i2c6: i2c@898000 { 1617 compatible = "qcom,geni-i2c"; 1618 reg = <0 0x00898000 0 0x4000>; 1619 clock-names = "se"; 1620 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1621 pinctrl-names = "default"; 1622 pinctrl-0 = <&qup_i2c6_default>; 1623 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1624 #address-cells = <1>; 1625 #size-cells = <0>; 1626 power-domains = <&rpmhpd SDM845_CX>; 1627 operating-points-v2 = <&qup_opp_table>; 1628 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1629 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, 1630 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; 1631 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1632 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1633 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1634 dma-names = "tx", "rx"; 1635 status = "disabled"; 1636 }; 1637 1638 spi6: spi@898000 { 1639 compatible = "qcom,geni-spi"; 1640 reg = <0 0x00898000 0 0x4000>; 1641 clock-names = "se"; 1642 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1643 pinctrl-names = "default"; 1644 pinctrl-0 = <&qup_spi6_default>; 1645 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1646 #address-cells = <1>; 1647 #size-cells = <0>; 1648 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1649 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1650 interconnect-names = "qup-core", "qup-config"; 1651 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1652 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1653 dma-names = "tx", "rx"; 1654 status = "disabled"; 1655 }; 1656 1657 uart6: serial@898000 { 1658 compatible = "qcom,geni-uart"; 1659 reg = <0 0x00898000 0 0x4000>; 1660 clock-names = "se"; 1661 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1662 pinctrl-names = "default"; 1663 pinctrl-0 = <&qup_uart6_default>; 1664 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1665 power-domains = <&rpmhpd SDM845_CX>; 1666 operating-points-v2 = <&qup_opp_table>; 1667 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1668 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1669 interconnect-names = "qup-core", "qup-config"; 1670 status = "disabled"; 1671 }; 1672 1673 i2c7: i2c@89c000 { 1674 compatible = "qcom,geni-i2c"; 1675 reg = <0 0x0089c000 0 0x4000>; 1676 clock-names = "se"; 1677 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1678 pinctrl-names = "default"; 1679 pinctrl-0 = <&qup_i2c7_default>; 1680 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1681 #address-cells = <1>; 1682 #size-cells = <0>; 1683 power-domains = <&rpmhpd SDM845_CX>; 1684 operating-points-v2 = <&qup_opp_table>; 1685 status = "disabled"; 1686 }; 1687 1688 spi7: spi@89c000 { 1689 compatible = "qcom,geni-spi"; 1690 reg = <0 0x0089c000 0 0x4000>; 1691 clock-names = "se"; 1692 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1693 pinctrl-names = "default"; 1694 pinctrl-0 = <&qup_spi7_default>; 1695 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1696 #address-cells = <1>; 1697 #size-cells = <0>; 1698 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1699 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1700 interconnect-names = "qup-core", "qup-config"; 1701 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1702 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1703 dma-names = "tx", "rx"; 1704 status = "disabled"; 1705 }; 1706 1707 uart7: serial@89c000 { 1708 compatible = "qcom,geni-uart"; 1709 reg = <0 0x0089c000 0 0x4000>; 1710 clock-names = "se"; 1711 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1712 pinctrl-names = "default"; 1713 pinctrl-0 = <&qup_uart7_default>; 1714 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1715 power-domains = <&rpmhpd SDM845_CX>; 1716 operating-points-v2 = <&qup_opp_table>; 1717 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1718 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1719 interconnect-names = "qup-core", "qup-config"; 1720 status = "disabled"; 1721 }; 1722 }; 1723 1724 gpi_dma1: dma-controller@a00000 { 1725 #dma-cells = <3>; 1726 compatible = "qcom,sdm845-gpi-dma"; 1727 reg = <0 0x00a00000 0 0x60000>; 1728 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1729 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1730 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1731 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1732 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1733 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1734 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1735 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1736 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1737 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1738 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1739 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 1740 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 1741 dma-channels = <13>; 1742 dma-channel-mask = <0xfa>; 1743 iommus = <&apps_smmu 0x06d6 0x0>; 1744 status = "disabled"; 1745 }; 1746 1747 qupv3_id_1: geniqup@ac0000 { 1748 compatible = "qcom,geni-se-qup"; 1749 reg = <0 0x00ac0000 0 0x6000>; 1750 clock-names = "m-ahb", "s-ahb"; 1751 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1752 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1753 iommus = <&apps_smmu 0x6c3 0x0>; 1754 #address-cells = <2>; 1755 #size-cells = <2>; 1756 ranges; 1757 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>; 1758 interconnect-names = "qup-core"; 1759 status = "disabled"; 1760 1761 i2c8: i2c@a80000 { 1762 compatible = "qcom,geni-i2c"; 1763 reg = <0 0x00a80000 0 0x4000>; 1764 clock-names = "se"; 1765 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1766 pinctrl-names = "default"; 1767 pinctrl-0 = <&qup_i2c8_default>; 1768 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1769 #address-cells = <1>; 1770 #size-cells = <0>; 1771 power-domains = <&rpmhpd SDM845_CX>; 1772 operating-points-v2 = <&qup_opp_table>; 1773 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1774 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 1775 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 1776 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1777 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1778 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1779 dma-names = "tx", "rx"; 1780 status = "disabled"; 1781 }; 1782 1783 spi8: spi@a80000 { 1784 compatible = "qcom,geni-spi"; 1785 reg = <0 0x00a80000 0 0x4000>; 1786 clock-names = "se"; 1787 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1788 pinctrl-names = "default"; 1789 pinctrl-0 = <&qup_spi8_default>; 1790 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1791 #address-cells = <1>; 1792 #size-cells = <0>; 1793 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1794 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1795 interconnect-names = "qup-core", "qup-config"; 1796 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1797 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1798 dma-names = "tx", "rx"; 1799 status = "disabled"; 1800 }; 1801 1802 uart8: serial@a80000 { 1803 compatible = "qcom,geni-uart"; 1804 reg = <0 0x00a80000 0 0x4000>; 1805 clock-names = "se"; 1806 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1807 pinctrl-names = "default"; 1808 pinctrl-0 = <&qup_uart8_default>; 1809 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1810 power-domains = <&rpmhpd SDM845_CX>; 1811 operating-points-v2 = <&qup_opp_table>; 1812 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1813 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1814 interconnect-names = "qup-core", "qup-config"; 1815 status = "disabled"; 1816 }; 1817 1818 i2c9: i2c@a84000 { 1819 compatible = "qcom,geni-i2c"; 1820 reg = <0 0x00a84000 0 0x4000>; 1821 clock-names = "se"; 1822 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1823 pinctrl-names = "default"; 1824 pinctrl-0 = <&qup_i2c9_default>; 1825 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1826 #address-cells = <1>; 1827 #size-cells = <0>; 1828 power-domains = <&rpmhpd SDM845_CX>; 1829 operating-points-v2 = <&qup_opp_table>; 1830 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1831 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 1832 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 1833 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1834 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1835 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1836 dma-names = "tx", "rx"; 1837 status = "disabled"; 1838 }; 1839 1840 spi9: spi@a84000 { 1841 compatible = "qcom,geni-spi"; 1842 reg = <0 0x00a84000 0 0x4000>; 1843 clock-names = "se"; 1844 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1845 pinctrl-names = "default"; 1846 pinctrl-0 = <&qup_spi9_default>; 1847 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1848 #address-cells = <1>; 1849 #size-cells = <0>; 1850 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1851 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1852 interconnect-names = "qup-core", "qup-config"; 1853 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1854 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1855 dma-names = "tx", "rx"; 1856 status = "disabled"; 1857 }; 1858 1859 uart9: serial@a84000 { 1860 compatible = "qcom,geni-debug-uart"; 1861 reg = <0 0x00a84000 0 0x4000>; 1862 clock-names = "se"; 1863 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1864 pinctrl-names = "default"; 1865 pinctrl-0 = <&qup_uart9_default>; 1866 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1867 power-domains = <&rpmhpd SDM845_CX>; 1868 operating-points-v2 = <&qup_opp_table>; 1869 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1870 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1871 interconnect-names = "qup-core", "qup-config"; 1872 status = "disabled"; 1873 }; 1874 1875 i2c10: i2c@a88000 { 1876 compatible = "qcom,geni-i2c"; 1877 reg = <0 0x00a88000 0 0x4000>; 1878 clock-names = "se"; 1879 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1880 pinctrl-names = "default"; 1881 pinctrl-0 = <&qup_i2c10_default>; 1882 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1883 #address-cells = <1>; 1884 #size-cells = <0>; 1885 power-domains = <&rpmhpd SDM845_CX>; 1886 operating-points-v2 = <&qup_opp_table>; 1887 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1888 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 1889 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 1890 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1891 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1892 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1893 dma-names = "tx", "rx"; 1894 status = "disabled"; 1895 }; 1896 1897 spi10: spi@a88000 { 1898 compatible = "qcom,geni-spi"; 1899 reg = <0 0x00a88000 0 0x4000>; 1900 clock-names = "se"; 1901 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1902 pinctrl-names = "default"; 1903 pinctrl-0 = <&qup_spi10_default>; 1904 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1905 #address-cells = <1>; 1906 #size-cells = <0>; 1907 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1908 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1909 interconnect-names = "qup-core", "qup-config"; 1910 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1911 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1912 dma-names = "tx", "rx"; 1913 status = "disabled"; 1914 }; 1915 1916 uart10: serial@a88000 { 1917 compatible = "qcom,geni-uart"; 1918 reg = <0 0x00a88000 0 0x4000>; 1919 clock-names = "se"; 1920 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1921 pinctrl-names = "default"; 1922 pinctrl-0 = <&qup_uart10_default>; 1923 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1924 power-domains = <&rpmhpd SDM845_CX>; 1925 operating-points-v2 = <&qup_opp_table>; 1926 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1927 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1928 interconnect-names = "qup-core", "qup-config"; 1929 status = "disabled"; 1930 }; 1931 1932 i2c11: i2c@a8c000 { 1933 compatible = "qcom,geni-i2c"; 1934 reg = <0 0x00a8c000 0 0x4000>; 1935 clock-names = "se"; 1936 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1937 pinctrl-names = "default"; 1938 pinctrl-0 = <&qup_i2c11_default>; 1939 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1940 #address-cells = <1>; 1941 #size-cells = <0>; 1942 power-domains = <&rpmhpd SDM845_CX>; 1943 operating-points-v2 = <&qup_opp_table>; 1944 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1945 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 1946 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 1947 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1948 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1949 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1950 dma-names = "tx", "rx"; 1951 status = "disabled"; 1952 }; 1953 1954 spi11: spi@a8c000 { 1955 compatible = "qcom,geni-spi"; 1956 reg = <0 0x00a8c000 0 0x4000>; 1957 clock-names = "se"; 1958 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1959 pinctrl-names = "default"; 1960 pinctrl-0 = <&qup_spi11_default>; 1961 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1962 #address-cells = <1>; 1963 #size-cells = <0>; 1964 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1965 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1966 interconnect-names = "qup-core", "qup-config"; 1967 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1968 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1969 dma-names = "tx", "rx"; 1970 status = "disabled"; 1971 }; 1972 1973 uart11: serial@a8c000 { 1974 compatible = "qcom,geni-uart"; 1975 reg = <0 0x00a8c000 0 0x4000>; 1976 clock-names = "se"; 1977 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1978 pinctrl-names = "default"; 1979 pinctrl-0 = <&qup_uart11_default>; 1980 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1981 power-domains = <&rpmhpd SDM845_CX>; 1982 operating-points-v2 = <&qup_opp_table>; 1983 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1984 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1985 interconnect-names = "qup-core", "qup-config"; 1986 status = "disabled"; 1987 }; 1988 1989 i2c12: i2c@a90000 { 1990 compatible = "qcom,geni-i2c"; 1991 reg = <0 0x00a90000 0 0x4000>; 1992 clock-names = "se"; 1993 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1994 pinctrl-names = "default"; 1995 pinctrl-0 = <&qup_i2c12_default>; 1996 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1997 #address-cells = <1>; 1998 #size-cells = <0>; 1999 power-domains = <&rpmhpd SDM845_CX>; 2000 operating-points-v2 = <&qup_opp_table>; 2001 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2002 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 2003 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 2004 interconnect-names = "qup-core", "qup-config", "qup-memory"; 2005 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 2006 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 2007 dma-names = "tx", "rx"; 2008 status = "disabled"; 2009 }; 2010 2011 spi12: spi@a90000 { 2012 compatible = "qcom,geni-spi"; 2013 reg = <0 0x00a90000 0 0x4000>; 2014 clock-names = "se"; 2015 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 2016 pinctrl-names = "default"; 2017 pinctrl-0 = <&qup_spi12_default>; 2018 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 2019 #address-cells = <1>; 2020 #size-cells = <0>; 2021 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2022 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 2023 interconnect-names = "qup-core", "qup-config"; 2024 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 2025 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 2026 dma-names = "tx", "rx"; 2027 status = "disabled"; 2028 }; 2029 2030 uart12: serial@a90000 { 2031 compatible = "qcom,geni-uart"; 2032 reg = <0 0x00a90000 0 0x4000>; 2033 clock-names = "se"; 2034 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 2035 pinctrl-names = "default"; 2036 pinctrl-0 = <&qup_uart12_default>; 2037 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 2038 power-domains = <&rpmhpd SDM845_CX>; 2039 operating-points-v2 = <&qup_opp_table>; 2040 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2041 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 2042 interconnect-names = "qup-core", "qup-config"; 2043 status = "disabled"; 2044 }; 2045 2046 i2c13: i2c@a94000 { 2047 compatible = "qcom,geni-i2c"; 2048 reg = <0 0x00a94000 0 0x4000>; 2049 clock-names = "se"; 2050 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 2051 pinctrl-names = "default"; 2052 pinctrl-0 = <&qup_i2c13_default>; 2053 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 2054 #address-cells = <1>; 2055 #size-cells = <0>; 2056 power-domains = <&rpmhpd SDM845_CX>; 2057 operating-points-v2 = <&qup_opp_table>; 2058 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2059 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 2060 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 2061 interconnect-names = "qup-core", "qup-config", "qup-memory"; 2062 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 2063 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 2064 dma-names = "tx", "rx"; 2065 status = "disabled"; 2066 }; 2067 2068 spi13: spi@a94000 { 2069 compatible = "qcom,geni-spi"; 2070 reg = <0 0x00a94000 0 0x4000>; 2071 clock-names = "se"; 2072 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 2073 pinctrl-names = "default"; 2074 pinctrl-0 = <&qup_spi13_default>; 2075 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 2076 #address-cells = <1>; 2077 #size-cells = <0>; 2078 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2079 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 2080 interconnect-names = "qup-core", "qup-config"; 2081 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 2082 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 2083 dma-names = "tx", "rx"; 2084 status = "disabled"; 2085 }; 2086 2087 uart13: serial@a94000 { 2088 compatible = "qcom,geni-uart"; 2089 reg = <0 0x00a94000 0 0x4000>; 2090 clock-names = "se"; 2091 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 2092 pinctrl-names = "default"; 2093 pinctrl-0 = <&qup_uart13_default>; 2094 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 2095 power-domains = <&rpmhpd SDM845_CX>; 2096 operating-points-v2 = <&qup_opp_table>; 2097 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2098 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 2099 interconnect-names = "qup-core", "qup-config"; 2100 status = "disabled"; 2101 }; 2102 2103 i2c14: i2c@a98000 { 2104 compatible = "qcom,geni-i2c"; 2105 reg = <0 0x00a98000 0 0x4000>; 2106 clock-names = "se"; 2107 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2108 pinctrl-names = "default"; 2109 pinctrl-0 = <&qup_i2c14_default>; 2110 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 2111 #address-cells = <1>; 2112 #size-cells = <0>; 2113 power-domains = <&rpmhpd SDM845_CX>; 2114 operating-points-v2 = <&qup_opp_table>; 2115 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2116 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 2117 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 2118 interconnect-names = "qup-core", "qup-config", "qup-memory"; 2119 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 2120 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 2121 dma-names = "tx", "rx"; 2122 status = "disabled"; 2123 }; 2124 2125 spi14: spi@a98000 { 2126 compatible = "qcom,geni-spi"; 2127 reg = <0 0x00a98000 0 0x4000>; 2128 clock-names = "se"; 2129 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2130 pinctrl-names = "default"; 2131 pinctrl-0 = <&qup_spi14_default>; 2132 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 2133 #address-cells = <1>; 2134 #size-cells = <0>; 2135 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2136 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 2137 interconnect-names = "qup-core", "qup-config"; 2138 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 2139 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 2140 dma-names = "tx", "rx"; 2141 status = "disabled"; 2142 }; 2143 2144 uart14: serial@a98000 { 2145 compatible = "qcom,geni-uart"; 2146 reg = <0 0x00a98000 0 0x4000>; 2147 clock-names = "se"; 2148 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2149 pinctrl-names = "default"; 2150 pinctrl-0 = <&qup_uart14_default>; 2151 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 2152 power-domains = <&rpmhpd SDM845_CX>; 2153 operating-points-v2 = <&qup_opp_table>; 2154 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2155 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 2156 interconnect-names = "qup-core", "qup-config"; 2157 status = "disabled"; 2158 }; 2159 2160 i2c15: i2c@a9c000 { 2161 compatible = "qcom,geni-i2c"; 2162 reg = <0 0x00a9c000 0 0x4000>; 2163 clock-names = "se"; 2164 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2165 pinctrl-names = "default"; 2166 pinctrl-0 = <&qup_i2c15_default>; 2167 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 2168 #address-cells = <1>; 2169 #size-cells = <0>; 2170 power-domains = <&rpmhpd SDM845_CX>; 2171 operating-points-v2 = <&qup_opp_table>; 2172 status = "disabled"; 2173 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2174 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 2175 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 2176 interconnect-names = "qup-core", "qup-config", "qup-memory"; 2177 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, 2178 <&gpi_dma1 1 7 QCOM_GPI_I2C>; 2179 dma-names = "tx", "rx"; 2180 }; 2181 2182 spi15: spi@a9c000 { 2183 compatible = "qcom,geni-spi"; 2184 reg = <0 0x00a9c000 0 0x4000>; 2185 clock-names = "se"; 2186 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2187 pinctrl-names = "default"; 2188 pinctrl-0 = <&qup_spi15_default>; 2189 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 2190 #address-cells = <1>; 2191 #size-cells = <0>; 2192 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2193 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 2194 interconnect-names = "qup-core", "qup-config"; 2195 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, 2196 <&gpi_dma1 1 7 QCOM_GPI_SPI>; 2197 dma-names = "tx", "rx"; 2198 status = "disabled"; 2199 }; 2200 2201 uart15: serial@a9c000 { 2202 compatible = "qcom,geni-uart"; 2203 reg = <0 0x00a9c000 0 0x4000>; 2204 clock-names = "se"; 2205 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2206 pinctrl-names = "default"; 2207 pinctrl-0 = <&qup_uart15_default>; 2208 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 2209 power-domains = <&rpmhpd SDM845_CX>; 2210 operating-points-v2 = <&qup_opp_table>; 2211 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2212 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 2213 interconnect-names = "qup-core", "qup-config"; 2214 status = "disabled"; 2215 }; 2216 }; 2217 2218 llcc: system-cache-controller@1100000 { 2219 compatible = "qcom,sdm845-llcc"; 2220 reg = <0 0x01100000 0 0x45000>, <0 0x01180000 0 0x50000>, 2221 <0 0x01200000 0 0x50000>, <0 0x01280000 0 0x50000>, 2222 <0 0x01300000 0 0x50000>; 2223 reg-names = "llcc0_base", "llcc1_base", "llcc2_base", 2224 "llcc3_base", "llcc_broadcast_base"; 2225 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 2226 }; 2227 2228 dma@10a2000 { 2229 compatible = "qcom,sdm845-dcc", "qcom,dcc"; 2230 reg = <0x0 0x010a2000 0x0 0x1000>, 2231 <0x0 0x010ae000 0x0 0x2000>; 2232 }; 2233 2234 pmu@114a000 { 2235 compatible = "qcom,sdm845-llcc-bwmon"; 2236 reg = <0 0x0114a000 0 0x1000>; 2237 interrupts = <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>; 2238 interconnects = <&mem_noc MASTER_LLCC 3 &mem_noc SLAVE_EBI1 3>; 2239 2240 operating-points-v2 = <&llcc_bwmon_opp_table>; 2241 2242 llcc_bwmon_opp_table: opp-table { 2243 compatible = "operating-points-v2"; 2244 2245 /* 2246 * The interconnect path bandwidth taken from 2247 * cpu4_opp_table bandwidth for gladiator_noc-mem_noc 2248 * interconnect. This also matches the 2249 * bandwidth table of qcom,llccbw (qcom,bw-tbl, 2250 * bus width: 4 bytes) from msm-4.9 downstream 2251 * kernel. 2252 */ 2253 opp-0 { 2254 opp-peak-kBps = <800000>; 2255 }; 2256 opp-1 { 2257 opp-peak-kBps = <1804000>; 2258 }; 2259 opp-2 { 2260 opp-peak-kBps = <3072000>; 2261 }; 2262 opp-3 { 2263 opp-peak-kBps = <5412000>; 2264 }; 2265 opp-4 { 2266 opp-peak-kBps = <7216000>; 2267 }; 2268 }; 2269 }; 2270 2271 pmu@1436400 { 2272 compatible = "qcom,sdm845-cpu-bwmon", "qcom,sdm845-bwmon"; 2273 reg = <0 0x01436400 0 0x600>; 2274 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 2275 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_LLCC 3>; 2276 2277 operating-points-v2 = <&cpu_bwmon_opp_table>; 2278 2279 cpu_bwmon_opp_table: opp-table { 2280 compatible = "operating-points-v2"; 2281 2282 /* 2283 * The interconnect path bandwidth taken from 2284 * cpu4_opp_table bandwidth for OSM L3 2285 * interconnect. This also matches the OSM L3 2286 * from bandwidth table of qcom,cpu4-l3lat-mon 2287 * (qcom,core-dev-table, bus width: 16 bytes) 2288 * from msm-4.9 downstream kernel. 2289 */ 2290 opp-0 { 2291 opp-peak-kBps = <4800000>; 2292 }; 2293 opp-1 { 2294 opp-peak-kBps = <9216000>; 2295 }; 2296 opp-2 { 2297 opp-peak-kBps = <15052800>; 2298 }; 2299 opp-3 { 2300 opp-peak-kBps = <20889600>; 2301 }; 2302 opp-4 { 2303 opp-peak-kBps = <25497600>; 2304 }; 2305 }; 2306 }; 2307 2308 pcie0: pci@1c00000 { 2309 compatible = "qcom,pcie-sdm845"; 2310 reg = <0 0x01c00000 0 0x2000>, 2311 <0 0x60000000 0 0xf1d>, 2312 <0 0x60000f20 0 0xa8>, 2313 <0 0x60100000 0 0x100000>, 2314 <0 0x01c07000 0 0x1000>; 2315 reg-names = "parf", "dbi", "elbi", "config", "mhi"; 2316 device_type = "pci"; 2317 linux,pci-domain = <0>; 2318 bus-range = <0x00 0xff>; 2319 num-lanes = <1>; 2320 2321 #address-cells = <3>; 2322 #size-cells = <2>; 2323 2324 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 2325 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0xd00000>; 2326 2327 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 2328 interrupt-names = "msi"; 2329 #interrupt-cells = <1>; 2330 interrupt-map-mask = <0 0 0 0x7>; 2331 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 2332 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 2333 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 2334 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 2335 2336 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 2337 <&gcc GCC_PCIE_0_AUX_CLK>, 2338 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 2339 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 2340 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 2341 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 2342 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; 2343 clock-names = "pipe", 2344 "aux", 2345 "cfg", 2346 "bus_master", 2347 "bus_slave", 2348 "slave_q2a", 2349 "tbu"; 2350 2351 iommu-map = <0x0 &apps_smmu 0x1c10 0x1>, 2352 <0x100 &apps_smmu 0x1c11 0x1>, 2353 <0x200 &apps_smmu 0x1c12 0x1>, 2354 <0x300 &apps_smmu 0x1c13 0x1>, 2355 <0x400 &apps_smmu 0x1c14 0x1>, 2356 <0x500 &apps_smmu 0x1c15 0x1>, 2357 <0x600 &apps_smmu 0x1c16 0x1>, 2358 <0x700 &apps_smmu 0x1c17 0x1>, 2359 <0x800 &apps_smmu 0x1c18 0x1>, 2360 <0x900 &apps_smmu 0x1c19 0x1>, 2361 <0xa00 &apps_smmu 0x1c1a 0x1>, 2362 <0xb00 &apps_smmu 0x1c1b 0x1>, 2363 <0xc00 &apps_smmu 0x1c1c 0x1>, 2364 <0xd00 &apps_smmu 0x1c1d 0x1>, 2365 <0xe00 &apps_smmu 0x1c1e 0x1>, 2366 <0xf00 &apps_smmu 0x1c1f 0x1>; 2367 2368 resets = <&gcc GCC_PCIE_0_BCR>; 2369 reset-names = "pci"; 2370 2371 power-domains = <&gcc PCIE_0_GDSC>; 2372 2373 phys = <&pcie0_lane>; 2374 phy-names = "pciephy"; 2375 2376 status = "disabled"; 2377 }; 2378 2379 pcie0_phy: phy@1c06000 { 2380 compatible = "qcom,sdm845-qmp-pcie-phy"; 2381 reg = <0 0x01c06000 0 0x18c>; 2382 #address-cells = <2>; 2383 #size-cells = <2>; 2384 ranges; 2385 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 2386 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 2387 <&gcc GCC_PCIE_0_CLKREF_CLK>, 2388 <&gcc GCC_PCIE_PHY_REFGEN_CLK>; 2389 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 2390 2391 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 2392 reset-names = "phy"; 2393 2394 assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>; 2395 assigned-clock-rates = <100000000>; 2396 2397 status = "disabled"; 2398 2399 pcie0_lane: phy@1c06200 { 2400 reg = <0 0x01c06200 0 0x128>, 2401 <0 0x01c06400 0 0x1fc>, 2402 <0 0x01c06800 0 0x218>, 2403 <0 0x01c06600 0 0x70>; 2404 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 2405 clock-names = "pipe0"; 2406 2407 #clock-cells = <0>; 2408 #phy-cells = <0>; 2409 clock-output-names = "pcie_0_pipe_clk"; 2410 }; 2411 }; 2412 2413 pcie1: pci@1c08000 { 2414 compatible = "qcom,pcie-sdm845"; 2415 reg = <0 0x01c08000 0 0x2000>, 2416 <0 0x40000000 0 0xf1d>, 2417 <0 0x40000f20 0 0xa8>, 2418 <0 0x40100000 0 0x100000>, 2419 <0 0x01c0c000 0 0x1000>; 2420 reg-names = "parf", "dbi", "elbi", "config", "mhi"; 2421 device_type = "pci"; 2422 linux,pci-domain = <1>; 2423 bus-range = <0x00 0xff>; 2424 num-lanes = <1>; 2425 2426 #address-cells = <3>; 2427 #size-cells = <2>; 2428 2429 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 2430 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 2431 2432 interrupts = <GIC_SPI 307 IRQ_TYPE_EDGE_RISING>; 2433 interrupt-names = "msi"; 2434 #interrupt-cells = <1>; 2435 interrupt-map-mask = <0 0 0 0x7>; 2436 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 2437 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 2438 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 2439 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 2440 2441 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 2442 <&gcc GCC_PCIE_1_AUX_CLK>, 2443 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2444 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 2445 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 2446 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 2447 <&gcc GCC_PCIE_1_CLKREF_CLK>, 2448 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; 2449 clock-names = "pipe", 2450 "aux", 2451 "cfg", 2452 "bus_master", 2453 "bus_slave", 2454 "slave_q2a", 2455 "ref", 2456 "tbu"; 2457 2458 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 2459 assigned-clock-rates = <19200000>; 2460 2461 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, 2462 <0x100 &apps_smmu 0x1c01 0x1>, 2463 <0x200 &apps_smmu 0x1c02 0x1>, 2464 <0x300 &apps_smmu 0x1c03 0x1>, 2465 <0x400 &apps_smmu 0x1c04 0x1>, 2466 <0x500 &apps_smmu 0x1c05 0x1>, 2467 <0x600 &apps_smmu 0x1c06 0x1>, 2468 <0x700 &apps_smmu 0x1c07 0x1>, 2469 <0x800 &apps_smmu 0x1c08 0x1>, 2470 <0x900 &apps_smmu 0x1c09 0x1>, 2471 <0xa00 &apps_smmu 0x1c0a 0x1>, 2472 <0xb00 &apps_smmu 0x1c0b 0x1>, 2473 <0xc00 &apps_smmu 0x1c0c 0x1>, 2474 <0xd00 &apps_smmu 0x1c0d 0x1>, 2475 <0xe00 &apps_smmu 0x1c0e 0x1>, 2476 <0xf00 &apps_smmu 0x1c0f 0x1>; 2477 2478 resets = <&gcc GCC_PCIE_1_BCR>; 2479 reset-names = "pci"; 2480 2481 power-domains = <&gcc PCIE_1_GDSC>; 2482 2483 phys = <&pcie1_lane>; 2484 phy-names = "pciephy"; 2485 2486 status = "disabled"; 2487 }; 2488 2489 pcie1_phy: phy@1c0a000 { 2490 compatible = "qcom,sdm845-qhp-pcie-phy"; 2491 reg = <0 0x01c0a000 0 0x800>; 2492 #address-cells = <2>; 2493 #size-cells = <2>; 2494 ranges; 2495 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 2496 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2497 <&gcc GCC_PCIE_1_CLKREF_CLK>, 2498 <&gcc GCC_PCIE_PHY_REFGEN_CLK>; 2499 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 2500 2501 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 2502 reset-names = "phy"; 2503 2504 assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>; 2505 assigned-clock-rates = <100000000>; 2506 2507 status = "disabled"; 2508 2509 pcie1_lane: phy@1c06200 { 2510 reg = <0 0x01c0a800 0 0x800>, 2511 <0 0x01c0a800 0 0x800>, 2512 <0 0x01c0b800 0 0x400>; 2513 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 2514 clock-names = "pipe0"; 2515 2516 #clock-cells = <0>; 2517 #phy-cells = <0>; 2518 clock-output-names = "pcie_1_pipe_clk"; 2519 }; 2520 }; 2521 2522 mem_noc: interconnect@1380000 { 2523 compatible = "qcom,sdm845-mem-noc"; 2524 reg = <0 0x01380000 0 0x27200>; 2525 #interconnect-cells = <2>; 2526 qcom,bcm-voters = <&apps_bcm_voter>; 2527 }; 2528 2529 dc_noc: interconnect@14e0000 { 2530 compatible = "qcom,sdm845-dc-noc"; 2531 reg = <0 0x014e0000 0 0x400>; 2532 #interconnect-cells = <2>; 2533 qcom,bcm-voters = <&apps_bcm_voter>; 2534 }; 2535 2536 config_noc: interconnect@1500000 { 2537 compatible = "qcom,sdm845-config-noc"; 2538 reg = <0 0x01500000 0 0x5080>; 2539 #interconnect-cells = <2>; 2540 qcom,bcm-voters = <&apps_bcm_voter>; 2541 }; 2542 2543 system_noc: interconnect@1620000 { 2544 compatible = "qcom,sdm845-system-noc"; 2545 reg = <0 0x01620000 0 0x18080>; 2546 #interconnect-cells = <2>; 2547 qcom,bcm-voters = <&apps_bcm_voter>; 2548 }; 2549 2550 aggre1_noc: interconnect@16e0000 { 2551 compatible = "qcom,sdm845-aggre1-noc"; 2552 reg = <0 0x016e0000 0 0x15080>; 2553 #interconnect-cells = <2>; 2554 qcom,bcm-voters = <&apps_bcm_voter>; 2555 }; 2556 2557 aggre2_noc: interconnect@1700000 { 2558 compatible = "qcom,sdm845-aggre2-noc"; 2559 reg = <0 0x01700000 0 0x1f300>; 2560 #interconnect-cells = <2>; 2561 qcom,bcm-voters = <&apps_bcm_voter>; 2562 }; 2563 2564 mmss_noc: interconnect@1740000 { 2565 compatible = "qcom,sdm845-mmss-noc"; 2566 reg = <0 0x01740000 0 0x1c100>; 2567 #interconnect-cells = <2>; 2568 qcom,bcm-voters = <&apps_bcm_voter>; 2569 }; 2570 2571 ufs_mem_hc: ufshc@1d84000 { 2572 compatible = "qcom,sdm845-ufshc", "qcom,ufshc", 2573 "jedec,ufs-2.0"; 2574 reg = <0 0x01d84000 0 0x2500>, 2575 <0 0x01d90000 0 0x8000>; 2576 reg-names = "std", "ice"; 2577 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2578 phys = <&ufs_mem_phy_lanes>; 2579 phy-names = "ufsphy"; 2580 lanes-per-direction = <2>; 2581 power-domains = <&gcc UFS_PHY_GDSC>; 2582 #reset-cells = <1>; 2583 resets = <&gcc GCC_UFS_PHY_BCR>; 2584 reset-names = "rst"; 2585 2586 iommus = <&apps_smmu 0x100 0xf>; 2587 2588 clock-names = 2589 "core_clk", 2590 "bus_aggr_clk", 2591 "iface_clk", 2592 "core_clk_unipro", 2593 "ref_clk", 2594 "tx_lane0_sync_clk", 2595 "rx_lane0_sync_clk", 2596 "rx_lane1_sync_clk", 2597 "ice_core_clk"; 2598 clocks = 2599 <&gcc GCC_UFS_PHY_AXI_CLK>, 2600 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2601 <&gcc GCC_UFS_PHY_AHB_CLK>, 2602 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2603 <&rpmhcc RPMH_CXO_CLK>, 2604 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2605 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2606 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, 2607 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 2608 freq-table-hz = 2609 <50000000 200000000>, 2610 <0 0>, 2611 <0 0>, 2612 <37500000 150000000>, 2613 <0 0>, 2614 <0 0>, 2615 <0 0>, 2616 <0 0>, 2617 <75000000 300000000>; 2618 2619 interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mem_noc SLAVE_EBI1 0>, 2620 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>; 2621 interconnect-names = "ufs-ddr", "cpu-ufs"; 2622 2623 status = "disabled"; 2624 }; 2625 2626 ufs_mem_phy: phy@1d87000 { 2627 compatible = "qcom,sdm845-qmp-ufs-phy"; 2628 reg = <0 0x01d87000 0 0x18c>; 2629 #address-cells = <2>; 2630 #size-cells = <2>; 2631 ranges; 2632 clock-names = "ref", 2633 "ref_aux"; 2634 clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, 2635 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 2636 2637 resets = <&ufs_mem_hc 0>; 2638 reset-names = "ufsphy"; 2639 status = "disabled"; 2640 2641 ufs_mem_phy_lanes: phy@1d87400 { 2642 reg = <0 0x01d87400 0 0x108>, 2643 <0 0x01d87600 0 0x1e0>, 2644 <0 0x01d87c00 0 0x1dc>, 2645 <0 0x01d87800 0 0x108>, 2646 <0 0x01d87a00 0 0x1e0>; 2647 #phy-cells = <0>; 2648 }; 2649 }; 2650 2651 cryptobam: dma-controller@1dc4000 { 2652 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 2653 reg = <0 0x01dc4000 0 0x24000>; 2654 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 2655 clocks = <&rpmhcc RPMH_CE_CLK>; 2656 clock-names = "bam_clk"; 2657 #dma-cells = <1>; 2658 qcom,ee = <0>; 2659 qcom,controlled-remotely; 2660 iommus = <&apps_smmu 0x704 0x1>, 2661 <&apps_smmu 0x706 0x1>, 2662 <&apps_smmu 0x714 0x1>, 2663 <&apps_smmu 0x716 0x1>; 2664 }; 2665 2666 crypto: crypto@1dfa000 { 2667 compatible = "qcom,crypto-v5.4"; 2668 reg = <0 0x01dfa000 0 0x6000>; 2669 clocks = <&gcc GCC_CE1_AHB_CLK>, 2670 <&gcc GCC_CE1_AXI_CLK>, 2671 <&rpmhcc RPMH_CE_CLK>; 2672 clock-names = "iface", "bus", "core"; 2673 dmas = <&cryptobam 6>, <&cryptobam 7>; 2674 dma-names = "rx", "tx"; 2675 iommus = <&apps_smmu 0x704 0x1>, 2676 <&apps_smmu 0x706 0x1>, 2677 <&apps_smmu 0x714 0x1>, 2678 <&apps_smmu 0x716 0x1>; 2679 }; 2680 2681 ipa: ipa@1e40000 { 2682 compatible = "qcom,sdm845-ipa"; 2683 2684 iommus = <&apps_smmu 0x720 0x0>, 2685 <&apps_smmu 0x722 0x0>; 2686 reg = <0 0x01e40000 0 0x7000>, 2687 <0 0x01e47000 0 0x2000>, 2688 <0 0x01e04000 0 0x2c000>; 2689 reg-names = "ipa-reg", 2690 "ipa-shared", 2691 "gsi"; 2692 2693 interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>, 2694 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 2695 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2696 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 2697 interrupt-names = "ipa", 2698 "gsi", 2699 "ipa-clock-query", 2700 "ipa-setup-ready"; 2701 2702 clocks = <&rpmhcc RPMH_IPA_CLK>; 2703 clock-names = "core"; 2704 2705 interconnects = <&aggre2_noc MASTER_IPA 0 &mem_noc SLAVE_EBI1 0>, 2706 <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>, 2707 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>; 2708 interconnect-names = "memory", 2709 "imem", 2710 "config"; 2711 2712 qcom,smem-states = <&ipa_smp2p_out 0>, 2713 <&ipa_smp2p_out 1>; 2714 qcom,smem-state-names = "ipa-clock-enabled-valid", 2715 "ipa-clock-enabled"; 2716 2717 status = "disabled"; 2718 }; 2719 2720 tcsr_mutex: hwlock@1f40000 { 2721 compatible = "qcom,tcsr-mutex"; 2722 reg = <0 0x01f40000 0 0x20000>; 2723 #hwlock-cells = <1>; 2724 }; 2725 2726 tcsr_regs_1: syscon@1f60000 { 2727 compatible = "qcom,sdm845-tcsr", "syscon"; 2728 reg = <0 0x01f60000 0 0x20000>; 2729 }; 2730 2731 tlmm: pinctrl@3400000 { 2732 compatible = "qcom,sdm845-pinctrl"; 2733 reg = <0 0x03400000 0 0xc00000>; 2734 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 2735 gpio-controller; 2736 #gpio-cells = <2>; 2737 interrupt-controller; 2738 #interrupt-cells = <2>; 2739 gpio-ranges = <&tlmm 0 0 151>; 2740 wakeup-parent = <&pdc_intc>; 2741 2742 cci0_default: cci0-default-state { 2743 /* SDA, SCL */ 2744 pins = "gpio17", "gpio18"; 2745 function = "cci_i2c"; 2746 2747 bias-pull-up; 2748 drive-strength = <2>; /* 2 mA */ 2749 }; 2750 2751 cci0_sleep: cci0-sleep-state { 2752 /* SDA, SCL */ 2753 pins = "gpio17", "gpio18"; 2754 function = "cci_i2c"; 2755 2756 drive-strength = <2>; /* 2 mA */ 2757 bias-pull-down; 2758 }; 2759 2760 cci1_default: cci1-default-state { 2761 /* SDA, SCL */ 2762 pins = "gpio19", "gpio20"; 2763 function = "cci_i2c"; 2764 2765 bias-pull-up; 2766 drive-strength = <2>; /* 2 mA */ 2767 }; 2768 2769 cci1_sleep: cci1-sleep-state { 2770 /* SDA, SCL */ 2771 pins = "gpio19", "gpio20"; 2772 function = "cci_i2c"; 2773 2774 drive-strength = <2>; /* 2 mA */ 2775 bias-pull-down; 2776 }; 2777 2778 qspi_clk: qspi-clk-state { 2779 pins = "gpio95"; 2780 function = "qspi_clk"; 2781 }; 2782 2783 qspi_cs0: qspi-cs0-state { 2784 pins = "gpio90"; 2785 function = "qspi_cs"; 2786 }; 2787 2788 qspi_cs1: qspi-cs1-state { 2789 pins = "gpio89"; 2790 function = "qspi_cs"; 2791 }; 2792 2793 qspi_data0: qspi-data0-state { 2794 pins = "gpio91"; 2795 function = "qspi_data"; 2796 }; 2797 2798 qspi_data1: qspi-data1-state { 2799 pins = "gpio92"; 2800 function = "qspi_data"; 2801 }; 2802 2803 qspi_data23: qspi-data23-state { 2804 pins = "gpio93", "gpio94"; 2805 function = "qspi_data"; 2806 }; 2807 2808 qup_i2c0_default: qup-i2c0-default-state { 2809 pins = "gpio0", "gpio1"; 2810 function = "qup0"; 2811 }; 2812 2813 qup_i2c1_default: qup-i2c1-default-state { 2814 pins = "gpio17", "gpio18"; 2815 function = "qup1"; 2816 }; 2817 2818 qup_i2c2_default: qup-i2c2-default-state { 2819 pins = "gpio27", "gpio28"; 2820 function = "qup2"; 2821 }; 2822 2823 qup_i2c3_default: qup-i2c3-default-state { 2824 pins = "gpio41", "gpio42"; 2825 function = "qup3"; 2826 }; 2827 2828 qup_i2c4_default: qup-i2c4-default-state { 2829 pins = "gpio89", "gpio90"; 2830 function = "qup4"; 2831 }; 2832 2833 qup_i2c5_default: qup-i2c5-default-state { 2834 pins = "gpio85", "gpio86"; 2835 function = "qup5"; 2836 }; 2837 2838 qup_i2c6_default: qup-i2c6-default-state { 2839 pins = "gpio45", "gpio46"; 2840 function = "qup6"; 2841 }; 2842 2843 qup_i2c7_default: qup-i2c7-default-state { 2844 pins = "gpio93", "gpio94"; 2845 function = "qup7"; 2846 }; 2847 2848 qup_i2c8_default: qup-i2c8-default-state { 2849 pins = "gpio65", "gpio66"; 2850 function = "qup8"; 2851 }; 2852 2853 qup_i2c9_default: qup-i2c9-default-state { 2854 pins = "gpio6", "gpio7"; 2855 function = "qup9"; 2856 }; 2857 2858 qup_i2c10_default: qup-i2c10-default-state { 2859 pins = "gpio55", "gpio56"; 2860 function = "qup10"; 2861 }; 2862 2863 qup_i2c11_default: qup-i2c11-default-state { 2864 pins = "gpio31", "gpio32"; 2865 function = "qup11"; 2866 }; 2867 2868 qup_i2c12_default: qup-i2c12-default-state { 2869 pins = "gpio49", "gpio50"; 2870 function = "qup12"; 2871 }; 2872 2873 qup_i2c13_default: qup-i2c13-default-state { 2874 pins = "gpio105", "gpio106"; 2875 function = "qup13"; 2876 }; 2877 2878 qup_i2c14_default: qup-i2c14-default-state { 2879 pins = "gpio33", "gpio34"; 2880 function = "qup14"; 2881 }; 2882 2883 qup_i2c15_default: qup-i2c15-default-state { 2884 pins = "gpio81", "gpio82"; 2885 function = "qup15"; 2886 }; 2887 2888 qup_spi0_default: qup-spi0-default-state { 2889 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 2890 function = "qup0"; 2891 }; 2892 2893 qup_spi1_default: qup-spi1-default-state { 2894 pins = "gpio17", "gpio18", "gpio19", "gpio20"; 2895 function = "qup1"; 2896 }; 2897 2898 qup_spi2_default: qup-spi2-default-state { 2899 pins = "gpio27", "gpio28", "gpio29", "gpio30"; 2900 function = "qup2"; 2901 }; 2902 2903 qup_spi3_default: qup-spi3-default-state { 2904 pins = "gpio41", "gpio42", "gpio43", "gpio44"; 2905 function = "qup3"; 2906 }; 2907 2908 qup_spi4_default: qup-spi4-default-state { 2909 pins = "gpio89", "gpio90", "gpio91", "gpio92"; 2910 function = "qup4"; 2911 }; 2912 2913 qup_spi5_default: qup-spi5-default-state { 2914 pins = "gpio85", "gpio86", "gpio87", "gpio88"; 2915 function = "qup5"; 2916 }; 2917 2918 qup_spi6_default: qup-spi6-default-state { 2919 pins = "gpio45", "gpio46", "gpio47", "gpio48"; 2920 function = "qup6"; 2921 }; 2922 2923 qup_spi7_default: qup-spi7-default-state { 2924 pins = "gpio93", "gpio94", "gpio95", "gpio96"; 2925 function = "qup7"; 2926 }; 2927 2928 qup_spi8_default: qup-spi8-default-state { 2929 pins = "gpio65", "gpio66", "gpio67", "gpio68"; 2930 function = "qup8"; 2931 }; 2932 2933 qup_spi9_default: qup-spi9-default-state { 2934 pins = "gpio6", "gpio7", "gpio4", "gpio5"; 2935 function = "qup9"; 2936 }; 2937 2938 qup_spi10_default: qup-spi10-default-state { 2939 pins = "gpio55", "gpio56", "gpio53", "gpio54"; 2940 function = "qup10"; 2941 }; 2942 2943 qup_spi11_default: qup-spi11-default-state { 2944 pins = "gpio31", "gpio32", "gpio33", "gpio34"; 2945 function = "qup11"; 2946 }; 2947 2948 qup_spi12_default: qup-spi12-default-state { 2949 pins = "gpio49", "gpio50", "gpio51", "gpio52"; 2950 function = "qup12"; 2951 }; 2952 2953 qup_spi13_default: qup-spi13-default-state { 2954 pins = "gpio105", "gpio106", "gpio107", "gpio108"; 2955 function = "qup13"; 2956 }; 2957 2958 qup_spi14_default: qup-spi14-default-state { 2959 pins = "gpio33", "gpio34", "gpio31", "gpio32"; 2960 function = "qup14"; 2961 }; 2962 2963 qup_spi15_default: qup-spi15-default-state { 2964 pins = "gpio81", "gpio82", "gpio83", "gpio84"; 2965 function = "qup15"; 2966 }; 2967 2968 qup_uart0_default: qup-uart0-default-state { 2969 qup_uart0_tx: tx-pins { 2970 pins = "gpio2"; 2971 function = "qup0"; 2972 }; 2973 2974 qup_uart0_rx: rx-pins { 2975 pins = "gpio3"; 2976 function = "qup0"; 2977 }; 2978 }; 2979 2980 qup_uart1_default: qup-uart1-default-state { 2981 qup_uart1_tx: tx-pins { 2982 pins = "gpio19"; 2983 function = "qup1"; 2984 }; 2985 2986 qup_uart1_rx: rx-pins { 2987 pins = "gpio20"; 2988 function = "qup1"; 2989 }; 2990 }; 2991 2992 qup_uart2_default: qup-uart2-default-state { 2993 qup_uart2_tx: tx-pins { 2994 pins = "gpio29"; 2995 function = "qup2"; 2996 }; 2997 2998 qup_uart2_rx: rx-pins { 2999 pins = "gpio30"; 3000 function = "qup2"; 3001 }; 3002 }; 3003 3004 qup_uart3_default: qup-uart3-default-state { 3005 qup_uart3_tx: tx-pins { 3006 pins = "gpio43"; 3007 function = "qup3"; 3008 }; 3009 3010 qup_uart3_rx: rx-pins { 3011 pins = "gpio44"; 3012 function = "qup3"; 3013 }; 3014 }; 3015 3016 qup_uart3_4pin: qup-uart3-4pin-state { 3017 qup_uart3_4pin_cts: cts-pins { 3018 pins = "gpio41"; 3019 function = "qup3"; 3020 }; 3021 3022 qup_uart3_4pin_rts_tx: rts-tx-pins { 3023 pins = "gpio42", "gpio43"; 3024 function = "qup3"; 3025 }; 3026 3027 qup_uart3_4pin_rx: rx-pins { 3028 pins = "gpio44"; 3029 function = "qup3"; 3030 }; 3031 }; 3032 3033 qup_uart4_default: qup-uart4-default-state { 3034 qup_uart4_tx: tx-pins { 3035 pins = "gpio91"; 3036 function = "qup4"; 3037 }; 3038 3039 qup_uart4_rx: rx-pins { 3040 pins = "gpio92"; 3041 function = "qup4"; 3042 }; 3043 }; 3044 3045 qup_uart5_default: qup-uart5-default-state { 3046 qup_uart5_tx: tx-pins { 3047 pins = "gpio87"; 3048 function = "qup5"; 3049 }; 3050 3051 qup_uart5_rx: rx-pins { 3052 pins = "gpio88"; 3053 function = "qup5"; 3054 }; 3055 }; 3056 3057 qup_uart6_default: qup-uart6-default-state { 3058 qup_uart6_tx: tx-pins { 3059 pins = "gpio47"; 3060 function = "qup6"; 3061 }; 3062 3063 qup_uart6_rx: rx-pins { 3064 pins = "gpio48"; 3065 function = "qup6"; 3066 }; 3067 }; 3068 3069 qup_uart6_4pin: qup-uart6-4pin-state { 3070 qup_uart6_4pin_cts: cts-pins { 3071 pins = "gpio45"; 3072 function = "qup6"; 3073 bias-pull-down; 3074 }; 3075 3076 qup_uart6_4pin_rts_tx: rts-tx-pins { 3077 pins = "gpio46", "gpio47"; 3078 function = "qup6"; 3079 drive-strength = <2>; 3080 bias-disable; 3081 }; 3082 3083 qup_uart6_4pin_rx: rx-pins { 3084 pins = "gpio48"; 3085 function = "qup6"; 3086 bias-pull-up; 3087 }; 3088 }; 3089 3090 qup_uart7_default: qup-uart7-default-state { 3091 qup_uart7_tx: tx-pins { 3092 pins = "gpio95"; 3093 function = "qup7"; 3094 }; 3095 3096 qup_uart7_rx: rx-pins { 3097 pins = "gpio96"; 3098 function = "qup7"; 3099 }; 3100 }; 3101 3102 qup_uart8_default: qup-uart8-default-state { 3103 qup_uart8_tx: tx-pins { 3104 pins = "gpio67"; 3105 function = "qup8"; 3106 }; 3107 3108 qup_uart8_rx: rx-pins { 3109 pins = "gpio68"; 3110 function = "qup8"; 3111 }; 3112 }; 3113 3114 qup_uart9_default: qup-uart9-default-state { 3115 qup_uart9_tx: tx-pins { 3116 pins = "gpio4"; 3117 function = "qup9"; 3118 }; 3119 3120 qup_uart9_rx: rx-pins { 3121 pins = "gpio5"; 3122 function = "qup9"; 3123 }; 3124 }; 3125 3126 qup_uart10_default: qup-uart10-default-state { 3127 qup_uart10_tx: tx-pins { 3128 pins = "gpio53"; 3129 function = "qup10"; 3130 }; 3131 3132 qup_uart10_rx: rx-pins { 3133 pins = "gpio54"; 3134 function = "qup10"; 3135 }; 3136 }; 3137 3138 qup_uart11_default: qup-uart11-default-state { 3139 qup_uart11_tx: tx-pins { 3140 pins = "gpio33"; 3141 function = "qup11"; 3142 }; 3143 3144 qup_uart11_rx: rx-pins { 3145 pins = "gpio34"; 3146 function = "qup11"; 3147 }; 3148 }; 3149 3150 qup_uart12_default: qup-uart12-default-state { 3151 qup_uart12_tx: tx-pins { 3152 pins = "gpio51"; 3153 function = "qup0"; 3154 }; 3155 3156 qup_uart12_rx: rx-pins { 3157 pins = "gpio52"; 3158 function = "qup0"; 3159 }; 3160 }; 3161 3162 qup_uart13_default: qup-uart13-default-state { 3163 qup_uart13_tx: tx-pins { 3164 pins = "gpio107"; 3165 function = "qup13"; 3166 }; 3167 3168 qup_uart13_rx: rx-pins { 3169 pins = "gpio108"; 3170 function = "qup13"; 3171 }; 3172 }; 3173 3174 qup_uart14_default: qup-uart14-default-state { 3175 qup_uart14_tx: tx-pins { 3176 pins = "gpio31"; 3177 function = "qup14"; 3178 }; 3179 3180 qup_uart14_rx: rx-pins { 3181 pins = "gpio32"; 3182 function = "qup14"; 3183 }; 3184 }; 3185 3186 qup_uart15_default: qup-uart15-default-state { 3187 qup_uart15_tx: tx-pins { 3188 pins = "gpio83"; 3189 function = "qup15"; 3190 }; 3191 3192 qup_uart15_rx: rx-pins { 3193 pins = "gpio84"; 3194 function = "qup15"; 3195 }; 3196 }; 3197 3198 quat_mi2s_sleep: quat-mi2s-sleep-state { 3199 pins = "gpio58", "gpio59"; 3200 function = "gpio"; 3201 drive-strength = <2>; 3202 bias-pull-down; 3203 }; 3204 3205 quat_mi2s_active: quat-mi2s-active-state { 3206 pins = "gpio58", "gpio59"; 3207 function = "qua_mi2s"; 3208 drive-strength = <8>; 3209 bias-disable; 3210 output-high; 3211 }; 3212 3213 quat_mi2s_sd0_sleep: quat-mi2s-sd0-sleep-state { 3214 pins = "gpio60"; 3215 function = "gpio"; 3216 drive-strength = <2>; 3217 bias-pull-down; 3218 }; 3219 3220 quat_mi2s_sd0_active: quat-mi2s-sd0-active-state { 3221 pins = "gpio60"; 3222 function = "qua_mi2s"; 3223 drive-strength = <8>; 3224 bias-disable; 3225 }; 3226 3227 quat_mi2s_sd1_sleep: quat-mi2s-sd1-sleep-state { 3228 pins = "gpio61"; 3229 function = "gpio"; 3230 drive-strength = <2>; 3231 bias-pull-down; 3232 }; 3233 3234 quat_mi2s_sd1_active: quat-mi2s-sd1-active-state { 3235 pins = "gpio61"; 3236 function = "qua_mi2s"; 3237 drive-strength = <8>; 3238 bias-disable; 3239 }; 3240 3241 quat_mi2s_sd2_sleep: quat-mi2s-sd2-sleep-state { 3242 pins = "gpio62"; 3243 function = "gpio"; 3244 drive-strength = <2>; 3245 bias-pull-down; 3246 }; 3247 3248 quat_mi2s_sd2_active: quat-mi2s-sd2-active-state { 3249 pins = "gpio62"; 3250 function = "qua_mi2s"; 3251 drive-strength = <8>; 3252 bias-disable; 3253 }; 3254 3255 quat_mi2s_sd3_sleep: quat-mi2s-sd3-sleep-state { 3256 pins = "gpio63"; 3257 function = "gpio"; 3258 drive-strength = <2>; 3259 bias-pull-down; 3260 }; 3261 3262 quat_mi2s_sd3_active: quat-mi2s-sd3-active-state { 3263 pins = "gpio63"; 3264 function = "qua_mi2s"; 3265 drive-strength = <8>; 3266 bias-disable; 3267 }; 3268 }; 3269 3270 mss_pil: remoteproc@4080000 { 3271 compatible = "qcom,sdm845-mss-pil"; 3272 reg = <0 0x04080000 0 0x408>, <0 0x04180000 0 0x48>; 3273 reg-names = "qdsp6", "rmb"; 3274 3275 interrupts-extended = 3276 <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, 3277 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3278 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3279 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3280 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 3281 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 3282 interrupt-names = "wdog", "fatal", "ready", 3283 "handover", "stop-ack", 3284 "shutdown-ack"; 3285 3286 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 3287 <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>, 3288 <&gcc GCC_BOOT_ROM_AHB_CLK>, 3289 <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>, 3290 <&gcc GCC_MSS_SNOC_AXI_CLK>, 3291 <&gcc GCC_MSS_MFAB_AXIS_CLK>, 3292 <&gcc GCC_PRNG_AHB_CLK>, 3293 <&rpmhcc RPMH_CXO_CLK>; 3294 clock-names = "iface", "bus", "mem", "gpll0_mss", 3295 "snoc_axi", "mnoc_axi", "prng", "xo"; 3296 3297 qcom,qmp = <&aoss_qmp>; 3298 3299 qcom,smem-states = <&modem_smp2p_out 0>; 3300 qcom,smem-state-names = "stop"; 3301 3302 resets = <&aoss_reset AOSS_CC_MSS_RESTART>, 3303 <&pdc_reset PDC_MODEM_SYNC_RESET>; 3304 reset-names = "mss_restart", "pdc_reset"; 3305 3306 qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>; 3307 3308 power-domains = <&rpmhpd SDM845_CX>, 3309 <&rpmhpd SDM845_MX>, 3310 <&rpmhpd SDM845_MSS>; 3311 power-domain-names = "cx", "mx", "mss"; 3312 3313 status = "disabled"; 3314 3315 mba { 3316 memory-region = <&mba_region>; 3317 }; 3318 3319 mpss { 3320 memory-region = <&mpss_region>; 3321 }; 3322 3323 metadata { 3324 memory-region = <&mdata_mem>; 3325 }; 3326 3327 glink-edge { 3328 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 3329 label = "modem"; 3330 qcom,remote-pid = <1>; 3331 mboxes = <&apss_shared 12>; 3332 }; 3333 }; 3334 3335 gpucc: clock-controller@5090000 { 3336 compatible = "qcom,sdm845-gpucc"; 3337 reg = <0 0x05090000 0 0x9000>; 3338 #clock-cells = <1>; 3339 #reset-cells = <1>; 3340 #power-domain-cells = <1>; 3341 clocks = <&rpmhcc RPMH_CXO_CLK>, 3342 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 3343 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 3344 clock-names = "bi_tcxo", 3345 "gcc_gpu_gpll0_clk_src", 3346 "gcc_gpu_gpll0_div_clk_src"; 3347 }; 3348 3349 slpi_pas: remoteproc@5c00000 { 3350 compatible = "qcom,sdm845-slpi-pas"; 3351 reg = <0 0x5c00000 0 0x4000>; 3352 3353 interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>, 3354 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3355 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3356 <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3357 <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 3358 interrupt-names = "wdog", "fatal", "ready", 3359 "handover", "stop-ack"; 3360 3361 clocks = <&rpmhcc RPMH_CXO_CLK>; 3362 clock-names = "xo"; 3363 3364 qcom,qmp = <&aoss_qmp>; 3365 3366 power-domains = <&rpmhpd SDM845_LCX>, 3367 <&rpmhpd SDM845_LMX>; 3368 power-domain-names = "lcx", "lmx"; 3369 3370 memory-region = <&slpi_mem>; 3371 3372 qcom,smem-states = <&slpi_smp2p_out 0>; 3373 qcom,smem-state-names = "stop"; 3374 3375 status = "disabled"; 3376 3377 glink-edge { 3378 interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>; 3379 label = "dsps"; 3380 qcom,remote-pid = <3>; 3381 mboxes = <&apss_shared 24>; 3382 3383 fastrpc { 3384 compatible = "qcom,fastrpc"; 3385 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3386 label = "sdsp"; 3387 qcom,non-secure-domain; 3388 qcom,vmids = <QCOM_SCM_VMID_HLOS QCOM_SCM_VMID_MSS_MSA 3389 QCOM_SCM_VMID_SSC_Q6 QCOM_SCM_VMID_ADSP_Q6>; 3390 memory-region = <&fastrpc_mem>; 3391 #address-cells = <1>; 3392 #size-cells = <0>; 3393 3394 compute-cb@0 { 3395 compatible = "qcom,fastrpc-compute-cb"; 3396 reg = <0>; 3397 }; 3398 }; 3399 }; 3400 }; 3401 3402 stm@6002000 { 3403 compatible = "arm,coresight-stm", "arm,primecell"; 3404 reg = <0 0x06002000 0 0x1000>, 3405 <0 0x16280000 0 0x180000>; 3406 reg-names = "stm-base", "stm-stimulus-base"; 3407 3408 clocks = <&aoss_qmp>; 3409 clock-names = "apb_pclk"; 3410 3411 out-ports { 3412 port { 3413 stm_out: endpoint { 3414 remote-endpoint = 3415 <&funnel0_in7>; 3416 }; 3417 }; 3418 }; 3419 }; 3420 3421 funnel@6041000 { 3422 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3423 reg = <0 0x06041000 0 0x1000>; 3424 3425 clocks = <&aoss_qmp>; 3426 clock-names = "apb_pclk"; 3427 3428 out-ports { 3429 port { 3430 funnel0_out: endpoint { 3431 remote-endpoint = 3432 <&merge_funnel_in0>; 3433 }; 3434 }; 3435 }; 3436 3437 in-ports { 3438 #address-cells = <1>; 3439 #size-cells = <0>; 3440 3441 port@7 { 3442 reg = <7>; 3443 funnel0_in7: endpoint { 3444 remote-endpoint = <&stm_out>; 3445 }; 3446 }; 3447 }; 3448 }; 3449 3450 funnel@6043000 { 3451 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3452 reg = <0 0x06043000 0 0x1000>; 3453 3454 clocks = <&aoss_qmp>; 3455 clock-names = "apb_pclk"; 3456 3457 out-ports { 3458 port { 3459 funnel2_out: endpoint { 3460 remote-endpoint = 3461 <&merge_funnel_in2>; 3462 }; 3463 }; 3464 }; 3465 3466 in-ports { 3467 #address-cells = <1>; 3468 #size-cells = <0>; 3469 3470 port@5 { 3471 reg = <5>; 3472 funnel2_in5: endpoint { 3473 remote-endpoint = 3474 <&apss_merge_funnel_out>; 3475 }; 3476 }; 3477 }; 3478 }; 3479 3480 funnel@6045000 { 3481 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3482 reg = <0 0x06045000 0 0x1000>; 3483 3484 clocks = <&aoss_qmp>; 3485 clock-names = "apb_pclk"; 3486 3487 out-ports { 3488 port { 3489 merge_funnel_out: endpoint { 3490 remote-endpoint = <&etf_in>; 3491 }; 3492 }; 3493 }; 3494 3495 in-ports { 3496 #address-cells = <1>; 3497 #size-cells = <0>; 3498 3499 port@0 { 3500 reg = <0>; 3501 merge_funnel_in0: endpoint { 3502 remote-endpoint = 3503 <&funnel0_out>; 3504 }; 3505 }; 3506 3507 port@2 { 3508 reg = <2>; 3509 merge_funnel_in2: endpoint { 3510 remote-endpoint = 3511 <&funnel2_out>; 3512 }; 3513 }; 3514 }; 3515 }; 3516 3517 replicator@6046000 { 3518 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 3519 reg = <0 0x06046000 0 0x1000>; 3520 3521 clocks = <&aoss_qmp>; 3522 clock-names = "apb_pclk"; 3523 3524 out-ports { 3525 port { 3526 replicator_out: endpoint { 3527 remote-endpoint = <&etr_in>; 3528 }; 3529 }; 3530 }; 3531 3532 in-ports { 3533 port { 3534 replicator_in: endpoint { 3535 remote-endpoint = <&etf_out>; 3536 }; 3537 }; 3538 }; 3539 }; 3540 3541 etf@6047000 { 3542 compatible = "arm,coresight-tmc", "arm,primecell"; 3543 reg = <0 0x06047000 0 0x1000>; 3544 3545 clocks = <&aoss_qmp>; 3546 clock-names = "apb_pclk"; 3547 3548 out-ports { 3549 port { 3550 etf_out: endpoint { 3551 remote-endpoint = 3552 <&replicator_in>; 3553 }; 3554 }; 3555 }; 3556 3557 in-ports { 3558 3559 port { 3560 etf_in: endpoint { 3561 remote-endpoint = 3562 <&merge_funnel_out>; 3563 }; 3564 }; 3565 }; 3566 }; 3567 3568 etr@6048000 { 3569 compatible = "arm,coresight-tmc", "arm,primecell"; 3570 reg = <0 0x06048000 0 0x1000>; 3571 3572 clocks = <&aoss_qmp>; 3573 clock-names = "apb_pclk"; 3574 arm,scatter-gather; 3575 3576 in-ports { 3577 port { 3578 etr_in: endpoint { 3579 remote-endpoint = 3580 <&replicator_out>; 3581 }; 3582 }; 3583 }; 3584 }; 3585 3586 etm@7040000 { 3587 compatible = "arm,coresight-etm4x", "arm,primecell"; 3588 reg = <0 0x07040000 0 0x1000>; 3589 3590 cpu = <&CPU0>; 3591 3592 clocks = <&aoss_qmp>; 3593 clock-names = "apb_pclk"; 3594 arm,coresight-loses-context-with-cpu; 3595 3596 out-ports { 3597 port { 3598 etm0_out: endpoint { 3599 remote-endpoint = 3600 <&apss_funnel_in0>; 3601 }; 3602 }; 3603 }; 3604 }; 3605 3606 etm@7140000 { 3607 compatible = "arm,coresight-etm4x", "arm,primecell"; 3608 reg = <0 0x07140000 0 0x1000>; 3609 3610 cpu = <&CPU1>; 3611 3612 clocks = <&aoss_qmp>; 3613 clock-names = "apb_pclk"; 3614 arm,coresight-loses-context-with-cpu; 3615 3616 out-ports { 3617 port { 3618 etm1_out: endpoint { 3619 remote-endpoint = 3620 <&apss_funnel_in1>; 3621 }; 3622 }; 3623 }; 3624 }; 3625 3626 etm@7240000 { 3627 compatible = "arm,coresight-etm4x", "arm,primecell"; 3628 reg = <0 0x07240000 0 0x1000>; 3629 3630 cpu = <&CPU2>; 3631 3632 clocks = <&aoss_qmp>; 3633 clock-names = "apb_pclk"; 3634 arm,coresight-loses-context-with-cpu; 3635 3636 out-ports { 3637 port { 3638 etm2_out: endpoint { 3639 remote-endpoint = 3640 <&apss_funnel_in2>; 3641 }; 3642 }; 3643 }; 3644 }; 3645 3646 etm@7340000 { 3647 compatible = "arm,coresight-etm4x", "arm,primecell"; 3648 reg = <0 0x07340000 0 0x1000>; 3649 3650 cpu = <&CPU3>; 3651 3652 clocks = <&aoss_qmp>; 3653 clock-names = "apb_pclk"; 3654 arm,coresight-loses-context-with-cpu; 3655 3656 out-ports { 3657 port { 3658 etm3_out: endpoint { 3659 remote-endpoint = 3660 <&apss_funnel_in3>; 3661 }; 3662 }; 3663 }; 3664 }; 3665 3666 etm@7440000 { 3667 compatible = "arm,coresight-etm4x", "arm,primecell"; 3668 reg = <0 0x07440000 0 0x1000>; 3669 3670 cpu = <&CPU4>; 3671 3672 clocks = <&aoss_qmp>; 3673 clock-names = "apb_pclk"; 3674 arm,coresight-loses-context-with-cpu; 3675 3676 out-ports { 3677 port { 3678 etm4_out: endpoint { 3679 remote-endpoint = 3680 <&apss_funnel_in4>; 3681 }; 3682 }; 3683 }; 3684 }; 3685 3686 etm@7540000 { 3687 compatible = "arm,coresight-etm4x", "arm,primecell"; 3688 reg = <0 0x07540000 0 0x1000>; 3689 3690 cpu = <&CPU5>; 3691 3692 clocks = <&aoss_qmp>; 3693 clock-names = "apb_pclk"; 3694 arm,coresight-loses-context-with-cpu; 3695 3696 out-ports { 3697 port { 3698 etm5_out: endpoint { 3699 remote-endpoint = 3700 <&apss_funnel_in5>; 3701 }; 3702 }; 3703 }; 3704 }; 3705 3706 etm@7640000 { 3707 compatible = "arm,coresight-etm4x", "arm,primecell"; 3708 reg = <0 0x07640000 0 0x1000>; 3709 3710 cpu = <&CPU6>; 3711 3712 clocks = <&aoss_qmp>; 3713 clock-names = "apb_pclk"; 3714 arm,coresight-loses-context-with-cpu; 3715 3716 out-ports { 3717 port { 3718 etm6_out: endpoint { 3719 remote-endpoint = 3720 <&apss_funnel_in6>; 3721 }; 3722 }; 3723 }; 3724 }; 3725 3726 etm@7740000 { 3727 compatible = "arm,coresight-etm4x", "arm,primecell"; 3728 reg = <0 0x07740000 0 0x1000>; 3729 3730 cpu = <&CPU7>; 3731 3732 clocks = <&aoss_qmp>; 3733 clock-names = "apb_pclk"; 3734 arm,coresight-loses-context-with-cpu; 3735 3736 out-ports { 3737 port { 3738 etm7_out: endpoint { 3739 remote-endpoint = 3740 <&apss_funnel_in7>; 3741 }; 3742 }; 3743 }; 3744 }; 3745 3746 funnel@7800000 { /* APSS Funnel */ 3747 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3748 reg = <0 0x07800000 0 0x1000>; 3749 3750 clocks = <&aoss_qmp>; 3751 clock-names = "apb_pclk"; 3752 3753 out-ports { 3754 port { 3755 apss_funnel_out: endpoint { 3756 remote-endpoint = 3757 <&apss_merge_funnel_in>; 3758 }; 3759 }; 3760 }; 3761 3762 in-ports { 3763 #address-cells = <1>; 3764 #size-cells = <0>; 3765 3766 port@0 { 3767 reg = <0>; 3768 apss_funnel_in0: endpoint { 3769 remote-endpoint = 3770 <&etm0_out>; 3771 }; 3772 }; 3773 3774 port@1 { 3775 reg = <1>; 3776 apss_funnel_in1: endpoint { 3777 remote-endpoint = 3778 <&etm1_out>; 3779 }; 3780 }; 3781 3782 port@2 { 3783 reg = <2>; 3784 apss_funnel_in2: endpoint { 3785 remote-endpoint = 3786 <&etm2_out>; 3787 }; 3788 }; 3789 3790 port@3 { 3791 reg = <3>; 3792 apss_funnel_in3: endpoint { 3793 remote-endpoint = 3794 <&etm3_out>; 3795 }; 3796 }; 3797 3798 port@4 { 3799 reg = <4>; 3800 apss_funnel_in4: endpoint { 3801 remote-endpoint = 3802 <&etm4_out>; 3803 }; 3804 }; 3805 3806 port@5 { 3807 reg = <5>; 3808 apss_funnel_in5: endpoint { 3809 remote-endpoint = 3810 <&etm5_out>; 3811 }; 3812 }; 3813 3814 port@6 { 3815 reg = <6>; 3816 apss_funnel_in6: endpoint { 3817 remote-endpoint = 3818 <&etm6_out>; 3819 }; 3820 }; 3821 3822 port@7 { 3823 reg = <7>; 3824 apss_funnel_in7: endpoint { 3825 remote-endpoint = 3826 <&etm7_out>; 3827 }; 3828 }; 3829 }; 3830 }; 3831 3832 funnel@7810000 { 3833 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3834 reg = <0 0x07810000 0 0x1000>; 3835 3836 clocks = <&aoss_qmp>; 3837 clock-names = "apb_pclk"; 3838 3839 out-ports { 3840 port { 3841 apss_merge_funnel_out: endpoint { 3842 remote-endpoint = 3843 <&funnel2_in5>; 3844 }; 3845 }; 3846 }; 3847 3848 in-ports { 3849 port { 3850 apss_merge_funnel_in: endpoint { 3851 remote-endpoint = 3852 <&apss_funnel_out>; 3853 }; 3854 }; 3855 }; 3856 }; 3857 3858 sdhc_2: mmc@8804000 { 3859 compatible = "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5"; 3860 reg = <0 0x08804000 0 0x1000>; 3861 3862 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 3863 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 3864 interrupt-names = "hc_irq", "pwr_irq"; 3865 3866 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3867 <&gcc GCC_SDCC2_APPS_CLK>, 3868 <&rpmhcc RPMH_CXO_CLK>; 3869 clock-names = "iface", "core", "xo"; 3870 iommus = <&apps_smmu 0xa0 0xf>; 3871 power-domains = <&rpmhpd SDM845_CX>; 3872 operating-points-v2 = <&sdhc2_opp_table>; 3873 3874 status = "disabled"; 3875 3876 sdhc2_opp_table: opp-table { 3877 compatible = "operating-points-v2"; 3878 3879 opp-9600000 { 3880 opp-hz = /bits/ 64 <9600000>; 3881 required-opps = <&rpmhpd_opp_min_svs>; 3882 }; 3883 3884 opp-19200000 { 3885 opp-hz = /bits/ 64 <19200000>; 3886 required-opps = <&rpmhpd_opp_low_svs>; 3887 }; 3888 3889 opp-100000000 { 3890 opp-hz = /bits/ 64 <100000000>; 3891 required-opps = <&rpmhpd_opp_svs>; 3892 }; 3893 3894 opp-201500000 { 3895 opp-hz = /bits/ 64 <201500000>; 3896 required-opps = <&rpmhpd_opp_svs_l1>; 3897 }; 3898 }; 3899 }; 3900 3901 qspi: spi@88df000 { 3902 compatible = "qcom,sdm845-qspi", "qcom,qspi-v1"; 3903 reg = <0 0x088df000 0 0x600>; 3904 iommus = <&apps_smmu 0x160 0x0>; 3905 #address-cells = <1>; 3906 #size-cells = <0>; 3907 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 3908 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 3909 <&gcc GCC_QSPI_CORE_CLK>; 3910 clock-names = "iface", "core"; 3911 power-domains = <&rpmhpd SDM845_CX>; 3912 operating-points-v2 = <&qspi_opp_table>; 3913 status = "disabled"; 3914 }; 3915 3916 slim: slim-ngd@171c0000 { 3917 compatible = "qcom,slim-ngd-v2.1.0"; 3918 reg = <0 0x171c0000 0 0x2c000>; 3919 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 3920 3921 dmas = <&slimbam 3>, <&slimbam 4>; 3922 dma-names = "rx", "tx"; 3923 3924 iommus = <&apps_smmu 0x1806 0x0>; 3925 #address-cells = <1>; 3926 #size-cells = <0>; 3927 status = "disabled"; 3928 }; 3929 3930 lmh_cluster1: lmh@17d70800 { 3931 compatible = "qcom,sdm845-lmh"; 3932 reg = <0 0x17d70800 0 0x400>; 3933 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 3934 cpus = <&CPU4>; 3935 qcom,lmh-temp-arm-millicelsius = <65000>; 3936 qcom,lmh-temp-low-millicelsius = <94500>; 3937 qcom,lmh-temp-high-millicelsius = <95000>; 3938 interrupt-controller; 3939 #interrupt-cells = <1>; 3940 }; 3941 3942 lmh_cluster0: lmh@17d78800 { 3943 compatible = "qcom,sdm845-lmh"; 3944 reg = <0 0x17d78800 0 0x400>; 3945 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 3946 cpus = <&CPU0>; 3947 qcom,lmh-temp-arm-millicelsius = <65000>; 3948 qcom,lmh-temp-low-millicelsius = <94500>; 3949 qcom,lmh-temp-high-millicelsius = <95000>; 3950 interrupt-controller; 3951 #interrupt-cells = <1>; 3952 }; 3953 3954 usb_1_hsphy: phy@88e2000 { 3955 compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy"; 3956 reg = <0 0x088e2000 0 0x400>; 3957 status = "disabled"; 3958 #phy-cells = <0>; 3959 3960 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 3961 <&rpmhcc RPMH_CXO_CLK>; 3962 clock-names = "cfg_ahb", "ref"; 3963 3964 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3965 3966 nvmem-cells = <&qusb2p_hstx_trim>; 3967 }; 3968 3969 usb_2_hsphy: phy@88e3000 { 3970 compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy"; 3971 reg = <0 0x088e3000 0 0x400>; 3972 status = "disabled"; 3973 #phy-cells = <0>; 3974 3975 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 3976 <&rpmhcc RPMH_CXO_CLK>; 3977 clock-names = "cfg_ahb", "ref"; 3978 3979 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3980 3981 nvmem-cells = <&qusb2s_hstx_trim>; 3982 }; 3983 3984 usb_1_qmpphy: phy@88e9000 { 3985 compatible = "qcom,sdm845-qmp-usb3-dp-phy"; 3986 reg = <0 0x088e9000 0 0x18c>, 3987 <0 0x088e8000 0 0x38>, 3988 <0 0x088ea000 0 0x40>; 3989 status = "disabled"; 3990 #address-cells = <2>; 3991 #size-cells = <2>; 3992 ranges; 3993 3994 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3995 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 3996 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 3997 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 3998 clock-names = "aux", "cfg_ahb", "ref", "com_aux"; 3999 4000 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 4001 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; 4002 reset-names = "phy", "common"; 4003 4004 usb_1_ssphy: usb3-phy@88e9200 { 4005 reg = <0 0x088e9200 0 0x128>, 4006 <0 0x088e9400 0 0x200>, 4007 <0 0x088e9c00 0 0x218>, 4008 <0 0x088e9600 0 0x128>, 4009 <0 0x088e9800 0 0x200>, 4010 <0 0x088e9a00 0 0x100>; 4011 #clock-cells = <0>; 4012 #phy-cells = <0>; 4013 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 4014 clock-names = "pipe0"; 4015 clock-output-names = "usb3_phy_pipe_clk_src"; 4016 }; 4017 4018 dp_phy: dp-phy@88ea200 { 4019 reg = <0 0x088ea200 0 0x200>, 4020 <0 0x088ea400 0 0x200>, 4021 <0 0x088eaa00 0 0x200>, 4022 <0 0x088ea600 0 0x200>, 4023 <0 0x088ea800 0 0x200>; 4024 #clock-cells = <1>; 4025 #phy-cells = <0>; 4026 }; 4027 }; 4028 4029 usb_2_qmpphy: phy@88eb000 { 4030 compatible = "qcom,sdm845-qmp-usb3-uni-phy"; 4031 reg = <0 0x088eb000 0 0x18c>; 4032 status = "disabled"; 4033 #address-cells = <2>; 4034 #size-cells = <2>; 4035 ranges; 4036 4037 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 4038 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 4039 <&gcc GCC_USB3_SEC_CLKREF_CLK>, 4040 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; 4041 clock-names = "aux", "cfg_ahb", "ref", "com_aux"; 4042 4043 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, 4044 <&gcc GCC_USB3_PHY_SEC_BCR>; 4045 reset-names = "phy", "common"; 4046 4047 usb_2_ssphy: phy@88eb200 { 4048 reg = <0 0x088eb200 0 0x128>, 4049 <0 0x088eb400 0 0x1fc>, 4050 <0 0x088eb800 0 0x218>, 4051 <0 0x088eb600 0 0x70>; 4052 #clock-cells = <0>; 4053 #phy-cells = <0>; 4054 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 4055 clock-names = "pipe0"; 4056 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 4057 }; 4058 }; 4059 4060 usb_1: usb@a6f8800 { 4061 compatible = "qcom,sdm845-dwc3", "qcom,dwc3"; 4062 reg = <0 0x0a6f8800 0 0x400>; 4063 status = "disabled"; 4064 #address-cells = <2>; 4065 #size-cells = <2>; 4066 ranges; 4067 dma-ranges; 4068 4069 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 4070 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 4071 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 4072 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 4073 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 4074 clock-names = "cfg_noc", 4075 "core", 4076 "iface", 4077 "sleep", 4078 "mock_utmi"; 4079 4080 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4081 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 4082 assigned-clock-rates = <19200000>, <150000000>; 4083 4084 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 4085 <&pdc_intc 6 IRQ_TYPE_LEVEL_HIGH>, 4086 <&pdc_intc 8 IRQ_TYPE_EDGE_BOTH>, 4087 <&pdc_intc 9 IRQ_TYPE_EDGE_BOTH>; 4088 interrupt-names = "hs_phy_irq", "ss_phy_irq", 4089 "dm_hs_phy_irq", "dp_hs_phy_irq"; 4090 4091 power-domains = <&gcc USB30_PRIM_GDSC>; 4092 4093 resets = <&gcc GCC_USB30_PRIM_BCR>; 4094 4095 interconnects = <&aggre2_noc MASTER_USB3_0 0 &mem_noc SLAVE_EBI1 0>, 4096 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; 4097 interconnect-names = "usb-ddr", "apps-usb"; 4098 4099 usb_1_dwc3: usb@a600000 { 4100 compatible = "snps,dwc3"; 4101 reg = <0 0x0a600000 0 0xcd00>; 4102 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 4103 iommus = <&apps_smmu 0x740 0>; 4104 snps,dis_u2_susphy_quirk; 4105 snps,dis_enblslpm_quirk; 4106 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 4107 phy-names = "usb2-phy", "usb3-phy"; 4108 }; 4109 }; 4110 4111 usb_2: usb@a8f8800 { 4112 compatible = "qcom,sdm845-dwc3", "qcom,dwc3"; 4113 reg = <0 0x0a8f8800 0 0x400>; 4114 status = "disabled"; 4115 #address-cells = <2>; 4116 #size-cells = <2>; 4117 ranges; 4118 dma-ranges; 4119 4120 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 4121 <&gcc GCC_USB30_SEC_MASTER_CLK>, 4122 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 4123 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 4124 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>; 4125 clock-names = "cfg_noc", 4126 "core", 4127 "iface", 4128 "sleep", 4129 "mock_utmi"; 4130 4131 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 4132 <&gcc GCC_USB30_SEC_MASTER_CLK>; 4133 assigned-clock-rates = <19200000>, <150000000>; 4134 4135 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 4136 <&pdc_intc 7 IRQ_TYPE_LEVEL_HIGH>, 4137 <&pdc_intc 10 IRQ_TYPE_EDGE_BOTH>, 4138 <&pdc_intc 11 IRQ_TYPE_EDGE_BOTH>; 4139 interrupt-names = "hs_phy_irq", "ss_phy_irq", 4140 "dm_hs_phy_irq", "dp_hs_phy_irq"; 4141 4142 power-domains = <&gcc USB30_SEC_GDSC>; 4143 4144 resets = <&gcc GCC_USB30_SEC_BCR>; 4145 4146 interconnects = <&aggre2_noc MASTER_USB3_1 0 &mem_noc SLAVE_EBI1 0>, 4147 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>; 4148 interconnect-names = "usb-ddr", "apps-usb"; 4149 4150 usb_2_dwc3: usb@a800000 { 4151 compatible = "snps,dwc3"; 4152 reg = <0 0x0a800000 0 0xcd00>; 4153 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 4154 iommus = <&apps_smmu 0x760 0>; 4155 snps,dis_u2_susphy_quirk; 4156 snps,dis_enblslpm_quirk; 4157 phys = <&usb_2_hsphy>, <&usb_2_ssphy>; 4158 phy-names = "usb2-phy", "usb3-phy"; 4159 }; 4160 }; 4161 4162 venus: video-codec@aa00000 { 4163 compatible = "qcom,sdm845-venus-v2"; 4164 reg = <0 0x0aa00000 0 0xff000>; 4165 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 4166 power-domains = <&videocc VENUS_GDSC>, 4167 <&videocc VCODEC0_GDSC>, 4168 <&videocc VCODEC1_GDSC>, 4169 <&rpmhpd SDM845_CX>; 4170 power-domain-names = "venus", "vcodec0", "vcodec1", "cx"; 4171 operating-points-v2 = <&venus_opp_table>; 4172 clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>, 4173 <&videocc VIDEO_CC_VENUS_AHB_CLK>, 4174 <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>, 4175 <&videocc VIDEO_CC_VCODEC0_CORE_CLK>, 4176 <&videocc VIDEO_CC_VCODEC0_AXI_CLK>, 4177 <&videocc VIDEO_CC_VCODEC1_CORE_CLK>, 4178 <&videocc VIDEO_CC_VCODEC1_AXI_CLK>; 4179 clock-names = "core", "iface", "bus", 4180 "vcodec0_core", "vcodec0_bus", 4181 "vcodec1_core", "vcodec1_bus"; 4182 iommus = <&apps_smmu 0x10a0 0x8>, 4183 <&apps_smmu 0x10b0 0x0>; 4184 memory-region = <&venus_mem>; 4185 interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mem_noc SLAVE_EBI1 0>, 4186 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>; 4187 interconnect-names = "video-mem", "cpu-cfg"; 4188 4189 status = "disabled"; 4190 4191 video-core0 { 4192 compatible = "venus-decoder"; 4193 }; 4194 4195 video-core1 { 4196 compatible = "venus-encoder"; 4197 }; 4198 4199 venus_opp_table: opp-table { 4200 compatible = "operating-points-v2"; 4201 4202 opp-100000000 { 4203 opp-hz = /bits/ 64 <100000000>; 4204 required-opps = <&rpmhpd_opp_min_svs>; 4205 }; 4206 4207 opp-200000000 { 4208 opp-hz = /bits/ 64 <200000000>; 4209 required-opps = <&rpmhpd_opp_low_svs>; 4210 }; 4211 4212 opp-320000000 { 4213 opp-hz = /bits/ 64 <320000000>; 4214 required-opps = <&rpmhpd_opp_svs>; 4215 }; 4216 4217 opp-380000000 { 4218 opp-hz = /bits/ 64 <380000000>; 4219 required-opps = <&rpmhpd_opp_svs_l1>; 4220 }; 4221 4222 opp-444000000 { 4223 opp-hz = /bits/ 64 <444000000>; 4224 required-opps = <&rpmhpd_opp_nom>; 4225 }; 4226 4227 opp-533000097 { 4228 opp-hz = /bits/ 64 <533000097>; 4229 required-opps = <&rpmhpd_opp_turbo>; 4230 }; 4231 }; 4232 }; 4233 4234 videocc: clock-controller@ab00000 { 4235 compatible = "qcom,sdm845-videocc"; 4236 reg = <0 0x0ab00000 0 0x10000>; 4237 clocks = <&rpmhcc RPMH_CXO_CLK>; 4238 clock-names = "bi_tcxo"; 4239 #clock-cells = <1>; 4240 #power-domain-cells = <1>; 4241 #reset-cells = <1>; 4242 }; 4243 4244 camss: camss@acb3000 { 4245 compatible = "qcom,sdm845-camss"; 4246 4247 reg = <0 0x0acb3000 0 0x1000>, 4248 <0 0x0acba000 0 0x1000>, 4249 <0 0x0acc8000 0 0x1000>, 4250 <0 0x0ac65000 0 0x1000>, 4251 <0 0x0ac66000 0 0x1000>, 4252 <0 0x0ac67000 0 0x1000>, 4253 <0 0x0ac68000 0 0x1000>, 4254 <0 0x0acaf000 0 0x4000>, 4255 <0 0x0acb6000 0 0x4000>, 4256 <0 0x0acc4000 0 0x4000>; 4257 reg-names = "csid0", 4258 "csid1", 4259 "csid2", 4260 "csiphy0", 4261 "csiphy1", 4262 "csiphy2", 4263 "csiphy3", 4264 "vfe0", 4265 "vfe1", 4266 "vfe_lite"; 4267 4268 interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>, 4269 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>, 4270 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>, 4271 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>, 4272 <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>, 4273 <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>, 4274 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, 4275 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>, 4276 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>, 4277 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>; 4278 interrupt-names = "csid0", 4279 "csid1", 4280 "csid2", 4281 "csiphy0", 4282 "csiphy1", 4283 "csiphy2", 4284 "csiphy3", 4285 "vfe0", 4286 "vfe1", 4287 "vfe_lite"; 4288 4289 power-domains = <&clock_camcc IFE_0_GDSC>, 4290 <&clock_camcc IFE_1_GDSC>, 4291 <&clock_camcc TITAN_TOP_GDSC>; 4292 4293 clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, 4294 <&clock_camcc CAM_CC_CPAS_AHB_CLK>, 4295 <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, 4296 <&clock_camcc CAM_CC_IFE_0_CSID_CLK>, 4297 <&clock_camcc CAM_CC_IFE_0_CSID_CLK_SRC>, 4298 <&clock_camcc CAM_CC_IFE_1_CSID_CLK>, 4299 <&clock_camcc CAM_CC_IFE_1_CSID_CLK_SRC>, 4300 <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK>, 4301 <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>, 4302 <&clock_camcc CAM_CC_CSIPHY0_CLK>, 4303 <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>, 4304 <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>, 4305 <&clock_camcc CAM_CC_CSIPHY1_CLK>, 4306 <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK>, 4307 <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>, 4308 <&clock_camcc CAM_CC_CSIPHY2_CLK>, 4309 <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK>, 4310 <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>, 4311 <&clock_camcc CAM_CC_CSIPHY3_CLK>, 4312 <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK>, 4313 <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>, 4314 <&gcc GCC_CAMERA_AHB_CLK>, 4315 <&gcc GCC_CAMERA_AXI_CLK>, 4316 <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, 4317 <&clock_camcc CAM_CC_SOC_AHB_CLK>, 4318 <&clock_camcc CAM_CC_IFE_0_AXI_CLK>, 4319 <&clock_camcc CAM_CC_IFE_0_CLK>, 4320 <&clock_camcc CAM_CC_IFE_0_CPHY_RX_CLK>, 4321 <&clock_camcc CAM_CC_IFE_0_CLK_SRC>, 4322 <&clock_camcc CAM_CC_IFE_1_AXI_CLK>, 4323 <&clock_camcc CAM_CC_IFE_1_CLK>, 4324 <&clock_camcc CAM_CC_IFE_1_CPHY_RX_CLK>, 4325 <&clock_camcc CAM_CC_IFE_1_CLK_SRC>, 4326 <&clock_camcc CAM_CC_IFE_LITE_CLK>, 4327 <&clock_camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, 4328 <&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>; 4329 clock-names = "camnoc_axi", 4330 "cpas_ahb", 4331 "cphy_rx_src", 4332 "csi0", 4333 "csi0_src", 4334 "csi1", 4335 "csi1_src", 4336 "csi2", 4337 "csi2_src", 4338 "csiphy0", 4339 "csiphy0_timer", 4340 "csiphy0_timer_src", 4341 "csiphy1", 4342 "csiphy1_timer", 4343 "csiphy1_timer_src", 4344 "csiphy2", 4345 "csiphy2_timer", 4346 "csiphy2_timer_src", 4347 "csiphy3", 4348 "csiphy3_timer", 4349 "csiphy3_timer_src", 4350 "gcc_camera_ahb", 4351 "gcc_camera_axi", 4352 "slow_ahb_src", 4353 "soc_ahb", 4354 "vfe0_axi", 4355 "vfe0", 4356 "vfe0_cphy_rx", 4357 "vfe0_src", 4358 "vfe1_axi", 4359 "vfe1", 4360 "vfe1_cphy_rx", 4361 "vfe1_src", 4362 "vfe_lite", 4363 "vfe_lite_cphy_rx", 4364 "vfe_lite_src"; 4365 4366 iommus = <&apps_smmu 0x0808 0x0>, 4367 <&apps_smmu 0x0810 0x8>, 4368 <&apps_smmu 0x0c08 0x0>, 4369 <&apps_smmu 0x0c10 0x8>; 4370 4371 status = "disabled"; 4372 4373 ports { 4374 #address-cells = <1>; 4375 #size-cells = <0>; 4376 4377 port@0 { 4378 reg = <0>; 4379 }; 4380 4381 port@1 { 4382 reg = <1>; 4383 }; 4384 4385 port@2 { 4386 reg = <2>; 4387 }; 4388 4389 port@3 { 4390 reg = <3>; 4391 }; 4392 }; 4393 }; 4394 4395 cci: cci@ac4a000 { 4396 compatible = "qcom,sdm845-cci", "qcom,msm8996-cci"; 4397 #address-cells = <1>; 4398 #size-cells = <0>; 4399 4400 reg = <0 0x0ac4a000 0 0x4000>; 4401 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>; 4402 power-domains = <&clock_camcc TITAN_TOP_GDSC>; 4403 4404 clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, 4405 <&clock_camcc CAM_CC_SOC_AHB_CLK>, 4406 <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, 4407 <&clock_camcc CAM_CC_CPAS_AHB_CLK>, 4408 <&clock_camcc CAM_CC_CCI_CLK>, 4409 <&clock_camcc CAM_CC_CCI_CLK_SRC>; 4410 clock-names = "camnoc_axi", 4411 "soc_ahb", 4412 "slow_ahb_src", 4413 "cpas_ahb", 4414 "cci", 4415 "cci_src"; 4416 4417 assigned-clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, 4418 <&clock_camcc CAM_CC_CCI_CLK>; 4419 assigned-clock-rates = <80000000>, <37500000>; 4420 4421 pinctrl-names = "default", "sleep"; 4422 pinctrl-0 = <&cci0_default &cci1_default>; 4423 pinctrl-1 = <&cci0_sleep &cci1_sleep>; 4424 4425 status = "disabled"; 4426 4427 cci_i2c0: i2c-bus@0 { 4428 reg = <0>; 4429 clock-frequency = <1000000>; 4430 #address-cells = <1>; 4431 #size-cells = <0>; 4432 }; 4433 4434 cci_i2c1: i2c-bus@1 { 4435 reg = <1>; 4436 clock-frequency = <1000000>; 4437 #address-cells = <1>; 4438 #size-cells = <0>; 4439 }; 4440 }; 4441 4442 clock_camcc: clock-controller@ad00000 { 4443 compatible = "qcom,sdm845-camcc"; 4444 reg = <0 0x0ad00000 0 0x10000>; 4445 #clock-cells = <1>; 4446 #reset-cells = <1>; 4447 #power-domain-cells = <1>; 4448 clocks = <&rpmhcc RPMH_CXO_CLK>; 4449 clock-names = "bi_tcxo"; 4450 }; 4451 4452 mdss: display-subsystem@ae00000 { 4453 compatible = "qcom,sdm845-mdss"; 4454 reg = <0 0x0ae00000 0 0x1000>; 4455 reg-names = "mdss"; 4456 4457 power-domains = <&dispcc MDSS_GDSC>; 4458 4459 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4460 <&dispcc DISP_CC_MDSS_MDP_CLK>; 4461 clock-names = "iface", "core"; 4462 4463 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 4464 interrupt-controller; 4465 #interrupt-cells = <1>; 4466 4467 interconnects = <&mmss_noc MASTER_MDP0 0 &mem_noc SLAVE_EBI1 0>, 4468 <&mmss_noc MASTER_MDP1 0 &mem_noc SLAVE_EBI1 0>; 4469 interconnect-names = "mdp0-mem", "mdp1-mem"; 4470 4471 iommus = <&apps_smmu 0x880 0x8>, 4472 <&apps_smmu 0xc80 0x8>; 4473 4474 status = "disabled"; 4475 4476 #address-cells = <2>; 4477 #size-cells = <2>; 4478 ranges; 4479 4480 mdss_mdp: display-controller@ae01000 { 4481 compatible = "qcom,sdm845-dpu"; 4482 reg = <0 0x0ae01000 0 0x8f000>, 4483 <0 0x0aeb0000 0 0x2008>; 4484 reg-names = "mdp", "vbif"; 4485 4486 clocks = <&gcc GCC_DISP_AXI_CLK>, 4487 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4488 <&dispcc DISP_CC_MDSS_AXI_CLK>, 4489 <&dispcc DISP_CC_MDSS_MDP_CLK>, 4490 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 4491 clock-names = "gcc-bus", "iface", "bus", "core", "vsync"; 4492 4493 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 4494 assigned-clock-rates = <19200000>; 4495 operating-points-v2 = <&mdp_opp_table>; 4496 power-domains = <&rpmhpd SDM845_CX>; 4497 4498 interrupt-parent = <&mdss>; 4499 interrupts = <0>; 4500 4501 ports { 4502 #address-cells = <1>; 4503 #size-cells = <0>; 4504 4505 port@0 { 4506 reg = <0>; 4507 dpu_intf0_out: endpoint { 4508 remote-endpoint = <&dp_in>; 4509 }; 4510 }; 4511 4512 port@1 { 4513 reg = <1>; 4514 dpu_intf1_out: endpoint { 4515 remote-endpoint = <&mdss_dsi0_in>; 4516 }; 4517 }; 4518 4519 port@2 { 4520 reg = <2>; 4521 dpu_intf2_out: endpoint { 4522 remote-endpoint = <&mdss_dsi1_in>; 4523 }; 4524 }; 4525 }; 4526 4527 mdp_opp_table: opp-table { 4528 compatible = "operating-points-v2"; 4529 4530 opp-19200000 { 4531 opp-hz = /bits/ 64 <19200000>; 4532 required-opps = <&rpmhpd_opp_min_svs>; 4533 }; 4534 4535 opp-171428571 { 4536 opp-hz = /bits/ 64 <171428571>; 4537 required-opps = <&rpmhpd_opp_low_svs>; 4538 }; 4539 4540 opp-344000000 { 4541 opp-hz = /bits/ 64 <344000000>; 4542 required-opps = <&rpmhpd_opp_svs_l1>; 4543 }; 4544 4545 opp-430000000 { 4546 opp-hz = /bits/ 64 <430000000>; 4547 required-opps = <&rpmhpd_opp_nom>; 4548 }; 4549 }; 4550 }; 4551 4552 mdss_dp: displayport-controller@ae90000 { 4553 status = "disabled"; 4554 compatible = "qcom,sdm845-dp"; 4555 4556 reg = <0 0x0ae90000 0 0x200>, 4557 <0 0x0ae90200 0 0x200>, 4558 <0 0x0ae90400 0 0x600>, 4559 <0 0x0ae90a00 0 0x600>, 4560 <0 0x0ae91000 0 0x600>; 4561 4562 interrupt-parent = <&mdss>; 4563 interrupts = <12>; 4564 4565 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4566 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 4567 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 4568 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 4569 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 4570 clock-names = "core_iface", "core_aux", "ctrl_link", 4571 "ctrl_link_iface", "stream_pixel"; 4572 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 4573 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 4574 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>; 4575 phys = <&dp_phy>; 4576 phy-names = "dp"; 4577 4578 operating-points-v2 = <&dp_opp_table>; 4579 power-domains = <&rpmhpd SDM845_CX>; 4580 4581 ports { 4582 #address-cells = <1>; 4583 #size-cells = <0>; 4584 port@0 { 4585 reg = <0>; 4586 dp_in: endpoint { 4587 remote-endpoint = <&dpu_intf0_out>; 4588 }; 4589 }; 4590 4591 port@1 { 4592 reg = <1>; 4593 dp_out: endpoint { }; 4594 }; 4595 }; 4596 4597 dp_opp_table: opp-table { 4598 compatible = "operating-points-v2"; 4599 4600 opp-162000000 { 4601 opp-hz = /bits/ 64 <162000000>; 4602 required-opps = <&rpmhpd_opp_low_svs>; 4603 }; 4604 4605 opp-270000000 { 4606 opp-hz = /bits/ 64 <270000000>; 4607 required-opps = <&rpmhpd_opp_svs>; 4608 }; 4609 4610 opp-540000000 { 4611 opp-hz = /bits/ 64 <540000000>; 4612 required-opps = <&rpmhpd_opp_svs_l1>; 4613 }; 4614 4615 opp-810000000 { 4616 opp-hz = /bits/ 64 <810000000>; 4617 required-opps = <&rpmhpd_opp_nom>; 4618 }; 4619 }; 4620 }; 4621 4622 mdss_dsi0: dsi@ae94000 { 4623 compatible = "qcom,sdm845-dsi-ctrl", 4624 "qcom,mdss-dsi-ctrl"; 4625 reg = <0 0x0ae94000 0 0x400>; 4626 reg-names = "dsi_ctrl"; 4627 4628 interrupt-parent = <&mdss>; 4629 interrupts = <4>; 4630 4631 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 4632 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 4633 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 4634 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 4635 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4636 <&dispcc DISP_CC_MDSS_AXI_CLK>; 4637 clock-names = "byte", 4638 "byte_intf", 4639 "pixel", 4640 "core", 4641 "iface", 4642 "bus"; 4643 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 4644 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; 4645 4646 operating-points-v2 = <&dsi_opp_table>; 4647 power-domains = <&rpmhpd SDM845_CX>; 4648 4649 phys = <&mdss_dsi0_phy>; 4650 4651 status = "disabled"; 4652 4653 #address-cells = <1>; 4654 #size-cells = <0>; 4655 4656 ports { 4657 #address-cells = <1>; 4658 #size-cells = <0>; 4659 4660 port@0 { 4661 reg = <0>; 4662 mdss_dsi0_in: endpoint { 4663 remote-endpoint = <&dpu_intf1_out>; 4664 }; 4665 }; 4666 4667 port@1 { 4668 reg = <1>; 4669 mdss_dsi0_out: endpoint { 4670 }; 4671 }; 4672 }; 4673 }; 4674 4675 mdss_dsi0_phy: phy@ae94400 { 4676 compatible = "qcom,dsi-phy-10nm"; 4677 reg = <0 0x0ae94400 0 0x200>, 4678 <0 0x0ae94600 0 0x280>, 4679 <0 0x0ae94a00 0 0x1e0>; 4680 reg-names = "dsi_phy", 4681 "dsi_phy_lane", 4682 "dsi_pll"; 4683 4684 #clock-cells = <1>; 4685 #phy-cells = <0>; 4686 4687 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4688 <&rpmhcc RPMH_CXO_CLK>; 4689 clock-names = "iface", "ref"; 4690 4691 status = "disabled"; 4692 }; 4693 4694 mdss_dsi1: dsi@ae96000 { 4695 compatible = "qcom,sdm845-dsi-ctrl", 4696 "qcom,mdss-dsi-ctrl"; 4697 reg = <0 0x0ae96000 0 0x400>; 4698 reg-names = "dsi_ctrl"; 4699 4700 interrupt-parent = <&mdss>; 4701 interrupts = <5>; 4702 4703 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 4704 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 4705 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 4706 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 4707 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4708 <&dispcc DISP_CC_MDSS_AXI_CLK>; 4709 clock-names = "byte", 4710 "byte_intf", 4711 "pixel", 4712 "core", 4713 "iface", 4714 "bus"; 4715 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 4716 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>; 4717 4718 operating-points-v2 = <&dsi_opp_table>; 4719 power-domains = <&rpmhpd SDM845_CX>; 4720 4721 phys = <&mdss_dsi1_phy>; 4722 4723 status = "disabled"; 4724 4725 #address-cells = <1>; 4726 #size-cells = <0>; 4727 4728 ports { 4729 #address-cells = <1>; 4730 #size-cells = <0>; 4731 4732 port@0 { 4733 reg = <0>; 4734 mdss_dsi1_in: endpoint { 4735 remote-endpoint = <&dpu_intf2_out>; 4736 }; 4737 }; 4738 4739 port@1 { 4740 reg = <1>; 4741 mdss_dsi1_out: endpoint { 4742 }; 4743 }; 4744 }; 4745 }; 4746 4747 mdss_dsi1_phy: phy@ae96400 { 4748 compatible = "qcom,dsi-phy-10nm"; 4749 reg = <0 0x0ae96400 0 0x200>, 4750 <0 0x0ae96600 0 0x280>, 4751 <0 0x0ae96a00 0 0x10e>; 4752 reg-names = "dsi_phy", 4753 "dsi_phy_lane", 4754 "dsi_pll"; 4755 4756 #clock-cells = <1>; 4757 #phy-cells = <0>; 4758 4759 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4760 <&rpmhcc RPMH_CXO_CLK>; 4761 clock-names = "iface", "ref"; 4762 4763 status = "disabled"; 4764 }; 4765 }; 4766 4767 gpu: gpu@5000000 { 4768 compatible = "qcom,adreno-630.2", "qcom,adreno"; 4769 4770 reg = <0 0x05000000 0 0x40000>, <0 0x509e000 0 0x10>; 4771 reg-names = "kgsl_3d0_reg_memory", "cx_mem"; 4772 4773 /* 4774 * Look ma, no clocks! The GPU clocks and power are 4775 * controlled entirely by the GMU 4776 */ 4777 4778 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 4779 4780 iommus = <&adreno_smmu 0>; 4781 4782 operating-points-v2 = <&gpu_opp_table>; 4783 4784 qcom,gmu = <&gmu>; 4785 4786 interconnects = <&mem_noc MASTER_GFX3D 0 &mem_noc SLAVE_EBI1 0>; 4787 interconnect-names = "gfx-mem"; 4788 4789 status = "disabled"; 4790 4791 gpu_opp_table: opp-table { 4792 compatible = "operating-points-v2"; 4793 4794 opp-710000000 { 4795 opp-hz = /bits/ 64 <710000000>; 4796 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4797 opp-peak-kBps = <7216000>; 4798 }; 4799 4800 opp-675000000 { 4801 opp-hz = /bits/ 64 <675000000>; 4802 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4803 opp-peak-kBps = <7216000>; 4804 }; 4805 4806 opp-596000000 { 4807 opp-hz = /bits/ 64 <596000000>; 4808 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4809 opp-peak-kBps = <6220000>; 4810 }; 4811 4812 opp-520000000 { 4813 opp-hz = /bits/ 64 <520000000>; 4814 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4815 opp-peak-kBps = <6220000>; 4816 }; 4817 4818 opp-414000000 { 4819 opp-hz = /bits/ 64 <414000000>; 4820 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4821 opp-peak-kBps = <4068000>; 4822 }; 4823 4824 opp-342000000 { 4825 opp-hz = /bits/ 64 <342000000>; 4826 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4827 opp-peak-kBps = <2724000>; 4828 }; 4829 4830 opp-257000000 { 4831 opp-hz = /bits/ 64 <257000000>; 4832 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4833 opp-peak-kBps = <1648000>; 4834 }; 4835 }; 4836 }; 4837 4838 adreno_smmu: iommu@5040000 { 4839 compatible = "qcom,sdm845-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2"; 4840 reg = <0 0x05040000 0 0x10000>; 4841 #iommu-cells = <1>; 4842 #global-interrupts = <2>; 4843 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 4844 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 4845 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, 4846 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, 4847 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>, 4848 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>, 4849 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>, 4850 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>, 4851 <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>, 4852 <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>; 4853 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 4854 <&gcc GCC_GPU_CFG_AHB_CLK>; 4855 clock-names = "bus", "iface"; 4856 4857 power-domains = <&gpucc GPU_CX_GDSC>; 4858 }; 4859 4860 gmu: gmu@506a000 { 4861 compatible = "qcom,adreno-gmu-630.2", "qcom,adreno-gmu"; 4862 4863 reg = <0 0x0506a000 0 0x30000>, 4864 <0 0x0b280000 0 0x10000>, 4865 <0 0x0b480000 0 0x10000>; 4866 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; 4867 4868 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 4869 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 4870 interrupt-names = "hfi", "gmu"; 4871 4872 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 4873 <&gpucc GPU_CC_CXO_CLK>, 4874 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 4875 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 4876 clock-names = "gmu", "cxo", "axi", "memnoc"; 4877 4878 power-domains = <&gpucc GPU_CX_GDSC>, 4879 <&gpucc GPU_GX_GDSC>; 4880 power-domain-names = "cx", "gx"; 4881 4882 iommus = <&adreno_smmu 5>; 4883 4884 operating-points-v2 = <&gmu_opp_table>; 4885 4886 status = "disabled"; 4887 4888 gmu_opp_table: opp-table { 4889 compatible = "operating-points-v2"; 4890 4891 opp-400000000 { 4892 opp-hz = /bits/ 64 <400000000>; 4893 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4894 }; 4895 4896 opp-200000000 { 4897 opp-hz = /bits/ 64 <200000000>; 4898 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 4899 }; 4900 }; 4901 }; 4902 4903 dispcc: clock-controller@af00000 { 4904 compatible = "qcom,sdm845-dispcc"; 4905 reg = <0 0x0af00000 0 0x10000>; 4906 clocks = <&rpmhcc RPMH_CXO_CLK>, 4907 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 4908 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, 4909 <&mdss_dsi0_phy 0>, 4910 <&mdss_dsi0_phy 1>, 4911 <&mdss_dsi1_phy 0>, 4912 <&mdss_dsi1_phy 1>, 4913 <&dp_phy 0>, 4914 <&dp_phy 1>; 4915 clock-names = "bi_tcxo", 4916 "gcc_disp_gpll0_clk_src", 4917 "gcc_disp_gpll0_div_clk_src", 4918 "dsi0_phy_pll_out_byteclk", 4919 "dsi0_phy_pll_out_dsiclk", 4920 "dsi1_phy_pll_out_byteclk", 4921 "dsi1_phy_pll_out_dsiclk", 4922 "dp_link_clk_divsel_ten", 4923 "dp_vco_divided_clk_src_mux"; 4924 #clock-cells = <1>; 4925 #reset-cells = <1>; 4926 #power-domain-cells = <1>; 4927 }; 4928 4929 pdc_intc: interrupt-controller@b220000 { 4930 compatible = "qcom,sdm845-pdc", "qcom,pdc"; 4931 reg = <0 0x0b220000 0 0x30000>; 4932 qcom,pdc-ranges = <0 480 94>, <94 609 15>, <115 630 7>; 4933 #interrupt-cells = <2>; 4934 interrupt-parent = <&intc>; 4935 interrupt-controller; 4936 }; 4937 4938 pdc_reset: reset-controller@b2e0000 { 4939 compatible = "qcom,sdm845-pdc-global"; 4940 reg = <0 0x0b2e0000 0 0x20000>; 4941 #reset-cells = <1>; 4942 }; 4943 4944 tsens0: thermal-sensor@c263000 { 4945 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; 4946 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 4947 <0 0x0c222000 0 0x1ff>; /* SROT */ 4948 #qcom,sensors = <13>; 4949 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 4950 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 4951 interrupt-names = "uplow", "critical"; 4952 #thermal-sensor-cells = <1>; 4953 }; 4954 4955 tsens1: thermal-sensor@c265000 { 4956 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; 4957 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 4958 <0 0x0c223000 0 0x1ff>; /* SROT */ 4959 #qcom,sensors = <8>; 4960 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 4961 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 4962 interrupt-names = "uplow", "critical"; 4963 #thermal-sensor-cells = <1>; 4964 }; 4965 4966 aoss_reset: reset-controller@c2a0000 { 4967 compatible = "qcom,sdm845-aoss-cc"; 4968 reg = <0 0x0c2a0000 0 0x31000>; 4969 #reset-cells = <1>; 4970 }; 4971 4972 aoss_qmp: power-management@c300000 { 4973 compatible = "qcom,sdm845-aoss-qmp", "qcom,aoss-qmp"; 4974 reg = <0 0x0c300000 0 0x400>; 4975 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; 4976 mboxes = <&apss_shared 0>; 4977 4978 #clock-cells = <0>; 4979 4980 cx_cdev: cx { 4981 #cooling-cells = <2>; 4982 }; 4983 4984 ebi_cdev: ebi { 4985 #cooling-cells = <2>; 4986 }; 4987 }; 4988 4989 sram@c3f0000 { 4990 compatible = "qcom,sdm845-rpmh-stats"; 4991 reg = <0 0x0c3f0000 0 0x400>; 4992 }; 4993 4994 spmi_bus: spmi@c440000 { 4995 compatible = "qcom,spmi-pmic-arb"; 4996 reg = <0 0x0c440000 0 0x1100>, 4997 <0 0x0c600000 0 0x2000000>, 4998 <0 0x0e600000 0 0x100000>, 4999 <0 0x0e700000 0 0xa0000>, 5000 <0 0x0c40a000 0 0x26000>; 5001 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 5002 interrupt-names = "periph_irq"; 5003 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>; 5004 qcom,ee = <0>; 5005 qcom,channel = <0>; 5006 #address-cells = <2>; 5007 #size-cells = <0>; 5008 interrupt-controller; 5009 #interrupt-cells = <4>; 5010 }; 5011 5012 sram@146bf000 { 5013 compatible = "qcom,sdm845-imem", "syscon", "simple-mfd"; 5014 reg = <0 0x146bf000 0 0x1000>; 5015 5016 #address-cells = <1>; 5017 #size-cells = <1>; 5018 5019 ranges = <0 0 0x146bf000 0x1000>; 5020 5021 pil-reloc@94c { 5022 compatible = "qcom,pil-reloc-info"; 5023 reg = <0x94c 0xc8>; 5024 }; 5025 }; 5026 5027 apps_smmu: iommu@15000000 { 5028 compatible = "qcom,sdm845-smmu-500", "arm,mmu-500"; 5029 reg = <0 0x15000000 0 0x80000>; 5030 #iommu-cells = <2>; 5031 #global-interrupts = <1>; 5032 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 5033 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 5034 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 5035 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 5036 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 5037 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 5038 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 5039 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 5040 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 5041 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 5042 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 5043 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 5044 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 5045 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 5046 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 5047 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 5048 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 5049 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 5050 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 5051 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 5052 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 5053 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 5054 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 5055 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 5056 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 5057 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 5058 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 5059 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 5060 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 5061 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 5062 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 5063 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 5064 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 5065 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 5066 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 5067 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 5068 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 5069 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 5070 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 5071 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 5072 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 5073 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 5074 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 5075 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 5076 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 5077 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 5078 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 5079 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 5080 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 5081 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 5082 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 5083 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 5084 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 5085 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 5086 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 5087 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 5088 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 5089 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 5090 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 5091 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 5092 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 5093 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 5094 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 5095 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 5096 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>; 5097 }; 5098 5099 lpasscc: clock-controller@17014000 { 5100 compatible = "qcom,sdm845-lpasscc"; 5101 reg = <0 0x17014000 0 0x1f004>, <0 0x17300000 0 0x200>; 5102 reg-names = "cc", "qdsp6ss"; 5103 #clock-cells = <1>; 5104 status = "disabled"; 5105 }; 5106 5107 gladiator_noc: interconnect@17900000 { 5108 compatible = "qcom,sdm845-gladiator-noc"; 5109 reg = <0 0x17900000 0 0xd080>; 5110 #interconnect-cells = <2>; 5111 qcom,bcm-voters = <&apps_bcm_voter>; 5112 }; 5113 5114 watchdog@17980000 { 5115 compatible = "qcom,apss-wdt-sdm845", "qcom,kpss-wdt"; 5116 reg = <0 0x17980000 0 0x1000>; 5117 clocks = <&sleep_clk>; 5118 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 5119 }; 5120 5121 apss_shared: mailbox@17990000 { 5122 compatible = "qcom,sdm845-apss-shared"; 5123 reg = <0 0x17990000 0 0x1000>; 5124 #mbox-cells = <1>; 5125 }; 5126 5127 apps_rsc: rsc@179c0000 { 5128 label = "apps_rsc"; 5129 compatible = "qcom,rpmh-rsc"; 5130 reg = <0 0x179c0000 0 0x10000>, 5131 <0 0x179d0000 0 0x10000>, 5132 <0 0x179e0000 0 0x10000>; 5133 reg-names = "drv-0", "drv-1", "drv-2"; 5134 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 5135 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 5136 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 5137 qcom,tcs-offset = <0xd00>; 5138 qcom,drv-id = <2>; 5139 qcom,tcs-config = <ACTIVE_TCS 2>, 5140 <SLEEP_TCS 3>, 5141 <WAKE_TCS 3>, 5142 <CONTROL_TCS 1>; 5143 power-domains = <&CLUSTER_PD>; 5144 5145 apps_bcm_voter: bcm-voter { 5146 compatible = "qcom,bcm-voter"; 5147 }; 5148 5149 rpmhcc: clock-controller { 5150 compatible = "qcom,sdm845-rpmh-clk"; 5151 #clock-cells = <1>; 5152 clock-names = "xo"; 5153 clocks = <&xo_board>; 5154 }; 5155 5156 rpmhpd: power-controller { 5157 compatible = "qcom,sdm845-rpmhpd"; 5158 #power-domain-cells = <1>; 5159 operating-points-v2 = <&rpmhpd_opp_table>; 5160 5161 rpmhpd_opp_table: opp-table { 5162 compatible = "operating-points-v2"; 5163 5164 rpmhpd_opp_ret: opp1 { 5165 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 5166 }; 5167 5168 rpmhpd_opp_min_svs: opp2 { 5169 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 5170 }; 5171 5172 rpmhpd_opp_low_svs: opp3 { 5173 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 5174 }; 5175 5176 rpmhpd_opp_svs: opp4 { 5177 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 5178 }; 5179 5180 rpmhpd_opp_svs_l1: opp5 { 5181 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 5182 }; 5183 5184 rpmhpd_opp_nom: opp6 { 5185 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 5186 }; 5187 5188 rpmhpd_opp_nom_l1: opp7 { 5189 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 5190 }; 5191 5192 rpmhpd_opp_nom_l2: opp8 { 5193 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 5194 }; 5195 5196 rpmhpd_opp_turbo: opp9 { 5197 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 5198 }; 5199 5200 rpmhpd_opp_turbo_l1: opp10 { 5201 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 5202 }; 5203 }; 5204 }; 5205 }; 5206 5207 intc: interrupt-controller@17a00000 { 5208 compatible = "arm,gic-v3"; 5209 #address-cells = <2>; 5210 #size-cells = <2>; 5211 ranges; 5212 #interrupt-cells = <3>; 5213 interrupt-controller; 5214 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 5215 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 5216 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 5217 5218 msi-controller@17a40000 { 5219 compatible = "arm,gic-v3-its"; 5220 msi-controller; 5221 #msi-cells = <1>; 5222 reg = <0 0x17a40000 0 0x20000>; 5223 status = "disabled"; 5224 }; 5225 }; 5226 5227 slimbam: dma-controller@17184000 { 5228 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 5229 qcom,controlled-remotely; 5230 reg = <0 0x17184000 0 0x2a000>; 5231 num-channels = <31>; 5232 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 5233 #dma-cells = <1>; 5234 qcom,ee = <1>; 5235 qcom,num-ees = <2>; 5236 iommus = <&apps_smmu 0x1806 0x0>; 5237 }; 5238 5239 timer@17c90000 { 5240 #address-cells = <1>; 5241 #size-cells = <1>; 5242 ranges = <0 0 0 0x20000000>; 5243 compatible = "arm,armv7-timer-mem"; 5244 reg = <0 0x17c90000 0 0x1000>; 5245 5246 frame@17ca0000 { 5247 frame-number = <0>; 5248 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 5249 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 5250 reg = <0x17ca0000 0x1000>, 5251 <0x17cb0000 0x1000>; 5252 }; 5253 5254 frame@17cc0000 { 5255 frame-number = <1>; 5256 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 5257 reg = <0x17cc0000 0x1000>; 5258 status = "disabled"; 5259 }; 5260 5261 frame@17cd0000 { 5262 frame-number = <2>; 5263 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 5264 reg = <0x17cd0000 0x1000>; 5265 status = "disabled"; 5266 }; 5267 5268 frame@17ce0000 { 5269 frame-number = <3>; 5270 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 5271 reg = <0x17ce0000 0x1000>; 5272 status = "disabled"; 5273 }; 5274 5275 frame@17cf0000 { 5276 frame-number = <4>; 5277 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 5278 reg = <0x17cf0000 0x1000>; 5279 status = "disabled"; 5280 }; 5281 5282 frame@17d00000 { 5283 frame-number = <5>; 5284 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 5285 reg = <0x17d00000 0x1000>; 5286 status = "disabled"; 5287 }; 5288 5289 frame@17d10000 { 5290 frame-number = <6>; 5291 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 5292 reg = <0x17d10000 0x1000>; 5293 status = "disabled"; 5294 }; 5295 }; 5296 5297 osm_l3: interconnect@17d41000 { 5298 compatible = "qcom,sdm845-osm-l3", "qcom,osm-l3"; 5299 reg = <0 0x17d41000 0 0x1400>; 5300 5301 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 5302 clock-names = "xo", "alternate"; 5303 5304 #interconnect-cells = <1>; 5305 }; 5306 5307 cpufreq_hw: cpufreq@17d43000 { 5308 compatible = "qcom,sdm845-cpufreq-hw", "qcom,cpufreq-hw"; 5309 reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>; 5310 reg-names = "freq-domain0", "freq-domain1"; 5311 5312 interrupts-extended = <&lmh_cluster0 0>, <&lmh_cluster1 0>; 5313 5314 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 5315 clock-names = "xo", "alternate"; 5316 5317 #freq-domain-cells = <1>; 5318 #clock-cells = <1>; 5319 }; 5320 5321 wifi: wifi@18800000 { 5322 compatible = "qcom,wcn3990-wifi"; 5323 status = "disabled"; 5324 reg = <0 0x18800000 0 0x800000>; 5325 reg-names = "membase"; 5326 memory-region = <&wlan_msa_mem>; 5327 clock-names = "cxo_ref_clk_pin"; 5328 clocks = <&rpmhcc RPMH_RF_CLK2>; 5329 interrupts = 5330 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 5331 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 5332 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 5333 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 5334 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 5335 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 5336 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 5337 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 5338 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 5339 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 5340 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 5341 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 5342 iommus = <&apps_smmu 0x0040 0x1>; 5343 }; 5344 }; 5345 5346 sound: sound { 5347 }; 5348 5349 thermal-zones { 5350 cpu0-thermal { 5351 polling-delay-passive = <250>; 5352 polling-delay = <1000>; 5353 5354 thermal-sensors = <&tsens0 1>; 5355 5356 trips { 5357 cpu0_alert0: trip-point0 { 5358 temperature = <90000>; 5359 hysteresis = <2000>; 5360 type = "passive"; 5361 }; 5362 5363 cpu0_alert1: trip-point1 { 5364 temperature = <95000>; 5365 hysteresis = <2000>; 5366 type = "passive"; 5367 }; 5368 5369 cpu0_crit: cpu-crit { 5370 temperature = <110000>; 5371 hysteresis = <1000>; 5372 type = "critical"; 5373 }; 5374 }; 5375 }; 5376 5377 cpu1-thermal { 5378 polling-delay-passive = <250>; 5379 polling-delay = <1000>; 5380 5381 thermal-sensors = <&tsens0 2>; 5382 5383 trips { 5384 cpu1_alert0: trip-point0 { 5385 temperature = <90000>; 5386 hysteresis = <2000>; 5387 type = "passive"; 5388 }; 5389 5390 cpu1_alert1: trip-point1 { 5391 temperature = <95000>; 5392 hysteresis = <2000>; 5393 type = "passive"; 5394 }; 5395 5396 cpu1_crit: cpu-crit { 5397 temperature = <110000>; 5398 hysteresis = <1000>; 5399 type = "critical"; 5400 }; 5401 }; 5402 }; 5403 5404 cpu2-thermal { 5405 polling-delay-passive = <250>; 5406 polling-delay = <1000>; 5407 5408 thermal-sensors = <&tsens0 3>; 5409 5410 trips { 5411 cpu2_alert0: trip-point0 { 5412 temperature = <90000>; 5413 hysteresis = <2000>; 5414 type = "passive"; 5415 }; 5416 5417 cpu2_alert1: trip-point1 { 5418 temperature = <95000>; 5419 hysteresis = <2000>; 5420 type = "passive"; 5421 }; 5422 5423 cpu2_crit: cpu-crit { 5424 temperature = <110000>; 5425 hysteresis = <1000>; 5426 type = "critical"; 5427 }; 5428 }; 5429 }; 5430 5431 cpu3-thermal { 5432 polling-delay-passive = <250>; 5433 polling-delay = <1000>; 5434 5435 thermal-sensors = <&tsens0 4>; 5436 5437 trips { 5438 cpu3_alert0: trip-point0 { 5439 temperature = <90000>; 5440 hysteresis = <2000>; 5441 type = "passive"; 5442 }; 5443 5444 cpu3_alert1: trip-point1 { 5445 temperature = <95000>; 5446 hysteresis = <2000>; 5447 type = "passive"; 5448 }; 5449 5450 cpu3_crit: cpu-crit { 5451 temperature = <110000>; 5452 hysteresis = <1000>; 5453 type = "critical"; 5454 }; 5455 }; 5456 }; 5457 5458 cpu4-thermal { 5459 polling-delay-passive = <250>; 5460 polling-delay = <1000>; 5461 5462 thermal-sensors = <&tsens0 7>; 5463 5464 trips { 5465 cpu4_alert0: trip-point0 { 5466 temperature = <90000>; 5467 hysteresis = <2000>; 5468 type = "passive"; 5469 }; 5470 5471 cpu4_alert1: trip-point1 { 5472 temperature = <95000>; 5473 hysteresis = <2000>; 5474 type = "passive"; 5475 }; 5476 5477 cpu4_crit: cpu-crit { 5478 temperature = <110000>; 5479 hysteresis = <1000>; 5480 type = "critical"; 5481 }; 5482 }; 5483 }; 5484 5485 cpu5-thermal { 5486 polling-delay-passive = <250>; 5487 polling-delay = <1000>; 5488 5489 thermal-sensors = <&tsens0 8>; 5490 5491 trips { 5492 cpu5_alert0: trip-point0 { 5493 temperature = <90000>; 5494 hysteresis = <2000>; 5495 type = "passive"; 5496 }; 5497 5498 cpu5_alert1: trip-point1 { 5499 temperature = <95000>; 5500 hysteresis = <2000>; 5501 type = "passive"; 5502 }; 5503 5504 cpu5_crit: cpu-crit { 5505 temperature = <110000>; 5506 hysteresis = <1000>; 5507 type = "critical"; 5508 }; 5509 }; 5510 }; 5511 5512 cpu6-thermal { 5513 polling-delay-passive = <250>; 5514 polling-delay = <1000>; 5515 5516 thermal-sensors = <&tsens0 9>; 5517 5518 trips { 5519 cpu6_alert0: trip-point0 { 5520 temperature = <90000>; 5521 hysteresis = <2000>; 5522 type = "passive"; 5523 }; 5524 5525 cpu6_alert1: trip-point1 { 5526 temperature = <95000>; 5527 hysteresis = <2000>; 5528 type = "passive"; 5529 }; 5530 5531 cpu6_crit: cpu-crit { 5532 temperature = <110000>; 5533 hysteresis = <1000>; 5534 type = "critical"; 5535 }; 5536 }; 5537 }; 5538 5539 cpu7-thermal { 5540 polling-delay-passive = <250>; 5541 polling-delay = <1000>; 5542 5543 thermal-sensors = <&tsens0 10>; 5544 5545 trips { 5546 cpu7_alert0: trip-point0 { 5547 temperature = <90000>; 5548 hysteresis = <2000>; 5549 type = "passive"; 5550 }; 5551 5552 cpu7_alert1: trip-point1 { 5553 temperature = <95000>; 5554 hysteresis = <2000>; 5555 type = "passive"; 5556 }; 5557 5558 cpu7_crit: cpu-crit { 5559 temperature = <110000>; 5560 hysteresis = <1000>; 5561 type = "critical"; 5562 }; 5563 }; 5564 }; 5565 5566 aoss0-thermal { 5567 polling-delay-passive = <250>; 5568 polling-delay = <1000>; 5569 5570 thermal-sensors = <&tsens0 0>; 5571 5572 trips { 5573 aoss0_alert0: trip-point0 { 5574 temperature = <90000>; 5575 hysteresis = <2000>; 5576 type = "hot"; 5577 }; 5578 }; 5579 }; 5580 5581 cluster0-thermal { 5582 polling-delay-passive = <250>; 5583 polling-delay = <1000>; 5584 5585 thermal-sensors = <&tsens0 5>; 5586 5587 trips { 5588 cluster0_alert0: trip-point0 { 5589 temperature = <90000>; 5590 hysteresis = <2000>; 5591 type = "hot"; 5592 }; 5593 cluster0_crit: cluster0_crit { 5594 temperature = <110000>; 5595 hysteresis = <2000>; 5596 type = "critical"; 5597 }; 5598 }; 5599 }; 5600 5601 cluster1-thermal { 5602 polling-delay-passive = <250>; 5603 polling-delay = <1000>; 5604 5605 thermal-sensors = <&tsens0 6>; 5606 5607 trips { 5608 cluster1_alert0: trip-point0 { 5609 temperature = <90000>; 5610 hysteresis = <2000>; 5611 type = "hot"; 5612 }; 5613 cluster1_crit: cluster1_crit { 5614 temperature = <110000>; 5615 hysteresis = <2000>; 5616 type = "critical"; 5617 }; 5618 }; 5619 }; 5620 5621 gpu-top-thermal { 5622 polling-delay-passive = <250>; 5623 polling-delay = <1000>; 5624 5625 thermal-sensors = <&tsens0 11>; 5626 5627 trips { 5628 gpu1_alert0: trip-point0 { 5629 temperature = <90000>; 5630 hysteresis = <2000>; 5631 type = "hot"; 5632 }; 5633 }; 5634 }; 5635 5636 gpu-bottom-thermal { 5637 polling-delay-passive = <250>; 5638 polling-delay = <1000>; 5639 5640 thermal-sensors = <&tsens0 12>; 5641 5642 trips { 5643 gpu2_alert0: trip-point0 { 5644 temperature = <90000>; 5645 hysteresis = <2000>; 5646 type = "hot"; 5647 }; 5648 }; 5649 }; 5650 5651 aoss1-thermal { 5652 polling-delay-passive = <250>; 5653 polling-delay = <1000>; 5654 5655 thermal-sensors = <&tsens1 0>; 5656 5657 trips { 5658 aoss1_alert0: trip-point0 { 5659 temperature = <90000>; 5660 hysteresis = <2000>; 5661 type = "hot"; 5662 }; 5663 }; 5664 }; 5665 5666 q6-modem-thermal { 5667 polling-delay-passive = <250>; 5668 polling-delay = <1000>; 5669 5670 thermal-sensors = <&tsens1 1>; 5671 5672 trips { 5673 q6_modem_alert0: trip-point0 { 5674 temperature = <90000>; 5675 hysteresis = <2000>; 5676 type = "hot"; 5677 }; 5678 }; 5679 }; 5680 5681 mem-thermal { 5682 polling-delay-passive = <250>; 5683 polling-delay = <1000>; 5684 5685 thermal-sensors = <&tsens1 2>; 5686 5687 trips { 5688 mem_alert0: trip-point0 { 5689 temperature = <90000>; 5690 hysteresis = <2000>; 5691 type = "hot"; 5692 }; 5693 }; 5694 }; 5695 5696 wlan-thermal { 5697 polling-delay-passive = <250>; 5698 polling-delay = <1000>; 5699 5700 thermal-sensors = <&tsens1 3>; 5701 5702 trips { 5703 wlan_alert0: trip-point0 { 5704 temperature = <90000>; 5705 hysteresis = <2000>; 5706 type = "hot"; 5707 }; 5708 }; 5709 }; 5710 5711 q6-hvx-thermal { 5712 polling-delay-passive = <250>; 5713 polling-delay = <1000>; 5714 5715 thermal-sensors = <&tsens1 4>; 5716 5717 trips { 5718 q6_hvx_alert0: trip-point0 { 5719 temperature = <90000>; 5720 hysteresis = <2000>; 5721 type = "hot"; 5722 }; 5723 }; 5724 }; 5725 5726 camera-thermal { 5727 polling-delay-passive = <250>; 5728 polling-delay = <1000>; 5729 5730 thermal-sensors = <&tsens1 5>; 5731 5732 trips { 5733 camera_alert0: trip-point0 { 5734 temperature = <90000>; 5735 hysteresis = <2000>; 5736 type = "hot"; 5737 }; 5738 }; 5739 }; 5740 5741 video-thermal { 5742 polling-delay-passive = <250>; 5743 polling-delay = <1000>; 5744 5745 thermal-sensors = <&tsens1 6>; 5746 5747 trips { 5748 video_alert0: trip-point0 { 5749 temperature = <90000>; 5750 hysteresis = <2000>; 5751 type = "hot"; 5752 }; 5753 }; 5754 }; 5755 5756 modem-thermal { 5757 polling-delay-passive = <250>; 5758 polling-delay = <1000>; 5759 5760 thermal-sensors = <&tsens1 7>; 5761 5762 trips { 5763 modem_alert0: trip-point0 { 5764 temperature = <90000>; 5765 hysteresis = <2000>; 5766 type = "hot"; 5767 }; 5768 }; 5769 }; 5770 }; 5771 5772 timer { 5773 compatible = "arm,armv8-timer"; 5774 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 5775 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 5776 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 5777 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 5778 }; 5779}; 5780