1// SPDX-License-Identifier: GPL-2.0 2/* 3 * SDM845 SoC device tree source 4 * 5 * Copyright (c) 2018, The Linux Foundation. All rights reserved. 6 */ 7 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9 10/ { 11 interrupt-parent = <&intc>; 12 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 chosen { }; 17 18 memory@80000000 { 19 device_type = "memory"; 20 /* We expect the bootloader to fill in the size */ 21 reg = <0 0x80000000 0 0>; 22 }; 23 24 reserved-memory { 25 #address-cells = <2>; 26 #size-cells = <2>; 27 ranges; 28 29 memory@85fc0000 { 30 reg = <0 0x85fc0000 0 0x20000>; 31 no-map; 32 }; 33 34 memory@85fe0000 { 35 compatible = "qcom,cmd-db"; 36 reg = <0x0 0x85fe0000 0x0 0x20000>; 37 no-map; 38 }; 39 40 smem_mem: memory@86000000 { 41 reg = <0x0 0x86000000 0x0 0x200000>; 42 no-map; 43 }; 44 45 memory@86200000 { 46 reg = <0 0x86200000 0 0x2d00000>; 47 no-map; 48 }; 49 }; 50 51 cpus { 52 #address-cells = <2>; 53 #size-cells = <0>; 54 55 CPU0: cpu@0 { 56 device_type = "cpu"; 57 compatible = "qcom,kryo385"; 58 reg = <0x0 0x0>; 59 enable-method = "psci"; 60 next-level-cache = <&L2_0>; 61 L2_0: l2-cache { 62 compatible = "cache"; 63 next-level-cache = <&L3_0>; 64 L3_0: l3-cache { 65 compatible = "cache"; 66 }; 67 }; 68 }; 69 70 CPU1: cpu@100 { 71 device_type = "cpu"; 72 compatible = "qcom,kryo385"; 73 reg = <0x0 0x100>; 74 enable-method = "psci"; 75 next-level-cache = <&L2_100>; 76 L2_100: l2-cache { 77 compatible = "cache"; 78 next-level-cache = <&L3_0>; 79 }; 80 }; 81 82 CPU2: cpu@200 { 83 device_type = "cpu"; 84 compatible = "qcom,kryo385"; 85 reg = <0x0 0x200>; 86 enable-method = "psci"; 87 next-level-cache = <&L2_200>; 88 L2_200: l2-cache { 89 compatible = "cache"; 90 next-level-cache = <&L3_0>; 91 }; 92 }; 93 94 CPU3: cpu@300 { 95 device_type = "cpu"; 96 compatible = "qcom,kryo385"; 97 reg = <0x0 0x300>; 98 enable-method = "psci"; 99 next-level-cache = <&L2_300>; 100 L2_300: l2-cache { 101 compatible = "cache"; 102 next-level-cache = <&L3_0>; 103 }; 104 }; 105 106 CPU4: cpu@400 { 107 device_type = "cpu"; 108 compatible = "qcom,kryo385"; 109 reg = <0x0 0x400>; 110 enable-method = "psci"; 111 next-level-cache = <&L2_400>; 112 L2_400: l2-cache { 113 compatible = "cache"; 114 next-level-cache = <&L3_0>; 115 }; 116 }; 117 118 CPU5: cpu@500 { 119 device_type = "cpu"; 120 compatible = "qcom,kryo385"; 121 reg = <0x0 0x500>; 122 enable-method = "psci"; 123 next-level-cache = <&L2_500>; 124 L2_500: l2-cache { 125 compatible = "cache"; 126 next-level-cache = <&L3_0>; 127 }; 128 }; 129 130 CPU6: cpu@600 { 131 device_type = "cpu"; 132 compatible = "qcom,kryo385"; 133 reg = <0x0 0x600>; 134 enable-method = "psci"; 135 next-level-cache = <&L2_600>; 136 L2_600: l2-cache { 137 compatible = "cache"; 138 next-level-cache = <&L3_0>; 139 }; 140 }; 141 142 CPU7: cpu@700 { 143 device_type = "cpu"; 144 compatible = "qcom,kryo385"; 145 reg = <0x0 0x700>; 146 enable-method = "psci"; 147 next-level-cache = <&L2_700>; 148 L2_700: l2-cache { 149 compatible = "cache"; 150 next-level-cache = <&L3_0>; 151 }; 152 }; 153 }; 154 155 timer { 156 compatible = "arm,armv8-timer"; 157 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 158 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 159 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 160 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 161 }; 162 163 clocks { 164 xo_board: xo-board { 165 compatible = "fixed-clock"; 166 #clock-cells = <0>; 167 clock-frequency = <38400000>; 168 clock-output-names = "xo_board"; 169 }; 170 171 sleep_clk: sleep-clk { 172 compatible = "fixed-clock"; 173 #clock-cells = <0>; 174 clock-frequency = <32764>; 175 }; 176 }; 177 178 tcsr_mutex: hwlock { 179 compatible = "qcom,tcsr-mutex"; 180 syscon = <&tcsr_mutex_regs 0 0x1000>; 181 #hwlock-cells = <1>; 182 }; 183 184 smem { 185 compatible = "qcom,smem"; 186 memory-region = <&smem_mem>; 187 hwlocks = <&tcsr_mutex 3>; 188 }; 189 190 psci { 191 compatible = "arm,psci-1.0"; 192 method = "smc"; 193 }; 194 195 soc: soc { 196 #address-cells = <1>; 197 #size-cells = <1>; 198 ranges = <0 0 0 0xffffffff>; 199 compatible = "simple-bus"; 200 201 gcc: clock-controller@100000 { 202 compatible = "qcom,gcc-sdm845"; 203 reg = <0x100000 0x1f0000>; 204 #clock-cells = <1>; 205 #reset-cells = <1>; 206 #power-domain-cells = <1>; 207 }; 208 209 tcsr_mutex_regs: syscon@1f40000 { 210 compatible = "syscon"; 211 reg = <0x1f40000 0x40000>; 212 }; 213 214 tlmm: pinctrl@3400000 { 215 compatible = "qcom,sdm845-pinctrl"; 216 reg = <0x03400000 0xc00000>; 217 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 218 gpio-controller; 219 #gpio-cells = <2>; 220 interrupt-controller; 221 #interrupt-cells = <2>; 222 }; 223 224 spmi_bus: spmi@c440000 { 225 compatible = "qcom,spmi-pmic-arb"; 226 reg = <0xc440000 0x1100>, 227 <0xc600000 0x2000000>, 228 <0xe600000 0x100000>, 229 <0xe700000 0xa0000>, 230 <0xc40a000 0x26000>; 231 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 232 interrupt-names = "periph_irq"; 233 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>; 234 qcom,ee = <0>; 235 qcom,channel = <0>; 236 #address-cells = <2>; 237 #size-cells = <0>; 238 interrupt-controller; 239 #interrupt-cells = <4>; 240 cell-index = <0>; 241 }; 242 243 apss_shared: mailbox@17990000 { 244 compatible = "qcom,sdm845-apss-shared"; 245 reg = <0x17990000 0x1000>; 246 #mbox-cells = <1>; 247 }; 248 249 intc: interrupt-controller@17a00000 { 250 compatible = "arm,gic-v3"; 251 #address-cells = <1>; 252 #size-cells = <1>; 253 ranges; 254 #interrupt-cells = <3>; 255 interrupt-controller; 256 reg = <0x17a00000 0x10000>, /* GICD */ 257 <0x17a60000 0x100000>; /* GICR * 8 */ 258 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 259 260 gic-its@17a40000 { 261 compatible = "arm,gic-v3-its"; 262 msi-controller; 263 #msi-cells = <1>; 264 reg = <0x17a40000 0x20000>; 265 status = "disabled"; 266 }; 267 }; 268 269 timer@17c90000 { 270 #address-cells = <1>; 271 #size-cells = <1>; 272 ranges; 273 compatible = "arm,armv7-timer-mem"; 274 reg = <0x17c90000 0x1000>; 275 276 frame@17ca0000 { 277 frame-number = <0>; 278 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 279 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 280 reg = <0x17ca0000 0x1000>, 281 <0x17cb0000 0x1000>; 282 }; 283 284 frame@17cc0000 { 285 frame-number = <1>; 286 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 287 reg = <0x17cc0000 0x1000>; 288 status = "disabled"; 289 }; 290 291 frame@17cd0000 { 292 frame-number = <2>; 293 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 294 reg = <0x17cd0000 0x1000>; 295 status = "disabled"; 296 }; 297 298 frame@17ce0000 { 299 frame-number = <3>; 300 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 301 reg = <0x17ce0000 0x1000>; 302 status = "disabled"; 303 }; 304 305 frame@17cf0000 { 306 frame-number = <4>; 307 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 308 reg = <0x17cf0000 0x1000>; 309 status = "disabled"; 310 }; 311 312 frame@17d00000 { 313 frame-number = <5>; 314 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 315 reg = <0x17d00000 0x1000>; 316 status = "disabled"; 317 }; 318 319 frame@17d10000 { 320 frame-number = <6>; 321 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 322 reg = <0x17d10000 0x1000>; 323 status = "disabled"; 324 }; 325 }; 326 }; 327}; 328