1// SPDX-License-Identifier: GPL-2.0 2/* 3 * SDM845 SoC device tree source 4 * 5 * Copyright (c) 2018, The Linux Foundation. All rights reserved. 6 */ 7 8#include <dt-bindings/clock/qcom,dispcc-sdm845.h> 9#include <dt-bindings/clock/qcom,gcc-sdm845.h> 10#include <dt-bindings/clock/qcom,rpmh.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/phy/phy-qcom-qusb2.h> 13#include <dt-bindings/reset/qcom,sdm845-aoss.h> 14#include <dt-bindings/soc/qcom,rpmh-rsc.h> 15 16/ { 17 interrupt-parent = <&intc>; 18 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 aliases { 23 i2c0 = &i2c0; 24 i2c1 = &i2c1; 25 i2c2 = &i2c2; 26 i2c3 = &i2c3; 27 i2c4 = &i2c4; 28 i2c5 = &i2c5; 29 i2c6 = &i2c6; 30 i2c7 = &i2c7; 31 i2c8 = &i2c8; 32 i2c9 = &i2c9; 33 i2c10 = &i2c10; 34 i2c11 = &i2c11; 35 i2c12 = &i2c12; 36 i2c13 = &i2c13; 37 i2c14 = &i2c14; 38 i2c15 = &i2c15; 39 spi0 = &spi0; 40 spi1 = &spi1; 41 spi2 = &spi2; 42 spi3 = &spi3; 43 spi4 = &spi4; 44 spi5 = &spi5; 45 spi6 = &spi6; 46 spi7 = &spi7; 47 spi8 = &spi8; 48 spi9 = &spi9; 49 spi10 = &spi10; 50 spi11 = &spi11; 51 spi12 = &spi12; 52 spi13 = &spi13; 53 spi14 = &spi14; 54 spi15 = &spi15; 55 }; 56 57 chosen { }; 58 59 memory@80000000 { 60 device_type = "memory"; 61 /* We expect the bootloader to fill in the size */ 62 reg = <0 0x80000000 0 0>; 63 }; 64 65 reserved-memory { 66 #address-cells = <2>; 67 #size-cells = <2>; 68 ranges; 69 70 memory@85fc0000 { 71 reg = <0 0x85fc0000 0 0x20000>; 72 no-map; 73 }; 74 75 memory@85fe0000 { 76 compatible = "qcom,cmd-db"; 77 reg = <0x0 0x85fe0000 0x0 0x20000>; 78 no-map; 79 }; 80 81 smem_mem: memory@86000000 { 82 reg = <0x0 0x86000000 0x0 0x200000>; 83 no-map; 84 }; 85 86 memory@86200000 { 87 reg = <0 0x86200000 0 0x2d00000>; 88 no-map; 89 }; 90 }; 91 92 cpus { 93 #address-cells = <2>; 94 #size-cells = <0>; 95 96 CPU0: cpu@0 { 97 device_type = "cpu"; 98 compatible = "qcom,kryo385"; 99 reg = <0x0 0x0>; 100 enable-method = "psci"; 101 next-level-cache = <&L2_0>; 102 L2_0: l2-cache { 103 compatible = "cache"; 104 next-level-cache = <&L3_0>; 105 L3_0: l3-cache { 106 compatible = "cache"; 107 }; 108 }; 109 }; 110 111 CPU1: cpu@100 { 112 device_type = "cpu"; 113 compatible = "qcom,kryo385"; 114 reg = <0x0 0x100>; 115 enable-method = "psci"; 116 next-level-cache = <&L2_100>; 117 L2_100: l2-cache { 118 compatible = "cache"; 119 next-level-cache = <&L3_0>; 120 }; 121 }; 122 123 CPU2: cpu@200 { 124 device_type = "cpu"; 125 compatible = "qcom,kryo385"; 126 reg = <0x0 0x200>; 127 enable-method = "psci"; 128 next-level-cache = <&L2_200>; 129 L2_200: l2-cache { 130 compatible = "cache"; 131 next-level-cache = <&L3_0>; 132 }; 133 }; 134 135 CPU3: cpu@300 { 136 device_type = "cpu"; 137 compatible = "qcom,kryo385"; 138 reg = <0x0 0x300>; 139 enable-method = "psci"; 140 next-level-cache = <&L2_300>; 141 L2_300: l2-cache { 142 compatible = "cache"; 143 next-level-cache = <&L3_0>; 144 }; 145 }; 146 147 CPU4: cpu@400 { 148 device_type = "cpu"; 149 compatible = "qcom,kryo385"; 150 reg = <0x0 0x400>; 151 enable-method = "psci"; 152 next-level-cache = <&L2_400>; 153 L2_400: l2-cache { 154 compatible = "cache"; 155 next-level-cache = <&L3_0>; 156 }; 157 }; 158 159 CPU5: cpu@500 { 160 device_type = "cpu"; 161 compatible = "qcom,kryo385"; 162 reg = <0x0 0x500>; 163 enable-method = "psci"; 164 next-level-cache = <&L2_500>; 165 L2_500: l2-cache { 166 compatible = "cache"; 167 next-level-cache = <&L3_0>; 168 }; 169 }; 170 171 CPU6: cpu@600 { 172 device_type = "cpu"; 173 compatible = "qcom,kryo385"; 174 reg = <0x0 0x600>; 175 enable-method = "psci"; 176 next-level-cache = <&L2_600>; 177 L2_600: l2-cache { 178 compatible = "cache"; 179 next-level-cache = <&L3_0>; 180 }; 181 }; 182 183 CPU7: cpu@700 { 184 device_type = "cpu"; 185 compatible = "qcom,kryo385"; 186 reg = <0x0 0x700>; 187 enable-method = "psci"; 188 next-level-cache = <&L2_700>; 189 L2_700: l2-cache { 190 compatible = "cache"; 191 next-level-cache = <&L3_0>; 192 }; 193 }; 194 }; 195 196 pmu { 197 compatible = "arm,armv8-pmuv3"; 198 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; 199 }; 200 201 timer { 202 compatible = "arm,armv8-timer"; 203 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 204 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 205 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 206 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 207 }; 208 209 clocks { 210 xo_board: xo-board { 211 compatible = "fixed-clock"; 212 #clock-cells = <0>; 213 clock-frequency = <38400000>; 214 clock-output-names = "xo_board"; 215 }; 216 217 sleep_clk: sleep-clk { 218 compatible = "fixed-clock"; 219 #clock-cells = <0>; 220 clock-frequency = <32764>; 221 }; 222 }; 223 224 tcsr_mutex: hwlock { 225 compatible = "qcom,tcsr-mutex"; 226 syscon = <&tcsr_mutex_regs 0 0x1000>; 227 #hwlock-cells = <1>; 228 }; 229 230 smem { 231 compatible = "qcom,smem"; 232 memory-region = <&smem_mem>; 233 hwlocks = <&tcsr_mutex 3>; 234 }; 235 236 smp2p-cdsp { 237 compatible = "qcom,smp2p"; 238 qcom,smem = <94>, <432>; 239 240 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; 241 242 mboxes = <&apss_shared 6>; 243 244 qcom,local-pid = <0>; 245 qcom,remote-pid = <5>; 246 247 cdsp_smp2p_out: master-kernel { 248 qcom,entry-name = "master-kernel"; 249 #qcom,smem-state-cells = <1>; 250 }; 251 252 cdsp_smp2p_in: slave-kernel { 253 qcom,entry-name = "slave-kernel"; 254 255 interrupt-controller; 256 #interrupt-cells = <2>; 257 }; 258 }; 259 260 smp2p-lpass { 261 compatible = "qcom,smp2p"; 262 qcom,smem = <443>, <429>; 263 264 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 265 266 mboxes = <&apss_shared 10>; 267 268 qcom,local-pid = <0>; 269 qcom,remote-pid = <2>; 270 271 adsp_smp2p_out: master-kernel { 272 qcom,entry-name = "master-kernel"; 273 #qcom,smem-state-cells = <1>; 274 }; 275 276 adsp_smp2p_in: slave-kernel { 277 qcom,entry-name = "slave-kernel"; 278 279 interrupt-controller; 280 #interrupt-cells = <2>; 281 }; 282 }; 283 284 smp2p-mpss { 285 compatible = "qcom,smp2p"; 286 qcom,smem = <435>, <428>; 287 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 288 mboxes = <&apss_shared 14>; 289 qcom,local-pid = <0>; 290 qcom,remote-pid = <1>; 291 292 modem_smp2p_out: master-kernel { 293 qcom,entry-name = "master-kernel"; 294 #qcom,smem-state-cells = <1>; 295 }; 296 297 modem_smp2p_in: slave-kernel { 298 qcom,entry-name = "slave-kernel"; 299 interrupt-controller; 300 #interrupt-cells = <2>; 301 }; 302 }; 303 304 smp2p-slpi { 305 compatible = "qcom,smp2p"; 306 qcom,smem = <481>, <430>; 307 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>; 308 mboxes = <&apss_shared 26>; 309 qcom,local-pid = <0>; 310 qcom,remote-pid = <3>; 311 312 slpi_smp2p_out: master-kernel { 313 qcom,entry-name = "master-kernel"; 314 #qcom,smem-state-cells = <1>; 315 }; 316 317 slpi_smp2p_in: slave-kernel { 318 qcom,entry-name = "slave-kernel"; 319 interrupt-controller; 320 #interrupt-cells = <2>; 321 }; 322 }; 323 324 psci { 325 compatible = "arm,psci-1.0"; 326 method = "smc"; 327 }; 328 329 soc: soc { 330 #address-cells = <1>; 331 #size-cells = <1>; 332 ranges = <0 0 0 0xffffffff>; 333 compatible = "simple-bus"; 334 335 gcc: clock-controller@100000 { 336 compatible = "qcom,gcc-sdm845"; 337 reg = <0x100000 0x1f0000>; 338 #clock-cells = <1>; 339 #reset-cells = <1>; 340 #power-domain-cells = <1>; 341 }; 342 343 qfprom@784000 { 344 compatible = "qcom,qfprom"; 345 reg = <0x784000 0x8ff>; 346 #address-cells = <1>; 347 #size-cells = <1>; 348 349 qusb2p_hstx_trim: hstx-trim-primary@1eb { 350 reg = <0x1eb 0x1>; 351 bits = <1 4>; 352 }; 353 354 qusb2s_hstx_trim: hstx-trim-secondary@1eb { 355 reg = <0x1eb 0x2>; 356 bits = <6 4>; 357 }; 358 }; 359 360 qupv3_id_0: geniqup@8c0000 { 361 compatible = "qcom,geni-se-qup"; 362 reg = <0x8c0000 0x6000>; 363 clock-names = "m-ahb", "s-ahb"; 364 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 365 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 366 #address-cells = <1>; 367 #size-cells = <1>; 368 ranges; 369 status = "disabled"; 370 371 i2c0: i2c@880000 { 372 compatible = "qcom,geni-i2c"; 373 reg = <0x880000 0x4000>; 374 clock-names = "se"; 375 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 376 pinctrl-names = "default"; 377 pinctrl-0 = <&qup_i2c0_default>; 378 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 379 #address-cells = <1>; 380 #size-cells = <0>; 381 status = "disabled"; 382 }; 383 384 spi0: spi@880000 { 385 compatible = "qcom,geni-spi"; 386 reg = <0x880000 0x4000>; 387 clock-names = "se"; 388 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 389 pinctrl-names = "default"; 390 pinctrl-0 = <&qup_spi0_default>; 391 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 392 #address-cells = <1>; 393 #size-cells = <0>; 394 status = "disabled"; 395 }; 396 397 i2c1: i2c@884000 { 398 compatible = "qcom,geni-i2c"; 399 reg = <0x884000 0x4000>; 400 clock-names = "se"; 401 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 402 pinctrl-names = "default"; 403 pinctrl-0 = <&qup_i2c1_default>; 404 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 405 #address-cells = <1>; 406 #size-cells = <0>; 407 status = "disabled"; 408 }; 409 410 spi1: spi@884000 { 411 compatible = "qcom,geni-spi"; 412 reg = <0x884000 0x4000>; 413 clock-names = "se"; 414 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 415 pinctrl-names = "default"; 416 pinctrl-0 = <&qup_spi1_default>; 417 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 418 #address-cells = <1>; 419 #size-cells = <0>; 420 status = "disabled"; 421 }; 422 423 i2c2: i2c@888000 { 424 compatible = "qcom,geni-i2c"; 425 reg = <0x888000 0x4000>; 426 clock-names = "se"; 427 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 428 pinctrl-names = "default"; 429 pinctrl-0 = <&qup_i2c2_default>; 430 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 431 #address-cells = <1>; 432 #size-cells = <0>; 433 status = "disabled"; 434 }; 435 436 spi2: spi@888000 { 437 compatible = "qcom,geni-spi"; 438 reg = <0x888000 0x4000>; 439 clock-names = "se"; 440 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 441 pinctrl-names = "default"; 442 pinctrl-0 = <&qup_spi2_default>; 443 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 444 #address-cells = <1>; 445 #size-cells = <0>; 446 status = "disabled"; 447 }; 448 449 i2c3: i2c@88c000 { 450 compatible = "qcom,geni-i2c"; 451 reg = <0x88c000 0x4000>; 452 clock-names = "se"; 453 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 454 pinctrl-names = "default"; 455 pinctrl-0 = <&qup_i2c3_default>; 456 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 457 #address-cells = <1>; 458 #size-cells = <0>; 459 status = "disabled"; 460 }; 461 462 spi3: spi@88c000 { 463 compatible = "qcom,geni-spi"; 464 reg = <0x88c000 0x4000>; 465 clock-names = "se"; 466 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 467 pinctrl-names = "default"; 468 pinctrl-0 = <&qup_spi3_default>; 469 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 470 #address-cells = <1>; 471 #size-cells = <0>; 472 status = "disabled"; 473 }; 474 475 i2c4: i2c@890000 { 476 compatible = "qcom,geni-i2c"; 477 reg = <0x890000 0x4000>; 478 clock-names = "se"; 479 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 480 pinctrl-names = "default"; 481 pinctrl-0 = <&qup_i2c4_default>; 482 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 483 #address-cells = <1>; 484 #size-cells = <0>; 485 status = "disabled"; 486 }; 487 488 spi4: spi@890000 { 489 compatible = "qcom,geni-spi"; 490 reg = <0x890000 0x4000>; 491 clock-names = "se"; 492 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 493 pinctrl-names = "default"; 494 pinctrl-0 = <&qup_spi4_default>; 495 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 496 #address-cells = <1>; 497 #size-cells = <0>; 498 status = "disabled"; 499 }; 500 501 i2c5: i2c@894000 { 502 compatible = "qcom,geni-i2c"; 503 reg = <0x894000 0x4000>; 504 clock-names = "se"; 505 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 506 pinctrl-names = "default"; 507 pinctrl-0 = <&qup_i2c5_default>; 508 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 509 #address-cells = <1>; 510 #size-cells = <0>; 511 status = "disabled"; 512 }; 513 514 spi5: spi@894000 { 515 compatible = "qcom,geni-spi"; 516 reg = <0x894000 0x4000>; 517 clock-names = "se"; 518 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 519 pinctrl-names = "default"; 520 pinctrl-0 = <&qup_spi5_default>; 521 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 522 #address-cells = <1>; 523 #size-cells = <0>; 524 status = "disabled"; 525 }; 526 527 i2c6: i2c@898000 { 528 compatible = "qcom,geni-i2c"; 529 reg = <0x898000 0x4000>; 530 clock-names = "se"; 531 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 532 pinctrl-names = "default"; 533 pinctrl-0 = <&qup_i2c6_default>; 534 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 535 #address-cells = <1>; 536 #size-cells = <0>; 537 status = "disabled"; 538 }; 539 540 spi6: spi@898000 { 541 compatible = "qcom,geni-spi"; 542 reg = <0x898000 0x4000>; 543 clock-names = "se"; 544 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 545 pinctrl-names = "default"; 546 pinctrl-0 = <&qup_spi6_default>; 547 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 548 #address-cells = <1>; 549 #size-cells = <0>; 550 status = "disabled"; 551 }; 552 553 i2c7: i2c@89c000 { 554 compatible = "qcom,geni-i2c"; 555 reg = <0x89c000 0x4000>; 556 clock-names = "se"; 557 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 558 pinctrl-names = "default"; 559 pinctrl-0 = <&qup_i2c7_default>; 560 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 561 #address-cells = <1>; 562 #size-cells = <0>; 563 status = "disabled"; 564 }; 565 566 spi7: spi@89c000 { 567 compatible = "qcom,geni-spi"; 568 reg = <0x89c000 0x4000>; 569 clock-names = "se"; 570 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 571 pinctrl-names = "default"; 572 pinctrl-0 = <&qup_spi7_default>; 573 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 574 #address-cells = <1>; 575 #size-cells = <0>; 576 status = "disabled"; 577 }; 578 }; 579 580 qupv3_id_1: geniqup@ac0000 { 581 compatible = "qcom,geni-se-qup"; 582 reg = <0xac0000 0x6000>; 583 clock-names = "m-ahb", "s-ahb"; 584 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 585 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 586 #address-cells = <1>; 587 #size-cells = <1>; 588 ranges; 589 status = "disabled"; 590 591 i2c8: i2c@a80000 { 592 compatible = "qcom,geni-i2c"; 593 reg = <0xa80000 0x4000>; 594 clock-names = "se"; 595 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 596 pinctrl-names = "default"; 597 pinctrl-0 = <&qup_i2c8_default>; 598 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 599 #address-cells = <1>; 600 #size-cells = <0>; 601 status = "disabled"; 602 }; 603 604 spi8: spi@a80000 { 605 compatible = "qcom,geni-spi"; 606 reg = <0xa80000 0x4000>; 607 clock-names = "se"; 608 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 609 pinctrl-names = "default"; 610 pinctrl-0 = <&qup_spi8_default>; 611 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 612 #address-cells = <1>; 613 #size-cells = <0>; 614 status = "disabled"; 615 }; 616 617 i2c9: i2c@a84000 { 618 compatible = "qcom,geni-i2c"; 619 reg = <0xa84000 0x4000>; 620 clock-names = "se"; 621 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 622 pinctrl-names = "default"; 623 pinctrl-0 = <&qup_i2c9_default>; 624 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 625 #address-cells = <1>; 626 #size-cells = <0>; 627 status = "disabled"; 628 }; 629 630 spi9: spi@a84000 { 631 compatible = "qcom,geni-spi"; 632 reg = <0xa84000 0x4000>; 633 clock-names = "se"; 634 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 635 pinctrl-names = "default"; 636 pinctrl-0 = <&qup_spi9_default>; 637 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 638 #address-cells = <1>; 639 #size-cells = <0>; 640 status = "disabled"; 641 }; 642 643 uart9: serial@a84000 { 644 compatible = "qcom,geni-debug-uart"; 645 reg = <0xa84000 0x4000>; 646 clock-names = "se"; 647 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 648 pinctrl-names = "default"; 649 pinctrl-0 = <&qup_uart9_default>; 650 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 651 status = "disabled"; 652 }; 653 654 i2c10: i2c@a88000 { 655 compatible = "qcom,geni-i2c"; 656 reg = <0xa88000 0x4000>; 657 clock-names = "se"; 658 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 659 pinctrl-names = "default"; 660 pinctrl-0 = <&qup_i2c10_default>; 661 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 662 #address-cells = <1>; 663 #size-cells = <0>; 664 status = "disabled"; 665 }; 666 667 spi10: spi@a88000 { 668 compatible = "qcom,geni-spi"; 669 reg = <0xa88000 0x4000>; 670 clock-names = "se"; 671 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 672 pinctrl-names = "default"; 673 pinctrl-0 = <&qup_spi10_default>; 674 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 675 #address-cells = <1>; 676 #size-cells = <0>; 677 status = "disabled"; 678 }; 679 680 i2c11: i2c@a8c000 { 681 compatible = "qcom,geni-i2c"; 682 reg = <0xa8c000 0x4000>; 683 clock-names = "se"; 684 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 685 pinctrl-names = "default"; 686 pinctrl-0 = <&qup_i2c11_default>; 687 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 688 #address-cells = <1>; 689 #size-cells = <0>; 690 status = "disabled"; 691 }; 692 693 spi11: spi@a8c000 { 694 compatible = "qcom,geni-spi"; 695 reg = <0xa8c000 0x4000>; 696 clock-names = "se"; 697 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 698 pinctrl-names = "default"; 699 pinctrl-0 = <&qup_spi11_default>; 700 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 701 #address-cells = <1>; 702 #size-cells = <0>; 703 status = "disabled"; 704 }; 705 706 i2c12: i2c@a90000 { 707 compatible = "qcom,geni-i2c"; 708 reg = <0xa90000 0x4000>; 709 clock-names = "se"; 710 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 711 pinctrl-names = "default"; 712 pinctrl-0 = <&qup_i2c12_default>; 713 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 714 #address-cells = <1>; 715 #size-cells = <0>; 716 status = "disabled"; 717 }; 718 719 spi12: spi@a90000 { 720 compatible = "qcom,geni-spi"; 721 reg = <0xa90000 0x4000>; 722 clock-names = "se"; 723 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 724 pinctrl-names = "default"; 725 pinctrl-0 = <&qup_spi12_default>; 726 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 727 #address-cells = <1>; 728 #size-cells = <0>; 729 status = "disabled"; 730 }; 731 732 i2c13: i2c@a94000 { 733 compatible = "qcom,geni-i2c"; 734 reg = <0xa94000 0x4000>; 735 clock-names = "se"; 736 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 737 pinctrl-names = "default"; 738 pinctrl-0 = <&qup_i2c13_default>; 739 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 740 #address-cells = <1>; 741 #size-cells = <0>; 742 status = "disabled"; 743 }; 744 745 spi13: spi@a94000 { 746 compatible = "qcom,geni-spi"; 747 reg = <0xa94000 0x4000>; 748 clock-names = "se"; 749 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 750 pinctrl-names = "default"; 751 pinctrl-0 = <&qup_spi13_default>; 752 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 753 #address-cells = <1>; 754 #size-cells = <0>; 755 status = "disabled"; 756 }; 757 758 i2c14: i2c@a98000 { 759 compatible = "qcom,geni-i2c"; 760 reg = <0xa98000 0x4000>; 761 clock-names = "se"; 762 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 763 pinctrl-names = "default"; 764 pinctrl-0 = <&qup_i2c14_default>; 765 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 766 #address-cells = <1>; 767 #size-cells = <0>; 768 status = "disabled"; 769 }; 770 771 spi14: spi@a98000 { 772 compatible = "qcom,geni-spi"; 773 reg = <0xa98000 0x4000>; 774 clock-names = "se"; 775 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 776 pinctrl-names = "default"; 777 pinctrl-0 = <&qup_spi14_default>; 778 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 779 #address-cells = <1>; 780 #size-cells = <0>; 781 status = "disabled"; 782 }; 783 784 i2c15: i2c@a9c000 { 785 compatible = "qcom,geni-i2c"; 786 reg = <0xa9c000 0x4000>; 787 clock-names = "se"; 788 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 789 pinctrl-names = "default"; 790 pinctrl-0 = <&qup_i2c15_default>; 791 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 792 #address-cells = <1>; 793 #size-cells = <0>; 794 status = "disabled"; 795 }; 796 797 spi15: spi@a9c000 { 798 compatible = "qcom,geni-spi"; 799 reg = <0xa9c000 0x4000>; 800 clock-names = "se"; 801 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 802 pinctrl-names = "default"; 803 pinctrl-0 = <&qup_spi15_default>; 804 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 805 #address-cells = <1>; 806 #size-cells = <0>; 807 status = "disabled"; 808 }; 809 }; 810 811 tcsr_mutex_regs: syscon@1f40000 { 812 compatible = "syscon"; 813 reg = <0x1f40000 0x40000>; 814 }; 815 816 tlmm: pinctrl@3400000 { 817 compatible = "qcom,sdm845-pinctrl"; 818 reg = <0x03400000 0xc00000>; 819 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 820 gpio-controller; 821 #gpio-cells = <2>; 822 interrupt-controller; 823 #interrupt-cells = <2>; 824 825 qup_i2c0_default: qup-i2c0-default { 826 pinmux { 827 pins = "gpio0", "gpio1"; 828 function = "qup0"; 829 }; 830 }; 831 832 qup_i2c1_default: qup-i2c1-default { 833 pinmux { 834 pins = "gpio17", "gpio18"; 835 function = "qup1"; 836 }; 837 }; 838 839 qup_i2c2_default: qup-i2c2-default { 840 pinmux { 841 pins = "gpio27", "gpio28"; 842 function = "qup2"; 843 }; 844 }; 845 846 qup_i2c3_default: qup-i2c3-default { 847 pinmux { 848 pins = "gpio41", "gpio42"; 849 function = "qup3"; 850 }; 851 }; 852 853 qup_i2c4_default: qup-i2c4-default { 854 pinmux { 855 pins = "gpio89", "gpio90"; 856 function = "qup4"; 857 }; 858 }; 859 860 qup_i2c5_default: qup-i2c5-default { 861 pinmux { 862 pins = "gpio85", "gpio86"; 863 function = "qup5"; 864 }; 865 }; 866 867 qup_i2c6_default: qup-i2c6-default { 868 pinmux { 869 pins = "gpio45", "gpio46"; 870 function = "qup6"; 871 }; 872 }; 873 874 qup_i2c7_default: qup-i2c7-default { 875 pinmux { 876 pins = "gpio93", "gpio94"; 877 function = "qup7"; 878 }; 879 }; 880 881 qup_i2c8_default: qup-i2c8-default { 882 pinmux { 883 pins = "gpio65", "gpio66"; 884 function = "qup8"; 885 }; 886 }; 887 888 qup_i2c9_default: qup-i2c9-default { 889 pinmux { 890 pins = "gpio6", "gpio7"; 891 function = "qup9"; 892 }; 893 }; 894 895 qup_i2c10_default: qup-i2c10-default { 896 pinmux { 897 pins = "gpio55", "gpio56"; 898 function = "qup10"; 899 }; 900 }; 901 902 qup_i2c11_default: qup-i2c11-default { 903 pinmux { 904 pins = "gpio31", "gpio32"; 905 function = "qup11"; 906 }; 907 }; 908 909 qup_i2c12_default: qup-i2c12-default { 910 pinmux { 911 pins = "gpio49", "gpio50"; 912 function = "qup12"; 913 }; 914 }; 915 916 qup_i2c13_default: qup-i2c13-default { 917 pinmux { 918 pins = "gpio105", "gpio106"; 919 function = "qup13"; 920 }; 921 }; 922 923 qup_i2c14_default: qup-i2c14-default { 924 pinmux { 925 pins = "gpio33", "gpio34"; 926 function = "qup14"; 927 }; 928 }; 929 930 qup_i2c15_default: qup-i2c15-default { 931 pinmux { 932 pins = "gpio81", "gpio82"; 933 function = "qup15"; 934 }; 935 }; 936 937 qup_spi0_default: qup-spi0-default { 938 pinmux { 939 pins = "gpio0", "gpio1", 940 "gpio2", "gpio3"; 941 function = "qup0"; 942 }; 943 }; 944 945 qup_spi1_default: qup-spi1-default { 946 pinmux { 947 pins = "gpio17", "gpio18", 948 "gpio19", "gpio20"; 949 function = "qup1"; 950 }; 951 }; 952 953 qup_spi2_default: qup-spi2-default { 954 pinmux { 955 pins = "gpio27", "gpio28", 956 "gpio29", "gpio30"; 957 function = "qup2"; 958 }; 959 }; 960 961 qup_spi3_default: qup-spi3-default { 962 pinmux { 963 pins = "gpio41", "gpio42", 964 "gpio43", "gpio44"; 965 function = "qup3"; 966 }; 967 }; 968 969 qup_spi4_default: qup-spi4-default { 970 pinmux { 971 pins = "gpio89", "gpio90", 972 "gpio91", "gpio92"; 973 function = "qup4"; 974 }; 975 }; 976 977 qup_spi5_default: qup-spi5-default { 978 pinmux { 979 pins = "gpio85", "gpio86", 980 "gpio87", "gpio88"; 981 function = "qup5"; 982 }; 983 }; 984 985 qup_spi6_default: qup-spi6-default { 986 pinmux { 987 pins = "gpio45", "gpio46", 988 "gpio47", "gpio48"; 989 function = "qup6"; 990 }; 991 }; 992 993 qup_spi7_default: qup-spi7-default { 994 pinmux { 995 pins = "gpio93", "gpio94", 996 "gpio95", "gpio96"; 997 function = "qup7"; 998 }; 999 }; 1000 1001 qup_spi8_default: qup-spi8-default { 1002 pinmux { 1003 pins = "gpio65", "gpio66", 1004 "gpio67", "gpio68"; 1005 function = "qup8"; 1006 }; 1007 }; 1008 1009 qup_spi9_default: qup-spi9-default { 1010 pinmux { 1011 pins = "gpio6", "gpio7", 1012 "gpio4", "gpio5"; 1013 function = "qup9"; 1014 }; 1015 }; 1016 1017 qup_spi10_default: qup-spi10-default { 1018 pinmux { 1019 pins = "gpio55", "gpio56", 1020 "gpio53", "gpio54"; 1021 function = "qup10"; 1022 }; 1023 }; 1024 1025 qup_spi11_default: qup-spi11-default { 1026 pinmux { 1027 pins = "gpio31", "gpio32", 1028 "gpio33", "gpio34"; 1029 function = "qup11"; 1030 }; 1031 }; 1032 1033 qup_spi12_default: qup-spi12-default { 1034 pinmux { 1035 pins = "gpio49", "gpio50", 1036 "gpio51", "gpio52"; 1037 function = "qup12"; 1038 }; 1039 }; 1040 1041 qup_spi13_default: qup-spi13-default { 1042 pinmux { 1043 pins = "gpio105", "gpio106", 1044 "gpio107", "gpio108"; 1045 function = "qup13"; 1046 }; 1047 }; 1048 1049 qup_spi14_default: qup-spi14-default { 1050 pinmux { 1051 pins = "gpio33", "gpio34", 1052 "gpio31", "gpio32"; 1053 function = "qup14"; 1054 }; 1055 }; 1056 1057 qup_spi15_default: qup-spi15-default { 1058 pinmux { 1059 pins = "gpio81", "gpio82", 1060 "gpio83", "gpio84"; 1061 function = "qup15"; 1062 }; 1063 }; 1064 1065 qup_uart9_default: qup-uart9-default { 1066 pinmux { 1067 pins = "gpio4", "gpio5"; 1068 function = "qup9"; 1069 }; 1070 }; 1071 }; 1072 1073 usb_1_hsphy: phy@88e2000 { 1074 compatible = "qcom,sdm845-qusb2-phy"; 1075 reg = <0x88e2000 0x400>; 1076 status = "disabled"; 1077 #phy-cells = <0>; 1078 1079 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 1080 <&rpmhcc RPMH_CXO_CLK>; 1081 clock-names = "cfg_ahb", "ref"; 1082 1083 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 1084 1085 nvmem-cells = <&qusb2p_hstx_trim>; 1086 }; 1087 1088 usb_2_hsphy: phy@88e3000 { 1089 compatible = "qcom,sdm845-qusb2-phy"; 1090 reg = <0x88e3000 0x400>; 1091 status = "disabled"; 1092 #phy-cells = <0>; 1093 1094 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 1095 <&rpmhcc RPMH_CXO_CLK>; 1096 clock-names = "cfg_ahb", "ref"; 1097 1098 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 1099 1100 nvmem-cells = <&qusb2s_hstx_trim>; 1101 }; 1102 1103 usb_1_qmpphy: phy@88e9000 { 1104 compatible = "qcom,sdm845-qmp-usb3-phy"; 1105 reg = <0x88e9000 0x18c>, 1106 <0x88e8000 0x10>; 1107 reg-names = "reg-base", "dp_com"; 1108 status = "disabled"; 1109 #clock-cells = <1>; 1110 #address-cells = <1>; 1111 #size-cells = <1>; 1112 ranges; 1113 1114 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 1115 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 1116 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 1117 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 1118 clock-names = "aux", "cfg_ahb", "ref", "com_aux"; 1119 1120 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 1121 <&gcc GCC_USB3_PHY_PRIM_BCR>; 1122 reset-names = "phy", "common"; 1123 1124 usb_1_ssphy: lane@88e9200 { 1125 reg = <0x88e9200 0x128>, 1126 <0x88e9400 0x200>, 1127 <0x88e9c00 0x218>, 1128 <0x88e9a00 0x100>; 1129 #phy-cells = <0>; 1130 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 1131 clock-names = "pipe0"; 1132 clock-output-names = "usb3_phy_pipe_clk_src"; 1133 }; 1134 }; 1135 1136 usb_2_qmpphy: phy@88eb000 { 1137 compatible = "qcom,sdm845-qmp-usb3-uni-phy"; 1138 reg = <0x88eb000 0x18c>; 1139 status = "disabled"; 1140 #clock-cells = <1>; 1141 #address-cells = <1>; 1142 #size-cells = <1>; 1143 ranges; 1144 1145 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 1146 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 1147 <&gcc GCC_USB3_SEC_CLKREF_CLK>, 1148 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; 1149 clock-names = "aux", "cfg_ahb", "ref", "com_aux"; 1150 1151 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, 1152 <&gcc GCC_USB3_PHY_SEC_BCR>; 1153 reset-names = "phy", "common"; 1154 1155 usb_2_ssphy: lane@88eb200 { 1156 reg = <0x88eb200 0x128>, 1157 <0x88eb400 0x1fc>, 1158 <0x88eb800 0x218>, 1159 <0x88e9600 0x70>; 1160 #phy-cells = <0>; 1161 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 1162 clock-names = "pipe0"; 1163 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 1164 }; 1165 }; 1166 1167 usb_1: usb@a6f8800 { 1168 compatible = "qcom,sdm845-dwc3", "qcom,dwc3"; 1169 reg = <0xa6f8800 0x400>; 1170 status = "disabled"; 1171 #address-cells = <1>; 1172 #size-cells = <1>; 1173 ranges; 1174 1175 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 1176 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 1177 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 1178 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1179 <&gcc GCC_USB30_PRIM_SLEEP_CLK>; 1180 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 1181 "sleep"; 1182 1183 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1184 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 1185 assigned-clock-rates = <19200000>, <150000000>; 1186 1187 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 1188 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>, 1189 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>, 1190 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>; 1191 interrupt-names = "hs_phy_irq", "ss_phy_irq", 1192 "dm_hs_phy_irq", "dp_hs_phy_irq"; 1193 1194 power-domains = <&gcc USB30_PRIM_GDSC>; 1195 1196 resets = <&gcc GCC_USB30_PRIM_BCR>; 1197 1198 usb_1_dwc3: dwc3@a600000 { 1199 compatible = "snps,dwc3"; 1200 reg = <0xa600000 0xcd00>; 1201 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 1202 snps,dis_u2_susphy_quirk; 1203 snps,dis_enblslpm_quirk; 1204 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 1205 phy-names = "usb2-phy", "usb3-phy"; 1206 }; 1207 }; 1208 1209 usb_2: usb@a8f8800 { 1210 compatible = "qcom,sdm845-dwc3", "qcom,dwc3"; 1211 reg = <0xa8f8800 0x400>; 1212 status = "disabled"; 1213 #address-cells = <1>; 1214 #size-cells = <1>; 1215 ranges; 1216 1217 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 1218 <&gcc GCC_USB30_SEC_MASTER_CLK>, 1219 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 1220 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 1221 <&gcc GCC_USB30_SEC_SLEEP_CLK>; 1222 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 1223 "sleep"; 1224 1225 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 1226 <&gcc GCC_USB30_SEC_MASTER_CLK>; 1227 assigned-clock-rates = <19200000>, <150000000>; 1228 1229 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 1230 <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>, 1231 <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>, 1232 <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>; 1233 interrupt-names = "hs_phy_irq", "ss_phy_irq", 1234 "dm_hs_phy_irq", "dp_hs_phy_irq"; 1235 1236 power-domains = <&gcc USB30_SEC_GDSC>; 1237 1238 resets = <&gcc GCC_USB30_SEC_BCR>; 1239 1240 usb_2_dwc3: dwc3@a800000 { 1241 compatible = "snps,dwc3"; 1242 reg = <0xa800000 0xcd00>; 1243 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 1244 snps,dis_u2_susphy_quirk; 1245 snps,dis_enblslpm_quirk; 1246 phys = <&usb_2_hsphy>, <&usb_2_ssphy>; 1247 phy-names = "usb2-phy", "usb3-phy"; 1248 }; 1249 }; 1250 1251 dispcc: clock-controller@af00000 { 1252 compatible = "qcom,sdm845-dispcc"; 1253 reg = <0xaf00000 0x10000>; 1254 #clock-cells = <1>; 1255 #reset-cells = <1>; 1256 #power-domain-cells = <1>; 1257 }; 1258 1259 tsens0: thermal-sensor@c263000 { 1260 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; 1261 reg = <0xc263000 0x1ff>, /* TM */ 1262 <0xc222000 0x1ff>; /* SROT */ 1263 #qcom,sensors = <13>; 1264 #thermal-sensor-cells = <1>; 1265 }; 1266 1267 tsens1: thermal-sensor@c265000 { 1268 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; 1269 reg = <0xc265000 0x1ff>, /* TM */ 1270 <0xc223000 0x1ff>; /* SROT */ 1271 #qcom,sensors = <8>; 1272 #thermal-sensor-cells = <1>; 1273 }; 1274 1275 aoss_reset: reset-controller@c2a0000 { 1276 compatible = "qcom,sdm845-aoss-cc"; 1277 reg = <0xc2a0000 0x31000>; 1278 #reset-cells = <1>; 1279 }; 1280 1281 spmi_bus: spmi@c440000 { 1282 compatible = "qcom,spmi-pmic-arb"; 1283 reg = <0xc440000 0x1100>, 1284 <0xc600000 0x2000000>, 1285 <0xe600000 0x100000>, 1286 <0xe700000 0xa0000>, 1287 <0xc40a000 0x26000>; 1288 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1289 interrupt-names = "periph_irq"; 1290 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>; 1291 qcom,ee = <0>; 1292 qcom,channel = <0>; 1293 #address-cells = <2>; 1294 #size-cells = <0>; 1295 interrupt-controller; 1296 #interrupt-cells = <4>; 1297 cell-index = <0>; 1298 }; 1299 1300 apss_shared: mailbox@17990000 { 1301 compatible = "qcom,sdm845-apss-shared"; 1302 reg = <0x17990000 0x1000>; 1303 #mbox-cells = <1>; 1304 }; 1305 1306 apps_rsc: rsc@179c0000 { 1307 label = "apps_rsc"; 1308 compatible = "qcom,rpmh-rsc"; 1309 reg = <0x179c0000 0x10000>, 1310 <0x179d0000 0x10000>, 1311 <0x179e0000 0x10000>; 1312 reg-names = "drv-0", "drv-1", "drv-2"; 1313 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 1314 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 1315 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1316 qcom,tcs-offset = <0xd00>; 1317 qcom,drv-id = <2>; 1318 qcom,tcs-config = <ACTIVE_TCS 2>, 1319 <SLEEP_TCS 3>, 1320 <WAKE_TCS 3>, 1321 <CONTROL_TCS 1>; 1322 1323 rpmhcc: clock-controller { 1324 compatible = "qcom,sdm845-rpmh-clk"; 1325 #clock-cells = <1>; 1326 }; 1327 }; 1328 1329 intc: interrupt-controller@17a00000 { 1330 compatible = "arm,gic-v3"; 1331 #address-cells = <1>; 1332 #size-cells = <1>; 1333 ranges; 1334 #interrupt-cells = <3>; 1335 interrupt-controller; 1336 reg = <0x17a00000 0x10000>, /* GICD */ 1337 <0x17a60000 0x100000>; /* GICR * 8 */ 1338 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 1339 1340 gic-its@17a40000 { 1341 compatible = "arm,gic-v3-its"; 1342 msi-controller; 1343 #msi-cells = <1>; 1344 reg = <0x17a40000 0x20000>; 1345 status = "disabled"; 1346 }; 1347 }; 1348 1349 timer@17c90000 { 1350 #address-cells = <1>; 1351 #size-cells = <1>; 1352 ranges; 1353 compatible = "arm,armv7-timer-mem"; 1354 reg = <0x17c90000 0x1000>; 1355 1356 frame@17ca0000 { 1357 frame-number = <0>; 1358 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 1359 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1360 reg = <0x17ca0000 0x1000>, 1361 <0x17cb0000 0x1000>; 1362 }; 1363 1364 frame@17cc0000 { 1365 frame-number = <1>; 1366 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 1367 reg = <0x17cc0000 0x1000>; 1368 status = "disabled"; 1369 }; 1370 1371 frame@17cd0000 { 1372 frame-number = <2>; 1373 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1374 reg = <0x17cd0000 0x1000>; 1375 status = "disabled"; 1376 }; 1377 1378 frame@17ce0000 { 1379 frame-number = <3>; 1380 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1381 reg = <0x17ce0000 0x1000>; 1382 status = "disabled"; 1383 }; 1384 1385 frame@17cf0000 { 1386 frame-number = <4>; 1387 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1388 reg = <0x17cf0000 0x1000>; 1389 status = "disabled"; 1390 }; 1391 1392 frame@17d00000 { 1393 frame-number = <5>; 1394 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1395 reg = <0x17d00000 0x1000>; 1396 status = "disabled"; 1397 }; 1398 1399 frame@17d10000 { 1400 frame-number = <6>; 1401 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1402 reg = <0x17d10000 0x1000>; 1403 status = "disabled"; 1404 }; 1405 }; 1406 }; 1407}; 1408