1// SPDX-License-Identifier: GPL-2.0 2/* 3 * SDM845 SoC device tree source 4 * 5 * Copyright (c) 2018, The Linux Foundation. All rights reserved. 6 */ 7 8#include <dt-bindings/clock/qcom,camcc-sdm845.h> 9#include <dt-bindings/clock/qcom,dispcc-sdm845.h> 10#include <dt-bindings/clock/qcom,gcc-sdm845.h> 11#include <dt-bindings/clock/qcom,gpucc-sdm845.h> 12#include <dt-bindings/clock/qcom,lpass-sdm845.h> 13#include <dt-bindings/clock/qcom,rpmh.h> 14#include <dt-bindings/clock/qcom,videocc-sdm845.h> 15#include <dt-bindings/dma/qcom-gpi.h> 16#include <dt-bindings/firmware/qcom,scm.h> 17#include <dt-bindings/gpio/gpio.h> 18#include <dt-bindings/interconnect/qcom,osm-l3.h> 19#include <dt-bindings/interconnect/qcom,sdm845.h> 20#include <dt-bindings/interrupt-controller/arm-gic.h> 21#include <dt-bindings/phy/phy-qcom-qmp.h> 22#include <dt-bindings/phy/phy-qcom-qusb2.h> 23#include <dt-bindings/power/qcom-rpmpd.h> 24#include <dt-bindings/reset/qcom,sdm845-aoss.h> 25#include <dt-bindings/reset/qcom,sdm845-pdc.h> 26#include <dt-bindings/soc/qcom,apr.h> 27#include <dt-bindings/soc/qcom,rpmh-rsc.h> 28#include <dt-bindings/clock/qcom,gcc-sdm845.h> 29#include <dt-bindings/thermal/thermal.h> 30 31/ { 32 interrupt-parent = <&intc>; 33 34 #address-cells = <2>; 35 #size-cells = <2>; 36 37 aliases { 38 i2c0 = &i2c0; 39 i2c1 = &i2c1; 40 i2c2 = &i2c2; 41 i2c3 = &i2c3; 42 i2c4 = &i2c4; 43 i2c5 = &i2c5; 44 i2c6 = &i2c6; 45 i2c7 = &i2c7; 46 i2c8 = &i2c8; 47 i2c9 = &i2c9; 48 i2c10 = &i2c10; 49 i2c11 = &i2c11; 50 i2c12 = &i2c12; 51 i2c13 = &i2c13; 52 i2c14 = &i2c14; 53 i2c15 = &i2c15; 54 spi0 = &spi0; 55 spi1 = &spi1; 56 spi2 = &spi2; 57 spi3 = &spi3; 58 spi4 = &spi4; 59 spi5 = &spi5; 60 spi6 = &spi6; 61 spi7 = &spi7; 62 spi8 = &spi8; 63 spi9 = &spi9; 64 spi10 = &spi10; 65 spi11 = &spi11; 66 spi12 = &spi12; 67 spi13 = &spi13; 68 spi14 = &spi14; 69 spi15 = &spi15; 70 }; 71 72 chosen { }; 73 74 clocks { 75 xo_board: xo-board { 76 compatible = "fixed-clock"; 77 #clock-cells = <0>; 78 clock-frequency = <38400000>; 79 clock-output-names = "xo_board"; 80 }; 81 82 sleep_clk: sleep-clk { 83 compatible = "fixed-clock"; 84 #clock-cells = <0>; 85 clock-frequency = <32764>; 86 }; 87 }; 88 89 cpus: cpus { 90 #address-cells = <2>; 91 #size-cells = <0>; 92 93 CPU0: cpu@0 { 94 device_type = "cpu"; 95 compatible = "qcom,kryo385"; 96 reg = <0x0 0x0>; 97 clocks = <&cpufreq_hw 0>; 98 enable-method = "psci"; 99 capacity-dmips-mhz = <611>; 100 dynamic-power-coefficient = <154>; 101 qcom,freq-domain = <&cpufreq_hw 0>; 102 operating-points-v2 = <&cpu0_opp_table>; 103 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 104 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 105 power-domains = <&CPU_PD0>; 106 power-domain-names = "psci"; 107 #cooling-cells = <2>; 108 next-level-cache = <&L2_0>; 109 L2_0: l2-cache { 110 compatible = "cache"; 111 cache-level = <2>; 112 cache-unified; 113 next-level-cache = <&L3_0>; 114 L3_0: l3-cache { 115 compatible = "cache"; 116 cache-level = <3>; 117 cache-unified; 118 }; 119 }; 120 }; 121 122 CPU1: cpu@100 { 123 device_type = "cpu"; 124 compatible = "qcom,kryo385"; 125 reg = <0x0 0x100>; 126 clocks = <&cpufreq_hw 0>; 127 enable-method = "psci"; 128 capacity-dmips-mhz = <611>; 129 dynamic-power-coefficient = <154>; 130 qcom,freq-domain = <&cpufreq_hw 0>; 131 operating-points-v2 = <&cpu0_opp_table>; 132 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 133 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 134 power-domains = <&CPU_PD1>; 135 power-domain-names = "psci"; 136 #cooling-cells = <2>; 137 next-level-cache = <&L2_100>; 138 L2_100: l2-cache { 139 compatible = "cache"; 140 cache-level = <2>; 141 cache-unified; 142 next-level-cache = <&L3_0>; 143 }; 144 }; 145 146 CPU2: cpu@200 { 147 device_type = "cpu"; 148 compatible = "qcom,kryo385"; 149 reg = <0x0 0x200>; 150 clocks = <&cpufreq_hw 0>; 151 enable-method = "psci"; 152 capacity-dmips-mhz = <611>; 153 dynamic-power-coefficient = <154>; 154 qcom,freq-domain = <&cpufreq_hw 0>; 155 operating-points-v2 = <&cpu0_opp_table>; 156 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 157 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 158 power-domains = <&CPU_PD2>; 159 power-domain-names = "psci"; 160 #cooling-cells = <2>; 161 next-level-cache = <&L2_200>; 162 L2_200: l2-cache { 163 compatible = "cache"; 164 cache-level = <2>; 165 cache-unified; 166 next-level-cache = <&L3_0>; 167 }; 168 }; 169 170 CPU3: cpu@300 { 171 device_type = "cpu"; 172 compatible = "qcom,kryo385"; 173 reg = <0x0 0x300>; 174 clocks = <&cpufreq_hw 0>; 175 enable-method = "psci"; 176 capacity-dmips-mhz = <611>; 177 dynamic-power-coefficient = <154>; 178 qcom,freq-domain = <&cpufreq_hw 0>; 179 operating-points-v2 = <&cpu0_opp_table>; 180 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 181 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 182 #cooling-cells = <2>; 183 power-domains = <&CPU_PD3>; 184 power-domain-names = "psci"; 185 next-level-cache = <&L2_300>; 186 L2_300: l2-cache { 187 compatible = "cache"; 188 cache-level = <2>; 189 cache-unified; 190 next-level-cache = <&L3_0>; 191 }; 192 }; 193 194 CPU4: cpu@400 { 195 device_type = "cpu"; 196 compatible = "qcom,kryo385"; 197 reg = <0x0 0x400>; 198 clocks = <&cpufreq_hw 1>; 199 enable-method = "psci"; 200 capacity-dmips-mhz = <1024>; 201 dynamic-power-coefficient = <442>; 202 qcom,freq-domain = <&cpufreq_hw 1>; 203 operating-points-v2 = <&cpu4_opp_table>; 204 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 205 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 206 power-domains = <&CPU_PD4>; 207 power-domain-names = "psci"; 208 #cooling-cells = <2>; 209 next-level-cache = <&L2_400>; 210 L2_400: l2-cache { 211 compatible = "cache"; 212 cache-level = <2>; 213 cache-unified; 214 next-level-cache = <&L3_0>; 215 }; 216 }; 217 218 CPU5: cpu@500 { 219 device_type = "cpu"; 220 compatible = "qcom,kryo385"; 221 reg = <0x0 0x500>; 222 clocks = <&cpufreq_hw 1>; 223 enable-method = "psci"; 224 capacity-dmips-mhz = <1024>; 225 dynamic-power-coefficient = <442>; 226 qcom,freq-domain = <&cpufreq_hw 1>; 227 operating-points-v2 = <&cpu4_opp_table>; 228 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 229 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 230 power-domains = <&CPU_PD5>; 231 power-domain-names = "psci"; 232 #cooling-cells = <2>; 233 next-level-cache = <&L2_500>; 234 L2_500: l2-cache { 235 compatible = "cache"; 236 cache-level = <2>; 237 cache-unified; 238 next-level-cache = <&L3_0>; 239 }; 240 }; 241 242 CPU6: cpu@600 { 243 device_type = "cpu"; 244 compatible = "qcom,kryo385"; 245 reg = <0x0 0x600>; 246 clocks = <&cpufreq_hw 1>; 247 enable-method = "psci"; 248 capacity-dmips-mhz = <1024>; 249 dynamic-power-coefficient = <442>; 250 qcom,freq-domain = <&cpufreq_hw 1>; 251 operating-points-v2 = <&cpu4_opp_table>; 252 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 253 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 254 power-domains = <&CPU_PD6>; 255 power-domain-names = "psci"; 256 #cooling-cells = <2>; 257 next-level-cache = <&L2_600>; 258 L2_600: l2-cache { 259 compatible = "cache"; 260 cache-level = <2>; 261 cache-unified; 262 next-level-cache = <&L3_0>; 263 }; 264 }; 265 266 CPU7: cpu@700 { 267 device_type = "cpu"; 268 compatible = "qcom,kryo385"; 269 reg = <0x0 0x700>; 270 clocks = <&cpufreq_hw 1>; 271 enable-method = "psci"; 272 capacity-dmips-mhz = <1024>; 273 dynamic-power-coefficient = <442>; 274 qcom,freq-domain = <&cpufreq_hw 1>; 275 operating-points-v2 = <&cpu4_opp_table>; 276 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 277 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 278 power-domains = <&CPU_PD7>; 279 power-domain-names = "psci"; 280 #cooling-cells = <2>; 281 next-level-cache = <&L2_700>; 282 L2_700: l2-cache { 283 compatible = "cache"; 284 cache-level = <2>; 285 cache-unified; 286 next-level-cache = <&L3_0>; 287 }; 288 }; 289 290 cpu-map { 291 cluster0 { 292 core0 { 293 cpu = <&CPU0>; 294 }; 295 296 core1 { 297 cpu = <&CPU1>; 298 }; 299 300 core2 { 301 cpu = <&CPU2>; 302 }; 303 304 core3 { 305 cpu = <&CPU3>; 306 }; 307 308 core4 { 309 cpu = <&CPU4>; 310 }; 311 312 core5 { 313 cpu = <&CPU5>; 314 }; 315 316 core6 { 317 cpu = <&CPU6>; 318 }; 319 320 core7 { 321 cpu = <&CPU7>; 322 }; 323 }; 324 }; 325 326 cpu_idle_states: idle-states { 327 entry-method = "psci"; 328 329 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 330 compatible = "arm,idle-state"; 331 idle-state-name = "little-rail-power-collapse"; 332 arm,psci-suspend-param = <0x40000004>; 333 entry-latency-us = <350>; 334 exit-latency-us = <461>; 335 min-residency-us = <1890>; 336 local-timer-stop; 337 }; 338 339 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 340 compatible = "arm,idle-state"; 341 idle-state-name = "big-rail-power-collapse"; 342 arm,psci-suspend-param = <0x40000004>; 343 entry-latency-us = <264>; 344 exit-latency-us = <621>; 345 min-residency-us = <952>; 346 local-timer-stop; 347 }; 348 }; 349 350 domain-idle-states { 351 CLUSTER_SLEEP_0: cluster-sleep-0 { 352 compatible = "domain-idle-state"; 353 arm,psci-suspend-param = <0x4100c244>; 354 entry-latency-us = <3263>; 355 exit-latency-us = <6562>; 356 min-residency-us = <9987>; 357 }; 358 }; 359 }; 360 361 firmware { 362 scm { 363 compatible = "qcom,scm-sdm845", "qcom,scm"; 364 }; 365 }; 366 367 memory@80000000 { 368 device_type = "memory"; 369 /* We expect the bootloader to fill in the size */ 370 reg = <0 0x80000000 0 0>; 371 }; 372 373 cpu0_opp_table: opp-table-cpu0 { 374 compatible = "operating-points-v2"; 375 opp-shared; 376 377 cpu0_opp1: opp-300000000 { 378 opp-hz = /bits/ 64 <300000000>; 379 opp-peak-kBps = <800000 4800000>; 380 }; 381 382 cpu0_opp2: opp-403200000 { 383 opp-hz = /bits/ 64 <403200000>; 384 opp-peak-kBps = <800000 4800000>; 385 }; 386 387 cpu0_opp3: opp-480000000 { 388 opp-hz = /bits/ 64 <480000000>; 389 opp-peak-kBps = <800000 6451200>; 390 }; 391 392 cpu0_opp4: opp-576000000 { 393 opp-hz = /bits/ 64 <576000000>; 394 opp-peak-kBps = <800000 6451200>; 395 }; 396 397 cpu0_opp5: opp-652800000 { 398 opp-hz = /bits/ 64 <652800000>; 399 opp-peak-kBps = <800000 7680000>; 400 }; 401 402 cpu0_opp6: opp-748800000 { 403 opp-hz = /bits/ 64 <748800000>; 404 opp-peak-kBps = <1804000 9216000>; 405 }; 406 407 cpu0_opp7: opp-825600000 { 408 opp-hz = /bits/ 64 <825600000>; 409 opp-peak-kBps = <1804000 9216000>; 410 }; 411 412 cpu0_opp8: opp-902400000 { 413 opp-hz = /bits/ 64 <902400000>; 414 opp-peak-kBps = <1804000 10444800>; 415 }; 416 417 cpu0_opp9: opp-979200000 { 418 opp-hz = /bits/ 64 <979200000>; 419 opp-peak-kBps = <1804000 11980800>; 420 }; 421 422 cpu0_opp10: opp-1056000000 { 423 opp-hz = /bits/ 64 <1056000000>; 424 opp-peak-kBps = <1804000 11980800>; 425 }; 426 427 cpu0_opp11: opp-1132800000 { 428 opp-hz = /bits/ 64 <1132800000>; 429 opp-peak-kBps = <2188000 13516800>; 430 }; 431 432 cpu0_opp12: opp-1228800000 { 433 opp-hz = /bits/ 64 <1228800000>; 434 opp-peak-kBps = <2188000 15052800>; 435 }; 436 437 cpu0_opp13: opp-1324800000 { 438 opp-hz = /bits/ 64 <1324800000>; 439 opp-peak-kBps = <2188000 16588800>; 440 }; 441 442 cpu0_opp14: opp-1420800000 { 443 opp-hz = /bits/ 64 <1420800000>; 444 opp-peak-kBps = <3072000 18124800>; 445 }; 446 447 cpu0_opp15: opp-1516800000 { 448 opp-hz = /bits/ 64 <1516800000>; 449 opp-peak-kBps = <3072000 19353600>; 450 }; 451 452 cpu0_opp16: opp-1612800000 { 453 opp-hz = /bits/ 64 <1612800000>; 454 opp-peak-kBps = <4068000 19353600>; 455 }; 456 457 cpu0_opp17: opp-1689600000 { 458 opp-hz = /bits/ 64 <1689600000>; 459 opp-peak-kBps = <4068000 20889600>; 460 }; 461 462 cpu0_opp18: opp-1766400000 { 463 opp-hz = /bits/ 64 <1766400000>; 464 opp-peak-kBps = <4068000 22425600>; 465 }; 466 }; 467 468 cpu4_opp_table: opp-table-cpu4 { 469 compatible = "operating-points-v2"; 470 opp-shared; 471 472 cpu4_opp1: opp-300000000 { 473 opp-hz = /bits/ 64 <300000000>; 474 opp-peak-kBps = <800000 4800000>; 475 }; 476 477 cpu4_opp2: opp-403200000 { 478 opp-hz = /bits/ 64 <403200000>; 479 opp-peak-kBps = <800000 4800000>; 480 }; 481 482 cpu4_opp3: opp-480000000 { 483 opp-hz = /bits/ 64 <480000000>; 484 opp-peak-kBps = <1804000 4800000>; 485 }; 486 487 cpu4_opp4: opp-576000000 { 488 opp-hz = /bits/ 64 <576000000>; 489 opp-peak-kBps = <1804000 4800000>; 490 }; 491 492 cpu4_opp5: opp-652800000 { 493 opp-hz = /bits/ 64 <652800000>; 494 opp-peak-kBps = <1804000 4800000>; 495 }; 496 497 cpu4_opp6: opp-748800000 { 498 opp-hz = /bits/ 64 <748800000>; 499 opp-peak-kBps = <1804000 4800000>; 500 }; 501 502 cpu4_opp7: opp-825600000 { 503 opp-hz = /bits/ 64 <825600000>; 504 opp-peak-kBps = <2188000 9216000>; 505 }; 506 507 cpu4_opp8: opp-902400000 { 508 opp-hz = /bits/ 64 <902400000>; 509 opp-peak-kBps = <2188000 9216000>; 510 }; 511 512 cpu4_opp9: opp-979200000 { 513 opp-hz = /bits/ 64 <979200000>; 514 opp-peak-kBps = <2188000 9216000>; 515 }; 516 517 cpu4_opp10: opp-1056000000 { 518 opp-hz = /bits/ 64 <1056000000>; 519 opp-peak-kBps = <3072000 9216000>; 520 }; 521 522 cpu4_opp11: opp-1132800000 { 523 opp-hz = /bits/ 64 <1132800000>; 524 opp-peak-kBps = <3072000 11980800>; 525 }; 526 527 cpu4_opp12: opp-1209600000 { 528 opp-hz = /bits/ 64 <1209600000>; 529 opp-peak-kBps = <4068000 11980800>; 530 }; 531 532 cpu4_opp13: opp-1286400000 { 533 opp-hz = /bits/ 64 <1286400000>; 534 opp-peak-kBps = <4068000 11980800>; 535 }; 536 537 cpu4_opp14: opp-1363200000 { 538 opp-hz = /bits/ 64 <1363200000>; 539 opp-peak-kBps = <4068000 15052800>; 540 }; 541 542 cpu4_opp15: opp-1459200000 { 543 opp-hz = /bits/ 64 <1459200000>; 544 opp-peak-kBps = <4068000 15052800>; 545 }; 546 547 cpu4_opp16: opp-1536000000 { 548 opp-hz = /bits/ 64 <1536000000>; 549 opp-peak-kBps = <5412000 15052800>; 550 }; 551 552 cpu4_opp17: opp-1612800000 { 553 opp-hz = /bits/ 64 <1612800000>; 554 opp-peak-kBps = <5412000 15052800>; 555 }; 556 557 cpu4_opp18: opp-1689600000 { 558 opp-hz = /bits/ 64 <1689600000>; 559 opp-peak-kBps = <5412000 19353600>; 560 }; 561 562 cpu4_opp19: opp-1766400000 { 563 opp-hz = /bits/ 64 <1766400000>; 564 opp-peak-kBps = <6220000 19353600>; 565 }; 566 567 cpu4_opp20: opp-1843200000 { 568 opp-hz = /bits/ 64 <1843200000>; 569 opp-peak-kBps = <6220000 19353600>; 570 }; 571 572 cpu4_opp21: opp-1920000000 { 573 opp-hz = /bits/ 64 <1920000000>; 574 opp-peak-kBps = <7216000 19353600>; 575 }; 576 577 cpu4_opp22: opp-1996800000 { 578 opp-hz = /bits/ 64 <1996800000>; 579 opp-peak-kBps = <7216000 20889600>; 580 }; 581 582 cpu4_opp23: opp-2092800000 { 583 opp-hz = /bits/ 64 <2092800000>; 584 opp-peak-kBps = <7216000 20889600>; 585 }; 586 587 cpu4_opp24: opp-2169600000 { 588 opp-hz = /bits/ 64 <2169600000>; 589 opp-peak-kBps = <7216000 20889600>; 590 }; 591 592 cpu4_opp25: opp-2246400000 { 593 opp-hz = /bits/ 64 <2246400000>; 594 opp-peak-kBps = <7216000 20889600>; 595 }; 596 597 cpu4_opp26: opp-2323200000 { 598 opp-hz = /bits/ 64 <2323200000>; 599 opp-peak-kBps = <7216000 20889600>; 600 }; 601 602 cpu4_opp27: opp-2400000000 { 603 opp-hz = /bits/ 64 <2400000000>; 604 opp-peak-kBps = <7216000 22425600>; 605 }; 606 607 cpu4_opp28: opp-2476800000 { 608 opp-hz = /bits/ 64 <2476800000>; 609 opp-peak-kBps = <7216000 22425600>; 610 }; 611 612 cpu4_opp29: opp-2553600000 { 613 opp-hz = /bits/ 64 <2553600000>; 614 opp-peak-kBps = <7216000 22425600>; 615 }; 616 617 cpu4_opp30: opp-2649600000 { 618 opp-hz = /bits/ 64 <2649600000>; 619 opp-peak-kBps = <7216000 22425600>; 620 }; 621 622 cpu4_opp31: opp-2745600000 { 623 opp-hz = /bits/ 64 <2745600000>; 624 opp-peak-kBps = <7216000 25497600>; 625 }; 626 627 cpu4_opp32: opp-2803200000 { 628 opp-hz = /bits/ 64 <2803200000>; 629 opp-peak-kBps = <7216000 25497600>; 630 }; 631 }; 632 633 dsi_opp_table: opp-table-dsi { 634 compatible = "operating-points-v2"; 635 636 opp-19200000 { 637 opp-hz = /bits/ 64 <19200000>; 638 required-opps = <&rpmhpd_opp_min_svs>; 639 }; 640 641 opp-180000000 { 642 opp-hz = /bits/ 64 <180000000>; 643 required-opps = <&rpmhpd_opp_low_svs>; 644 }; 645 646 opp-275000000 { 647 opp-hz = /bits/ 64 <275000000>; 648 required-opps = <&rpmhpd_opp_svs>; 649 }; 650 651 opp-328580000 { 652 opp-hz = /bits/ 64 <328580000>; 653 required-opps = <&rpmhpd_opp_svs_l1>; 654 }; 655 656 opp-358000000 { 657 opp-hz = /bits/ 64 <358000000>; 658 required-opps = <&rpmhpd_opp_nom>; 659 }; 660 }; 661 662 qspi_opp_table: opp-table-qspi { 663 compatible = "operating-points-v2"; 664 665 opp-19200000 { 666 opp-hz = /bits/ 64 <19200000>; 667 required-opps = <&rpmhpd_opp_min_svs>; 668 }; 669 670 opp-100000000 { 671 opp-hz = /bits/ 64 <100000000>; 672 required-opps = <&rpmhpd_opp_low_svs>; 673 }; 674 675 opp-150000000 { 676 opp-hz = /bits/ 64 <150000000>; 677 required-opps = <&rpmhpd_opp_svs>; 678 }; 679 680 opp-300000000 { 681 opp-hz = /bits/ 64 <300000000>; 682 required-opps = <&rpmhpd_opp_nom>; 683 }; 684 }; 685 686 qup_opp_table: opp-table-qup { 687 compatible = "operating-points-v2"; 688 689 opp-50000000 { 690 opp-hz = /bits/ 64 <50000000>; 691 required-opps = <&rpmhpd_opp_min_svs>; 692 }; 693 694 opp-75000000 { 695 opp-hz = /bits/ 64 <75000000>; 696 required-opps = <&rpmhpd_opp_low_svs>; 697 }; 698 699 opp-100000000 { 700 opp-hz = /bits/ 64 <100000000>; 701 required-opps = <&rpmhpd_opp_svs>; 702 }; 703 704 opp-128000000 { 705 opp-hz = /bits/ 64 <128000000>; 706 required-opps = <&rpmhpd_opp_nom>; 707 }; 708 }; 709 710 pmu { 711 compatible = "arm,armv8-pmuv3"; 712 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; 713 }; 714 715 psci: psci { 716 compatible = "arm,psci-1.0"; 717 method = "smc"; 718 719 CPU_PD0: power-domain-cpu0 { 720 #power-domain-cells = <0>; 721 power-domains = <&CLUSTER_PD>; 722 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 723 }; 724 725 CPU_PD1: power-domain-cpu1 { 726 #power-domain-cells = <0>; 727 power-domains = <&CLUSTER_PD>; 728 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 729 }; 730 731 CPU_PD2: power-domain-cpu2 { 732 #power-domain-cells = <0>; 733 power-domains = <&CLUSTER_PD>; 734 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 735 }; 736 737 CPU_PD3: power-domain-cpu3 { 738 #power-domain-cells = <0>; 739 power-domains = <&CLUSTER_PD>; 740 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 741 }; 742 743 CPU_PD4: power-domain-cpu4 { 744 #power-domain-cells = <0>; 745 power-domains = <&CLUSTER_PD>; 746 domain-idle-states = <&BIG_CPU_SLEEP_0>; 747 }; 748 749 CPU_PD5: power-domain-cpu5 { 750 #power-domain-cells = <0>; 751 power-domains = <&CLUSTER_PD>; 752 domain-idle-states = <&BIG_CPU_SLEEP_0>; 753 }; 754 755 CPU_PD6: power-domain-cpu6 { 756 #power-domain-cells = <0>; 757 power-domains = <&CLUSTER_PD>; 758 domain-idle-states = <&BIG_CPU_SLEEP_0>; 759 }; 760 761 CPU_PD7: power-domain-cpu7 { 762 #power-domain-cells = <0>; 763 power-domains = <&CLUSTER_PD>; 764 domain-idle-states = <&BIG_CPU_SLEEP_0>; 765 }; 766 767 CLUSTER_PD: power-domain-cluster { 768 #power-domain-cells = <0>; 769 domain-idle-states = <&CLUSTER_SLEEP_0>; 770 }; 771 }; 772 773 reserved-memory { 774 #address-cells = <2>; 775 #size-cells = <2>; 776 ranges; 777 778 hyp_mem: hyp-mem@85700000 { 779 reg = <0 0x85700000 0 0x600000>; 780 no-map; 781 }; 782 783 xbl_mem: xbl-mem@85e00000 { 784 reg = <0 0x85e00000 0 0x100000>; 785 no-map; 786 }; 787 788 aop_mem: aop-mem@85fc0000 { 789 reg = <0 0x85fc0000 0 0x20000>; 790 no-map; 791 }; 792 793 aop_cmd_db_mem: aop-cmd-db-mem@85fe0000 { 794 compatible = "qcom,cmd-db"; 795 reg = <0x0 0x85fe0000 0 0x20000>; 796 no-map; 797 }; 798 799 smem@86000000 { 800 compatible = "qcom,smem"; 801 reg = <0x0 0x86000000 0 0x200000>; 802 no-map; 803 hwlocks = <&tcsr_mutex 3>; 804 }; 805 806 tz_mem: tz@86200000 { 807 reg = <0 0x86200000 0 0x2d00000>; 808 no-map; 809 }; 810 811 rmtfs_mem: rmtfs@88f00000 { 812 compatible = "qcom,rmtfs-mem"; 813 reg = <0 0x88f00000 0 0x200000>; 814 no-map; 815 816 qcom,client-id = <1>; 817 qcom,vmid = <15>; 818 }; 819 820 qseecom_mem: qseecom@8ab00000 { 821 reg = <0 0x8ab00000 0 0x1400000>; 822 no-map; 823 }; 824 825 camera_mem: camera-mem@8bf00000 { 826 reg = <0 0x8bf00000 0 0x500000>; 827 no-map; 828 }; 829 830 ipa_fw_mem: ipa-fw@8c400000 { 831 reg = <0 0x8c400000 0 0x10000>; 832 no-map; 833 }; 834 835 ipa_gsi_mem: ipa-gsi@8c410000 { 836 reg = <0 0x8c410000 0 0x5000>; 837 no-map; 838 }; 839 840 gpu_mem: gpu@8c415000 { 841 reg = <0 0x8c415000 0 0x2000>; 842 no-map; 843 }; 844 845 adsp_mem: adsp@8c500000 { 846 reg = <0 0x8c500000 0 0x1a00000>; 847 no-map; 848 }; 849 850 wlan_msa_mem: wlan-msa@8df00000 { 851 reg = <0 0x8df00000 0 0x100000>; 852 no-map; 853 }; 854 855 mpss_region: mpss@8e000000 { 856 reg = <0 0x8e000000 0 0x7800000>; 857 no-map; 858 }; 859 860 venus_mem: venus@95800000 { 861 reg = <0 0x95800000 0 0x500000>; 862 no-map; 863 }; 864 865 cdsp_mem: cdsp@95d00000 { 866 reg = <0 0x95d00000 0 0x800000>; 867 no-map; 868 }; 869 870 mba_region: mba@96500000 { 871 reg = <0 0x96500000 0 0x200000>; 872 no-map; 873 }; 874 875 slpi_mem: slpi@96700000 { 876 reg = <0 0x96700000 0 0x1400000>; 877 no-map; 878 }; 879 880 spss_mem: spss@97b00000 { 881 reg = <0 0x97b00000 0 0x100000>; 882 no-map; 883 }; 884 885 mdata_mem: mpss-metadata { 886 alloc-ranges = <0 0xa0000000 0 0x20000000>; 887 size = <0 0x4000>; 888 no-map; 889 }; 890 891 fastrpc_mem: fastrpc { 892 compatible = "shared-dma-pool"; 893 alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; 894 alignment = <0x0 0x400000>; 895 size = <0x0 0x1000000>; 896 reusable; 897 }; 898 }; 899 900 adsp_pas: remoteproc-adsp { 901 compatible = "qcom,sdm845-adsp-pas"; 902 903 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 904 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 905 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 906 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 907 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 908 interrupt-names = "wdog", "fatal", "ready", 909 "handover", "stop-ack"; 910 911 clocks = <&rpmhcc RPMH_CXO_CLK>; 912 clock-names = "xo"; 913 914 memory-region = <&adsp_mem>; 915 916 qcom,qmp = <&aoss_qmp>; 917 918 qcom,smem-states = <&adsp_smp2p_out 0>; 919 qcom,smem-state-names = "stop"; 920 921 status = "disabled"; 922 923 glink-edge { 924 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 925 label = "lpass"; 926 qcom,remote-pid = <2>; 927 mboxes = <&apss_shared 8>; 928 929 apr { 930 compatible = "qcom,apr-v2"; 931 qcom,glink-channels = "apr_audio_svc"; 932 qcom,domain = <APR_DOMAIN_ADSP>; 933 #address-cells = <1>; 934 #size-cells = <0>; 935 qcom,intents = <512 20>; 936 937 service@3 { 938 reg = <APR_SVC_ADSP_CORE>; 939 compatible = "qcom,q6core"; 940 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 941 }; 942 943 q6afe: service@4 { 944 compatible = "qcom,q6afe"; 945 reg = <APR_SVC_AFE>; 946 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 947 q6afedai: dais { 948 compatible = "qcom,q6afe-dais"; 949 #address-cells = <1>; 950 #size-cells = <0>; 951 #sound-dai-cells = <1>; 952 }; 953 }; 954 955 q6asm: service@7 { 956 compatible = "qcom,q6asm"; 957 reg = <APR_SVC_ASM>; 958 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 959 q6asmdai: dais { 960 compatible = "qcom,q6asm-dais"; 961 #address-cells = <1>; 962 #size-cells = <0>; 963 #sound-dai-cells = <1>; 964 iommus = <&apps_smmu 0x1821 0x0>; 965 }; 966 }; 967 968 q6adm: service@8 { 969 compatible = "qcom,q6adm"; 970 reg = <APR_SVC_ADM>; 971 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 972 q6routing: routing { 973 compatible = "qcom,q6adm-routing"; 974 #sound-dai-cells = <0>; 975 }; 976 }; 977 }; 978 979 fastrpc { 980 compatible = "qcom,fastrpc"; 981 qcom,glink-channels = "fastrpcglink-apps-dsp"; 982 label = "adsp"; 983 qcom,non-secure-domain; 984 #address-cells = <1>; 985 #size-cells = <0>; 986 987 compute-cb@3 { 988 compatible = "qcom,fastrpc-compute-cb"; 989 reg = <3>; 990 iommus = <&apps_smmu 0x1823 0x0>; 991 }; 992 993 compute-cb@4 { 994 compatible = "qcom,fastrpc-compute-cb"; 995 reg = <4>; 996 iommus = <&apps_smmu 0x1824 0x0>; 997 }; 998 }; 999 }; 1000 }; 1001 1002 cdsp_pas: remoteproc-cdsp { 1003 compatible = "qcom,sdm845-cdsp-pas"; 1004 1005 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 1006 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1007 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1008 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1009 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 1010 interrupt-names = "wdog", "fatal", "ready", 1011 "handover", "stop-ack"; 1012 1013 clocks = <&rpmhcc RPMH_CXO_CLK>; 1014 clock-names = "xo"; 1015 1016 memory-region = <&cdsp_mem>; 1017 1018 qcom,qmp = <&aoss_qmp>; 1019 1020 qcom,smem-states = <&cdsp_smp2p_out 0>; 1021 qcom,smem-state-names = "stop"; 1022 1023 status = "disabled"; 1024 1025 glink-edge { 1026 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>; 1027 label = "turing"; 1028 qcom,remote-pid = <5>; 1029 mboxes = <&apss_shared 4>; 1030 fastrpc { 1031 compatible = "qcom,fastrpc"; 1032 qcom,glink-channels = "fastrpcglink-apps-dsp"; 1033 label = "cdsp"; 1034 qcom,non-secure-domain; 1035 #address-cells = <1>; 1036 #size-cells = <0>; 1037 1038 compute-cb@1 { 1039 compatible = "qcom,fastrpc-compute-cb"; 1040 reg = <1>; 1041 iommus = <&apps_smmu 0x1401 0x30>; 1042 }; 1043 1044 compute-cb@2 { 1045 compatible = "qcom,fastrpc-compute-cb"; 1046 reg = <2>; 1047 iommus = <&apps_smmu 0x1402 0x30>; 1048 }; 1049 1050 compute-cb@3 { 1051 compatible = "qcom,fastrpc-compute-cb"; 1052 reg = <3>; 1053 iommus = <&apps_smmu 0x1403 0x30>; 1054 }; 1055 1056 compute-cb@4 { 1057 compatible = "qcom,fastrpc-compute-cb"; 1058 reg = <4>; 1059 iommus = <&apps_smmu 0x1404 0x30>; 1060 }; 1061 1062 compute-cb@5 { 1063 compatible = "qcom,fastrpc-compute-cb"; 1064 reg = <5>; 1065 iommus = <&apps_smmu 0x1405 0x30>; 1066 }; 1067 1068 compute-cb@6 { 1069 compatible = "qcom,fastrpc-compute-cb"; 1070 reg = <6>; 1071 iommus = <&apps_smmu 0x1406 0x30>; 1072 }; 1073 1074 compute-cb@7 { 1075 compatible = "qcom,fastrpc-compute-cb"; 1076 reg = <7>; 1077 iommus = <&apps_smmu 0x1407 0x30>; 1078 }; 1079 1080 compute-cb@8 { 1081 compatible = "qcom,fastrpc-compute-cb"; 1082 reg = <8>; 1083 iommus = <&apps_smmu 0x1408 0x30>; 1084 }; 1085 }; 1086 }; 1087 }; 1088 1089 smp2p-cdsp { 1090 compatible = "qcom,smp2p"; 1091 qcom,smem = <94>, <432>; 1092 1093 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; 1094 1095 mboxes = <&apss_shared 6>; 1096 1097 qcom,local-pid = <0>; 1098 qcom,remote-pid = <5>; 1099 1100 cdsp_smp2p_out: master-kernel { 1101 qcom,entry-name = "master-kernel"; 1102 #qcom,smem-state-cells = <1>; 1103 }; 1104 1105 cdsp_smp2p_in: slave-kernel { 1106 qcom,entry-name = "slave-kernel"; 1107 1108 interrupt-controller; 1109 #interrupt-cells = <2>; 1110 }; 1111 }; 1112 1113 smp2p-lpass { 1114 compatible = "qcom,smp2p"; 1115 qcom,smem = <443>, <429>; 1116 1117 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 1118 1119 mboxes = <&apss_shared 10>; 1120 1121 qcom,local-pid = <0>; 1122 qcom,remote-pid = <2>; 1123 1124 adsp_smp2p_out: master-kernel { 1125 qcom,entry-name = "master-kernel"; 1126 #qcom,smem-state-cells = <1>; 1127 }; 1128 1129 adsp_smp2p_in: slave-kernel { 1130 qcom,entry-name = "slave-kernel"; 1131 1132 interrupt-controller; 1133 #interrupt-cells = <2>; 1134 }; 1135 }; 1136 1137 smp2p-mpss { 1138 compatible = "qcom,smp2p"; 1139 qcom,smem = <435>, <428>; 1140 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 1141 mboxes = <&apss_shared 14>; 1142 qcom,local-pid = <0>; 1143 qcom,remote-pid = <1>; 1144 1145 modem_smp2p_out: master-kernel { 1146 qcom,entry-name = "master-kernel"; 1147 #qcom,smem-state-cells = <1>; 1148 }; 1149 1150 modem_smp2p_in: slave-kernel { 1151 qcom,entry-name = "slave-kernel"; 1152 interrupt-controller; 1153 #interrupt-cells = <2>; 1154 }; 1155 1156 ipa_smp2p_out: ipa-ap-to-modem { 1157 qcom,entry-name = "ipa"; 1158 #qcom,smem-state-cells = <1>; 1159 }; 1160 1161 ipa_smp2p_in: ipa-modem-to-ap { 1162 qcom,entry-name = "ipa"; 1163 interrupt-controller; 1164 #interrupt-cells = <2>; 1165 }; 1166 }; 1167 1168 smp2p-slpi { 1169 compatible = "qcom,smp2p"; 1170 qcom,smem = <481>, <430>; 1171 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>; 1172 mboxes = <&apss_shared 26>; 1173 qcom,local-pid = <0>; 1174 qcom,remote-pid = <3>; 1175 1176 slpi_smp2p_out: master-kernel { 1177 qcom,entry-name = "master-kernel"; 1178 #qcom,smem-state-cells = <1>; 1179 }; 1180 1181 slpi_smp2p_in: slave-kernel { 1182 qcom,entry-name = "slave-kernel"; 1183 interrupt-controller; 1184 #interrupt-cells = <2>; 1185 }; 1186 }; 1187 1188 soc: soc@0 { 1189 #address-cells = <2>; 1190 #size-cells = <2>; 1191 ranges = <0 0 0 0 0x10 0>; 1192 dma-ranges = <0 0 0 0 0x10 0>; 1193 compatible = "simple-bus"; 1194 1195 gcc: clock-controller@100000 { 1196 compatible = "qcom,gcc-sdm845"; 1197 reg = <0 0x00100000 0 0x1f0000>; 1198 clocks = <&rpmhcc RPMH_CXO_CLK>, 1199 <&rpmhcc RPMH_CXO_CLK_A>, 1200 <&sleep_clk>, 1201 <&pcie0_lane>, 1202 <&pcie1_lane>; 1203 clock-names = "bi_tcxo", 1204 "bi_tcxo_ao", 1205 "sleep_clk", 1206 "pcie_0_pipe_clk", 1207 "pcie_1_pipe_clk"; 1208 #clock-cells = <1>; 1209 #reset-cells = <1>; 1210 #power-domain-cells = <1>; 1211 power-domains = <&rpmhpd SDM845_CX>; 1212 }; 1213 1214 qfprom@784000 { 1215 compatible = "qcom,sdm845-qfprom", "qcom,qfprom"; 1216 reg = <0 0x00784000 0 0x8ff>; 1217 #address-cells = <1>; 1218 #size-cells = <1>; 1219 1220 qusb2p_hstx_trim: hstx-trim-primary@1eb { 1221 reg = <0x1eb 0x1>; 1222 bits = <1 4>; 1223 }; 1224 1225 qusb2s_hstx_trim: hstx-trim-secondary@1eb { 1226 reg = <0x1eb 0x2>; 1227 bits = <6 4>; 1228 }; 1229 }; 1230 1231 rng: rng@793000 { 1232 compatible = "qcom,prng-ee"; 1233 reg = <0 0x00793000 0 0x1000>; 1234 clocks = <&gcc GCC_PRNG_AHB_CLK>; 1235 clock-names = "core"; 1236 }; 1237 1238 gpi_dma0: dma-controller@800000 { 1239 #dma-cells = <3>; 1240 compatible = "qcom,sdm845-gpi-dma"; 1241 reg = <0 0x00800000 0 0x60000>; 1242 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 1243 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 1244 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 1245 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 1246 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 1247 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 1248 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 1249 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 1250 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 1251 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 1252 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 1253 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 1254 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 1255 dma-channels = <13>; 1256 dma-channel-mask = <0xfa>; 1257 iommus = <&apps_smmu 0x0016 0x0>; 1258 status = "disabled"; 1259 }; 1260 1261 qupv3_id_0: geniqup@8c0000 { 1262 compatible = "qcom,geni-se-qup"; 1263 reg = <0 0x008c0000 0 0x6000>; 1264 clock-names = "m-ahb", "s-ahb"; 1265 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1266 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1267 iommus = <&apps_smmu 0x3 0x0>; 1268 #address-cells = <2>; 1269 #size-cells = <2>; 1270 ranges; 1271 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>; 1272 interconnect-names = "qup-core"; 1273 status = "disabled"; 1274 1275 i2c0: i2c@880000 { 1276 compatible = "qcom,geni-i2c"; 1277 reg = <0 0x00880000 0 0x4000>; 1278 clock-names = "se"; 1279 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1280 pinctrl-names = "default"; 1281 pinctrl-0 = <&qup_i2c0_default>; 1282 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1283 #address-cells = <1>; 1284 #size-cells = <0>; 1285 power-domains = <&rpmhpd SDM845_CX>; 1286 operating-points-v2 = <&qup_opp_table>; 1287 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1288 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, 1289 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; 1290 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1291 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1292 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1293 dma-names = "tx", "rx"; 1294 status = "disabled"; 1295 }; 1296 1297 spi0: spi@880000 { 1298 compatible = "qcom,geni-spi"; 1299 reg = <0 0x00880000 0 0x4000>; 1300 clock-names = "se"; 1301 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1302 pinctrl-names = "default"; 1303 pinctrl-0 = <&qup_spi0_default>; 1304 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1305 #address-cells = <1>; 1306 #size-cells = <0>; 1307 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1308 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1309 interconnect-names = "qup-core", "qup-config"; 1310 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1311 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1312 dma-names = "tx", "rx"; 1313 status = "disabled"; 1314 }; 1315 1316 uart0: serial@880000 { 1317 compatible = "qcom,geni-uart"; 1318 reg = <0 0x00880000 0 0x4000>; 1319 clock-names = "se"; 1320 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1321 pinctrl-names = "default"; 1322 pinctrl-0 = <&qup_uart0_default>; 1323 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1324 power-domains = <&rpmhpd SDM845_CX>; 1325 operating-points-v2 = <&qup_opp_table>; 1326 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1327 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1328 interconnect-names = "qup-core", "qup-config"; 1329 status = "disabled"; 1330 }; 1331 1332 i2c1: i2c@884000 { 1333 compatible = "qcom,geni-i2c"; 1334 reg = <0 0x00884000 0 0x4000>; 1335 clock-names = "se"; 1336 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1337 pinctrl-names = "default"; 1338 pinctrl-0 = <&qup_i2c1_default>; 1339 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1340 #address-cells = <1>; 1341 #size-cells = <0>; 1342 power-domains = <&rpmhpd SDM845_CX>; 1343 operating-points-v2 = <&qup_opp_table>; 1344 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1345 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, 1346 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; 1347 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1348 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1349 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1350 dma-names = "tx", "rx"; 1351 status = "disabled"; 1352 }; 1353 1354 spi1: spi@884000 { 1355 compatible = "qcom,geni-spi"; 1356 reg = <0 0x00884000 0 0x4000>; 1357 clock-names = "se"; 1358 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1359 pinctrl-names = "default"; 1360 pinctrl-0 = <&qup_spi1_default>; 1361 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1362 #address-cells = <1>; 1363 #size-cells = <0>; 1364 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1365 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1366 interconnect-names = "qup-core", "qup-config"; 1367 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1368 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1369 dma-names = "tx", "rx"; 1370 status = "disabled"; 1371 }; 1372 1373 uart1: serial@884000 { 1374 compatible = "qcom,geni-uart"; 1375 reg = <0 0x00884000 0 0x4000>; 1376 clock-names = "se"; 1377 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1378 pinctrl-names = "default"; 1379 pinctrl-0 = <&qup_uart1_default>; 1380 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1381 power-domains = <&rpmhpd SDM845_CX>; 1382 operating-points-v2 = <&qup_opp_table>; 1383 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1384 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1385 interconnect-names = "qup-core", "qup-config"; 1386 status = "disabled"; 1387 }; 1388 1389 i2c2: i2c@888000 { 1390 compatible = "qcom,geni-i2c"; 1391 reg = <0 0x00888000 0 0x4000>; 1392 clock-names = "se"; 1393 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1394 pinctrl-names = "default"; 1395 pinctrl-0 = <&qup_i2c2_default>; 1396 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1397 #address-cells = <1>; 1398 #size-cells = <0>; 1399 power-domains = <&rpmhpd SDM845_CX>; 1400 operating-points-v2 = <&qup_opp_table>; 1401 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1402 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, 1403 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; 1404 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1405 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1406 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1407 dma-names = "tx", "rx"; 1408 status = "disabled"; 1409 }; 1410 1411 spi2: spi@888000 { 1412 compatible = "qcom,geni-spi"; 1413 reg = <0 0x00888000 0 0x4000>; 1414 clock-names = "se"; 1415 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1416 pinctrl-names = "default"; 1417 pinctrl-0 = <&qup_spi2_default>; 1418 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1419 #address-cells = <1>; 1420 #size-cells = <0>; 1421 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1422 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1423 interconnect-names = "qup-core", "qup-config"; 1424 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1425 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1426 dma-names = "tx", "rx"; 1427 status = "disabled"; 1428 }; 1429 1430 uart2: serial@888000 { 1431 compatible = "qcom,geni-uart"; 1432 reg = <0 0x00888000 0 0x4000>; 1433 clock-names = "se"; 1434 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1435 pinctrl-names = "default"; 1436 pinctrl-0 = <&qup_uart2_default>; 1437 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1438 power-domains = <&rpmhpd SDM845_CX>; 1439 operating-points-v2 = <&qup_opp_table>; 1440 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1441 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1442 interconnect-names = "qup-core", "qup-config"; 1443 status = "disabled"; 1444 }; 1445 1446 i2c3: i2c@88c000 { 1447 compatible = "qcom,geni-i2c"; 1448 reg = <0 0x0088c000 0 0x4000>; 1449 clock-names = "se"; 1450 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1451 pinctrl-names = "default"; 1452 pinctrl-0 = <&qup_i2c3_default>; 1453 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1454 #address-cells = <1>; 1455 #size-cells = <0>; 1456 power-domains = <&rpmhpd SDM845_CX>; 1457 operating-points-v2 = <&qup_opp_table>; 1458 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1459 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, 1460 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; 1461 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1462 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1463 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1464 dma-names = "tx", "rx"; 1465 status = "disabled"; 1466 }; 1467 1468 spi3: spi@88c000 { 1469 compatible = "qcom,geni-spi"; 1470 reg = <0 0x0088c000 0 0x4000>; 1471 clock-names = "se"; 1472 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1473 pinctrl-names = "default"; 1474 pinctrl-0 = <&qup_spi3_default>; 1475 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1476 #address-cells = <1>; 1477 #size-cells = <0>; 1478 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1479 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1480 interconnect-names = "qup-core", "qup-config"; 1481 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1482 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1483 dma-names = "tx", "rx"; 1484 status = "disabled"; 1485 }; 1486 1487 uart3: serial@88c000 { 1488 compatible = "qcom,geni-uart"; 1489 reg = <0 0x0088c000 0 0x4000>; 1490 clock-names = "se"; 1491 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1492 pinctrl-names = "default"; 1493 pinctrl-0 = <&qup_uart3_default>; 1494 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1495 power-domains = <&rpmhpd SDM845_CX>; 1496 operating-points-v2 = <&qup_opp_table>; 1497 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1498 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1499 interconnect-names = "qup-core", "qup-config"; 1500 status = "disabled"; 1501 }; 1502 1503 i2c4: i2c@890000 { 1504 compatible = "qcom,geni-i2c"; 1505 reg = <0 0x00890000 0 0x4000>; 1506 clock-names = "se"; 1507 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1508 pinctrl-names = "default"; 1509 pinctrl-0 = <&qup_i2c4_default>; 1510 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1511 #address-cells = <1>; 1512 #size-cells = <0>; 1513 power-domains = <&rpmhpd SDM845_CX>; 1514 operating-points-v2 = <&qup_opp_table>; 1515 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1516 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, 1517 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; 1518 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1519 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1520 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1521 dma-names = "tx", "rx"; 1522 status = "disabled"; 1523 }; 1524 1525 spi4: spi@890000 { 1526 compatible = "qcom,geni-spi"; 1527 reg = <0 0x00890000 0 0x4000>; 1528 clock-names = "se"; 1529 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1530 pinctrl-names = "default"; 1531 pinctrl-0 = <&qup_spi4_default>; 1532 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1533 #address-cells = <1>; 1534 #size-cells = <0>; 1535 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1536 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1537 interconnect-names = "qup-core", "qup-config"; 1538 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1539 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1540 dma-names = "tx", "rx"; 1541 status = "disabled"; 1542 }; 1543 1544 uart4: serial@890000 { 1545 compatible = "qcom,geni-uart"; 1546 reg = <0 0x00890000 0 0x4000>; 1547 clock-names = "se"; 1548 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1549 pinctrl-names = "default"; 1550 pinctrl-0 = <&qup_uart4_default>; 1551 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1552 power-domains = <&rpmhpd SDM845_CX>; 1553 operating-points-v2 = <&qup_opp_table>; 1554 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1555 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1556 interconnect-names = "qup-core", "qup-config"; 1557 status = "disabled"; 1558 }; 1559 1560 i2c5: i2c@894000 { 1561 compatible = "qcom,geni-i2c"; 1562 reg = <0 0x00894000 0 0x4000>; 1563 clock-names = "se"; 1564 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1565 pinctrl-names = "default"; 1566 pinctrl-0 = <&qup_i2c5_default>; 1567 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1568 #address-cells = <1>; 1569 #size-cells = <0>; 1570 power-domains = <&rpmhpd SDM845_CX>; 1571 operating-points-v2 = <&qup_opp_table>; 1572 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1573 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, 1574 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; 1575 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1576 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1577 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1578 dma-names = "tx", "rx"; 1579 status = "disabled"; 1580 }; 1581 1582 spi5: spi@894000 { 1583 compatible = "qcom,geni-spi"; 1584 reg = <0 0x00894000 0 0x4000>; 1585 clock-names = "se"; 1586 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1587 pinctrl-names = "default"; 1588 pinctrl-0 = <&qup_spi5_default>; 1589 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1590 #address-cells = <1>; 1591 #size-cells = <0>; 1592 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1593 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1594 interconnect-names = "qup-core", "qup-config"; 1595 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1596 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1597 dma-names = "tx", "rx"; 1598 status = "disabled"; 1599 }; 1600 1601 uart5: serial@894000 { 1602 compatible = "qcom,geni-uart"; 1603 reg = <0 0x00894000 0 0x4000>; 1604 clock-names = "se"; 1605 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1606 pinctrl-names = "default"; 1607 pinctrl-0 = <&qup_uart5_default>; 1608 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1609 power-domains = <&rpmhpd SDM845_CX>; 1610 operating-points-v2 = <&qup_opp_table>; 1611 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1612 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1613 interconnect-names = "qup-core", "qup-config"; 1614 status = "disabled"; 1615 }; 1616 1617 i2c6: i2c@898000 { 1618 compatible = "qcom,geni-i2c"; 1619 reg = <0 0x00898000 0 0x4000>; 1620 clock-names = "se"; 1621 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1622 pinctrl-names = "default"; 1623 pinctrl-0 = <&qup_i2c6_default>; 1624 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1625 #address-cells = <1>; 1626 #size-cells = <0>; 1627 power-domains = <&rpmhpd SDM845_CX>; 1628 operating-points-v2 = <&qup_opp_table>; 1629 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1630 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, 1631 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; 1632 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1633 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1634 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1635 dma-names = "tx", "rx"; 1636 status = "disabled"; 1637 }; 1638 1639 spi6: spi@898000 { 1640 compatible = "qcom,geni-spi"; 1641 reg = <0 0x00898000 0 0x4000>; 1642 clock-names = "se"; 1643 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1644 pinctrl-names = "default"; 1645 pinctrl-0 = <&qup_spi6_default>; 1646 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1647 #address-cells = <1>; 1648 #size-cells = <0>; 1649 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1650 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1651 interconnect-names = "qup-core", "qup-config"; 1652 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1653 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1654 dma-names = "tx", "rx"; 1655 status = "disabled"; 1656 }; 1657 1658 uart6: serial@898000 { 1659 compatible = "qcom,geni-uart"; 1660 reg = <0 0x00898000 0 0x4000>; 1661 clock-names = "se"; 1662 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1663 pinctrl-names = "default"; 1664 pinctrl-0 = <&qup_uart6_default>; 1665 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1666 power-domains = <&rpmhpd SDM845_CX>; 1667 operating-points-v2 = <&qup_opp_table>; 1668 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1669 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1670 interconnect-names = "qup-core", "qup-config"; 1671 status = "disabled"; 1672 }; 1673 1674 i2c7: i2c@89c000 { 1675 compatible = "qcom,geni-i2c"; 1676 reg = <0 0x0089c000 0 0x4000>; 1677 clock-names = "se"; 1678 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1679 pinctrl-names = "default"; 1680 pinctrl-0 = <&qup_i2c7_default>; 1681 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1682 #address-cells = <1>; 1683 #size-cells = <0>; 1684 power-domains = <&rpmhpd SDM845_CX>; 1685 operating-points-v2 = <&qup_opp_table>; 1686 status = "disabled"; 1687 }; 1688 1689 spi7: spi@89c000 { 1690 compatible = "qcom,geni-spi"; 1691 reg = <0 0x0089c000 0 0x4000>; 1692 clock-names = "se"; 1693 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1694 pinctrl-names = "default"; 1695 pinctrl-0 = <&qup_spi7_default>; 1696 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1697 #address-cells = <1>; 1698 #size-cells = <0>; 1699 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1700 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1701 interconnect-names = "qup-core", "qup-config"; 1702 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1703 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1704 dma-names = "tx", "rx"; 1705 status = "disabled"; 1706 }; 1707 1708 uart7: serial@89c000 { 1709 compatible = "qcom,geni-uart"; 1710 reg = <0 0x0089c000 0 0x4000>; 1711 clock-names = "se"; 1712 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1713 pinctrl-names = "default"; 1714 pinctrl-0 = <&qup_uart7_default>; 1715 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1716 power-domains = <&rpmhpd SDM845_CX>; 1717 operating-points-v2 = <&qup_opp_table>; 1718 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1719 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1720 interconnect-names = "qup-core", "qup-config"; 1721 status = "disabled"; 1722 }; 1723 }; 1724 1725 gpi_dma1: dma-controller@a00000 { 1726 #dma-cells = <3>; 1727 compatible = "qcom,sdm845-gpi-dma"; 1728 reg = <0 0x00a00000 0 0x60000>; 1729 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1730 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1731 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1732 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1733 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1734 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1735 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1736 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1737 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1738 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1739 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1740 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 1741 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 1742 dma-channels = <13>; 1743 dma-channel-mask = <0xfa>; 1744 iommus = <&apps_smmu 0x06d6 0x0>; 1745 status = "disabled"; 1746 }; 1747 1748 qupv3_id_1: geniqup@ac0000 { 1749 compatible = "qcom,geni-se-qup"; 1750 reg = <0 0x00ac0000 0 0x6000>; 1751 clock-names = "m-ahb", "s-ahb"; 1752 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1753 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1754 iommus = <&apps_smmu 0x6c3 0x0>; 1755 #address-cells = <2>; 1756 #size-cells = <2>; 1757 ranges; 1758 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>; 1759 interconnect-names = "qup-core"; 1760 status = "disabled"; 1761 1762 i2c8: i2c@a80000 { 1763 compatible = "qcom,geni-i2c"; 1764 reg = <0 0x00a80000 0 0x4000>; 1765 clock-names = "se"; 1766 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1767 pinctrl-names = "default"; 1768 pinctrl-0 = <&qup_i2c8_default>; 1769 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1770 #address-cells = <1>; 1771 #size-cells = <0>; 1772 power-domains = <&rpmhpd SDM845_CX>; 1773 operating-points-v2 = <&qup_opp_table>; 1774 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1775 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 1776 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 1777 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1778 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1779 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1780 dma-names = "tx", "rx"; 1781 status = "disabled"; 1782 }; 1783 1784 spi8: spi@a80000 { 1785 compatible = "qcom,geni-spi"; 1786 reg = <0 0x00a80000 0 0x4000>; 1787 clock-names = "se"; 1788 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1789 pinctrl-names = "default"; 1790 pinctrl-0 = <&qup_spi8_default>; 1791 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1792 #address-cells = <1>; 1793 #size-cells = <0>; 1794 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1795 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1796 interconnect-names = "qup-core", "qup-config"; 1797 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1798 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1799 dma-names = "tx", "rx"; 1800 status = "disabled"; 1801 }; 1802 1803 uart8: serial@a80000 { 1804 compatible = "qcom,geni-uart"; 1805 reg = <0 0x00a80000 0 0x4000>; 1806 clock-names = "se"; 1807 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1808 pinctrl-names = "default"; 1809 pinctrl-0 = <&qup_uart8_default>; 1810 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1811 power-domains = <&rpmhpd SDM845_CX>; 1812 operating-points-v2 = <&qup_opp_table>; 1813 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1814 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1815 interconnect-names = "qup-core", "qup-config"; 1816 status = "disabled"; 1817 }; 1818 1819 i2c9: i2c@a84000 { 1820 compatible = "qcom,geni-i2c"; 1821 reg = <0 0x00a84000 0 0x4000>; 1822 clock-names = "se"; 1823 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1824 pinctrl-names = "default"; 1825 pinctrl-0 = <&qup_i2c9_default>; 1826 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1827 #address-cells = <1>; 1828 #size-cells = <0>; 1829 power-domains = <&rpmhpd SDM845_CX>; 1830 operating-points-v2 = <&qup_opp_table>; 1831 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1832 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 1833 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 1834 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1835 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1836 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1837 dma-names = "tx", "rx"; 1838 status = "disabled"; 1839 }; 1840 1841 spi9: spi@a84000 { 1842 compatible = "qcom,geni-spi"; 1843 reg = <0 0x00a84000 0 0x4000>; 1844 clock-names = "se"; 1845 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1846 pinctrl-names = "default"; 1847 pinctrl-0 = <&qup_spi9_default>; 1848 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1849 #address-cells = <1>; 1850 #size-cells = <0>; 1851 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1852 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1853 interconnect-names = "qup-core", "qup-config"; 1854 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1855 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1856 dma-names = "tx", "rx"; 1857 status = "disabled"; 1858 }; 1859 1860 uart9: serial@a84000 { 1861 compatible = "qcom,geni-debug-uart"; 1862 reg = <0 0x00a84000 0 0x4000>; 1863 clock-names = "se"; 1864 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1865 pinctrl-names = "default"; 1866 pinctrl-0 = <&qup_uart9_default>; 1867 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1868 power-domains = <&rpmhpd SDM845_CX>; 1869 operating-points-v2 = <&qup_opp_table>; 1870 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1871 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1872 interconnect-names = "qup-core", "qup-config"; 1873 status = "disabled"; 1874 }; 1875 1876 i2c10: i2c@a88000 { 1877 compatible = "qcom,geni-i2c"; 1878 reg = <0 0x00a88000 0 0x4000>; 1879 clock-names = "se"; 1880 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1881 pinctrl-names = "default"; 1882 pinctrl-0 = <&qup_i2c10_default>; 1883 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1884 #address-cells = <1>; 1885 #size-cells = <0>; 1886 power-domains = <&rpmhpd SDM845_CX>; 1887 operating-points-v2 = <&qup_opp_table>; 1888 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1889 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 1890 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 1891 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1892 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1893 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1894 dma-names = "tx", "rx"; 1895 status = "disabled"; 1896 }; 1897 1898 spi10: spi@a88000 { 1899 compatible = "qcom,geni-spi"; 1900 reg = <0 0x00a88000 0 0x4000>; 1901 clock-names = "se"; 1902 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1903 pinctrl-names = "default"; 1904 pinctrl-0 = <&qup_spi10_default>; 1905 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1906 #address-cells = <1>; 1907 #size-cells = <0>; 1908 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1909 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1910 interconnect-names = "qup-core", "qup-config"; 1911 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1912 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1913 dma-names = "tx", "rx"; 1914 status = "disabled"; 1915 }; 1916 1917 uart10: serial@a88000 { 1918 compatible = "qcom,geni-uart"; 1919 reg = <0 0x00a88000 0 0x4000>; 1920 clock-names = "se"; 1921 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1922 pinctrl-names = "default"; 1923 pinctrl-0 = <&qup_uart10_default>; 1924 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1925 power-domains = <&rpmhpd SDM845_CX>; 1926 operating-points-v2 = <&qup_opp_table>; 1927 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1928 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1929 interconnect-names = "qup-core", "qup-config"; 1930 status = "disabled"; 1931 }; 1932 1933 i2c11: i2c@a8c000 { 1934 compatible = "qcom,geni-i2c"; 1935 reg = <0 0x00a8c000 0 0x4000>; 1936 clock-names = "se"; 1937 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1938 pinctrl-names = "default"; 1939 pinctrl-0 = <&qup_i2c11_default>; 1940 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1941 #address-cells = <1>; 1942 #size-cells = <0>; 1943 power-domains = <&rpmhpd SDM845_CX>; 1944 operating-points-v2 = <&qup_opp_table>; 1945 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1946 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 1947 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 1948 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1949 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1950 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1951 dma-names = "tx", "rx"; 1952 status = "disabled"; 1953 }; 1954 1955 spi11: spi@a8c000 { 1956 compatible = "qcom,geni-spi"; 1957 reg = <0 0x00a8c000 0 0x4000>; 1958 clock-names = "se"; 1959 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1960 pinctrl-names = "default"; 1961 pinctrl-0 = <&qup_spi11_default>; 1962 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1963 #address-cells = <1>; 1964 #size-cells = <0>; 1965 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1966 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1967 interconnect-names = "qup-core", "qup-config"; 1968 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1969 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1970 dma-names = "tx", "rx"; 1971 status = "disabled"; 1972 }; 1973 1974 uart11: serial@a8c000 { 1975 compatible = "qcom,geni-uart"; 1976 reg = <0 0x00a8c000 0 0x4000>; 1977 clock-names = "se"; 1978 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1979 pinctrl-names = "default"; 1980 pinctrl-0 = <&qup_uart11_default>; 1981 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1982 power-domains = <&rpmhpd SDM845_CX>; 1983 operating-points-v2 = <&qup_opp_table>; 1984 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1985 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1986 interconnect-names = "qup-core", "qup-config"; 1987 status = "disabled"; 1988 }; 1989 1990 i2c12: i2c@a90000 { 1991 compatible = "qcom,geni-i2c"; 1992 reg = <0 0x00a90000 0 0x4000>; 1993 clock-names = "se"; 1994 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1995 pinctrl-names = "default"; 1996 pinctrl-0 = <&qup_i2c12_default>; 1997 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1998 #address-cells = <1>; 1999 #size-cells = <0>; 2000 power-domains = <&rpmhpd SDM845_CX>; 2001 operating-points-v2 = <&qup_opp_table>; 2002 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2003 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 2004 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 2005 interconnect-names = "qup-core", "qup-config", "qup-memory"; 2006 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 2007 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 2008 dma-names = "tx", "rx"; 2009 status = "disabled"; 2010 }; 2011 2012 spi12: spi@a90000 { 2013 compatible = "qcom,geni-spi"; 2014 reg = <0 0x00a90000 0 0x4000>; 2015 clock-names = "se"; 2016 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 2017 pinctrl-names = "default"; 2018 pinctrl-0 = <&qup_spi12_default>; 2019 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 2020 #address-cells = <1>; 2021 #size-cells = <0>; 2022 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2023 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 2024 interconnect-names = "qup-core", "qup-config"; 2025 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 2026 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 2027 dma-names = "tx", "rx"; 2028 status = "disabled"; 2029 }; 2030 2031 uart12: serial@a90000 { 2032 compatible = "qcom,geni-uart"; 2033 reg = <0 0x00a90000 0 0x4000>; 2034 clock-names = "se"; 2035 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 2036 pinctrl-names = "default"; 2037 pinctrl-0 = <&qup_uart12_default>; 2038 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 2039 power-domains = <&rpmhpd SDM845_CX>; 2040 operating-points-v2 = <&qup_opp_table>; 2041 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2042 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 2043 interconnect-names = "qup-core", "qup-config"; 2044 status = "disabled"; 2045 }; 2046 2047 i2c13: i2c@a94000 { 2048 compatible = "qcom,geni-i2c"; 2049 reg = <0 0x00a94000 0 0x4000>; 2050 clock-names = "se"; 2051 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 2052 pinctrl-names = "default"; 2053 pinctrl-0 = <&qup_i2c13_default>; 2054 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 2055 #address-cells = <1>; 2056 #size-cells = <0>; 2057 power-domains = <&rpmhpd SDM845_CX>; 2058 operating-points-v2 = <&qup_opp_table>; 2059 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2060 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 2061 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 2062 interconnect-names = "qup-core", "qup-config", "qup-memory"; 2063 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 2064 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 2065 dma-names = "tx", "rx"; 2066 status = "disabled"; 2067 }; 2068 2069 spi13: spi@a94000 { 2070 compatible = "qcom,geni-spi"; 2071 reg = <0 0x00a94000 0 0x4000>; 2072 clock-names = "se"; 2073 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 2074 pinctrl-names = "default"; 2075 pinctrl-0 = <&qup_spi13_default>; 2076 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 2077 #address-cells = <1>; 2078 #size-cells = <0>; 2079 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2080 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 2081 interconnect-names = "qup-core", "qup-config"; 2082 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 2083 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 2084 dma-names = "tx", "rx"; 2085 status = "disabled"; 2086 }; 2087 2088 uart13: serial@a94000 { 2089 compatible = "qcom,geni-uart"; 2090 reg = <0 0x00a94000 0 0x4000>; 2091 clock-names = "se"; 2092 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 2093 pinctrl-names = "default"; 2094 pinctrl-0 = <&qup_uart13_default>; 2095 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 2096 power-domains = <&rpmhpd SDM845_CX>; 2097 operating-points-v2 = <&qup_opp_table>; 2098 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2099 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 2100 interconnect-names = "qup-core", "qup-config"; 2101 status = "disabled"; 2102 }; 2103 2104 i2c14: i2c@a98000 { 2105 compatible = "qcom,geni-i2c"; 2106 reg = <0 0x00a98000 0 0x4000>; 2107 clock-names = "se"; 2108 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2109 pinctrl-names = "default"; 2110 pinctrl-0 = <&qup_i2c14_default>; 2111 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 2112 #address-cells = <1>; 2113 #size-cells = <0>; 2114 power-domains = <&rpmhpd SDM845_CX>; 2115 operating-points-v2 = <&qup_opp_table>; 2116 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2117 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 2118 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 2119 interconnect-names = "qup-core", "qup-config", "qup-memory"; 2120 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 2121 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 2122 dma-names = "tx", "rx"; 2123 status = "disabled"; 2124 }; 2125 2126 spi14: spi@a98000 { 2127 compatible = "qcom,geni-spi"; 2128 reg = <0 0x00a98000 0 0x4000>; 2129 clock-names = "se"; 2130 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2131 pinctrl-names = "default"; 2132 pinctrl-0 = <&qup_spi14_default>; 2133 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 2134 #address-cells = <1>; 2135 #size-cells = <0>; 2136 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2137 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 2138 interconnect-names = "qup-core", "qup-config"; 2139 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 2140 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 2141 dma-names = "tx", "rx"; 2142 status = "disabled"; 2143 }; 2144 2145 uart14: serial@a98000 { 2146 compatible = "qcom,geni-uart"; 2147 reg = <0 0x00a98000 0 0x4000>; 2148 clock-names = "se"; 2149 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2150 pinctrl-names = "default"; 2151 pinctrl-0 = <&qup_uart14_default>; 2152 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 2153 power-domains = <&rpmhpd SDM845_CX>; 2154 operating-points-v2 = <&qup_opp_table>; 2155 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2156 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 2157 interconnect-names = "qup-core", "qup-config"; 2158 status = "disabled"; 2159 }; 2160 2161 i2c15: i2c@a9c000 { 2162 compatible = "qcom,geni-i2c"; 2163 reg = <0 0x00a9c000 0 0x4000>; 2164 clock-names = "se"; 2165 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2166 pinctrl-names = "default"; 2167 pinctrl-0 = <&qup_i2c15_default>; 2168 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 2169 #address-cells = <1>; 2170 #size-cells = <0>; 2171 power-domains = <&rpmhpd SDM845_CX>; 2172 operating-points-v2 = <&qup_opp_table>; 2173 status = "disabled"; 2174 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2175 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 2176 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 2177 interconnect-names = "qup-core", "qup-config", "qup-memory"; 2178 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, 2179 <&gpi_dma1 1 7 QCOM_GPI_I2C>; 2180 dma-names = "tx", "rx"; 2181 }; 2182 2183 spi15: spi@a9c000 { 2184 compatible = "qcom,geni-spi"; 2185 reg = <0 0x00a9c000 0 0x4000>; 2186 clock-names = "se"; 2187 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2188 pinctrl-names = "default"; 2189 pinctrl-0 = <&qup_spi15_default>; 2190 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 2191 #address-cells = <1>; 2192 #size-cells = <0>; 2193 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2194 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 2195 interconnect-names = "qup-core", "qup-config"; 2196 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, 2197 <&gpi_dma1 1 7 QCOM_GPI_SPI>; 2198 dma-names = "tx", "rx"; 2199 status = "disabled"; 2200 }; 2201 2202 uart15: serial@a9c000 { 2203 compatible = "qcom,geni-uart"; 2204 reg = <0 0x00a9c000 0 0x4000>; 2205 clock-names = "se"; 2206 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2207 pinctrl-names = "default"; 2208 pinctrl-0 = <&qup_uart15_default>; 2209 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 2210 power-domains = <&rpmhpd SDM845_CX>; 2211 operating-points-v2 = <&qup_opp_table>; 2212 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2213 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 2214 interconnect-names = "qup-core", "qup-config"; 2215 status = "disabled"; 2216 }; 2217 }; 2218 2219 llcc: system-cache-controller@1100000 { 2220 compatible = "qcom,sdm845-llcc"; 2221 reg = <0 0x01100000 0 0x45000>, <0 0x01180000 0 0x50000>, 2222 <0 0x01200000 0 0x50000>, <0 0x01280000 0 0x50000>, 2223 <0 0x01300000 0 0x50000>; 2224 reg-names = "llcc0_base", "llcc1_base", "llcc2_base", 2225 "llcc3_base", "llcc_broadcast_base"; 2226 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 2227 }; 2228 2229 dma@10a2000 { 2230 compatible = "qcom,sdm845-dcc", "qcom,dcc"; 2231 reg = <0x0 0x010a2000 0x0 0x1000>, 2232 <0x0 0x010ae000 0x0 0x2000>; 2233 }; 2234 2235 pmu@114a000 { 2236 compatible = "qcom,sdm845-llcc-bwmon"; 2237 reg = <0 0x0114a000 0 0x1000>; 2238 interrupts = <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>; 2239 interconnects = <&mem_noc MASTER_LLCC 3 &mem_noc SLAVE_EBI1 3>; 2240 2241 operating-points-v2 = <&llcc_bwmon_opp_table>; 2242 2243 llcc_bwmon_opp_table: opp-table { 2244 compatible = "operating-points-v2"; 2245 2246 /* 2247 * The interconnect path bandwidth taken from 2248 * cpu4_opp_table bandwidth for gladiator_noc-mem_noc 2249 * interconnect. This also matches the 2250 * bandwidth table of qcom,llccbw (qcom,bw-tbl, 2251 * bus width: 4 bytes) from msm-4.9 downstream 2252 * kernel. 2253 */ 2254 opp-0 { 2255 opp-peak-kBps = <800000>; 2256 }; 2257 opp-1 { 2258 opp-peak-kBps = <1804000>; 2259 }; 2260 opp-2 { 2261 opp-peak-kBps = <3072000>; 2262 }; 2263 opp-3 { 2264 opp-peak-kBps = <5412000>; 2265 }; 2266 opp-4 { 2267 opp-peak-kBps = <7216000>; 2268 }; 2269 }; 2270 }; 2271 2272 pmu@1436400 { 2273 compatible = "qcom,sdm845-cpu-bwmon", "qcom,sdm845-bwmon"; 2274 reg = <0 0x01436400 0 0x600>; 2275 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 2276 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_LLCC 3>; 2277 2278 operating-points-v2 = <&cpu_bwmon_opp_table>; 2279 2280 cpu_bwmon_opp_table: opp-table { 2281 compatible = "operating-points-v2"; 2282 2283 /* 2284 * The interconnect path bandwidth taken from 2285 * cpu4_opp_table bandwidth for OSM L3 2286 * interconnect. This also matches the OSM L3 2287 * from bandwidth table of qcom,cpu4-l3lat-mon 2288 * (qcom,core-dev-table, bus width: 16 bytes) 2289 * from msm-4.9 downstream kernel. 2290 */ 2291 opp-0 { 2292 opp-peak-kBps = <4800000>; 2293 }; 2294 opp-1 { 2295 opp-peak-kBps = <9216000>; 2296 }; 2297 opp-2 { 2298 opp-peak-kBps = <15052800>; 2299 }; 2300 opp-3 { 2301 opp-peak-kBps = <20889600>; 2302 }; 2303 opp-4 { 2304 opp-peak-kBps = <25497600>; 2305 }; 2306 }; 2307 }; 2308 2309 pcie0: pci@1c00000 { 2310 compatible = "qcom,pcie-sdm845"; 2311 reg = <0 0x01c00000 0 0x2000>, 2312 <0 0x60000000 0 0xf1d>, 2313 <0 0x60000f20 0 0xa8>, 2314 <0 0x60100000 0 0x100000>, 2315 <0 0x01c07000 0 0x1000>; 2316 reg-names = "parf", "dbi", "elbi", "config", "mhi"; 2317 device_type = "pci"; 2318 linux,pci-domain = <0>; 2319 bus-range = <0x00 0xff>; 2320 num-lanes = <1>; 2321 2322 #address-cells = <3>; 2323 #size-cells = <2>; 2324 2325 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 2326 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0xd00000>; 2327 2328 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 2329 interrupt-names = "msi"; 2330 #interrupt-cells = <1>; 2331 interrupt-map-mask = <0 0 0 0x7>; 2332 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 2333 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 2334 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 2335 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 2336 2337 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 2338 <&gcc GCC_PCIE_0_AUX_CLK>, 2339 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 2340 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 2341 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 2342 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 2343 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; 2344 clock-names = "pipe", 2345 "aux", 2346 "cfg", 2347 "bus_master", 2348 "bus_slave", 2349 "slave_q2a", 2350 "tbu"; 2351 2352 iommu-map = <0x0 &apps_smmu 0x1c10 0x1>, 2353 <0x100 &apps_smmu 0x1c11 0x1>, 2354 <0x200 &apps_smmu 0x1c12 0x1>, 2355 <0x300 &apps_smmu 0x1c13 0x1>, 2356 <0x400 &apps_smmu 0x1c14 0x1>, 2357 <0x500 &apps_smmu 0x1c15 0x1>, 2358 <0x600 &apps_smmu 0x1c16 0x1>, 2359 <0x700 &apps_smmu 0x1c17 0x1>, 2360 <0x800 &apps_smmu 0x1c18 0x1>, 2361 <0x900 &apps_smmu 0x1c19 0x1>, 2362 <0xa00 &apps_smmu 0x1c1a 0x1>, 2363 <0xb00 &apps_smmu 0x1c1b 0x1>, 2364 <0xc00 &apps_smmu 0x1c1c 0x1>, 2365 <0xd00 &apps_smmu 0x1c1d 0x1>, 2366 <0xe00 &apps_smmu 0x1c1e 0x1>, 2367 <0xf00 &apps_smmu 0x1c1f 0x1>; 2368 2369 resets = <&gcc GCC_PCIE_0_BCR>; 2370 reset-names = "pci"; 2371 2372 power-domains = <&gcc PCIE_0_GDSC>; 2373 2374 phys = <&pcie0_lane>; 2375 phy-names = "pciephy"; 2376 2377 status = "disabled"; 2378 }; 2379 2380 pcie0_phy: phy@1c06000 { 2381 compatible = "qcom,sdm845-qmp-pcie-phy"; 2382 reg = <0 0x01c06000 0 0x18c>; 2383 #address-cells = <2>; 2384 #size-cells = <2>; 2385 ranges; 2386 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 2387 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 2388 <&gcc GCC_PCIE_0_CLKREF_CLK>, 2389 <&gcc GCC_PCIE_PHY_REFGEN_CLK>; 2390 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 2391 2392 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 2393 reset-names = "phy"; 2394 2395 assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>; 2396 assigned-clock-rates = <100000000>; 2397 2398 status = "disabled"; 2399 2400 pcie0_lane: phy@1c06200 { 2401 reg = <0 0x01c06200 0 0x128>, 2402 <0 0x01c06400 0 0x1fc>, 2403 <0 0x01c06800 0 0x218>, 2404 <0 0x01c06600 0 0x70>; 2405 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 2406 clock-names = "pipe0"; 2407 2408 #clock-cells = <0>; 2409 #phy-cells = <0>; 2410 clock-output-names = "pcie_0_pipe_clk"; 2411 }; 2412 }; 2413 2414 pcie1: pci@1c08000 { 2415 compatible = "qcom,pcie-sdm845"; 2416 reg = <0 0x01c08000 0 0x2000>, 2417 <0 0x40000000 0 0xf1d>, 2418 <0 0x40000f20 0 0xa8>, 2419 <0 0x40100000 0 0x100000>, 2420 <0 0x01c0c000 0 0x1000>; 2421 reg-names = "parf", "dbi", "elbi", "config", "mhi"; 2422 device_type = "pci"; 2423 linux,pci-domain = <1>; 2424 bus-range = <0x00 0xff>; 2425 num-lanes = <1>; 2426 2427 #address-cells = <3>; 2428 #size-cells = <2>; 2429 2430 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 2431 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 2432 2433 interrupts = <GIC_SPI 307 IRQ_TYPE_EDGE_RISING>; 2434 interrupt-names = "msi"; 2435 #interrupt-cells = <1>; 2436 interrupt-map-mask = <0 0 0 0x7>; 2437 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 2438 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 2439 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 2440 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 2441 2442 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 2443 <&gcc GCC_PCIE_1_AUX_CLK>, 2444 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2445 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 2446 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 2447 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 2448 <&gcc GCC_PCIE_1_CLKREF_CLK>, 2449 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; 2450 clock-names = "pipe", 2451 "aux", 2452 "cfg", 2453 "bus_master", 2454 "bus_slave", 2455 "slave_q2a", 2456 "ref", 2457 "tbu"; 2458 2459 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 2460 assigned-clock-rates = <19200000>; 2461 2462 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, 2463 <0x100 &apps_smmu 0x1c01 0x1>, 2464 <0x200 &apps_smmu 0x1c02 0x1>, 2465 <0x300 &apps_smmu 0x1c03 0x1>, 2466 <0x400 &apps_smmu 0x1c04 0x1>, 2467 <0x500 &apps_smmu 0x1c05 0x1>, 2468 <0x600 &apps_smmu 0x1c06 0x1>, 2469 <0x700 &apps_smmu 0x1c07 0x1>, 2470 <0x800 &apps_smmu 0x1c08 0x1>, 2471 <0x900 &apps_smmu 0x1c09 0x1>, 2472 <0xa00 &apps_smmu 0x1c0a 0x1>, 2473 <0xb00 &apps_smmu 0x1c0b 0x1>, 2474 <0xc00 &apps_smmu 0x1c0c 0x1>, 2475 <0xd00 &apps_smmu 0x1c0d 0x1>, 2476 <0xe00 &apps_smmu 0x1c0e 0x1>, 2477 <0xf00 &apps_smmu 0x1c0f 0x1>; 2478 2479 resets = <&gcc GCC_PCIE_1_BCR>; 2480 reset-names = "pci"; 2481 2482 power-domains = <&gcc PCIE_1_GDSC>; 2483 2484 phys = <&pcie1_lane>; 2485 phy-names = "pciephy"; 2486 2487 status = "disabled"; 2488 }; 2489 2490 pcie1_phy: phy@1c0a000 { 2491 compatible = "qcom,sdm845-qhp-pcie-phy"; 2492 reg = <0 0x01c0a000 0 0x800>; 2493 #address-cells = <2>; 2494 #size-cells = <2>; 2495 ranges; 2496 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 2497 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2498 <&gcc GCC_PCIE_1_CLKREF_CLK>, 2499 <&gcc GCC_PCIE_PHY_REFGEN_CLK>; 2500 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 2501 2502 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 2503 reset-names = "phy"; 2504 2505 assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>; 2506 assigned-clock-rates = <100000000>; 2507 2508 status = "disabled"; 2509 2510 pcie1_lane: phy@1c06200 { 2511 reg = <0 0x01c0a800 0 0x800>, 2512 <0 0x01c0a800 0 0x800>, 2513 <0 0x01c0b800 0 0x400>; 2514 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 2515 clock-names = "pipe0"; 2516 2517 #clock-cells = <0>; 2518 #phy-cells = <0>; 2519 clock-output-names = "pcie_1_pipe_clk"; 2520 }; 2521 }; 2522 2523 mem_noc: interconnect@1380000 { 2524 compatible = "qcom,sdm845-mem-noc"; 2525 reg = <0 0x01380000 0 0x27200>; 2526 #interconnect-cells = <2>; 2527 qcom,bcm-voters = <&apps_bcm_voter>; 2528 }; 2529 2530 dc_noc: interconnect@14e0000 { 2531 compatible = "qcom,sdm845-dc-noc"; 2532 reg = <0 0x014e0000 0 0x400>; 2533 #interconnect-cells = <2>; 2534 qcom,bcm-voters = <&apps_bcm_voter>; 2535 }; 2536 2537 config_noc: interconnect@1500000 { 2538 compatible = "qcom,sdm845-config-noc"; 2539 reg = <0 0x01500000 0 0x5080>; 2540 #interconnect-cells = <2>; 2541 qcom,bcm-voters = <&apps_bcm_voter>; 2542 }; 2543 2544 system_noc: interconnect@1620000 { 2545 compatible = "qcom,sdm845-system-noc"; 2546 reg = <0 0x01620000 0 0x18080>; 2547 #interconnect-cells = <2>; 2548 qcom,bcm-voters = <&apps_bcm_voter>; 2549 }; 2550 2551 aggre1_noc: interconnect@16e0000 { 2552 compatible = "qcom,sdm845-aggre1-noc"; 2553 reg = <0 0x016e0000 0 0x15080>; 2554 #interconnect-cells = <2>; 2555 qcom,bcm-voters = <&apps_bcm_voter>; 2556 }; 2557 2558 aggre2_noc: interconnect@1700000 { 2559 compatible = "qcom,sdm845-aggre2-noc"; 2560 reg = <0 0x01700000 0 0x1f300>; 2561 #interconnect-cells = <2>; 2562 qcom,bcm-voters = <&apps_bcm_voter>; 2563 }; 2564 2565 mmss_noc: interconnect@1740000 { 2566 compatible = "qcom,sdm845-mmss-noc"; 2567 reg = <0 0x01740000 0 0x1c100>; 2568 #interconnect-cells = <2>; 2569 qcom,bcm-voters = <&apps_bcm_voter>; 2570 }; 2571 2572 ufs_mem_hc: ufshc@1d84000 { 2573 compatible = "qcom,sdm845-ufshc", "qcom,ufshc", 2574 "jedec,ufs-2.0"; 2575 reg = <0 0x01d84000 0 0x2500>, 2576 <0 0x01d90000 0 0x8000>; 2577 reg-names = "std", "ice"; 2578 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2579 phys = <&ufs_mem_phy_lanes>; 2580 phy-names = "ufsphy"; 2581 lanes-per-direction = <2>; 2582 power-domains = <&gcc UFS_PHY_GDSC>; 2583 #reset-cells = <1>; 2584 resets = <&gcc GCC_UFS_PHY_BCR>; 2585 reset-names = "rst"; 2586 2587 iommus = <&apps_smmu 0x100 0xf>; 2588 2589 clock-names = 2590 "core_clk", 2591 "bus_aggr_clk", 2592 "iface_clk", 2593 "core_clk_unipro", 2594 "ref_clk", 2595 "tx_lane0_sync_clk", 2596 "rx_lane0_sync_clk", 2597 "rx_lane1_sync_clk", 2598 "ice_core_clk"; 2599 clocks = 2600 <&gcc GCC_UFS_PHY_AXI_CLK>, 2601 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2602 <&gcc GCC_UFS_PHY_AHB_CLK>, 2603 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2604 <&rpmhcc RPMH_CXO_CLK>, 2605 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2606 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2607 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, 2608 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 2609 freq-table-hz = 2610 <50000000 200000000>, 2611 <0 0>, 2612 <0 0>, 2613 <37500000 150000000>, 2614 <0 0>, 2615 <0 0>, 2616 <0 0>, 2617 <0 0>, 2618 <75000000 300000000>; 2619 2620 interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mem_noc SLAVE_EBI1 0>, 2621 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>; 2622 interconnect-names = "ufs-ddr", "cpu-ufs"; 2623 2624 status = "disabled"; 2625 }; 2626 2627 ufs_mem_phy: phy@1d87000 { 2628 compatible = "qcom,sdm845-qmp-ufs-phy"; 2629 reg = <0 0x01d87000 0 0x18c>; 2630 #address-cells = <2>; 2631 #size-cells = <2>; 2632 ranges; 2633 clock-names = "ref", 2634 "ref_aux"; 2635 clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, 2636 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 2637 2638 power-domains = <&gcc UFS_PHY_GDSC>; 2639 2640 resets = <&ufs_mem_hc 0>; 2641 reset-names = "ufsphy"; 2642 status = "disabled"; 2643 2644 ufs_mem_phy_lanes: phy@1d87400 { 2645 reg = <0 0x01d87400 0 0x108>, 2646 <0 0x01d87600 0 0x1e0>, 2647 <0 0x01d87c00 0 0x1dc>, 2648 <0 0x01d87800 0 0x108>, 2649 <0 0x01d87a00 0 0x1e0>; 2650 #phy-cells = <0>; 2651 }; 2652 }; 2653 2654 cryptobam: dma-controller@1dc4000 { 2655 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 2656 reg = <0 0x01dc4000 0 0x24000>; 2657 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 2658 clocks = <&rpmhcc RPMH_CE_CLK>; 2659 clock-names = "bam_clk"; 2660 #dma-cells = <1>; 2661 qcom,ee = <0>; 2662 qcom,controlled-remotely; 2663 iommus = <&apps_smmu 0x704 0x1>, 2664 <&apps_smmu 0x706 0x1>, 2665 <&apps_smmu 0x714 0x1>, 2666 <&apps_smmu 0x716 0x1>; 2667 }; 2668 2669 crypto: crypto@1dfa000 { 2670 compatible = "qcom,crypto-v5.4"; 2671 reg = <0 0x01dfa000 0 0x6000>; 2672 clocks = <&gcc GCC_CE1_AHB_CLK>, 2673 <&gcc GCC_CE1_AXI_CLK>, 2674 <&rpmhcc RPMH_CE_CLK>; 2675 clock-names = "iface", "bus", "core"; 2676 dmas = <&cryptobam 6>, <&cryptobam 7>; 2677 dma-names = "rx", "tx"; 2678 iommus = <&apps_smmu 0x704 0x1>, 2679 <&apps_smmu 0x706 0x1>, 2680 <&apps_smmu 0x714 0x1>, 2681 <&apps_smmu 0x716 0x1>; 2682 }; 2683 2684 ipa: ipa@1e40000 { 2685 compatible = "qcom,sdm845-ipa"; 2686 2687 iommus = <&apps_smmu 0x720 0x0>, 2688 <&apps_smmu 0x722 0x0>; 2689 reg = <0 0x01e40000 0 0x7000>, 2690 <0 0x01e47000 0 0x2000>, 2691 <0 0x01e04000 0 0x2c000>; 2692 reg-names = "ipa-reg", 2693 "ipa-shared", 2694 "gsi"; 2695 2696 interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>, 2697 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 2698 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2699 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 2700 interrupt-names = "ipa", 2701 "gsi", 2702 "ipa-clock-query", 2703 "ipa-setup-ready"; 2704 2705 clocks = <&rpmhcc RPMH_IPA_CLK>; 2706 clock-names = "core"; 2707 2708 interconnects = <&aggre2_noc MASTER_IPA 0 &mem_noc SLAVE_EBI1 0>, 2709 <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>, 2710 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>; 2711 interconnect-names = "memory", 2712 "imem", 2713 "config"; 2714 2715 qcom,smem-states = <&ipa_smp2p_out 0>, 2716 <&ipa_smp2p_out 1>; 2717 qcom,smem-state-names = "ipa-clock-enabled-valid", 2718 "ipa-clock-enabled"; 2719 2720 status = "disabled"; 2721 }; 2722 2723 tcsr_mutex: hwlock@1f40000 { 2724 compatible = "qcom,tcsr-mutex"; 2725 reg = <0 0x01f40000 0 0x20000>; 2726 #hwlock-cells = <1>; 2727 }; 2728 2729 tcsr_regs_1: syscon@1f60000 { 2730 compatible = "qcom,sdm845-tcsr", "syscon"; 2731 reg = <0 0x01f60000 0 0x20000>; 2732 }; 2733 2734 tlmm: pinctrl@3400000 { 2735 compatible = "qcom,sdm845-pinctrl"; 2736 reg = <0 0x03400000 0 0xc00000>; 2737 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 2738 gpio-controller; 2739 #gpio-cells = <2>; 2740 interrupt-controller; 2741 #interrupt-cells = <2>; 2742 gpio-ranges = <&tlmm 0 0 151>; 2743 wakeup-parent = <&pdc_intc>; 2744 2745 cci0_default: cci0-default-state { 2746 /* SDA, SCL */ 2747 pins = "gpio17", "gpio18"; 2748 function = "cci_i2c"; 2749 2750 bias-pull-up; 2751 drive-strength = <2>; /* 2 mA */ 2752 }; 2753 2754 cci0_sleep: cci0-sleep-state { 2755 /* SDA, SCL */ 2756 pins = "gpio17", "gpio18"; 2757 function = "cci_i2c"; 2758 2759 drive-strength = <2>; /* 2 mA */ 2760 bias-pull-down; 2761 }; 2762 2763 cci1_default: cci1-default-state { 2764 /* SDA, SCL */ 2765 pins = "gpio19", "gpio20"; 2766 function = "cci_i2c"; 2767 2768 bias-pull-up; 2769 drive-strength = <2>; /* 2 mA */ 2770 }; 2771 2772 cci1_sleep: cci1-sleep-state { 2773 /* SDA, SCL */ 2774 pins = "gpio19", "gpio20"; 2775 function = "cci_i2c"; 2776 2777 drive-strength = <2>; /* 2 mA */ 2778 bias-pull-down; 2779 }; 2780 2781 qspi_clk: qspi-clk-state { 2782 pins = "gpio95"; 2783 function = "qspi_clk"; 2784 }; 2785 2786 qspi_cs0: qspi-cs0-state { 2787 pins = "gpio90"; 2788 function = "qspi_cs"; 2789 }; 2790 2791 qspi_cs1: qspi-cs1-state { 2792 pins = "gpio89"; 2793 function = "qspi_cs"; 2794 }; 2795 2796 qspi_data0: qspi-data0-state { 2797 pins = "gpio91"; 2798 function = "qspi_data"; 2799 }; 2800 2801 qspi_data1: qspi-data1-state { 2802 pins = "gpio92"; 2803 function = "qspi_data"; 2804 }; 2805 2806 qspi_data23: qspi-data23-state { 2807 pins = "gpio93", "gpio94"; 2808 function = "qspi_data"; 2809 }; 2810 2811 qup_i2c0_default: qup-i2c0-default-state { 2812 pins = "gpio0", "gpio1"; 2813 function = "qup0"; 2814 }; 2815 2816 qup_i2c1_default: qup-i2c1-default-state { 2817 pins = "gpio17", "gpio18"; 2818 function = "qup1"; 2819 }; 2820 2821 qup_i2c2_default: qup-i2c2-default-state { 2822 pins = "gpio27", "gpio28"; 2823 function = "qup2"; 2824 }; 2825 2826 qup_i2c3_default: qup-i2c3-default-state { 2827 pins = "gpio41", "gpio42"; 2828 function = "qup3"; 2829 }; 2830 2831 qup_i2c4_default: qup-i2c4-default-state { 2832 pins = "gpio89", "gpio90"; 2833 function = "qup4"; 2834 }; 2835 2836 qup_i2c5_default: qup-i2c5-default-state { 2837 pins = "gpio85", "gpio86"; 2838 function = "qup5"; 2839 }; 2840 2841 qup_i2c6_default: qup-i2c6-default-state { 2842 pins = "gpio45", "gpio46"; 2843 function = "qup6"; 2844 }; 2845 2846 qup_i2c7_default: qup-i2c7-default-state { 2847 pins = "gpio93", "gpio94"; 2848 function = "qup7"; 2849 }; 2850 2851 qup_i2c8_default: qup-i2c8-default-state { 2852 pins = "gpio65", "gpio66"; 2853 function = "qup8"; 2854 }; 2855 2856 qup_i2c9_default: qup-i2c9-default-state { 2857 pins = "gpio6", "gpio7"; 2858 function = "qup9"; 2859 }; 2860 2861 qup_i2c10_default: qup-i2c10-default-state { 2862 pins = "gpio55", "gpio56"; 2863 function = "qup10"; 2864 }; 2865 2866 qup_i2c11_default: qup-i2c11-default-state { 2867 pins = "gpio31", "gpio32"; 2868 function = "qup11"; 2869 }; 2870 2871 qup_i2c12_default: qup-i2c12-default-state { 2872 pins = "gpio49", "gpio50"; 2873 function = "qup12"; 2874 }; 2875 2876 qup_i2c13_default: qup-i2c13-default-state { 2877 pins = "gpio105", "gpio106"; 2878 function = "qup13"; 2879 }; 2880 2881 qup_i2c14_default: qup-i2c14-default-state { 2882 pins = "gpio33", "gpio34"; 2883 function = "qup14"; 2884 }; 2885 2886 qup_i2c15_default: qup-i2c15-default-state { 2887 pins = "gpio81", "gpio82"; 2888 function = "qup15"; 2889 }; 2890 2891 qup_spi0_default: qup-spi0-default-state { 2892 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 2893 function = "qup0"; 2894 }; 2895 2896 qup_spi1_default: qup-spi1-default-state { 2897 pins = "gpio17", "gpio18", "gpio19", "gpio20"; 2898 function = "qup1"; 2899 }; 2900 2901 qup_spi2_default: qup-spi2-default-state { 2902 pins = "gpio27", "gpio28", "gpio29", "gpio30"; 2903 function = "qup2"; 2904 }; 2905 2906 qup_spi3_default: qup-spi3-default-state { 2907 pins = "gpio41", "gpio42", "gpio43", "gpio44"; 2908 function = "qup3"; 2909 }; 2910 2911 qup_spi4_default: qup-spi4-default-state { 2912 pins = "gpio89", "gpio90", "gpio91", "gpio92"; 2913 function = "qup4"; 2914 }; 2915 2916 qup_spi5_default: qup-spi5-default-state { 2917 pins = "gpio85", "gpio86", "gpio87", "gpio88"; 2918 function = "qup5"; 2919 }; 2920 2921 qup_spi6_default: qup-spi6-default-state { 2922 pins = "gpio45", "gpio46", "gpio47", "gpio48"; 2923 function = "qup6"; 2924 }; 2925 2926 qup_spi7_default: qup-spi7-default-state { 2927 pins = "gpio93", "gpio94", "gpio95", "gpio96"; 2928 function = "qup7"; 2929 }; 2930 2931 qup_spi8_default: qup-spi8-default-state { 2932 pins = "gpio65", "gpio66", "gpio67", "gpio68"; 2933 function = "qup8"; 2934 }; 2935 2936 qup_spi9_default: qup-spi9-default-state { 2937 pins = "gpio6", "gpio7", "gpio4", "gpio5"; 2938 function = "qup9"; 2939 }; 2940 2941 qup_spi10_default: qup-spi10-default-state { 2942 pins = "gpio55", "gpio56", "gpio53", "gpio54"; 2943 function = "qup10"; 2944 }; 2945 2946 qup_spi11_default: qup-spi11-default-state { 2947 pins = "gpio31", "gpio32", "gpio33", "gpio34"; 2948 function = "qup11"; 2949 }; 2950 2951 qup_spi12_default: qup-spi12-default-state { 2952 pins = "gpio49", "gpio50", "gpio51", "gpio52"; 2953 function = "qup12"; 2954 }; 2955 2956 qup_spi13_default: qup-spi13-default-state { 2957 pins = "gpio105", "gpio106", "gpio107", "gpio108"; 2958 function = "qup13"; 2959 }; 2960 2961 qup_spi14_default: qup-spi14-default-state { 2962 pins = "gpio33", "gpio34", "gpio31", "gpio32"; 2963 function = "qup14"; 2964 }; 2965 2966 qup_spi15_default: qup-spi15-default-state { 2967 pins = "gpio81", "gpio82", "gpio83", "gpio84"; 2968 function = "qup15"; 2969 }; 2970 2971 qup_uart0_default: qup-uart0-default-state { 2972 qup_uart0_tx: tx-pins { 2973 pins = "gpio2"; 2974 function = "qup0"; 2975 }; 2976 2977 qup_uart0_rx: rx-pins { 2978 pins = "gpio3"; 2979 function = "qup0"; 2980 }; 2981 }; 2982 2983 qup_uart1_default: qup-uart1-default-state { 2984 qup_uart1_tx: tx-pins { 2985 pins = "gpio19"; 2986 function = "qup1"; 2987 }; 2988 2989 qup_uart1_rx: rx-pins { 2990 pins = "gpio20"; 2991 function = "qup1"; 2992 }; 2993 }; 2994 2995 qup_uart2_default: qup-uart2-default-state { 2996 qup_uart2_tx: tx-pins { 2997 pins = "gpio29"; 2998 function = "qup2"; 2999 }; 3000 3001 qup_uart2_rx: rx-pins { 3002 pins = "gpio30"; 3003 function = "qup2"; 3004 }; 3005 }; 3006 3007 qup_uart3_default: qup-uart3-default-state { 3008 qup_uart3_tx: tx-pins { 3009 pins = "gpio43"; 3010 function = "qup3"; 3011 }; 3012 3013 qup_uart3_rx: rx-pins { 3014 pins = "gpio44"; 3015 function = "qup3"; 3016 }; 3017 }; 3018 3019 qup_uart3_4pin: qup-uart3-4pin-state { 3020 qup_uart3_4pin_cts: cts-pins { 3021 pins = "gpio41"; 3022 function = "qup3"; 3023 }; 3024 3025 qup_uart3_4pin_rts_tx: rts-tx-pins { 3026 pins = "gpio42", "gpio43"; 3027 function = "qup3"; 3028 }; 3029 3030 qup_uart3_4pin_rx: rx-pins { 3031 pins = "gpio44"; 3032 function = "qup3"; 3033 }; 3034 }; 3035 3036 qup_uart4_default: qup-uart4-default-state { 3037 qup_uart4_tx: tx-pins { 3038 pins = "gpio91"; 3039 function = "qup4"; 3040 }; 3041 3042 qup_uart4_rx: rx-pins { 3043 pins = "gpio92"; 3044 function = "qup4"; 3045 }; 3046 }; 3047 3048 qup_uart5_default: qup-uart5-default-state { 3049 qup_uart5_tx: tx-pins { 3050 pins = "gpio87"; 3051 function = "qup5"; 3052 }; 3053 3054 qup_uart5_rx: rx-pins { 3055 pins = "gpio88"; 3056 function = "qup5"; 3057 }; 3058 }; 3059 3060 qup_uart6_default: qup-uart6-default-state { 3061 qup_uart6_tx: tx-pins { 3062 pins = "gpio47"; 3063 function = "qup6"; 3064 }; 3065 3066 qup_uart6_rx: rx-pins { 3067 pins = "gpio48"; 3068 function = "qup6"; 3069 }; 3070 }; 3071 3072 qup_uart6_4pin: qup-uart6-4pin-state { 3073 qup_uart6_4pin_cts: cts-pins { 3074 pins = "gpio45"; 3075 function = "qup6"; 3076 bias-pull-down; 3077 }; 3078 3079 qup_uart6_4pin_rts_tx: rts-tx-pins { 3080 pins = "gpio46", "gpio47"; 3081 function = "qup6"; 3082 drive-strength = <2>; 3083 bias-disable; 3084 }; 3085 3086 qup_uart6_4pin_rx: rx-pins { 3087 pins = "gpio48"; 3088 function = "qup6"; 3089 bias-pull-up; 3090 }; 3091 }; 3092 3093 qup_uart7_default: qup-uart7-default-state { 3094 qup_uart7_tx: tx-pins { 3095 pins = "gpio95"; 3096 function = "qup7"; 3097 }; 3098 3099 qup_uart7_rx: rx-pins { 3100 pins = "gpio96"; 3101 function = "qup7"; 3102 }; 3103 }; 3104 3105 qup_uart8_default: qup-uart8-default-state { 3106 qup_uart8_tx: tx-pins { 3107 pins = "gpio67"; 3108 function = "qup8"; 3109 }; 3110 3111 qup_uart8_rx: rx-pins { 3112 pins = "gpio68"; 3113 function = "qup8"; 3114 }; 3115 }; 3116 3117 qup_uart9_default: qup-uart9-default-state { 3118 qup_uart9_tx: tx-pins { 3119 pins = "gpio4"; 3120 function = "qup9"; 3121 }; 3122 3123 qup_uart9_rx: rx-pins { 3124 pins = "gpio5"; 3125 function = "qup9"; 3126 }; 3127 }; 3128 3129 qup_uart10_default: qup-uart10-default-state { 3130 qup_uart10_tx: tx-pins { 3131 pins = "gpio53"; 3132 function = "qup10"; 3133 }; 3134 3135 qup_uart10_rx: rx-pins { 3136 pins = "gpio54"; 3137 function = "qup10"; 3138 }; 3139 }; 3140 3141 qup_uart11_default: qup-uart11-default-state { 3142 qup_uart11_tx: tx-pins { 3143 pins = "gpio33"; 3144 function = "qup11"; 3145 }; 3146 3147 qup_uart11_rx: rx-pins { 3148 pins = "gpio34"; 3149 function = "qup11"; 3150 }; 3151 }; 3152 3153 qup_uart12_default: qup-uart12-default-state { 3154 qup_uart12_tx: tx-pins { 3155 pins = "gpio51"; 3156 function = "qup0"; 3157 }; 3158 3159 qup_uart12_rx: rx-pins { 3160 pins = "gpio52"; 3161 function = "qup0"; 3162 }; 3163 }; 3164 3165 qup_uart13_default: qup-uart13-default-state { 3166 qup_uart13_tx: tx-pins { 3167 pins = "gpio107"; 3168 function = "qup13"; 3169 }; 3170 3171 qup_uart13_rx: rx-pins { 3172 pins = "gpio108"; 3173 function = "qup13"; 3174 }; 3175 }; 3176 3177 qup_uart14_default: qup-uart14-default-state { 3178 qup_uart14_tx: tx-pins { 3179 pins = "gpio31"; 3180 function = "qup14"; 3181 }; 3182 3183 qup_uart14_rx: rx-pins { 3184 pins = "gpio32"; 3185 function = "qup14"; 3186 }; 3187 }; 3188 3189 qup_uart15_default: qup-uart15-default-state { 3190 qup_uart15_tx: tx-pins { 3191 pins = "gpio83"; 3192 function = "qup15"; 3193 }; 3194 3195 qup_uart15_rx: rx-pins { 3196 pins = "gpio84"; 3197 function = "qup15"; 3198 }; 3199 }; 3200 3201 quat_mi2s_sleep: quat-mi2s-sleep-state { 3202 pins = "gpio58", "gpio59"; 3203 function = "gpio"; 3204 drive-strength = <2>; 3205 bias-pull-down; 3206 }; 3207 3208 quat_mi2s_active: quat-mi2s-active-state { 3209 pins = "gpio58", "gpio59"; 3210 function = "qua_mi2s"; 3211 drive-strength = <8>; 3212 bias-disable; 3213 output-high; 3214 }; 3215 3216 quat_mi2s_sd0_sleep: quat-mi2s-sd0-sleep-state { 3217 pins = "gpio60"; 3218 function = "gpio"; 3219 drive-strength = <2>; 3220 bias-pull-down; 3221 }; 3222 3223 quat_mi2s_sd0_active: quat-mi2s-sd0-active-state { 3224 pins = "gpio60"; 3225 function = "qua_mi2s"; 3226 drive-strength = <8>; 3227 bias-disable; 3228 }; 3229 3230 quat_mi2s_sd1_sleep: quat-mi2s-sd1-sleep-state { 3231 pins = "gpio61"; 3232 function = "gpio"; 3233 drive-strength = <2>; 3234 bias-pull-down; 3235 }; 3236 3237 quat_mi2s_sd1_active: quat-mi2s-sd1-active-state { 3238 pins = "gpio61"; 3239 function = "qua_mi2s"; 3240 drive-strength = <8>; 3241 bias-disable; 3242 }; 3243 3244 quat_mi2s_sd2_sleep: quat-mi2s-sd2-sleep-state { 3245 pins = "gpio62"; 3246 function = "gpio"; 3247 drive-strength = <2>; 3248 bias-pull-down; 3249 }; 3250 3251 quat_mi2s_sd2_active: quat-mi2s-sd2-active-state { 3252 pins = "gpio62"; 3253 function = "qua_mi2s"; 3254 drive-strength = <8>; 3255 bias-disable; 3256 }; 3257 3258 quat_mi2s_sd3_sleep: quat-mi2s-sd3-sleep-state { 3259 pins = "gpio63"; 3260 function = "gpio"; 3261 drive-strength = <2>; 3262 bias-pull-down; 3263 }; 3264 3265 quat_mi2s_sd3_active: quat-mi2s-sd3-active-state { 3266 pins = "gpio63"; 3267 function = "qua_mi2s"; 3268 drive-strength = <8>; 3269 bias-disable; 3270 }; 3271 }; 3272 3273 mss_pil: remoteproc@4080000 { 3274 compatible = "qcom,sdm845-mss-pil"; 3275 reg = <0 0x04080000 0 0x408>, <0 0x04180000 0 0x48>; 3276 reg-names = "qdsp6", "rmb"; 3277 3278 interrupts-extended = 3279 <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, 3280 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3281 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3282 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3283 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 3284 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 3285 interrupt-names = "wdog", "fatal", "ready", 3286 "handover", "stop-ack", 3287 "shutdown-ack"; 3288 3289 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 3290 <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>, 3291 <&gcc GCC_BOOT_ROM_AHB_CLK>, 3292 <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>, 3293 <&gcc GCC_MSS_SNOC_AXI_CLK>, 3294 <&gcc GCC_MSS_MFAB_AXIS_CLK>, 3295 <&gcc GCC_PRNG_AHB_CLK>, 3296 <&rpmhcc RPMH_CXO_CLK>; 3297 clock-names = "iface", "bus", "mem", "gpll0_mss", 3298 "snoc_axi", "mnoc_axi", "prng", "xo"; 3299 3300 qcom,qmp = <&aoss_qmp>; 3301 3302 qcom,smem-states = <&modem_smp2p_out 0>; 3303 qcom,smem-state-names = "stop"; 3304 3305 resets = <&aoss_reset AOSS_CC_MSS_RESTART>, 3306 <&pdc_reset PDC_MODEM_SYNC_RESET>; 3307 reset-names = "mss_restart", "pdc_reset"; 3308 3309 qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>; 3310 3311 power-domains = <&rpmhpd SDM845_CX>, 3312 <&rpmhpd SDM845_MX>, 3313 <&rpmhpd SDM845_MSS>; 3314 power-domain-names = "cx", "mx", "mss"; 3315 3316 status = "disabled"; 3317 3318 mba { 3319 memory-region = <&mba_region>; 3320 }; 3321 3322 mpss { 3323 memory-region = <&mpss_region>; 3324 }; 3325 3326 metadata { 3327 memory-region = <&mdata_mem>; 3328 }; 3329 3330 glink-edge { 3331 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 3332 label = "modem"; 3333 qcom,remote-pid = <1>; 3334 mboxes = <&apss_shared 12>; 3335 }; 3336 }; 3337 3338 gpucc: clock-controller@5090000 { 3339 compatible = "qcom,sdm845-gpucc"; 3340 reg = <0 0x05090000 0 0x9000>; 3341 #clock-cells = <1>; 3342 #reset-cells = <1>; 3343 #power-domain-cells = <1>; 3344 clocks = <&rpmhcc RPMH_CXO_CLK>, 3345 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 3346 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 3347 clock-names = "bi_tcxo", 3348 "gcc_gpu_gpll0_clk_src", 3349 "gcc_gpu_gpll0_div_clk_src"; 3350 }; 3351 3352 slpi_pas: remoteproc@5c00000 { 3353 compatible = "qcom,sdm845-slpi-pas"; 3354 reg = <0 0x5c00000 0 0x4000>; 3355 3356 interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>, 3357 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3358 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3359 <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3360 <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 3361 interrupt-names = "wdog", "fatal", "ready", 3362 "handover", "stop-ack"; 3363 3364 clocks = <&rpmhcc RPMH_CXO_CLK>; 3365 clock-names = "xo"; 3366 3367 qcom,qmp = <&aoss_qmp>; 3368 3369 power-domains = <&rpmhpd SDM845_LCX>, 3370 <&rpmhpd SDM845_LMX>; 3371 power-domain-names = "lcx", "lmx"; 3372 3373 memory-region = <&slpi_mem>; 3374 3375 qcom,smem-states = <&slpi_smp2p_out 0>; 3376 qcom,smem-state-names = "stop"; 3377 3378 status = "disabled"; 3379 3380 glink-edge { 3381 interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>; 3382 label = "dsps"; 3383 qcom,remote-pid = <3>; 3384 mboxes = <&apss_shared 24>; 3385 3386 fastrpc { 3387 compatible = "qcom,fastrpc"; 3388 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3389 label = "sdsp"; 3390 qcom,non-secure-domain; 3391 qcom,vmids = <QCOM_SCM_VMID_HLOS QCOM_SCM_VMID_MSS_MSA 3392 QCOM_SCM_VMID_SSC_Q6 QCOM_SCM_VMID_ADSP_Q6>; 3393 memory-region = <&fastrpc_mem>; 3394 #address-cells = <1>; 3395 #size-cells = <0>; 3396 3397 compute-cb@0 { 3398 compatible = "qcom,fastrpc-compute-cb"; 3399 reg = <0>; 3400 }; 3401 }; 3402 }; 3403 }; 3404 3405 stm@6002000 { 3406 compatible = "arm,coresight-stm", "arm,primecell"; 3407 reg = <0 0x06002000 0 0x1000>, 3408 <0 0x16280000 0 0x180000>; 3409 reg-names = "stm-base", "stm-stimulus-base"; 3410 3411 clocks = <&aoss_qmp>; 3412 clock-names = "apb_pclk"; 3413 3414 out-ports { 3415 port { 3416 stm_out: endpoint { 3417 remote-endpoint = 3418 <&funnel0_in7>; 3419 }; 3420 }; 3421 }; 3422 }; 3423 3424 funnel@6041000 { 3425 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3426 reg = <0 0x06041000 0 0x1000>; 3427 3428 clocks = <&aoss_qmp>; 3429 clock-names = "apb_pclk"; 3430 3431 out-ports { 3432 port { 3433 funnel0_out: endpoint { 3434 remote-endpoint = 3435 <&merge_funnel_in0>; 3436 }; 3437 }; 3438 }; 3439 3440 in-ports { 3441 #address-cells = <1>; 3442 #size-cells = <0>; 3443 3444 port@7 { 3445 reg = <7>; 3446 funnel0_in7: endpoint { 3447 remote-endpoint = <&stm_out>; 3448 }; 3449 }; 3450 }; 3451 }; 3452 3453 funnel@6043000 { 3454 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3455 reg = <0 0x06043000 0 0x1000>; 3456 3457 clocks = <&aoss_qmp>; 3458 clock-names = "apb_pclk"; 3459 3460 out-ports { 3461 port { 3462 funnel2_out: endpoint { 3463 remote-endpoint = 3464 <&merge_funnel_in2>; 3465 }; 3466 }; 3467 }; 3468 3469 in-ports { 3470 #address-cells = <1>; 3471 #size-cells = <0>; 3472 3473 port@5 { 3474 reg = <5>; 3475 funnel2_in5: endpoint { 3476 remote-endpoint = 3477 <&apss_merge_funnel_out>; 3478 }; 3479 }; 3480 }; 3481 }; 3482 3483 funnel@6045000 { 3484 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3485 reg = <0 0x06045000 0 0x1000>; 3486 3487 clocks = <&aoss_qmp>; 3488 clock-names = "apb_pclk"; 3489 3490 out-ports { 3491 port { 3492 merge_funnel_out: endpoint { 3493 remote-endpoint = <&etf_in>; 3494 }; 3495 }; 3496 }; 3497 3498 in-ports { 3499 #address-cells = <1>; 3500 #size-cells = <0>; 3501 3502 port@0 { 3503 reg = <0>; 3504 merge_funnel_in0: endpoint { 3505 remote-endpoint = 3506 <&funnel0_out>; 3507 }; 3508 }; 3509 3510 port@2 { 3511 reg = <2>; 3512 merge_funnel_in2: endpoint { 3513 remote-endpoint = 3514 <&funnel2_out>; 3515 }; 3516 }; 3517 }; 3518 }; 3519 3520 replicator@6046000 { 3521 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 3522 reg = <0 0x06046000 0 0x1000>; 3523 3524 clocks = <&aoss_qmp>; 3525 clock-names = "apb_pclk"; 3526 3527 out-ports { 3528 port { 3529 replicator_out: endpoint { 3530 remote-endpoint = <&etr_in>; 3531 }; 3532 }; 3533 }; 3534 3535 in-ports { 3536 port { 3537 replicator_in: endpoint { 3538 remote-endpoint = <&etf_out>; 3539 }; 3540 }; 3541 }; 3542 }; 3543 3544 etf@6047000 { 3545 compatible = "arm,coresight-tmc", "arm,primecell"; 3546 reg = <0 0x06047000 0 0x1000>; 3547 3548 clocks = <&aoss_qmp>; 3549 clock-names = "apb_pclk"; 3550 3551 out-ports { 3552 port { 3553 etf_out: endpoint { 3554 remote-endpoint = 3555 <&replicator_in>; 3556 }; 3557 }; 3558 }; 3559 3560 in-ports { 3561 3562 port { 3563 etf_in: endpoint { 3564 remote-endpoint = 3565 <&merge_funnel_out>; 3566 }; 3567 }; 3568 }; 3569 }; 3570 3571 etr@6048000 { 3572 compatible = "arm,coresight-tmc", "arm,primecell"; 3573 reg = <0 0x06048000 0 0x1000>; 3574 3575 clocks = <&aoss_qmp>; 3576 clock-names = "apb_pclk"; 3577 arm,scatter-gather; 3578 3579 in-ports { 3580 port { 3581 etr_in: endpoint { 3582 remote-endpoint = 3583 <&replicator_out>; 3584 }; 3585 }; 3586 }; 3587 }; 3588 3589 etm@7040000 { 3590 compatible = "arm,coresight-etm4x", "arm,primecell"; 3591 reg = <0 0x07040000 0 0x1000>; 3592 3593 cpu = <&CPU0>; 3594 3595 clocks = <&aoss_qmp>; 3596 clock-names = "apb_pclk"; 3597 arm,coresight-loses-context-with-cpu; 3598 3599 out-ports { 3600 port { 3601 etm0_out: endpoint { 3602 remote-endpoint = 3603 <&apss_funnel_in0>; 3604 }; 3605 }; 3606 }; 3607 }; 3608 3609 etm@7140000 { 3610 compatible = "arm,coresight-etm4x", "arm,primecell"; 3611 reg = <0 0x07140000 0 0x1000>; 3612 3613 cpu = <&CPU1>; 3614 3615 clocks = <&aoss_qmp>; 3616 clock-names = "apb_pclk"; 3617 arm,coresight-loses-context-with-cpu; 3618 3619 out-ports { 3620 port { 3621 etm1_out: endpoint { 3622 remote-endpoint = 3623 <&apss_funnel_in1>; 3624 }; 3625 }; 3626 }; 3627 }; 3628 3629 etm@7240000 { 3630 compatible = "arm,coresight-etm4x", "arm,primecell"; 3631 reg = <0 0x07240000 0 0x1000>; 3632 3633 cpu = <&CPU2>; 3634 3635 clocks = <&aoss_qmp>; 3636 clock-names = "apb_pclk"; 3637 arm,coresight-loses-context-with-cpu; 3638 3639 out-ports { 3640 port { 3641 etm2_out: endpoint { 3642 remote-endpoint = 3643 <&apss_funnel_in2>; 3644 }; 3645 }; 3646 }; 3647 }; 3648 3649 etm@7340000 { 3650 compatible = "arm,coresight-etm4x", "arm,primecell"; 3651 reg = <0 0x07340000 0 0x1000>; 3652 3653 cpu = <&CPU3>; 3654 3655 clocks = <&aoss_qmp>; 3656 clock-names = "apb_pclk"; 3657 arm,coresight-loses-context-with-cpu; 3658 3659 out-ports { 3660 port { 3661 etm3_out: endpoint { 3662 remote-endpoint = 3663 <&apss_funnel_in3>; 3664 }; 3665 }; 3666 }; 3667 }; 3668 3669 etm@7440000 { 3670 compatible = "arm,coresight-etm4x", "arm,primecell"; 3671 reg = <0 0x07440000 0 0x1000>; 3672 3673 cpu = <&CPU4>; 3674 3675 clocks = <&aoss_qmp>; 3676 clock-names = "apb_pclk"; 3677 arm,coresight-loses-context-with-cpu; 3678 3679 out-ports { 3680 port { 3681 etm4_out: endpoint { 3682 remote-endpoint = 3683 <&apss_funnel_in4>; 3684 }; 3685 }; 3686 }; 3687 }; 3688 3689 etm@7540000 { 3690 compatible = "arm,coresight-etm4x", "arm,primecell"; 3691 reg = <0 0x07540000 0 0x1000>; 3692 3693 cpu = <&CPU5>; 3694 3695 clocks = <&aoss_qmp>; 3696 clock-names = "apb_pclk"; 3697 arm,coresight-loses-context-with-cpu; 3698 3699 out-ports { 3700 port { 3701 etm5_out: endpoint { 3702 remote-endpoint = 3703 <&apss_funnel_in5>; 3704 }; 3705 }; 3706 }; 3707 }; 3708 3709 etm@7640000 { 3710 compatible = "arm,coresight-etm4x", "arm,primecell"; 3711 reg = <0 0x07640000 0 0x1000>; 3712 3713 cpu = <&CPU6>; 3714 3715 clocks = <&aoss_qmp>; 3716 clock-names = "apb_pclk"; 3717 arm,coresight-loses-context-with-cpu; 3718 3719 out-ports { 3720 port { 3721 etm6_out: endpoint { 3722 remote-endpoint = 3723 <&apss_funnel_in6>; 3724 }; 3725 }; 3726 }; 3727 }; 3728 3729 etm@7740000 { 3730 compatible = "arm,coresight-etm4x", "arm,primecell"; 3731 reg = <0 0x07740000 0 0x1000>; 3732 3733 cpu = <&CPU7>; 3734 3735 clocks = <&aoss_qmp>; 3736 clock-names = "apb_pclk"; 3737 arm,coresight-loses-context-with-cpu; 3738 3739 out-ports { 3740 port { 3741 etm7_out: endpoint { 3742 remote-endpoint = 3743 <&apss_funnel_in7>; 3744 }; 3745 }; 3746 }; 3747 }; 3748 3749 funnel@7800000 { /* APSS Funnel */ 3750 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3751 reg = <0 0x07800000 0 0x1000>; 3752 3753 clocks = <&aoss_qmp>; 3754 clock-names = "apb_pclk"; 3755 3756 out-ports { 3757 port { 3758 apss_funnel_out: endpoint { 3759 remote-endpoint = 3760 <&apss_merge_funnel_in>; 3761 }; 3762 }; 3763 }; 3764 3765 in-ports { 3766 #address-cells = <1>; 3767 #size-cells = <0>; 3768 3769 port@0 { 3770 reg = <0>; 3771 apss_funnel_in0: endpoint { 3772 remote-endpoint = 3773 <&etm0_out>; 3774 }; 3775 }; 3776 3777 port@1 { 3778 reg = <1>; 3779 apss_funnel_in1: endpoint { 3780 remote-endpoint = 3781 <&etm1_out>; 3782 }; 3783 }; 3784 3785 port@2 { 3786 reg = <2>; 3787 apss_funnel_in2: endpoint { 3788 remote-endpoint = 3789 <&etm2_out>; 3790 }; 3791 }; 3792 3793 port@3 { 3794 reg = <3>; 3795 apss_funnel_in3: endpoint { 3796 remote-endpoint = 3797 <&etm3_out>; 3798 }; 3799 }; 3800 3801 port@4 { 3802 reg = <4>; 3803 apss_funnel_in4: endpoint { 3804 remote-endpoint = 3805 <&etm4_out>; 3806 }; 3807 }; 3808 3809 port@5 { 3810 reg = <5>; 3811 apss_funnel_in5: endpoint { 3812 remote-endpoint = 3813 <&etm5_out>; 3814 }; 3815 }; 3816 3817 port@6 { 3818 reg = <6>; 3819 apss_funnel_in6: endpoint { 3820 remote-endpoint = 3821 <&etm6_out>; 3822 }; 3823 }; 3824 3825 port@7 { 3826 reg = <7>; 3827 apss_funnel_in7: endpoint { 3828 remote-endpoint = 3829 <&etm7_out>; 3830 }; 3831 }; 3832 }; 3833 }; 3834 3835 funnel@7810000 { 3836 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3837 reg = <0 0x07810000 0 0x1000>; 3838 3839 clocks = <&aoss_qmp>; 3840 clock-names = "apb_pclk"; 3841 3842 out-ports { 3843 port { 3844 apss_merge_funnel_out: endpoint { 3845 remote-endpoint = 3846 <&funnel2_in5>; 3847 }; 3848 }; 3849 }; 3850 3851 in-ports { 3852 port { 3853 apss_merge_funnel_in: endpoint { 3854 remote-endpoint = 3855 <&apss_funnel_out>; 3856 }; 3857 }; 3858 }; 3859 }; 3860 3861 sdhc_2: mmc@8804000 { 3862 compatible = "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5"; 3863 reg = <0 0x08804000 0 0x1000>; 3864 3865 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 3866 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 3867 interrupt-names = "hc_irq", "pwr_irq"; 3868 3869 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3870 <&gcc GCC_SDCC2_APPS_CLK>, 3871 <&rpmhcc RPMH_CXO_CLK>; 3872 clock-names = "iface", "core", "xo"; 3873 iommus = <&apps_smmu 0xa0 0xf>; 3874 power-domains = <&rpmhpd SDM845_CX>; 3875 operating-points-v2 = <&sdhc2_opp_table>; 3876 3877 status = "disabled"; 3878 3879 sdhc2_opp_table: opp-table { 3880 compatible = "operating-points-v2"; 3881 3882 opp-9600000 { 3883 opp-hz = /bits/ 64 <9600000>; 3884 required-opps = <&rpmhpd_opp_min_svs>; 3885 }; 3886 3887 opp-19200000 { 3888 opp-hz = /bits/ 64 <19200000>; 3889 required-opps = <&rpmhpd_opp_low_svs>; 3890 }; 3891 3892 opp-100000000 { 3893 opp-hz = /bits/ 64 <100000000>; 3894 required-opps = <&rpmhpd_opp_svs>; 3895 }; 3896 3897 opp-201500000 { 3898 opp-hz = /bits/ 64 <201500000>; 3899 required-opps = <&rpmhpd_opp_svs_l1>; 3900 }; 3901 }; 3902 }; 3903 3904 qspi: spi@88df000 { 3905 compatible = "qcom,sdm845-qspi", "qcom,qspi-v1"; 3906 reg = <0 0x088df000 0 0x600>; 3907 iommus = <&apps_smmu 0x160 0x0>; 3908 #address-cells = <1>; 3909 #size-cells = <0>; 3910 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 3911 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 3912 <&gcc GCC_QSPI_CORE_CLK>; 3913 clock-names = "iface", "core"; 3914 power-domains = <&rpmhpd SDM845_CX>; 3915 operating-points-v2 = <&qspi_opp_table>; 3916 status = "disabled"; 3917 }; 3918 3919 slim: slim-ngd@171c0000 { 3920 compatible = "qcom,slim-ngd-v2.1.0"; 3921 reg = <0 0x171c0000 0 0x2c000>; 3922 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 3923 3924 dmas = <&slimbam 3>, <&slimbam 4>; 3925 dma-names = "rx", "tx"; 3926 3927 iommus = <&apps_smmu 0x1806 0x0>; 3928 #address-cells = <1>; 3929 #size-cells = <0>; 3930 status = "disabled"; 3931 }; 3932 3933 lmh_cluster1: lmh@17d70800 { 3934 compatible = "qcom,sdm845-lmh"; 3935 reg = <0 0x17d70800 0 0x400>; 3936 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 3937 cpus = <&CPU4>; 3938 qcom,lmh-temp-arm-millicelsius = <65000>; 3939 qcom,lmh-temp-low-millicelsius = <94500>; 3940 qcom,lmh-temp-high-millicelsius = <95000>; 3941 interrupt-controller; 3942 #interrupt-cells = <1>; 3943 }; 3944 3945 lmh_cluster0: lmh@17d78800 { 3946 compatible = "qcom,sdm845-lmh"; 3947 reg = <0 0x17d78800 0 0x400>; 3948 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 3949 cpus = <&CPU0>; 3950 qcom,lmh-temp-arm-millicelsius = <65000>; 3951 qcom,lmh-temp-low-millicelsius = <94500>; 3952 qcom,lmh-temp-high-millicelsius = <95000>; 3953 interrupt-controller; 3954 #interrupt-cells = <1>; 3955 }; 3956 3957 usb_1_hsphy: phy@88e2000 { 3958 compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy"; 3959 reg = <0 0x088e2000 0 0x400>; 3960 status = "disabled"; 3961 #phy-cells = <0>; 3962 3963 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 3964 <&rpmhcc RPMH_CXO_CLK>; 3965 clock-names = "cfg_ahb", "ref"; 3966 3967 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3968 3969 nvmem-cells = <&qusb2p_hstx_trim>; 3970 }; 3971 3972 usb_2_hsphy: phy@88e3000 { 3973 compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy"; 3974 reg = <0 0x088e3000 0 0x400>; 3975 status = "disabled"; 3976 #phy-cells = <0>; 3977 3978 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 3979 <&rpmhcc RPMH_CXO_CLK>; 3980 clock-names = "cfg_ahb", "ref"; 3981 3982 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3983 3984 nvmem-cells = <&qusb2s_hstx_trim>; 3985 }; 3986 3987 usb_1_qmpphy: phy@88e8000 { 3988 compatible = "qcom,sdm845-qmp-usb3-dp-phy"; 3989 reg = <0 0x088e8000 0 0x3000>; 3990 status = "disabled"; 3991 3992 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3993 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 3994 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 3995 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, 3996 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>; 3997 clock-names = "aux", 3998 "ref", 3999 "com_aux", 4000 "usb3_pipe", 4001 "cfg_ahb"; 4002 4003 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 4004 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; 4005 reset-names = "phy", "common"; 4006 4007 #clock-cells = <1>; 4008 #phy-cells = <1>; 4009 }; 4010 4011 usb_2_qmpphy: phy@88eb000 { 4012 compatible = "qcom,sdm845-qmp-usb3-uni-phy"; 4013 reg = <0 0x088eb000 0 0x1000>; 4014 4015 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 4016 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 4017 <&gcc GCC_USB3_SEC_CLKREF_CLK>, 4018 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, 4019 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 4020 clock-names = "aux", 4021 "cfg_ahb", 4022 "ref", 4023 "com_aux", 4024 "pipe"; 4025 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 4026 #clock-cells = <0>; 4027 #phy-cells = <0>; 4028 4029 resets = <&gcc GCC_USB3_PHY_SEC_BCR>, 4030 <&gcc GCC_USB3PHY_PHY_SEC_BCR>; 4031 reset-names = "phy", 4032 "phy_phy"; 4033 4034 status = "disabled"; 4035 }; 4036 4037 usb_1: usb@a6f8800 { 4038 compatible = "qcom,sdm845-dwc3", "qcom,dwc3"; 4039 reg = <0 0x0a6f8800 0 0x400>; 4040 status = "disabled"; 4041 #address-cells = <2>; 4042 #size-cells = <2>; 4043 ranges; 4044 dma-ranges; 4045 4046 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 4047 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 4048 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 4049 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 4050 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 4051 clock-names = "cfg_noc", 4052 "core", 4053 "iface", 4054 "sleep", 4055 "mock_utmi"; 4056 4057 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4058 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 4059 assigned-clock-rates = <19200000>, <150000000>; 4060 4061 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 4062 <&pdc_intc 6 IRQ_TYPE_LEVEL_HIGH>, 4063 <&pdc_intc 8 IRQ_TYPE_EDGE_BOTH>, 4064 <&pdc_intc 9 IRQ_TYPE_EDGE_BOTH>; 4065 interrupt-names = "hs_phy_irq", "ss_phy_irq", 4066 "dm_hs_phy_irq", "dp_hs_phy_irq"; 4067 4068 power-domains = <&gcc USB30_PRIM_GDSC>; 4069 4070 resets = <&gcc GCC_USB30_PRIM_BCR>; 4071 4072 interconnects = <&aggre2_noc MASTER_USB3_0 0 &mem_noc SLAVE_EBI1 0>, 4073 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; 4074 interconnect-names = "usb-ddr", "apps-usb"; 4075 4076 usb_1_dwc3: usb@a600000 { 4077 compatible = "snps,dwc3"; 4078 reg = <0 0x0a600000 0 0xcd00>; 4079 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 4080 iommus = <&apps_smmu 0x740 0>; 4081 snps,dis_u2_susphy_quirk; 4082 snps,dis_enblslpm_quirk; 4083 snps,parkmode-disable-ss-quirk; 4084 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 4085 phy-names = "usb2-phy", "usb3-phy"; 4086 }; 4087 }; 4088 4089 usb_2: usb@a8f8800 { 4090 compatible = "qcom,sdm845-dwc3", "qcom,dwc3"; 4091 reg = <0 0x0a8f8800 0 0x400>; 4092 status = "disabled"; 4093 #address-cells = <2>; 4094 #size-cells = <2>; 4095 ranges; 4096 dma-ranges; 4097 4098 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 4099 <&gcc GCC_USB30_SEC_MASTER_CLK>, 4100 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 4101 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 4102 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>; 4103 clock-names = "cfg_noc", 4104 "core", 4105 "iface", 4106 "sleep", 4107 "mock_utmi"; 4108 4109 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 4110 <&gcc GCC_USB30_SEC_MASTER_CLK>; 4111 assigned-clock-rates = <19200000>, <150000000>; 4112 4113 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 4114 <&pdc_intc 7 IRQ_TYPE_LEVEL_HIGH>, 4115 <&pdc_intc 10 IRQ_TYPE_EDGE_BOTH>, 4116 <&pdc_intc 11 IRQ_TYPE_EDGE_BOTH>; 4117 interrupt-names = "hs_phy_irq", "ss_phy_irq", 4118 "dm_hs_phy_irq", "dp_hs_phy_irq"; 4119 4120 power-domains = <&gcc USB30_SEC_GDSC>; 4121 4122 resets = <&gcc GCC_USB30_SEC_BCR>; 4123 4124 interconnects = <&aggre2_noc MASTER_USB3_1 0 &mem_noc SLAVE_EBI1 0>, 4125 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>; 4126 interconnect-names = "usb-ddr", "apps-usb"; 4127 4128 usb_2_dwc3: usb@a800000 { 4129 compatible = "snps,dwc3"; 4130 reg = <0 0x0a800000 0 0xcd00>; 4131 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 4132 iommus = <&apps_smmu 0x760 0>; 4133 snps,dis_u2_susphy_quirk; 4134 snps,dis_enblslpm_quirk; 4135 snps,parkmode-disable-ss-quirk; 4136 phys = <&usb_2_hsphy>, <&usb_2_qmpphy>; 4137 phy-names = "usb2-phy", "usb3-phy"; 4138 }; 4139 }; 4140 4141 venus: video-codec@aa00000 { 4142 compatible = "qcom,sdm845-venus-v2"; 4143 reg = <0 0x0aa00000 0 0xff000>; 4144 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 4145 power-domains = <&videocc VENUS_GDSC>, 4146 <&videocc VCODEC0_GDSC>, 4147 <&videocc VCODEC1_GDSC>, 4148 <&rpmhpd SDM845_CX>; 4149 power-domain-names = "venus", "vcodec0", "vcodec1", "cx"; 4150 operating-points-v2 = <&venus_opp_table>; 4151 clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>, 4152 <&videocc VIDEO_CC_VENUS_AHB_CLK>, 4153 <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>, 4154 <&videocc VIDEO_CC_VCODEC0_CORE_CLK>, 4155 <&videocc VIDEO_CC_VCODEC0_AXI_CLK>, 4156 <&videocc VIDEO_CC_VCODEC1_CORE_CLK>, 4157 <&videocc VIDEO_CC_VCODEC1_AXI_CLK>; 4158 clock-names = "core", "iface", "bus", 4159 "vcodec0_core", "vcodec0_bus", 4160 "vcodec1_core", "vcodec1_bus"; 4161 iommus = <&apps_smmu 0x10a0 0x8>, 4162 <&apps_smmu 0x10b0 0x0>; 4163 memory-region = <&venus_mem>; 4164 interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mem_noc SLAVE_EBI1 0>, 4165 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>; 4166 interconnect-names = "video-mem", "cpu-cfg"; 4167 4168 status = "disabled"; 4169 4170 video-core0 { 4171 compatible = "venus-decoder"; 4172 }; 4173 4174 video-core1 { 4175 compatible = "venus-encoder"; 4176 }; 4177 4178 venus_opp_table: opp-table { 4179 compatible = "operating-points-v2"; 4180 4181 opp-100000000 { 4182 opp-hz = /bits/ 64 <100000000>; 4183 required-opps = <&rpmhpd_opp_min_svs>; 4184 }; 4185 4186 opp-200000000 { 4187 opp-hz = /bits/ 64 <200000000>; 4188 required-opps = <&rpmhpd_opp_low_svs>; 4189 }; 4190 4191 opp-320000000 { 4192 opp-hz = /bits/ 64 <320000000>; 4193 required-opps = <&rpmhpd_opp_svs>; 4194 }; 4195 4196 opp-380000000 { 4197 opp-hz = /bits/ 64 <380000000>; 4198 required-opps = <&rpmhpd_opp_svs_l1>; 4199 }; 4200 4201 opp-444000000 { 4202 opp-hz = /bits/ 64 <444000000>; 4203 required-opps = <&rpmhpd_opp_nom>; 4204 }; 4205 4206 opp-533000097 { 4207 opp-hz = /bits/ 64 <533000097>; 4208 required-opps = <&rpmhpd_opp_turbo>; 4209 }; 4210 }; 4211 }; 4212 4213 videocc: clock-controller@ab00000 { 4214 compatible = "qcom,sdm845-videocc"; 4215 reg = <0 0x0ab00000 0 0x10000>; 4216 clocks = <&rpmhcc RPMH_CXO_CLK>; 4217 clock-names = "bi_tcxo"; 4218 #clock-cells = <1>; 4219 #power-domain-cells = <1>; 4220 #reset-cells = <1>; 4221 }; 4222 4223 camss: camss@acb3000 { 4224 compatible = "qcom,sdm845-camss"; 4225 4226 reg = <0 0x0acb3000 0 0x1000>, 4227 <0 0x0acba000 0 0x1000>, 4228 <0 0x0acc8000 0 0x1000>, 4229 <0 0x0ac65000 0 0x1000>, 4230 <0 0x0ac66000 0 0x1000>, 4231 <0 0x0ac67000 0 0x1000>, 4232 <0 0x0ac68000 0 0x1000>, 4233 <0 0x0acaf000 0 0x4000>, 4234 <0 0x0acb6000 0 0x4000>, 4235 <0 0x0acc4000 0 0x4000>; 4236 reg-names = "csid0", 4237 "csid1", 4238 "csid2", 4239 "csiphy0", 4240 "csiphy1", 4241 "csiphy2", 4242 "csiphy3", 4243 "vfe0", 4244 "vfe1", 4245 "vfe_lite"; 4246 4247 interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>, 4248 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>, 4249 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>, 4250 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>, 4251 <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>, 4252 <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>, 4253 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, 4254 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>, 4255 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>, 4256 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>; 4257 interrupt-names = "csid0", 4258 "csid1", 4259 "csid2", 4260 "csiphy0", 4261 "csiphy1", 4262 "csiphy2", 4263 "csiphy3", 4264 "vfe0", 4265 "vfe1", 4266 "vfe_lite"; 4267 4268 power-domains = <&clock_camcc IFE_0_GDSC>, 4269 <&clock_camcc IFE_1_GDSC>, 4270 <&clock_camcc TITAN_TOP_GDSC>; 4271 4272 clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, 4273 <&clock_camcc CAM_CC_CPAS_AHB_CLK>, 4274 <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, 4275 <&clock_camcc CAM_CC_IFE_0_CSID_CLK>, 4276 <&clock_camcc CAM_CC_IFE_0_CSID_CLK_SRC>, 4277 <&clock_camcc CAM_CC_IFE_1_CSID_CLK>, 4278 <&clock_camcc CAM_CC_IFE_1_CSID_CLK_SRC>, 4279 <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK>, 4280 <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>, 4281 <&clock_camcc CAM_CC_CSIPHY0_CLK>, 4282 <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>, 4283 <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>, 4284 <&clock_camcc CAM_CC_CSIPHY1_CLK>, 4285 <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK>, 4286 <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>, 4287 <&clock_camcc CAM_CC_CSIPHY2_CLK>, 4288 <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK>, 4289 <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>, 4290 <&clock_camcc CAM_CC_CSIPHY3_CLK>, 4291 <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK>, 4292 <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>, 4293 <&gcc GCC_CAMERA_AHB_CLK>, 4294 <&gcc GCC_CAMERA_AXI_CLK>, 4295 <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, 4296 <&clock_camcc CAM_CC_SOC_AHB_CLK>, 4297 <&clock_camcc CAM_CC_IFE_0_AXI_CLK>, 4298 <&clock_camcc CAM_CC_IFE_0_CLK>, 4299 <&clock_camcc CAM_CC_IFE_0_CPHY_RX_CLK>, 4300 <&clock_camcc CAM_CC_IFE_0_CLK_SRC>, 4301 <&clock_camcc CAM_CC_IFE_1_AXI_CLK>, 4302 <&clock_camcc CAM_CC_IFE_1_CLK>, 4303 <&clock_camcc CAM_CC_IFE_1_CPHY_RX_CLK>, 4304 <&clock_camcc CAM_CC_IFE_1_CLK_SRC>, 4305 <&clock_camcc CAM_CC_IFE_LITE_CLK>, 4306 <&clock_camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, 4307 <&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>; 4308 clock-names = "camnoc_axi", 4309 "cpas_ahb", 4310 "cphy_rx_src", 4311 "csi0", 4312 "csi0_src", 4313 "csi1", 4314 "csi1_src", 4315 "csi2", 4316 "csi2_src", 4317 "csiphy0", 4318 "csiphy0_timer", 4319 "csiphy0_timer_src", 4320 "csiphy1", 4321 "csiphy1_timer", 4322 "csiphy1_timer_src", 4323 "csiphy2", 4324 "csiphy2_timer", 4325 "csiphy2_timer_src", 4326 "csiphy3", 4327 "csiphy3_timer", 4328 "csiphy3_timer_src", 4329 "gcc_camera_ahb", 4330 "gcc_camera_axi", 4331 "slow_ahb_src", 4332 "soc_ahb", 4333 "vfe0_axi", 4334 "vfe0", 4335 "vfe0_cphy_rx", 4336 "vfe0_src", 4337 "vfe1_axi", 4338 "vfe1", 4339 "vfe1_cphy_rx", 4340 "vfe1_src", 4341 "vfe_lite", 4342 "vfe_lite_cphy_rx", 4343 "vfe_lite_src"; 4344 4345 iommus = <&apps_smmu 0x0808 0x0>, 4346 <&apps_smmu 0x0810 0x8>, 4347 <&apps_smmu 0x0c08 0x0>, 4348 <&apps_smmu 0x0c10 0x8>; 4349 4350 status = "disabled"; 4351 4352 ports { 4353 #address-cells = <1>; 4354 #size-cells = <0>; 4355 4356 port@0 { 4357 reg = <0>; 4358 }; 4359 4360 port@1 { 4361 reg = <1>; 4362 }; 4363 4364 port@2 { 4365 reg = <2>; 4366 }; 4367 4368 port@3 { 4369 reg = <3>; 4370 }; 4371 }; 4372 }; 4373 4374 cci: cci@ac4a000 { 4375 compatible = "qcom,sdm845-cci", "qcom,msm8996-cci"; 4376 #address-cells = <1>; 4377 #size-cells = <0>; 4378 4379 reg = <0 0x0ac4a000 0 0x4000>; 4380 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>; 4381 power-domains = <&clock_camcc TITAN_TOP_GDSC>; 4382 4383 clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, 4384 <&clock_camcc CAM_CC_SOC_AHB_CLK>, 4385 <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, 4386 <&clock_camcc CAM_CC_CPAS_AHB_CLK>, 4387 <&clock_camcc CAM_CC_CCI_CLK>, 4388 <&clock_camcc CAM_CC_CCI_CLK_SRC>; 4389 clock-names = "camnoc_axi", 4390 "soc_ahb", 4391 "slow_ahb_src", 4392 "cpas_ahb", 4393 "cci", 4394 "cci_src"; 4395 4396 assigned-clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, 4397 <&clock_camcc CAM_CC_CCI_CLK>; 4398 assigned-clock-rates = <80000000>, <37500000>; 4399 4400 pinctrl-names = "default", "sleep"; 4401 pinctrl-0 = <&cci0_default &cci1_default>; 4402 pinctrl-1 = <&cci0_sleep &cci1_sleep>; 4403 4404 status = "disabled"; 4405 4406 cci_i2c0: i2c-bus@0 { 4407 reg = <0>; 4408 clock-frequency = <1000000>; 4409 #address-cells = <1>; 4410 #size-cells = <0>; 4411 }; 4412 4413 cci_i2c1: i2c-bus@1 { 4414 reg = <1>; 4415 clock-frequency = <1000000>; 4416 #address-cells = <1>; 4417 #size-cells = <0>; 4418 }; 4419 }; 4420 4421 clock_camcc: clock-controller@ad00000 { 4422 compatible = "qcom,sdm845-camcc"; 4423 reg = <0 0x0ad00000 0 0x10000>; 4424 #clock-cells = <1>; 4425 #reset-cells = <1>; 4426 #power-domain-cells = <1>; 4427 clocks = <&rpmhcc RPMH_CXO_CLK>; 4428 clock-names = "bi_tcxo"; 4429 }; 4430 4431 mdss: display-subsystem@ae00000 { 4432 compatible = "qcom,sdm845-mdss"; 4433 reg = <0 0x0ae00000 0 0x1000>; 4434 reg-names = "mdss"; 4435 4436 power-domains = <&dispcc MDSS_GDSC>; 4437 4438 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4439 <&dispcc DISP_CC_MDSS_MDP_CLK>; 4440 clock-names = "iface", "core"; 4441 4442 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 4443 interrupt-controller; 4444 #interrupt-cells = <1>; 4445 4446 interconnects = <&mmss_noc MASTER_MDP0 0 &mem_noc SLAVE_EBI1 0>, 4447 <&mmss_noc MASTER_MDP1 0 &mem_noc SLAVE_EBI1 0>; 4448 interconnect-names = "mdp0-mem", "mdp1-mem"; 4449 4450 iommus = <&apps_smmu 0x880 0x8>, 4451 <&apps_smmu 0xc80 0x8>; 4452 4453 status = "disabled"; 4454 4455 #address-cells = <2>; 4456 #size-cells = <2>; 4457 ranges; 4458 4459 mdss_mdp: display-controller@ae01000 { 4460 compatible = "qcom,sdm845-dpu"; 4461 reg = <0 0x0ae01000 0 0x8f000>, 4462 <0 0x0aeb0000 0 0x2008>; 4463 reg-names = "mdp", "vbif"; 4464 4465 clocks = <&gcc GCC_DISP_AXI_CLK>, 4466 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4467 <&dispcc DISP_CC_MDSS_AXI_CLK>, 4468 <&dispcc DISP_CC_MDSS_MDP_CLK>, 4469 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 4470 clock-names = "gcc-bus", "iface", "bus", "core", "vsync"; 4471 4472 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 4473 assigned-clock-rates = <19200000>; 4474 operating-points-v2 = <&mdp_opp_table>; 4475 power-domains = <&rpmhpd SDM845_CX>; 4476 4477 interrupt-parent = <&mdss>; 4478 interrupts = <0>; 4479 4480 ports { 4481 #address-cells = <1>; 4482 #size-cells = <0>; 4483 4484 port@0 { 4485 reg = <0>; 4486 dpu_intf0_out: endpoint { 4487 remote-endpoint = <&dp_in>; 4488 }; 4489 }; 4490 4491 port@1 { 4492 reg = <1>; 4493 dpu_intf1_out: endpoint { 4494 remote-endpoint = <&mdss_dsi0_in>; 4495 }; 4496 }; 4497 4498 port@2 { 4499 reg = <2>; 4500 dpu_intf2_out: endpoint { 4501 remote-endpoint = <&mdss_dsi1_in>; 4502 }; 4503 }; 4504 }; 4505 4506 mdp_opp_table: opp-table { 4507 compatible = "operating-points-v2"; 4508 4509 opp-19200000 { 4510 opp-hz = /bits/ 64 <19200000>; 4511 required-opps = <&rpmhpd_opp_min_svs>; 4512 }; 4513 4514 opp-171428571 { 4515 opp-hz = /bits/ 64 <171428571>; 4516 required-opps = <&rpmhpd_opp_low_svs>; 4517 }; 4518 4519 opp-344000000 { 4520 opp-hz = /bits/ 64 <344000000>; 4521 required-opps = <&rpmhpd_opp_svs_l1>; 4522 }; 4523 4524 opp-430000000 { 4525 opp-hz = /bits/ 64 <430000000>; 4526 required-opps = <&rpmhpd_opp_nom>; 4527 }; 4528 }; 4529 }; 4530 4531 mdss_dp: displayport-controller@ae90000 { 4532 status = "disabled"; 4533 compatible = "qcom,sdm845-dp"; 4534 4535 reg = <0 0x0ae90000 0 0x200>, 4536 <0 0x0ae90200 0 0x200>, 4537 <0 0x0ae90400 0 0x600>, 4538 <0 0x0ae90a00 0 0x600>, 4539 <0 0x0ae91000 0 0x600>; 4540 4541 interrupt-parent = <&mdss>; 4542 interrupts = <12>; 4543 4544 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4545 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 4546 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 4547 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 4548 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 4549 clock-names = "core_iface", "core_aux", "ctrl_link", 4550 "ctrl_link_iface", "stream_pixel"; 4551 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 4552 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 4553 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 4554 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 4555 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; 4556 phy-names = "dp"; 4557 4558 operating-points-v2 = <&dp_opp_table>; 4559 power-domains = <&rpmhpd SDM845_CX>; 4560 4561 ports { 4562 #address-cells = <1>; 4563 #size-cells = <0>; 4564 port@0 { 4565 reg = <0>; 4566 dp_in: endpoint { 4567 remote-endpoint = <&dpu_intf0_out>; 4568 }; 4569 }; 4570 4571 port@1 { 4572 reg = <1>; 4573 dp_out: endpoint { }; 4574 }; 4575 }; 4576 4577 dp_opp_table: opp-table { 4578 compatible = "operating-points-v2"; 4579 4580 opp-162000000 { 4581 opp-hz = /bits/ 64 <162000000>; 4582 required-opps = <&rpmhpd_opp_low_svs>; 4583 }; 4584 4585 opp-270000000 { 4586 opp-hz = /bits/ 64 <270000000>; 4587 required-opps = <&rpmhpd_opp_svs>; 4588 }; 4589 4590 opp-540000000 { 4591 opp-hz = /bits/ 64 <540000000>; 4592 required-opps = <&rpmhpd_opp_svs_l1>; 4593 }; 4594 4595 opp-810000000 { 4596 opp-hz = /bits/ 64 <810000000>; 4597 required-opps = <&rpmhpd_opp_nom>; 4598 }; 4599 }; 4600 }; 4601 4602 mdss_dsi0: dsi@ae94000 { 4603 compatible = "qcom,sdm845-dsi-ctrl", 4604 "qcom,mdss-dsi-ctrl"; 4605 reg = <0 0x0ae94000 0 0x400>; 4606 reg-names = "dsi_ctrl"; 4607 4608 interrupt-parent = <&mdss>; 4609 interrupts = <4>; 4610 4611 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 4612 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 4613 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 4614 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 4615 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4616 <&dispcc DISP_CC_MDSS_AXI_CLK>; 4617 clock-names = "byte", 4618 "byte_intf", 4619 "pixel", 4620 "core", 4621 "iface", 4622 "bus"; 4623 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 4624 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; 4625 4626 operating-points-v2 = <&dsi_opp_table>; 4627 power-domains = <&rpmhpd SDM845_CX>; 4628 4629 phys = <&mdss_dsi0_phy>; 4630 4631 status = "disabled"; 4632 4633 #address-cells = <1>; 4634 #size-cells = <0>; 4635 4636 ports { 4637 #address-cells = <1>; 4638 #size-cells = <0>; 4639 4640 port@0 { 4641 reg = <0>; 4642 mdss_dsi0_in: endpoint { 4643 remote-endpoint = <&dpu_intf1_out>; 4644 }; 4645 }; 4646 4647 port@1 { 4648 reg = <1>; 4649 mdss_dsi0_out: endpoint { 4650 }; 4651 }; 4652 }; 4653 }; 4654 4655 mdss_dsi0_phy: phy@ae94400 { 4656 compatible = "qcom,dsi-phy-10nm"; 4657 reg = <0 0x0ae94400 0 0x200>, 4658 <0 0x0ae94600 0 0x280>, 4659 <0 0x0ae94a00 0 0x1e0>; 4660 reg-names = "dsi_phy", 4661 "dsi_phy_lane", 4662 "dsi_pll"; 4663 4664 #clock-cells = <1>; 4665 #phy-cells = <0>; 4666 4667 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4668 <&rpmhcc RPMH_CXO_CLK>; 4669 clock-names = "iface", "ref"; 4670 4671 status = "disabled"; 4672 }; 4673 4674 mdss_dsi1: dsi@ae96000 { 4675 compatible = "qcom,sdm845-dsi-ctrl", 4676 "qcom,mdss-dsi-ctrl"; 4677 reg = <0 0x0ae96000 0 0x400>; 4678 reg-names = "dsi_ctrl"; 4679 4680 interrupt-parent = <&mdss>; 4681 interrupts = <5>; 4682 4683 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 4684 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 4685 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 4686 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 4687 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4688 <&dispcc DISP_CC_MDSS_AXI_CLK>; 4689 clock-names = "byte", 4690 "byte_intf", 4691 "pixel", 4692 "core", 4693 "iface", 4694 "bus"; 4695 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 4696 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>; 4697 4698 operating-points-v2 = <&dsi_opp_table>; 4699 power-domains = <&rpmhpd SDM845_CX>; 4700 4701 phys = <&mdss_dsi1_phy>; 4702 4703 status = "disabled"; 4704 4705 #address-cells = <1>; 4706 #size-cells = <0>; 4707 4708 ports { 4709 #address-cells = <1>; 4710 #size-cells = <0>; 4711 4712 port@0 { 4713 reg = <0>; 4714 mdss_dsi1_in: endpoint { 4715 remote-endpoint = <&dpu_intf2_out>; 4716 }; 4717 }; 4718 4719 port@1 { 4720 reg = <1>; 4721 mdss_dsi1_out: endpoint { 4722 }; 4723 }; 4724 }; 4725 }; 4726 4727 mdss_dsi1_phy: phy@ae96400 { 4728 compatible = "qcom,dsi-phy-10nm"; 4729 reg = <0 0x0ae96400 0 0x200>, 4730 <0 0x0ae96600 0 0x280>, 4731 <0 0x0ae96a00 0 0x10e>; 4732 reg-names = "dsi_phy", 4733 "dsi_phy_lane", 4734 "dsi_pll"; 4735 4736 #clock-cells = <1>; 4737 #phy-cells = <0>; 4738 4739 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4740 <&rpmhcc RPMH_CXO_CLK>; 4741 clock-names = "iface", "ref"; 4742 4743 status = "disabled"; 4744 }; 4745 }; 4746 4747 gpu: gpu@5000000 { 4748 compatible = "qcom,adreno-630.2", "qcom,adreno"; 4749 4750 reg = <0 0x05000000 0 0x40000>, <0 0x509e000 0 0x10>; 4751 reg-names = "kgsl_3d0_reg_memory", "cx_mem"; 4752 4753 /* 4754 * Look ma, no clocks! The GPU clocks and power are 4755 * controlled entirely by the GMU 4756 */ 4757 4758 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 4759 4760 iommus = <&adreno_smmu 0>; 4761 4762 operating-points-v2 = <&gpu_opp_table>; 4763 4764 qcom,gmu = <&gmu>; 4765 4766 interconnects = <&mem_noc MASTER_GFX3D 0 &mem_noc SLAVE_EBI1 0>; 4767 interconnect-names = "gfx-mem"; 4768 4769 status = "disabled"; 4770 4771 gpu_opp_table: opp-table { 4772 compatible = "operating-points-v2"; 4773 4774 opp-710000000 { 4775 opp-hz = /bits/ 64 <710000000>; 4776 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4777 opp-peak-kBps = <7216000>; 4778 }; 4779 4780 opp-675000000 { 4781 opp-hz = /bits/ 64 <675000000>; 4782 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4783 opp-peak-kBps = <7216000>; 4784 }; 4785 4786 opp-596000000 { 4787 opp-hz = /bits/ 64 <596000000>; 4788 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4789 opp-peak-kBps = <6220000>; 4790 }; 4791 4792 opp-520000000 { 4793 opp-hz = /bits/ 64 <520000000>; 4794 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4795 opp-peak-kBps = <6220000>; 4796 }; 4797 4798 opp-414000000 { 4799 opp-hz = /bits/ 64 <414000000>; 4800 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4801 opp-peak-kBps = <4068000>; 4802 }; 4803 4804 opp-342000000 { 4805 opp-hz = /bits/ 64 <342000000>; 4806 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4807 opp-peak-kBps = <2724000>; 4808 }; 4809 4810 opp-257000000 { 4811 opp-hz = /bits/ 64 <257000000>; 4812 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4813 opp-peak-kBps = <1648000>; 4814 }; 4815 }; 4816 }; 4817 4818 adreno_smmu: iommu@5040000 { 4819 compatible = "qcom,sdm845-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2"; 4820 reg = <0 0x05040000 0 0x10000>; 4821 #iommu-cells = <1>; 4822 #global-interrupts = <2>; 4823 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 4824 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 4825 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, 4826 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, 4827 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>, 4828 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>, 4829 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>, 4830 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>, 4831 <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>, 4832 <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>; 4833 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 4834 <&gcc GCC_GPU_CFG_AHB_CLK>; 4835 clock-names = "bus", "iface"; 4836 4837 power-domains = <&gpucc GPU_CX_GDSC>; 4838 }; 4839 4840 gmu: gmu@506a000 { 4841 compatible = "qcom,adreno-gmu-630.2", "qcom,adreno-gmu"; 4842 4843 reg = <0 0x0506a000 0 0x30000>, 4844 <0 0x0b280000 0 0x10000>, 4845 <0 0x0b480000 0 0x10000>; 4846 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; 4847 4848 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 4849 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 4850 interrupt-names = "hfi", "gmu"; 4851 4852 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 4853 <&gpucc GPU_CC_CXO_CLK>, 4854 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 4855 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 4856 clock-names = "gmu", "cxo", "axi", "memnoc"; 4857 4858 power-domains = <&gpucc GPU_CX_GDSC>, 4859 <&gpucc GPU_GX_GDSC>; 4860 power-domain-names = "cx", "gx"; 4861 4862 iommus = <&adreno_smmu 5>; 4863 4864 operating-points-v2 = <&gmu_opp_table>; 4865 4866 status = "disabled"; 4867 4868 gmu_opp_table: opp-table { 4869 compatible = "operating-points-v2"; 4870 4871 opp-400000000 { 4872 opp-hz = /bits/ 64 <400000000>; 4873 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4874 }; 4875 4876 opp-200000000 { 4877 opp-hz = /bits/ 64 <200000000>; 4878 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 4879 }; 4880 }; 4881 }; 4882 4883 dispcc: clock-controller@af00000 { 4884 compatible = "qcom,sdm845-dispcc"; 4885 reg = <0 0x0af00000 0 0x10000>; 4886 clocks = <&rpmhcc RPMH_CXO_CLK>, 4887 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 4888 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, 4889 <&mdss_dsi0_phy 0>, 4890 <&mdss_dsi0_phy 1>, 4891 <&mdss_dsi1_phy 0>, 4892 <&mdss_dsi1_phy 1>, 4893 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 4894 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 4895 clock-names = "bi_tcxo", 4896 "gcc_disp_gpll0_clk_src", 4897 "gcc_disp_gpll0_div_clk_src", 4898 "dsi0_phy_pll_out_byteclk", 4899 "dsi0_phy_pll_out_dsiclk", 4900 "dsi1_phy_pll_out_byteclk", 4901 "dsi1_phy_pll_out_dsiclk", 4902 "dp_link_clk_divsel_ten", 4903 "dp_vco_divided_clk_src_mux"; 4904 #clock-cells = <1>; 4905 #reset-cells = <1>; 4906 #power-domain-cells = <1>; 4907 }; 4908 4909 pdc_intc: interrupt-controller@b220000 { 4910 compatible = "qcom,sdm845-pdc", "qcom,pdc"; 4911 reg = <0 0x0b220000 0 0x30000>; 4912 qcom,pdc-ranges = <0 480 94>, <94 609 15>, <115 630 7>; 4913 #interrupt-cells = <2>; 4914 interrupt-parent = <&intc>; 4915 interrupt-controller; 4916 }; 4917 4918 pdc_reset: reset-controller@b2e0000 { 4919 compatible = "qcom,sdm845-pdc-global"; 4920 reg = <0 0x0b2e0000 0 0x20000>; 4921 #reset-cells = <1>; 4922 }; 4923 4924 tsens0: thermal-sensor@c263000 { 4925 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; 4926 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 4927 <0 0x0c222000 0 0x1ff>; /* SROT */ 4928 #qcom,sensors = <13>; 4929 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 4930 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 4931 interrupt-names = "uplow", "critical"; 4932 #thermal-sensor-cells = <1>; 4933 }; 4934 4935 tsens1: thermal-sensor@c265000 { 4936 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; 4937 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 4938 <0 0x0c223000 0 0x1ff>; /* SROT */ 4939 #qcom,sensors = <8>; 4940 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 4941 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 4942 interrupt-names = "uplow", "critical"; 4943 #thermal-sensor-cells = <1>; 4944 }; 4945 4946 aoss_reset: reset-controller@c2a0000 { 4947 compatible = "qcom,sdm845-aoss-cc"; 4948 reg = <0 0x0c2a0000 0 0x31000>; 4949 #reset-cells = <1>; 4950 }; 4951 4952 aoss_qmp: power-management@c300000 { 4953 compatible = "qcom,sdm845-aoss-qmp", "qcom,aoss-qmp"; 4954 reg = <0 0x0c300000 0 0x400>; 4955 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; 4956 mboxes = <&apss_shared 0>; 4957 4958 #clock-cells = <0>; 4959 4960 cx_cdev: cx { 4961 #cooling-cells = <2>; 4962 }; 4963 4964 ebi_cdev: ebi { 4965 #cooling-cells = <2>; 4966 }; 4967 }; 4968 4969 sram@c3f0000 { 4970 compatible = "qcom,sdm845-rpmh-stats"; 4971 reg = <0 0x0c3f0000 0 0x400>; 4972 }; 4973 4974 spmi_bus: spmi@c440000 { 4975 compatible = "qcom,spmi-pmic-arb"; 4976 reg = <0 0x0c440000 0 0x1100>, 4977 <0 0x0c600000 0 0x2000000>, 4978 <0 0x0e600000 0 0x100000>, 4979 <0 0x0e700000 0 0xa0000>, 4980 <0 0x0c40a000 0 0x26000>; 4981 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 4982 interrupt-names = "periph_irq"; 4983 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>; 4984 qcom,ee = <0>; 4985 qcom,channel = <0>; 4986 #address-cells = <2>; 4987 #size-cells = <0>; 4988 interrupt-controller; 4989 #interrupt-cells = <4>; 4990 }; 4991 4992 sram@146bf000 { 4993 compatible = "qcom,sdm845-imem", "syscon", "simple-mfd"; 4994 reg = <0 0x146bf000 0 0x1000>; 4995 4996 #address-cells = <1>; 4997 #size-cells = <1>; 4998 4999 ranges = <0 0 0x146bf000 0x1000>; 5000 5001 pil-reloc@94c { 5002 compatible = "qcom,pil-reloc-info"; 5003 reg = <0x94c 0xc8>; 5004 }; 5005 }; 5006 5007 apps_smmu: iommu@15000000 { 5008 compatible = "qcom,sdm845-smmu-500", "arm,mmu-500"; 5009 reg = <0 0x15000000 0 0x80000>; 5010 #iommu-cells = <2>; 5011 #global-interrupts = <1>; 5012 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 5013 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 5014 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 5015 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 5016 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 5017 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 5018 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 5019 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 5020 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 5021 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 5022 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 5023 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 5024 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 5025 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 5026 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 5027 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 5028 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 5029 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 5030 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 5031 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 5032 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 5033 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 5034 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 5035 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 5036 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 5037 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 5038 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 5039 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 5040 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 5041 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 5042 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 5043 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 5044 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 5045 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 5046 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 5047 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 5048 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 5049 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 5050 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 5051 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 5052 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 5053 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 5054 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 5055 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 5056 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 5057 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 5058 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 5059 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 5060 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 5061 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 5062 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 5063 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 5064 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 5065 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 5066 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 5067 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 5068 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 5069 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 5070 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 5071 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 5072 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 5073 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 5074 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 5075 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 5076 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>; 5077 }; 5078 5079 lpasscc: clock-controller@17014000 { 5080 compatible = "qcom,sdm845-lpasscc"; 5081 reg = <0 0x17014000 0 0x1f004>, <0 0x17300000 0 0x200>; 5082 reg-names = "cc", "qdsp6ss"; 5083 #clock-cells = <1>; 5084 status = "disabled"; 5085 }; 5086 5087 gladiator_noc: interconnect@17900000 { 5088 compatible = "qcom,sdm845-gladiator-noc"; 5089 reg = <0 0x17900000 0 0xd080>; 5090 #interconnect-cells = <2>; 5091 qcom,bcm-voters = <&apps_bcm_voter>; 5092 }; 5093 5094 watchdog@17980000 { 5095 compatible = "qcom,apss-wdt-sdm845", "qcom,kpss-wdt"; 5096 reg = <0 0x17980000 0 0x1000>; 5097 clocks = <&sleep_clk>; 5098 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 5099 }; 5100 5101 apss_shared: mailbox@17990000 { 5102 compatible = "qcom,sdm845-apss-shared"; 5103 reg = <0 0x17990000 0 0x1000>; 5104 #mbox-cells = <1>; 5105 }; 5106 5107 apps_rsc: rsc@179c0000 { 5108 label = "apps_rsc"; 5109 compatible = "qcom,rpmh-rsc"; 5110 reg = <0 0x179c0000 0 0x10000>, 5111 <0 0x179d0000 0 0x10000>, 5112 <0 0x179e0000 0 0x10000>; 5113 reg-names = "drv-0", "drv-1", "drv-2"; 5114 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 5115 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 5116 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 5117 qcom,tcs-offset = <0xd00>; 5118 qcom,drv-id = <2>; 5119 qcom,tcs-config = <ACTIVE_TCS 2>, 5120 <SLEEP_TCS 3>, 5121 <WAKE_TCS 3>, 5122 <CONTROL_TCS 1>; 5123 power-domains = <&CLUSTER_PD>; 5124 5125 apps_bcm_voter: bcm-voter { 5126 compatible = "qcom,bcm-voter"; 5127 }; 5128 5129 rpmhcc: clock-controller { 5130 compatible = "qcom,sdm845-rpmh-clk"; 5131 #clock-cells = <1>; 5132 clock-names = "xo"; 5133 clocks = <&xo_board>; 5134 }; 5135 5136 rpmhpd: power-controller { 5137 compatible = "qcom,sdm845-rpmhpd"; 5138 #power-domain-cells = <1>; 5139 operating-points-v2 = <&rpmhpd_opp_table>; 5140 5141 rpmhpd_opp_table: opp-table { 5142 compatible = "operating-points-v2"; 5143 5144 rpmhpd_opp_ret: opp1 { 5145 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 5146 }; 5147 5148 rpmhpd_opp_min_svs: opp2 { 5149 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 5150 }; 5151 5152 rpmhpd_opp_low_svs: opp3 { 5153 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 5154 }; 5155 5156 rpmhpd_opp_svs: opp4 { 5157 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 5158 }; 5159 5160 rpmhpd_opp_svs_l1: opp5 { 5161 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 5162 }; 5163 5164 rpmhpd_opp_nom: opp6 { 5165 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 5166 }; 5167 5168 rpmhpd_opp_nom_l1: opp7 { 5169 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 5170 }; 5171 5172 rpmhpd_opp_nom_l2: opp8 { 5173 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 5174 }; 5175 5176 rpmhpd_opp_turbo: opp9 { 5177 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 5178 }; 5179 5180 rpmhpd_opp_turbo_l1: opp10 { 5181 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 5182 }; 5183 }; 5184 }; 5185 }; 5186 5187 intc: interrupt-controller@17a00000 { 5188 compatible = "arm,gic-v3"; 5189 #address-cells = <2>; 5190 #size-cells = <2>; 5191 ranges; 5192 #interrupt-cells = <3>; 5193 interrupt-controller; 5194 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 5195 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 5196 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 5197 5198 msi-controller@17a40000 { 5199 compatible = "arm,gic-v3-its"; 5200 msi-controller; 5201 #msi-cells = <1>; 5202 reg = <0 0x17a40000 0 0x20000>; 5203 status = "disabled"; 5204 }; 5205 }; 5206 5207 slimbam: dma-controller@17184000 { 5208 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 5209 qcom,controlled-remotely; 5210 reg = <0 0x17184000 0 0x2a000>; 5211 num-channels = <31>; 5212 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 5213 #dma-cells = <1>; 5214 qcom,ee = <1>; 5215 qcom,num-ees = <2>; 5216 iommus = <&apps_smmu 0x1806 0x0>; 5217 }; 5218 5219 timer@17c90000 { 5220 #address-cells = <1>; 5221 #size-cells = <1>; 5222 ranges = <0 0 0 0x20000000>; 5223 compatible = "arm,armv7-timer-mem"; 5224 reg = <0 0x17c90000 0 0x1000>; 5225 5226 frame@17ca0000 { 5227 frame-number = <0>; 5228 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 5229 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 5230 reg = <0x17ca0000 0x1000>, 5231 <0x17cb0000 0x1000>; 5232 }; 5233 5234 frame@17cc0000 { 5235 frame-number = <1>; 5236 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 5237 reg = <0x17cc0000 0x1000>; 5238 status = "disabled"; 5239 }; 5240 5241 frame@17cd0000 { 5242 frame-number = <2>; 5243 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 5244 reg = <0x17cd0000 0x1000>; 5245 status = "disabled"; 5246 }; 5247 5248 frame@17ce0000 { 5249 frame-number = <3>; 5250 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 5251 reg = <0x17ce0000 0x1000>; 5252 status = "disabled"; 5253 }; 5254 5255 frame@17cf0000 { 5256 frame-number = <4>; 5257 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 5258 reg = <0x17cf0000 0x1000>; 5259 status = "disabled"; 5260 }; 5261 5262 frame@17d00000 { 5263 frame-number = <5>; 5264 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 5265 reg = <0x17d00000 0x1000>; 5266 status = "disabled"; 5267 }; 5268 5269 frame@17d10000 { 5270 frame-number = <6>; 5271 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 5272 reg = <0x17d10000 0x1000>; 5273 status = "disabled"; 5274 }; 5275 }; 5276 5277 osm_l3: interconnect@17d41000 { 5278 compatible = "qcom,sdm845-osm-l3", "qcom,osm-l3"; 5279 reg = <0 0x17d41000 0 0x1400>; 5280 5281 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 5282 clock-names = "xo", "alternate"; 5283 5284 #interconnect-cells = <1>; 5285 }; 5286 5287 cpufreq_hw: cpufreq@17d43000 { 5288 compatible = "qcom,sdm845-cpufreq-hw", "qcom,cpufreq-hw"; 5289 reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>; 5290 reg-names = "freq-domain0", "freq-domain1"; 5291 5292 interrupts-extended = <&lmh_cluster0 0>, <&lmh_cluster1 0>; 5293 5294 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 5295 clock-names = "xo", "alternate"; 5296 5297 #freq-domain-cells = <1>; 5298 #clock-cells = <1>; 5299 }; 5300 5301 wifi: wifi@18800000 { 5302 compatible = "qcom,wcn3990-wifi"; 5303 status = "disabled"; 5304 reg = <0 0x18800000 0 0x800000>; 5305 reg-names = "membase"; 5306 memory-region = <&wlan_msa_mem>; 5307 clock-names = "cxo_ref_clk_pin"; 5308 clocks = <&rpmhcc RPMH_RF_CLK2>; 5309 interrupts = 5310 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 5311 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 5312 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 5313 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 5314 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 5315 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 5316 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 5317 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 5318 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 5319 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 5320 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 5321 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 5322 iommus = <&apps_smmu 0x0040 0x1>; 5323 }; 5324 }; 5325 5326 sound: sound { 5327 }; 5328 5329 thermal-zones { 5330 cpu0-thermal { 5331 polling-delay-passive = <250>; 5332 polling-delay = <1000>; 5333 5334 thermal-sensors = <&tsens0 1>; 5335 5336 trips { 5337 cpu0_alert0: trip-point0 { 5338 temperature = <90000>; 5339 hysteresis = <2000>; 5340 type = "passive"; 5341 }; 5342 5343 cpu0_alert1: trip-point1 { 5344 temperature = <95000>; 5345 hysteresis = <2000>; 5346 type = "passive"; 5347 }; 5348 5349 cpu0_crit: cpu-crit { 5350 temperature = <110000>; 5351 hysteresis = <1000>; 5352 type = "critical"; 5353 }; 5354 }; 5355 }; 5356 5357 cpu1-thermal { 5358 polling-delay-passive = <250>; 5359 polling-delay = <1000>; 5360 5361 thermal-sensors = <&tsens0 2>; 5362 5363 trips { 5364 cpu1_alert0: trip-point0 { 5365 temperature = <90000>; 5366 hysteresis = <2000>; 5367 type = "passive"; 5368 }; 5369 5370 cpu1_alert1: trip-point1 { 5371 temperature = <95000>; 5372 hysteresis = <2000>; 5373 type = "passive"; 5374 }; 5375 5376 cpu1_crit: cpu-crit { 5377 temperature = <110000>; 5378 hysteresis = <1000>; 5379 type = "critical"; 5380 }; 5381 }; 5382 }; 5383 5384 cpu2-thermal { 5385 polling-delay-passive = <250>; 5386 polling-delay = <1000>; 5387 5388 thermal-sensors = <&tsens0 3>; 5389 5390 trips { 5391 cpu2_alert0: trip-point0 { 5392 temperature = <90000>; 5393 hysteresis = <2000>; 5394 type = "passive"; 5395 }; 5396 5397 cpu2_alert1: trip-point1 { 5398 temperature = <95000>; 5399 hysteresis = <2000>; 5400 type = "passive"; 5401 }; 5402 5403 cpu2_crit: cpu-crit { 5404 temperature = <110000>; 5405 hysteresis = <1000>; 5406 type = "critical"; 5407 }; 5408 }; 5409 }; 5410 5411 cpu3-thermal { 5412 polling-delay-passive = <250>; 5413 polling-delay = <1000>; 5414 5415 thermal-sensors = <&tsens0 4>; 5416 5417 trips { 5418 cpu3_alert0: trip-point0 { 5419 temperature = <90000>; 5420 hysteresis = <2000>; 5421 type = "passive"; 5422 }; 5423 5424 cpu3_alert1: trip-point1 { 5425 temperature = <95000>; 5426 hysteresis = <2000>; 5427 type = "passive"; 5428 }; 5429 5430 cpu3_crit: cpu-crit { 5431 temperature = <110000>; 5432 hysteresis = <1000>; 5433 type = "critical"; 5434 }; 5435 }; 5436 }; 5437 5438 cpu4-thermal { 5439 polling-delay-passive = <250>; 5440 polling-delay = <1000>; 5441 5442 thermal-sensors = <&tsens0 7>; 5443 5444 trips { 5445 cpu4_alert0: trip-point0 { 5446 temperature = <90000>; 5447 hysteresis = <2000>; 5448 type = "passive"; 5449 }; 5450 5451 cpu4_alert1: trip-point1 { 5452 temperature = <95000>; 5453 hysteresis = <2000>; 5454 type = "passive"; 5455 }; 5456 5457 cpu4_crit: cpu-crit { 5458 temperature = <110000>; 5459 hysteresis = <1000>; 5460 type = "critical"; 5461 }; 5462 }; 5463 }; 5464 5465 cpu5-thermal { 5466 polling-delay-passive = <250>; 5467 polling-delay = <1000>; 5468 5469 thermal-sensors = <&tsens0 8>; 5470 5471 trips { 5472 cpu5_alert0: trip-point0 { 5473 temperature = <90000>; 5474 hysteresis = <2000>; 5475 type = "passive"; 5476 }; 5477 5478 cpu5_alert1: trip-point1 { 5479 temperature = <95000>; 5480 hysteresis = <2000>; 5481 type = "passive"; 5482 }; 5483 5484 cpu5_crit: cpu-crit { 5485 temperature = <110000>; 5486 hysteresis = <1000>; 5487 type = "critical"; 5488 }; 5489 }; 5490 }; 5491 5492 cpu6-thermal { 5493 polling-delay-passive = <250>; 5494 polling-delay = <1000>; 5495 5496 thermal-sensors = <&tsens0 9>; 5497 5498 trips { 5499 cpu6_alert0: trip-point0 { 5500 temperature = <90000>; 5501 hysteresis = <2000>; 5502 type = "passive"; 5503 }; 5504 5505 cpu6_alert1: trip-point1 { 5506 temperature = <95000>; 5507 hysteresis = <2000>; 5508 type = "passive"; 5509 }; 5510 5511 cpu6_crit: cpu-crit { 5512 temperature = <110000>; 5513 hysteresis = <1000>; 5514 type = "critical"; 5515 }; 5516 }; 5517 }; 5518 5519 cpu7-thermal { 5520 polling-delay-passive = <250>; 5521 polling-delay = <1000>; 5522 5523 thermal-sensors = <&tsens0 10>; 5524 5525 trips { 5526 cpu7_alert0: trip-point0 { 5527 temperature = <90000>; 5528 hysteresis = <2000>; 5529 type = "passive"; 5530 }; 5531 5532 cpu7_alert1: trip-point1 { 5533 temperature = <95000>; 5534 hysteresis = <2000>; 5535 type = "passive"; 5536 }; 5537 5538 cpu7_crit: cpu-crit { 5539 temperature = <110000>; 5540 hysteresis = <1000>; 5541 type = "critical"; 5542 }; 5543 }; 5544 }; 5545 5546 aoss0-thermal { 5547 polling-delay-passive = <250>; 5548 polling-delay = <1000>; 5549 5550 thermal-sensors = <&tsens0 0>; 5551 5552 trips { 5553 aoss0_alert0: trip-point0 { 5554 temperature = <90000>; 5555 hysteresis = <2000>; 5556 type = "hot"; 5557 }; 5558 }; 5559 }; 5560 5561 cluster0-thermal { 5562 polling-delay-passive = <250>; 5563 polling-delay = <1000>; 5564 5565 thermal-sensors = <&tsens0 5>; 5566 5567 trips { 5568 cluster0_alert0: trip-point0 { 5569 temperature = <90000>; 5570 hysteresis = <2000>; 5571 type = "hot"; 5572 }; 5573 cluster0_crit: cluster0_crit { 5574 temperature = <110000>; 5575 hysteresis = <2000>; 5576 type = "critical"; 5577 }; 5578 }; 5579 }; 5580 5581 cluster1-thermal { 5582 polling-delay-passive = <250>; 5583 polling-delay = <1000>; 5584 5585 thermal-sensors = <&tsens0 6>; 5586 5587 trips { 5588 cluster1_alert0: trip-point0 { 5589 temperature = <90000>; 5590 hysteresis = <2000>; 5591 type = "hot"; 5592 }; 5593 cluster1_crit: cluster1_crit { 5594 temperature = <110000>; 5595 hysteresis = <2000>; 5596 type = "critical"; 5597 }; 5598 }; 5599 }; 5600 5601 gpu-top-thermal { 5602 polling-delay-passive = <250>; 5603 polling-delay = <1000>; 5604 5605 thermal-sensors = <&tsens0 11>; 5606 5607 trips { 5608 gpu1_alert0: trip-point0 { 5609 temperature = <90000>; 5610 hysteresis = <2000>; 5611 type = "hot"; 5612 }; 5613 }; 5614 }; 5615 5616 gpu-bottom-thermal { 5617 polling-delay-passive = <250>; 5618 polling-delay = <1000>; 5619 5620 thermal-sensors = <&tsens0 12>; 5621 5622 trips { 5623 gpu2_alert0: trip-point0 { 5624 temperature = <90000>; 5625 hysteresis = <2000>; 5626 type = "hot"; 5627 }; 5628 }; 5629 }; 5630 5631 aoss1-thermal { 5632 polling-delay-passive = <250>; 5633 polling-delay = <1000>; 5634 5635 thermal-sensors = <&tsens1 0>; 5636 5637 trips { 5638 aoss1_alert0: trip-point0 { 5639 temperature = <90000>; 5640 hysteresis = <2000>; 5641 type = "hot"; 5642 }; 5643 }; 5644 }; 5645 5646 q6-modem-thermal { 5647 polling-delay-passive = <250>; 5648 polling-delay = <1000>; 5649 5650 thermal-sensors = <&tsens1 1>; 5651 5652 trips { 5653 q6_modem_alert0: trip-point0 { 5654 temperature = <90000>; 5655 hysteresis = <2000>; 5656 type = "hot"; 5657 }; 5658 }; 5659 }; 5660 5661 mem-thermal { 5662 polling-delay-passive = <250>; 5663 polling-delay = <1000>; 5664 5665 thermal-sensors = <&tsens1 2>; 5666 5667 trips { 5668 mem_alert0: trip-point0 { 5669 temperature = <90000>; 5670 hysteresis = <2000>; 5671 type = "hot"; 5672 }; 5673 }; 5674 }; 5675 5676 wlan-thermal { 5677 polling-delay-passive = <250>; 5678 polling-delay = <1000>; 5679 5680 thermal-sensors = <&tsens1 3>; 5681 5682 trips { 5683 wlan_alert0: trip-point0 { 5684 temperature = <90000>; 5685 hysteresis = <2000>; 5686 type = "hot"; 5687 }; 5688 }; 5689 }; 5690 5691 q6-hvx-thermal { 5692 polling-delay-passive = <250>; 5693 polling-delay = <1000>; 5694 5695 thermal-sensors = <&tsens1 4>; 5696 5697 trips { 5698 q6_hvx_alert0: trip-point0 { 5699 temperature = <90000>; 5700 hysteresis = <2000>; 5701 type = "hot"; 5702 }; 5703 }; 5704 }; 5705 5706 camera-thermal { 5707 polling-delay-passive = <250>; 5708 polling-delay = <1000>; 5709 5710 thermal-sensors = <&tsens1 5>; 5711 5712 trips { 5713 camera_alert0: trip-point0 { 5714 temperature = <90000>; 5715 hysteresis = <2000>; 5716 type = "hot"; 5717 }; 5718 }; 5719 }; 5720 5721 video-thermal { 5722 polling-delay-passive = <250>; 5723 polling-delay = <1000>; 5724 5725 thermal-sensors = <&tsens1 6>; 5726 5727 trips { 5728 video_alert0: trip-point0 { 5729 temperature = <90000>; 5730 hysteresis = <2000>; 5731 type = "hot"; 5732 }; 5733 }; 5734 }; 5735 5736 modem-thermal { 5737 polling-delay-passive = <250>; 5738 polling-delay = <1000>; 5739 5740 thermal-sensors = <&tsens1 7>; 5741 5742 trips { 5743 modem_alert0: trip-point0 { 5744 temperature = <90000>; 5745 hysteresis = <2000>; 5746 type = "hot"; 5747 }; 5748 }; 5749 }; 5750 }; 5751 5752 timer { 5753 compatible = "arm,armv8-timer"; 5754 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 5755 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 5756 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 5757 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 5758 }; 5759}; 5760