1// SPDX-License-Identifier: GPL-2.0 2/* 3 * SDM845 SoC device tree source 4 * 5 * Copyright (c) 2018, The Linux Foundation. All rights reserved. 6 */ 7 8#include <dt-bindings/clock/qcom,camcc-sdm845.h> 9#include <dt-bindings/clock/qcom,dispcc-sdm845.h> 10#include <dt-bindings/clock/qcom,gcc-sdm845.h> 11#include <dt-bindings/clock/qcom,gpucc-sdm845.h> 12#include <dt-bindings/clock/qcom,lpass-sdm845.h> 13#include <dt-bindings/clock/qcom,rpmh.h> 14#include <dt-bindings/clock/qcom,videocc-sdm845.h> 15#include <dt-bindings/interconnect/qcom,sdm845.h> 16#include <dt-bindings/interrupt-controller/arm-gic.h> 17#include <dt-bindings/phy/phy-qcom-qusb2.h> 18#include <dt-bindings/power/qcom-rpmpd.h> 19#include <dt-bindings/reset/qcom,sdm845-aoss.h> 20#include <dt-bindings/reset/qcom,sdm845-pdc.h> 21#include <dt-bindings/soc/qcom,apr.h> 22#include <dt-bindings/soc/qcom,rpmh-rsc.h> 23#include <dt-bindings/clock/qcom,gcc-sdm845.h> 24#include <dt-bindings/thermal/thermal.h> 25 26/ { 27 interrupt-parent = <&intc>; 28 29 #address-cells = <2>; 30 #size-cells = <2>; 31 32 aliases { 33 i2c0 = &i2c0; 34 i2c1 = &i2c1; 35 i2c2 = &i2c2; 36 i2c3 = &i2c3; 37 i2c4 = &i2c4; 38 i2c5 = &i2c5; 39 i2c6 = &i2c6; 40 i2c7 = &i2c7; 41 i2c8 = &i2c8; 42 i2c9 = &i2c9; 43 i2c10 = &i2c10; 44 i2c11 = &i2c11; 45 i2c12 = &i2c12; 46 i2c13 = &i2c13; 47 i2c14 = &i2c14; 48 i2c15 = &i2c15; 49 spi0 = &spi0; 50 spi1 = &spi1; 51 spi2 = &spi2; 52 spi3 = &spi3; 53 spi4 = &spi4; 54 spi5 = &spi5; 55 spi6 = &spi6; 56 spi7 = &spi7; 57 spi8 = &spi8; 58 spi9 = &spi9; 59 spi10 = &spi10; 60 spi11 = &spi11; 61 spi12 = &spi12; 62 spi13 = &spi13; 63 spi14 = &spi14; 64 spi15 = &spi15; 65 }; 66 67 chosen { }; 68 69 memory@80000000 { 70 device_type = "memory"; 71 /* We expect the bootloader to fill in the size */ 72 reg = <0 0x80000000 0 0>; 73 }; 74 75 reserved-memory { 76 #address-cells = <2>; 77 #size-cells = <2>; 78 ranges; 79 80 hyp_mem: memory@85700000 { 81 reg = <0 0x85700000 0 0x600000>; 82 no-map; 83 }; 84 85 xbl_mem: memory@85e00000 { 86 reg = <0 0x85e00000 0 0x100000>; 87 no-map; 88 }; 89 90 aop_mem: memory@85fc0000 { 91 reg = <0 0x85fc0000 0 0x20000>; 92 no-map; 93 }; 94 95 aop_cmd_db_mem: memory@85fe0000 { 96 compatible = "qcom,cmd-db"; 97 reg = <0x0 0x85fe0000 0 0x20000>; 98 no-map; 99 }; 100 101 smem_mem: memory@86000000 { 102 reg = <0x0 0x86000000 0 0x200000>; 103 no-map; 104 }; 105 106 tz_mem: memory@86200000 { 107 reg = <0 0x86200000 0 0x2d00000>; 108 no-map; 109 }; 110 111 rmtfs_mem: memory@88f00000 { 112 compatible = "qcom,rmtfs-mem"; 113 reg = <0 0x88f00000 0 0x200000>; 114 no-map; 115 116 qcom,client-id = <1>; 117 qcom,vmid = <15>; 118 }; 119 120 qseecom_mem: memory@8ab00000 { 121 reg = <0 0x8ab00000 0 0x1400000>; 122 no-map; 123 }; 124 125 camera_mem: memory@8bf00000 { 126 reg = <0 0x8bf00000 0 0x500000>; 127 no-map; 128 }; 129 130 ipa_fw_mem: memory@8c400000 { 131 reg = <0 0x8c400000 0 0x10000>; 132 no-map; 133 }; 134 135 ipa_gsi_mem: memory@8c410000 { 136 reg = <0 0x8c410000 0 0x5000>; 137 no-map; 138 }; 139 140 gpu_mem: memory@8c415000 { 141 reg = <0 0x8c415000 0 0x2000>; 142 no-map; 143 }; 144 145 adsp_mem: memory@8c500000 { 146 reg = <0 0x8c500000 0 0x1a00000>; 147 no-map; 148 }; 149 150 wlan_msa_mem: memory@8df00000 { 151 reg = <0 0x8df00000 0 0x100000>; 152 no-map; 153 }; 154 155 mpss_region: memory@8e000000 { 156 reg = <0 0x8e000000 0 0x7800000>; 157 no-map; 158 }; 159 160 venus_mem: memory@95800000 { 161 reg = <0 0x95800000 0 0x500000>; 162 no-map; 163 }; 164 165 cdsp_mem: memory@95d00000 { 166 reg = <0 0x95d00000 0 0x800000>; 167 no-map; 168 }; 169 170 mba_region: memory@96500000 { 171 reg = <0 0x96500000 0 0x200000>; 172 no-map; 173 }; 174 175 slpi_mem: memory@96700000 { 176 reg = <0 0x96700000 0 0x1400000>; 177 no-map; 178 }; 179 180 spss_mem: memory@97b00000 { 181 reg = <0 0x97b00000 0 0x100000>; 182 no-map; 183 }; 184 }; 185 186 cpus { 187 #address-cells = <2>; 188 #size-cells = <0>; 189 190 CPU0: cpu@0 { 191 device_type = "cpu"; 192 compatible = "qcom,kryo385"; 193 reg = <0x0 0x0>; 194 enable-method = "psci"; 195 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 196 &LITTLE_CPU_SLEEP_1 197 &CLUSTER_SLEEP_0>; 198 capacity-dmips-mhz = <607>; 199 dynamic-power-coefficient = <100>; 200 qcom,freq-domain = <&cpufreq_hw 0>; 201 #cooling-cells = <2>; 202 next-level-cache = <&L2_0>; 203 L2_0: l2-cache { 204 compatible = "cache"; 205 next-level-cache = <&L3_0>; 206 L3_0: l3-cache { 207 compatible = "cache"; 208 }; 209 }; 210 }; 211 212 CPU1: cpu@100 { 213 device_type = "cpu"; 214 compatible = "qcom,kryo385"; 215 reg = <0x0 0x100>; 216 enable-method = "psci"; 217 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 218 &LITTLE_CPU_SLEEP_1 219 &CLUSTER_SLEEP_0>; 220 capacity-dmips-mhz = <607>; 221 dynamic-power-coefficient = <100>; 222 qcom,freq-domain = <&cpufreq_hw 0>; 223 #cooling-cells = <2>; 224 next-level-cache = <&L2_100>; 225 L2_100: l2-cache { 226 compatible = "cache"; 227 next-level-cache = <&L3_0>; 228 }; 229 }; 230 231 CPU2: cpu@200 { 232 device_type = "cpu"; 233 compatible = "qcom,kryo385"; 234 reg = <0x0 0x200>; 235 enable-method = "psci"; 236 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 237 &LITTLE_CPU_SLEEP_1 238 &CLUSTER_SLEEP_0>; 239 capacity-dmips-mhz = <607>; 240 dynamic-power-coefficient = <100>; 241 qcom,freq-domain = <&cpufreq_hw 0>; 242 #cooling-cells = <2>; 243 next-level-cache = <&L2_200>; 244 L2_200: l2-cache { 245 compatible = "cache"; 246 next-level-cache = <&L3_0>; 247 }; 248 }; 249 250 CPU3: cpu@300 { 251 device_type = "cpu"; 252 compatible = "qcom,kryo385"; 253 reg = <0x0 0x300>; 254 enable-method = "psci"; 255 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 256 &LITTLE_CPU_SLEEP_1 257 &CLUSTER_SLEEP_0>; 258 capacity-dmips-mhz = <607>; 259 dynamic-power-coefficient = <100>; 260 qcom,freq-domain = <&cpufreq_hw 0>; 261 #cooling-cells = <2>; 262 next-level-cache = <&L2_300>; 263 L2_300: l2-cache { 264 compatible = "cache"; 265 next-level-cache = <&L3_0>; 266 }; 267 }; 268 269 CPU4: cpu@400 { 270 device_type = "cpu"; 271 compatible = "qcom,kryo385"; 272 reg = <0x0 0x400>; 273 enable-method = "psci"; 274 capacity-dmips-mhz = <1024>; 275 cpu-idle-states = <&BIG_CPU_SLEEP_0 276 &BIG_CPU_SLEEP_1 277 &CLUSTER_SLEEP_0>; 278 dynamic-power-coefficient = <396>; 279 qcom,freq-domain = <&cpufreq_hw 1>; 280 #cooling-cells = <2>; 281 next-level-cache = <&L2_400>; 282 L2_400: l2-cache { 283 compatible = "cache"; 284 next-level-cache = <&L3_0>; 285 }; 286 }; 287 288 CPU5: cpu@500 { 289 device_type = "cpu"; 290 compatible = "qcom,kryo385"; 291 reg = <0x0 0x500>; 292 enable-method = "psci"; 293 capacity-dmips-mhz = <1024>; 294 cpu-idle-states = <&BIG_CPU_SLEEP_0 295 &BIG_CPU_SLEEP_1 296 &CLUSTER_SLEEP_0>; 297 dynamic-power-coefficient = <396>; 298 qcom,freq-domain = <&cpufreq_hw 1>; 299 #cooling-cells = <2>; 300 next-level-cache = <&L2_500>; 301 L2_500: l2-cache { 302 compatible = "cache"; 303 next-level-cache = <&L3_0>; 304 }; 305 }; 306 307 CPU6: cpu@600 { 308 device_type = "cpu"; 309 compatible = "qcom,kryo385"; 310 reg = <0x0 0x600>; 311 enable-method = "psci"; 312 capacity-dmips-mhz = <1024>; 313 cpu-idle-states = <&BIG_CPU_SLEEP_0 314 &BIG_CPU_SLEEP_1 315 &CLUSTER_SLEEP_0>; 316 dynamic-power-coefficient = <396>; 317 qcom,freq-domain = <&cpufreq_hw 1>; 318 #cooling-cells = <2>; 319 next-level-cache = <&L2_600>; 320 L2_600: l2-cache { 321 compatible = "cache"; 322 next-level-cache = <&L3_0>; 323 }; 324 }; 325 326 CPU7: cpu@700 { 327 device_type = "cpu"; 328 compatible = "qcom,kryo385"; 329 reg = <0x0 0x700>; 330 enable-method = "psci"; 331 capacity-dmips-mhz = <1024>; 332 cpu-idle-states = <&BIG_CPU_SLEEP_0 333 &BIG_CPU_SLEEP_1 334 &CLUSTER_SLEEP_0>; 335 dynamic-power-coefficient = <396>; 336 qcom,freq-domain = <&cpufreq_hw 1>; 337 #cooling-cells = <2>; 338 next-level-cache = <&L2_700>; 339 L2_700: l2-cache { 340 compatible = "cache"; 341 next-level-cache = <&L3_0>; 342 }; 343 }; 344 345 cpu-map { 346 cluster0 { 347 core0 { 348 cpu = <&CPU0>; 349 }; 350 351 core1 { 352 cpu = <&CPU1>; 353 }; 354 355 core2 { 356 cpu = <&CPU2>; 357 }; 358 359 core3 { 360 cpu = <&CPU3>; 361 }; 362 363 core4 { 364 cpu = <&CPU4>; 365 }; 366 367 core5 { 368 cpu = <&CPU5>; 369 }; 370 371 core6 { 372 cpu = <&CPU6>; 373 }; 374 375 core7 { 376 cpu = <&CPU7>; 377 }; 378 }; 379 }; 380 381 idle-states { 382 entry-method = "psci"; 383 384 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 385 compatible = "arm,idle-state"; 386 idle-state-name = "little-power-down"; 387 arm,psci-suspend-param = <0x40000003>; 388 entry-latency-us = <350>; 389 exit-latency-us = <461>; 390 min-residency-us = <1890>; 391 local-timer-stop; 392 }; 393 394 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 395 compatible = "arm,idle-state"; 396 idle-state-name = "little-rail-power-down"; 397 arm,psci-suspend-param = <0x40000004>; 398 entry-latency-us = <360>; 399 exit-latency-us = <531>; 400 min-residency-us = <3934>; 401 local-timer-stop; 402 }; 403 404 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 405 compatible = "arm,idle-state"; 406 idle-state-name = "big-power-down"; 407 arm,psci-suspend-param = <0x40000003>; 408 entry-latency-us = <264>; 409 exit-latency-us = <621>; 410 min-residency-us = <952>; 411 local-timer-stop; 412 }; 413 414 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 415 compatible = "arm,idle-state"; 416 idle-state-name = "big-rail-power-down"; 417 arm,psci-suspend-param = <0x40000004>; 418 entry-latency-us = <702>; 419 exit-latency-us = <1061>; 420 min-residency-us = <4488>; 421 local-timer-stop; 422 }; 423 424 CLUSTER_SLEEP_0: cluster-sleep-0 { 425 compatible = "arm,idle-state"; 426 idle-state-name = "cluster-power-down"; 427 arm,psci-suspend-param = <0x400000F4>; 428 entry-latency-us = <3263>; 429 exit-latency-us = <6562>; 430 min-residency-us = <9987>; 431 local-timer-stop; 432 }; 433 }; 434 }; 435 436 pmu { 437 compatible = "arm,armv8-pmuv3"; 438 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; 439 }; 440 441 timer { 442 compatible = "arm,armv8-timer"; 443 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 444 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 445 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 446 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 447 }; 448 449 clocks { 450 xo_board: xo-board { 451 compatible = "fixed-clock"; 452 #clock-cells = <0>; 453 clock-frequency = <38400000>; 454 clock-output-names = "xo_board"; 455 }; 456 457 sleep_clk: sleep-clk { 458 compatible = "fixed-clock"; 459 #clock-cells = <0>; 460 clock-frequency = <32764>; 461 }; 462 }; 463 464 firmware { 465 scm { 466 compatible = "qcom,scm-sdm845", "qcom,scm"; 467 }; 468 }; 469 470 adsp_pas: remoteproc-adsp { 471 compatible = "qcom,sdm845-adsp-pas"; 472 473 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 474 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 475 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 476 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 477 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 478 interrupt-names = "wdog", "fatal", "ready", 479 "handover", "stop-ack"; 480 481 clocks = <&rpmhcc RPMH_CXO_CLK>; 482 clock-names = "xo"; 483 484 memory-region = <&adsp_mem>; 485 486 qcom,smem-states = <&adsp_smp2p_out 0>; 487 qcom,smem-state-names = "stop"; 488 489 status = "disabled"; 490 491 glink-edge { 492 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 493 label = "lpass"; 494 qcom,remote-pid = <2>; 495 mboxes = <&apss_shared 8>; 496 497 apr { 498 compatible = "qcom,apr-v2"; 499 qcom,glink-channels = "apr_audio_svc"; 500 qcom,apr-domain = <APR_DOMAIN_ADSP>; 501 #address-cells = <1>; 502 #size-cells = <0>; 503 qcom,intents = <512 20>; 504 505 apr-service@3 { 506 reg = <APR_SVC_ADSP_CORE>; 507 compatible = "qcom,q6core"; 508 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 509 }; 510 511 q6afe: apr-service@4 { 512 compatible = "qcom,q6afe"; 513 reg = <APR_SVC_AFE>; 514 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 515 q6afedai: dais { 516 compatible = "qcom,q6afe-dais"; 517 #address-cells = <1>; 518 #size-cells = <0>; 519 #sound-dai-cells = <1>; 520 }; 521 }; 522 523 q6asm: apr-service@7 { 524 compatible = "qcom,q6asm"; 525 reg = <APR_SVC_ASM>; 526 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 527 q6asmdai: dais { 528 compatible = "qcom,q6asm-dais"; 529 #address-cells = <1>; 530 #size-cells = <0>; 531 #sound-dai-cells = <1>; 532 iommus = <&apps_smmu 0x1821 0x0>; 533 }; 534 }; 535 536 q6adm: apr-service@8 { 537 compatible = "qcom,q6adm"; 538 reg = <APR_SVC_ADM>; 539 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 540 q6routing: routing { 541 compatible = "qcom,q6adm-routing"; 542 #sound-dai-cells = <0>; 543 }; 544 }; 545 }; 546 547 fastrpc { 548 compatible = "qcom,fastrpc"; 549 qcom,glink-channels = "fastrpcglink-apps-dsp"; 550 label = "adsp"; 551 #address-cells = <1>; 552 #size-cells = <0>; 553 554 compute-cb@3 { 555 compatible = "qcom,fastrpc-compute-cb"; 556 reg = <3>; 557 iommus = <&apps_smmu 0x1823 0x0>; 558 }; 559 560 compute-cb@4 { 561 compatible = "qcom,fastrpc-compute-cb"; 562 reg = <4>; 563 iommus = <&apps_smmu 0x1824 0x0>; 564 }; 565 }; 566 }; 567 }; 568 569 cdsp_pas: remoteproc-cdsp { 570 compatible = "qcom,sdm845-cdsp-pas"; 571 572 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 573 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 574 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 575 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 576 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 577 interrupt-names = "wdog", "fatal", "ready", 578 "handover", "stop-ack"; 579 580 clocks = <&rpmhcc RPMH_CXO_CLK>; 581 clock-names = "xo"; 582 583 memory-region = <&cdsp_mem>; 584 585 qcom,smem-states = <&cdsp_smp2p_out 0>; 586 qcom,smem-state-names = "stop"; 587 588 status = "disabled"; 589 590 glink-edge { 591 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>; 592 label = "turing"; 593 qcom,remote-pid = <5>; 594 mboxes = <&apss_shared 4>; 595 fastrpc { 596 compatible = "qcom,fastrpc"; 597 qcom,glink-channels = "fastrpcglink-apps-dsp"; 598 label = "cdsp"; 599 #address-cells = <1>; 600 #size-cells = <0>; 601 602 compute-cb@1 { 603 compatible = "qcom,fastrpc-compute-cb"; 604 reg = <1>; 605 iommus = <&apps_smmu 0x1401 0x30>; 606 }; 607 608 compute-cb@2 { 609 compatible = "qcom,fastrpc-compute-cb"; 610 reg = <2>; 611 iommus = <&apps_smmu 0x1402 0x30>; 612 }; 613 614 compute-cb@3 { 615 compatible = "qcom,fastrpc-compute-cb"; 616 reg = <3>; 617 iommus = <&apps_smmu 0x1403 0x30>; 618 }; 619 620 compute-cb@4 { 621 compatible = "qcom,fastrpc-compute-cb"; 622 reg = <4>; 623 iommus = <&apps_smmu 0x1404 0x30>; 624 }; 625 626 compute-cb@5 { 627 compatible = "qcom,fastrpc-compute-cb"; 628 reg = <5>; 629 iommus = <&apps_smmu 0x1405 0x30>; 630 }; 631 632 compute-cb@6 { 633 compatible = "qcom,fastrpc-compute-cb"; 634 reg = <6>; 635 iommus = <&apps_smmu 0x1406 0x30>; 636 }; 637 638 compute-cb@7 { 639 compatible = "qcom,fastrpc-compute-cb"; 640 reg = <7>; 641 iommus = <&apps_smmu 0x1407 0x30>; 642 }; 643 644 compute-cb@8 { 645 compatible = "qcom,fastrpc-compute-cb"; 646 reg = <8>; 647 iommus = <&apps_smmu 0x1408 0x30>; 648 }; 649 }; 650 }; 651 }; 652 653 tcsr_mutex: hwlock { 654 compatible = "qcom,tcsr-mutex"; 655 syscon = <&tcsr_mutex_regs 0 0x1000>; 656 #hwlock-cells = <1>; 657 }; 658 659 smem { 660 compatible = "qcom,smem"; 661 memory-region = <&smem_mem>; 662 hwlocks = <&tcsr_mutex 3>; 663 }; 664 665 smp2p-cdsp { 666 compatible = "qcom,smp2p"; 667 qcom,smem = <94>, <432>; 668 669 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; 670 671 mboxes = <&apss_shared 6>; 672 673 qcom,local-pid = <0>; 674 qcom,remote-pid = <5>; 675 676 cdsp_smp2p_out: master-kernel { 677 qcom,entry-name = "master-kernel"; 678 #qcom,smem-state-cells = <1>; 679 }; 680 681 cdsp_smp2p_in: slave-kernel { 682 qcom,entry-name = "slave-kernel"; 683 684 interrupt-controller; 685 #interrupt-cells = <2>; 686 }; 687 }; 688 689 smp2p-lpass { 690 compatible = "qcom,smp2p"; 691 qcom,smem = <443>, <429>; 692 693 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 694 695 mboxes = <&apss_shared 10>; 696 697 qcom,local-pid = <0>; 698 qcom,remote-pid = <2>; 699 700 adsp_smp2p_out: master-kernel { 701 qcom,entry-name = "master-kernel"; 702 #qcom,smem-state-cells = <1>; 703 }; 704 705 adsp_smp2p_in: slave-kernel { 706 qcom,entry-name = "slave-kernel"; 707 708 interrupt-controller; 709 #interrupt-cells = <2>; 710 }; 711 }; 712 713 smp2p-mpss { 714 compatible = "qcom,smp2p"; 715 qcom,smem = <435>, <428>; 716 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 717 mboxes = <&apss_shared 14>; 718 qcom,local-pid = <0>; 719 qcom,remote-pid = <1>; 720 721 modem_smp2p_out: master-kernel { 722 qcom,entry-name = "master-kernel"; 723 #qcom,smem-state-cells = <1>; 724 }; 725 726 modem_smp2p_in: slave-kernel { 727 qcom,entry-name = "slave-kernel"; 728 interrupt-controller; 729 #interrupt-cells = <2>; 730 }; 731 732 ipa_smp2p_out: ipa-ap-to-modem { 733 qcom,entry-name = "ipa"; 734 #qcom,smem-state-cells = <1>; 735 }; 736 737 ipa_smp2p_in: ipa-modem-to-ap { 738 qcom,entry-name = "ipa"; 739 interrupt-controller; 740 #interrupt-cells = <2>; 741 }; 742 }; 743 744 smp2p-slpi { 745 compatible = "qcom,smp2p"; 746 qcom,smem = <481>, <430>; 747 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>; 748 mboxes = <&apss_shared 26>; 749 qcom,local-pid = <0>; 750 qcom,remote-pid = <3>; 751 752 slpi_smp2p_out: master-kernel { 753 qcom,entry-name = "master-kernel"; 754 #qcom,smem-state-cells = <1>; 755 }; 756 757 slpi_smp2p_in: slave-kernel { 758 qcom,entry-name = "slave-kernel"; 759 interrupt-controller; 760 #interrupt-cells = <2>; 761 }; 762 }; 763 764 psci { 765 compatible = "arm,psci-1.0"; 766 method = "smc"; 767 }; 768 769 soc: soc@0 { 770 #address-cells = <2>; 771 #size-cells = <2>; 772 ranges = <0 0 0 0 0x10 0>; 773 dma-ranges = <0 0 0 0 0x10 0>; 774 compatible = "simple-bus"; 775 776 gcc: clock-controller@100000 { 777 compatible = "qcom,gcc-sdm845"; 778 reg = <0 0x00100000 0 0x1f0000>; 779 #clock-cells = <1>; 780 #reset-cells = <1>; 781 #power-domain-cells = <1>; 782 }; 783 784 qfprom@784000 { 785 compatible = "qcom,qfprom"; 786 reg = <0 0x00784000 0 0x8ff>; 787 #address-cells = <1>; 788 #size-cells = <1>; 789 790 qusb2p_hstx_trim: hstx-trim-primary@1eb { 791 reg = <0x1eb 0x1>; 792 bits = <1 4>; 793 }; 794 795 qusb2s_hstx_trim: hstx-trim-secondary@1eb { 796 reg = <0x1eb 0x2>; 797 bits = <6 4>; 798 }; 799 }; 800 801 rng: rng@793000 { 802 compatible = "qcom,prng-ee"; 803 reg = <0 0x00793000 0 0x1000>; 804 clocks = <&gcc GCC_PRNG_AHB_CLK>; 805 clock-names = "core"; 806 }; 807 808 qupv3_id_0: geniqup@8c0000 { 809 compatible = "qcom,geni-se-qup"; 810 reg = <0 0x008c0000 0 0x6000>; 811 clock-names = "m-ahb", "s-ahb"; 812 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 813 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 814 #address-cells = <2>; 815 #size-cells = <2>; 816 ranges; 817 status = "disabled"; 818 819 i2c0: i2c@880000 { 820 compatible = "qcom,geni-i2c"; 821 reg = <0 0x00880000 0 0x4000>; 822 clock-names = "se"; 823 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 824 pinctrl-names = "default"; 825 pinctrl-0 = <&qup_i2c0_default>; 826 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 827 #address-cells = <1>; 828 #size-cells = <0>; 829 status = "disabled"; 830 }; 831 832 spi0: spi@880000 { 833 compatible = "qcom,geni-spi"; 834 reg = <0 0x00880000 0 0x4000>; 835 clock-names = "se"; 836 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 837 pinctrl-names = "default"; 838 pinctrl-0 = <&qup_spi0_default>; 839 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 840 #address-cells = <1>; 841 #size-cells = <0>; 842 status = "disabled"; 843 }; 844 845 uart0: serial@880000 { 846 compatible = "qcom,geni-uart"; 847 reg = <0 0x00880000 0 0x4000>; 848 clock-names = "se"; 849 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 850 pinctrl-names = "default"; 851 pinctrl-0 = <&qup_uart0_default>; 852 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 853 status = "disabled"; 854 }; 855 856 i2c1: i2c@884000 { 857 compatible = "qcom,geni-i2c"; 858 reg = <0 0x00884000 0 0x4000>; 859 clock-names = "se"; 860 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 861 pinctrl-names = "default"; 862 pinctrl-0 = <&qup_i2c1_default>; 863 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 864 #address-cells = <1>; 865 #size-cells = <0>; 866 status = "disabled"; 867 }; 868 869 spi1: spi@884000 { 870 compatible = "qcom,geni-spi"; 871 reg = <0 0x00884000 0 0x4000>; 872 clock-names = "se"; 873 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 874 pinctrl-names = "default"; 875 pinctrl-0 = <&qup_spi1_default>; 876 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 877 #address-cells = <1>; 878 #size-cells = <0>; 879 status = "disabled"; 880 }; 881 882 uart1: serial@884000 { 883 compatible = "qcom,geni-uart"; 884 reg = <0 0x00884000 0 0x4000>; 885 clock-names = "se"; 886 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 887 pinctrl-names = "default"; 888 pinctrl-0 = <&qup_uart1_default>; 889 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 890 status = "disabled"; 891 }; 892 893 i2c2: i2c@888000 { 894 compatible = "qcom,geni-i2c"; 895 reg = <0 0x00888000 0 0x4000>; 896 clock-names = "se"; 897 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 898 pinctrl-names = "default"; 899 pinctrl-0 = <&qup_i2c2_default>; 900 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 901 #address-cells = <1>; 902 #size-cells = <0>; 903 status = "disabled"; 904 }; 905 906 spi2: spi@888000 { 907 compatible = "qcom,geni-spi"; 908 reg = <0 0x00888000 0 0x4000>; 909 clock-names = "se"; 910 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 911 pinctrl-names = "default"; 912 pinctrl-0 = <&qup_spi2_default>; 913 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 914 #address-cells = <1>; 915 #size-cells = <0>; 916 status = "disabled"; 917 }; 918 919 uart2: serial@888000 { 920 compatible = "qcom,geni-uart"; 921 reg = <0 0x00888000 0 0x4000>; 922 clock-names = "se"; 923 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 924 pinctrl-names = "default"; 925 pinctrl-0 = <&qup_uart2_default>; 926 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 927 status = "disabled"; 928 }; 929 930 i2c3: i2c@88c000 { 931 compatible = "qcom,geni-i2c"; 932 reg = <0 0x0088c000 0 0x4000>; 933 clock-names = "se"; 934 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 935 pinctrl-names = "default"; 936 pinctrl-0 = <&qup_i2c3_default>; 937 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 938 #address-cells = <1>; 939 #size-cells = <0>; 940 status = "disabled"; 941 }; 942 943 spi3: spi@88c000 { 944 compatible = "qcom,geni-spi"; 945 reg = <0 0x0088c000 0 0x4000>; 946 clock-names = "se"; 947 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 948 pinctrl-names = "default"; 949 pinctrl-0 = <&qup_spi3_default>; 950 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 951 #address-cells = <1>; 952 #size-cells = <0>; 953 status = "disabled"; 954 }; 955 956 uart3: serial@88c000 { 957 compatible = "qcom,geni-uart"; 958 reg = <0 0x0088c000 0 0x4000>; 959 clock-names = "se"; 960 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 961 pinctrl-names = "default"; 962 pinctrl-0 = <&qup_uart3_default>; 963 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 964 status = "disabled"; 965 }; 966 967 i2c4: i2c@890000 { 968 compatible = "qcom,geni-i2c"; 969 reg = <0 0x00890000 0 0x4000>; 970 clock-names = "se"; 971 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 972 pinctrl-names = "default"; 973 pinctrl-0 = <&qup_i2c4_default>; 974 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 975 #address-cells = <1>; 976 #size-cells = <0>; 977 status = "disabled"; 978 }; 979 980 spi4: spi@890000 { 981 compatible = "qcom,geni-spi"; 982 reg = <0 0x00890000 0 0x4000>; 983 clock-names = "se"; 984 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 985 pinctrl-names = "default"; 986 pinctrl-0 = <&qup_spi4_default>; 987 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 988 #address-cells = <1>; 989 #size-cells = <0>; 990 status = "disabled"; 991 }; 992 993 uart4: serial@890000 { 994 compatible = "qcom,geni-uart"; 995 reg = <0 0x00890000 0 0x4000>; 996 clock-names = "se"; 997 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 998 pinctrl-names = "default"; 999 pinctrl-0 = <&qup_uart4_default>; 1000 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1001 status = "disabled"; 1002 }; 1003 1004 i2c5: i2c@894000 { 1005 compatible = "qcom,geni-i2c"; 1006 reg = <0 0x00894000 0 0x4000>; 1007 clock-names = "se"; 1008 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1009 pinctrl-names = "default"; 1010 pinctrl-0 = <&qup_i2c5_default>; 1011 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1012 #address-cells = <1>; 1013 #size-cells = <0>; 1014 status = "disabled"; 1015 }; 1016 1017 spi5: spi@894000 { 1018 compatible = "qcom,geni-spi"; 1019 reg = <0 0x00894000 0 0x4000>; 1020 clock-names = "se"; 1021 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1022 pinctrl-names = "default"; 1023 pinctrl-0 = <&qup_spi5_default>; 1024 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1025 #address-cells = <1>; 1026 #size-cells = <0>; 1027 status = "disabled"; 1028 }; 1029 1030 uart5: serial@894000 { 1031 compatible = "qcom,geni-uart"; 1032 reg = <0 0x00894000 0 0x4000>; 1033 clock-names = "se"; 1034 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1035 pinctrl-names = "default"; 1036 pinctrl-0 = <&qup_uart5_default>; 1037 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1038 status = "disabled"; 1039 }; 1040 1041 i2c6: i2c@898000 { 1042 compatible = "qcom,geni-i2c"; 1043 reg = <0 0x00898000 0 0x4000>; 1044 clock-names = "se"; 1045 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1046 pinctrl-names = "default"; 1047 pinctrl-0 = <&qup_i2c6_default>; 1048 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1049 #address-cells = <1>; 1050 #size-cells = <0>; 1051 status = "disabled"; 1052 }; 1053 1054 spi6: spi@898000 { 1055 compatible = "qcom,geni-spi"; 1056 reg = <0 0x00898000 0 0x4000>; 1057 clock-names = "se"; 1058 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1059 pinctrl-names = "default"; 1060 pinctrl-0 = <&qup_spi6_default>; 1061 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1062 #address-cells = <1>; 1063 #size-cells = <0>; 1064 status = "disabled"; 1065 }; 1066 1067 uart6: serial@898000 { 1068 compatible = "qcom,geni-uart"; 1069 reg = <0 0x00898000 0 0x4000>; 1070 clock-names = "se"; 1071 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1072 pinctrl-names = "default"; 1073 pinctrl-0 = <&qup_uart6_default>; 1074 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1075 status = "disabled"; 1076 }; 1077 1078 i2c7: i2c@89c000 { 1079 compatible = "qcom,geni-i2c"; 1080 reg = <0 0x0089c000 0 0x4000>; 1081 clock-names = "se"; 1082 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1083 pinctrl-names = "default"; 1084 pinctrl-0 = <&qup_i2c7_default>; 1085 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1086 #address-cells = <1>; 1087 #size-cells = <0>; 1088 status = "disabled"; 1089 }; 1090 1091 spi7: spi@89c000 { 1092 compatible = "qcom,geni-spi"; 1093 reg = <0 0x0089c000 0 0x4000>; 1094 clock-names = "se"; 1095 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1096 pinctrl-names = "default"; 1097 pinctrl-0 = <&qup_spi7_default>; 1098 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1099 #address-cells = <1>; 1100 #size-cells = <0>; 1101 status = "disabled"; 1102 }; 1103 1104 uart7: serial@89c000 { 1105 compatible = "qcom,geni-uart"; 1106 reg = <0 0x0089c000 0 0x4000>; 1107 clock-names = "se"; 1108 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1109 pinctrl-names = "default"; 1110 pinctrl-0 = <&qup_uart7_default>; 1111 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1112 status = "disabled"; 1113 }; 1114 }; 1115 1116 qupv3_id_1: geniqup@ac0000 { 1117 compatible = "qcom,geni-se-qup"; 1118 reg = <0 0x00ac0000 0 0x6000>; 1119 clock-names = "m-ahb", "s-ahb"; 1120 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1121 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1122 #address-cells = <2>; 1123 #size-cells = <2>; 1124 ranges; 1125 status = "disabled"; 1126 1127 i2c8: i2c@a80000 { 1128 compatible = "qcom,geni-i2c"; 1129 reg = <0 0x00a80000 0 0x4000>; 1130 clock-names = "se"; 1131 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1132 pinctrl-names = "default"; 1133 pinctrl-0 = <&qup_i2c8_default>; 1134 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1135 #address-cells = <1>; 1136 #size-cells = <0>; 1137 status = "disabled"; 1138 }; 1139 1140 spi8: spi@a80000 { 1141 compatible = "qcom,geni-spi"; 1142 reg = <0 0x00a80000 0 0x4000>; 1143 clock-names = "se"; 1144 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1145 pinctrl-names = "default"; 1146 pinctrl-0 = <&qup_spi8_default>; 1147 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1148 #address-cells = <1>; 1149 #size-cells = <0>; 1150 status = "disabled"; 1151 }; 1152 1153 uart8: serial@a80000 { 1154 compatible = "qcom,geni-uart"; 1155 reg = <0 0x00a80000 0 0x4000>; 1156 clock-names = "se"; 1157 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1158 pinctrl-names = "default"; 1159 pinctrl-0 = <&qup_uart8_default>; 1160 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1161 status = "disabled"; 1162 }; 1163 1164 i2c9: i2c@a84000 { 1165 compatible = "qcom,geni-i2c"; 1166 reg = <0 0x00a84000 0 0x4000>; 1167 clock-names = "se"; 1168 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1169 pinctrl-names = "default"; 1170 pinctrl-0 = <&qup_i2c9_default>; 1171 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1172 #address-cells = <1>; 1173 #size-cells = <0>; 1174 status = "disabled"; 1175 }; 1176 1177 spi9: spi@a84000 { 1178 compatible = "qcom,geni-spi"; 1179 reg = <0 0x00a84000 0 0x4000>; 1180 clock-names = "se"; 1181 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1182 pinctrl-names = "default"; 1183 pinctrl-0 = <&qup_spi9_default>; 1184 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1185 #address-cells = <1>; 1186 #size-cells = <0>; 1187 status = "disabled"; 1188 }; 1189 1190 uart9: serial@a84000 { 1191 compatible = "qcom,geni-debug-uart"; 1192 reg = <0 0x00a84000 0 0x4000>; 1193 clock-names = "se"; 1194 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1195 pinctrl-names = "default"; 1196 pinctrl-0 = <&qup_uart9_default>; 1197 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1198 status = "disabled"; 1199 }; 1200 1201 i2c10: i2c@a88000 { 1202 compatible = "qcom,geni-i2c"; 1203 reg = <0 0x00a88000 0 0x4000>; 1204 clock-names = "se"; 1205 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1206 pinctrl-names = "default"; 1207 pinctrl-0 = <&qup_i2c10_default>; 1208 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1209 #address-cells = <1>; 1210 #size-cells = <0>; 1211 status = "disabled"; 1212 }; 1213 1214 spi10: spi@a88000 { 1215 compatible = "qcom,geni-spi"; 1216 reg = <0 0x00a88000 0 0x4000>; 1217 clock-names = "se"; 1218 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1219 pinctrl-names = "default"; 1220 pinctrl-0 = <&qup_spi10_default>; 1221 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1222 #address-cells = <1>; 1223 #size-cells = <0>; 1224 status = "disabled"; 1225 }; 1226 1227 uart10: serial@a88000 { 1228 compatible = "qcom,geni-uart"; 1229 reg = <0 0x00a88000 0 0x4000>; 1230 clock-names = "se"; 1231 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1232 pinctrl-names = "default"; 1233 pinctrl-0 = <&qup_uart10_default>; 1234 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1235 status = "disabled"; 1236 }; 1237 1238 i2c11: i2c@a8c000 { 1239 compatible = "qcom,geni-i2c"; 1240 reg = <0 0x00a8c000 0 0x4000>; 1241 clock-names = "se"; 1242 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1243 pinctrl-names = "default"; 1244 pinctrl-0 = <&qup_i2c11_default>; 1245 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1246 #address-cells = <1>; 1247 #size-cells = <0>; 1248 status = "disabled"; 1249 }; 1250 1251 spi11: spi@a8c000 { 1252 compatible = "qcom,geni-spi"; 1253 reg = <0 0x00a8c000 0 0x4000>; 1254 clock-names = "se"; 1255 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1256 pinctrl-names = "default"; 1257 pinctrl-0 = <&qup_spi11_default>; 1258 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1259 #address-cells = <1>; 1260 #size-cells = <0>; 1261 status = "disabled"; 1262 }; 1263 1264 uart11: serial@a8c000 { 1265 compatible = "qcom,geni-uart"; 1266 reg = <0 0x00a8c000 0 0x4000>; 1267 clock-names = "se"; 1268 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1269 pinctrl-names = "default"; 1270 pinctrl-0 = <&qup_uart11_default>; 1271 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1272 status = "disabled"; 1273 }; 1274 1275 i2c12: i2c@a90000 { 1276 compatible = "qcom,geni-i2c"; 1277 reg = <0 0x00a90000 0 0x4000>; 1278 clock-names = "se"; 1279 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1280 pinctrl-names = "default"; 1281 pinctrl-0 = <&qup_i2c12_default>; 1282 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1283 #address-cells = <1>; 1284 #size-cells = <0>; 1285 status = "disabled"; 1286 }; 1287 1288 spi12: spi@a90000 { 1289 compatible = "qcom,geni-spi"; 1290 reg = <0 0x00a90000 0 0x4000>; 1291 clock-names = "se"; 1292 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1293 pinctrl-names = "default"; 1294 pinctrl-0 = <&qup_spi12_default>; 1295 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1296 #address-cells = <1>; 1297 #size-cells = <0>; 1298 status = "disabled"; 1299 }; 1300 1301 uart12: serial@a90000 { 1302 compatible = "qcom,geni-uart"; 1303 reg = <0 0x00a90000 0 0x4000>; 1304 clock-names = "se"; 1305 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1306 pinctrl-names = "default"; 1307 pinctrl-0 = <&qup_uart12_default>; 1308 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1309 status = "disabled"; 1310 }; 1311 1312 i2c13: i2c@a94000 { 1313 compatible = "qcom,geni-i2c"; 1314 reg = <0 0x00a94000 0 0x4000>; 1315 clock-names = "se"; 1316 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1317 pinctrl-names = "default"; 1318 pinctrl-0 = <&qup_i2c13_default>; 1319 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1320 #address-cells = <1>; 1321 #size-cells = <0>; 1322 status = "disabled"; 1323 }; 1324 1325 spi13: spi@a94000 { 1326 compatible = "qcom,geni-spi"; 1327 reg = <0 0x00a94000 0 0x4000>; 1328 clock-names = "se"; 1329 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1330 pinctrl-names = "default"; 1331 pinctrl-0 = <&qup_spi13_default>; 1332 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1333 #address-cells = <1>; 1334 #size-cells = <0>; 1335 status = "disabled"; 1336 }; 1337 1338 uart13: serial@a94000 { 1339 compatible = "qcom,geni-uart"; 1340 reg = <0 0x00a94000 0 0x4000>; 1341 clock-names = "se"; 1342 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1343 pinctrl-names = "default"; 1344 pinctrl-0 = <&qup_uart13_default>; 1345 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1346 status = "disabled"; 1347 }; 1348 1349 i2c14: i2c@a98000 { 1350 compatible = "qcom,geni-i2c"; 1351 reg = <0 0x00a98000 0 0x4000>; 1352 clock-names = "se"; 1353 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1354 pinctrl-names = "default"; 1355 pinctrl-0 = <&qup_i2c14_default>; 1356 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 1357 #address-cells = <1>; 1358 #size-cells = <0>; 1359 status = "disabled"; 1360 }; 1361 1362 spi14: spi@a98000 { 1363 compatible = "qcom,geni-spi"; 1364 reg = <0 0x00a98000 0 0x4000>; 1365 clock-names = "se"; 1366 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1367 pinctrl-names = "default"; 1368 pinctrl-0 = <&qup_spi14_default>; 1369 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 1370 #address-cells = <1>; 1371 #size-cells = <0>; 1372 status = "disabled"; 1373 }; 1374 1375 uart14: serial@a98000 { 1376 compatible = "qcom,geni-uart"; 1377 reg = <0 0x00a98000 0 0x4000>; 1378 clock-names = "se"; 1379 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1380 pinctrl-names = "default"; 1381 pinctrl-0 = <&qup_uart14_default>; 1382 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 1383 status = "disabled"; 1384 }; 1385 1386 i2c15: i2c@a9c000 { 1387 compatible = "qcom,geni-i2c"; 1388 reg = <0 0x00a9c000 0 0x4000>; 1389 clock-names = "se"; 1390 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1391 pinctrl-names = "default"; 1392 pinctrl-0 = <&qup_i2c15_default>; 1393 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1394 #address-cells = <1>; 1395 #size-cells = <0>; 1396 status = "disabled"; 1397 }; 1398 1399 spi15: spi@a9c000 { 1400 compatible = "qcom,geni-spi"; 1401 reg = <0 0x00a9c000 0 0x4000>; 1402 clock-names = "se"; 1403 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1404 pinctrl-names = "default"; 1405 pinctrl-0 = <&qup_spi15_default>; 1406 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1407 #address-cells = <1>; 1408 #size-cells = <0>; 1409 status = "disabled"; 1410 }; 1411 1412 uart15: serial@a9c000 { 1413 compatible = "qcom,geni-uart"; 1414 reg = <0 0x00a9c000 0 0x4000>; 1415 clock-names = "se"; 1416 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1417 pinctrl-names = "default"; 1418 pinctrl-0 = <&qup_uart15_default>; 1419 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1420 status = "disabled"; 1421 }; 1422 }; 1423 1424 system-cache-controller@1100000 { 1425 compatible = "qcom,sdm845-llcc"; 1426 reg = <0 0x01100000 0 0x200000>, <0 0x01300000 0 0x50000>; 1427 reg-names = "llcc_base", "llcc_broadcast_base"; 1428 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 1429 }; 1430 1431 pcie0: pci@1c00000 { 1432 compatible = "qcom,pcie-sdm845", "snps,dw-pcie"; 1433 reg = <0 0x01c00000 0 0x2000>, 1434 <0 0x60000000 0 0xf1d>, 1435 <0 0x60000f20 0 0xa8>, 1436 <0 0x60100000 0 0x100000>; 1437 reg-names = "parf", "dbi", "elbi", "config"; 1438 device_type = "pci"; 1439 linux,pci-domain = <0>; 1440 bus-range = <0x00 0xff>; 1441 num-lanes = <1>; 1442 1443 #address-cells = <3>; 1444 #size-cells = <2>; 1445 1446 ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>, 1447 <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0xd00000>; 1448 1449 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 1450 interrupt-names = "msi"; 1451 #interrupt-cells = <1>; 1452 interrupt-map-mask = <0 0 0 0x7>; 1453 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1454 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1455 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1456 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1457 1458 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1459 <&gcc GCC_PCIE_0_AUX_CLK>, 1460 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1461 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1462 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1463 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1464 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; 1465 clock-names = "pipe", 1466 "aux", 1467 "cfg", 1468 "bus_master", 1469 "bus_slave", 1470 "slave_q2a", 1471 "tbu"; 1472 1473 iommus = <&apps_smmu 0x1c10 0xf>; 1474 iommu-map = <0x0 &apps_smmu 0x1c10 0x1>, 1475 <0x100 &apps_smmu 0x1c11 0x1>, 1476 <0x200 &apps_smmu 0x1c12 0x1>, 1477 <0x300 &apps_smmu 0x1c13 0x1>, 1478 <0x400 &apps_smmu 0x1c14 0x1>, 1479 <0x500 &apps_smmu 0x1c15 0x1>, 1480 <0x600 &apps_smmu 0x1c16 0x1>, 1481 <0x700 &apps_smmu 0x1c17 0x1>, 1482 <0x800 &apps_smmu 0x1c18 0x1>, 1483 <0x900 &apps_smmu 0x1c19 0x1>, 1484 <0xa00 &apps_smmu 0x1c1a 0x1>, 1485 <0xb00 &apps_smmu 0x1c1b 0x1>, 1486 <0xc00 &apps_smmu 0x1c1c 0x1>, 1487 <0xd00 &apps_smmu 0x1c1d 0x1>, 1488 <0xe00 &apps_smmu 0x1c1e 0x1>, 1489 <0xf00 &apps_smmu 0x1c1f 0x1>; 1490 1491 resets = <&gcc GCC_PCIE_0_BCR>; 1492 reset-names = "pci"; 1493 1494 power-domains = <&gcc PCIE_0_GDSC>; 1495 1496 phys = <&pcie0_lane>; 1497 phy-names = "pciephy"; 1498 1499 status = "disabled"; 1500 }; 1501 1502 pcie0_phy: phy@1c06000 { 1503 compatible = "qcom,sdm845-qmp-pcie-phy"; 1504 reg = <0 0x01c06000 0 0x18c>; 1505 #address-cells = <2>; 1506 #size-cells = <2>; 1507 ranges; 1508 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1509 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1510 <&gcc GCC_PCIE_0_CLKREF_CLK>, 1511 <&gcc GCC_PCIE_PHY_REFGEN_CLK>; 1512 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 1513 1514 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1515 reset-names = "phy"; 1516 1517 assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>; 1518 assigned-clock-rates = <100000000>; 1519 1520 status = "disabled"; 1521 1522 pcie0_lane: lanes@1c06200 { 1523 reg = <0 0x01c06200 0 0x128>, 1524 <0 0x01c06400 0 0x1fc>, 1525 <0 0x01c06800 0 0x218>, 1526 <0 0x01c06600 0 0x70>; 1527 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 1528 clock-names = "pipe0"; 1529 1530 #phy-cells = <0>; 1531 clock-output-names = "pcie_0_pipe_clk"; 1532 }; 1533 }; 1534 1535 pcie1: pci@1c08000 { 1536 compatible = "qcom,pcie-sdm845", "snps,dw-pcie"; 1537 reg = <0 0x01c08000 0 0x2000>, 1538 <0 0x40000000 0 0xf1d>, 1539 <0 0x40000f20 0 0xa8>, 1540 <0 0x40100000 0 0x100000>; 1541 reg-names = "parf", "dbi", "elbi", "config"; 1542 device_type = "pci"; 1543 linux,pci-domain = <1>; 1544 bus-range = <0x00 0xff>; 1545 num-lanes = <1>; 1546 1547 #address-cells = <3>; 1548 #size-cells = <2>; 1549 1550 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, 1551 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1552 1553 interrupts = <GIC_SPI 307 IRQ_TYPE_EDGE_RISING>; 1554 interrupt-names = "msi"; 1555 #interrupt-cells = <1>; 1556 interrupt-map-mask = <0 0 0 0x7>; 1557 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1558 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1559 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1560 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1561 1562 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1563 <&gcc GCC_PCIE_1_AUX_CLK>, 1564 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1565 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1566 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1567 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1568 <&gcc GCC_PCIE_1_CLKREF_CLK>, 1569 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; 1570 clock-names = "pipe", 1571 "aux", 1572 "cfg", 1573 "bus_master", 1574 "bus_slave", 1575 "slave_q2a", 1576 "ref", 1577 "tbu"; 1578 1579 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 1580 assigned-clock-rates = <19200000>; 1581 1582 iommus = <&apps_smmu 0x1c00 0xf>; 1583 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, 1584 <0x100 &apps_smmu 0x1c01 0x1>, 1585 <0x200 &apps_smmu 0x1c02 0x1>, 1586 <0x300 &apps_smmu 0x1c03 0x1>, 1587 <0x400 &apps_smmu 0x1c04 0x1>, 1588 <0x500 &apps_smmu 0x1c05 0x1>, 1589 <0x600 &apps_smmu 0x1c06 0x1>, 1590 <0x700 &apps_smmu 0x1c07 0x1>, 1591 <0x800 &apps_smmu 0x1c08 0x1>, 1592 <0x900 &apps_smmu 0x1c09 0x1>, 1593 <0xa00 &apps_smmu 0x1c0a 0x1>, 1594 <0xb00 &apps_smmu 0x1c0b 0x1>, 1595 <0xc00 &apps_smmu 0x1c0c 0x1>, 1596 <0xd00 &apps_smmu 0x1c0d 0x1>, 1597 <0xe00 &apps_smmu 0x1c0e 0x1>, 1598 <0xf00 &apps_smmu 0x1c0f 0x1>; 1599 1600 resets = <&gcc GCC_PCIE_1_BCR>; 1601 reset-names = "pci"; 1602 1603 power-domains = <&gcc PCIE_1_GDSC>; 1604 1605 phys = <&pcie1_lane>; 1606 phy-names = "pciephy"; 1607 1608 status = "disabled"; 1609 }; 1610 1611 pcie1_phy: phy@1c0a000 { 1612 compatible = "qcom,sdm845-qhp-pcie-phy"; 1613 reg = <0 0x01c0a000 0 0x800>; 1614 #address-cells = <2>; 1615 #size-cells = <2>; 1616 ranges; 1617 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1618 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1619 <&gcc GCC_PCIE_1_CLKREF_CLK>, 1620 <&gcc GCC_PCIE_PHY_REFGEN_CLK>; 1621 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 1622 1623 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 1624 reset-names = "phy"; 1625 1626 assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>; 1627 assigned-clock-rates = <100000000>; 1628 1629 status = "disabled"; 1630 1631 pcie1_lane: lanes@1c06200 { 1632 reg = <0 0x01c0a800 0 0x800>, 1633 <0 0x01c0a800 0 0x800>, 1634 <0 0x01c0b800 0 0x400>; 1635 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 1636 clock-names = "pipe0"; 1637 1638 #phy-cells = <0>; 1639 clock-output-names = "pcie_1_pipe_clk"; 1640 }; 1641 }; 1642 1643 mem_noc: interconnect@1380000 { 1644 compatible = "qcom,sdm845-mem-noc"; 1645 reg = <0 0x01380000 0 0x27200>; 1646 #interconnect-cells = <1>; 1647 qcom,bcm-voters = <&apps_bcm_voter>; 1648 }; 1649 1650 dc_noc: interconnect@14e0000 { 1651 compatible = "qcom,sdm845-dc-noc"; 1652 reg = <0 0x014e0000 0 0x400>; 1653 #interconnect-cells = <1>; 1654 qcom,bcm-voters = <&apps_bcm_voter>; 1655 }; 1656 1657 config_noc: interconnect@1500000 { 1658 compatible = "qcom,sdm845-config-noc"; 1659 reg = <0 0x01500000 0 0x5080>; 1660 #interconnect-cells = <1>; 1661 qcom,bcm-voters = <&apps_bcm_voter>; 1662 }; 1663 1664 system_noc: interconnect@1620000 { 1665 compatible = "qcom,sdm845-system-noc"; 1666 reg = <0 0x01620000 0 0x18080>; 1667 #interconnect-cells = <1>; 1668 qcom,bcm-voters = <&apps_bcm_voter>; 1669 }; 1670 1671 aggre1_noc: interconnect@16e0000 { 1672 compatible = "qcom,sdm845-aggre1-noc"; 1673 reg = <0 0x016e0000 0 0x15080>; 1674 #interconnect-cells = <1>; 1675 qcom,bcm-voters = <&apps_bcm_voter>; 1676 }; 1677 1678 aggre2_noc: interconnect@1700000 { 1679 compatible = "qcom,sdm845-aggre2-noc"; 1680 reg = <0 0x01700000 0 0x1f300>; 1681 #interconnect-cells = <1>; 1682 qcom,bcm-voters = <&apps_bcm_voter>; 1683 }; 1684 1685 mmss_noc: interconnect@1740000 { 1686 compatible = "qcom,sdm845-mmss-noc"; 1687 reg = <0 0x01740000 0 0x1c100>; 1688 #interconnect-cells = <1>; 1689 qcom,bcm-voters = <&apps_bcm_voter>; 1690 }; 1691 1692 ufs_mem_hc: ufshc@1d84000 { 1693 compatible = "qcom,sdm845-ufshc", "qcom,ufshc", 1694 "jedec,ufs-2.0"; 1695 reg = <0 0x01d84000 0 0x2500>; 1696 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 1697 phys = <&ufs_mem_phy_lanes>; 1698 phy-names = "ufsphy"; 1699 lanes-per-direction = <2>; 1700 power-domains = <&gcc UFS_PHY_GDSC>; 1701 #reset-cells = <1>; 1702 resets = <&gcc GCC_UFS_PHY_BCR>; 1703 reset-names = "rst"; 1704 1705 iommus = <&apps_smmu 0x100 0xf>; 1706 1707 clock-names = 1708 "core_clk", 1709 "bus_aggr_clk", 1710 "iface_clk", 1711 "core_clk_unipro", 1712 "ref_clk", 1713 "tx_lane0_sync_clk", 1714 "rx_lane0_sync_clk", 1715 "rx_lane1_sync_clk"; 1716 clocks = 1717 <&gcc GCC_UFS_PHY_AXI_CLK>, 1718 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1719 <&gcc GCC_UFS_PHY_AHB_CLK>, 1720 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 1721 <&rpmhcc RPMH_CXO_CLK>, 1722 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 1723 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 1724 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 1725 freq-table-hz = 1726 <50000000 200000000>, 1727 <0 0>, 1728 <0 0>, 1729 <37500000 150000000>, 1730 <0 0>, 1731 <0 0>, 1732 <0 0>, 1733 <0 0>; 1734 1735 status = "disabled"; 1736 }; 1737 1738 ufs_mem_phy: phy@1d87000 { 1739 compatible = "qcom,sdm845-qmp-ufs-phy"; 1740 reg = <0 0x01d87000 0 0x18c>; 1741 #address-cells = <2>; 1742 #size-cells = <2>; 1743 ranges; 1744 clock-names = "ref", 1745 "ref_aux"; 1746 clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, 1747 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 1748 1749 resets = <&ufs_mem_hc 0>; 1750 reset-names = "ufsphy"; 1751 status = "disabled"; 1752 1753 ufs_mem_phy_lanes: lanes@1d87400 { 1754 reg = <0 0x01d87400 0 0x108>, 1755 <0 0x01d87600 0 0x1e0>, 1756 <0 0x01d87c00 0 0x1dc>, 1757 <0 0x01d87800 0 0x108>, 1758 <0 0x01d87a00 0 0x1e0>; 1759 #phy-cells = <0>; 1760 }; 1761 }; 1762 1763 ipa: ipa@1e40000 { 1764 compatible = "qcom,sdm845-ipa"; 1765 1766 iommus = <&apps_smmu 0x720 0x3>; 1767 reg = <0 0x1e40000 0 0x7000>, 1768 <0 0x1e47000 0 0x2000>, 1769 <0 0x1e04000 0 0x2c000>; 1770 reg-names = "ipa-reg", 1771 "ipa-shared", 1772 "gsi"; 1773 1774 interrupts-extended = <&intc 0 311 IRQ_TYPE_EDGE_RISING>, 1775 <&intc 0 432 IRQ_TYPE_LEVEL_HIGH>, 1776 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1777 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 1778 interrupt-names = "ipa", 1779 "gsi", 1780 "ipa-clock-query", 1781 "ipa-setup-ready"; 1782 1783 clocks = <&rpmhcc RPMH_IPA_CLK>; 1784 clock-names = "core"; 1785 1786 interconnects = <&aggre2_noc MASTER_IPA &mem_noc SLAVE_EBI1>, 1787 <&aggre2_noc MASTER_IPA &system_noc SLAVE_IMEM>, 1788 <&gladiator_noc MASTER_APPSS_PROC &config_noc SLAVE_IPA_CFG>; 1789 interconnect-names = "memory", 1790 "imem", 1791 "config"; 1792 1793 qcom,smem-states = <&ipa_smp2p_out 0>, 1794 <&ipa_smp2p_out 1>; 1795 qcom,smem-state-names = "ipa-clock-enabled-valid", 1796 "ipa-clock-enabled"; 1797 1798 modem-remoteproc = <&mss_pil>; 1799 1800 status = "disabled"; 1801 }; 1802 1803 tcsr_mutex_regs: syscon@1f40000 { 1804 compatible = "syscon"; 1805 reg = <0 0x01f40000 0 0x40000>; 1806 }; 1807 1808 tlmm: pinctrl@3400000 { 1809 compatible = "qcom,sdm845-pinctrl"; 1810 reg = <0 0x03400000 0 0xc00000>; 1811 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1812 gpio-controller; 1813 #gpio-cells = <2>; 1814 interrupt-controller; 1815 #interrupt-cells = <2>; 1816 gpio-ranges = <&tlmm 0 0 150>; 1817 wakeup-parent = <&pdc_intc>; 1818 1819 cci0_default: cci0-default { 1820 /* SDA, SCL */ 1821 pins = "gpio17", "gpio18"; 1822 function = "cci_i2c"; 1823 1824 bias-pull-up; 1825 drive-strength = <2>; /* 2 mA */ 1826 }; 1827 1828 cci0_sleep: cci0-sleep { 1829 /* SDA, SCL */ 1830 pins = "gpio17", "gpio18"; 1831 function = "cci_i2c"; 1832 1833 drive-strength = <2>; /* 2 mA */ 1834 bias-pull-down; 1835 }; 1836 1837 cci1_default: cci1-default { 1838 /* SDA, SCL */ 1839 pins = "gpio19", "gpio20"; 1840 function = "cci_i2c"; 1841 1842 bias-pull-up; 1843 drive-strength = <2>; /* 2 mA */ 1844 }; 1845 1846 cci1_sleep: cci1-sleep { 1847 /* SDA, SCL */ 1848 pins = "gpio19", "gpio20"; 1849 function = "cci_i2c"; 1850 1851 drive-strength = <2>; /* 2 mA */ 1852 bias-pull-down; 1853 }; 1854 1855 qspi_clk: qspi-clk { 1856 pinmux { 1857 pins = "gpio95"; 1858 function = "qspi_clk"; 1859 }; 1860 }; 1861 1862 qspi_cs0: qspi-cs0 { 1863 pinmux { 1864 pins = "gpio90"; 1865 function = "qspi_cs"; 1866 }; 1867 }; 1868 1869 qspi_cs1: qspi-cs1 { 1870 pinmux { 1871 pins = "gpio89"; 1872 function = "qspi_cs"; 1873 }; 1874 }; 1875 1876 qspi_data01: qspi-data01 { 1877 pinmux-data { 1878 pins = "gpio91", "gpio92"; 1879 function = "qspi_data"; 1880 }; 1881 }; 1882 1883 qspi_data12: qspi-data12 { 1884 pinmux-data { 1885 pins = "gpio93", "gpio94"; 1886 function = "qspi_data"; 1887 }; 1888 }; 1889 1890 qup_i2c0_default: qup-i2c0-default { 1891 pinmux { 1892 pins = "gpio0", "gpio1"; 1893 function = "qup0"; 1894 }; 1895 }; 1896 1897 qup_i2c1_default: qup-i2c1-default { 1898 pinmux { 1899 pins = "gpio17", "gpio18"; 1900 function = "qup1"; 1901 }; 1902 }; 1903 1904 qup_i2c2_default: qup-i2c2-default { 1905 pinmux { 1906 pins = "gpio27", "gpio28"; 1907 function = "qup2"; 1908 }; 1909 }; 1910 1911 qup_i2c3_default: qup-i2c3-default { 1912 pinmux { 1913 pins = "gpio41", "gpio42"; 1914 function = "qup3"; 1915 }; 1916 }; 1917 1918 qup_i2c4_default: qup-i2c4-default { 1919 pinmux { 1920 pins = "gpio89", "gpio90"; 1921 function = "qup4"; 1922 }; 1923 }; 1924 1925 qup_i2c5_default: qup-i2c5-default { 1926 pinmux { 1927 pins = "gpio85", "gpio86"; 1928 function = "qup5"; 1929 }; 1930 }; 1931 1932 qup_i2c6_default: qup-i2c6-default { 1933 pinmux { 1934 pins = "gpio45", "gpio46"; 1935 function = "qup6"; 1936 }; 1937 }; 1938 1939 qup_i2c7_default: qup-i2c7-default { 1940 pinmux { 1941 pins = "gpio93", "gpio94"; 1942 function = "qup7"; 1943 }; 1944 }; 1945 1946 qup_i2c8_default: qup-i2c8-default { 1947 pinmux { 1948 pins = "gpio65", "gpio66"; 1949 function = "qup8"; 1950 }; 1951 }; 1952 1953 qup_i2c9_default: qup-i2c9-default { 1954 pinmux { 1955 pins = "gpio6", "gpio7"; 1956 function = "qup9"; 1957 }; 1958 }; 1959 1960 qup_i2c10_default: qup-i2c10-default { 1961 pinmux { 1962 pins = "gpio55", "gpio56"; 1963 function = "qup10"; 1964 }; 1965 }; 1966 1967 qup_i2c11_default: qup-i2c11-default { 1968 pinmux { 1969 pins = "gpio31", "gpio32"; 1970 function = "qup11"; 1971 }; 1972 }; 1973 1974 qup_i2c12_default: qup-i2c12-default { 1975 pinmux { 1976 pins = "gpio49", "gpio50"; 1977 function = "qup12"; 1978 }; 1979 }; 1980 1981 qup_i2c13_default: qup-i2c13-default { 1982 pinmux { 1983 pins = "gpio105", "gpio106"; 1984 function = "qup13"; 1985 }; 1986 }; 1987 1988 qup_i2c14_default: qup-i2c14-default { 1989 pinmux { 1990 pins = "gpio33", "gpio34"; 1991 function = "qup14"; 1992 }; 1993 }; 1994 1995 qup_i2c15_default: qup-i2c15-default { 1996 pinmux { 1997 pins = "gpio81", "gpio82"; 1998 function = "qup15"; 1999 }; 2000 }; 2001 2002 qup_spi0_default: qup-spi0-default { 2003 pinmux { 2004 pins = "gpio0", "gpio1", 2005 "gpio2", "gpio3"; 2006 function = "qup0"; 2007 }; 2008 }; 2009 2010 qup_spi1_default: qup-spi1-default { 2011 pinmux { 2012 pins = "gpio17", "gpio18", 2013 "gpio19", "gpio20"; 2014 function = "qup1"; 2015 }; 2016 }; 2017 2018 qup_spi2_default: qup-spi2-default { 2019 pinmux { 2020 pins = "gpio27", "gpio28", 2021 "gpio29", "gpio30"; 2022 function = "qup2"; 2023 }; 2024 }; 2025 2026 qup_spi3_default: qup-spi3-default { 2027 pinmux { 2028 pins = "gpio41", "gpio42", 2029 "gpio43", "gpio44"; 2030 function = "qup3"; 2031 }; 2032 }; 2033 2034 qup_spi4_default: qup-spi4-default { 2035 pinmux { 2036 pins = "gpio89", "gpio90", 2037 "gpio91", "gpio92"; 2038 function = "qup4"; 2039 }; 2040 }; 2041 2042 qup_spi5_default: qup-spi5-default { 2043 pinmux { 2044 pins = "gpio85", "gpio86", 2045 "gpio87", "gpio88"; 2046 function = "qup5"; 2047 }; 2048 }; 2049 2050 qup_spi6_default: qup-spi6-default { 2051 pinmux { 2052 pins = "gpio45", "gpio46", 2053 "gpio47", "gpio48"; 2054 function = "qup6"; 2055 }; 2056 }; 2057 2058 qup_spi7_default: qup-spi7-default { 2059 pinmux { 2060 pins = "gpio93", "gpio94", 2061 "gpio95", "gpio96"; 2062 function = "qup7"; 2063 }; 2064 }; 2065 2066 qup_spi8_default: qup-spi8-default { 2067 pinmux { 2068 pins = "gpio65", "gpio66", 2069 "gpio67", "gpio68"; 2070 function = "qup8"; 2071 }; 2072 }; 2073 2074 qup_spi9_default: qup-spi9-default { 2075 pinmux { 2076 pins = "gpio6", "gpio7", 2077 "gpio4", "gpio5"; 2078 function = "qup9"; 2079 }; 2080 }; 2081 2082 qup_spi10_default: qup-spi10-default { 2083 pinmux { 2084 pins = "gpio55", "gpio56", 2085 "gpio53", "gpio54"; 2086 function = "qup10"; 2087 }; 2088 }; 2089 2090 qup_spi11_default: qup-spi11-default { 2091 pinmux { 2092 pins = "gpio31", "gpio32", 2093 "gpio33", "gpio34"; 2094 function = "qup11"; 2095 }; 2096 }; 2097 2098 qup_spi12_default: qup-spi12-default { 2099 pinmux { 2100 pins = "gpio49", "gpio50", 2101 "gpio51", "gpio52"; 2102 function = "qup12"; 2103 }; 2104 }; 2105 2106 qup_spi13_default: qup-spi13-default { 2107 pinmux { 2108 pins = "gpio105", "gpio106", 2109 "gpio107", "gpio108"; 2110 function = "qup13"; 2111 }; 2112 }; 2113 2114 qup_spi14_default: qup-spi14-default { 2115 pinmux { 2116 pins = "gpio33", "gpio34", 2117 "gpio31", "gpio32"; 2118 function = "qup14"; 2119 }; 2120 }; 2121 2122 qup_spi15_default: qup-spi15-default { 2123 pinmux { 2124 pins = "gpio81", "gpio82", 2125 "gpio83", "gpio84"; 2126 function = "qup15"; 2127 }; 2128 }; 2129 2130 qup_uart0_default: qup-uart0-default { 2131 pinmux { 2132 pins = "gpio2", "gpio3"; 2133 function = "qup0"; 2134 }; 2135 }; 2136 2137 qup_uart1_default: qup-uart1-default { 2138 pinmux { 2139 pins = "gpio19", "gpio20"; 2140 function = "qup1"; 2141 }; 2142 }; 2143 2144 qup_uart2_default: qup-uart2-default { 2145 pinmux { 2146 pins = "gpio29", "gpio30"; 2147 function = "qup2"; 2148 }; 2149 }; 2150 2151 qup_uart3_default: qup-uart3-default { 2152 pinmux { 2153 pins = "gpio43", "gpio44"; 2154 function = "qup3"; 2155 }; 2156 }; 2157 2158 qup_uart4_default: qup-uart4-default { 2159 pinmux { 2160 pins = "gpio91", "gpio92"; 2161 function = "qup4"; 2162 }; 2163 }; 2164 2165 qup_uart5_default: qup-uart5-default { 2166 pinmux { 2167 pins = "gpio87", "gpio88"; 2168 function = "qup5"; 2169 }; 2170 }; 2171 2172 qup_uart6_default: qup-uart6-default { 2173 pinmux { 2174 pins = "gpio47", "gpio48"; 2175 function = "qup6"; 2176 }; 2177 }; 2178 2179 qup_uart7_default: qup-uart7-default { 2180 pinmux { 2181 pins = "gpio95", "gpio96"; 2182 function = "qup7"; 2183 }; 2184 }; 2185 2186 qup_uart8_default: qup-uart8-default { 2187 pinmux { 2188 pins = "gpio67", "gpio68"; 2189 function = "qup8"; 2190 }; 2191 }; 2192 2193 qup_uart9_default: qup-uart9-default { 2194 pinmux { 2195 pins = "gpio4", "gpio5"; 2196 function = "qup9"; 2197 }; 2198 }; 2199 2200 qup_uart10_default: qup-uart10-default { 2201 pinmux { 2202 pins = "gpio53", "gpio54"; 2203 function = "qup10"; 2204 }; 2205 }; 2206 2207 qup_uart11_default: qup-uart11-default { 2208 pinmux { 2209 pins = "gpio33", "gpio34"; 2210 function = "qup11"; 2211 }; 2212 }; 2213 2214 qup_uart12_default: qup-uart12-default { 2215 pinmux { 2216 pins = "gpio51", "gpio52"; 2217 function = "qup12"; 2218 }; 2219 }; 2220 2221 qup_uart13_default: qup-uart13-default { 2222 pinmux { 2223 pins = "gpio107", "gpio108"; 2224 function = "qup13"; 2225 }; 2226 }; 2227 2228 qup_uart14_default: qup-uart14-default { 2229 pinmux { 2230 pins = "gpio31", "gpio32"; 2231 function = "qup14"; 2232 }; 2233 }; 2234 2235 qup_uart15_default: qup-uart15-default { 2236 pinmux { 2237 pins = "gpio83", "gpio84"; 2238 function = "qup15"; 2239 }; 2240 }; 2241 2242 quat_mi2s_sleep: quat_mi2s_sleep { 2243 mux { 2244 pins = "gpio58", "gpio59"; 2245 function = "gpio"; 2246 }; 2247 2248 config { 2249 pins = "gpio58", "gpio59"; 2250 drive-strength = <2>; 2251 bias-pull-down; 2252 input-enable; 2253 }; 2254 }; 2255 2256 quat_mi2s_active: quat_mi2s_active { 2257 mux { 2258 pins = "gpio58", "gpio59"; 2259 function = "qua_mi2s"; 2260 }; 2261 2262 config { 2263 pins = "gpio58", "gpio59"; 2264 drive-strength = <8>; 2265 bias-disable; 2266 output-high; 2267 }; 2268 }; 2269 2270 quat_mi2s_sd0_sleep: quat_mi2s_sd0_sleep { 2271 mux { 2272 pins = "gpio60"; 2273 function = "gpio"; 2274 }; 2275 2276 config { 2277 pins = "gpio60"; 2278 drive-strength = <2>; 2279 bias-pull-down; 2280 input-enable; 2281 }; 2282 }; 2283 2284 quat_mi2s_sd0_active: quat_mi2s_sd0_active { 2285 mux { 2286 pins = "gpio60"; 2287 function = "qua_mi2s"; 2288 }; 2289 2290 config { 2291 pins = "gpio60"; 2292 drive-strength = <8>; 2293 bias-disable; 2294 }; 2295 }; 2296 2297 quat_mi2s_sd1_sleep: quat_mi2s_sd1_sleep { 2298 mux { 2299 pins = "gpio61"; 2300 function = "gpio"; 2301 }; 2302 2303 config { 2304 pins = "gpio61"; 2305 drive-strength = <2>; 2306 bias-pull-down; 2307 input-enable; 2308 }; 2309 }; 2310 2311 quat_mi2s_sd1_active: quat_mi2s_sd1_active { 2312 mux { 2313 pins = "gpio61"; 2314 function = "qua_mi2s"; 2315 }; 2316 2317 config { 2318 pins = "gpio61"; 2319 drive-strength = <8>; 2320 bias-disable; 2321 }; 2322 }; 2323 2324 quat_mi2s_sd2_sleep: quat_mi2s_sd2_sleep { 2325 mux { 2326 pins = "gpio62"; 2327 function = "gpio"; 2328 }; 2329 2330 config { 2331 pins = "gpio62"; 2332 drive-strength = <2>; 2333 bias-pull-down; 2334 input-enable; 2335 }; 2336 }; 2337 2338 quat_mi2s_sd2_active: quat_mi2s_sd2_active { 2339 mux { 2340 pins = "gpio62"; 2341 function = "qua_mi2s"; 2342 }; 2343 2344 config { 2345 pins = "gpio62"; 2346 drive-strength = <8>; 2347 bias-disable; 2348 }; 2349 }; 2350 2351 quat_mi2s_sd3_sleep: quat_mi2s_sd3_sleep { 2352 mux { 2353 pins = "gpio63"; 2354 function = "gpio"; 2355 }; 2356 2357 config { 2358 pins = "gpio63"; 2359 drive-strength = <2>; 2360 bias-pull-down; 2361 input-enable; 2362 }; 2363 }; 2364 2365 quat_mi2s_sd3_active: quat_mi2s_sd3_active { 2366 mux { 2367 pins = "gpio63"; 2368 function = "qua_mi2s"; 2369 }; 2370 2371 config { 2372 pins = "gpio63"; 2373 drive-strength = <8>; 2374 bias-disable; 2375 }; 2376 }; 2377 }; 2378 2379 mss_pil: remoteproc@4080000 { 2380 compatible = "qcom,sdm845-mss-pil"; 2381 reg = <0 0x04080000 0 0x408>, <0 0x04180000 0 0x48>; 2382 reg-names = "qdsp6", "rmb"; 2383 2384 interrupts-extended = 2385 <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, 2386 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2387 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2388 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2389 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2390 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2391 interrupt-names = "wdog", "fatal", "ready", 2392 "handover", "stop-ack", 2393 "shutdown-ack"; 2394 2395 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 2396 <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>, 2397 <&gcc GCC_BOOT_ROM_AHB_CLK>, 2398 <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>, 2399 <&gcc GCC_MSS_SNOC_AXI_CLK>, 2400 <&gcc GCC_MSS_MFAB_AXIS_CLK>, 2401 <&gcc GCC_PRNG_AHB_CLK>, 2402 <&rpmhcc RPMH_CXO_CLK>; 2403 clock-names = "iface", "bus", "mem", "gpll0_mss", 2404 "snoc_axi", "mnoc_axi", "prng", "xo"; 2405 2406 qcom,smem-states = <&modem_smp2p_out 0>; 2407 qcom,smem-state-names = "stop"; 2408 2409 resets = <&aoss_reset AOSS_CC_MSS_RESTART>, 2410 <&pdc_reset PDC_MODEM_SYNC_RESET>; 2411 reset-names = "mss_restart", "pdc_reset"; 2412 2413 qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>; 2414 2415 power-domains = <&aoss_qmp 2>, 2416 <&rpmhpd SDM845_CX>, 2417 <&rpmhpd SDM845_MX>, 2418 <&rpmhpd SDM845_MSS>; 2419 power-domain-names = "load_state", "cx", "mx", "mss"; 2420 2421 mba { 2422 memory-region = <&mba_region>; 2423 }; 2424 2425 mpss { 2426 memory-region = <&mpss_region>; 2427 }; 2428 2429 glink-edge { 2430 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 2431 label = "modem"; 2432 qcom,remote-pid = <1>; 2433 mboxes = <&apss_shared 12>; 2434 }; 2435 }; 2436 2437 gpucc: clock-controller@5090000 { 2438 compatible = "qcom,sdm845-gpucc"; 2439 reg = <0 0x05090000 0 0x9000>; 2440 #clock-cells = <1>; 2441 #reset-cells = <1>; 2442 #power-domain-cells = <1>; 2443 clocks = <&rpmhcc RPMH_CXO_CLK>, 2444 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2445 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2446 clock-names = "bi_tcxo", 2447 "gcc_gpu_gpll0_clk_src", 2448 "gcc_gpu_gpll0_div_clk_src"; 2449 }; 2450 2451 stm@6002000 { 2452 compatible = "arm,coresight-stm", "arm,primecell"; 2453 reg = <0 0x06002000 0 0x1000>, 2454 <0 0x16280000 0 0x180000>; 2455 reg-names = "stm-base", "stm-stimulus-base"; 2456 2457 clocks = <&aoss_qmp>; 2458 clock-names = "apb_pclk"; 2459 2460 out-ports { 2461 port { 2462 stm_out: endpoint { 2463 remote-endpoint = 2464 <&funnel0_in7>; 2465 }; 2466 }; 2467 }; 2468 }; 2469 2470 funnel@6041000 { 2471 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2472 reg = <0 0x06041000 0 0x1000>; 2473 2474 clocks = <&aoss_qmp>; 2475 clock-names = "apb_pclk"; 2476 2477 out-ports { 2478 port { 2479 funnel0_out: endpoint { 2480 remote-endpoint = 2481 <&merge_funnel_in0>; 2482 }; 2483 }; 2484 }; 2485 2486 in-ports { 2487 #address-cells = <1>; 2488 #size-cells = <0>; 2489 2490 port@7 { 2491 reg = <7>; 2492 funnel0_in7: endpoint { 2493 remote-endpoint = <&stm_out>; 2494 }; 2495 }; 2496 }; 2497 }; 2498 2499 funnel@6043000 { 2500 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2501 reg = <0 0x06043000 0 0x1000>; 2502 2503 clocks = <&aoss_qmp>; 2504 clock-names = "apb_pclk"; 2505 2506 out-ports { 2507 port { 2508 funnel2_out: endpoint { 2509 remote-endpoint = 2510 <&merge_funnel_in2>; 2511 }; 2512 }; 2513 }; 2514 2515 in-ports { 2516 #address-cells = <1>; 2517 #size-cells = <0>; 2518 2519 port@5 { 2520 reg = <5>; 2521 funnel2_in5: endpoint { 2522 remote-endpoint = 2523 <&apss_merge_funnel_out>; 2524 }; 2525 }; 2526 }; 2527 }; 2528 2529 funnel@6045000 { 2530 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2531 reg = <0 0x06045000 0 0x1000>; 2532 2533 clocks = <&aoss_qmp>; 2534 clock-names = "apb_pclk"; 2535 2536 out-ports { 2537 port { 2538 merge_funnel_out: endpoint { 2539 remote-endpoint = <&etf_in>; 2540 }; 2541 }; 2542 }; 2543 2544 in-ports { 2545 #address-cells = <1>; 2546 #size-cells = <0>; 2547 2548 port@0 { 2549 reg = <0>; 2550 merge_funnel_in0: endpoint { 2551 remote-endpoint = 2552 <&funnel0_out>; 2553 }; 2554 }; 2555 2556 port@2 { 2557 reg = <2>; 2558 merge_funnel_in2: endpoint { 2559 remote-endpoint = 2560 <&funnel2_out>; 2561 }; 2562 }; 2563 }; 2564 }; 2565 2566 replicator@6046000 { 2567 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2568 reg = <0 0x06046000 0 0x1000>; 2569 2570 clocks = <&aoss_qmp>; 2571 clock-names = "apb_pclk"; 2572 2573 out-ports { 2574 port { 2575 replicator_out: endpoint { 2576 remote-endpoint = <&etr_in>; 2577 }; 2578 }; 2579 }; 2580 2581 in-ports { 2582 port { 2583 replicator_in: endpoint { 2584 remote-endpoint = <&etf_out>; 2585 }; 2586 }; 2587 }; 2588 }; 2589 2590 etf@6047000 { 2591 compatible = "arm,coresight-tmc", "arm,primecell"; 2592 reg = <0 0x06047000 0 0x1000>; 2593 2594 clocks = <&aoss_qmp>; 2595 clock-names = "apb_pclk"; 2596 2597 out-ports { 2598 port { 2599 etf_out: endpoint { 2600 remote-endpoint = 2601 <&replicator_in>; 2602 }; 2603 }; 2604 }; 2605 2606 in-ports { 2607 #address-cells = <1>; 2608 #size-cells = <0>; 2609 2610 port@1 { 2611 reg = <1>; 2612 etf_in: endpoint { 2613 remote-endpoint = 2614 <&merge_funnel_out>; 2615 }; 2616 }; 2617 }; 2618 }; 2619 2620 etr@6048000 { 2621 compatible = "arm,coresight-tmc", "arm,primecell"; 2622 reg = <0 0x06048000 0 0x1000>; 2623 2624 clocks = <&aoss_qmp>; 2625 clock-names = "apb_pclk"; 2626 arm,scatter-gather; 2627 2628 in-ports { 2629 port { 2630 etr_in: endpoint { 2631 remote-endpoint = 2632 <&replicator_out>; 2633 }; 2634 }; 2635 }; 2636 }; 2637 2638 etm@7040000 { 2639 compatible = "arm,coresight-etm4x", "arm,primecell"; 2640 reg = <0 0x07040000 0 0x1000>; 2641 2642 cpu = <&CPU0>; 2643 2644 clocks = <&aoss_qmp>; 2645 clock-names = "apb_pclk"; 2646 2647 out-ports { 2648 port { 2649 etm0_out: endpoint { 2650 remote-endpoint = 2651 <&apss_funnel_in0>; 2652 }; 2653 }; 2654 }; 2655 }; 2656 2657 etm@7140000 { 2658 compatible = "arm,coresight-etm4x", "arm,primecell"; 2659 reg = <0 0x07140000 0 0x1000>; 2660 2661 cpu = <&CPU1>; 2662 2663 clocks = <&aoss_qmp>; 2664 clock-names = "apb_pclk"; 2665 2666 out-ports { 2667 port { 2668 etm1_out: endpoint { 2669 remote-endpoint = 2670 <&apss_funnel_in1>; 2671 }; 2672 }; 2673 }; 2674 }; 2675 2676 etm@7240000 { 2677 compatible = "arm,coresight-etm4x", "arm,primecell"; 2678 reg = <0 0x07240000 0 0x1000>; 2679 2680 cpu = <&CPU2>; 2681 2682 clocks = <&aoss_qmp>; 2683 clock-names = "apb_pclk"; 2684 2685 out-ports { 2686 port { 2687 etm2_out: endpoint { 2688 remote-endpoint = 2689 <&apss_funnel_in2>; 2690 }; 2691 }; 2692 }; 2693 }; 2694 2695 etm@7340000 { 2696 compatible = "arm,coresight-etm4x", "arm,primecell"; 2697 reg = <0 0x07340000 0 0x1000>; 2698 2699 cpu = <&CPU3>; 2700 2701 clocks = <&aoss_qmp>; 2702 clock-names = "apb_pclk"; 2703 2704 out-ports { 2705 port { 2706 etm3_out: endpoint { 2707 remote-endpoint = 2708 <&apss_funnel_in3>; 2709 }; 2710 }; 2711 }; 2712 }; 2713 2714 etm@7440000 { 2715 compatible = "arm,coresight-etm4x", "arm,primecell"; 2716 reg = <0 0x07440000 0 0x1000>; 2717 2718 cpu = <&CPU4>; 2719 2720 clocks = <&aoss_qmp>; 2721 clock-names = "apb_pclk"; 2722 2723 out-ports { 2724 port { 2725 etm4_out: endpoint { 2726 remote-endpoint = 2727 <&apss_funnel_in4>; 2728 }; 2729 }; 2730 }; 2731 }; 2732 2733 etm@7540000 { 2734 compatible = "arm,coresight-etm4x", "arm,primecell"; 2735 reg = <0 0x07540000 0 0x1000>; 2736 2737 cpu = <&CPU5>; 2738 2739 clocks = <&aoss_qmp>; 2740 clock-names = "apb_pclk"; 2741 2742 out-ports { 2743 port { 2744 etm5_out: endpoint { 2745 remote-endpoint = 2746 <&apss_funnel_in5>; 2747 }; 2748 }; 2749 }; 2750 }; 2751 2752 etm@7640000 { 2753 compatible = "arm,coresight-etm4x", "arm,primecell"; 2754 reg = <0 0x07640000 0 0x1000>; 2755 2756 cpu = <&CPU6>; 2757 2758 clocks = <&aoss_qmp>; 2759 clock-names = "apb_pclk"; 2760 2761 out-ports { 2762 port { 2763 etm6_out: endpoint { 2764 remote-endpoint = 2765 <&apss_funnel_in6>; 2766 }; 2767 }; 2768 }; 2769 }; 2770 2771 etm@7740000 { 2772 compatible = "arm,coresight-etm4x", "arm,primecell"; 2773 reg = <0 0x07740000 0 0x1000>; 2774 2775 cpu = <&CPU7>; 2776 2777 clocks = <&aoss_qmp>; 2778 clock-names = "apb_pclk"; 2779 2780 out-ports { 2781 port { 2782 etm7_out: endpoint { 2783 remote-endpoint = 2784 <&apss_funnel_in7>; 2785 }; 2786 }; 2787 }; 2788 }; 2789 2790 funnel@7800000 { /* APSS Funnel */ 2791 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2792 reg = <0 0x07800000 0 0x1000>; 2793 2794 clocks = <&aoss_qmp>; 2795 clock-names = "apb_pclk"; 2796 2797 out-ports { 2798 port { 2799 apss_funnel_out: endpoint { 2800 remote-endpoint = 2801 <&apss_merge_funnel_in>; 2802 }; 2803 }; 2804 }; 2805 2806 in-ports { 2807 #address-cells = <1>; 2808 #size-cells = <0>; 2809 2810 port@0 { 2811 reg = <0>; 2812 apss_funnel_in0: endpoint { 2813 remote-endpoint = 2814 <&etm0_out>; 2815 }; 2816 }; 2817 2818 port@1 { 2819 reg = <1>; 2820 apss_funnel_in1: endpoint { 2821 remote-endpoint = 2822 <&etm1_out>; 2823 }; 2824 }; 2825 2826 port@2 { 2827 reg = <2>; 2828 apss_funnel_in2: endpoint { 2829 remote-endpoint = 2830 <&etm2_out>; 2831 }; 2832 }; 2833 2834 port@3 { 2835 reg = <3>; 2836 apss_funnel_in3: endpoint { 2837 remote-endpoint = 2838 <&etm3_out>; 2839 }; 2840 }; 2841 2842 port@4 { 2843 reg = <4>; 2844 apss_funnel_in4: endpoint { 2845 remote-endpoint = 2846 <&etm4_out>; 2847 }; 2848 }; 2849 2850 port@5 { 2851 reg = <5>; 2852 apss_funnel_in5: endpoint { 2853 remote-endpoint = 2854 <&etm5_out>; 2855 }; 2856 }; 2857 2858 port@6 { 2859 reg = <6>; 2860 apss_funnel_in6: endpoint { 2861 remote-endpoint = 2862 <&etm6_out>; 2863 }; 2864 }; 2865 2866 port@7 { 2867 reg = <7>; 2868 apss_funnel_in7: endpoint { 2869 remote-endpoint = 2870 <&etm7_out>; 2871 }; 2872 }; 2873 }; 2874 }; 2875 2876 funnel@7810000 { 2877 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2878 reg = <0 0x07810000 0 0x1000>; 2879 2880 clocks = <&aoss_qmp>; 2881 clock-names = "apb_pclk"; 2882 2883 out-ports { 2884 port { 2885 apss_merge_funnel_out: endpoint { 2886 remote-endpoint = 2887 <&funnel2_in5>; 2888 }; 2889 }; 2890 }; 2891 2892 in-ports { 2893 port { 2894 apss_merge_funnel_in: endpoint { 2895 remote-endpoint = 2896 <&apss_funnel_out>; 2897 }; 2898 }; 2899 }; 2900 }; 2901 2902 sdhc_2: sdhci@8804000 { 2903 compatible = "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5"; 2904 reg = <0 0x08804000 0 0x1000>; 2905 2906 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 2907 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 2908 interrupt-names = "hc_irq", "pwr_irq"; 2909 2910 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 2911 <&gcc GCC_SDCC2_APPS_CLK>; 2912 clock-names = "iface", "core"; 2913 iommus = <&apps_smmu 0xa0 0xf>; 2914 2915 status = "disabled"; 2916 }; 2917 2918 qspi: spi@88df000 { 2919 compatible = "qcom,sdm845-qspi", "qcom,qspi-v1"; 2920 reg = <0 0x088df000 0 0x600>; 2921 #address-cells = <1>; 2922 #size-cells = <0>; 2923 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 2924 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 2925 <&gcc GCC_QSPI_CORE_CLK>; 2926 clock-names = "iface", "core"; 2927 status = "disabled"; 2928 }; 2929 2930 slim: slim@171c0000 { 2931 compatible = "qcom,slim-ngd-v2.1.0"; 2932 reg = <0 0x171c0000 0 0x2c000>; 2933 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 2934 2935 qcom,apps-ch-pipes = <0x780000>; 2936 qcom,ea-pc = <0x270>; 2937 status = "okay"; 2938 dmas = <&slimbam 3>, <&slimbam 4>, 2939 <&slimbam 5>, <&slimbam 6>; 2940 dma-names = "rx", "tx", "tx2", "rx2"; 2941 2942 iommus = <&apps_smmu 0x1806 0x0>; 2943 #address-cells = <1>; 2944 #size-cells = <0>; 2945 2946 ngd@1 { 2947 reg = <1>; 2948 #address-cells = <2>; 2949 #size-cells = <0>; 2950 2951 wcd9340_ifd: ifd@0{ 2952 compatible = "slim217,250"; 2953 reg = <0 0>; 2954 }; 2955 2956 wcd9340: codec@1{ 2957 compatible = "slim217,250"; 2958 reg = <1 0>; 2959 slim-ifc-dev = <&wcd9340_ifd>; 2960 2961 #sound-dai-cells = <1>; 2962 2963 interrupts-extended = <&tlmm 54 IRQ_TYPE_LEVEL_HIGH>; 2964 interrupt-controller; 2965 #interrupt-cells = <1>; 2966 2967 #clock-cells = <0>; 2968 clock-frequency = <9600000>; 2969 clock-output-names = "mclk"; 2970 qcom,micbias1-millivolt = <1800>; 2971 qcom,micbias2-millivolt = <1800>; 2972 qcom,micbias3-millivolt = <1800>; 2973 qcom,micbias4-millivolt = <1800>; 2974 2975 #address-cells = <1>; 2976 #size-cells = <1>; 2977 2978 wcdgpio: gpio-controller@42 { 2979 compatible = "qcom,wcd9340-gpio"; 2980 gpio-controller; 2981 #gpio-cells = <2>; 2982 reg = <0x42 0x2>; 2983 }; 2984 2985 swm: swm@c85 { 2986 compatible = "qcom,soundwire-v1.3.0"; 2987 reg = <0xc85 0x40>; 2988 interrupts-extended = <&wcd9340 20>; 2989 2990 qcom,dout-ports = <6>; 2991 qcom,din-ports = <2>; 2992 qcom,ports-sinterval-low =/bits/ 8 <0x07 0x1F 0x3F 0x7 0x1F 0x3F 0x0F 0x0F>; 2993 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0C 0x6 0x12 0x0D 0x07 0x0A >; 2994 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x1F 0x00 0x00 0x1F 0x00 0x00>; 2995 2996 #sound-dai-cells = <1>; 2997 clocks = <&wcd9340>; 2998 clock-names = "iface"; 2999 #address-cells = <2>; 3000 #size-cells = <0>; 3001 3002 3003 }; 3004 }; 3005 }; 3006 }; 3007 3008 sound: sound { 3009 }; 3010 3011 usb_1_hsphy: phy@88e2000 { 3012 compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy"; 3013 reg = <0 0x088e2000 0 0x400>; 3014 status = "disabled"; 3015 #phy-cells = <0>; 3016 3017 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 3018 <&rpmhcc RPMH_CXO_CLK>; 3019 clock-names = "cfg_ahb", "ref"; 3020 3021 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3022 3023 nvmem-cells = <&qusb2p_hstx_trim>; 3024 }; 3025 3026 usb_2_hsphy: phy@88e3000 { 3027 compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy"; 3028 reg = <0 0x088e3000 0 0x400>; 3029 status = "disabled"; 3030 #phy-cells = <0>; 3031 3032 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 3033 <&rpmhcc RPMH_CXO_CLK>; 3034 clock-names = "cfg_ahb", "ref"; 3035 3036 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3037 3038 nvmem-cells = <&qusb2s_hstx_trim>; 3039 }; 3040 3041 usb_1_qmpphy: phy@88e9000 { 3042 compatible = "qcom,sdm845-qmp-usb3-phy"; 3043 reg = <0 0x088e9000 0 0x18c>, 3044 <0 0x088e8000 0 0x10>; 3045 reg-names = "reg-base", "dp_com"; 3046 status = "disabled"; 3047 #clock-cells = <1>; 3048 #address-cells = <2>; 3049 #size-cells = <2>; 3050 ranges; 3051 3052 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3053 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 3054 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 3055 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 3056 clock-names = "aux", "cfg_ahb", "ref", "com_aux"; 3057 3058 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 3059 <&gcc GCC_USB3_PHY_PRIM_BCR>; 3060 reset-names = "phy", "common"; 3061 3062 usb_1_ssphy: lanes@88e9200 { 3063 reg = <0 0x088e9200 0 0x128>, 3064 <0 0x088e9400 0 0x200>, 3065 <0 0x088e9c00 0 0x218>, 3066 <0 0x088e9600 0 0x128>, 3067 <0 0x088e9800 0 0x200>, 3068 <0 0x088e9a00 0 0x100>; 3069 #phy-cells = <0>; 3070 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3071 clock-names = "pipe0"; 3072 clock-output-names = "usb3_phy_pipe_clk_src"; 3073 }; 3074 }; 3075 3076 usb_2_qmpphy: phy@88eb000 { 3077 compatible = "qcom,sdm845-qmp-usb3-uni-phy"; 3078 reg = <0 0x088eb000 0 0x18c>; 3079 status = "disabled"; 3080 #clock-cells = <1>; 3081 #address-cells = <2>; 3082 #size-cells = <2>; 3083 ranges; 3084 3085 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 3086 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 3087 <&gcc GCC_USB3_SEC_CLKREF_CLK>, 3088 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; 3089 clock-names = "aux", "cfg_ahb", "ref", "com_aux"; 3090 3091 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, 3092 <&gcc GCC_USB3_PHY_SEC_BCR>; 3093 reset-names = "phy", "common"; 3094 3095 usb_2_ssphy: lane@88eb200 { 3096 reg = <0 0x088eb200 0 0x128>, 3097 <0 0x088eb400 0 0x1fc>, 3098 <0 0x088eb800 0 0x218>, 3099 <0 0x088eb600 0 0x70>; 3100 #phy-cells = <0>; 3101 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 3102 clock-names = "pipe0"; 3103 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 3104 }; 3105 }; 3106 3107 usb_1: usb@a6f8800 { 3108 compatible = "qcom,sdm845-dwc3", "qcom,dwc3"; 3109 reg = <0 0x0a6f8800 0 0x400>; 3110 status = "disabled"; 3111 #address-cells = <2>; 3112 #size-cells = <2>; 3113 ranges; 3114 dma-ranges; 3115 3116 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3117 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3118 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3119 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3120 <&gcc GCC_USB30_PRIM_SLEEP_CLK>; 3121 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 3122 "sleep"; 3123 3124 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3125 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3126 assigned-clock-rates = <19200000>, <150000000>; 3127 3128 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 3129 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>, 3130 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>, 3131 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>; 3132 interrupt-names = "hs_phy_irq", "ss_phy_irq", 3133 "dm_hs_phy_irq", "dp_hs_phy_irq"; 3134 3135 power-domains = <&gcc USB30_PRIM_GDSC>; 3136 3137 resets = <&gcc GCC_USB30_PRIM_BCR>; 3138 3139 interconnects = <&aggre2_noc MASTER_USB3_0 &mem_noc SLAVE_EBI1>, 3140 <&gladiator_noc MASTER_APPSS_PROC &config_noc SLAVE_USB3_0>; 3141 interconnect-names = "usb-ddr", "apps-usb"; 3142 3143 usb_1_dwc3: dwc3@a600000 { 3144 compatible = "snps,dwc3"; 3145 reg = <0 0x0a600000 0 0xcd00>; 3146 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 3147 iommus = <&apps_smmu 0x740 0>; 3148 snps,dis_u2_susphy_quirk; 3149 snps,dis_enblslpm_quirk; 3150 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 3151 phy-names = "usb2-phy", "usb3-phy"; 3152 }; 3153 }; 3154 3155 usb_2: usb@a8f8800 { 3156 compatible = "qcom,sdm845-dwc3", "qcom,dwc3"; 3157 reg = <0 0x0a8f8800 0 0x400>; 3158 status = "disabled"; 3159 #address-cells = <2>; 3160 #size-cells = <2>; 3161 ranges; 3162 dma-ranges; 3163 3164 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 3165 <&gcc GCC_USB30_SEC_MASTER_CLK>, 3166 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 3167 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3168 <&gcc GCC_USB30_SEC_SLEEP_CLK>; 3169 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 3170 "sleep"; 3171 3172 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3173 <&gcc GCC_USB30_SEC_MASTER_CLK>; 3174 assigned-clock-rates = <19200000>, <150000000>; 3175 3176 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 3177 <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>, 3178 <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>, 3179 <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>; 3180 interrupt-names = "hs_phy_irq", "ss_phy_irq", 3181 "dm_hs_phy_irq", "dp_hs_phy_irq"; 3182 3183 power-domains = <&gcc USB30_SEC_GDSC>; 3184 3185 resets = <&gcc GCC_USB30_SEC_BCR>; 3186 3187 interconnects = <&aggre2_noc MASTER_USB3_1 &mem_noc SLAVE_EBI1>, 3188 <&gladiator_noc MASTER_APPSS_PROC &config_noc SLAVE_USB3_1>; 3189 interconnect-names = "usb-ddr", "apps-usb"; 3190 3191 usb_2_dwc3: dwc3@a800000 { 3192 compatible = "snps,dwc3"; 3193 reg = <0 0x0a800000 0 0xcd00>; 3194 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 3195 iommus = <&apps_smmu 0x760 0>; 3196 snps,dis_u2_susphy_quirk; 3197 snps,dis_enblslpm_quirk; 3198 phys = <&usb_2_hsphy>, <&usb_2_ssphy>; 3199 phy-names = "usb2-phy", "usb3-phy"; 3200 }; 3201 }; 3202 3203 venus: video-codec@aa00000 { 3204 compatible = "qcom,sdm845-venus-v2"; 3205 reg = <0 0x0aa00000 0 0xff000>; 3206 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 3207 power-domains = <&videocc VENUS_GDSC>, 3208 <&videocc VCODEC0_GDSC>, 3209 <&videocc VCODEC1_GDSC>; 3210 power-domain-names = "venus", "vcodec0", "vcodec1"; 3211 clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>, 3212 <&videocc VIDEO_CC_VENUS_AHB_CLK>, 3213 <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>, 3214 <&videocc VIDEO_CC_VCODEC0_CORE_CLK>, 3215 <&videocc VIDEO_CC_VCODEC0_AXI_CLK>, 3216 <&videocc VIDEO_CC_VCODEC1_CORE_CLK>, 3217 <&videocc VIDEO_CC_VCODEC1_AXI_CLK>; 3218 clock-names = "core", "iface", "bus", 3219 "vcodec0_core", "vcodec0_bus", 3220 "vcodec1_core", "vcodec1_bus"; 3221 iommus = <&apps_smmu 0x10a0 0x8>, 3222 <&apps_smmu 0x10b0 0x0>; 3223 memory-region = <&venus_mem>; 3224 3225 video-core0 { 3226 compatible = "venus-decoder"; 3227 }; 3228 3229 video-core1 { 3230 compatible = "venus-encoder"; 3231 }; 3232 }; 3233 3234 videocc: clock-controller@ab00000 { 3235 compatible = "qcom,sdm845-videocc"; 3236 reg = <0 0x0ab00000 0 0x10000>; 3237 clocks = <&rpmhcc RPMH_CXO_CLK>; 3238 clock-names = "bi_tcxo"; 3239 #clock-cells = <1>; 3240 #power-domain-cells = <1>; 3241 #reset-cells = <1>; 3242 }; 3243 3244 cci: cci@ac4a000 { 3245 compatible = "qcom,sdm845-cci"; 3246 #address-cells = <1>; 3247 #size-cells = <0>; 3248 3249 reg = <0 0x0ac4a000 0 0x4000>; 3250 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>; 3251 power-domains = <&clock_camcc TITAN_TOP_GDSC>; 3252 3253 clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, 3254 <&clock_camcc CAM_CC_SOC_AHB_CLK>, 3255 <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, 3256 <&clock_camcc CAM_CC_CPAS_AHB_CLK>, 3257 <&clock_camcc CAM_CC_CCI_CLK>, 3258 <&clock_camcc CAM_CC_CCI_CLK_SRC>; 3259 clock-names = "camnoc_axi", 3260 "soc_ahb", 3261 "slow_ahb_src", 3262 "cpas_ahb", 3263 "cci", 3264 "cci_src"; 3265 3266 assigned-clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, 3267 <&clock_camcc CAM_CC_CCI_CLK>; 3268 assigned-clock-rates = <80000000>, <37500000>; 3269 3270 pinctrl-names = "default", "sleep"; 3271 pinctrl-0 = <&cci0_default &cci1_default>; 3272 pinctrl-1 = <&cci0_sleep &cci1_sleep>; 3273 3274 status = "disabled"; 3275 3276 cci_i2c0: i2c-bus@0 { 3277 reg = <0>; 3278 clock-frequency = <1000000>; 3279 #address-cells = <1>; 3280 #size-cells = <0>; 3281 }; 3282 3283 cci_i2c1: i2c-bus@1 { 3284 reg = <1>; 3285 clock-frequency = <1000000>; 3286 #address-cells = <1>; 3287 #size-cells = <0>; 3288 }; 3289 }; 3290 3291 clock_camcc: clock-controller@ad00000 { 3292 compatible = "qcom,sdm845-camcc"; 3293 reg = <0 0x0ad00000 0 0x10000>; 3294 #clock-cells = <1>; 3295 #reset-cells = <1>; 3296 #power-domain-cells = <1>; 3297 }; 3298 3299 mdss: mdss@ae00000 { 3300 compatible = "qcom,sdm845-mdss"; 3301 reg = <0 0x0ae00000 0 0x1000>; 3302 reg-names = "mdss"; 3303 3304 power-domains = <&dispcc MDSS_GDSC>; 3305 3306 clocks = <&gcc GCC_DISP_AHB_CLK>, 3307 <&gcc GCC_DISP_AXI_CLK>, 3308 <&dispcc DISP_CC_MDSS_MDP_CLK>; 3309 clock-names = "iface", "bus", "core"; 3310 3311 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; 3312 assigned-clock-rates = <300000000>; 3313 3314 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 3315 interrupt-controller; 3316 #interrupt-cells = <1>; 3317 3318 iommus = <&apps_smmu 0x880 0x8>, 3319 <&apps_smmu 0xc80 0x8>; 3320 3321 status = "disabled"; 3322 3323 #address-cells = <2>; 3324 #size-cells = <2>; 3325 ranges; 3326 3327 mdss_mdp: mdp@ae01000 { 3328 compatible = "qcom,sdm845-dpu"; 3329 reg = <0 0x0ae01000 0 0x8f000>, 3330 <0 0x0aeb0000 0 0x2008>; 3331 reg-names = "mdp", "vbif"; 3332 3333 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3334 <&dispcc DISP_CC_MDSS_AXI_CLK>, 3335 <&dispcc DISP_CC_MDSS_MDP_CLK>, 3336 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3337 clock-names = "iface", "bus", "core", "vsync"; 3338 3339 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, 3340 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3341 assigned-clock-rates = <300000000>, 3342 <19200000>; 3343 3344 interrupt-parent = <&mdss>; 3345 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; 3346 3347 status = "disabled"; 3348 3349 ports { 3350 #address-cells = <1>; 3351 #size-cells = <0>; 3352 3353 port@0 { 3354 reg = <0>; 3355 dpu_intf1_out: endpoint { 3356 remote-endpoint = <&dsi0_in>; 3357 }; 3358 }; 3359 3360 port@1 { 3361 reg = <1>; 3362 dpu_intf2_out: endpoint { 3363 remote-endpoint = <&dsi1_in>; 3364 }; 3365 }; 3366 }; 3367 }; 3368 3369 dsi0: dsi@ae94000 { 3370 compatible = "qcom,mdss-dsi-ctrl"; 3371 reg = <0 0x0ae94000 0 0x400>; 3372 reg-names = "dsi_ctrl"; 3373 3374 interrupt-parent = <&mdss>; 3375 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; 3376 3377 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 3378 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 3379 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 3380 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 3381 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3382 <&dispcc DISP_CC_MDSS_AXI_CLK>; 3383 clock-names = "byte", 3384 "byte_intf", 3385 "pixel", 3386 "core", 3387 "iface", 3388 "bus"; 3389 3390 phys = <&dsi0_phy>; 3391 phy-names = "dsi"; 3392 3393 status = "disabled"; 3394 3395 ports { 3396 #address-cells = <1>; 3397 #size-cells = <0>; 3398 3399 port@0 { 3400 reg = <0>; 3401 dsi0_in: endpoint { 3402 remote-endpoint = <&dpu_intf1_out>; 3403 }; 3404 }; 3405 3406 port@1 { 3407 reg = <1>; 3408 dsi0_out: endpoint { 3409 }; 3410 }; 3411 }; 3412 }; 3413 3414 dsi0_phy: dsi-phy@ae94400 { 3415 compatible = "qcom,dsi-phy-10nm"; 3416 reg = <0 0x0ae94400 0 0x200>, 3417 <0 0x0ae94600 0 0x280>, 3418 <0 0x0ae94a00 0 0x1e0>; 3419 reg-names = "dsi_phy", 3420 "dsi_phy_lane", 3421 "dsi_pll"; 3422 3423 #clock-cells = <1>; 3424 #phy-cells = <0>; 3425 3426 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3427 <&rpmhcc RPMH_CXO_CLK>; 3428 clock-names = "iface", "ref"; 3429 3430 status = "disabled"; 3431 }; 3432 3433 dsi1: dsi@ae96000 { 3434 compatible = "qcom,mdss-dsi-ctrl"; 3435 reg = <0 0x0ae96000 0 0x400>; 3436 reg-names = "dsi_ctrl"; 3437 3438 interrupt-parent = <&mdss>; 3439 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; 3440 3441 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 3442 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 3443 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 3444 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 3445 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3446 <&dispcc DISP_CC_MDSS_AXI_CLK>; 3447 clock-names = "byte", 3448 "byte_intf", 3449 "pixel", 3450 "core", 3451 "iface", 3452 "bus"; 3453 3454 phys = <&dsi1_phy>; 3455 phy-names = "dsi"; 3456 3457 status = "disabled"; 3458 3459 ports { 3460 #address-cells = <1>; 3461 #size-cells = <0>; 3462 3463 port@0 { 3464 reg = <0>; 3465 dsi1_in: endpoint { 3466 remote-endpoint = <&dpu_intf2_out>; 3467 }; 3468 }; 3469 3470 port@1 { 3471 reg = <1>; 3472 dsi1_out: endpoint { 3473 }; 3474 }; 3475 }; 3476 }; 3477 3478 dsi1_phy: dsi-phy@ae96400 { 3479 compatible = "qcom,dsi-phy-10nm"; 3480 reg = <0 0x0ae96400 0 0x200>, 3481 <0 0x0ae96600 0 0x280>, 3482 <0 0x0ae96a00 0 0x10e>; 3483 reg-names = "dsi_phy", 3484 "dsi_phy_lane", 3485 "dsi_pll"; 3486 3487 #clock-cells = <1>; 3488 #phy-cells = <0>; 3489 3490 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3491 <&rpmhcc RPMH_CXO_CLK>; 3492 clock-names = "iface", "ref"; 3493 3494 status = "disabled"; 3495 }; 3496 }; 3497 3498 gpu: gpu@5000000 { 3499 compatible = "qcom,adreno-630.2", "qcom,adreno"; 3500 #stream-id-cells = <16>; 3501 3502 reg = <0 0x5000000 0 0x40000>, <0 0x509e000 0 0x10>; 3503 reg-names = "kgsl_3d0_reg_memory", "cx_mem"; 3504 3505 /* 3506 * Look ma, no clocks! The GPU clocks and power are 3507 * controlled entirely by the GMU 3508 */ 3509 3510 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 3511 3512 iommus = <&adreno_smmu 0>; 3513 3514 operating-points-v2 = <&gpu_opp_table>; 3515 3516 qcom,gmu = <&gmu>; 3517 3518 gpu_opp_table: opp-table { 3519 compatible = "operating-points-v2"; 3520 3521 opp-710000000 { 3522 opp-hz = /bits/ 64 <710000000>; 3523 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3524 }; 3525 3526 opp-675000000 { 3527 opp-hz = /bits/ 64 <675000000>; 3528 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3529 }; 3530 3531 opp-596000000 { 3532 opp-hz = /bits/ 64 <596000000>; 3533 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3534 }; 3535 3536 opp-520000000 { 3537 opp-hz = /bits/ 64 <520000000>; 3538 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3539 }; 3540 3541 opp-414000000 { 3542 opp-hz = /bits/ 64 <414000000>; 3543 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3544 }; 3545 3546 opp-342000000 { 3547 opp-hz = /bits/ 64 <342000000>; 3548 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3549 }; 3550 3551 opp-257000000 { 3552 opp-hz = /bits/ 64 <257000000>; 3553 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3554 }; 3555 }; 3556 }; 3557 3558 adreno_smmu: iommu@5040000 { 3559 compatible = "qcom,sdm845-smmu-v2", "qcom,smmu-v2"; 3560 reg = <0 0x5040000 0 0x10000>; 3561 #iommu-cells = <1>; 3562 #global-interrupts = <2>; 3563 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 3564 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 3565 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, 3566 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, 3567 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>, 3568 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>, 3569 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>, 3570 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>, 3571 <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>, 3572 <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>; 3573 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 3574 <&gcc GCC_GPU_CFG_AHB_CLK>; 3575 clock-names = "bus", "iface"; 3576 3577 power-domains = <&gpucc GPU_CX_GDSC>; 3578 }; 3579 3580 gmu: gmu@506a000 { 3581 compatible="qcom,adreno-gmu-630.2", "qcom,adreno-gmu"; 3582 3583 reg = <0 0x506a000 0 0x30000>, 3584 <0 0xb280000 0 0x10000>, 3585 <0 0xb480000 0 0x10000>; 3586 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; 3587 3588 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 3589 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 3590 interrupt-names = "hfi", "gmu"; 3591 3592 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 3593 <&gpucc GPU_CC_CXO_CLK>, 3594 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 3595 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 3596 clock-names = "gmu", "cxo", "axi", "memnoc"; 3597 3598 power-domains = <&gpucc GPU_CX_GDSC>, 3599 <&gpucc GPU_GX_GDSC>; 3600 power-domain-names = "cx", "gx"; 3601 3602 iommus = <&adreno_smmu 5>; 3603 3604 operating-points-v2 = <&gmu_opp_table>; 3605 3606 gmu_opp_table: opp-table { 3607 compatible = "operating-points-v2"; 3608 3609 opp-400000000 { 3610 opp-hz = /bits/ 64 <400000000>; 3611 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3612 }; 3613 3614 opp-200000000 { 3615 opp-hz = /bits/ 64 <200000000>; 3616 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3617 }; 3618 }; 3619 }; 3620 3621 dispcc: clock-controller@af00000 { 3622 compatible = "qcom,sdm845-dispcc"; 3623 reg = <0 0x0af00000 0 0x10000>; 3624 clocks = <&rpmhcc RPMH_CXO_CLK>, 3625 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 3626 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, 3627 <&dsi0_phy 0>, 3628 <&dsi0_phy 1>, 3629 <&dsi1_phy 0>, 3630 <&dsi1_phy 1>, 3631 <0>, 3632 <0>; 3633 clock-names = "bi_tcxo", 3634 "gcc_disp_gpll0_clk_src", 3635 "gcc_disp_gpll0_div_clk_src", 3636 "dsi0_phy_pll_out_byteclk", 3637 "dsi0_phy_pll_out_dsiclk", 3638 "dsi1_phy_pll_out_byteclk", 3639 "dsi1_phy_pll_out_dsiclk", 3640 "dp_link_clk_divsel_ten", 3641 "dp_vco_divided_clk_src_mux"; 3642 #clock-cells = <1>; 3643 #reset-cells = <1>; 3644 #power-domain-cells = <1>; 3645 }; 3646 3647 pdc_intc: interrupt-controller@b220000 { 3648 compatible = "qcom,sdm845-pdc", "qcom,pdc"; 3649 reg = <0 0x0b220000 0 0x30000>; 3650 qcom,pdc-ranges = <0 480 94>, <94 609 15>, <115 630 7>; 3651 #interrupt-cells = <2>; 3652 interrupt-parent = <&intc>; 3653 interrupt-controller; 3654 }; 3655 3656 pdc_reset: reset-controller@b2e0000 { 3657 compatible = "qcom,sdm845-pdc-global"; 3658 reg = <0 0x0b2e0000 0 0x20000>; 3659 #reset-cells = <1>; 3660 }; 3661 3662 tsens0: thermal-sensor@c263000 { 3663 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; 3664 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 3665 <0 0x0c222000 0 0x1ff>; /* SROT */ 3666 #qcom,sensors = <13>; 3667 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 3668 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 3669 interrupt-names = "uplow", "critical"; 3670 #thermal-sensor-cells = <1>; 3671 }; 3672 3673 tsens1: thermal-sensor@c265000 { 3674 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; 3675 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 3676 <0 0x0c223000 0 0x1ff>; /* SROT */ 3677 #qcom,sensors = <8>; 3678 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 3679 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 3680 interrupt-names = "uplow", "critical"; 3681 #thermal-sensor-cells = <1>; 3682 }; 3683 3684 aoss_reset: reset-controller@c2a0000 { 3685 compatible = "qcom,sdm845-aoss-cc"; 3686 reg = <0 0x0c2a0000 0 0x31000>; 3687 #reset-cells = <1>; 3688 }; 3689 3690 aoss_qmp: qmp@c300000 { 3691 compatible = "qcom,sdm845-aoss-qmp"; 3692 reg = <0 0x0c300000 0 0x100000>; 3693 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; 3694 mboxes = <&apss_shared 0>; 3695 3696 #clock-cells = <0>; 3697 #power-domain-cells = <1>; 3698 3699 cx_cdev: cx { 3700 #cooling-cells = <2>; 3701 }; 3702 3703 ebi_cdev: ebi { 3704 #cooling-cells = <2>; 3705 }; 3706 }; 3707 3708 spmi_bus: spmi@c440000 { 3709 compatible = "qcom,spmi-pmic-arb"; 3710 reg = <0 0x0c440000 0 0x1100>, 3711 <0 0x0c600000 0 0x2000000>, 3712 <0 0x0e600000 0 0x100000>, 3713 <0 0x0e700000 0 0xa0000>, 3714 <0 0x0c40a000 0 0x26000>; 3715 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 3716 interrupt-names = "periph_irq"; 3717 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>; 3718 qcom,ee = <0>; 3719 qcom,channel = <0>; 3720 #address-cells = <2>; 3721 #size-cells = <0>; 3722 interrupt-controller; 3723 #interrupt-cells = <4>; 3724 cell-index = <0>; 3725 }; 3726 3727 apps_smmu: iommu@15000000 { 3728 compatible = "qcom,sdm845-smmu-500", "arm,mmu-500"; 3729 reg = <0 0x15000000 0 0x80000>; 3730 #iommu-cells = <2>; 3731 #global-interrupts = <1>; 3732 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3733 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 3734 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3735 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3736 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3737 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3738 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3739 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3740 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3741 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3742 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3743 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3744 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3745 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3746 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3747 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3748 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3749 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3750 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3751 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3752 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3753 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3754 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3755 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3756 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3757 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3758 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3759 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3760 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3761 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3762 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3763 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3764 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3765 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3766 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3767 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3768 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3769 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3770 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3771 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3772 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3773 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3774 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3775 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3776 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3777 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3778 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3779 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3780 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3781 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3782 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3783 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3784 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3785 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3786 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3787 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3788 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3789 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3790 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3791 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3792 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3793 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3794 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3795 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3796 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>; 3797 }; 3798 3799 lpasscc: clock-controller@17014000 { 3800 compatible = "qcom,sdm845-lpasscc"; 3801 reg = <0 0x17014000 0 0x1f004>, <0 0x17300000 0 0x200>; 3802 reg-names = "cc", "qdsp6ss"; 3803 #clock-cells = <1>; 3804 status = "disabled"; 3805 }; 3806 3807 gladiator_noc: interconnect@17900000 { 3808 compatible = "qcom,sdm845-gladiator-noc"; 3809 reg = <0 0x17900000 0 0xd080>; 3810 #interconnect-cells = <1>; 3811 qcom,bcm-voters = <&apps_bcm_voter>; 3812 }; 3813 3814 watchdog@17980000 { 3815 compatible = "qcom,apss-wdt-sdm845", "qcom,kpss-wdt"; 3816 reg = <0 0x17980000 0 0x1000>; 3817 clocks = <&sleep_clk>; 3818 }; 3819 3820 apss_shared: mailbox@17990000 { 3821 compatible = "qcom,sdm845-apss-shared"; 3822 reg = <0 0x17990000 0 0x1000>; 3823 #mbox-cells = <1>; 3824 }; 3825 3826 apps_rsc: rsc@179c0000 { 3827 label = "apps_rsc"; 3828 compatible = "qcom,rpmh-rsc"; 3829 reg = <0 0x179c0000 0 0x10000>, 3830 <0 0x179d0000 0 0x10000>, 3831 <0 0x179e0000 0 0x10000>; 3832 reg-names = "drv-0", "drv-1", "drv-2"; 3833 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3834 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3835 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3836 qcom,tcs-offset = <0xd00>; 3837 qcom,drv-id = <2>; 3838 qcom,tcs-config = <ACTIVE_TCS 2>, 3839 <SLEEP_TCS 3>, 3840 <WAKE_TCS 3>, 3841 <CONTROL_TCS 1>; 3842 3843 apps_bcm_voter: bcm-voter { 3844 compatible = "qcom,bcm-voter"; 3845 }; 3846 3847 rpmhcc: clock-controller { 3848 compatible = "qcom,sdm845-rpmh-clk"; 3849 #clock-cells = <1>; 3850 clock-names = "xo"; 3851 clocks = <&xo_board>; 3852 }; 3853 3854 rpmhpd: power-controller { 3855 compatible = "qcom,sdm845-rpmhpd"; 3856 #power-domain-cells = <1>; 3857 operating-points-v2 = <&rpmhpd_opp_table>; 3858 3859 rpmhpd_opp_table: opp-table { 3860 compatible = "operating-points-v2"; 3861 3862 rpmhpd_opp_ret: opp1 { 3863 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3864 }; 3865 3866 rpmhpd_opp_min_svs: opp2 { 3867 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3868 }; 3869 3870 rpmhpd_opp_low_svs: opp3 { 3871 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3872 }; 3873 3874 rpmhpd_opp_svs: opp4 { 3875 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3876 }; 3877 3878 rpmhpd_opp_svs_l1: opp5 { 3879 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3880 }; 3881 3882 rpmhpd_opp_nom: opp6 { 3883 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3884 }; 3885 3886 rpmhpd_opp_nom_l1: opp7 { 3887 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3888 }; 3889 3890 rpmhpd_opp_nom_l2: opp8 { 3891 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 3892 }; 3893 3894 rpmhpd_opp_turbo: opp9 { 3895 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3896 }; 3897 3898 rpmhpd_opp_turbo_l1: opp10 { 3899 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3900 }; 3901 }; 3902 }; 3903 }; 3904 3905 intc: interrupt-controller@17a00000 { 3906 compatible = "arm,gic-v3"; 3907 #address-cells = <2>; 3908 #size-cells = <2>; 3909 ranges; 3910 #interrupt-cells = <3>; 3911 interrupt-controller; 3912 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 3913 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 3914 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3915 3916 msi-controller@17a40000 { 3917 compatible = "arm,gic-v3-its"; 3918 msi-controller; 3919 #msi-cells = <1>; 3920 reg = <0 0x17a40000 0 0x20000>; 3921 status = "disabled"; 3922 }; 3923 }; 3924 3925 slimbam: dma@17184000 { 3926 compatible = "qcom,bam-v1.7.0"; 3927 qcom,controlled-remotely; 3928 reg = <0 0x17184000 0 0x2a000>; 3929 num-channels = <31>; 3930 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 3931 #dma-cells = <1>; 3932 qcom,ee = <1>; 3933 qcom,num-ees = <2>; 3934 iommus = <&apps_smmu 0x1806 0x0>; 3935 }; 3936 3937 timer@17c90000 { 3938 #address-cells = <2>; 3939 #size-cells = <2>; 3940 ranges; 3941 compatible = "arm,armv7-timer-mem"; 3942 reg = <0 0x17c90000 0 0x1000>; 3943 3944 frame@17ca0000 { 3945 frame-number = <0>; 3946 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 3947 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3948 reg = <0 0x17ca0000 0 0x1000>, 3949 <0 0x17cb0000 0 0x1000>; 3950 }; 3951 3952 frame@17cc0000 { 3953 frame-number = <1>; 3954 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 3955 reg = <0 0x17cc0000 0 0x1000>; 3956 status = "disabled"; 3957 }; 3958 3959 frame@17cd0000 { 3960 frame-number = <2>; 3961 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3962 reg = <0 0x17cd0000 0 0x1000>; 3963 status = "disabled"; 3964 }; 3965 3966 frame@17ce0000 { 3967 frame-number = <3>; 3968 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3969 reg = <0 0x17ce0000 0 0x1000>; 3970 status = "disabled"; 3971 }; 3972 3973 frame@17cf0000 { 3974 frame-number = <4>; 3975 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3976 reg = <0 0x17cf0000 0 0x1000>; 3977 status = "disabled"; 3978 }; 3979 3980 frame@17d00000 { 3981 frame-number = <5>; 3982 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3983 reg = <0 0x17d00000 0 0x1000>; 3984 status = "disabled"; 3985 }; 3986 3987 frame@17d10000 { 3988 frame-number = <6>; 3989 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3990 reg = <0 0x17d10000 0 0x1000>; 3991 status = "disabled"; 3992 }; 3993 }; 3994 3995 osm_l3: interconnect@17d41000 { 3996 compatible = "qcom,sdm845-osm-l3"; 3997 reg = <0 0x17d41000 0 0x1400>; 3998 3999 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 4000 clock-names = "xo", "alternate"; 4001 4002 #interconnect-cells = <1>; 4003 }; 4004 4005 cpufreq_hw: cpufreq@17d43000 { 4006 compatible = "qcom,cpufreq-hw"; 4007 reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>; 4008 reg-names = "freq-domain0", "freq-domain1"; 4009 4010 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 4011 clock-names = "xo", "alternate"; 4012 4013 #freq-domain-cells = <1>; 4014 }; 4015 4016 wifi: wifi@18800000 { 4017 compatible = "qcom,wcn3990-wifi"; 4018 status = "disabled"; 4019 reg = <0 0x18800000 0 0x800000>; 4020 reg-names = "membase"; 4021 memory-region = <&wlan_msa_mem>; 4022 clock-names = "cxo_ref_clk_pin"; 4023 clocks = <&rpmhcc RPMH_RF_CLK2>; 4024 interrupts = 4025 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 4026 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 4027 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 4028 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 4029 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 4030 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 4031 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 4032 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 4033 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 4034 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 4035 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 4036 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 4037 iommus = <&apps_smmu 0x0040 0x1>; 4038 }; 4039 }; 4040 4041 thermal-zones { 4042 cpu0-thermal { 4043 polling-delay-passive = <250>; 4044 polling-delay = <1000>; 4045 4046 thermal-sensors = <&tsens0 1>; 4047 4048 trips { 4049 cpu0_alert0: trip-point0 { 4050 temperature = <90000>; 4051 hysteresis = <2000>; 4052 type = "passive"; 4053 }; 4054 4055 cpu0_alert1: trip-point1 { 4056 temperature = <95000>; 4057 hysteresis = <2000>; 4058 type = "passive"; 4059 }; 4060 4061 cpu0_crit: cpu_crit { 4062 temperature = <110000>; 4063 hysteresis = <1000>; 4064 type = "critical"; 4065 }; 4066 }; 4067 4068 cooling-maps { 4069 map0 { 4070 trip = <&cpu0_alert0>; 4071 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4072 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4073 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4074 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4075 }; 4076 map1 { 4077 trip = <&cpu0_alert1>; 4078 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4079 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4080 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4081 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4082 }; 4083 }; 4084 }; 4085 4086 cpu1-thermal { 4087 polling-delay-passive = <250>; 4088 polling-delay = <1000>; 4089 4090 thermal-sensors = <&tsens0 2>; 4091 4092 trips { 4093 cpu1_alert0: trip-point0 { 4094 temperature = <90000>; 4095 hysteresis = <2000>; 4096 type = "passive"; 4097 }; 4098 4099 cpu1_alert1: trip-point1 { 4100 temperature = <95000>; 4101 hysteresis = <2000>; 4102 type = "passive"; 4103 }; 4104 4105 cpu1_crit: cpu_crit { 4106 temperature = <110000>; 4107 hysteresis = <1000>; 4108 type = "critical"; 4109 }; 4110 }; 4111 4112 cooling-maps { 4113 map0 { 4114 trip = <&cpu1_alert0>; 4115 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4116 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4117 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4118 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4119 }; 4120 map1 { 4121 trip = <&cpu1_alert1>; 4122 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4123 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4124 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4125 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4126 }; 4127 }; 4128 }; 4129 4130 cpu2-thermal { 4131 polling-delay-passive = <250>; 4132 polling-delay = <1000>; 4133 4134 thermal-sensors = <&tsens0 3>; 4135 4136 trips { 4137 cpu2_alert0: trip-point0 { 4138 temperature = <90000>; 4139 hysteresis = <2000>; 4140 type = "passive"; 4141 }; 4142 4143 cpu2_alert1: trip-point1 { 4144 temperature = <95000>; 4145 hysteresis = <2000>; 4146 type = "passive"; 4147 }; 4148 4149 cpu2_crit: cpu_crit { 4150 temperature = <110000>; 4151 hysteresis = <1000>; 4152 type = "critical"; 4153 }; 4154 }; 4155 4156 cooling-maps { 4157 map0 { 4158 trip = <&cpu2_alert0>; 4159 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4160 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4161 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4162 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4163 }; 4164 map1 { 4165 trip = <&cpu2_alert1>; 4166 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4167 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4168 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4169 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4170 }; 4171 }; 4172 }; 4173 4174 cpu3-thermal { 4175 polling-delay-passive = <250>; 4176 polling-delay = <1000>; 4177 4178 thermal-sensors = <&tsens0 4>; 4179 4180 trips { 4181 cpu3_alert0: trip-point0 { 4182 temperature = <90000>; 4183 hysteresis = <2000>; 4184 type = "passive"; 4185 }; 4186 4187 cpu3_alert1: trip-point1 { 4188 temperature = <95000>; 4189 hysteresis = <2000>; 4190 type = "passive"; 4191 }; 4192 4193 cpu3_crit: cpu_crit { 4194 temperature = <110000>; 4195 hysteresis = <1000>; 4196 type = "critical"; 4197 }; 4198 }; 4199 4200 cooling-maps { 4201 map0 { 4202 trip = <&cpu3_alert0>; 4203 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4204 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4205 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4206 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4207 }; 4208 map1 { 4209 trip = <&cpu3_alert1>; 4210 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4211 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4212 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4213 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4214 }; 4215 }; 4216 }; 4217 4218 cpu4-thermal { 4219 polling-delay-passive = <250>; 4220 polling-delay = <1000>; 4221 4222 thermal-sensors = <&tsens0 7>; 4223 4224 trips { 4225 cpu4_alert0: trip-point0 { 4226 temperature = <90000>; 4227 hysteresis = <2000>; 4228 type = "passive"; 4229 }; 4230 4231 cpu4_alert1: trip-point1 { 4232 temperature = <95000>; 4233 hysteresis = <2000>; 4234 type = "passive"; 4235 }; 4236 4237 cpu4_crit: cpu_crit { 4238 temperature = <110000>; 4239 hysteresis = <1000>; 4240 type = "critical"; 4241 }; 4242 }; 4243 4244 cooling-maps { 4245 map0 { 4246 trip = <&cpu4_alert0>; 4247 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4248 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4249 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4250 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4251 }; 4252 map1 { 4253 trip = <&cpu4_alert1>; 4254 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4255 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4256 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4257 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4258 }; 4259 }; 4260 }; 4261 4262 cpu5-thermal { 4263 polling-delay-passive = <250>; 4264 polling-delay = <1000>; 4265 4266 thermal-sensors = <&tsens0 8>; 4267 4268 trips { 4269 cpu5_alert0: trip-point0 { 4270 temperature = <90000>; 4271 hysteresis = <2000>; 4272 type = "passive"; 4273 }; 4274 4275 cpu5_alert1: trip-point1 { 4276 temperature = <95000>; 4277 hysteresis = <2000>; 4278 type = "passive"; 4279 }; 4280 4281 cpu5_crit: cpu_crit { 4282 temperature = <110000>; 4283 hysteresis = <1000>; 4284 type = "critical"; 4285 }; 4286 }; 4287 4288 cooling-maps { 4289 map0 { 4290 trip = <&cpu5_alert0>; 4291 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4292 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4293 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4294 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4295 }; 4296 map1 { 4297 trip = <&cpu5_alert1>; 4298 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4299 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4300 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4301 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4302 }; 4303 }; 4304 }; 4305 4306 cpu6-thermal { 4307 polling-delay-passive = <250>; 4308 polling-delay = <1000>; 4309 4310 thermal-sensors = <&tsens0 9>; 4311 4312 trips { 4313 cpu6_alert0: trip-point0 { 4314 temperature = <90000>; 4315 hysteresis = <2000>; 4316 type = "passive"; 4317 }; 4318 4319 cpu6_alert1: trip-point1 { 4320 temperature = <95000>; 4321 hysteresis = <2000>; 4322 type = "passive"; 4323 }; 4324 4325 cpu6_crit: cpu_crit { 4326 temperature = <110000>; 4327 hysteresis = <1000>; 4328 type = "critical"; 4329 }; 4330 }; 4331 4332 cooling-maps { 4333 map0 { 4334 trip = <&cpu6_alert0>; 4335 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4336 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4337 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4338 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4339 }; 4340 map1 { 4341 trip = <&cpu6_alert1>; 4342 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4343 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4344 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4345 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4346 }; 4347 }; 4348 }; 4349 4350 cpu7-thermal { 4351 polling-delay-passive = <250>; 4352 polling-delay = <1000>; 4353 4354 thermal-sensors = <&tsens0 10>; 4355 4356 trips { 4357 cpu7_alert0: trip-point0 { 4358 temperature = <90000>; 4359 hysteresis = <2000>; 4360 type = "passive"; 4361 }; 4362 4363 cpu7_alert1: trip-point1 { 4364 temperature = <95000>; 4365 hysteresis = <2000>; 4366 type = "passive"; 4367 }; 4368 4369 cpu7_crit: cpu_crit { 4370 temperature = <110000>; 4371 hysteresis = <1000>; 4372 type = "critical"; 4373 }; 4374 }; 4375 4376 cooling-maps { 4377 map0 { 4378 trip = <&cpu7_alert0>; 4379 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4380 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4381 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4382 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4383 }; 4384 map1 { 4385 trip = <&cpu7_alert1>; 4386 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4387 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4388 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4389 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4390 }; 4391 }; 4392 }; 4393 4394 aoss0-thermal { 4395 polling-delay-passive = <250>; 4396 polling-delay = <1000>; 4397 4398 thermal-sensors = <&tsens0 0>; 4399 4400 trips { 4401 aoss0_alert0: trip-point0 { 4402 temperature = <90000>; 4403 hysteresis = <2000>; 4404 type = "hot"; 4405 }; 4406 }; 4407 }; 4408 4409 cluster0-thermal { 4410 polling-delay-passive = <250>; 4411 polling-delay = <1000>; 4412 4413 thermal-sensors = <&tsens0 5>; 4414 4415 trips { 4416 cluster0_alert0: trip-point0 { 4417 temperature = <90000>; 4418 hysteresis = <2000>; 4419 type = "hot"; 4420 }; 4421 cluster0_crit: cluster0_crit { 4422 temperature = <110000>; 4423 hysteresis = <2000>; 4424 type = "critical"; 4425 }; 4426 }; 4427 }; 4428 4429 cluster1-thermal { 4430 polling-delay-passive = <250>; 4431 polling-delay = <1000>; 4432 4433 thermal-sensors = <&tsens0 6>; 4434 4435 trips { 4436 cluster1_alert0: trip-point0 { 4437 temperature = <90000>; 4438 hysteresis = <2000>; 4439 type = "hot"; 4440 }; 4441 cluster1_crit: cluster1_crit { 4442 temperature = <110000>; 4443 hysteresis = <2000>; 4444 type = "critical"; 4445 }; 4446 }; 4447 }; 4448 4449 gpu-thermal-top { 4450 polling-delay-passive = <250>; 4451 polling-delay = <1000>; 4452 4453 thermal-sensors = <&tsens0 11>; 4454 4455 trips { 4456 gpu1_alert0: trip-point0 { 4457 temperature = <90000>; 4458 hysteresis = <2000>; 4459 type = "hot"; 4460 }; 4461 }; 4462 }; 4463 4464 gpu-thermal-bottom { 4465 polling-delay-passive = <250>; 4466 polling-delay = <1000>; 4467 4468 thermal-sensors = <&tsens0 12>; 4469 4470 trips { 4471 gpu2_alert0: trip-point0 { 4472 temperature = <90000>; 4473 hysteresis = <2000>; 4474 type = "hot"; 4475 }; 4476 }; 4477 }; 4478 4479 aoss1-thermal { 4480 polling-delay-passive = <250>; 4481 polling-delay = <1000>; 4482 4483 thermal-sensors = <&tsens1 0>; 4484 4485 trips { 4486 aoss1_alert0: trip-point0 { 4487 temperature = <90000>; 4488 hysteresis = <2000>; 4489 type = "hot"; 4490 }; 4491 }; 4492 }; 4493 4494 q6-modem-thermal { 4495 polling-delay-passive = <250>; 4496 polling-delay = <1000>; 4497 4498 thermal-sensors = <&tsens1 1>; 4499 4500 trips { 4501 q6_modem_alert0: trip-point0 { 4502 temperature = <90000>; 4503 hysteresis = <2000>; 4504 type = "hot"; 4505 }; 4506 }; 4507 }; 4508 4509 mem-thermal { 4510 polling-delay-passive = <250>; 4511 polling-delay = <1000>; 4512 4513 thermal-sensors = <&tsens1 2>; 4514 4515 trips { 4516 mem_alert0: trip-point0 { 4517 temperature = <90000>; 4518 hysteresis = <2000>; 4519 type = "hot"; 4520 }; 4521 }; 4522 }; 4523 4524 wlan-thermal { 4525 polling-delay-passive = <250>; 4526 polling-delay = <1000>; 4527 4528 thermal-sensors = <&tsens1 3>; 4529 4530 trips { 4531 wlan_alert0: trip-point0 { 4532 temperature = <90000>; 4533 hysteresis = <2000>; 4534 type = "hot"; 4535 }; 4536 }; 4537 }; 4538 4539 q6-hvx-thermal { 4540 polling-delay-passive = <250>; 4541 polling-delay = <1000>; 4542 4543 thermal-sensors = <&tsens1 4>; 4544 4545 trips { 4546 q6_hvx_alert0: trip-point0 { 4547 temperature = <90000>; 4548 hysteresis = <2000>; 4549 type = "hot"; 4550 }; 4551 }; 4552 }; 4553 4554 camera-thermal { 4555 polling-delay-passive = <250>; 4556 polling-delay = <1000>; 4557 4558 thermal-sensors = <&tsens1 5>; 4559 4560 trips { 4561 camera_alert0: trip-point0 { 4562 temperature = <90000>; 4563 hysteresis = <2000>; 4564 type = "hot"; 4565 }; 4566 }; 4567 }; 4568 4569 video-thermal { 4570 polling-delay-passive = <250>; 4571 polling-delay = <1000>; 4572 4573 thermal-sensors = <&tsens1 6>; 4574 4575 trips { 4576 video_alert0: trip-point0 { 4577 temperature = <90000>; 4578 hysteresis = <2000>; 4579 type = "hot"; 4580 }; 4581 }; 4582 }; 4583 4584 modem-thermal { 4585 polling-delay-passive = <250>; 4586 polling-delay = <1000>; 4587 4588 thermal-sensors = <&tsens1 7>; 4589 4590 trips { 4591 modem_alert0: trip-point0 { 4592 temperature = <90000>; 4593 hysteresis = <2000>; 4594 type = "hot"; 4595 }; 4596 }; 4597 }; 4598 }; 4599}; 4600