1// SPDX-License-Identifier: GPL-2.0 2/* 3 * SDM845 SoC device tree source 4 * 5 * Copyright (c) 2018, The Linux Foundation. All rights reserved. 6 */ 7 8#include <dt-bindings/clock/qcom,dispcc-sdm845.h> 9#include <dt-bindings/clock/qcom,gcc-sdm845.h> 10#include <dt-bindings/clock/qcom,gpucc-sdm845.h> 11#include <dt-bindings/clock/qcom,lpass-sdm845.h> 12#include <dt-bindings/clock/qcom,rpmh.h> 13#include <dt-bindings/clock/qcom,videocc-sdm845.h> 14#include <dt-bindings/interconnect/qcom,sdm845.h> 15#include <dt-bindings/interrupt-controller/arm-gic.h> 16#include <dt-bindings/phy/phy-qcom-qusb2.h> 17#include <dt-bindings/power/qcom-rpmpd.h> 18#include <dt-bindings/reset/qcom,sdm845-aoss.h> 19#include <dt-bindings/reset/qcom,sdm845-pdc.h> 20#include <dt-bindings/soc/qcom,apr.h> 21#include <dt-bindings/soc/qcom,rpmh-rsc.h> 22#include <dt-bindings/clock/qcom,gcc-sdm845.h> 23#include <dt-bindings/thermal/thermal.h> 24 25/ { 26 interrupt-parent = <&intc>; 27 28 #address-cells = <2>; 29 #size-cells = <2>; 30 31 aliases { 32 i2c0 = &i2c0; 33 i2c1 = &i2c1; 34 i2c2 = &i2c2; 35 i2c3 = &i2c3; 36 i2c4 = &i2c4; 37 i2c5 = &i2c5; 38 i2c6 = &i2c6; 39 i2c7 = &i2c7; 40 i2c8 = &i2c8; 41 i2c9 = &i2c9; 42 i2c10 = &i2c10; 43 i2c11 = &i2c11; 44 i2c12 = &i2c12; 45 i2c13 = &i2c13; 46 i2c14 = &i2c14; 47 i2c15 = &i2c15; 48 spi0 = &spi0; 49 spi1 = &spi1; 50 spi2 = &spi2; 51 spi3 = &spi3; 52 spi4 = &spi4; 53 spi5 = &spi5; 54 spi6 = &spi6; 55 spi7 = &spi7; 56 spi8 = &spi8; 57 spi9 = &spi9; 58 spi10 = &spi10; 59 spi11 = &spi11; 60 spi12 = &spi12; 61 spi13 = &spi13; 62 spi14 = &spi14; 63 spi15 = &spi15; 64 }; 65 66 chosen { }; 67 68 memory@80000000 { 69 device_type = "memory"; 70 /* We expect the bootloader to fill in the size */ 71 reg = <0 0x80000000 0 0>; 72 }; 73 74 reserved-memory { 75 #address-cells = <2>; 76 #size-cells = <2>; 77 ranges; 78 79 hyp_mem: memory@85700000 { 80 reg = <0 0x85700000 0 0x600000>; 81 no-map; 82 }; 83 84 xbl_mem: memory@85e00000 { 85 reg = <0 0x85e00000 0 0x100000>; 86 no-map; 87 }; 88 89 aop_mem: memory@85fc0000 { 90 reg = <0 0x85fc0000 0 0x20000>; 91 no-map; 92 }; 93 94 aop_cmd_db_mem: memory@85fe0000 { 95 compatible = "qcom,cmd-db"; 96 reg = <0x0 0x85fe0000 0 0x20000>; 97 no-map; 98 }; 99 100 smem_mem: memory@86000000 { 101 reg = <0x0 0x86000000 0 0x200000>; 102 no-map; 103 }; 104 105 tz_mem: memory@86200000 { 106 reg = <0 0x86200000 0 0x2d00000>; 107 no-map; 108 }; 109 110 rmtfs_mem: memory@88f00000 { 111 compatible = "qcom,rmtfs-mem"; 112 reg = <0 0x88f00000 0 0x200000>; 113 no-map; 114 115 qcom,client-id = <1>; 116 qcom,vmid = <15>; 117 }; 118 119 qseecom_mem: memory@8ab00000 { 120 reg = <0 0x8ab00000 0 0x1400000>; 121 no-map; 122 }; 123 124 camera_mem: memory@8bf00000 { 125 reg = <0 0x8bf00000 0 0x500000>; 126 no-map; 127 }; 128 129 ipa_fw_mem: memory@8c400000 { 130 reg = <0 0x8c400000 0 0x10000>; 131 no-map; 132 }; 133 134 ipa_gsi_mem: memory@8c410000 { 135 reg = <0 0x8c410000 0 0x5000>; 136 no-map; 137 }; 138 139 gpu_mem: memory@8c415000 { 140 reg = <0 0x8c415000 0 0x2000>; 141 no-map; 142 }; 143 144 adsp_mem: memory@8c500000 { 145 reg = <0 0x8c500000 0 0x1a00000>; 146 no-map; 147 }; 148 149 wlan_msa_mem: memory@8df00000 { 150 reg = <0 0x8df00000 0 0x100000>; 151 no-map; 152 }; 153 154 mpss_region: memory@8e000000 { 155 reg = <0 0x8e000000 0 0x7800000>; 156 no-map; 157 }; 158 159 venus_mem: memory@95800000 { 160 reg = <0 0x95800000 0 0x500000>; 161 no-map; 162 }; 163 164 cdsp_mem: memory@95d00000 { 165 reg = <0 0x95d00000 0 0x800000>; 166 no-map; 167 }; 168 169 mba_region: memory@96500000 { 170 reg = <0 0x96500000 0 0x200000>; 171 no-map; 172 }; 173 174 slpi_mem: memory@96700000 { 175 reg = <0 0x96700000 0 0x1400000>; 176 no-map; 177 }; 178 179 spss_mem: memory@97b00000 { 180 reg = <0 0x97b00000 0 0x100000>; 181 no-map; 182 }; 183 }; 184 185 cpus { 186 #address-cells = <2>; 187 #size-cells = <0>; 188 189 CPU0: cpu@0 { 190 device_type = "cpu"; 191 compatible = "qcom,kryo385"; 192 reg = <0x0 0x0>; 193 enable-method = "psci"; 194 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 195 &LITTLE_CPU_SLEEP_1 196 &CLUSTER_SLEEP_0>; 197 capacity-dmips-mhz = <607>; 198 dynamic-power-coefficient = <100>; 199 qcom,freq-domain = <&cpufreq_hw 0>; 200 #cooling-cells = <2>; 201 next-level-cache = <&L2_0>; 202 L2_0: l2-cache { 203 compatible = "cache"; 204 next-level-cache = <&L3_0>; 205 L3_0: l3-cache { 206 compatible = "cache"; 207 }; 208 }; 209 }; 210 211 CPU1: cpu@100 { 212 device_type = "cpu"; 213 compatible = "qcom,kryo385"; 214 reg = <0x0 0x100>; 215 enable-method = "psci"; 216 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 217 &LITTLE_CPU_SLEEP_1 218 &CLUSTER_SLEEP_0>; 219 capacity-dmips-mhz = <607>; 220 dynamic-power-coefficient = <100>; 221 qcom,freq-domain = <&cpufreq_hw 0>; 222 #cooling-cells = <2>; 223 next-level-cache = <&L2_100>; 224 L2_100: l2-cache { 225 compatible = "cache"; 226 next-level-cache = <&L3_0>; 227 }; 228 }; 229 230 CPU2: cpu@200 { 231 device_type = "cpu"; 232 compatible = "qcom,kryo385"; 233 reg = <0x0 0x200>; 234 enable-method = "psci"; 235 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 236 &LITTLE_CPU_SLEEP_1 237 &CLUSTER_SLEEP_0>; 238 capacity-dmips-mhz = <607>; 239 dynamic-power-coefficient = <100>; 240 qcom,freq-domain = <&cpufreq_hw 0>; 241 #cooling-cells = <2>; 242 next-level-cache = <&L2_200>; 243 L2_200: l2-cache { 244 compatible = "cache"; 245 next-level-cache = <&L3_0>; 246 }; 247 }; 248 249 CPU3: cpu@300 { 250 device_type = "cpu"; 251 compatible = "qcom,kryo385"; 252 reg = <0x0 0x300>; 253 enable-method = "psci"; 254 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 255 &LITTLE_CPU_SLEEP_1 256 &CLUSTER_SLEEP_0>; 257 capacity-dmips-mhz = <607>; 258 dynamic-power-coefficient = <100>; 259 qcom,freq-domain = <&cpufreq_hw 0>; 260 #cooling-cells = <2>; 261 next-level-cache = <&L2_300>; 262 L2_300: l2-cache { 263 compatible = "cache"; 264 next-level-cache = <&L3_0>; 265 }; 266 }; 267 268 CPU4: cpu@400 { 269 device_type = "cpu"; 270 compatible = "qcom,kryo385"; 271 reg = <0x0 0x400>; 272 enable-method = "psci"; 273 capacity-dmips-mhz = <1024>; 274 cpu-idle-states = <&BIG_CPU_SLEEP_0 275 &BIG_CPU_SLEEP_1 276 &CLUSTER_SLEEP_0>; 277 dynamic-power-coefficient = <396>; 278 qcom,freq-domain = <&cpufreq_hw 1>; 279 #cooling-cells = <2>; 280 next-level-cache = <&L2_400>; 281 L2_400: l2-cache { 282 compatible = "cache"; 283 next-level-cache = <&L3_0>; 284 }; 285 }; 286 287 CPU5: cpu@500 { 288 device_type = "cpu"; 289 compatible = "qcom,kryo385"; 290 reg = <0x0 0x500>; 291 enable-method = "psci"; 292 capacity-dmips-mhz = <1024>; 293 cpu-idle-states = <&BIG_CPU_SLEEP_0 294 &BIG_CPU_SLEEP_1 295 &CLUSTER_SLEEP_0>; 296 dynamic-power-coefficient = <396>; 297 qcom,freq-domain = <&cpufreq_hw 1>; 298 #cooling-cells = <2>; 299 next-level-cache = <&L2_500>; 300 L2_500: l2-cache { 301 compatible = "cache"; 302 next-level-cache = <&L3_0>; 303 }; 304 }; 305 306 CPU6: cpu@600 { 307 device_type = "cpu"; 308 compatible = "qcom,kryo385"; 309 reg = <0x0 0x600>; 310 enable-method = "psci"; 311 capacity-dmips-mhz = <1024>; 312 cpu-idle-states = <&BIG_CPU_SLEEP_0 313 &BIG_CPU_SLEEP_1 314 &CLUSTER_SLEEP_0>; 315 dynamic-power-coefficient = <396>; 316 qcom,freq-domain = <&cpufreq_hw 1>; 317 #cooling-cells = <2>; 318 next-level-cache = <&L2_600>; 319 L2_600: l2-cache { 320 compatible = "cache"; 321 next-level-cache = <&L3_0>; 322 }; 323 }; 324 325 CPU7: cpu@700 { 326 device_type = "cpu"; 327 compatible = "qcom,kryo385"; 328 reg = <0x0 0x700>; 329 enable-method = "psci"; 330 capacity-dmips-mhz = <1024>; 331 cpu-idle-states = <&BIG_CPU_SLEEP_0 332 &BIG_CPU_SLEEP_1 333 &CLUSTER_SLEEP_0>; 334 dynamic-power-coefficient = <396>; 335 qcom,freq-domain = <&cpufreq_hw 1>; 336 #cooling-cells = <2>; 337 next-level-cache = <&L2_700>; 338 L2_700: l2-cache { 339 compatible = "cache"; 340 next-level-cache = <&L3_0>; 341 }; 342 }; 343 344 cpu-map { 345 cluster0 { 346 core0 { 347 cpu = <&CPU0>; 348 }; 349 350 core1 { 351 cpu = <&CPU1>; 352 }; 353 354 core2 { 355 cpu = <&CPU2>; 356 }; 357 358 core3 { 359 cpu = <&CPU3>; 360 }; 361 362 core4 { 363 cpu = <&CPU4>; 364 }; 365 366 core5 { 367 cpu = <&CPU5>; 368 }; 369 370 core6 { 371 cpu = <&CPU6>; 372 }; 373 374 core7 { 375 cpu = <&CPU7>; 376 }; 377 }; 378 }; 379 380 idle-states { 381 entry-method = "psci"; 382 383 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 384 compatible = "arm,idle-state"; 385 idle-state-name = "little-power-down"; 386 arm,psci-suspend-param = <0x40000003>; 387 entry-latency-us = <350>; 388 exit-latency-us = <461>; 389 min-residency-us = <1890>; 390 local-timer-stop; 391 }; 392 393 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 394 compatible = "arm,idle-state"; 395 idle-state-name = "little-rail-power-down"; 396 arm,psci-suspend-param = <0x40000004>; 397 entry-latency-us = <360>; 398 exit-latency-us = <531>; 399 min-residency-us = <3934>; 400 local-timer-stop; 401 }; 402 403 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 404 compatible = "arm,idle-state"; 405 idle-state-name = "big-power-down"; 406 arm,psci-suspend-param = <0x40000003>; 407 entry-latency-us = <264>; 408 exit-latency-us = <621>; 409 min-residency-us = <952>; 410 local-timer-stop; 411 }; 412 413 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 414 compatible = "arm,idle-state"; 415 idle-state-name = "big-rail-power-down"; 416 arm,psci-suspend-param = <0x40000004>; 417 entry-latency-us = <702>; 418 exit-latency-us = <1061>; 419 min-residency-us = <4488>; 420 local-timer-stop; 421 }; 422 423 CLUSTER_SLEEP_0: cluster-sleep-0 { 424 compatible = "arm,idle-state"; 425 idle-state-name = "cluster-power-down"; 426 arm,psci-suspend-param = <0x400000F4>; 427 entry-latency-us = <3263>; 428 exit-latency-us = <6562>; 429 min-residency-us = <9987>; 430 local-timer-stop; 431 }; 432 }; 433 }; 434 435 pmu { 436 compatible = "arm,armv8-pmuv3"; 437 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; 438 }; 439 440 timer { 441 compatible = "arm,armv8-timer"; 442 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 443 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 444 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 445 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 446 }; 447 448 clocks { 449 xo_board: xo-board { 450 compatible = "fixed-clock"; 451 #clock-cells = <0>; 452 clock-frequency = <38400000>; 453 clock-output-names = "xo_board"; 454 }; 455 456 sleep_clk: sleep-clk { 457 compatible = "fixed-clock"; 458 #clock-cells = <0>; 459 clock-frequency = <32764>; 460 }; 461 }; 462 463 firmware { 464 scm { 465 compatible = "qcom,scm-sdm845", "qcom,scm"; 466 }; 467 }; 468 469 adsp_pas: remoteproc-adsp { 470 compatible = "qcom,sdm845-adsp-pas"; 471 472 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 473 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 474 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 475 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 476 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 477 interrupt-names = "wdog", "fatal", "ready", 478 "handover", "stop-ack"; 479 480 clocks = <&rpmhcc RPMH_CXO_CLK>; 481 clock-names = "xo"; 482 483 memory-region = <&adsp_mem>; 484 485 qcom,smem-states = <&adsp_smp2p_out 0>; 486 qcom,smem-state-names = "stop"; 487 488 status = "disabled"; 489 490 glink-edge { 491 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 492 label = "lpass"; 493 qcom,remote-pid = <2>; 494 mboxes = <&apss_shared 8>; 495 496 apr { 497 compatible = "qcom,apr-v2"; 498 qcom,glink-channels = "apr_audio_svc"; 499 qcom,apr-domain = <APR_DOMAIN_ADSP>; 500 #address-cells = <1>; 501 #size-cells = <0>; 502 qcom,intents = <512 20>; 503 504 apr-service@3 { 505 reg = <APR_SVC_ADSP_CORE>; 506 compatible = "qcom,q6core"; 507 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 508 }; 509 510 q6afe: apr-service@4 { 511 compatible = "qcom,q6afe"; 512 reg = <APR_SVC_AFE>; 513 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 514 q6afedai: dais { 515 compatible = "qcom,q6afe-dais"; 516 #address-cells = <1>; 517 #size-cells = <0>; 518 #sound-dai-cells = <1>; 519 }; 520 }; 521 522 q6asm: apr-service@7 { 523 compatible = "qcom,q6asm"; 524 reg = <APR_SVC_ASM>; 525 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 526 q6asmdai: dais { 527 compatible = "qcom,q6asm-dais"; 528 #address-cells = <1>; 529 #size-cells = <0>; 530 #sound-dai-cells = <1>; 531 iommus = <&apps_smmu 0x1821 0x0>; 532 }; 533 }; 534 535 q6adm: apr-service@8 { 536 compatible = "qcom,q6adm"; 537 reg = <APR_SVC_ADM>; 538 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 539 q6routing: routing { 540 compatible = "qcom,q6adm-routing"; 541 #sound-dai-cells = <0>; 542 }; 543 }; 544 }; 545 546 fastrpc { 547 compatible = "qcom,fastrpc"; 548 qcom,glink-channels = "fastrpcglink-apps-dsp"; 549 label = "adsp"; 550 #address-cells = <1>; 551 #size-cells = <0>; 552 553 compute-cb@3 { 554 compatible = "qcom,fastrpc-compute-cb"; 555 reg = <3>; 556 iommus = <&apps_smmu 0x1823 0x0>; 557 }; 558 559 compute-cb@4 { 560 compatible = "qcom,fastrpc-compute-cb"; 561 reg = <4>; 562 iommus = <&apps_smmu 0x1824 0x0>; 563 }; 564 }; 565 }; 566 }; 567 568 cdsp_pas: remoteproc-cdsp { 569 compatible = "qcom,sdm845-cdsp-pas"; 570 571 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 572 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 573 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 574 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 575 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 576 interrupt-names = "wdog", "fatal", "ready", 577 "handover", "stop-ack"; 578 579 clocks = <&rpmhcc RPMH_CXO_CLK>; 580 clock-names = "xo"; 581 582 memory-region = <&cdsp_mem>; 583 584 qcom,smem-states = <&cdsp_smp2p_out 0>; 585 qcom,smem-state-names = "stop"; 586 587 status = "disabled"; 588 589 glink-edge { 590 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>; 591 label = "turing"; 592 qcom,remote-pid = <5>; 593 mboxes = <&apss_shared 4>; 594 fastrpc { 595 compatible = "qcom,fastrpc"; 596 qcom,glink-channels = "fastrpcglink-apps-dsp"; 597 label = "cdsp"; 598 #address-cells = <1>; 599 #size-cells = <0>; 600 601 compute-cb@1 { 602 compatible = "qcom,fastrpc-compute-cb"; 603 reg = <1>; 604 iommus = <&apps_smmu 0x1401 0x30>; 605 }; 606 607 compute-cb@2 { 608 compatible = "qcom,fastrpc-compute-cb"; 609 reg = <2>; 610 iommus = <&apps_smmu 0x1402 0x30>; 611 }; 612 613 compute-cb@3 { 614 compatible = "qcom,fastrpc-compute-cb"; 615 reg = <3>; 616 iommus = <&apps_smmu 0x1403 0x30>; 617 }; 618 619 compute-cb@4 { 620 compatible = "qcom,fastrpc-compute-cb"; 621 reg = <4>; 622 iommus = <&apps_smmu 0x1404 0x30>; 623 }; 624 625 compute-cb@5 { 626 compatible = "qcom,fastrpc-compute-cb"; 627 reg = <5>; 628 iommus = <&apps_smmu 0x1405 0x30>; 629 }; 630 631 compute-cb@6 { 632 compatible = "qcom,fastrpc-compute-cb"; 633 reg = <6>; 634 iommus = <&apps_smmu 0x1406 0x30>; 635 }; 636 637 compute-cb@7 { 638 compatible = "qcom,fastrpc-compute-cb"; 639 reg = <7>; 640 iommus = <&apps_smmu 0x1407 0x30>; 641 }; 642 643 compute-cb@8 { 644 compatible = "qcom,fastrpc-compute-cb"; 645 reg = <8>; 646 iommus = <&apps_smmu 0x1408 0x30>; 647 }; 648 }; 649 }; 650 }; 651 652 tcsr_mutex: hwlock { 653 compatible = "qcom,tcsr-mutex"; 654 syscon = <&tcsr_mutex_regs 0 0x1000>; 655 #hwlock-cells = <1>; 656 }; 657 658 smem { 659 compatible = "qcom,smem"; 660 memory-region = <&smem_mem>; 661 hwlocks = <&tcsr_mutex 3>; 662 }; 663 664 smp2p-cdsp { 665 compatible = "qcom,smp2p"; 666 qcom,smem = <94>, <432>; 667 668 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; 669 670 mboxes = <&apss_shared 6>; 671 672 qcom,local-pid = <0>; 673 qcom,remote-pid = <5>; 674 675 cdsp_smp2p_out: master-kernel { 676 qcom,entry-name = "master-kernel"; 677 #qcom,smem-state-cells = <1>; 678 }; 679 680 cdsp_smp2p_in: slave-kernel { 681 qcom,entry-name = "slave-kernel"; 682 683 interrupt-controller; 684 #interrupt-cells = <2>; 685 }; 686 }; 687 688 smp2p-lpass { 689 compatible = "qcom,smp2p"; 690 qcom,smem = <443>, <429>; 691 692 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 693 694 mboxes = <&apss_shared 10>; 695 696 qcom,local-pid = <0>; 697 qcom,remote-pid = <2>; 698 699 adsp_smp2p_out: master-kernel { 700 qcom,entry-name = "master-kernel"; 701 #qcom,smem-state-cells = <1>; 702 }; 703 704 adsp_smp2p_in: slave-kernel { 705 qcom,entry-name = "slave-kernel"; 706 707 interrupt-controller; 708 #interrupt-cells = <2>; 709 }; 710 }; 711 712 smp2p-mpss { 713 compatible = "qcom,smp2p"; 714 qcom,smem = <435>, <428>; 715 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 716 mboxes = <&apss_shared 14>; 717 qcom,local-pid = <0>; 718 qcom,remote-pid = <1>; 719 720 modem_smp2p_out: master-kernel { 721 qcom,entry-name = "master-kernel"; 722 #qcom,smem-state-cells = <1>; 723 }; 724 725 modem_smp2p_in: slave-kernel { 726 qcom,entry-name = "slave-kernel"; 727 interrupt-controller; 728 #interrupt-cells = <2>; 729 }; 730 731 ipa_smp2p_out: ipa-ap-to-modem { 732 qcom,entry-name = "ipa"; 733 #qcom,smem-state-cells = <1>; 734 }; 735 736 ipa_smp2p_in: ipa-modem-to-ap { 737 qcom,entry-name = "ipa"; 738 interrupt-controller; 739 #interrupt-cells = <2>; 740 }; 741 }; 742 743 smp2p-slpi { 744 compatible = "qcom,smp2p"; 745 qcom,smem = <481>, <430>; 746 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>; 747 mboxes = <&apss_shared 26>; 748 qcom,local-pid = <0>; 749 qcom,remote-pid = <3>; 750 751 slpi_smp2p_out: master-kernel { 752 qcom,entry-name = "master-kernel"; 753 #qcom,smem-state-cells = <1>; 754 }; 755 756 slpi_smp2p_in: slave-kernel { 757 qcom,entry-name = "slave-kernel"; 758 interrupt-controller; 759 #interrupt-cells = <2>; 760 }; 761 }; 762 763 psci { 764 compatible = "arm,psci-1.0"; 765 method = "smc"; 766 }; 767 768 soc: soc@0 { 769 #address-cells = <2>; 770 #size-cells = <2>; 771 ranges = <0 0 0 0 0x10 0>; 772 dma-ranges = <0 0 0 0 0x10 0>; 773 compatible = "simple-bus"; 774 775 gcc: clock-controller@100000 { 776 compatible = "qcom,gcc-sdm845"; 777 reg = <0 0x00100000 0 0x1f0000>; 778 #clock-cells = <1>; 779 #reset-cells = <1>; 780 #power-domain-cells = <1>; 781 }; 782 783 qfprom@784000 { 784 compatible = "qcom,qfprom"; 785 reg = <0 0x00784000 0 0x8ff>; 786 #address-cells = <1>; 787 #size-cells = <1>; 788 789 qusb2p_hstx_trim: hstx-trim-primary@1eb { 790 reg = <0x1eb 0x1>; 791 bits = <1 4>; 792 }; 793 794 qusb2s_hstx_trim: hstx-trim-secondary@1eb { 795 reg = <0x1eb 0x2>; 796 bits = <6 4>; 797 }; 798 }; 799 800 rng: rng@793000 { 801 compatible = "qcom,prng-ee"; 802 reg = <0 0x00793000 0 0x1000>; 803 clocks = <&gcc GCC_PRNG_AHB_CLK>; 804 clock-names = "core"; 805 }; 806 807 qupv3_id_0: geniqup@8c0000 { 808 compatible = "qcom,geni-se-qup"; 809 reg = <0 0x008c0000 0 0x6000>; 810 clock-names = "m-ahb", "s-ahb"; 811 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 812 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 813 #address-cells = <2>; 814 #size-cells = <2>; 815 ranges; 816 status = "disabled"; 817 818 i2c0: i2c@880000 { 819 compatible = "qcom,geni-i2c"; 820 reg = <0 0x00880000 0 0x4000>; 821 clock-names = "se"; 822 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 823 pinctrl-names = "default"; 824 pinctrl-0 = <&qup_i2c0_default>; 825 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 826 #address-cells = <1>; 827 #size-cells = <0>; 828 status = "disabled"; 829 }; 830 831 spi0: spi@880000 { 832 compatible = "qcom,geni-spi"; 833 reg = <0 0x00880000 0 0x4000>; 834 clock-names = "se"; 835 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 836 pinctrl-names = "default"; 837 pinctrl-0 = <&qup_spi0_default>; 838 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 839 #address-cells = <1>; 840 #size-cells = <0>; 841 status = "disabled"; 842 }; 843 844 uart0: serial@880000 { 845 compatible = "qcom,geni-uart"; 846 reg = <0 0x00880000 0 0x4000>; 847 clock-names = "se"; 848 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 849 pinctrl-names = "default"; 850 pinctrl-0 = <&qup_uart0_default>; 851 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 852 status = "disabled"; 853 }; 854 855 i2c1: i2c@884000 { 856 compatible = "qcom,geni-i2c"; 857 reg = <0 0x00884000 0 0x4000>; 858 clock-names = "se"; 859 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 860 pinctrl-names = "default"; 861 pinctrl-0 = <&qup_i2c1_default>; 862 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 863 #address-cells = <1>; 864 #size-cells = <0>; 865 status = "disabled"; 866 }; 867 868 spi1: spi@884000 { 869 compatible = "qcom,geni-spi"; 870 reg = <0 0x00884000 0 0x4000>; 871 clock-names = "se"; 872 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 873 pinctrl-names = "default"; 874 pinctrl-0 = <&qup_spi1_default>; 875 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 876 #address-cells = <1>; 877 #size-cells = <0>; 878 status = "disabled"; 879 }; 880 881 uart1: serial@884000 { 882 compatible = "qcom,geni-uart"; 883 reg = <0 0x00884000 0 0x4000>; 884 clock-names = "se"; 885 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 886 pinctrl-names = "default"; 887 pinctrl-0 = <&qup_uart1_default>; 888 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 889 status = "disabled"; 890 }; 891 892 i2c2: i2c@888000 { 893 compatible = "qcom,geni-i2c"; 894 reg = <0 0x00888000 0 0x4000>; 895 clock-names = "se"; 896 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 897 pinctrl-names = "default"; 898 pinctrl-0 = <&qup_i2c2_default>; 899 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 900 #address-cells = <1>; 901 #size-cells = <0>; 902 status = "disabled"; 903 }; 904 905 spi2: spi@888000 { 906 compatible = "qcom,geni-spi"; 907 reg = <0 0x00888000 0 0x4000>; 908 clock-names = "se"; 909 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 910 pinctrl-names = "default"; 911 pinctrl-0 = <&qup_spi2_default>; 912 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 913 #address-cells = <1>; 914 #size-cells = <0>; 915 status = "disabled"; 916 }; 917 918 uart2: serial@888000 { 919 compatible = "qcom,geni-uart"; 920 reg = <0 0x00888000 0 0x4000>; 921 clock-names = "se"; 922 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 923 pinctrl-names = "default"; 924 pinctrl-0 = <&qup_uart2_default>; 925 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 926 status = "disabled"; 927 }; 928 929 i2c3: i2c@88c000 { 930 compatible = "qcom,geni-i2c"; 931 reg = <0 0x0088c000 0 0x4000>; 932 clock-names = "se"; 933 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 934 pinctrl-names = "default"; 935 pinctrl-0 = <&qup_i2c3_default>; 936 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 937 #address-cells = <1>; 938 #size-cells = <0>; 939 status = "disabled"; 940 }; 941 942 spi3: spi@88c000 { 943 compatible = "qcom,geni-spi"; 944 reg = <0 0x0088c000 0 0x4000>; 945 clock-names = "se"; 946 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 947 pinctrl-names = "default"; 948 pinctrl-0 = <&qup_spi3_default>; 949 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 950 #address-cells = <1>; 951 #size-cells = <0>; 952 status = "disabled"; 953 }; 954 955 uart3: serial@88c000 { 956 compatible = "qcom,geni-uart"; 957 reg = <0 0x0088c000 0 0x4000>; 958 clock-names = "se"; 959 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 960 pinctrl-names = "default"; 961 pinctrl-0 = <&qup_uart3_default>; 962 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 963 status = "disabled"; 964 }; 965 966 i2c4: i2c@890000 { 967 compatible = "qcom,geni-i2c"; 968 reg = <0 0x00890000 0 0x4000>; 969 clock-names = "se"; 970 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 971 pinctrl-names = "default"; 972 pinctrl-0 = <&qup_i2c4_default>; 973 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 974 #address-cells = <1>; 975 #size-cells = <0>; 976 status = "disabled"; 977 }; 978 979 spi4: spi@890000 { 980 compatible = "qcom,geni-spi"; 981 reg = <0 0x00890000 0 0x4000>; 982 clock-names = "se"; 983 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 984 pinctrl-names = "default"; 985 pinctrl-0 = <&qup_spi4_default>; 986 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 987 #address-cells = <1>; 988 #size-cells = <0>; 989 status = "disabled"; 990 }; 991 992 uart4: serial@890000 { 993 compatible = "qcom,geni-uart"; 994 reg = <0 0x00890000 0 0x4000>; 995 clock-names = "se"; 996 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 997 pinctrl-names = "default"; 998 pinctrl-0 = <&qup_uart4_default>; 999 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1000 status = "disabled"; 1001 }; 1002 1003 i2c5: i2c@894000 { 1004 compatible = "qcom,geni-i2c"; 1005 reg = <0 0x00894000 0 0x4000>; 1006 clock-names = "se"; 1007 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1008 pinctrl-names = "default"; 1009 pinctrl-0 = <&qup_i2c5_default>; 1010 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1011 #address-cells = <1>; 1012 #size-cells = <0>; 1013 status = "disabled"; 1014 }; 1015 1016 spi5: spi@894000 { 1017 compatible = "qcom,geni-spi"; 1018 reg = <0 0x00894000 0 0x4000>; 1019 clock-names = "se"; 1020 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1021 pinctrl-names = "default"; 1022 pinctrl-0 = <&qup_spi5_default>; 1023 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1024 #address-cells = <1>; 1025 #size-cells = <0>; 1026 status = "disabled"; 1027 }; 1028 1029 uart5: serial@894000 { 1030 compatible = "qcom,geni-uart"; 1031 reg = <0 0x00894000 0 0x4000>; 1032 clock-names = "se"; 1033 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1034 pinctrl-names = "default"; 1035 pinctrl-0 = <&qup_uart5_default>; 1036 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1037 status = "disabled"; 1038 }; 1039 1040 i2c6: i2c@898000 { 1041 compatible = "qcom,geni-i2c"; 1042 reg = <0 0x00898000 0 0x4000>; 1043 clock-names = "se"; 1044 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1045 pinctrl-names = "default"; 1046 pinctrl-0 = <&qup_i2c6_default>; 1047 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1048 #address-cells = <1>; 1049 #size-cells = <0>; 1050 status = "disabled"; 1051 }; 1052 1053 spi6: spi@898000 { 1054 compatible = "qcom,geni-spi"; 1055 reg = <0 0x00898000 0 0x4000>; 1056 clock-names = "se"; 1057 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1058 pinctrl-names = "default"; 1059 pinctrl-0 = <&qup_spi6_default>; 1060 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1061 #address-cells = <1>; 1062 #size-cells = <0>; 1063 status = "disabled"; 1064 }; 1065 1066 uart6: serial@898000 { 1067 compatible = "qcom,geni-uart"; 1068 reg = <0 0x00898000 0 0x4000>; 1069 clock-names = "se"; 1070 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1071 pinctrl-names = "default"; 1072 pinctrl-0 = <&qup_uart6_default>; 1073 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1074 status = "disabled"; 1075 }; 1076 1077 i2c7: i2c@89c000 { 1078 compatible = "qcom,geni-i2c"; 1079 reg = <0 0x0089c000 0 0x4000>; 1080 clock-names = "se"; 1081 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1082 pinctrl-names = "default"; 1083 pinctrl-0 = <&qup_i2c7_default>; 1084 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1085 #address-cells = <1>; 1086 #size-cells = <0>; 1087 status = "disabled"; 1088 }; 1089 1090 spi7: spi@89c000 { 1091 compatible = "qcom,geni-spi"; 1092 reg = <0 0x0089c000 0 0x4000>; 1093 clock-names = "se"; 1094 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1095 pinctrl-names = "default"; 1096 pinctrl-0 = <&qup_spi7_default>; 1097 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1098 #address-cells = <1>; 1099 #size-cells = <0>; 1100 status = "disabled"; 1101 }; 1102 1103 uart7: serial@89c000 { 1104 compatible = "qcom,geni-uart"; 1105 reg = <0 0x0089c000 0 0x4000>; 1106 clock-names = "se"; 1107 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1108 pinctrl-names = "default"; 1109 pinctrl-0 = <&qup_uart7_default>; 1110 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1111 status = "disabled"; 1112 }; 1113 }; 1114 1115 qupv3_id_1: geniqup@ac0000 { 1116 compatible = "qcom,geni-se-qup"; 1117 reg = <0 0x00ac0000 0 0x6000>; 1118 clock-names = "m-ahb", "s-ahb"; 1119 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1120 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1121 #address-cells = <2>; 1122 #size-cells = <2>; 1123 ranges; 1124 status = "disabled"; 1125 1126 i2c8: i2c@a80000 { 1127 compatible = "qcom,geni-i2c"; 1128 reg = <0 0x00a80000 0 0x4000>; 1129 clock-names = "se"; 1130 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1131 pinctrl-names = "default"; 1132 pinctrl-0 = <&qup_i2c8_default>; 1133 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1134 #address-cells = <1>; 1135 #size-cells = <0>; 1136 status = "disabled"; 1137 }; 1138 1139 spi8: spi@a80000 { 1140 compatible = "qcom,geni-spi"; 1141 reg = <0 0x00a80000 0 0x4000>; 1142 clock-names = "se"; 1143 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1144 pinctrl-names = "default"; 1145 pinctrl-0 = <&qup_spi8_default>; 1146 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1147 #address-cells = <1>; 1148 #size-cells = <0>; 1149 status = "disabled"; 1150 }; 1151 1152 uart8: serial@a80000 { 1153 compatible = "qcom,geni-uart"; 1154 reg = <0 0x00a80000 0 0x4000>; 1155 clock-names = "se"; 1156 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1157 pinctrl-names = "default"; 1158 pinctrl-0 = <&qup_uart8_default>; 1159 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1160 status = "disabled"; 1161 }; 1162 1163 i2c9: i2c@a84000 { 1164 compatible = "qcom,geni-i2c"; 1165 reg = <0 0x00a84000 0 0x4000>; 1166 clock-names = "se"; 1167 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1168 pinctrl-names = "default"; 1169 pinctrl-0 = <&qup_i2c9_default>; 1170 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1171 #address-cells = <1>; 1172 #size-cells = <0>; 1173 status = "disabled"; 1174 }; 1175 1176 spi9: spi@a84000 { 1177 compatible = "qcom,geni-spi"; 1178 reg = <0 0x00a84000 0 0x4000>; 1179 clock-names = "se"; 1180 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1181 pinctrl-names = "default"; 1182 pinctrl-0 = <&qup_spi9_default>; 1183 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1184 #address-cells = <1>; 1185 #size-cells = <0>; 1186 status = "disabled"; 1187 }; 1188 1189 uart9: serial@a84000 { 1190 compatible = "qcom,geni-debug-uart"; 1191 reg = <0 0x00a84000 0 0x4000>; 1192 clock-names = "se"; 1193 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1194 pinctrl-names = "default"; 1195 pinctrl-0 = <&qup_uart9_default>; 1196 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1197 status = "disabled"; 1198 }; 1199 1200 i2c10: i2c@a88000 { 1201 compatible = "qcom,geni-i2c"; 1202 reg = <0 0x00a88000 0 0x4000>; 1203 clock-names = "se"; 1204 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1205 pinctrl-names = "default"; 1206 pinctrl-0 = <&qup_i2c10_default>; 1207 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1208 #address-cells = <1>; 1209 #size-cells = <0>; 1210 status = "disabled"; 1211 }; 1212 1213 spi10: spi@a88000 { 1214 compatible = "qcom,geni-spi"; 1215 reg = <0 0x00a88000 0 0x4000>; 1216 clock-names = "se"; 1217 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1218 pinctrl-names = "default"; 1219 pinctrl-0 = <&qup_spi10_default>; 1220 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1221 #address-cells = <1>; 1222 #size-cells = <0>; 1223 status = "disabled"; 1224 }; 1225 1226 uart10: serial@a88000 { 1227 compatible = "qcom,geni-uart"; 1228 reg = <0 0x00a88000 0 0x4000>; 1229 clock-names = "se"; 1230 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1231 pinctrl-names = "default"; 1232 pinctrl-0 = <&qup_uart10_default>; 1233 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1234 status = "disabled"; 1235 }; 1236 1237 i2c11: i2c@a8c000 { 1238 compatible = "qcom,geni-i2c"; 1239 reg = <0 0x00a8c000 0 0x4000>; 1240 clock-names = "se"; 1241 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1242 pinctrl-names = "default"; 1243 pinctrl-0 = <&qup_i2c11_default>; 1244 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1245 #address-cells = <1>; 1246 #size-cells = <0>; 1247 status = "disabled"; 1248 }; 1249 1250 spi11: spi@a8c000 { 1251 compatible = "qcom,geni-spi"; 1252 reg = <0 0x00a8c000 0 0x4000>; 1253 clock-names = "se"; 1254 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1255 pinctrl-names = "default"; 1256 pinctrl-0 = <&qup_spi11_default>; 1257 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1258 #address-cells = <1>; 1259 #size-cells = <0>; 1260 status = "disabled"; 1261 }; 1262 1263 uart11: serial@a8c000 { 1264 compatible = "qcom,geni-uart"; 1265 reg = <0 0x00a8c000 0 0x4000>; 1266 clock-names = "se"; 1267 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1268 pinctrl-names = "default"; 1269 pinctrl-0 = <&qup_uart11_default>; 1270 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1271 status = "disabled"; 1272 }; 1273 1274 i2c12: i2c@a90000 { 1275 compatible = "qcom,geni-i2c"; 1276 reg = <0 0x00a90000 0 0x4000>; 1277 clock-names = "se"; 1278 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1279 pinctrl-names = "default"; 1280 pinctrl-0 = <&qup_i2c12_default>; 1281 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1282 #address-cells = <1>; 1283 #size-cells = <0>; 1284 status = "disabled"; 1285 }; 1286 1287 spi12: spi@a90000 { 1288 compatible = "qcom,geni-spi"; 1289 reg = <0 0x00a90000 0 0x4000>; 1290 clock-names = "se"; 1291 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1292 pinctrl-names = "default"; 1293 pinctrl-0 = <&qup_spi12_default>; 1294 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1295 #address-cells = <1>; 1296 #size-cells = <0>; 1297 status = "disabled"; 1298 }; 1299 1300 uart12: serial@a90000 { 1301 compatible = "qcom,geni-uart"; 1302 reg = <0 0x00a90000 0 0x4000>; 1303 clock-names = "se"; 1304 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1305 pinctrl-names = "default"; 1306 pinctrl-0 = <&qup_uart12_default>; 1307 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1308 status = "disabled"; 1309 }; 1310 1311 i2c13: i2c@a94000 { 1312 compatible = "qcom,geni-i2c"; 1313 reg = <0 0x00a94000 0 0x4000>; 1314 clock-names = "se"; 1315 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1316 pinctrl-names = "default"; 1317 pinctrl-0 = <&qup_i2c13_default>; 1318 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1319 #address-cells = <1>; 1320 #size-cells = <0>; 1321 status = "disabled"; 1322 }; 1323 1324 spi13: spi@a94000 { 1325 compatible = "qcom,geni-spi"; 1326 reg = <0 0x00a94000 0 0x4000>; 1327 clock-names = "se"; 1328 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1329 pinctrl-names = "default"; 1330 pinctrl-0 = <&qup_spi13_default>; 1331 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1332 #address-cells = <1>; 1333 #size-cells = <0>; 1334 status = "disabled"; 1335 }; 1336 1337 uart13: serial@a94000 { 1338 compatible = "qcom,geni-uart"; 1339 reg = <0 0x00a94000 0 0x4000>; 1340 clock-names = "se"; 1341 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1342 pinctrl-names = "default"; 1343 pinctrl-0 = <&qup_uart13_default>; 1344 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1345 status = "disabled"; 1346 }; 1347 1348 i2c14: i2c@a98000 { 1349 compatible = "qcom,geni-i2c"; 1350 reg = <0 0x00a98000 0 0x4000>; 1351 clock-names = "se"; 1352 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1353 pinctrl-names = "default"; 1354 pinctrl-0 = <&qup_i2c14_default>; 1355 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 1356 #address-cells = <1>; 1357 #size-cells = <0>; 1358 status = "disabled"; 1359 }; 1360 1361 spi14: spi@a98000 { 1362 compatible = "qcom,geni-spi"; 1363 reg = <0 0x00a98000 0 0x4000>; 1364 clock-names = "se"; 1365 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1366 pinctrl-names = "default"; 1367 pinctrl-0 = <&qup_spi14_default>; 1368 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 1369 #address-cells = <1>; 1370 #size-cells = <0>; 1371 status = "disabled"; 1372 }; 1373 1374 uart14: serial@a98000 { 1375 compatible = "qcom,geni-uart"; 1376 reg = <0 0x00a98000 0 0x4000>; 1377 clock-names = "se"; 1378 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1379 pinctrl-names = "default"; 1380 pinctrl-0 = <&qup_uart14_default>; 1381 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 1382 status = "disabled"; 1383 }; 1384 1385 i2c15: i2c@a9c000 { 1386 compatible = "qcom,geni-i2c"; 1387 reg = <0 0x00a9c000 0 0x4000>; 1388 clock-names = "se"; 1389 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1390 pinctrl-names = "default"; 1391 pinctrl-0 = <&qup_i2c15_default>; 1392 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1393 #address-cells = <1>; 1394 #size-cells = <0>; 1395 status = "disabled"; 1396 }; 1397 1398 spi15: spi@a9c000 { 1399 compatible = "qcom,geni-spi"; 1400 reg = <0 0x00a9c000 0 0x4000>; 1401 clock-names = "se"; 1402 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1403 pinctrl-names = "default"; 1404 pinctrl-0 = <&qup_spi15_default>; 1405 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1406 #address-cells = <1>; 1407 #size-cells = <0>; 1408 status = "disabled"; 1409 }; 1410 1411 uart15: serial@a9c000 { 1412 compatible = "qcom,geni-uart"; 1413 reg = <0 0x00a9c000 0 0x4000>; 1414 clock-names = "se"; 1415 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1416 pinctrl-names = "default"; 1417 pinctrl-0 = <&qup_uart15_default>; 1418 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1419 status = "disabled"; 1420 }; 1421 }; 1422 1423 system-cache-controller@1100000 { 1424 compatible = "qcom,sdm845-llcc"; 1425 reg = <0 0x01100000 0 0x200000>, <0 0x01300000 0 0x50000>; 1426 reg-names = "llcc_base", "llcc_broadcast_base"; 1427 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 1428 }; 1429 1430 pcie0: pci@1c00000 { 1431 compatible = "qcom,pcie-sdm845", "snps,dw-pcie"; 1432 reg = <0 0x01c00000 0 0x2000>, 1433 <0 0x60000000 0 0xf1d>, 1434 <0 0x60000f20 0 0xa8>, 1435 <0 0x60100000 0 0x100000>; 1436 reg-names = "parf", "dbi", "elbi", "config"; 1437 device_type = "pci"; 1438 linux,pci-domain = <0>; 1439 bus-range = <0x00 0xff>; 1440 num-lanes = <1>; 1441 1442 #address-cells = <3>; 1443 #size-cells = <2>; 1444 1445 ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>, 1446 <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0xd00000>; 1447 1448 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 1449 interrupt-names = "msi"; 1450 #interrupt-cells = <1>; 1451 interrupt-map-mask = <0 0 0 0x7>; 1452 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1453 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1454 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1455 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1456 1457 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1458 <&gcc GCC_PCIE_0_AUX_CLK>, 1459 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1460 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1461 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1462 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1463 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; 1464 clock-names = "pipe", 1465 "aux", 1466 "cfg", 1467 "bus_master", 1468 "bus_slave", 1469 "slave_q2a", 1470 "tbu"; 1471 1472 iommus = <&apps_smmu 0x1c10 0xf>; 1473 iommu-map = <0x0 &apps_smmu 0x1c10 0x1>, 1474 <0x100 &apps_smmu 0x1c11 0x1>, 1475 <0x200 &apps_smmu 0x1c12 0x1>, 1476 <0x300 &apps_smmu 0x1c13 0x1>, 1477 <0x400 &apps_smmu 0x1c14 0x1>, 1478 <0x500 &apps_smmu 0x1c15 0x1>, 1479 <0x600 &apps_smmu 0x1c16 0x1>, 1480 <0x700 &apps_smmu 0x1c17 0x1>, 1481 <0x800 &apps_smmu 0x1c18 0x1>, 1482 <0x900 &apps_smmu 0x1c19 0x1>, 1483 <0xa00 &apps_smmu 0x1c1a 0x1>, 1484 <0xb00 &apps_smmu 0x1c1b 0x1>, 1485 <0xc00 &apps_smmu 0x1c1c 0x1>, 1486 <0xd00 &apps_smmu 0x1c1d 0x1>, 1487 <0xe00 &apps_smmu 0x1c1e 0x1>, 1488 <0xf00 &apps_smmu 0x1c1f 0x1>; 1489 1490 resets = <&gcc GCC_PCIE_0_BCR>; 1491 reset-names = "pci"; 1492 1493 power-domains = <&gcc PCIE_0_GDSC>; 1494 1495 phys = <&pcie0_lane>; 1496 phy-names = "pciephy"; 1497 1498 status = "disabled"; 1499 }; 1500 1501 pcie0_phy: phy@1c06000 { 1502 compatible = "qcom,sdm845-qmp-pcie-phy"; 1503 reg = <0 0x01c06000 0 0x18c>; 1504 #address-cells = <2>; 1505 #size-cells = <2>; 1506 ranges; 1507 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1508 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1509 <&gcc GCC_PCIE_0_CLKREF_CLK>, 1510 <&gcc GCC_PCIE_PHY_REFGEN_CLK>; 1511 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 1512 1513 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1514 reset-names = "phy"; 1515 1516 assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>; 1517 assigned-clock-rates = <100000000>; 1518 1519 status = "disabled"; 1520 1521 pcie0_lane: lanes@1c06200 { 1522 reg = <0 0x01c06200 0 0x128>, 1523 <0 0x01c06400 0 0x1fc>, 1524 <0 0x01c06800 0 0x218>, 1525 <0 0x01c06600 0 0x70>; 1526 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 1527 clock-names = "pipe0"; 1528 1529 #phy-cells = <0>; 1530 clock-output-names = "pcie_0_pipe_clk"; 1531 }; 1532 }; 1533 1534 pcie1: pci@1c08000 { 1535 compatible = "qcom,pcie-sdm845", "snps,dw-pcie"; 1536 reg = <0 0x01c08000 0 0x2000>, 1537 <0 0x40000000 0 0xf1d>, 1538 <0 0x40000f20 0 0xa8>, 1539 <0 0x40100000 0 0x100000>; 1540 reg-names = "parf", "dbi", "elbi", "config"; 1541 device_type = "pci"; 1542 linux,pci-domain = <1>; 1543 bus-range = <0x00 0xff>; 1544 num-lanes = <1>; 1545 1546 #address-cells = <3>; 1547 #size-cells = <2>; 1548 1549 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, 1550 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1551 1552 interrupts = <GIC_SPI 307 IRQ_TYPE_EDGE_RISING>; 1553 interrupt-names = "msi"; 1554 #interrupt-cells = <1>; 1555 interrupt-map-mask = <0 0 0 0x7>; 1556 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1557 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1558 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1559 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1560 1561 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1562 <&gcc GCC_PCIE_1_AUX_CLK>, 1563 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1564 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1565 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1566 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1567 <&gcc GCC_PCIE_1_CLKREF_CLK>, 1568 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; 1569 clock-names = "pipe", 1570 "aux", 1571 "cfg", 1572 "bus_master", 1573 "bus_slave", 1574 "slave_q2a", 1575 "ref", 1576 "tbu"; 1577 1578 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 1579 assigned-clock-rates = <19200000>; 1580 1581 iommus = <&apps_smmu 0x1c00 0xf>; 1582 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, 1583 <0x100 &apps_smmu 0x1c01 0x1>, 1584 <0x200 &apps_smmu 0x1c02 0x1>, 1585 <0x300 &apps_smmu 0x1c03 0x1>, 1586 <0x400 &apps_smmu 0x1c04 0x1>, 1587 <0x500 &apps_smmu 0x1c05 0x1>, 1588 <0x600 &apps_smmu 0x1c06 0x1>, 1589 <0x700 &apps_smmu 0x1c07 0x1>, 1590 <0x800 &apps_smmu 0x1c08 0x1>, 1591 <0x900 &apps_smmu 0x1c09 0x1>, 1592 <0xa00 &apps_smmu 0x1c0a 0x1>, 1593 <0xb00 &apps_smmu 0x1c0b 0x1>, 1594 <0xc00 &apps_smmu 0x1c0c 0x1>, 1595 <0xd00 &apps_smmu 0x1c0d 0x1>, 1596 <0xe00 &apps_smmu 0x1c0e 0x1>, 1597 <0xf00 &apps_smmu 0x1c0f 0x1>; 1598 1599 resets = <&gcc GCC_PCIE_1_BCR>; 1600 reset-names = "pci"; 1601 1602 power-domains = <&gcc PCIE_1_GDSC>; 1603 1604 phys = <&pcie1_lane>; 1605 phy-names = "pciephy"; 1606 1607 status = "disabled"; 1608 }; 1609 1610 pcie1_phy: phy@1c0a000 { 1611 compatible = "qcom,sdm845-qhp-pcie-phy"; 1612 reg = <0 0x01c0a000 0 0x800>; 1613 #address-cells = <2>; 1614 #size-cells = <2>; 1615 ranges; 1616 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1617 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1618 <&gcc GCC_PCIE_1_CLKREF_CLK>, 1619 <&gcc GCC_PCIE_PHY_REFGEN_CLK>; 1620 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 1621 1622 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 1623 reset-names = "phy"; 1624 1625 assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>; 1626 assigned-clock-rates = <100000000>; 1627 1628 status = "disabled"; 1629 1630 pcie1_lane: lanes@1c06200 { 1631 reg = <0 0x01c0a800 0 0x800>, 1632 <0 0x01c0a800 0 0x800>, 1633 <0 0x01c0b800 0 0x400>; 1634 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 1635 clock-names = "pipe0"; 1636 1637 #phy-cells = <0>; 1638 clock-output-names = "pcie_1_pipe_clk"; 1639 }; 1640 }; 1641 1642 mem_noc: interconnect@1380000 { 1643 compatible = "qcom,sdm845-mem-noc"; 1644 reg = <0 0x01380000 0 0x27200>; 1645 #interconnect-cells = <1>; 1646 qcom,bcm-voters = <&apps_bcm_voter>; 1647 }; 1648 1649 dc_noc: interconnect@14e0000 { 1650 compatible = "qcom,sdm845-dc-noc"; 1651 reg = <0 0x014e0000 0 0x400>; 1652 #interconnect-cells = <1>; 1653 qcom,bcm-voters = <&apps_bcm_voter>; 1654 }; 1655 1656 config_noc: interconnect@1500000 { 1657 compatible = "qcom,sdm845-config-noc"; 1658 reg = <0 0x01500000 0 0x5080>; 1659 #interconnect-cells = <1>; 1660 qcom,bcm-voters = <&apps_bcm_voter>; 1661 }; 1662 1663 system_noc: interconnect@1620000 { 1664 compatible = "qcom,sdm845-system-noc"; 1665 reg = <0 0x01620000 0 0x18080>; 1666 #interconnect-cells = <1>; 1667 qcom,bcm-voters = <&apps_bcm_voter>; 1668 }; 1669 1670 aggre1_noc: interconnect@16e0000 { 1671 compatible = "qcom,sdm845-aggre1-noc"; 1672 reg = <0 0x016e0000 0 0x15080>; 1673 #interconnect-cells = <1>; 1674 qcom,bcm-voters = <&apps_bcm_voter>; 1675 }; 1676 1677 aggre2_noc: interconnect@1700000 { 1678 compatible = "qcom,sdm845-aggre2-noc"; 1679 reg = <0 0x01700000 0 0x1f300>; 1680 #interconnect-cells = <1>; 1681 qcom,bcm-voters = <&apps_bcm_voter>; 1682 }; 1683 1684 mmss_noc: interconnect@1740000 { 1685 compatible = "qcom,sdm845-mmss-noc"; 1686 reg = <0 0x01740000 0 0x1c100>; 1687 #interconnect-cells = <1>; 1688 qcom,bcm-voters = <&apps_bcm_voter>; 1689 }; 1690 1691 ufs_mem_hc: ufshc@1d84000 { 1692 compatible = "qcom,sdm845-ufshc", "qcom,ufshc", 1693 "jedec,ufs-2.0"; 1694 reg = <0 0x01d84000 0 0x2500>; 1695 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 1696 phys = <&ufs_mem_phy_lanes>; 1697 phy-names = "ufsphy"; 1698 lanes-per-direction = <2>; 1699 power-domains = <&gcc UFS_PHY_GDSC>; 1700 #reset-cells = <1>; 1701 resets = <&gcc GCC_UFS_PHY_BCR>; 1702 reset-names = "rst"; 1703 1704 iommus = <&apps_smmu 0x100 0xf>; 1705 1706 clock-names = 1707 "core_clk", 1708 "bus_aggr_clk", 1709 "iface_clk", 1710 "core_clk_unipro", 1711 "ref_clk", 1712 "tx_lane0_sync_clk", 1713 "rx_lane0_sync_clk", 1714 "rx_lane1_sync_clk"; 1715 clocks = 1716 <&gcc GCC_UFS_PHY_AXI_CLK>, 1717 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1718 <&gcc GCC_UFS_PHY_AHB_CLK>, 1719 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 1720 <&rpmhcc RPMH_CXO_CLK>, 1721 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 1722 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 1723 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 1724 freq-table-hz = 1725 <50000000 200000000>, 1726 <0 0>, 1727 <0 0>, 1728 <37500000 150000000>, 1729 <0 0>, 1730 <0 0>, 1731 <0 0>, 1732 <0 0>; 1733 1734 status = "disabled"; 1735 }; 1736 1737 ufs_mem_phy: phy@1d87000 { 1738 compatible = "qcom,sdm845-qmp-ufs-phy"; 1739 reg = <0 0x01d87000 0 0x18c>; 1740 #address-cells = <2>; 1741 #size-cells = <2>; 1742 ranges; 1743 clock-names = "ref", 1744 "ref_aux"; 1745 clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, 1746 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 1747 1748 resets = <&ufs_mem_hc 0>; 1749 reset-names = "ufsphy"; 1750 status = "disabled"; 1751 1752 ufs_mem_phy_lanes: lanes@1d87400 { 1753 reg = <0 0x01d87400 0 0x108>, 1754 <0 0x01d87600 0 0x1e0>, 1755 <0 0x01d87c00 0 0x1dc>, 1756 <0 0x01d87800 0 0x108>, 1757 <0 0x01d87a00 0 0x1e0>; 1758 #phy-cells = <0>; 1759 }; 1760 }; 1761 1762 ipa: ipa@1e40000 { 1763 compatible = "qcom,sdm845-ipa"; 1764 1765 iommus = <&apps_smmu 0x720 0x3>; 1766 reg = <0 0x1e40000 0 0x7000>, 1767 <0 0x1e47000 0 0x2000>, 1768 <0 0x1e04000 0 0x2c000>; 1769 reg-names = "ipa-reg", 1770 "ipa-shared", 1771 "gsi"; 1772 1773 interrupts-extended = <&intc 0 311 IRQ_TYPE_EDGE_RISING>, 1774 <&intc 0 432 IRQ_TYPE_LEVEL_HIGH>, 1775 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1776 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 1777 interrupt-names = "ipa", 1778 "gsi", 1779 "ipa-clock-query", 1780 "ipa-setup-ready"; 1781 1782 clocks = <&rpmhcc RPMH_IPA_CLK>; 1783 clock-names = "core"; 1784 1785 interconnects = <&aggre2_noc MASTER_IPA &mem_noc SLAVE_EBI1>, 1786 <&aggre2_noc MASTER_IPA &system_noc SLAVE_IMEM>, 1787 <&gladiator_noc MASTER_APPSS_PROC &config_noc SLAVE_IPA_CFG>; 1788 interconnect-names = "memory", 1789 "imem", 1790 "config"; 1791 1792 qcom,smem-states = <&ipa_smp2p_out 0>, 1793 <&ipa_smp2p_out 1>; 1794 qcom,smem-state-names = "ipa-clock-enabled-valid", 1795 "ipa-clock-enabled"; 1796 1797 modem-remoteproc = <&mss_pil>; 1798 1799 status = "disabled"; 1800 }; 1801 1802 tcsr_mutex_regs: syscon@1f40000 { 1803 compatible = "syscon"; 1804 reg = <0 0x01f40000 0 0x40000>; 1805 }; 1806 1807 tlmm: pinctrl@3400000 { 1808 compatible = "qcom,sdm845-pinctrl"; 1809 reg = <0 0x03400000 0 0xc00000>; 1810 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1811 gpio-controller; 1812 #gpio-cells = <2>; 1813 interrupt-controller; 1814 #interrupt-cells = <2>; 1815 gpio-ranges = <&tlmm 0 0 150>; 1816 wakeup-parent = <&pdc_intc>; 1817 1818 qspi_clk: qspi-clk { 1819 pinmux { 1820 pins = "gpio95"; 1821 function = "qspi_clk"; 1822 }; 1823 }; 1824 1825 qspi_cs0: qspi-cs0 { 1826 pinmux { 1827 pins = "gpio90"; 1828 function = "qspi_cs"; 1829 }; 1830 }; 1831 1832 qspi_cs1: qspi-cs1 { 1833 pinmux { 1834 pins = "gpio89"; 1835 function = "qspi_cs"; 1836 }; 1837 }; 1838 1839 qspi_data01: qspi-data01 { 1840 pinmux-data { 1841 pins = "gpio91", "gpio92"; 1842 function = "qspi_data"; 1843 }; 1844 }; 1845 1846 qspi_data12: qspi-data12 { 1847 pinmux-data { 1848 pins = "gpio93", "gpio94"; 1849 function = "qspi_data"; 1850 }; 1851 }; 1852 1853 qup_i2c0_default: qup-i2c0-default { 1854 pinmux { 1855 pins = "gpio0", "gpio1"; 1856 function = "qup0"; 1857 }; 1858 }; 1859 1860 qup_i2c1_default: qup-i2c1-default { 1861 pinmux { 1862 pins = "gpio17", "gpio18"; 1863 function = "qup1"; 1864 }; 1865 }; 1866 1867 qup_i2c2_default: qup-i2c2-default { 1868 pinmux { 1869 pins = "gpio27", "gpio28"; 1870 function = "qup2"; 1871 }; 1872 }; 1873 1874 qup_i2c3_default: qup-i2c3-default { 1875 pinmux { 1876 pins = "gpio41", "gpio42"; 1877 function = "qup3"; 1878 }; 1879 }; 1880 1881 qup_i2c4_default: qup-i2c4-default { 1882 pinmux { 1883 pins = "gpio89", "gpio90"; 1884 function = "qup4"; 1885 }; 1886 }; 1887 1888 qup_i2c5_default: qup-i2c5-default { 1889 pinmux { 1890 pins = "gpio85", "gpio86"; 1891 function = "qup5"; 1892 }; 1893 }; 1894 1895 qup_i2c6_default: qup-i2c6-default { 1896 pinmux { 1897 pins = "gpio45", "gpio46"; 1898 function = "qup6"; 1899 }; 1900 }; 1901 1902 qup_i2c7_default: qup-i2c7-default { 1903 pinmux { 1904 pins = "gpio93", "gpio94"; 1905 function = "qup7"; 1906 }; 1907 }; 1908 1909 qup_i2c8_default: qup-i2c8-default { 1910 pinmux { 1911 pins = "gpio65", "gpio66"; 1912 function = "qup8"; 1913 }; 1914 }; 1915 1916 qup_i2c9_default: qup-i2c9-default { 1917 pinmux { 1918 pins = "gpio6", "gpio7"; 1919 function = "qup9"; 1920 }; 1921 }; 1922 1923 qup_i2c10_default: qup-i2c10-default { 1924 pinmux { 1925 pins = "gpio55", "gpio56"; 1926 function = "qup10"; 1927 }; 1928 }; 1929 1930 qup_i2c11_default: qup-i2c11-default { 1931 pinmux { 1932 pins = "gpio31", "gpio32"; 1933 function = "qup11"; 1934 }; 1935 }; 1936 1937 qup_i2c12_default: qup-i2c12-default { 1938 pinmux { 1939 pins = "gpio49", "gpio50"; 1940 function = "qup12"; 1941 }; 1942 }; 1943 1944 qup_i2c13_default: qup-i2c13-default { 1945 pinmux { 1946 pins = "gpio105", "gpio106"; 1947 function = "qup13"; 1948 }; 1949 }; 1950 1951 qup_i2c14_default: qup-i2c14-default { 1952 pinmux { 1953 pins = "gpio33", "gpio34"; 1954 function = "qup14"; 1955 }; 1956 }; 1957 1958 qup_i2c15_default: qup-i2c15-default { 1959 pinmux { 1960 pins = "gpio81", "gpio82"; 1961 function = "qup15"; 1962 }; 1963 }; 1964 1965 qup_spi0_default: qup-spi0-default { 1966 pinmux { 1967 pins = "gpio0", "gpio1", 1968 "gpio2", "gpio3"; 1969 function = "qup0"; 1970 }; 1971 }; 1972 1973 qup_spi1_default: qup-spi1-default { 1974 pinmux { 1975 pins = "gpio17", "gpio18", 1976 "gpio19", "gpio20"; 1977 function = "qup1"; 1978 }; 1979 }; 1980 1981 qup_spi2_default: qup-spi2-default { 1982 pinmux { 1983 pins = "gpio27", "gpio28", 1984 "gpio29", "gpio30"; 1985 function = "qup2"; 1986 }; 1987 }; 1988 1989 qup_spi3_default: qup-spi3-default { 1990 pinmux { 1991 pins = "gpio41", "gpio42", 1992 "gpio43", "gpio44"; 1993 function = "qup3"; 1994 }; 1995 }; 1996 1997 qup_spi4_default: qup-spi4-default { 1998 pinmux { 1999 pins = "gpio89", "gpio90", 2000 "gpio91", "gpio92"; 2001 function = "qup4"; 2002 }; 2003 }; 2004 2005 qup_spi5_default: qup-spi5-default { 2006 pinmux { 2007 pins = "gpio85", "gpio86", 2008 "gpio87", "gpio88"; 2009 function = "qup5"; 2010 }; 2011 }; 2012 2013 qup_spi6_default: qup-spi6-default { 2014 pinmux { 2015 pins = "gpio45", "gpio46", 2016 "gpio47", "gpio48"; 2017 function = "qup6"; 2018 }; 2019 }; 2020 2021 qup_spi7_default: qup-spi7-default { 2022 pinmux { 2023 pins = "gpio93", "gpio94", 2024 "gpio95", "gpio96"; 2025 function = "qup7"; 2026 }; 2027 }; 2028 2029 qup_spi8_default: qup-spi8-default { 2030 pinmux { 2031 pins = "gpio65", "gpio66", 2032 "gpio67", "gpio68"; 2033 function = "qup8"; 2034 }; 2035 }; 2036 2037 qup_spi9_default: qup-spi9-default { 2038 pinmux { 2039 pins = "gpio6", "gpio7", 2040 "gpio4", "gpio5"; 2041 function = "qup9"; 2042 }; 2043 }; 2044 2045 qup_spi10_default: qup-spi10-default { 2046 pinmux { 2047 pins = "gpio55", "gpio56", 2048 "gpio53", "gpio54"; 2049 function = "qup10"; 2050 }; 2051 }; 2052 2053 qup_spi11_default: qup-spi11-default { 2054 pinmux { 2055 pins = "gpio31", "gpio32", 2056 "gpio33", "gpio34"; 2057 function = "qup11"; 2058 }; 2059 }; 2060 2061 qup_spi12_default: qup-spi12-default { 2062 pinmux { 2063 pins = "gpio49", "gpio50", 2064 "gpio51", "gpio52"; 2065 function = "qup12"; 2066 }; 2067 }; 2068 2069 qup_spi13_default: qup-spi13-default { 2070 pinmux { 2071 pins = "gpio105", "gpio106", 2072 "gpio107", "gpio108"; 2073 function = "qup13"; 2074 }; 2075 }; 2076 2077 qup_spi14_default: qup-spi14-default { 2078 pinmux { 2079 pins = "gpio33", "gpio34", 2080 "gpio31", "gpio32"; 2081 function = "qup14"; 2082 }; 2083 }; 2084 2085 qup_spi15_default: qup-spi15-default { 2086 pinmux { 2087 pins = "gpio81", "gpio82", 2088 "gpio83", "gpio84"; 2089 function = "qup15"; 2090 }; 2091 }; 2092 2093 qup_uart0_default: qup-uart0-default { 2094 pinmux { 2095 pins = "gpio2", "gpio3"; 2096 function = "qup0"; 2097 }; 2098 }; 2099 2100 qup_uart1_default: qup-uart1-default { 2101 pinmux { 2102 pins = "gpio19", "gpio20"; 2103 function = "qup1"; 2104 }; 2105 }; 2106 2107 qup_uart2_default: qup-uart2-default { 2108 pinmux { 2109 pins = "gpio29", "gpio30"; 2110 function = "qup2"; 2111 }; 2112 }; 2113 2114 qup_uart3_default: qup-uart3-default { 2115 pinmux { 2116 pins = "gpio43", "gpio44"; 2117 function = "qup3"; 2118 }; 2119 }; 2120 2121 qup_uart4_default: qup-uart4-default { 2122 pinmux { 2123 pins = "gpio91", "gpio92"; 2124 function = "qup4"; 2125 }; 2126 }; 2127 2128 qup_uart5_default: qup-uart5-default { 2129 pinmux { 2130 pins = "gpio87", "gpio88"; 2131 function = "qup5"; 2132 }; 2133 }; 2134 2135 qup_uart6_default: qup-uart6-default { 2136 pinmux { 2137 pins = "gpio47", "gpio48"; 2138 function = "qup6"; 2139 }; 2140 }; 2141 2142 qup_uart7_default: qup-uart7-default { 2143 pinmux { 2144 pins = "gpio95", "gpio96"; 2145 function = "qup7"; 2146 }; 2147 }; 2148 2149 qup_uart8_default: qup-uart8-default { 2150 pinmux { 2151 pins = "gpio67", "gpio68"; 2152 function = "qup8"; 2153 }; 2154 }; 2155 2156 qup_uart9_default: qup-uart9-default { 2157 pinmux { 2158 pins = "gpio4", "gpio5"; 2159 function = "qup9"; 2160 }; 2161 }; 2162 2163 qup_uart10_default: qup-uart10-default { 2164 pinmux { 2165 pins = "gpio53", "gpio54"; 2166 function = "qup10"; 2167 }; 2168 }; 2169 2170 qup_uart11_default: qup-uart11-default { 2171 pinmux { 2172 pins = "gpio33", "gpio34"; 2173 function = "qup11"; 2174 }; 2175 }; 2176 2177 qup_uart12_default: qup-uart12-default { 2178 pinmux { 2179 pins = "gpio51", "gpio52"; 2180 function = "qup12"; 2181 }; 2182 }; 2183 2184 qup_uart13_default: qup-uart13-default { 2185 pinmux { 2186 pins = "gpio107", "gpio108"; 2187 function = "qup13"; 2188 }; 2189 }; 2190 2191 qup_uart14_default: qup-uart14-default { 2192 pinmux { 2193 pins = "gpio31", "gpio32"; 2194 function = "qup14"; 2195 }; 2196 }; 2197 2198 qup_uart15_default: qup-uart15-default { 2199 pinmux { 2200 pins = "gpio83", "gpio84"; 2201 function = "qup15"; 2202 }; 2203 }; 2204 2205 quat_mi2s_sleep: quat_mi2s_sleep { 2206 mux { 2207 pins = "gpio58", "gpio59"; 2208 function = "gpio"; 2209 }; 2210 2211 config { 2212 pins = "gpio58", "gpio59"; 2213 drive-strength = <2>; 2214 bias-pull-down; 2215 input-enable; 2216 }; 2217 }; 2218 2219 quat_mi2s_active: quat_mi2s_active { 2220 mux { 2221 pins = "gpio58", "gpio59"; 2222 function = "qua_mi2s"; 2223 }; 2224 2225 config { 2226 pins = "gpio58", "gpio59"; 2227 drive-strength = <8>; 2228 bias-disable; 2229 output-high; 2230 }; 2231 }; 2232 2233 quat_mi2s_sd0_sleep: quat_mi2s_sd0_sleep { 2234 mux { 2235 pins = "gpio60"; 2236 function = "gpio"; 2237 }; 2238 2239 config { 2240 pins = "gpio60"; 2241 drive-strength = <2>; 2242 bias-pull-down; 2243 input-enable; 2244 }; 2245 }; 2246 2247 quat_mi2s_sd0_active: quat_mi2s_sd0_active { 2248 mux { 2249 pins = "gpio60"; 2250 function = "qua_mi2s"; 2251 }; 2252 2253 config { 2254 pins = "gpio60"; 2255 drive-strength = <8>; 2256 bias-disable; 2257 }; 2258 }; 2259 2260 quat_mi2s_sd1_sleep: quat_mi2s_sd1_sleep { 2261 mux { 2262 pins = "gpio61"; 2263 function = "gpio"; 2264 }; 2265 2266 config { 2267 pins = "gpio61"; 2268 drive-strength = <2>; 2269 bias-pull-down; 2270 input-enable; 2271 }; 2272 }; 2273 2274 quat_mi2s_sd1_active: quat_mi2s_sd1_active { 2275 mux { 2276 pins = "gpio61"; 2277 function = "qua_mi2s"; 2278 }; 2279 2280 config { 2281 pins = "gpio61"; 2282 drive-strength = <8>; 2283 bias-disable; 2284 }; 2285 }; 2286 2287 quat_mi2s_sd2_sleep: quat_mi2s_sd2_sleep { 2288 mux { 2289 pins = "gpio62"; 2290 function = "gpio"; 2291 }; 2292 2293 config { 2294 pins = "gpio62"; 2295 drive-strength = <2>; 2296 bias-pull-down; 2297 input-enable; 2298 }; 2299 }; 2300 2301 quat_mi2s_sd2_active: quat_mi2s_sd2_active { 2302 mux { 2303 pins = "gpio62"; 2304 function = "qua_mi2s"; 2305 }; 2306 2307 config { 2308 pins = "gpio62"; 2309 drive-strength = <8>; 2310 bias-disable; 2311 }; 2312 }; 2313 2314 quat_mi2s_sd3_sleep: quat_mi2s_sd3_sleep { 2315 mux { 2316 pins = "gpio63"; 2317 function = "gpio"; 2318 }; 2319 2320 config { 2321 pins = "gpio63"; 2322 drive-strength = <2>; 2323 bias-pull-down; 2324 input-enable; 2325 }; 2326 }; 2327 2328 quat_mi2s_sd3_active: quat_mi2s_sd3_active { 2329 mux { 2330 pins = "gpio63"; 2331 function = "qua_mi2s"; 2332 }; 2333 2334 config { 2335 pins = "gpio63"; 2336 drive-strength = <8>; 2337 bias-disable; 2338 }; 2339 }; 2340 }; 2341 2342 mss_pil: remoteproc@4080000 { 2343 compatible = "qcom,sdm845-mss-pil"; 2344 reg = <0 0x04080000 0 0x408>, <0 0x04180000 0 0x48>; 2345 reg-names = "qdsp6", "rmb"; 2346 2347 interrupts-extended = 2348 <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, 2349 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2350 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2351 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2352 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2353 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2354 interrupt-names = "wdog", "fatal", "ready", 2355 "handover", "stop-ack", 2356 "shutdown-ack"; 2357 2358 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 2359 <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>, 2360 <&gcc GCC_BOOT_ROM_AHB_CLK>, 2361 <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>, 2362 <&gcc GCC_MSS_SNOC_AXI_CLK>, 2363 <&gcc GCC_MSS_MFAB_AXIS_CLK>, 2364 <&gcc GCC_PRNG_AHB_CLK>, 2365 <&rpmhcc RPMH_CXO_CLK>; 2366 clock-names = "iface", "bus", "mem", "gpll0_mss", 2367 "snoc_axi", "mnoc_axi", "prng", "xo"; 2368 2369 qcom,smem-states = <&modem_smp2p_out 0>; 2370 qcom,smem-state-names = "stop"; 2371 2372 resets = <&aoss_reset AOSS_CC_MSS_RESTART>, 2373 <&pdc_reset PDC_MODEM_SYNC_RESET>; 2374 reset-names = "mss_restart", "pdc_reset"; 2375 2376 qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>; 2377 2378 power-domains = <&aoss_qmp 2>, 2379 <&rpmhpd SDM845_CX>, 2380 <&rpmhpd SDM845_MX>, 2381 <&rpmhpd SDM845_MSS>; 2382 power-domain-names = "load_state", "cx", "mx", "mss"; 2383 2384 mba { 2385 memory-region = <&mba_region>; 2386 }; 2387 2388 mpss { 2389 memory-region = <&mpss_region>; 2390 }; 2391 2392 glink-edge { 2393 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 2394 label = "modem"; 2395 qcom,remote-pid = <1>; 2396 mboxes = <&apss_shared 12>; 2397 }; 2398 }; 2399 2400 gpucc: clock-controller@5090000 { 2401 compatible = "qcom,sdm845-gpucc"; 2402 reg = <0 0x05090000 0 0x9000>; 2403 #clock-cells = <1>; 2404 #reset-cells = <1>; 2405 #power-domain-cells = <1>; 2406 clocks = <&rpmhcc RPMH_CXO_CLK>, 2407 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2408 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2409 clock-names = "bi_tcxo", 2410 "gcc_gpu_gpll0_clk_src", 2411 "gcc_gpu_gpll0_div_clk_src"; 2412 }; 2413 2414 stm@6002000 { 2415 compatible = "arm,coresight-stm", "arm,primecell"; 2416 reg = <0 0x06002000 0 0x1000>, 2417 <0 0x16280000 0 0x180000>; 2418 reg-names = "stm-base", "stm-stimulus-base"; 2419 2420 clocks = <&aoss_qmp>; 2421 clock-names = "apb_pclk"; 2422 2423 out-ports { 2424 port { 2425 stm_out: endpoint { 2426 remote-endpoint = 2427 <&funnel0_in7>; 2428 }; 2429 }; 2430 }; 2431 }; 2432 2433 funnel@6041000 { 2434 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2435 reg = <0 0x06041000 0 0x1000>; 2436 2437 clocks = <&aoss_qmp>; 2438 clock-names = "apb_pclk"; 2439 2440 out-ports { 2441 port { 2442 funnel0_out: endpoint { 2443 remote-endpoint = 2444 <&merge_funnel_in0>; 2445 }; 2446 }; 2447 }; 2448 2449 in-ports { 2450 #address-cells = <1>; 2451 #size-cells = <0>; 2452 2453 port@7 { 2454 reg = <7>; 2455 funnel0_in7: endpoint { 2456 remote-endpoint = <&stm_out>; 2457 }; 2458 }; 2459 }; 2460 }; 2461 2462 funnel@6043000 { 2463 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2464 reg = <0 0x06043000 0 0x1000>; 2465 2466 clocks = <&aoss_qmp>; 2467 clock-names = "apb_pclk"; 2468 2469 out-ports { 2470 port { 2471 funnel2_out: endpoint { 2472 remote-endpoint = 2473 <&merge_funnel_in2>; 2474 }; 2475 }; 2476 }; 2477 2478 in-ports { 2479 #address-cells = <1>; 2480 #size-cells = <0>; 2481 2482 port@5 { 2483 reg = <5>; 2484 funnel2_in5: endpoint { 2485 remote-endpoint = 2486 <&apss_merge_funnel_out>; 2487 }; 2488 }; 2489 }; 2490 }; 2491 2492 funnel@6045000 { 2493 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2494 reg = <0 0x06045000 0 0x1000>; 2495 2496 clocks = <&aoss_qmp>; 2497 clock-names = "apb_pclk"; 2498 2499 out-ports { 2500 port { 2501 merge_funnel_out: endpoint { 2502 remote-endpoint = <&etf_in>; 2503 }; 2504 }; 2505 }; 2506 2507 in-ports { 2508 #address-cells = <1>; 2509 #size-cells = <0>; 2510 2511 port@0 { 2512 reg = <0>; 2513 merge_funnel_in0: endpoint { 2514 remote-endpoint = 2515 <&funnel0_out>; 2516 }; 2517 }; 2518 2519 port@2 { 2520 reg = <2>; 2521 merge_funnel_in2: endpoint { 2522 remote-endpoint = 2523 <&funnel2_out>; 2524 }; 2525 }; 2526 }; 2527 }; 2528 2529 replicator@6046000 { 2530 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2531 reg = <0 0x06046000 0 0x1000>; 2532 2533 clocks = <&aoss_qmp>; 2534 clock-names = "apb_pclk"; 2535 2536 out-ports { 2537 port { 2538 replicator_out: endpoint { 2539 remote-endpoint = <&etr_in>; 2540 }; 2541 }; 2542 }; 2543 2544 in-ports { 2545 port { 2546 replicator_in: endpoint { 2547 remote-endpoint = <&etf_out>; 2548 }; 2549 }; 2550 }; 2551 }; 2552 2553 etf@6047000 { 2554 compatible = "arm,coresight-tmc", "arm,primecell"; 2555 reg = <0 0x06047000 0 0x1000>; 2556 2557 clocks = <&aoss_qmp>; 2558 clock-names = "apb_pclk"; 2559 2560 out-ports { 2561 port { 2562 etf_out: endpoint { 2563 remote-endpoint = 2564 <&replicator_in>; 2565 }; 2566 }; 2567 }; 2568 2569 in-ports { 2570 #address-cells = <1>; 2571 #size-cells = <0>; 2572 2573 port@1 { 2574 reg = <1>; 2575 etf_in: endpoint { 2576 remote-endpoint = 2577 <&merge_funnel_out>; 2578 }; 2579 }; 2580 }; 2581 }; 2582 2583 etr@6048000 { 2584 compatible = "arm,coresight-tmc", "arm,primecell"; 2585 reg = <0 0x06048000 0 0x1000>; 2586 2587 clocks = <&aoss_qmp>; 2588 clock-names = "apb_pclk"; 2589 arm,scatter-gather; 2590 2591 in-ports { 2592 port { 2593 etr_in: endpoint { 2594 remote-endpoint = 2595 <&replicator_out>; 2596 }; 2597 }; 2598 }; 2599 }; 2600 2601 etm@7040000 { 2602 compatible = "arm,coresight-etm4x", "arm,primecell"; 2603 reg = <0 0x07040000 0 0x1000>; 2604 2605 cpu = <&CPU0>; 2606 2607 clocks = <&aoss_qmp>; 2608 clock-names = "apb_pclk"; 2609 2610 out-ports { 2611 port { 2612 etm0_out: endpoint { 2613 remote-endpoint = 2614 <&apss_funnel_in0>; 2615 }; 2616 }; 2617 }; 2618 }; 2619 2620 etm@7140000 { 2621 compatible = "arm,coresight-etm4x", "arm,primecell"; 2622 reg = <0 0x07140000 0 0x1000>; 2623 2624 cpu = <&CPU1>; 2625 2626 clocks = <&aoss_qmp>; 2627 clock-names = "apb_pclk"; 2628 2629 out-ports { 2630 port { 2631 etm1_out: endpoint { 2632 remote-endpoint = 2633 <&apss_funnel_in1>; 2634 }; 2635 }; 2636 }; 2637 }; 2638 2639 etm@7240000 { 2640 compatible = "arm,coresight-etm4x", "arm,primecell"; 2641 reg = <0 0x07240000 0 0x1000>; 2642 2643 cpu = <&CPU2>; 2644 2645 clocks = <&aoss_qmp>; 2646 clock-names = "apb_pclk"; 2647 2648 out-ports { 2649 port { 2650 etm2_out: endpoint { 2651 remote-endpoint = 2652 <&apss_funnel_in2>; 2653 }; 2654 }; 2655 }; 2656 }; 2657 2658 etm@7340000 { 2659 compatible = "arm,coresight-etm4x", "arm,primecell"; 2660 reg = <0 0x07340000 0 0x1000>; 2661 2662 cpu = <&CPU3>; 2663 2664 clocks = <&aoss_qmp>; 2665 clock-names = "apb_pclk"; 2666 2667 out-ports { 2668 port { 2669 etm3_out: endpoint { 2670 remote-endpoint = 2671 <&apss_funnel_in3>; 2672 }; 2673 }; 2674 }; 2675 }; 2676 2677 etm@7440000 { 2678 compatible = "arm,coresight-etm4x", "arm,primecell"; 2679 reg = <0 0x07440000 0 0x1000>; 2680 2681 cpu = <&CPU4>; 2682 2683 clocks = <&aoss_qmp>; 2684 clock-names = "apb_pclk"; 2685 2686 out-ports { 2687 port { 2688 etm4_out: endpoint { 2689 remote-endpoint = 2690 <&apss_funnel_in4>; 2691 }; 2692 }; 2693 }; 2694 }; 2695 2696 etm@7540000 { 2697 compatible = "arm,coresight-etm4x", "arm,primecell"; 2698 reg = <0 0x07540000 0 0x1000>; 2699 2700 cpu = <&CPU5>; 2701 2702 clocks = <&aoss_qmp>; 2703 clock-names = "apb_pclk"; 2704 2705 out-ports { 2706 port { 2707 etm5_out: endpoint { 2708 remote-endpoint = 2709 <&apss_funnel_in5>; 2710 }; 2711 }; 2712 }; 2713 }; 2714 2715 etm@7640000 { 2716 compatible = "arm,coresight-etm4x", "arm,primecell"; 2717 reg = <0 0x07640000 0 0x1000>; 2718 2719 cpu = <&CPU6>; 2720 2721 clocks = <&aoss_qmp>; 2722 clock-names = "apb_pclk"; 2723 2724 out-ports { 2725 port { 2726 etm6_out: endpoint { 2727 remote-endpoint = 2728 <&apss_funnel_in6>; 2729 }; 2730 }; 2731 }; 2732 }; 2733 2734 etm@7740000 { 2735 compatible = "arm,coresight-etm4x", "arm,primecell"; 2736 reg = <0 0x07740000 0 0x1000>; 2737 2738 cpu = <&CPU7>; 2739 2740 clocks = <&aoss_qmp>; 2741 clock-names = "apb_pclk"; 2742 2743 out-ports { 2744 port { 2745 etm7_out: endpoint { 2746 remote-endpoint = 2747 <&apss_funnel_in7>; 2748 }; 2749 }; 2750 }; 2751 }; 2752 2753 funnel@7800000 { /* APSS Funnel */ 2754 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2755 reg = <0 0x07800000 0 0x1000>; 2756 2757 clocks = <&aoss_qmp>; 2758 clock-names = "apb_pclk"; 2759 2760 out-ports { 2761 port { 2762 apss_funnel_out: endpoint { 2763 remote-endpoint = 2764 <&apss_merge_funnel_in>; 2765 }; 2766 }; 2767 }; 2768 2769 in-ports { 2770 #address-cells = <1>; 2771 #size-cells = <0>; 2772 2773 port@0 { 2774 reg = <0>; 2775 apss_funnel_in0: endpoint { 2776 remote-endpoint = 2777 <&etm0_out>; 2778 }; 2779 }; 2780 2781 port@1 { 2782 reg = <1>; 2783 apss_funnel_in1: endpoint { 2784 remote-endpoint = 2785 <&etm1_out>; 2786 }; 2787 }; 2788 2789 port@2 { 2790 reg = <2>; 2791 apss_funnel_in2: endpoint { 2792 remote-endpoint = 2793 <&etm2_out>; 2794 }; 2795 }; 2796 2797 port@3 { 2798 reg = <3>; 2799 apss_funnel_in3: endpoint { 2800 remote-endpoint = 2801 <&etm3_out>; 2802 }; 2803 }; 2804 2805 port@4 { 2806 reg = <4>; 2807 apss_funnel_in4: endpoint { 2808 remote-endpoint = 2809 <&etm4_out>; 2810 }; 2811 }; 2812 2813 port@5 { 2814 reg = <5>; 2815 apss_funnel_in5: endpoint { 2816 remote-endpoint = 2817 <&etm5_out>; 2818 }; 2819 }; 2820 2821 port@6 { 2822 reg = <6>; 2823 apss_funnel_in6: endpoint { 2824 remote-endpoint = 2825 <&etm6_out>; 2826 }; 2827 }; 2828 2829 port@7 { 2830 reg = <7>; 2831 apss_funnel_in7: endpoint { 2832 remote-endpoint = 2833 <&etm7_out>; 2834 }; 2835 }; 2836 }; 2837 }; 2838 2839 funnel@7810000 { 2840 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2841 reg = <0 0x07810000 0 0x1000>; 2842 2843 clocks = <&aoss_qmp>; 2844 clock-names = "apb_pclk"; 2845 2846 out-ports { 2847 port { 2848 apss_merge_funnel_out: endpoint { 2849 remote-endpoint = 2850 <&funnel2_in5>; 2851 }; 2852 }; 2853 }; 2854 2855 in-ports { 2856 port { 2857 apss_merge_funnel_in: endpoint { 2858 remote-endpoint = 2859 <&apss_funnel_out>; 2860 }; 2861 }; 2862 }; 2863 }; 2864 2865 sdhc_2: sdhci@8804000 { 2866 compatible = "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5"; 2867 reg = <0 0x08804000 0 0x1000>; 2868 2869 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 2870 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 2871 interrupt-names = "hc_irq", "pwr_irq"; 2872 2873 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 2874 <&gcc GCC_SDCC2_APPS_CLK>; 2875 clock-names = "iface", "core"; 2876 iommus = <&apps_smmu 0xa0 0xf>; 2877 2878 status = "disabled"; 2879 }; 2880 2881 qspi: spi@88df000 { 2882 compatible = "qcom,sdm845-qspi", "qcom,qspi-v1"; 2883 reg = <0 0x088df000 0 0x600>; 2884 #address-cells = <1>; 2885 #size-cells = <0>; 2886 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 2887 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 2888 <&gcc GCC_QSPI_CORE_CLK>; 2889 clock-names = "iface", "core"; 2890 status = "disabled"; 2891 }; 2892 2893 slim: slim@171c0000 { 2894 compatible = "qcom,slim-ngd-v2.1.0"; 2895 reg = <0 0x171c0000 0 0x2c000>; 2896 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 2897 2898 qcom,apps-ch-pipes = <0x780000>; 2899 qcom,ea-pc = <0x270>; 2900 status = "okay"; 2901 dmas = <&slimbam 3>, <&slimbam 4>, 2902 <&slimbam 5>, <&slimbam 6>; 2903 dma-names = "rx", "tx", "tx2", "rx2"; 2904 2905 iommus = <&apps_smmu 0x1806 0x0>; 2906 #address-cells = <1>; 2907 #size-cells = <0>; 2908 2909 ngd@1 { 2910 reg = <1>; 2911 #address-cells = <2>; 2912 #size-cells = <0>; 2913 2914 wcd9340_ifd: ifd@0{ 2915 compatible = "slim217,250"; 2916 reg = <0 0>; 2917 }; 2918 2919 wcd9340: codec@1{ 2920 compatible = "slim217,250"; 2921 reg = <1 0>; 2922 slim-ifc-dev = <&wcd9340_ifd>; 2923 2924 #sound-dai-cells = <1>; 2925 2926 interrupts-extended = <&tlmm 54 IRQ_TYPE_LEVEL_HIGH>; 2927 interrupt-controller; 2928 #interrupt-cells = <1>; 2929 2930 #clock-cells = <0>; 2931 clock-frequency = <9600000>; 2932 clock-output-names = "mclk"; 2933 qcom,micbias1-millivolt = <1800>; 2934 qcom,micbias2-millivolt = <1800>; 2935 qcom,micbias3-millivolt = <1800>; 2936 qcom,micbias4-millivolt = <1800>; 2937 2938 #address-cells = <1>; 2939 #size-cells = <1>; 2940 2941 wcdgpio: gpio-controller@42 { 2942 compatible = "qcom,wcd9340-gpio"; 2943 gpio-controller; 2944 #gpio-cells = <2>; 2945 reg = <0x42 0x2>; 2946 }; 2947 2948 swm: swm@c85 { 2949 compatible = "qcom,soundwire-v1.3.0"; 2950 reg = <0xc85 0x40>; 2951 interrupts-extended = <&wcd9340 20>; 2952 2953 qcom,dout-ports = <6>; 2954 qcom,din-ports = <2>; 2955 qcom,ports-sinterval-low =/bits/ 8 <0x07 0x1F 0x3F 0x7 0x1F 0x3F 0x0F 0x0F>; 2956 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0C 0x6 0x12 0x0D 0x07 0x0A >; 2957 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x1F 0x00 0x00 0x1F 0x00 0x00>; 2958 2959 #sound-dai-cells = <1>; 2960 clocks = <&wcd9340>; 2961 clock-names = "iface"; 2962 #address-cells = <2>; 2963 #size-cells = <0>; 2964 2965 2966 }; 2967 }; 2968 }; 2969 }; 2970 2971 sound: sound { 2972 }; 2973 2974 usb_1_hsphy: phy@88e2000 { 2975 compatible = "qcom,sdm845-qusb2-phy"; 2976 reg = <0 0x088e2000 0 0x400>; 2977 status = "disabled"; 2978 #phy-cells = <0>; 2979 2980 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 2981 <&rpmhcc RPMH_CXO_CLK>; 2982 clock-names = "cfg_ahb", "ref"; 2983 2984 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2985 2986 nvmem-cells = <&qusb2p_hstx_trim>; 2987 }; 2988 2989 usb_2_hsphy: phy@88e3000 { 2990 compatible = "qcom,sdm845-qusb2-phy"; 2991 reg = <0 0x088e3000 0 0x400>; 2992 status = "disabled"; 2993 #phy-cells = <0>; 2994 2995 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 2996 <&rpmhcc RPMH_CXO_CLK>; 2997 clock-names = "cfg_ahb", "ref"; 2998 2999 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3000 3001 nvmem-cells = <&qusb2s_hstx_trim>; 3002 }; 3003 3004 usb_1_qmpphy: phy@88e9000 { 3005 compatible = "qcom,sdm845-qmp-usb3-phy"; 3006 reg = <0 0x088e9000 0 0x18c>, 3007 <0 0x088e8000 0 0x10>; 3008 reg-names = "reg-base", "dp_com"; 3009 status = "disabled"; 3010 #clock-cells = <1>; 3011 #address-cells = <2>; 3012 #size-cells = <2>; 3013 ranges; 3014 3015 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3016 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 3017 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 3018 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 3019 clock-names = "aux", "cfg_ahb", "ref", "com_aux"; 3020 3021 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 3022 <&gcc GCC_USB3_PHY_PRIM_BCR>; 3023 reset-names = "phy", "common"; 3024 3025 usb_1_ssphy: lanes@88e9200 { 3026 reg = <0 0x088e9200 0 0x128>, 3027 <0 0x088e9400 0 0x200>, 3028 <0 0x088e9c00 0 0x218>, 3029 <0 0x088e9600 0 0x128>, 3030 <0 0x088e9800 0 0x200>, 3031 <0 0x088e9a00 0 0x100>; 3032 #phy-cells = <0>; 3033 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3034 clock-names = "pipe0"; 3035 clock-output-names = "usb3_phy_pipe_clk_src"; 3036 }; 3037 }; 3038 3039 usb_2_qmpphy: phy@88eb000 { 3040 compatible = "qcom,sdm845-qmp-usb3-uni-phy"; 3041 reg = <0 0x088eb000 0 0x18c>; 3042 status = "disabled"; 3043 #clock-cells = <1>; 3044 #address-cells = <2>; 3045 #size-cells = <2>; 3046 ranges; 3047 3048 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 3049 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 3050 <&gcc GCC_USB3_SEC_CLKREF_CLK>, 3051 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; 3052 clock-names = "aux", "cfg_ahb", "ref", "com_aux"; 3053 3054 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, 3055 <&gcc GCC_USB3_PHY_SEC_BCR>; 3056 reset-names = "phy", "common"; 3057 3058 usb_2_ssphy: lane@88eb200 { 3059 reg = <0 0x088eb200 0 0x128>, 3060 <0 0x088eb400 0 0x1fc>, 3061 <0 0x088eb800 0 0x218>, 3062 <0 0x088eb600 0 0x70>; 3063 #phy-cells = <0>; 3064 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 3065 clock-names = "pipe0"; 3066 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 3067 }; 3068 }; 3069 3070 usb_1: usb@a6f8800 { 3071 compatible = "qcom,sdm845-dwc3", "qcom,dwc3"; 3072 reg = <0 0x0a6f8800 0 0x400>; 3073 status = "disabled"; 3074 #address-cells = <2>; 3075 #size-cells = <2>; 3076 ranges; 3077 dma-ranges; 3078 3079 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3080 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3081 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3082 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3083 <&gcc GCC_USB30_PRIM_SLEEP_CLK>; 3084 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 3085 "sleep"; 3086 3087 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3088 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3089 assigned-clock-rates = <19200000>, <150000000>; 3090 3091 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 3092 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>, 3093 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>, 3094 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>; 3095 interrupt-names = "hs_phy_irq", "ss_phy_irq", 3096 "dm_hs_phy_irq", "dp_hs_phy_irq"; 3097 3098 power-domains = <&gcc USB30_PRIM_GDSC>; 3099 3100 resets = <&gcc GCC_USB30_PRIM_BCR>; 3101 3102 usb_1_dwc3: dwc3@a600000 { 3103 compatible = "snps,dwc3"; 3104 reg = <0 0x0a600000 0 0xcd00>; 3105 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 3106 iommus = <&apps_smmu 0x740 0>; 3107 snps,dis_u2_susphy_quirk; 3108 snps,dis_enblslpm_quirk; 3109 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 3110 phy-names = "usb2-phy", "usb3-phy"; 3111 }; 3112 }; 3113 3114 usb_2: usb@a8f8800 { 3115 compatible = "qcom,sdm845-dwc3", "qcom,dwc3"; 3116 reg = <0 0x0a8f8800 0 0x400>; 3117 status = "disabled"; 3118 #address-cells = <2>; 3119 #size-cells = <2>; 3120 ranges; 3121 dma-ranges; 3122 3123 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 3124 <&gcc GCC_USB30_SEC_MASTER_CLK>, 3125 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 3126 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3127 <&gcc GCC_USB30_SEC_SLEEP_CLK>; 3128 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 3129 "sleep"; 3130 3131 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3132 <&gcc GCC_USB30_SEC_MASTER_CLK>; 3133 assigned-clock-rates = <19200000>, <150000000>; 3134 3135 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 3136 <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>, 3137 <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>, 3138 <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>; 3139 interrupt-names = "hs_phy_irq", "ss_phy_irq", 3140 "dm_hs_phy_irq", "dp_hs_phy_irq"; 3141 3142 power-domains = <&gcc USB30_SEC_GDSC>; 3143 3144 resets = <&gcc GCC_USB30_SEC_BCR>; 3145 3146 usb_2_dwc3: dwc3@a800000 { 3147 compatible = "snps,dwc3"; 3148 reg = <0 0x0a800000 0 0xcd00>; 3149 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 3150 iommus = <&apps_smmu 0x760 0>; 3151 snps,dis_u2_susphy_quirk; 3152 snps,dis_enblslpm_quirk; 3153 phys = <&usb_2_hsphy>, <&usb_2_ssphy>; 3154 phy-names = "usb2-phy", "usb3-phy"; 3155 }; 3156 }; 3157 3158 venus: video-codec@aa00000 { 3159 compatible = "qcom,sdm845-venus-v2"; 3160 reg = <0 0x0aa00000 0 0xff000>; 3161 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 3162 power-domains = <&videocc VENUS_GDSC>, 3163 <&videocc VCODEC0_GDSC>, 3164 <&videocc VCODEC1_GDSC>; 3165 power-domain-names = "venus", "vcodec0", "vcodec1"; 3166 clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>, 3167 <&videocc VIDEO_CC_VENUS_AHB_CLK>, 3168 <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>, 3169 <&videocc VIDEO_CC_VCODEC0_CORE_CLK>, 3170 <&videocc VIDEO_CC_VCODEC0_AXI_CLK>, 3171 <&videocc VIDEO_CC_VCODEC1_CORE_CLK>, 3172 <&videocc VIDEO_CC_VCODEC1_AXI_CLK>; 3173 clock-names = "core", "iface", "bus", 3174 "vcodec0_core", "vcodec0_bus", 3175 "vcodec1_core", "vcodec1_bus"; 3176 iommus = <&apps_smmu 0x10a0 0x8>, 3177 <&apps_smmu 0x10b0 0x0>; 3178 memory-region = <&venus_mem>; 3179 3180 video-core0 { 3181 compatible = "venus-decoder"; 3182 }; 3183 3184 video-core1 { 3185 compatible = "venus-encoder"; 3186 }; 3187 }; 3188 3189 videocc: clock-controller@ab00000 { 3190 compatible = "qcom,sdm845-videocc"; 3191 reg = <0 0x0ab00000 0 0x10000>; 3192 clocks = <&rpmhcc RPMH_CXO_CLK>; 3193 clock-names = "bi_tcxo"; 3194 #clock-cells = <1>; 3195 #power-domain-cells = <1>; 3196 #reset-cells = <1>; 3197 }; 3198 3199 mdss: mdss@ae00000 { 3200 compatible = "qcom,sdm845-mdss"; 3201 reg = <0 0x0ae00000 0 0x1000>; 3202 reg-names = "mdss"; 3203 3204 power-domains = <&dispcc MDSS_GDSC>; 3205 3206 clocks = <&gcc GCC_DISP_AHB_CLK>, 3207 <&gcc GCC_DISP_AXI_CLK>, 3208 <&dispcc DISP_CC_MDSS_MDP_CLK>; 3209 clock-names = "iface", "bus", "core"; 3210 3211 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; 3212 assigned-clock-rates = <300000000>; 3213 3214 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 3215 interrupt-controller; 3216 #interrupt-cells = <1>; 3217 3218 iommus = <&apps_smmu 0x880 0x8>, 3219 <&apps_smmu 0xc80 0x8>; 3220 3221 status = "disabled"; 3222 3223 #address-cells = <2>; 3224 #size-cells = <2>; 3225 ranges; 3226 3227 mdss_mdp: mdp@ae01000 { 3228 compatible = "qcom,sdm845-dpu"; 3229 reg = <0 0x0ae01000 0 0x8f000>, 3230 <0 0x0aeb0000 0 0x2008>; 3231 reg-names = "mdp", "vbif"; 3232 3233 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3234 <&dispcc DISP_CC_MDSS_AXI_CLK>, 3235 <&dispcc DISP_CC_MDSS_MDP_CLK>, 3236 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3237 clock-names = "iface", "bus", "core", "vsync"; 3238 3239 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, 3240 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3241 assigned-clock-rates = <300000000>, 3242 <19200000>; 3243 3244 interrupt-parent = <&mdss>; 3245 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; 3246 3247 status = "disabled"; 3248 3249 ports { 3250 #address-cells = <1>; 3251 #size-cells = <0>; 3252 3253 port@0 { 3254 reg = <0>; 3255 dpu_intf1_out: endpoint { 3256 remote-endpoint = <&dsi0_in>; 3257 }; 3258 }; 3259 3260 port@1 { 3261 reg = <1>; 3262 dpu_intf2_out: endpoint { 3263 remote-endpoint = <&dsi1_in>; 3264 }; 3265 }; 3266 }; 3267 }; 3268 3269 dsi0: dsi@ae94000 { 3270 compatible = "qcom,mdss-dsi-ctrl"; 3271 reg = <0 0x0ae94000 0 0x400>; 3272 reg-names = "dsi_ctrl"; 3273 3274 interrupt-parent = <&mdss>; 3275 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; 3276 3277 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 3278 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 3279 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 3280 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 3281 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3282 <&dispcc DISP_CC_MDSS_AXI_CLK>; 3283 clock-names = "byte", 3284 "byte_intf", 3285 "pixel", 3286 "core", 3287 "iface", 3288 "bus"; 3289 3290 phys = <&dsi0_phy>; 3291 phy-names = "dsi"; 3292 3293 status = "disabled"; 3294 3295 ports { 3296 #address-cells = <1>; 3297 #size-cells = <0>; 3298 3299 port@0 { 3300 reg = <0>; 3301 dsi0_in: endpoint { 3302 remote-endpoint = <&dpu_intf1_out>; 3303 }; 3304 }; 3305 3306 port@1 { 3307 reg = <1>; 3308 dsi0_out: endpoint { 3309 }; 3310 }; 3311 }; 3312 }; 3313 3314 dsi0_phy: dsi-phy@ae94400 { 3315 compatible = "qcom,dsi-phy-10nm"; 3316 reg = <0 0x0ae94400 0 0x200>, 3317 <0 0x0ae94600 0 0x280>, 3318 <0 0x0ae94a00 0 0x1e0>; 3319 reg-names = "dsi_phy", 3320 "dsi_phy_lane", 3321 "dsi_pll"; 3322 3323 #clock-cells = <1>; 3324 #phy-cells = <0>; 3325 3326 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3327 <&rpmhcc RPMH_CXO_CLK>; 3328 clock-names = "iface", "ref"; 3329 3330 status = "disabled"; 3331 }; 3332 3333 dsi1: dsi@ae96000 { 3334 compatible = "qcom,mdss-dsi-ctrl"; 3335 reg = <0 0x0ae96000 0 0x400>; 3336 reg-names = "dsi_ctrl"; 3337 3338 interrupt-parent = <&mdss>; 3339 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; 3340 3341 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 3342 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 3343 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 3344 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 3345 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3346 <&dispcc DISP_CC_MDSS_AXI_CLK>; 3347 clock-names = "byte", 3348 "byte_intf", 3349 "pixel", 3350 "core", 3351 "iface", 3352 "bus"; 3353 3354 phys = <&dsi1_phy>; 3355 phy-names = "dsi"; 3356 3357 status = "disabled"; 3358 3359 ports { 3360 #address-cells = <1>; 3361 #size-cells = <0>; 3362 3363 port@0 { 3364 reg = <0>; 3365 dsi1_in: endpoint { 3366 remote-endpoint = <&dpu_intf2_out>; 3367 }; 3368 }; 3369 3370 port@1 { 3371 reg = <1>; 3372 dsi1_out: endpoint { 3373 }; 3374 }; 3375 }; 3376 }; 3377 3378 dsi1_phy: dsi-phy@ae96400 { 3379 compatible = "qcom,dsi-phy-10nm"; 3380 reg = <0 0x0ae96400 0 0x200>, 3381 <0 0x0ae96600 0 0x280>, 3382 <0 0x0ae96a00 0 0x10e>; 3383 reg-names = "dsi_phy", 3384 "dsi_phy_lane", 3385 "dsi_pll"; 3386 3387 #clock-cells = <1>; 3388 #phy-cells = <0>; 3389 3390 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3391 <&rpmhcc RPMH_CXO_CLK>; 3392 clock-names = "iface", "ref"; 3393 3394 status = "disabled"; 3395 }; 3396 }; 3397 3398 gpu: gpu@5000000 { 3399 compatible = "qcom,adreno-630.2", "qcom,adreno"; 3400 #stream-id-cells = <16>; 3401 3402 reg = <0 0x5000000 0 0x40000>, <0 0x509e000 0 0x10>; 3403 reg-names = "kgsl_3d0_reg_memory", "cx_mem"; 3404 3405 /* 3406 * Look ma, no clocks! The GPU clocks and power are 3407 * controlled entirely by the GMU 3408 */ 3409 3410 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 3411 3412 iommus = <&adreno_smmu 0>; 3413 3414 operating-points-v2 = <&gpu_opp_table>; 3415 3416 qcom,gmu = <&gmu>; 3417 3418 gpu_opp_table: opp-table { 3419 compatible = "operating-points-v2"; 3420 3421 opp-710000000 { 3422 opp-hz = /bits/ 64 <710000000>; 3423 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3424 }; 3425 3426 opp-675000000 { 3427 opp-hz = /bits/ 64 <675000000>; 3428 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3429 }; 3430 3431 opp-596000000 { 3432 opp-hz = /bits/ 64 <596000000>; 3433 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3434 }; 3435 3436 opp-520000000 { 3437 opp-hz = /bits/ 64 <520000000>; 3438 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3439 }; 3440 3441 opp-414000000 { 3442 opp-hz = /bits/ 64 <414000000>; 3443 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3444 }; 3445 3446 opp-342000000 { 3447 opp-hz = /bits/ 64 <342000000>; 3448 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3449 }; 3450 3451 opp-257000000 { 3452 opp-hz = /bits/ 64 <257000000>; 3453 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3454 }; 3455 }; 3456 }; 3457 3458 adreno_smmu: iommu@5040000 { 3459 compatible = "qcom,sdm845-smmu-v2", "qcom,smmu-v2"; 3460 reg = <0 0x5040000 0 0x10000>; 3461 #iommu-cells = <1>; 3462 #global-interrupts = <2>; 3463 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 3464 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 3465 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, 3466 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, 3467 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>, 3468 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>, 3469 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>, 3470 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>, 3471 <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>, 3472 <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>; 3473 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 3474 <&gcc GCC_GPU_CFG_AHB_CLK>; 3475 clock-names = "bus", "iface"; 3476 3477 power-domains = <&gpucc GPU_CX_GDSC>; 3478 }; 3479 3480 gmu: gmu@506a000 { 3481 compatible="qcom,adreno-gmu-630.2", "qcom,adreno-gmu"; 3482 3483 reg = <0 0x506a000 0 0x30000>, 3484 <0 0xb280000 0 0x10000>, 3485 <0 0xb480000 0 0x10000>; 3486 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; 3487 3488 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 3489 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 3490 interrupt-names = "hfi", "gmu"; 3491 3492 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 3493 <&gpucc GPU_CC_CXO_CLK>, 3494 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 3495 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 3496 clock-names = "gmu", "cxo", "axi", "memnoc"; 3497 3498 power-domains = <&gpucc GPU_CX_GDSC>, 3499 <&gpucc GPU_GX_GDSC>; 3500 power-domain-names = "cx", "gx"; 3501 3502 iommus = <&adreno_smmu 5>; 3503 3504 operating-points-v2 = <&gmu_opp_table>; 3505 3506 gmu_opp_table: opp-table { 3507 compatible = "operating-points-v2"; 3508 3509 opp-400000000 { 3510 opp-hz = /bits/ 64 <400000000>; 3511 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3512 }; 3513 3514 opp-200000000 { 3515 opp-hz = /bits/ 64 <200000000>; 3516 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3517 }; 3518 }; 3519 }; 3520 3521 dispcc: clock-controller@af00000 { 3522 compatible = "qcom,sdm845-dispcc"; 3523 reg = <0 0x0af00000 0 0x10000>; 3524 clocks = <&rpmhcc RPMH_CXO_CLK>, 3525 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 3526 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, 3527 <&dsi0_phy 0>, 3528 <&dsi0_phy 1>, 3529 <&dsi1_phy 0>, 3530 <&dsi1_phy 1>, 3531 <0>, 3532 <0>; 3533 clock-names = "bi_tcxo", 3534 "gcc_disp_gpll0_clk_src", 3535 "gcc_disp_gpll0_div_clk_src", 3536 "dsi0_phy_pll_out_byteclk", 3537 "dsi0_phy_pll_out_dsiclk", 3538 "dsi1_phy_pll_out_byteclk", 3539 "dsi1_phy_pll_out_dsiclk", 3540 "dp_link_clk_divsel_ten", 3541 "dp_vco_divided_clk_src_mux"; 3542 #clock-cells = <1>; 3543 #reset-cells = <1>; 3544 #power-domain-cells = <1>; 3545 }; 3546 3547 pdc_intc: interrupt-controller@b220000 { 3548 compatible = "qcom,sdm845-pdc", "qcom,pdc"; 3549 reg = <0 0x0b220000 0 0x30000>; 3550 qcom,pdc-ranges = <0 480 94>, <94 609 15>, <115 630 7>; 3551 #interrupt-cells = <2>; 3552 interrupt-parent = <&intc>; 3553 interrupt-controller; 3554 }; 3555 3556 pdc_reset: reset-controller@b2e0000 { 3557 compatible = "qcom,sdm845-pdc-global"; 3558 reg = <0 0x0b2e0000 0 0x20000>; 3559 #reset-cells = <1>; 3560 }; 3561 3562 tsens0: thermal-sensor@c263000 { 3563 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; 3564 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 3565 <0 0x0c222000 0 0x1ff>; /* SROT */ 3566 #qcom,sensors = <13>; 3567 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 3568 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 3569 interrupt-names = "uplow", "critical"; 3570 #thermal-sensor-cells = <1>; 3571 }; 3572 3573 tsens1: thermal-sensor@c265000 { 3574 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; 3575 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 3576 <0 0x0c223000 0 0x1ff>; /* SROT */ 3577 #qcom,sensors = <8>; 3578 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 3579 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 3580 interrupt-names = "uplow", "critical"; 3581 #thermal-sensor-cells = <1>; 3582 }; 3583 3584 aoss_reset: reset-controller@c2a0000 { 3585 compatible = "qcom,sdm845-aoss-cc"; 3586 reg = <0 0x0c2a0000 0 0x31000>; 3587 #reset-cells = <1>; 3588 }; 3589 3590 aoss_qmp: qmp@c300000 { 3591 compatible = "qcom,sdm845-aoss-qmp"; 3592 reg = <0 0x0c300000 0 0x100000>; 3593 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; 3594 mboxes = <&apss_shared 0>; 3595 3596 #clock-cells = <0>; 3597 #power-domain-cells = <1>; 3598 3599 cx_cdev: cx { 3600 #cooling-cells = <2>; 3601 }; 3602 3603 ebi_cdev: ebi { 3604 #cooling-cells = <2>; 3605 }; 3606 }; 3607 3608 spmi_bus: spmi@c440000 { 3609 compatible = "qcom,spmi-pmic-arb"; 3610 reg = <0 0x0c440000 0 0x1100>, 3611 <0 0x0c600000 0 0x2000000>, 3612 <0 0x0e600000 0 0x100000>, 3613 <0 0x0e700000 0 0xa0000>, 3614 <0 0x0c40a000 0 0x26000>; 3615 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 3616 interrupt-names = "periph_irq"; 3617 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>; 3618 qcom,ee = <0>; 3619 qcom,channel = <0>; 3620 #address-cells = <2>; 3621 #size-cells = <0>; 3622 interrupt-controller; 3623 #interrupt-cells = <4>; 3624 cell-index = <0>; 3625 }; 3626 3627 apps_smmu: iommu@15000000 { 3628 compatible = "qcom,sdm845-smmu-500", "arm,mmu-500"; 3629 reg = <0 0x15000000 0 0x80000>; 3630 #iommu-cells = <2>; 3631 #global-interrupts = <1>; 3632 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3633 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 3634 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3635 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3636 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3637 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3638 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3639 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3640 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3641 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3642 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3643 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3644 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3645 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3646 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3647 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3648 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3649 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3650 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3651 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3652 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3653 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3654 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3655 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3656 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3657 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3658 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3659 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3660 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3661 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3662 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3663 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3664 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3665 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3666 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3667 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3668 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3669 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3670 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3671 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3672 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3673 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3674 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3675 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3676 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3677 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3678 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3679 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3680 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3681 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3682 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3683 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3684 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3685 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3686 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3687 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3688 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3689 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3690 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3691 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3692 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3693 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3694 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3695 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3696 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>; 3697 }; 3698 3699 lpasscc: clock-controller@17014000 { 3700 compatible = "qcom,sdm845-lpasscc"; 3701 reg = <0 0x17014000 0 0x1f004>, <0 0x17300000 0 0x200>; 3702 reg-names = "cc", "qdsp6ss"; 3703 #clock-cells = <1>; 3704 status = "disabled"; 3705 }; 3706 3707 gladiator_noc: interconnect@17900000 { 3708 compatible = "qcom,sdm845-gladiator-noc"; 3709 reg = <0 0x17900000 0 0xd080>; 3710 #interconnect-cells = <1>; 3711 qcom,bcm-voters = <&apps_bcm_voter>; 3712 }; 3713 3714 watchdog@17980000 { 3715 compatible = "qcom,apss-wdt-sdm845", "qcom,kpss-wdt"; 3716 reg = <0 0x17980000 0 0x1000>; 3717 clocks = <&sleep_clk>; 3718 }; 3719 3720 apss_shared: mailbox@17990000 { 3721 compatible = "qcom,sdm845-apss-shared"; 3722 reg = <0 0x17990000 0 0x1000>; 3723 #mbox-cells = <1>; 3724 }; 3725 3726 apps_rsc: rsc@179c0000 { 3727 label = "apps_rsc"; 3728 compatible = "qcom,rpmh-rsc"; 3729 reg = <0 0x179c0000 0 0x10000>, 3730 <0 0x179d0000 0 0x10000>, 3731 <0 0x179e0000 0 0x10000>; 3732 reg-names = "drv-0", "drv-1", "drv-2"; 3733 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3734 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3735 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3736 qcom,tcs-offset = <0xd00>; 3737 qcom,drv-id = <2>; 3738 qcom,tcs-config = <ACTIVE_TCS 2>, 3739 <SLEEP_TCS 3>, 3740 <WAKE_TCS 3>, 3741 <CONTROL_TCS 1>; 3742 3743 apps_bcm_voter: bcm-voter { 3744 compatible = "qcom,bcm-voter"; 3745 }; 3746 3747 rpmhcc: clock-controller { 3748 compatible = "qcom,sdm845-rpmh-clk"; 3749 #clock-cells = <1>; 3750 clock-names = "xo"; 3751 clocks = <&xo_board>; 3752 }; 3753 3754 rpmhpd: power-controller { 3755 compatible = "qcom,sdm845-rpmhpd"; 3756 #power-domain-cells = <1>; 3757 operating-points-v2 = <&rpmhpd_opp_table>; 3758 3759 rpmhpd_opp_table: opp-table { 3760 compatible = "operating-points-v2"; 3761 3762 rpmhpd_opp_ret: opp1 { 3763 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3764 }; 3765 3766 rpmhpd_opp_min_svs: opp2 { 3767 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3768 }; 3769 3770 rpmhpd_opp_low_svs: opp3 { 3771 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3772 }; 3773 3774 rpmhpd_opp_svs: opp4 { 3775 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3776 }; 3777 3778 rpmhpd_opp_svs_l1: opp5 { 3779 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3780 }; 3781 3782 rpmhpd_opp_nom: opp6 { 3783 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3784 }; 3785 3786 rpmhpd_opp_nom_l1: opp7 { 3787 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3788 }; 3789 3790 rpmhpd_opp_nom_l2: opp8 { 3791 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 3792 }; 3793 3794 rpmhpd_opp_turbo: opp9 { 3795 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3796 }; 3797 3798 rpmhpd_opp_turbo_l1: opp10 { 3799 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3800 }; 3801 }; 3802 }; 3803 }; 3804 3805 intc: interrupt-controller@17a00000 { 3806 compatible = "arm,gic-v3"; 3807 #address-cells = <2>; 3808 #size-cells = <2>; 3809 ranges; 3810 #interrupt-cells = <3>; 3811 interrupt-controller; 3812 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 3813 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 3814 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3815 3816 msi-controller@17a40000 { 3817 compatible = "arm,gic-v3-its"; 3818 msi-controller; 3819 #msi-cells = <1>; 3820 reg = <0 0x17a40000 0 0x20000>; 3821 status = "disabled"; 3822 }; 3823 }; 3824 3825 slimbam: dma@17184000 { 3826 compatible = "qcom,bam-v1.7.0"; 3827 qcom,controlled-remotely; 3828 reg = <0 0x17184000 0 0x2a000>; 3829 num-channels = <31>; 3830 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 3831 #dma-cells = <1>; 3832 qcom,ee = <1>; 3833 qcom,num-ees = <2>; 3834 iommus = <&apps_smmu 0x1806 0x0>; 3835 }; 3836 3837 timer@17c90000 { 3838 #address-cells = <2>; 3839 #size-cells = <2>; 3840 ranges; 3841 compatible = "arm,armv7-timer-mem"; 3842 reg = <0 0x17c90000 0 0x1000>; 3843 3844 frame@17ca0000 { 3845 frame-number = <0>; 3846 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 3847 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3848 reg = <0 0x17ca0000 0 0x1000>, 3849 <0 0x17cb0000 0 0x1000>; 3850 }; 3851 3852 frame@17cc0000 { 3853 frame-number = <1>; 3854 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 3855 reg = <0 0x17cc0000 0 0x1000>; 3856 status = "disabled"; 3857 }; 3858 3859 frame@17cd0000 { 3860 frame-number = <2>; 3861 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3862 reg = <0 0x17cd0000 0 0x1000>; 3863 status = "disabled"; 3864 }; 3865 3866 frame@17ce0000 { 3867 frame-number = <3>; 3868 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3869 reg = <0 0x17ce0000 0 0x1000>; 3870 status = "disabled"; 3871 }; 3872 3873 frame@17cf0000 { 3874 frame-number = <4>; 3875 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3876 reg = <0 0x17cf0000 0 0x1000>; 3877 status = "disabled"; 3878 }; 3879 3880 frame@17d00000 { 3881 frame-number = <5>; 3882 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3883 reg = <0 0x17d00000 0 0x1000>; 3884 status = "disabled"; 3885 }; 3886 3887 frame@17d10000 { 3888 frame-number = <6>; 3889 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3890 reg = <0 0x17d10000 0 0x1000>; 3891 status = "disabled"; 3892 }; 3893 }; 3894 3895 osm_l3: interconnect@17d41000 { 3896 compatible = "qcom,sdm845-osm-l3"; 3897 reg = <0 0x17d41000 0 0x1400>; 3898 3899 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 3900 clock-names = "xo", "alternate"; 3901 3902 #interconnect-cells = <1>; 3903 }; 3904 3905 cpufreq_hw: cpufreq@17d43000 { 3906 compatible = "qcom,cpufreq-hw"; 3907 reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>; 3908 reg-names = "freq-domain0", "freq-domain1"; 3909 3910 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 3911 clock-names = "xo", "alternate"; 3912 3913 #freq-domain-cells = <1>; 3914 }; 3915 3916 wifi: wifi@18800000 { 3917 compatible = "qcom,wcn3990-wifi"; 3918 status = "disabled"; 3919 reg = <0 0x18800000 0 0x800000>; 3920 reg-names = "membase"; 3921 memory-region = <&wlan_msa_mem>; 3922 clock-names = "cxo_ref_clk_pin"; 3923 clocks = <&rpmhcc RPMH_RF_CLK2>; 3924 interrupts = 3925 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 3926 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 3927 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 3928 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 3929 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 3930 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 3931 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 3932 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 3933 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 3934 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 3935 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 3936 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 3937 iommus = <&apps_smmu 0x0040 0x1>; 3938 }; 3939 }; 3940 3941 thermal-zones { 3942 cpu0-thermal { 3943 polling-delay-passive = <250>; 3944 polling-delay = <1000>; 3945 3946 thermal-sensors = <&tsens0 1>; 3947 3948 trips { 3949 cpu0_alert0: trip-point0 { 3950 temperature = <90000>; 3951 hysteresis = <2000>; 3952 type = "passive"; 3953 }; 3954 3955 cpu0_alert1: trip-point1 { 3956 temperature = <95000>; 3957 hysteresis = <2000>; 3958 type = "passive"; 3959 }; 3960 3961 cpu0_crit: cpu_crit { 3962 temperature = <110000>; 3963 hysteresis = <1000>; 3964 type = "critical"; 3965 }; 3966 }; 3967 3968 cooling-maps { 3969 map0 { 3970 trip = <&cpu0_alert0>; 3971 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3972 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3973 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3974 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3975 }; 3976 map1 { 3977 trip = <&cpu0_alert1>; 3978 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3979 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3980 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3981 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3982 }; 3983 }; 3984 }; 3985 3986 cpu1-thermal { 3987 polling-delay-passive = <250>; 3988 polling-delay = <1000>; 3989 3990 thermal-sensors = <&tsens0 2>; 3991 3992 trips { 3993 cpu1_alert0: trip-point0 { 3994 temperature = <90000>; 3995 hysteresis = <2000>; 3996 type = "passive"; 3997 }; 3998 3999 cpu1_alert1: trip-point1 { 4000 temperature = <95000>; 4001 hysteresis = <2000>; 4002 type = "passive"; 4003 }; 4004 4005 cpu1_crit: cpu_crit { 4006 temperature = <110000>; 4007 hysteresis = <1000>; 4008 type = "critical"; 4009 }; 4010 }; 4011 4012 cooling-maps { 4013 map0 { 4014 trip = <&cpu1_alert0>; 4015 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4016 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4017 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4018 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4019 }; 4020 map1 { 4021 trip = <&cpu1_alert1>; 4022 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4023 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4024 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4025 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4026 }; 4027 }; 4028 }; 4029 4030 cpu2-thermal { 4031 polling-delay-passive = <250>; 4032 polling-delay = <1000>; 4033 4034 thermal-sensors = <&tsens0 3>; 4035 4036 trips { 4037 cpu2_alert0: trip-point0 { 4038 temperature = <90000>; 4039 hysteresis = <2000>; 4040 type = "passive"; 4041 }; 4042 4043 cpu2_alert1: trip-point1 { 4044 temperature = <95000>; 4045 hysteresis = <2000>; 4046 type = "passive"; 4047 }; 4048 4049 cpu2_crit: cpu_crit { 4050 temperature = <110000>; 4051 hysteresis = <1000>; 4052 type = "critical"; 4053 }; 4054 }; 4055 4056 cooling-maps { 4057 map0 { 4058 trip = <&cpu2_alert0>; 4059 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4060 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4061 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4062 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4063 }; 4064 map1 { 4065 trip = <&cpu2_alert1>; 4066 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4067 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4068 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4069 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4070 }; 4071 }; 4072 }; 4073 4074 cpu3-thermal { 4075 polling-delay-passive = <250>; 4076 polling-delay = <1000>; 4077 4078 thermal-sensors = <&tsens0 4>; 4079 4080 trips { 4081 cpu3_alert0: trip-point0 { 4082 temperature = <90000>; 4083 hysteresis = <2000>; 4084 type = "passive"; 4085 }; 4086 4087 cpu3_alert1: trip-point1 { 4088 temperature = <95000>; 4089 hysteresis = <2000>; 4090 type = "passive"; 4091 }; 4092 4093 cpu3_crit: cpu_crit { 4094 temperature = <110000>; 4095 hysteresis = <1000>; 4096 type = "critical"; 4097 }; 4098 }; 4099 4100 cooling-maps { 4101 map0 { 4102 trip = <&cpu3_alert0>; 4103 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4104 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4105 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4106 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4107 }; 4108 map1 { 4109 trip = <&cpu3_alert1>; 4110 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4111 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4112 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4113 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4114 }; 4115 }; 4116 }; 4117 4118 cpu4-thermal { 4119 polling-delay-passive = <250>; 4120 polling-delay = <1000>; 4121 4122 thermal-sensors = <&tsens0 7>; 4123 4124 trips { 4125 cpu4_alert0: trip-point0 { 4126 temperature = <90000>; 4127 hysteresis = <2000>; 4128 type = "passive"; 4129 }; 4130 4131 cpu4_alert1: trip-point1 { 4132 temperature = <95000>; 4133 hysteresis = <2000>; 4134 type = "passive"; 4135 }; 4136 4137 cpu4_crit: cpu_crit { 4138 temperature = <110000>; 4139 hysteresis = <1000>; 4140 type = "critical"; 4141 }; 4142 }; 4143 4144 cooling-maps { 4145 map0 { 4146 trip = <&cpu4_alert0>; 4147 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4148 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4149 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4150 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4151 }; 4152 map1 { 4153 trip = <&cpu4_alert1>; 4154 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4155 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4156 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4157 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4158 }; 4159 }; 4160 }; 4161 4162 cpu5-thermal { 4163 polling-delay-passive = <250>; 4164 polling-delay = <1000>; 4165 4166 thermal-sensors = <&tsens0 8>; 4167 4168 trips { 4169 cpu5_alert0: trip-point0 { 4170 temperature = <90000>; 4171 hysteresis = <2000>; 4172 type = "passive"; 4173 }; 4174 4175 cpu5_alert1: trip-point1 { 4176 temperature = <95000>; 4177 hysteresis = <2000>; 4178 type = "passive"; 4179 }; 4180 4181 cpu5_crit: cpu_crit { 4182 temperature = <110000>; 4183 hysteresis = <1000>; 4184 type = "critical"; 4185 }; 4186 }; 4187 4188 cooling-maps { 4189 map0 { 4190 trip = <&cpu5_alert0>; 4191 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4192 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4193 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4194 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4195 }; 4196 map1 { 4197 trip = <&cpu5_alert1>; 4198 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4199 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4200 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4201 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4202 }; 4203 }; 4204 }; 4205 4206 cpu6-thermal { 4207 polling-delay-passive = <250>; 4208 polling-delay = <1000>; 4209 4210 thermal-sensors = <&tsens0 9>; 4211 4212 trips { 4213 cpu6_alert0: trip-point0 { 4214 temperature = <90000>; 4215 hysteresis = <2000>; 4216 type = "passive"; 4217 }; 4218 4219 cpu6_alert1: trip-point1 { 4220 temperature = <95000>; 4221 hysteresis = <2000>; 4222 type = "passive"; 4223 }; 4224 4225 cpu6_crit: cpu_crit { 4226 temperature = <110000>; 4227 hysteresis = <1000>; 4228 type = "critical"; 4229 }; 4230 }; 4231 4232 cooling-maps { 4233 map0 { 4234 trip = <&cpu6_alert0>; 4235 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4236 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4237 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4238 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4239 }; 4240 map1 { 4241 trip = <&cpu6_alert1>; 4242 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4243 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4244 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4245 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4246 }; 4247 }; 4248 }; 4249 4250 cpu7-thermal { 4251 polling-delay-passive = <250>; 4252 polling-delay = <1000>; 4253 4254 thermal-sensors = <&tsens0 10>; 4255 4256 trips { 4257 cpu7_alert0: trip-point0 { 4258 temperature = <90000>; 4259 hysteresis = <2000>; 4260 type = "passive"; 4261 }; 4262 4263 cpu7_alert1: trip-point1 { 4264 temperature = <95000>; 4265 hysteresis = <2000>; 4266 type = "passive"; 4267 }; 4268 4269 cpu7_crit: cpu_crit { 4270 temperature = <110000>; 4271 hysteresis = <1000>; 4272 type = "critical"; 4273 }; 4274 }; 4275 4276 cooling-maps { 4277 map0 { 4278 trip = <&cpu7_alert0>; 4279 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4280 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4281 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4282 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4283 }; 4284 map1 { 4285 trip = <&cpu7_alert1>; 4286 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4287 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4288 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4289 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4290 }; 4291 }; 4292 }; 4293 4294 aoss0-thermal { 4295 polling-delay-passive = <250>; 4296 polling-delay = <1000>; 4297 4298 thermal-sensors = <&tsens0 0>; 4299 4300 trips { 4301 aoss0_alert0: trip-point0 { 4302 temperature = <90000>; 4303 hysteresis = <2000>; 4304 type = "hot"; 4305 }; 4306 }; 4307 }; 4308 4309 cluster0-thermal { 4310 polling-delay-passive = <250>; 4311 polling-delay = <1000>; 4312 4313 thermal-sensors = <&tsens0 5>; 4314 4315 trips { 4316 cluster0_alert0: trip-point0 { 4317 temperature = <90000>; 4318 hysteresis = <2000>; 4319 type = "hot"; 4320 }; 4321 cluster0_crit: cluster0_crit { 4322 temperature = <110000>; 4323 hysteresis = <2000>; 4324 type = "critical"; 4325 }; 4326 }; 4327 }; 4328 4329 cluster1-thermal { 4330 polling-delay-passive = <250>; 4331 polling-delay = <1000>; 4332 4333 thermal-sensors = <&tsens0 6>; 4334 4335 trips { 4336 cluster1_alert0: trip-point0 { 4337 temperature = <90000>; 4338 hysteresis = <2000>; 4339 type = "hot"; 4340 }; 4341 cluster1_crit: cluster1_crit { 4342 temperature = <110000>; 4343 hysteresis = <2000>; 4344 type = "critical"; 4345 }; 4346 }; 4347 }; 4348 4349 gpu-thermal-top { 4350 polling-delay-passive = <250>; 4351 polling-delay = <1000>; 4352 4353 thermal-sensors = <&tsens0 11>; 4354 4355 trips { 4356 gpu1_alert0: trip-point0 { 4357 temperature = <90000>; 4358 hysteresis = <2000>; 4359 type = "hot"; 4360 }; 4361 }; 4362 }; 4363 4364 gpu-thermal-bottom { 4365 polling-delay-passive = <250>; 4366 polling-delay = <1000>; 4367 4368 thermal-sensors = <&tsens0 12>; 4369 4370 trips { 4371 gpu2_alert0: trip-point0 { 4372 temperature = <90000>; 4373 hysteresis = <2000>; 4374 type = "hot"; 4375 }; 4376 }; 4377 }; 4378 4379 aoss1-thermal { 4380 polling-delay-passive = <250>; 4381 polling-delay = <1000>; 4382 4383 thermal-sensors = <&tsens1 0>; 4384 4385 trips { 4386 aoss1_alert0: trip-point0 { 4387 temperature = <90000>; 4388 hysteresis = <2000>; 4389 type = "hot"; 4390 }; 4391 }; 4392 }; 4393 4394 q6-modem-thermal { 4395 polling-delay-passive = <250>; 4396 polling-delay = <1000>; 4397 4398 thermal-sensors = <&tsens1 1>; 4399 4400 trips { 4401 q6_modem_alert0: trip-point0 { 4402 temperature = <90000>; 4403 hysteresis = <2000>; 4404 type = "hot"; 4405 }; 4406 }; 4407 }; 4408 4409 mem-thermal { 4410 polling-delay-passive = <250>; 4411 polling-delay = <1000>; 4412 4413 thermal-sensors = <&tsens1 2>; 4414 4415 trips { 4416 mem_alert0: trip-point0 { 4417 temperature = <90000>; 4418 hysteresis = <2000>; 4419 type = "hot"; 4420 }; 4421 }; 4422 }; 4423 4424 wlan-thermal { 4425 polling-delay-passive = <250>; 4426 polling-delay = <1000>; 4427 4428 thermal-sensors = <&tsens1 3>; 4429 4430 trips { 4431 wlan_alert0: trip-point0 { 4432 temperature = <90000>; 4433 hysteresis = <2000>; 4434 type = "hot"; 4435 }; 4436 }; 4437 }; 4438 4439 q6-hvx-thermal { 4440 polling-delay-passive = <250>; 4441 polling-delay = <1000>; 4442 4443 thermal-sensors = <&tsens1 4>; 4444 4445 trips { 4446 q6_hvx_alert0: trip-point0 { 4447 temperature = <90000>; 4448 hysteresis = <2000>; 4449 type = "hot"; 4450 }; 4451 }; 4452 }; 4453 4454 camera-thermal { 4455 polling-delay-passive = <250>; 4456 polling-delay = <1000>; 4457 4458 thermal-sensors = <&tsens1 5>; 4459 4460 trips { 4461 camera_alert0: trip-point0 { 4462 temperature = <90000>; 4463 hysteresis = <2000>; 4464 type = "hot"; 4465 }; 4466 }; 4467 }; 4468 4469 video-thermal { 4470 polling-delay-passive = <250>; 4471 polling-delay = <1000>; 4472 4473 thermal-sensors = <&tsens1 6>; 4474 4475 trips { 4476 video_alert0: trip-point0 { 4477 temperature = <90000>; 4478 hysteresis = <2000>; 4479 type = "hot"; 4480 }; 4481 }; 4482 }; 4483 4484 modem-thermal { 4485 polling-delay-passive = <250>; 4486 polling-delay = <1000>; 4487 4488 thermal-sensors = <&tsens1 7>; 4489 4490 trips { 4491 modem_alert0: trip-point0 { 4492 temperature = <90000>; 4493 hysteresis = <2000>; 4494 type = "hot"; 4495 }; 4496 }; 4497 }; 4498 }; 4499}; 4500