1// SPDX-License-Identifier: GPL-2.0 2/* 3 * SDM845 SoC device tree source 4 * 5 * Copyright (c) 2018, The Linux Foundation. All rights reserved. 6 */ 7 8#include <dt-bindings/clock/qcom,camcc-sdm845.h> 9#include <dt-bindings/clock/qcom,dispcc-sdm845.h> 10#include <dt-bindings/clock/qcom,gcc-sdm845.h> 11#include <dt-bindings/clock/qcom,gpucc-sdm845.h> 12#include <dt-bindings/clock/qcom,lpass-sdm845.h> 13#include <dt-bindings/clock/qcom,rpmh.h> 14#include <dt-bindings/clock/qcom,videocc-sdm845.h> 15#include <dt-bindings/dma/qcom-gpi.h> 16#include <dt-bindings/gpio/gpio.h> 17#include <dt-bindings/interconnect/qcom,osm-l3.h> 18#include <dt-bindings/interconnect/qcom,sdm845.h> 19#include <dt-bindings/interrupt-controller/arm-gic.h> 20#include <dt-bindings/phy/phy-qcom-qusb2.h> 21#include <dt-bindings/power/qcom-rpmpd.h> 22#include <dt-bindings/reset/qcom,sdm845-aoss.h> 23#include <dt-bindings/reset/qcom,sdm845-pdc.h> 24#include <dt-bindings/soc/qcom,apr.h> 25#include <dt-bindings/soc/qcom,rpmh-rsc.h> 26#include <dt-bindings/clock/qcom,gcc-sdm845.h> 27#include <dt-bindings/thermal/thermal.h> 28 29/ { 30 interrupt-parent = <&intc>; 31 32 #address-cells = <2>; 33 #size-cells = <2>; 34 35 aliases { 36 i2c0 = &i2c0; 37 i2c1 = &i2c1; 38 i2c2 = &i2c2; 39 i2c3 = &i2c3; 40 i2c4 = &i2c4; 41 i2c5 = &i2c5; 42 i2c6 = &i2c6; 43 i2c7 = &i2c7; 44 i2c8 = &i2c8; 45 i2c9 = &i2c9; 46 i2c10 = &i2c10; 47 i2c11 = &i2c11; 48 i2c12 = &i2c12; 49 i2c13 = &i2c13; 50 i2c14 = &i2c14; 51 i2c15 = &i2c15; 52 spi0 = &spi0; 53 spi1 = &spi1; 54 spi2 = &spi2; 55 spi3 = &spi3; 56 spi4 = &spi4; 57 spi5 = &spi5; 58 spi6 = &spi6; 59 spi7 = &spi7; 60 spi8 = &spi8; 61 spi9 = &spi9; 62 spi10 = &spi10; 63 spi11 = &spi11; 64 spi12 = &spi12; 65 spi13 = &spi13; 66 spi14 = &spi14; 67 spi15 = &spi15; 68 }; 69 70 chosen { }; 71 72 clocks { 73 xo_board: xo-board { 74 compatible = "fixed-clock"; 75 #clock-cells = <0>; 76 clock-frequency = <38400000>; 77 clock-output-names = "xo_board"; 78 }; 79 80 sleep_clk: sleep-clk { 81 compatible = "fixed-clock"; 82 #clock-cells = <0>; 83 clock-frequency = <32764>; 84 }; 85 }; 86 87 cpus: cpus { 88 #address-cells = <2>; 89 #size-cells = <0>; 90 91 CPU0: cpu@0 { 92 device_type = "cpu"; 93 compatible = "qcom,kryo385"; 94 reg = <0x0 0x0>; 95 enable-method = "psci"; 96 capacity-dmips-mhz = <611>; 97 dynamic-power-coefficient = <290>; 98 qcom,freq-domain = <&cpufreq_hw 0>; 99 operating-points-v2 = <&cpu0_opp_table>; 100 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 101 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 102 power-domains = <&CPU_PD0>; 103 power-domain-names = "psci"; 104 #cooling-cells = <2>; 105 next-level-cache = <&L2_0>; 106 L2_0: l2-cache { 107 compatible = "cache"; 108 cache-level = <2>; 109 next-level-cache = <&L3_0>; 110 L3_0: l3-cache { 111 compatible = "cache"; 112 cache-level = <3>; 113 }; 114 }; 115 }; 116 117 CPU1: cpu@100 { 118 device_type = "cpu"; 119 compatible = "qcom,kryo385"; 120 reg = <0x0 0x100>; 121 enable-method = "psci"; 122 capacity-dmips-mhz = <611>; 123 dynamic-power-coefficient = <290>; 124 qcom,freq-domain = <&cpufreq_hw 0>; 125 operating-points-v2 = <&cpu0_opp_table>; 126 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 127 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 128 power-domains = <&CPU_PD1>; 129 power-domain-names = "psci"; 130 #cooling-cells = <2>; 131 next-level-cache = <&L2_100>; 132 L2_100: l2-cache { 133 compatible = "cache"; 134 cache-level = <2>; 135 next-level-cache = <&L3_0>; 136 }; 137 }; 138 139 CPU2: cpu@200 { 140 device_type = "cpu"; 141 compatible = "qcom,kryo385"; 142 reg = <0x0 0x200>; 143 enable-method = "psci"; 144 capacity-dmips-mhz = <611>; 145 dynamic-power-coefficient = <290>; 146 qcom,freq-domain = <&cpufreq_hw 0>; 147 operating-points-v2 = <&cpu0_opp_table>; 148 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 149 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 150 power-domains = <&CPU_PD2>; 151 power-domain-names = "psci"; 152 #cooling-cells = <2>; 153 next-level-cache = <&L2_200>; 154 L2_200: l2-cache { 155 compatible = "cache"; 156 cache-level = <2>; 157 next-level-cache = <&L3_0>; 158 }; 159 }; 160 161 CPU3: cpu@300 { 162 device_type = "cpu"; 163 compatible = "qcom,kryo385"; 164 reg = <0x0 0x300>; 165 enable-method = "psci"; 166 capacity-dmips-mhz = <611>; 167 dynamic-power-coefficient = <290>; 168 qcom,freq-domain = <&cpufreq_hw 0>; 169 operating-points-v2 = <&cpu0_opp_table>; 170 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 171 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 172 #cooling-cells = <2>; 173 power-domains = <&CPU_PD3>; 174 power-domain-names = "psci"; 175 next-level-cache = <&L2_300>; 176 L2_300: l2-cache { 177 compatible = "cache"; 178 cache-level = <2>; 179 next-level-cache = <&L3_0>; 180 }; 181 }; 182 183 CPU4: cpu@400 { 184 device_type = "cpu"; 185 compatible = "qcom,kryo385"; 186 reg = <0x0 0x400>; 187 enable-method = "psci"; 188 capacity-dmips-mhz = <1024>; 189 dynamic-power-coefficient = <442>; 190 qcom,freq-domain = <&cpufreq_hw 1>; 191 operating-points-v2 = <&cpu4_opp_table>; 192 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 193 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 194 power-domains = <&CPU_PD4>; 195 power-domain-names = "psci"; 196 #cooling-cells = <2>; 197 next-level-cache = <&L2_400>; 198 L2_400: l2-cache { 199 compatible = "cache"; 200 cache-level = <2>; 201 next-level-cache = <&L3_0>; 202 }; 203 }; 204 205 CPU5: cpu@500 { 206 device_type = "cpu"; 207 compatible = "qcom,kryo385"; 208 reg = <0x0 0x500>; 209 enable-method = "psci"; 210 capacity-dmips-mhz = <1024>; 211 dynamic-power-coefficient = <442>; 212 qcom,freq-domain = <&cpufreq_hw 1>; 213 operating-points-v2 = <&cpu4_opp_table>; 214 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 215 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 216 power-domains = <&CPU_PD5>; 217 power-domain-names = "psci"; 218 #cooling-cells = <2>; 219 next-level-cache = <&L2_500>; 220 L2_500: l2-cache { 221 compatible = "cache"; 222 cache-level = <2>; 223 next-level-cache = <&L3_0>; 224 }; 225 }; 226 227 CPU6: cpu@600 { 228 device_type = "cpu"; 229 compatible = "qcom,kryo385"; 230 reg = <0x0 0x600>; 231 enable-method = "psci"; 232 capacity-dmips-mhz = <1024>; 233 dynamic-power-coefficient = <442>; 234 qcom,freq-domain = <&cpufreq_hw 1>; 235 operating-points-v2 = <&cpu4_opp_table>; 236 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 237 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 238 power-domains = <&CPU_PD6>; 239 power-domain-names = "psci"; 240 #cooling-cells = <2>; 241 next-level-cache = <&L2_600>; 242 L2_600: l2-cache { 243 compatible = "cache"; 244 cache-level = <2>; 245 next-level-cache = <&L3_0>; 246 }; 247 }; 248 249 CPU7: cpu@700 { 250 device_type = "cpu"; 251 compatible = "qcom,kryo385"; 252 reg = <0x0 0x700>; 253 enable-method = "psci"; 254 capacity-dmips-mhz = <1024>; 255 dynamic-power-coefficient = <442>; 256 qcom,freq-domain = <&cpufreq_hw 1>; 257 operating-points-v2 = <&cpu4_opp_table>; 258 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 259 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 260 power-domains = <&CPU_PD7>; 261 power-domain-names = "psci"; 262 #cooling-cells = <2>; 263 next-level-cache = <&L2_700>; 264 L2_700: l2-cache { 265 compatible = "cache"; 266 cache-level = <2>; 267 next-level-cache = <&L3_0>; 268 }; 269 }; 270 271 cpu-map { 272 cluster0 { 273 core0 { 274 cpu = <&CPU0>; 275 }; 276 277 core1 { 278 cpu = <&CPU1>; 279 }; 280 281 core2 { 282 cpu = <&CPU2>; 283 }; 284 285 core3 { 286 cpu = <&CPU3>; 287 }; 288 289 core4 { 290 cpu = <&CPU4>; 291 }; 292 293 core5 { 294 cpu = <&CPU5>; 295 }; 296 297 core6 { 298 cpu = <&CPU6>; 299 }; 300 301 core7 { 302 cpu = <&CPU7>; 303 }; 304 }; 305 }; 306 307 cpu_idle_states: idle-states { 308 entry-method = "psci"; 309 310 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 311 compatible = "arm,idle-state"; 312 idle-state-name = "little-rail-power-collapse"; 313 arm,psci-suspend-param = <0x40000004>; 314 entry-latency-us = <350>; 315 exit-latency-us = <461>; 316 min-residency-us = <1890>; 317 local-timer-stop; 318 }; 319 320 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 321 compatible = "arm,idle-state"; 322 idle-state-name = "big-rail-power-collapse"; 323 arm,psci-suspend-param = <0x40000004>; 324 entry-latency-us = <264>; 325 exit-latency-us = <621>; 326 min-residency-us = <952>; 327 local-timer-stop; 328 }; 329 }; 330 331 domain-idle-states { 332 CLUSTER_SLEEP_0: cluster-sleep-0 { 333 compatible = "domain-idle-state"; 334 idle-state-name = "cluster-power-collapse"; 335 arm,psci-suspend-param = <0x4100c244>; 336 entry-latency-us = <3263>; 337 exit-latency-us = <6562>; 338 min-residency-us = <9987>; 339 local-timer-stop; 340 }; 341 }; 342 }; 343 344 firmware { 345 scm { 346 compatible = "qcom,scm-sdm845", "qcom,scm"; 347 }; 348 }; 349 350 memory@80000000 { 351 device_type = "memory"; 352 /* We expect the bootloader to fill in the size */ 353 reg = <0 0x80000000 0 0>; 354 }; 355 356 cpu0_opp_table: opp-table-cpu0 { 357 compatible = "operating-points-v2"; 358 opp-shared; 359 360 cpu0_opp1: opp-300000000 { 361 opp-hz = /bits/ 64 <300000000>; 362 opp-peak-kBps = <800000 4800000>; 363 }; 364 365 cpu0_opp2: opp-403200000 { 366 opp-hz = /bits/ 64 <403200000>; 367 opp-peak-kBps = <800000 4800000>; 368 }; 369 370 cpu0_opp3: opp-480000000 { 371 opp-hz = /bits/ 64 <480000000>; 372 opp-peak-kBps = <800000 6451200>; 373 }; 374 375 cpu0_opp4: opp-576000000 { 376 opp-hz = /bits/ 64 <576000000>; 377 opp-peak-kBps = <800000 6451200>; 378 }; 379 380 cpu0_opp5: opp-652800000 { 381 opp-hz = /bits/ 64 <652800000>; 382 opp-peak-kBps = <800000 7680000>; 383 }; 384 385 cpu0_opp6: opp-748800000 { 386 opp-hz = /bits/ 64 <748800000>; 387 opp-peak-kBps = <1804000 9216000>; 388 }; 389 390 cpu0_opp7: opp-825600000 { 391 opp-hz = /bits/ 64 <825600000>; 392 opp-peak-kBps = <1804000 9216000>; 393 }; 394 395 cpu0_opp8: opp-902400000 { 396 opp-hz = /bits/ 64 <902400000>; 397 opp-peak-kBps = <1804000 10444800>; 398 }; 399 400 cpu0_opp9: opp-979200000 { 401 opp-hz = /bits/ 64 <979200000>; 402 opp-peak-kBps = <1804000 11980800>; 403 }; 404 405 cpu0_opp10: opp-1056000000 { 406 opp-hz = /bits/ 64 <1056000000>; 407 opp-peak-kBps = <1804000 11980800>; 408 }; 409 410 cpu0_opp11: opp-1132800000 { 411 opp-hz = /bits/ 64 <1132800000>; 412 opp-peak-kBps = <2188000 13516800>; 413 }; 414 415 cpu0_opp12: opp-1228800000 { 416 opp-hz = /bits/ 64 <1228800000>; 417 opp-peak-kBps = <2188000 15052800>; 418 }; 419 420 cpu0_opp13: opp-1324800000 { 421 opp-hz = /bits/ 64 <1324800000>; 422 opp-peak-kBps = <2188000 16588800>; 423 }; 424 425 cpu0_opp14: opp-1420800000 { 426 opp-hz = /bits/ 64 <1420800000>; 427 opp-peak-kBps = <3072000 18124800>; 428 }; 429 430 cpu0_opp15: opp-1516800000 { 431 opp-hz = /bits/ 64 <1516800000>; 432 opp-peak-kBps = <3072000 19353600>; 433 }; 434 435 cpu0_opp16: opp-1612800000 { 436 opp-hz = /bits/ 64 <1612800000>; 437 opp-peak-kBps = <4068000 19353600>; 438 }; 439 440 cpu0_opp17: opp-1689600000 { 441 opp-hz = /bits/ 64 <1689600000>; 442 opp-peak-kBps = <4068000 20889600>; 443 }; 444 445 cpu0_opp18: opp-1766400000 { 446 opp-hz = /bits/ 64 <1766400000>; 447 opp-peak-kBps = <4068000 22425600>; 448 }; 449 }; 450 451 cpu4_opp_table: opp-table-cpu4 { 452 compatible = "operating-points-v2"; 453 opp-shared; 454 455 cpu4_opp1: opp-300000000 { 456 opp-hz = /bits/ 64 <300000000>; 457 opp-peak-kBps = <800000 4800000>; 458 }; 459 460 cpu4_opp2: opp-403200000 { 461 opp-hz = /bits/ 64 <403200000>; 462 opp-peak-kBps = <800000 4800000>; 463 }; 464 465 cpu4_opp3: opp-480000000 { 466 opp-hz = /bits/ 64 <480000000>; 467 opp-peak-kBps = <1804000 4800000>; 468 }; 469 470 cpu4_opp4: opp-576000000 { 471 opp-hz = /bits/ 64 <576000000>; 472 opp-peak-kBps = <1804000 4800000>; 473 }; 474 475 cpu4_opp5: opp-652800000 { 476 opp-hz = /bits/ 64 <652800000>; 477 opp-peak-kBps = <1804000 4800000>; 478 }; 479 480 cpu4_opp6: opp-748800000 { 481 opp-hz = /bits/ 64 <748800000>; 482 opp-peak-kBps = <1804000 4800000>; 483 }; 484 485 cpu4_opp7: opp-825600000 { 486 opp-hz = /bits/ 64 <825600000>; 487 opp-peak-kBps = <2188000 9216000>; 488 }; 489 490 cpu4_opp8: opp-902400000 { 491 opp-hz = /bits/ 64 <902400000>; 492 opp-peak-kBps = <2188000 9216000>; 493 }; 494 495 cpu4_opp9: opp-979200000 { 496 opp-hz = /bits/ 64 <979200000>; 497 opp-peak-kBps = <2188000 9216000>; 498 }; 499 500 cpu4_opp10: opp-1056000000 { 501 opp-hz = /bits/ 64 <1056000000>; 502 opp-peak-kBps = <3072000 9216000>; 503 }; 504 505 cpu4_opp11: opp-1132800000 { 506 opp-hz = /bits/ 64 <1132800000>; 507 opp-peak-kBps = <3072000 11980800>; 508 }; 509 510 cpu4_opp12: opp-1209600000 { 511 opp-hz = /bits/ 64 <1209600000>; 512 opp-peak-kBps = <4068000 11980800>; 513 }; 514 515 cpu4_opp13: opp-1286400000 { 516 opp-hz = /bits/ 64 <1286400000>; 517 opp-peak-kBps = <4068000 11980800>; 518 }; 519 520 cpu4_opp14: opp-1363200000 { 521 opp-hz = /bits/ 64 <1363200000>; 522 opp-peak-kBps = <4068000 15052800>; 523 }; 524 525 cpu4_opp15: opp-1459200000 { 526 opp-hz = /bits/ 64 <1459200000>; 527 opp-peak-kBps = <4068000 15052800>; 528 }; 529 530 cpu4_opp16: opp-1536000000 { 531 opp-hz = /bits/ 64 <1536000000>; 532 opp-peak-kBps = <5412000 15052800>; 533 }; 534 535 cpu4_opp17: opp-1612800000 { 536 opp-hz = /bits/ 64 <1612800000>; 537 opp-peak-kBps = <5412000 15052800>; 538 }; 539 540 cpu4_opp18: opp-1689600000 { 541 opp-hz = /bits/ 64 <1689600000>; 542 opp-peak-kBps = <5412000 19353600>; 543 }; 544 545 cpu4_opp19: opp-1766400000 { 546 opp-hz = /bits/ 64 <1766400000>; 547 opp-peak-kBps = <6220000 19353600>; 548 }; 549 550 cpu4_opp20: opp-1843200000 { 551 opp-hz = /bits/ 64 <1843200000>; 552 opp-peak-kBps = <6220000 19353600>; 553 }; 554 555 cpu4_opp21: opp-1920000000 { 556 opp-hz = /bits/ 64 <1920000000>; 557 opp-peak-kBps = <7216000 19353600>; 558 }; 559 560 cpu4_opp22: opp-1996800000 { 561 opp-hz = /bits/ 64 <1996800000>; 562 opp-peak-kBps = <7216000 20889600>; 563 }; 564 565 cpu4_opp23: opp-2092800000 { 566 opp-hz = /bits/ 64 <2092800000>; 567 opp-peak-kBps = <7216000 20889600>; 568 }; 569 570 cpu4_opp24: opp-2169600000 { 571 opp-hz = /bits/ 64 <2169600000>; 572 opp-peak-kBps = <7216000 20889600>; 573 }; 574 575 cpu4_opp25: opp-2246400000 { 576 opp-hz = /bits/ 64 <2246400000>; 577 opp-peak-kBps = <7216000 20889600>; 578 }; 579 580 cpu4_opp26: opp-2323200000 { 581 opp-hz = /bits/ 64 <2323200000>; 582 opp-peak-kBps = <7216000 20889600>; 583 }; 584 585 cpu4_opp27: opp-2400000000 { 586 opp-hz = /bits/ 64 <2400000000>; 587 opp-peak-kBps = <7216000 22425600>; 588 }; 589 590 cpu4_opp28: opp-2476800000 { 591 opp-hz = /bits/ 64 <2476800000>; 592 opp-peak-kBps = <7216000 22425600>; 593 }; 594 595 cpu4_opp29: opp-2553600000 { 596 opp-hz = /bits/ 64 <2553600000>; 597 opp-peak-kBps = <7216000 22425600>; 598 }; 599 600 cpu4_opp30: opp-2649600000 { 601 opp-hz = /bits/ 64 <2649600000>; 602 opp-peak-kBps = <7216000 22425600>; 603 }; 604 605 cpu4_opp31: opp-2745600000 { 606 opp-hz = /bits/ 64 <2745600000>; 607 opp-peak-kBps = <7216000 25497600>; 608 }; 609 610 cpu4_opp32: opp-2803200000 { 611 opp-hz = /bits/ 64 <2803200000>; 612 opp-peak-kBps = <7216000 25497600>; 613 }; 614 }; 615 616 dsi_opp_table: opp-table-dsi { 617 compatible = "operating-points-v2"; 618 619 opp-19200000 { 620 opp-hz = /bits/ 64 <19200000>; 621 required-opps = <&rpmhpd_opp_min_svs>; 622 }; 623 624 opp-180000000 { 625 opp-hz = /bits/ 64 <180000000>; 626 required-opps = <&rpmhpd_opp_low_svs>; 627 }; 628 629 opp-275000000 { 630 opp-hz = /bits/ 64 <275000000>; 631 required-opps = <&rpmhpd_opp_svs>; 632 }; 633 634 opp-328580000 { 635 opp-hz = /bits/ 64 <328580000>; 636 required-opps = <&rpmhpd_opp_svs_l1>; 637 }; 638 639 opp-358000000 { 640 opp-hz = /bits/ 64 <358000000>; 641 required-opps = <&rpmhpd_opp_nom>; 642 }; 643 }; 644 645 qspi_opp_table: opp-table-qspi { 646 compatible = "operating-points-v2"; 647 648 opp-19200000 { 649 opp-hz = /bits/ 64 <19200000>; 650 required-opps = <&rpmhpd_opp_min_svs>; 651 }; 652 653 opp-100000000 { 654 opp-hz = /bits/ 64 <100000000>; 655 required-opps = <&rpmhpd_opp_low_svs>; 656 }; 657 658 opp-150000000 { 659 opp-hz = /bits/ 64 <150000000>; 660 required-opps = <&rpmhpd_opp_svs>; 661 }; 662 663 opp-300000000 { 664 opp-hz = /bits/ 64 <300000000>; 665 required-opps = <&rpmhpd_opp_nom>; 666 }; 667 }; 668 669 qup_opp_table: opp-table-qup { 670 compatible = "operating-points-v2"; 671 672 opp-50000000 { 673 opp-hz = /bits/ 64 <50000000>; 674 required-opps = <&rpmhpd_opp_min_svs>; 675 }; 676 677 opp-75000000 { 678 opp-hz = /bits/ 64 <75000000>; 679 required-opps = <&rpmhpd_opp_low_svs>; 680 }; 681 682 opp-100000000 { 683 opp-hz = /bits/ 64 <100000000>; 684 required-opps = <&rpmhpd_opp_svs>; 685 }; 686 687 opp-128000000 { 688 opp-hz = /bits/ 64 <128000000>; 689 required-opps = <&rpmhpd_opp_nom>; 690 }; 691 }; 692 693 pmu { 694 compatible = "arm,armv8-pmuv3"; 695 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; 696 }; 697 698 psci: psci { 699 compatible = "arm,psci-1.0"; 700 method = "smc"; 701 702 CPU_PD0: power-domain-cpu0 { 703 #power-domain-cells = <0>; 704 power-domains = <&CLUSTER_PD>; 705 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 706 }; 707 708 CPU_PD1: power-domain-cpu1 { 709 #power-domain-cells = <0>; 710 power-domains = <&CLUSTER_PD>; 711 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 712 }; 713 714 CPU_PD2: power-domain-cpu2 { 715 #power-domain-cells = <0>; 716 power-domains = <&CLUSTER_PD>; 717 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 718 }; 719 720 CPU_PD3: power-domain-cpu3 { 721 #power-domain-cells = <0>; 722 power-domains = <&CLUSTER_PD>; 723 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 724 }; 725 726 CPU_PD4: power-domain-cpu4 { 727 #power-domain-cells = <0>; 728 power-domains = <&CLUSTER_PD>; 729 domain-idle-states = <&BIG_CPU_SLEEP_0>; 730 }; 731 732 CPU_PD5: power-domain-cpu5 { 733 #power-domain-cells = <0>; 734 power-domains = <&CLUSTER_PD>; 735 domain-idle-states = <&BIG_CPU_SLEEP_0>; 736 }; 737 738 CPU_PD6: power-domain-cpu6 { 739 #power-domain-cells = <0>; 740 power-domains = <&CLUSTER_PD>; 741 domain-idle-states = <&BIG_CPU_SLEEP_0>; 742 }; 743 744 CPU_PD7: power-domain-cpu7 { 745 #power-domain-cells = <0>; 746 power-domains = <&CLUSTER_PD>; 747 domain-idle-states = <&BIG_CPU_SLEEP_0>; 748 }; 749 750 CLUSTER_PD: power-domain-cluster { 751 #power-domain-cells = <0>; 752 domain-idle-states = <&CLUSTER_SLEEP_0>; 753 }; 754 }; 755 756 reserved-memory { 757 #address-cells = <2>; 758 #size-cells = <2>; 759 ranges; 760 761 hyp_mem: hyp-mem@85700000 { 762 reg = <0 0x85700000 0 0x600000>; 763 no-map; 764 }; 765 766 xbl_mem: xbl-mem@85e00000 { 767 reg = <0 0x85e00000 0 0x100000>; 768 no-map; 769 }; 770 771 aop_mem: aop-mem@85fc0000 { 772 reg = <0 0x85fc0000 0 0x20000>; 773 no-map; 774 }; 775 776 aop_cmd_db_mem: aop-cmd-db-mem@85fe0000 { 777 compatible = "qcom,cmd-db"; 778 reg = <0x0 0x85fe0000 0 0x20000>; 779 no-map; 780 }; 781 782 smem@86000000 { 783 compatible = "qcom,smem"; 784 reg = <0x0 0x86000000 0 0x200000>; 785 no-map; 786 hwlocks = <&tcsr_mutex 3>; 787 }; 788 789 tz_mem: tz@86200000 { 790 reg = <0 0x86200000 0 0x2d00000>; 791 no-map; 792 }; 793 794 rmtfs_mem: rmtfs@88f00000 { 795 compatible = "qcom,rmtfs-mem"; 796 reg = <0 0x88f00000 0 0x200000>; 797 no-map; 798 799 qcom,client-id = <1>; 800 qcom,vmid = <15>; 801 }; 802 803 qseecom_mem: qseecom@8ab00000 { 804 reg = <0 0x8ab00000 0 0x1400000>; 805 no-map; 806 }; 807 808 camera_mem: camera-mem@8bf00000 { 809 reg = <0 0x8bf00000 0 0x500000>; 810 no-map; 811 }; 812 813 ipa_fw_mem: ipa-fw@8c400000 { 814 reg = <0 0x8c400000 0 0x10000>; 815 no-map; 816 }; 817 818 ipa_gsi_mem: ipa-gsi@8c410000 { 819 reg = <0 0x8c410000 0 0x5000>; 820 no-map; 821 }; 822 823 gpu_mem: gpu@8c415000 { 824 reg = <0 0x8c415000 0 0x2000>; 825 no-map; 826 }; 827 828 adsp_mem: adsp@8c500000 { 829 reg = <0 0x8c500000 0 0x1a00000>; 830 no-map; 831 }; 832 833 wlan_msa_mem: wlan-msa@8df00000 { 834 reg = <0 0x8df00000 0 0x100000>; 835 no-map; 836 }; 837 838 mpss_region: mpss@8e000000 { 839 reg = <0 0x8e000000 0 0x7800000>; 840 no-map; 841 }; 842 843 venus_mem: venus@95800000 { 844 reg = <0 0x95800000 0 0x500000>; 845 no-map; 846 }; 847 848 cdsp_mem: cdsp@95d00000 { 849 reg = <0 0x95d00000 0 0x800000>; 850 no-map; 851 }; 852 853 mba_region: mba@96500000 { 854 reg = <0 0x96500000 0 0x200000>; 855 no-map; 856 }; 857 858 slpi_mem: slpi@96700000 { 859 reg = <0 0x96700000 0 0x1400000>; 860 no-map; 861 }; 862 863 spss_mem: spss@97b00000 { 864 reg = <0 0x97b00000 0 0x100000>; 865 no-map; 866 }; 867 868 mdata_mem: mpss-metadata { 869 alloc-ranges = <0 0xa0000000 0 0x20000000>; 870 size = <0 0x4000>; 871 no-map; 872 }; 873 }; 874 875 adsp_pas: remoteproc-adsp { 876 compatible = "qcom,sdm845-adsp-pas"; 877 878 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 879 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 880 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 881 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 882 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 883 interrupt-names = "wdog", "fatal", "ready", 884 "handover", "stop-ack"; 885 886 clocks = <&rpmhcc RPMH_CXO_CLK>; 887 clock-names = "xo"; 888 889 memory-region = <&adsp_mem>; 890 891 qcom,qmp = <&aoss_qmp>; 892 893 qcom,smem-states = <&adsp_smp2p_out 0>; 894 qcom,smem-state-names = "stop"; 895 896 status = "disabled"; 897 898 glink-edge { 899 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 900 label = "lpass"; 901 qcom,remote-pid = <2>; 902 mboxes = <&apss_shared 8>; 903 904 apr { 905 compatible = "qcom,apr-v2"; 906 qcom,glink-channels = "apr_audio_svc"; 907 qcom,domain = <APR_DOMAIN_ADSP>; 908 #address-cells = <1>; 909 #size-cells = <0>; 910 qcom,intents = <512 20>; 911 912 service@3 { 913 reg = <APR_SVC_ADSP_CORE>; 914 compatible = "qcom,q6core"; 915 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 916 }; 917 918 q6afe: service@4 { 919 compatible = "qcom,q6afe"; 920 reg = <APR_SVC_AFE>; 921 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 922 q6afedai: dais { 923 compatible = "qcom,q6afe-dais"; 924 #address-cells = <1>; 925 #size-cells = <0>; 926 #sound-dai-cells = <1>; 927 }; 928 }; 929 930 q6asm: service@7 { 931 compatible = "qcom,q6asm"; 932 reg = <APR_SVC_ASM>; 933 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 934 q6asmdai: dais { 935 compatible = "qcom,q6asm-dais"; 936 #address-cells = <1>; 937 #size-cells = <0>; 938 #sound-dai-cells = <1>; 939 iommus = <&apps_smmu 0x1821 0x0>; 940 }; 941 }; 942 943 q6adm: service@8 { 944 compatible = "qcom,q6adm"; 945 reg = <APR_SVC_ADM>; 946 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 947 q6routing: routing { 948 compatible = "qcom,q6adm-routing"; 949 #sound-dai-cells = <0>; 950 }; 951 }; 952 }; 953 954 fastrpc { 955 compatible = "qcom,fastrpc"; 956 qcom,glink-channels = "fastrpcglink-apps-dsp"; 957 label = "adsp"; 958 qcom,non-secure-domain; 959 #address-cells = <1>; 960 #size-cells = <0>; 961 962 compute-cb@3 { 963 compatible = "qcom,fastrpc-compute-cb"; 964 reg = <3>; 965 iommus = <&apps_smmu 0x1823 0x0>; 966 }; 967 968 compute-cb@4 { 969 compatible = "qcom,fastrpc-compute-cb"; 970 reg = <4>; 971 iommus = <&apps_smmu 0x1824 0x0>; 972 }; 973 }; 974 }; 975 }; 976 977 cdsp_pas: remoteproc-cdsp { 978 compatible = "qcom,sdm845-cdsp-pas"; 979 980 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 981 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 982 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 983 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 984 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 985 interrupt-names = "wdog", "fatal", "ready", 986 "handover", "stop-ack"; 987 988 clocks = <&rpmhcc RPMH_CXO_CLK>; 989 clock-names = "xo"; 990 991 memory-region = <&cdsp_mem>; 992 993 qcom,qmp = <&aoss_qmp>; 994 995 qcom,smem-states = <&cdsp_smp2p_out 0>; 996 qcom,smem-state-names = "stop"; 997 998 status = "disabled"; 999 1000 glink-edge { 1001 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>; 1002 label = "turing"; 1003 qcom,remote-pid = <5>; 1004 mboxes = <&apss_shared 4>; 1005 fastrpc { 1006 compatible = "qcom,fastrpc"; 1007 qcom,glink-channels = "fastrpcglink-apps-dsp"; 1008 label = "cdsp"; 1009 qcom,non-secure-domain; 1010 #address-cells = <1>; 1011 #size-cells = <0>; 1012 1013 compute-cb@1 { 1014 compatible = "qcom,fastrpc-compute-cb"; 1015 reg = <1>; 1016 iommus = <&apps_smmu 0x1401 0x30>; 1017 }; 1018 1019 compute-cb@2 { 1020 compatible = "qcom,fastrpc-compute-cb"; 1021 reg = <2>; 1022 iommus = <&apps_smmu 0x1402 0x30>; 1023 }; 1024 1025 compute-cb@3 { 1026 compatible = "qcom,fastrpc-compute-cb"; 1027 reg = <3>; 1028 iommus = <&apps_smmu 0x1403 0x30>; 1029 }; 1030 1031 compute-cb@4 { 1032 compatible = "qcom,fastrpc-compute-cb"; 1033 reg = <4>; 1034 iommus = <&apps_smmu 0x1404 0x30>; 1035 }; 1036 1037 compute-cb@5 { 1038 compatible = "qcom,fastrpc-compute-cb"; 1039 reg = <5>; 1040 iommus = <&apps_smmu 0x1405 0x30>; 1041 }; 1042 1043 compute-cb@6 { 1044 compatible = "qcom,fastrpc-compute-cb"; 1045 reg = <6>; 1046 iommus = <&apps_smmu 0x1406 0x30>; 1047 }; 1048 1049 compute-cb@7 { 1050 compatible = "qcom,fastrpc-compute-cb"; 1051 reg = <7>; 1052 iommus = <&apps_smmu 0x1407 0x30>; 1053 }; 1054 1055 compute-cb@8 { 1056 compatible = "qcom,fastrpc-compute-cb"; 1057 reg = <8>; 1058 iommus = <&apps_smmu 0x1408 0x30>; 1059 }; 1060 }; 1061 }; 1062 }; 1063 1064 smp2p-cdsp { 1065 compatible = "qcom,smp2p"; 1066 qcom,smem = <94>, <432>; 1067 1068 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; 1069 1070 mboxes = <&apss_shared 6>; 1071 1072 qcom,local-pid = <0>; 1073 qcom,remote-pid = <5>; 1074 1075 cdsp_smp2p_out: master-kernel { 1076 qcom,entry-name = "master-kernel"; 1077 #qcom,smem-state-cells = <1>; 1078 }; 1079 1080 cdsp_smp2p_in: slave-kernel { 1081 qcom,entry-name = "slave-kernel"; 1082 1083 interrupt-controller; 1084 #interrupt-cells = <2>; 1085 }; 1086 }; 1087 1088 smp2p-lpass { 1089 compatible = "qcom,smp2p"; 1090 qcom,smem = <443>, <429>; 1091 1092 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 1093 1094 mboxes = <&apss_shared 10>; 1095 1096 qcom,local-pid = <0>; 1097 qcom,remote-pid = <2>; 1098 1099 adsp_smp2p_out: master-kernel { 1100 qcom,entry-name = "master-kernel"; 1101 #qcom,smem-state-cells = <1>; 1102 }; 1103 1104 adsp_smp2p_in: slave-kernel { 1105 qcom,entry-name = "slave-kernel"; 1106 1107 interrupt-controller; 1108 #interrupt-cells = <2>; 1109 }; 1110 }; 1111 1112 smp2p-mpss { 1113 compatible = "qcom,smp2p"; 1114 qcom,smem = <435>, <428>; 1115 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 1116 mboxes = <&apss_shared 14>; 1117 qcom,local-pid = <0>; 1118 qcom,remote-pid = <1>; 1119 1120 modem_smp2p_out: master-kernel { 1121 qcom,entry-name = "master-kernel"; 1122 #qcom,smem-state-cells = <1>; 1123 }; 1124 1125 modem_smp2p_in: slave-kernel { 1126 qcom,entry-name = "slave-kernel"; 1127 interrupt-controller; 1128 #interrupt-cells = <2>; 1129 }; 1130 1131 ipa_smp2p_out: ipa-ap-to-modem { 1132 qcom,entry-name = "ipa"; 1133 #qcom,smem-state-cells = <1>; 1134 }; 1135 1136 ipa_smp2p_in: ipa-modem-to-ap { 1137 qcom,entry-name = "ipa"; 1138 interrupt-controller; 1139 #interrupt-cells = <2>; 1140 }; 1141 }; 1142 1143 smp2p-slpi { 1144 compatible = "qcom,smp2p"; 1145 qcom,smem = <481>, <430>; 1146 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>; 1147 mboxes = <&apss_shared 26>; 1148 qcom,local-pid = <0>; 1149 qcom,remote-pid = <3>; 1150 1151 slpi_smp2p_out: master-kernel { 1152 qcom,entry-name = "master-kernel"; 1153 #qcom,smem-state-cells = <1>; 1154 }; 1155 1156 slpi_smp2p_in: slave-kernel { 1157 qcom,entry-name = "slave-kernel"; 1158 interrupt-controller; 1159 #interrupt-cells = <2>; 1160 }; 1161 }; 1162 1163 soc: soc@0 { 1164 #address-cells = <2>; 1165 #size-cells = <2>; 1166 ranges = <0 0 0 0 0x10 0>; 1167 dma-ranges = <0 0 0 0 0x10 0>; 1168 compatible = "simple-bus"; 1169 1170 gcc: clock-controller@100000 { 1171 compatible = "qcom,gcc-sdm845"; 1172 reg = <0 0x00100000 0 0x1f0000>; 1173 clocks = <&rpmhcc RPMH_CXO_CLK>, 1174 <&rpmhcc RPMH_CXO_CLK_A>, 1175 <&sleep_clk>, 1176 <&pcie0_lane>, 1177 <&pcie1_lane>; 1178 clock-names = "bi_tcxo", 1179 "bi_tcxo_ao", 1180 "sleep_clk", 1181 "pcie_0_pipe_clk", 1182 "pcie_1_pipe_clk"; 1183 #clock-cells = <1>; 1184 #reset-cells = <1>; 1185 #power-domain-cells = <1>; 1186 }; 1187 1188 qfprom@784000 { 1189 compatible = "qcom,sdm845-qfprom", "qcom,qfprom"; 1190 reg = <0 0x00784000 0 0x8ff>; 1191 #address-cells = <1>; 1192 #size-cells = <1>; 1193 1194 qusb2p_hstx_trim: hstx-trim-primary@1eb { 1195 reg = <0x1eb 0x1>; 1196 bits = <1 4>; 1197 }; 1198 1199 qusb2s_hstx_trim: hstx-trim-secondary@1eb { 1200 reg = <0x1eb 0x2>; 1201 bits = <6 4>; 1202 }; 1203 }; 1204 1205 rng: rng@793000 { 1206 compatible = "qcom,prng-ee"; 1207 reg = <0 0x00793000 0 0x1000>; 1208 clocks = <&gcc GCC_PRNG_AHB_CLK>; 1209 clock-names = "core"; 1210 }; 1211 1212 gpi_dma0: dma-controller@800000 { 1213 #dma-cells = <3>; 1214 compatible = "qcom,sdm845-gpi-dma"; 1215 reg = <0 0x00800000 0 0x60000>; 1216 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 1217 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 1218 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 1219 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 1220 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 1221 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 1222 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 1223 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 1224 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 1225 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 1226 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 1227 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 1228 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 1229 dma-channels = <13>; 1230 dma-channel-mask = <0xfa>; 1231 iommus = <&apps_smmu 0x0016 0x0>; 1232 status = "disabled"; 1233 }; 1234 1235 qupv3_id_0: geniqup@8c0000 { 1236 compatible = "qcom,geni-se-qup"; 1237 reg = <0 0x008c0000 0 0x6000>; 1238 clock-names = "m-ahb", "s-ahb"; 1239 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1240 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1241 iommus = <&apps_smmu 0x3 0x0>; 1242 #address-cells = <2>; 1243 #size-cells = <2>; 1244 ranges; 1245 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>; 1246 interconnect-names = "qup-core"; 1247 status = "disabled"; 1248 1249 i2c0: i2c@880000 { 1250 compatible = "qcom,geni-i2c"; 1251 reg = <0 0x00880000 0 0x4000>; 1252 clock-names = "se"; 1253 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1254 pinctrl-names = "default"; 1255 pinctrl-0 = <&qup_i2c0_default>; 1256 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1257 #address-cells = <1>; 1258 #size-cells = <0>; 1259 power-domains = <&rpmhpd SDM845_CX>; 1260 operating-points-v2 = <&qup_opp_table>; 1261 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1262 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, 1263 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; 1264 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1265 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1266 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1267 dma-names = "tx", "rx"; 1268 status = "disabled"; 1269 }; 1270 1271 spi0: spi@880000 { 1272 compatible = "qcom,geni-spi"; 1273 reg = <0 0x00880000 0 0x4000>; 1274 clock-names = "se"; 1275 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1276 pinctrl-names = "default"; 1277 pinctrl-0 = <&qup_spi0_default>; 1278 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1279 #address-cells = <1>; 1280 #size-cells = <0>; 1281 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1282 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1283 interconnect-names = "qup-core", "qup-config"; 1284 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1285 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1286 dma-names = "tx", "rx"; 1287 status = "disabled"; 1288 }; 1289 1290 uart0: serial@880000 { 1291 compatible = "qcom,geni-uart"; 1292 reg = <0 0x00880000 0 0x4000>; 1293 clock-names = "se"; 1294 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1295 pinctrl-names = "default"; 1296 pinctrl-0 = <&qup_uart0_default>; 1297 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1298 power-domains = <&rpmhpd SDM845_CX>; 1299 operating-points-v2 = <&qup_opp_table>; 1300 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1301 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1302 interconnect-names = "qup-core", "qup-config"; 1303 status = "disabled"; 1304 }; 1305 1306 i2c1: i2c@884000 { 1307 compatible = "qcom,geni-i2c"; 1308 reg = <0 0x00884000 0 0x4000>; 1309 clock-names = "se"; 1310 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1311 pinctrl-names = "default"; 1312 pinctrl-0 = <&qup_i2c1_default>; 1313 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1314 #address-cells = <1>; 1315 #size-cells = <0>; 1316 power-domains = <&rpmhpd SDM845_CX>; 1317 operating-points-v2 = <&qup_opp_table>; 1318 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1319 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, 1320 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; 1321 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1322 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1323 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1324 dma-names = "tx", "rx"; 1325 status = "disabled"; 1326 }; 1327 1328 spi1: spi@884000 { 1329 compatible = "qcom,geni-spi"; 1330 reg = <0 0x00884000 0 0x4000>; 1331 clock-names = "se"; 1332 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1333 pinctrl-names = "default"; 1334 pinctrl-0 = <&qup_spi1_default>; 1335 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1336 #address-cells = <1>; 1337 #size-cells = <0>; 1338 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1339 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1340 interconnect-names = "qup-core", "qup-config"; 1341 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1342 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1343 dma-names = "tx", "rx"; 1344 status = "disabled"; 1345 }; 1346 1347 uart1: serial@884000 { 1348 compatible = "qcom,geni-uart"; 1349 reg = <0 0x00884000 0 0x4000>; 1350 clock-names = "se"; 1351 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1352 pinctrl-names = "default"; 1353 pinctrl-0 = <&qup_uart1_default>; 1354 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1355 power-domains = <&rpmhpd SDM845_CX>; 1356 operating-points-v2 = <&qup_opp_table>; 1357 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1358 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1359 interconnect-names = "qup-core", "qup-config"; 1360 status = "disabled"; 1361 }; 1362 1363 i2c2: i2c@888000 { 1364 compatible = "qcom,geni-i2c"; 1365 reg = <0 0x00888000 0 0x4000>; 1366 clock-names = "se"; 1367 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1368 pinctrl-names = "default"; 1369 pinctrl-0 = <&qup_i2c2_default>; 1370 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1371 #address-cells = <1>; 1372 #size-cells = <0>; 1373 power-domains = <&rpmhpd SDM845_CX>; 1374 operating-points-v2 = <&qup_opp_table>; 1375 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1376 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, 1377 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; 1378 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1379 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1380 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1381 dma-names = "tx", "rx"; 1382 status = "disabled"; 1383 }; 1384 1385 spi2: spi@888000 { 1386 compatible = "qcom,geni-spi"; 1387 reg = <0 0x00888000 0 0x4000>; 1388 clock-names = "se"; 1389 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1390 pinctrl-names = "default"; 1391 pinctrl-0 = <&qup_spi2_default>; 1392 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1393 #address-cells = <1>; 1394 #size-cells = <0>; 1395 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1396 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1397 interconnect-names = "qup-core", "qup-config"; 1398 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1399 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1400 dma-names = "tx", "rx"; 1401 status = "disabled"; 1402 }; 1403 1404 uart2: serial@888000 { 1405 compatible = "qcom,geni-uart"; 1406 reg = <0 0x00888000 0 0x4000>; 1407 clock-names = "se"; 1408 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1409 pinctrl-names = "default"; 1410 pinctrl-0 = <&qup_uart2_default>; 1411 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1412 power-domains = <&rpmhpd SDM845_CX>; 1413 operating-points-v2 = <&qup_opp_table>; 1414 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1415 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1416 interconnect-names = "qup-core", "qup-config"; 1417 status = "disabled"; 1418 }; 1419 1420 i2c3: i2c@88c000 { 1421 compatible = "qcom,geni-i2c"; 1422 reg = <0 0x0088c000 0 0x4000>; 1423 clock-names = "se"; 1424 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1425 pinctrl-names = "default"; 1426 pinctrl-0 = <&qup_i2c3_default>; 1427 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1428 #address-cells = <1>; 1429 #size-cells = <0>; 1430 power-domains = <&rpmhpd SDM845_CX>; 1431 operating-points-v2 = <&qup_opp_table>; 1432 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1433 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, 1434 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; 1435 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1436 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1437 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1438 dma-names = "tx", "rx"; 1439 status = "disabled"; 1440 }; 1441 1442 spi3: spi@88c000 { 1443 compatible = "qcom,geni-spi"; 1444 reg = <0 0x0088c000 0 0x4000>; 1445 clock-names = "se"; 1446 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1447 pinctrl-names = "default"; 1448 pinctrl-0 = <&qup_spi3_default>; 1449 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1450 #address-cells = <1>; 1451 #size-cells = <0>; 1452 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1453 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1454 interconnect-names = "qup-core", "qup-config"; 1455 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1456 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1457 dma-names = "tx", "rx"; 1458 status = "disabled"; 1459 }; 1460 1461 uart3: serial@88c000 { 1462 compatible = "qcom,geni-uart"; 1463 reg = <0 0x0088c000 0 0x4000>; 1464 clock-names = "se"; 1465 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1466 pinctrl-names = "default"; 1467 pinctrl-0 = <&qup_uart3_default>; 1468 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1469 power-domains = <&rpmhpd SDM845_CX>; 1470 operating-points-v2 = <&qup_opp_table>; 1471 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1472 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1473 interconnect-names = "qup-core", "qup-config"; 1474 status = "disabled"; 1475 }; 1476 1477 i2c4: i2c@890000 { 1478 compatible = "qcom,geni-i2c"; 1479 reg = <0 0x00890000 0 0x4000>; 1480 clock-names = "se"; 1481 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1482 pinctrl-names = "default"; 1483 pinctrl-0 = <&qup_i2c4_default>; 1484 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1485 #address-cells = <1>; 1486 #size-cells = <0>; 1487 power-domains = <&rpmhpd SDM845_CX>; 1488 operating-points-v2 = <&qup_opp_table>; 1489 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1490 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, 1491 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; 1492 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1493 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1494 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1495 dma-names = "tx", "rx"; 1496 status = "disabled"; 1497 }; 1498 1499 spi4: spi@890000 { 1500 compatible = "qcom,geni-spi"; 1501 reg = <0 0x00890000 0 0x4000>; 1502 clock-names = "se"; 1503 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1504 pinctrl-names = "default"; 1505 pinctrl-0 = <&qup_spi4_default>; 1506 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1507 #address-cells = <1>; 1508 #size-cells = <0>; 1509 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1510 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1511 interconnect-names = "qup-core", "qup-config"; 1512 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1513 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1514 dma-names = "tx", "rx"; 1515 status = "disabled"; 1516 }; 1517 1518 uart4: serial@890000 { 1519 compatible = "qcom,geni-uart"; 1520 reg = <0 0x00890000 0 0x4000>; 1521 clock-names = "se"; 1522 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1523 pinctrl-names = "default"; 1524 pinctrl-0 = <&qup_uart4_default>; 1525 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1526 power-domains = <&rpmhpd SDM845_CX>; 1527 operating-points-v2 = <&qup_opp_table>; 1528 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1529 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1530 interconnect-names = "qup-core", "qup-config"; 1531 status = "disabled"; 1532 }; 1533 1534 i2c5: i2c@894000 { 1535 compatible = "qcom,geni-i2c"; 1536 reg = <0 0x00894000 0 0x4000>; 1537 clock-names = "se"; 1538 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1539 pinctrl-names = "default"; 1540 pinctrl-0 = <&qup_i2c5_default>; 1541 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1542 #address-cells = <1>; 1543 #size-cells = <0>; 1544 power-domains = <&rpmhpd SDM845_CX>; 1545 operating-points-v2 = <&qup_opp_table>; 1546 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1547 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, 1548 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; 1549 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1550 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1551 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1552 dma-names = "tx", "rx"; 1553 status = "disabled"; 1554 }; 1555 1556 spi5: spi@894000 { 1557 compatible = "qcom,geni-spi"; 1558 reg = <0 0x00894000 0 0x4000>; 1559 clock-names = "se"; 1560 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1561 pinctrl-names = "default"; 1562 pinctrl-0 = <&qup_spi5_default>; 1563 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1564 #address-cells = <1>; 1565 #size-cells = <0>; 1566 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1567 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1568 interconnect-names = "qup-core", "qup-config"; 1569 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1570 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1571 dma-names = "tx", "rx"; 1572 status = "disabled"; 1573 }; 1574 1575 uart5: serial@894000 { 1576 compatible = "qcom,geni-uart"; 1577 reg = <0 0x00894000 0 0x4000>; 1578 clock-names = "se"; 1579 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1580 pinctrl-names = "default"; 1581 pinctrl-0 = <&qup_uart5_default>; 1582 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1583 power-domains = <&rpmhpd SDM845_CX>; 1584 operating-points-v2 = <&qup_opp_table>; 1585 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1586 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1587 interconnect-names = "qup-core", "qup-config"; 1588 status = "disabled"; 1589 }; 1590 1591 i2c6: i2c@898000 { 1592 compatible = "qcom,geni-i2c"; 1593 reg = <0 0x00898000 0 0x4000>; 1594 clock-names = "se"; 1595 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1596 pinctrl-names = "default"; 1597 pinctrl-0 = <&qup_i2c6_default>; 1598 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1599 #address-cells = <1>; 1600 #size-cells = <0>; 1601 power-domains = <&rpmhpd SDM845_CX>; 1602 operating-points-v2 = <&qup_opp_table>; 1603 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1604 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, 1605 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; 1606 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1607 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1608 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1609 dma-names = "tx", "rx"; 1610 status = "disabled"; 1611 }; 1612 1613 spi6: spi@898000 { 1614 compatible = "qcom,geni-spi"; 1615 reg = <0 0x00898000 0 0x4000>; 1616 clock-names = "se"; 1617 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1618 pinctrl-names = "default"; 1619 pinctrl-0 = <&qup_spi6_default>; 1620 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1621 #address-cells = <1>; 1622 #size-cells = <0>; 1623 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1624 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1625 interconnect-names = "qup-core", "qup-config"; 1626 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1627 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1628 dma-names = "tx", "rx"; 1629 status = "disabled"; 1630 }; 1631 1632 uart6: serial@898000 { 1633 compatible = "qcom,geni-uart"; 1634 reg = <0 0x00898000 0 0x4000>; 1635 clock-names = "se"; 1636 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1637 pinctrl-names = "default"; 1638 pinctrl-0 = <&qup_uart6_default>; 1639 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1640 power-domains = <&rpmhpd SDM845_CX>; 1641 operating-points-v2 = <&qup_opp_table>; 1642 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1643 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1644 interconnect-names = "qup-core", "qup-config"; 1645 status = "disabled"; 1646 }; 1647 1648 i2c7: i2c@89c000 { 1649 compatible = "qcom,geni-i2c"; 1650 reg = <0 0x0089c000 0 0x4000>; 1651 clock-names = "se"; 1652 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1653 pinctrl-names = "default"; 1654 pinctrl-0 = <&qup_i2c7_default>; 1655 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1656 #address-cells = <1>; 1657 #size-cells = <0>; 1658 power-domains = <&rpmhpd SDM845_CX>; 1659 operating-points-v2 = <&qup_opp_table>; 1660 status = "disabled"; 1661 }; 1662 1663 spi7: spi@89c000 { 1664 compatible = "qcom,geni-spi"; 1665 reg = <0 0x0089c000 0 0x4000>; 1666 clock-names = "se"; 1667 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1668 pinctrl-names = "default"; 1669 pinctrl-0 = <&qup_spi7_default>; 1670 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1671 #address-cells = <1>; 1672 #size-cells = <0>; 1673 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1674 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1675 interconnect-names = "qup-core", "qup-config"; 1676 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1677 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1678 dma-names = "tx", "rx"; 1679 status = "disabled"; 1680 }; 1681 1682 uart7: serial@89c000 { 1683 compatible = "qcom,geni-uart"; 1684 reg = <0 0x0089c000 0 0x4000>; 1685 clock-names = "se"; 1686 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1687 pinctrl-names = "default"; 1688 pinctrl-0 = <&qup_uart7_default>; 1689 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1690 power-domains = <&rpmhpd SDM845_CX>; 1691 operating-points-v2 = <&qup_opp_table>; 1692 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1693 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1694 interconnect-names = "qup-core", "qup-config"; 1695 status = "disabled"; 1696 }; 1697 }; 1698 1699 gpi_dma1: dma-controller@a00000 { 1700 #dma-cells = <3>; 1701 compatible = "qcom,sdm845-gpi-dma"; 1702 reg = <0 0x00a00000 0 0x60000>; 1703 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1704 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1705 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1706 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1707 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1708 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1709 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1710 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1711 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1712 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1713 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1714 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 1715 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 1716 dma-channels = <13>; 1717 dma-channel-mask = <0xfa>; 1718 iommus = <&apps_smmu 0x06d6 0x0>; 1719 status = "disabled"; 1720 }; 1721 1722 qupv3_id_1: geniqup@ac0000 { 1723 compatible = "qcom,geni-se-qup"; 1724 reg = <0 0x00ac0000 0 0x6000>; 1725 clock-names = "m-ahb", "s-ahb"; 1726 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1727 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1728 iommus = <&apps_smmu 0x6c3 0x0>; 1729 #address-cells = <2>; 1730 #size-cells = <2>; 1731 ranges; 1732 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>; 1733 interconnect-names = "qup-core"; 1734 status = "disabled"; 1735 1736 i2c8: i2c@a80000 { 1737 compatible = "qcom,geni-i2c"; 1738 reg = <0 0x00a80000 0 0x4000>; 1739 clock-names = "se"; 1740 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1741 pinctrl-names = "default"; 1742 pinctrl-0 = <&qup_i2c8_default>; 1743 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1744 #address-cells = <1>; 1745 #size-cells = <0>; 1746 power-domains = <&rpmhpd SDM845_CX>; 1747 operating-points-v2 = <&qup_opp_table>; 1748 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1749 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 1750 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 1751 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1752 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1753 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1754 dma-names = "tx", "rx"; 1755 status = "disabled"; 1756 }; 1757 1758 spi8: spi@a80000 { 1759 compatible = "qcom,geni-spi"; 1760 reg = <0 0x00a80000 0 0x4000>; 1761 clock-names = "se"; 1762 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1763 pinctrl-names = "default"; 1764 pinctrl-0 = <&qup_spi8_default>; 1765 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1766 #address-cells = <1>; 1767 #size-cells = <0>; 1768 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1769 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1770 interconnect-names = "qup-core", "qup-config"; 1771 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1772 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1773 dma-names = "tx", "rx"; 1774 status = "disabled"; 1775 }; 1776 1777 uart8: serial@a80000 { 1778 compatible = "qcom,geni-uart"; 1779 reg = <0 0x00a80000 0 0x4000>; 1780 clock-names = "se"; 1781 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1782 pinctrl-names = "default"; 1783 pinctrl-0 = <&qup_uart8_default>; 1784 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1785 power-domains = <&rpmhpd SDM845_CX>; 1786 operating-points-v2 = <&qup_opp_table>; 1787 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1788 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1789 interconnect-names = "qup-core", "qup-config"; 1790 status = "disabled"; 1791 }; 1792 1793 i2c9: i2c@a84000 { 1794 compatible = "qcom,geni-i2c"; 1795 reg = <0 0x00a84000 0 0x4000>; 1796 clock-names = "se"; 1797 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1798 pinctrl-names = "default"; 1799 pinctrl-0 = <&qup_i2c9_default>; 1800 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1801 #address-cells = <1>; 1802 #size-cells = <0>; 1803 power-domains = <&rpmhpd SDM845_CX>; 1804 operating-points-v2 = <&qup_opp_table>; 1805 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1806 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 1807 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 1808 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1809 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1810 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1811 dma-names = "tx", "rx"; 1812 status = "disabled"; 1813 }; 1814 1815 spi9: spi@a84000 { 1816 compatible = "qcom,geni-spi"; 1817 reg = <0 0x00a84000 0 0x4000>; 1818 clock-names = "se"; 1819 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1820 pinctrl-names = "default"; 1821 pinctrl-0 = <&qup_spi9_default>; 1822 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1823 #address-cells = <1>; 1824 #size-cells = <0>; 1825 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1826 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1827 interconnect-names = "qup-core", "qup-config"; 1828 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1829 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1830 dma-names = "tx", "rx"; 1831 status = "disabled"; 1832 }; 1833 1834 uart9: serial@a84000 { 1835 compatible = "qcom,geni-debug-uart"; 1836 reg = <0 0x00a84000 0 0x4000>; 1837 clock-names = "se"; 1838 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1839 pinctrl-names = "default"; 1840 pinctrl-0 = <&qup_uart9_default>; 1841 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1842 power-domains = <&rpmhpd SDM845_CX>; 1843 operating-points-v2 = <&qup_opp_table>; 1844 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1845 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1846 interconnect-names = "qup-core", "qup-config"; 1847 status = "disabled"; 1848 }; 1849 1850 i2c10: i2c@a88000 { 1851 compatible = "qcom,geni-i2c"; 1852 reg = <0 0x00a88000 0 0x4000>; 1853 clock-names = "se"; 1854 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1855 pinctrl-names = "default"; 1856 pinctrl-0 = <&qup_i2c10_default>; 1857 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1858 #address-cells = <1>; 1859 #size-cells = <0>; 1860 power-domains = <&rpmhpd SDM845_CX>; 1861 operating-points-v2 = <&qup_opp_table>; 1862 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1863 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 1864 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 1865 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1866 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1867 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1868 dma-names = "tx", "rx"; 1869 status = "disabled"; 1870 }; 1871 1872 spi10: spi@a88000 { 1873 compatible = "qcom,geni-spi"; 1874 reg = <0 0x00a88000 0 0x4000>; 1875 clock-names = "se"; 1876 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1877 pinctrl-names = "default"; 1878 pinctrl-0 = <&qup_spi10_default>; 1879 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1880 #address-cells = <1>; 1881 #size-cells = <0>; 1882 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1883 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1884 interconnect-names = "qup-core", "qup-config"; 1885 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1886 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1887 dma-names = "tx", "rx"; 1888 status = "disabled"; 1889 }; 1890 1891 uart10: serial@a88000 { 1892 compatible = "qcom,geni-uart"; 1893 reg = <0 0x00a88000 0 0x4000>; 1894 clock-names = "se"; 1895 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1896 pinctrl-names = "default"; 1897 pinctrl-0 = <&qup_uart10_default>; 1898 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1899 power-domains = <&rpmhpd SDM845_CX>; 1900 operating-points-v2 = <&qup_opp_table>; 1901 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1902 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1903 interconnect-names = "qup-core", "qup-config"; 1904 status = "disabled"; 1905 }; 1906 1907 i2c11: i2c@a8c000 { 1908 compatible = "qcom,geni-i2c"; 1909 reg = <0 0x00a8c000 0 0x4000>; 1910 clock-names = "se"; 1911 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1912 pinctrl-names = "default"; 1913 pinctrl-0 = <&qup_i2c11_default>; 1914 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1915 #address-cells = <1>; 1916 #size-cells = <0>; 1917 power-domains = <&rpmhpd SDM845_CX>; 1918 operating-points-v2 = <&qup_opp_table>; 1919 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1920 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 1921 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 1922 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1923 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1924 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1925 dma-names = "tx", "rx"; 1926 status = "disabled"; 1927 }; 1928 1929 spi11: spi@a8c000 { 1930 compatible = "qcom,geni-spi"; 1931 reg = <0 0x00a8c000 0 0x4000>; 1932 clock-names = "se"; 1933 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1934 pinctrl-names = "default"; 1935 pinctrl-0 = <&qup_spi11_default>; 1936 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1937 #address-cells = <1>; 1938 #size-cells = <0>; 1939 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1940 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1941 interconnect-names = "qup-core", "qup-config"; 1942 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1943 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1944 dma-names = "tx", "rx"; 1945 status = "disabled"; 1946 }; 1947 1948 uart11: serial@a8c000 { 1949 compatible = "qcom,geni-uart"; 1950 reg = <0 0x00a8c000 0 0x4000>; 1951 clock-names = "se"; 1952 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1953 pinctrl-names = "default"; 1954 pinctrl-0 = <&qup_uart11_default>; 1955 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1956 power-domains = <&rpmhpd SDM845_CX>; 1957 operating-points-v2 = <&qup_opp_table>; 1958 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1959 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1960 interconnect-names = "qup-core", "qup-config"; 1961 status = "disabled"; 1962 }; 1963 1964 i2c12: i2c@a90000 { 1965 compatible = "qcom,geni-i2c"; 1966 reg = <0 0x00a90000 0 0x4000>; 1967 clock-names = "se"; 1968 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1969 pinctrl-names = "default"; 1970 pinctrl-0 = <&qup_i2c12_default>; 1971 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1972 #address-cells = <1>; 1973 #size-cells = <0>; 1974 power-domains = <&rpmhpd SDM845_CX>; 1975 operating-points-v2 = <&qup_opp_table>; 1976 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1977 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 1978 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 1979 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1980 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1981 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1982 dma-names = "tx", "rx"; 1983 status = "disabled"; 1984 }; 1985 1986 spi12: spi@a90000 { 1987 compatible = "qcom,geni-spi"; 1988 reg = <0 0x00a90000 0 0x4000>; 1989 clock-names = "se"; 1990 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1991 pinctrl-names = "default"; 1992 pinctrl-0 = <&qup_spi12_default>; 1993 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1994 #address-cells = <1>; 1995 #size-cells = <0>; 1996 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1997 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1998 interconnect-names = "qup-core", "qup-config"; 1999 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 2000 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 2001 dma-names = "tx", "rx"; 2002 status = "disabled"; 2003 }; 2004 2005 uart12: serial@a90000 { 2006 compatible = "qcom,geni-uart"; 2007 reg = <0 0x00a90000 0 0x4000>; 2008 clock-names = "se"; 2009 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 2010 pinctrl-names = "default"; 2011 pinctrl-0 = <&qup_uart12_default>; 2012 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 2013 power-domains = <&rpmhpd SDM845_CX>; 2014 operating-points-v2 = <&qup_opp_table>; 2015 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2016 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 2017 interconnect-names = "qup-core", "qup-config"; 2018 status = "disabled"; 2019 }; 2020 2021 i2c13: i2c@a94000 { 2022 compatible = "qcom,geni-i2c"; 2023 reg = <0 0x00a94000 0 0x4000>; 2024 clock-names = "se"; 2025 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 2026 pinctrl-names = "default"; 2027 pinctrl-0 = <&qup_i2c13_default>; 2028 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 2029 #address-cells = <1>; 2030 #size-cells = <0>; 2031 power-domains = <&rpmhpd SDM845_CX>; 2032 operating-points-v2 = <&qup_opp_table>; 2033 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2034 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 2035 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 2036 interconnect-names = "qup-core", "qup-config", "qup-memory"; 2037 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 2038 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 2039 dma-names = "tx", "rx"; 2040 status = "disabled"; 2041 }; 2042 2043 spi13: spi@a94000 { 2044 compatible = "qcom,geni-spi"; 2045 reg = <0 0x00a94000 0 0x4000>; 2046 clock-names = "se"; 2047 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 2048 pinctrl-names = "default"; 2049 pinctrl-0 = <&qup_spi13_default>; 2050 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 2051 #address-cells = <1>; 2052 #size-cells = <0>; 2053 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2054 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 2055 interconnect-names = "qup-core", "qup-config"; 2056 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 2057 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 2058 dma-names = "tx", "rx"; 2059 status = "disabled"; 2060 }; 2061 2062 uart13: serial@a94000 { 2063 compatible = "qcom,geni-uart"; 2064 reg = <0 0x00a94000 0 0x4000>; 2065 clock-names = "se"; 2066 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 2067 pinctrl-names = "default"; 2068 pinctrl-0 = <&qup_uart13_default>; 2069 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 2070 power-domains = <&rpmhpd SDM845_CX>; 2071 operating-points-v2 = <&qup_opp_table>; 2072 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2073 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 2074 interconnect-names = "qup-core", "qup-config"; 2075 status = "disabled"; 2076 }; 2077 2078 i2c14: i2c@a98000 { 2079 compatible = "qcom,geni-i2c"; 2080 reg = <0 0x00a98000 0 0x4000>; 2081 clock-names = "se"; 2082 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2083 pinctrl-names = "default"; 2084 pinctrl-0 = <&qup_i2c14_default>; 2085 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 2086 #address-cells = <1>; 2087 #size-cells = <0>; 2088 power-domains = <&rpmhpd SDM845_CX>; 2089 operating-points-v2 = <&qup_opp_table>; 2090 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2091 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 2092 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 2093 interconnect-names = "qup-core", "qup-config", "qup-memory"; 2094 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 2095 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 2096 dma-names = "tx", "rx"; 2097 status = "disabled"; 2098 }; 2099 2100 spi14: spi@a98000 { 2101 compatible = "qcom,geni-spi"; 2102 reg = <0 0x00a98000 0 0x4000>; 2103 clock-names = "se"; 2104 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2105 pinctrl-names = "default"; 2106 pinctrl-0 = <&qup_spi14_default>; 2107 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 2108 #address-cells = <1>; 2109 #size-cells = <0>; 2110 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2111 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 2112 interconnect-names = "qup-core", "qup-config"; 2113 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 2114 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 2115 dma-names = "tx", "rx"; 2116 status = "disabled"; 2117 }; 2118 2119 uart14: serial@a98000 { 2120 compatible = "qcom,geni-uart"; 2121 reg = <0 0x00a98000 0 0x4000>; 2122 clock-names = "se"; 2123 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2124 pinctrl-names = "default"; 2125 pinctrl-0 = <&qup_uart14_default>; 2126 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 2127 power-domains = <&rpmhpd SDM845_CX>; 2128 operating-points-v2 = <&qup_opp_table>; 2129 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2130 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 2131 interconnect-names = "qup-core", "qup-config"; 2132 status = "disabled"; 2133 }; 2134 2135 i2c15: i2c@a9c000 { 2136 compatible = "qcom,geni-i2c"; 2137 reg = <0 0x00a9c000 0 0x4000>; 2138 clock-names = "se"; 2139 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2140 pinctrl-names = "default"; 2141 pinctrl-0 = <&qup_i2c15_default>; 2142 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 2143 #address-cells = <1>; 2144 #size-cells = <0>; 2145 power-domains = <&rpmhpd SDM845_CX>; 2146 operating-points-v2 = <&qup_opp_table>; 2147 status = "disabled"; 2148 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2149 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 2150 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 2151 interconnect-names = "qup-core", "qup-config", "qup-memory"; 2152 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, 2153 <&gpi_dma1 1 7 QCOM_GPI_I2C>; 2154 dma-names = "tx", "rx"; 2155 }; 2156 2157 spi15: spi@a9c000 { 2158 compatible = "qcom,geni-spi"; 2159 reg = <0 0x00a9c000 0 0x4000>; 2160 clock-names = "se"; 2161 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2162 pinctrl-names = "default"; 2163 pinctrl-0 = <&qup_spi15_default>; 2164 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 2165 #address-cells = <1>; 2166 #size-cells = <0>; 2167 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2168 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 2169 interconnect-names = "qup-core", "qup-config"; 2170 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, 2171 <&gpi_dma1 1 7 QCOM_GPI_SPI>; 2172 dma-names = "tx", "rx"; 2173 status = "disabled"; 2174 }; 2175 2176 uart15: serial@a9c000 { 2177 compatible = "qcom,geni-uart"; 2178 reg = <0 0x00a9c000 0 0x4000>; 2179 clock-names = "se"; 2180 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2181 pinctrl-names = "default"; 2182 pinctrl-0 = <&qup_uart15_default>; 2183 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 2184 power-domains = <&rpmhpd SDM845_CX>; 2185 operating-points-v2 = <&qup_opp_table>; 2186 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 2187 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 2188 interconnect-names = "qup-core", "qup-config"; 2189 status = "disabled"; 2190 }; 2191 }; 2192 2193 llcc: system-cache-controller@1100000 { 2194 compatible = "qcom,sdm845-llcc"; 2195 reg = <0 0x01100000 0 0x31000>, <0 0x01300000 0 0x50000>; 2196 reg-names = "llcc_base", "llcc_broadcast_base"; 2197 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 2198 }; 2199 2200 dma@10a2000 { 2201 compatible = "qcom,sdm845-dcc", "qcom,dcc"; 2202 reg = <0x0 0x010a2000 0x0 0x1000>, 2203 <0x0 0x010ae000 0x0 0x2000>; 2204 }; 2205 2206 pmu@114a000 { 2207 compatible = "qcom,sdm845-llcc-bwmon"; 2208 reg = <0 0x0114a000 0 0x1000>; 2209 interrupts = <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>; 2210 interconnects = <&mem_noc MASTER_LLCC 3 &mem_noc SLAVE_EBI1 3>; 2211 2212 operating-points-v2 = <&llcc_bwmon_opp_table>; 2213 2214 llcc_bwmon_opp_table: opp-table { 2215 compatible = "operating-points-v2"; 2216 2217 /* 2218 * The interconnect path bandwidth taken from 2219 * cpu4_opp_table bandwidth for gladiator_noc-mem_noc 2220 * interconnect. This also matches the 2221 * bandwidth table of qcom,llccbw (qcom,bw-tbl, 2222 * bus width: 4 bytes) from msm-4.9 downstream 2223 * kernel. 2224 */ 2225 opp-0 { 2226 opp-peak-kBps = <800000>; 2227 }; 2228 opp-1 { 2229 opp-peak-kBps = <1804000>; 2230 }; 2231 opp-2 { 2232 opp-peak-kBps = <3072000>; 2233 }; 2234 opp-3 { 2235 opp-peak-kBps = <5412000>; 2236 }; 2237 opp-4 { 2238 opp-peak-kBps = <7216000>; 2239 }; 2240 }; 2241 }; 2242 2243 pmu@1436400 { 2244 compatible = "qcom,sdm845-bwmon", "qcom,msm8998-bwmon"; 2245 reg = <0 0x01436400 0 0x600>; 2246 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 2247 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_LLCC 3>; 2248 2249 operating-points-v2 = <&cpu_bwmon_opp_table>; 2250 2251 cpu_bwmon_opp_table: opp-table { 2252 compatible = "operating-points-v2"; 2253 2254 /* 2255 * The interconnect path bandwidth taken from 2256 * cpu4_opp_table bandwidth for OSM L3 2257 * interconnect. This also matches the OSM L3 2258 * from bandwidth table of qcom,cpu4-l3lat-mon 2259 * (qcom,core-dev-table, bus width: 16 bytes) 2260 * from msm-4.9 downstream kernel. 2261 */ 2262 opp-0 { 2263 opp-peak-kBps = <4800000>; 2264 }; 2265 opp-1 { 2266 opp-peak-kBps = <9216000>; 2267 }; 2268 opp-2 { 2269 opp-peak-kBps = <15052800>; 2270 }; 2271 opp-3 { 2272 opp-peak-kBps = <20889600>; 2273 }; 2274 opp-4 { 2275 opp-peak-kBps = <25497600>; 2276 }; 2277 }; 2278 }; 2279 2280 pcie0: pci@1c00000 { 2281 compatible = "qcom,pcie-sdm845"; 2282 reg = <0 0x01c00000 0 0x2000>, 2283 <0 0x60000000 0 0xf1d>, 2284 <0 0x60000f20 0 0xa8>, 2285 <0 0x60100000 0 0x100000>; 2286 reg-names = "parf", "dbi", "elbi", "config"; 2287 device_type = "pci"; 2288 linux,pci-domain = <0>; 2289 bus-range = <0x00 0xff>; 2290 num-lanes = <1>; 2291 2292 #address-cells = <3>; 2293 #size-cells = <2>; 2294 2295 ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>, 2296 <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0xd00000>; 2297 2298 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 2299 interrupt-names = "msi"; 2300 #interrupt-cells = <1>; 2301 interrupt-map-mask = <0 0 0 0x7>; 2302 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 2303 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 2304 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 2305 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 2306 2307 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 2308 <&gcc GCC_PCIE_0_AUX_CLK>, 2309 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 2310 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 2311 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 2312 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 2313 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; 2314 clock-names = "pipe", 2315 "aux", 2316 "cfg", 2317 "bus_master", 2318 "bus_slave", 2319 "slave_q2a", 2320 "tbu"; 2321 2322 iommus = <&apps_smmu 0x1c10 0xf>; 2323 iommu-map = <0x0 &apps_smmu 0x1c10 0x1>, 2324 <0x100 &apps_smmu 0x1c11 0x1>, 2325 <0x200 &apps_smmu 0x1c12 0x1>, 2326 <0x300 &apps_smmu 0x1c13 0x1>, 2327 <0x400 &apps_smmu 0x1c14 0x1>, 2328 <0x500 &apps_smmu 0x1c15 0x1>, 2329 <0x600 &apps_smmu 0x1c16 0x1>, 2330 <0x700 &apps_smmu 0x1c17 0x1>, 2331 <0x800 &apps_smmu 0x1c18 0x1>, 2332 <0x900 &apps_smmu 0x1c19 0x1>, 2333 <0xa00 &apps_smmu 0x1c1a 0x1>, 2334 <0xb00 &apps_smmu 0x1c1b 0x1>, 2335 <0xc00 &apps_smmu 0x1c1c 0x1>, 2336 <0xd00 &apps_smmu 0x1c1d 0x1>, 2337 <0xe00 &apps_smmu 0x1c1e 0x1>, 2338 <0xf00 &apps_smmu 0x1c1f 0x1>; 2339 2340 resets = <&gcc GCC_PCIE_0_BCR>; 2341 reset-names = "pci"; 2342 2343 power-domains = <&gcc PCIE_0_GDSC>; 2344 2345 phys = <&pcie0_lane>; 2346 phy-names = "pciephy"; 2347 2348 status = "disabled"; 2349 }; 2350 2351 pcie0_phy: phy@1c06000 { 2352 compatible = "qcom,sdm845-qmp-pcie-phy"; 2353 reg = <0 0x01c06000 0 0x18c>; 2354 #address-cells = <2>; 2355 #size-cells = <2>; 2356 ranges; 2357 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 2358 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 2359 <&gcc GCC_PCIE_0_CLKREF_CLK>, 2360 <&gcc GCC_PCIE_PHY_REFGEN_CLK>; 2361 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 2362 2363 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 2364 reset-names = "phy"; 2365 2366 assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>; 2367 assigned-clock-rates = <100000000>; 2368 2369 status = "disabled"; 2370 2371 pcie0_lane: phy@1c06200 { 2372 reg = <0 0x01c06200 0 0x128>, 2373 <0 0x01c06400 0 0x1fc>, 2374 <0 0x01c06800 0 0x218>, 2375 <0 0x01c06600 0 0x70>; 2376 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 2377 clock-names = "pipe0"; 2378 2379 #clock-cells = <0>; 2380 #phy-cells = <0>; 2381 clock-output-names = "pcie_0_pipe_clk"; 2382 }; 2383 }; 2384 2385 pcie1: pci@1c08000 { 2386 compatible = "qcom,pcie-sdm845"; 2387 reg = <0 0x01c08000 0 0x2000>, 2388 <0 0x40000000 0 0xf1d>, 2389 <0 0x40000f20 0 0xa8>, 2390 <0 0x40100000 0 0x100000>; 2391 reg-names = "parf", "dbi", "elbi", "config"; 2392 device_type = "pci"; 2393 linux,pci-domain = <1>; 2394 bus-range = <0x00 0xff>; 2395 num-lanes = <1>; 2396 2397 #address-cells = <3>; 2398 #size-cells = <2>; 2399 2400 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, 2401 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 2402 2403 interrupts = <GIC_SPI 307 IRQ_TYPE_EDGE_RISING>; 2404 interrupt-names = "msi"; 2405 #interrupt-cells = <1>; 2406 interrupt-map-mask = <0 0 0 0x7>; 2407 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 2408 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 2409 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 2410 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 2411 2412 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 2413 <&gcc GCC_PCIE_1_AUX_CLK>, 2414 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2415 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 2416 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 2417 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 2418 <&gcc GCC_PCIE_1_CLKREF_CLK>, 2419 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; 2420 clock-names = "pipe", 2421 "aux", 2422 "cfg", 2423 "bus_master", 2424 "bus_slave", 2425 "slave_q2a", 2426 "ref", 2427 "tbu"; 2428 2429 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 2430 assigned-clock-rates = <19200000>; 2431 2432 iommus = <&apps_smmu 0x1c00 0xf>; 2433 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, 2434 <0x100 &apps_smmu 0x1c01 0x1>, 2435 <0x200 &apps_smmu 0x1c02 0x1>, 2436 <0x300 &apps_smmu 0x1c03 0x1>, 2437 <0x400 &apps_smmu 0x1c04 0x1>, 2438 <0x500 &apps_smmu 0x1c05 0x1>, 2439 <0x600 &apps_smmu 0x1c06 0x1>, 2440 <0x700 &apps_smmu 0x1c07 0x1>, 2441 <0x800 &apps_smmu 0x1c08 0x1>, 2442 <0x900 &apps_smmu 0x1c09 0x1>, 2443 <0xa00 &apps_smmu 0x1c0a 0x1>, 2444 <0xb00 &apps_smmu 0x1c0b 0x1>, 2445 <0xc00 &apps_smmu 0x1c0c 0x1>, 2446 <0xd00 &apps_smmu 0x1c0d 0x1>, 2447 <0xe00 &apps_smmu 0x1c0e 0x1>, 2448 <0xf00 &apps_smmu 0x1c0f 0x1>; 2449 2450 resets = <&gcc GCC_PCIE_1_BCR>; 2451 reset-names = "pci"; 2452 2453 power-domains = <&gcc PCIE_1_GDSC>; 2454 2455 phys = <&pcie1_lane>; 2456 phy-names = "pciephy"; 2457 2458 status = "disabled"; 2459 }; 2460 2461 pcie1_phy: phy@1c0a000 { 2462 compatible = "qcom,sdm845-qhp-pcie-phy"; 2463 reg = <0 0x01c0a000 0 0x800>; 2464 #address-cells = <2>; 2465 #size-cells = <2>; 2466 ranges; 2467 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 2468 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2469 <&gcc GCC_PCIE_1_CLKREF_CLK>, 2470 <&gcc GCC_PCIE_PHY_REFGEN_CLK>; 2471 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 2472 2473 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 2474 reset-names = "phy"; 2475 2476 assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>; 2477 assigned-clock-rates = <100000000>; 2478 2479 status = "disabled"; 2480 2481 pcie1_lane: phy@1c06200 { 2482 reg = <0 0x01c0a800 0 0x800>, 2483 <0 0x01c0a800 0 0x800>, 2484 <0 0x01c0b800 0 0x400>; 2485 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 2486 clock-names = "pipe0"; 2487 2488 #clock-cells = <0>; 2489 #phy-cells = <0>; 2490 clock-output-names = "pcie_1_pipe_clk"; 2491 }; 2492 }; 2493 2494 mem_noc: interconnect@1380000 { 2495 compatible = "qcom,sdm845-mem-noc"; 2496 reg = <0 0x01380000 0 0x27200>; 2497 #interconnect-cells = <2>; 2498 qcom,bcm-voters = <&apps_bcm_voter>; 2499 }; 2500 2501 dc_noc: interconnect@14e0000 { 2502 compatible = "qcom,sdm845-dc-noc"; 2503 reg = <0 0x014e0000 0 0x400>; 2504 #interconnect-cells = <2>; 2505 qcom,bcm-voters = <&apps_bcm_voter>; 2506 }; 2507 2508 config_noc: interconnect@1500000 { 2509 compatible = "qcom,sdm845-config-noc"; 2510 reg = <0 0x01500000 0 0x5080>; 2511 #interconnect-cells = <2>; 2512 qcom,bcm-voters = <&apps_bcm_voter>; 2513 }; 2514 2515 system_noc: interconnect@1620000 { 2516 compatible = "qcom,sdm845-system-noc"; 2517 reg = <0 0x01620000 0 0x18080>; 2518 #interconnect-cells = <2>; 2519 qcom,bcm-voters = <&apps_bcm_voter>; 2520 }; 2521 2522 aggre1_noc: interconnect@16e0000 { 2523 compatible = "qcom,sdm845-aggre1-noc"; 2524 reg = <0 0x016e0000 0 0x15080>; 2525 #interconnect-cells = <2>; 2526 qcom,bcm-voters = <&apps_bcm_voter>; 2527 }; 2528 2529 aggre2_noc: interconnect@1700000 { 2530 compatible = "qcom,sdm845-aggre2-noc"; 2531 reg = <0 0x01700000 0 0x1f300>; 2532 #interconnect-cells = <2>; 2533 qcom,bcm-voters = <&apps_bcm_voter>; 2534 }; 2535 2536 mmss_noc: interconnect@1740000 { 2537 compatible = "qcom,sdm845-mmss-noc"; 2538 reg = <0 0x01740000 0 0x1c100>; 2539 #interconnect-cells = <2>; 2540 qcom,bcm-voters = <&apps_bcm_voter>; 2541 }; 2542 2543 ufs_mem_hc: ufshc@1d84000 { 2544 compatible = "qcom,sdm845-ufshc", "qcom,ufshc", 2545 "jedec,ufs-2.0"; 2546 reg = <0 0x01d84000 0 0x2500>, 2547 <0 0x01d90000 0 0x8000>; 2548 reg-names = "std", "ice"; 2549 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2550 phys = <&ufs_mem_phy_lanes>; 2551 phy-names = "ufsphy"; 2552 lanes-per-direction = <2>; 2553 power-domains = <&gcc UFS_PHY_GDSC>; 2554 #reset-cells = <1>; 2555 resets = <&gcc GCC_UFS_PHY_BCR>; 2556 reset-names = "rst"; 2557 2558 iommus = <&apps_smmu 0x100 0xf>; 2559 2560 clock-names = 2561 "core_clk", 2562 "bus_aggr_clk", 2563 "iface_clk", 2564 "core_clk_unipro", 2565 "ref_clk", 2566 "tx_lane0_sync_clk", 2567 "rx_lane0_sync_clk", 2568 "rx_lane1_sync_clk", 2569 "ice_core_clk"; 2570 clocks = 2571 <&gcc GCC_UFS_PHY_AXI_CLK>, 2572 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2573 <&gcc GCC_UFS_PHY_AHB_CLK>, 2574 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2575 <&rpmhcc RPMH_CXO_CLK>, 2576 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2577 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2578 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, 2579 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 2580 freq-table-hz = 2581 <50000000 200000000>, 2582 <0 0>, 2583 <0 0>, 2584 <37500000 150000000>, 2585 <0 0>, 2586 <0 0>, 2587 <0 0>, 2588 <0 0>, 2589 <0 300000000>; 2590 2591 status = "disabled"; 2592 }; 2593 2594 ufs_mem_phy: phy@1d87000 { 2595 compatible = "qcom,sdm845-qmp-ufs-phy"; 2596 reg = <0 0x01d87000 0 0x18c>; 2597 #address-cells = <2>; 2598 #size-cells = <2>; 2599 ranges; 2600 clock-names = "ref", 2601 "ref_aux"; 2602 clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, 2603 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 2604 2605 resets = <&ufs_mem_hc 0>; 2606 reset-names = "ufsphy"; 2607 status = "disabled"; 2608 2609 ufs_mem_phy_lanes: phy@1d87400 { 2610 reg = <0 0x01d87400 0 0x108>, 2611 <0 0x01d87600 0 0x1e0>, 2612 <0 0x01d87c00 0 0x1dc>, 2613 <0 0x01d87800 0 0x108>, 2614 <0 0x01d87a00 0 0x1e0>; 2615 #phy-cells = <0>; 2616 }; 2617 }; 2618 2619 cryptobam: dma-controller@1dc4000 { 2620 compatible = "qcom,bam-v1.7.0"; 2621 reg = <0 0x01dc4000 0 0x24000>; 2622 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 2623 clocks = <&rpmhcc RPMH_CE_CLK>; 2624 clock-names = "bam_clk"; 2625 #dma-cells = <1>; 2626 qcom,ee = <0>; 2627 qcom,controlled-remotely; 2628 iommus = <&apps_smmu 0x704 0x1>, 2629 <&apps_smmu 0x706 0x1>, 2630 <&apps_smmu 0x714 0x1>, 2631 <&apps_smmu 0x716 0x1>; 2632 }; 2633 2634 crypto: crypto@1dfa000 { 2635 compatible = "qcom,crypto-v5.4"; 2636 reg = <0 0x01dfa000 0 0x6000>; 2637 clocks = <&gcc GCC_CE1_AHB_CLK>, 2638 <&gcc GCC_CE1_AXI_CLK>, 2639 <&rpmhcc RPMH_CE_CLK>; 2640 clock-names = "iface", "bus", "core"; 2641 dmas = <&cryptobam 6>, <&cryptobam 7>; 2642 dma-names = "rx", "tx"; 2643 iommus = <&apps_smmu 0x704 0x1>, 2644 <&apps_smmu 0x706 0x1>, 2645 <&apps_smmu 0x714 0x1>, 2646 <&apps_smmu 0x716 0x1>; 2647 }; 2648 2649 ipa: ipa@1e40000 { 2650 compatible = "qcom,sdm845-ipa"; 2651 2652 iommus = <&apps_smmu 0x720 0x0>, 2653 <&apps_smmu 0x722 0x0>; 2654 reg = <0 0x01e40000 0 0x7000>, 2655 <0 0x01e47000 0 0x2000>, 2656 <0 0x01e04000 0 0x2c000>; 2657 reg-names = "ipa-reg", 2658 "ipa-shared", 2659 "gsi"; 2660 2661 interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>, 2662 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 2663 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2664 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 2665 interrupt-names = "ipa", 2666 "gsi", 2667 "ipa-clock-query", 2668 "ipa-setup-ready"; 2669 2670 clocks = <&rpmhcc RPMH_IPA_CLK>; 2671 clock-names = "core"; 2672 2673 interconnects = <&aggre2_noc MASTER_IPA 0 &mem_noc SLAVE_EBI1 0>, 2674 <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>, 2675 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>; 2676 interconnect-names = "memory", 2677 "imem", 2678 "config"; 2679 2680 qcom,smem-states = <&ipa_smp2p_out 0>, 2681 <&ipa_smp2p_out 1>; 2682 qcom,smem-state-names = "ipa-clock-enabled-valid", 2683 "ipa-clock-enabled"; 2684 2685 status = "disabled"; 2686 }; 2687 2688 tcsr_mutex: hwlock@1f40000 { 2689 compatible = "qcom,tcsr-mutex"; 2690 reg = <0 0x01f40000 0 0x20000>; 2691 #hwlock-cells = <1>; 2692 }; 2693 2694 tcsr_regs_1: syscon@1f60000 { 2695 compatible = "qcom,sdm845-tcsr", "syscon"; 2696 reg = <0 0x01f60000 0 0x20000>; 2697 }; 2698 2699 tlmm: pinctrl@3400000 { 2700 compatible = "qcom,sdm845-pinctrl"; 2701 reg = <0 0x03400000 0 0xc00000>; 2702 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 2703 gpio-controller; 2704 #gpio-cells = <2>; 2705 interrupt-controller; 2706 #interrupt-cells = <2>; 2707 gpio-ranges = <&tlmm 0 0 151>; 2708 wakeup-parent = <&pdc_intc>; 2709 2710 cci0_default: cci0-default-state { 2711 /* SDA, SCL */ 2712 pins = "gpio17", "gpio18"; 2713 function = "cci_i2c"; 2714 2715 bias-pull-up; 2716 drive-strength = <2>; /* 2 mA */ 2717 }; 2718 2719 cci0_sleep: cci0-sleep-state { 2720 /* SDA, SCL */ 2721 pins = "gpio17", "gpio18"; 2722 function = "cci_i2c"; 2723 2724 drive-strength = <2>; /* 2 mA */ 2725 bias-pull-down; 2726 }; 2727 2728 cci1_default: cci1-default-state { 2729 /* SDA, SCL */ 2730 pins = "gpio19", "gpio20"; 2731 function = "cci_i2c"; 2732 2733 bias-pull-up; 2734 drive-strength = <2>; /* 2 mA */ 2735 }; 2736 2737 cci1_sleep: cci1-sleep-state { 2738 /* SDA, SCL */ 2739 pins = "gpio19", "gpio20"; 2740 function = "cci_i2c"; 2741 2742 drive-strength = <2>; /* 2 mA */ 2743 bias-pull-down; 2744 }; 2745 2746 qspi_clk: qspi-clk-state { 2747 pins = "gpio95"; 2748 function = "qspi_clk"; 2749 }; 2750 2751 qspi_cs0: qspi-cs0-state { 2752 pins = "gpio90"; 2753 function = "qspi_cs"; 2754 }; 2755 2756 qspi_cs1: qspi-cs1-state { 2757 pins = "gpio89"; 2758 function = "qspi_cs"; 2759 }; 2760 2761 qspi_data01: qspi-data01-state { 2762 pins = "gpio91", "gpio92"; 2763 function = "qspi_data"; 2764 }; 2765 2766 qspi_data12: qspi-data12-state { 2767 pins = "gpio93", "gpio94"; 2768 function = "qspi_data"; 2769 }; 2770 2771 qup_i2c0_default: qup-i2c0-default-state { 2772 pins = "gpio0", "gpio1"; 2773 function = "qup0"; 2774 }; 2775 2776 qup_i2c1_default: qup-i2c1-default-state { 2777 pins = "gpio17", "gpio18"; 2778 function = "qup1"; 2779 }; 2780 2781 qup_i2c2_default: qup-i2c2-default-state { 2782 pins = "gpio27", "gpio28"; 2783 function = "qup2"; 2784 }; 2785 2786 qup_i2c3_default: qup-i2c3-default-state { 2787 pins = "gpio41", "gpio42"; 2788 function = "qup3"; 2789 }; 2790 2791 qup_i2c4_default: qup-i2c4-default-state { 2792 pins = "gpio89", "gpio90"; 2793 function = "qup4"; 2794 }; 2795 2796 qup_i2c5_default: qup-i2c5-default-state { 2797 pins = "gpio85", "gpio86"; 2798 function = "qup5"; 2799 }; 2800 2801 qup_i2c6_default: qup-i2c6-default-state { 2802 pins = "gpio45", "gpio46"; 2803 function = "qup6"; 2804 }; 2805 2806 qup_i2c7_default: qup-i2c7-default-state { 2807 pins = "gpio93", "gpio94"; 2808 function = "qup7"; 2809 }; 2810 2811 qup_i2c8_default: qup-i2c8-default-state { 2812 pins = "gpio65", "gpio66"; 2813 function = "qup8"; 2814 }; 2815 2816 qup_i2c9_default: qup-i2c9-default-state { 2817 pins = "gpio6", "gpio7"; 2818 function = "qup9"; 2819 }; 2820 2821 qup_i2c10_default: qup-i2c10-default-state { 2822 pins = "gpio55", "gpio56"; 2823 function = "qup10"; 2824 }; 2825 2826 qup_i2c11_default: qup-i2c11-default-state { 2827 pins = "gpio31", "gpio32"; 2828 function = "qup11"; 2829 }; 2830 2831 qup_i2c12_default: qup-i2c12-default-state { 2832 pins = "gpio49", "gpio50"; 2833 function = "qup12"; 2834 }; 2835 2836 qup_i2c13_default: qup-i2c13-default-state { 2837 pins = "gpio105", "gpio106"; 2838 function = "qup13"; 2839 }; 2840 2841 qup_i2c14_default: qup-i2c14-default-state { 2842 pins = "gpio33", "gpio34"; 2843 function = "qup14"; 2844 }; 2845 2846 qup_i2c15_default: qup-i2c15-default-state { 2847 pins = "gpio81", "gpio82"; 2848 function = "qup15"; 2849 }; 2850 2851 qup_spi0_default: qup-spi0-default-state { 2852 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 2853 function = "qup0"; 2854 }; 2855 2856 qup_spi1_default: qup-spi1-default-state { 2857 pins = "gpio17", "gpio18", "gpio19", "gpio20"; 2858 function = "qup1"; 2859 }; 2860 2861 qup_spi2_default: qup-spi2-default-state { 2862 pins = "gpio27", "gpio28", "gpio29", "gpio30"; 2863 function = "qup2"; 2864 }; 2865 2866 qup_spi3_default: qup-spi3-default-state { 2867 pins = "gpio41", "gpio42", "gpio43", "gpio44"; 2868 function = "qup3"; 2869 }; 2870 2871 qup_spi4_default: qup-spi4-default-state { 2872 pins = "gpio89", "gpio90", "gpio91", "gpio92"; 2873 function = "qup4"; 2874 }; 2875 2876 qup_spi5_default: qup-spi5-default-state { 2877 pins = "gpio85", "gpio86", "gpio87", "gpio88"; 2878 function = "qup5"; 2879 }; 2880 2881 qup_spi6_default: qup-spi6-default-state { 2882 pins = "gpio45", "gpio46", "gpio47", "gpio48"; 2883 function = "qup6"; 2884 }; 2885 2886 qup_spi7_default: qup-spi7-default-state { 2887 pins = "gpio93", "gpio94", "gpio95", "gpio96"; 2888 function = "qup7"; 2889 }; 2890 2891 qup_spi8_default: qup-spi8-default-state { 2892 pins = "gpio65", "gpio66", "gpio67", "gpio68"; 2893 function = "qup8"; 2894 }; 2895 2896 qup_spi9_default: qup-spi9-default-state { 2897 pins = "gpio6", "gpio7", "gpio4", "gpio5"; 2898 function = "qup9"; 2899 }; 2900 2901 qup_spi10_default: qup-spi10-default-state { 2902 pins = "gpio55", "gpio56", "gpio53", "gpio54"; 2903 function = "qup10"; 2904 }; 2905 2906 qup_spi11_default: qup-spi11-default-state { 2907 pins = "gpio31", "gpio32", "gpio33", "gpio34"; 2908 function = "qup11"; 2909 }; 2910 2911 qup_spi12_default: qup-spi12-default-state { 2912 pins = "gpio49", "gpio50", "gpio51", "gpio52"; 2913 function = "qup12"; 2914 }; 2915 2916 qup_spi13_default: qup-spi13-default-state { 2917 pins = "gpio105", "gpio106", "gpio107", "gpio108"; 2918 function = "qup13"; 2919 }; 2920 2921 qup_spi14_default: qup-spi14-default-state { 2922 pins = "gpio33", "gpio34", "gpio31", "gpio32"; 2923 function = "qup14"; 2924 }; 2925 2926 qup_spi15_default: qup-spi15-default-state { 2927 pins = "gpio81", "gpio82", "gpio83", "gpio84"; 2928 function = "qup15"; 2929 }; 2930 2931 qup_uart0_default: qup-uart0-default-state { 2932 qup_uart0_tx: tx-pins { 2933 pins = "gpio2"; 2934 function = "qup0"; 2935 }; 2936 2937 qup_uart0_rx: rx-pins { 2938 pins = "gpio3"; 2939 function = "qup0"; 2940 }; 2941 }; 2942 2943 qup_uart1_default: qup-uart1-default-state { 2944 qup_uart1_tx: tx-pins { 2945 pins = "gpio19"; 2946 function = "qup1"; 2947 }; 2948 2949 qup_uart1_rx: rx-pins { 2950 pins = "gpio20"; 2951 function = "qup1"; 2952 }; 2953 }; 2954 2955 qup_uart2_default: qup-uart2-default-state { 2956 qup_uart2_tx: tx-pins { 2957 pins = "gpio29"; 2958 function = "qup2"; 2959 }; 2960 2961 qup_uart2_rx: rx-pins { 2962 pins = "gpio30"; 2963 function = "qup2"; 2964 }; 2965 }; 2966 2967 qup_uart3_default: qup-uart3-default-state { 2968 qup_uart3_tx: tx-pins { 2969 pins = "gpio43"; 2970 function = "qup3"; 2971 }; 2972 2973 qup_uart3_rx: rx-pins { 2974 pins = "gpio44"; 2975 function = "qup3"; 2976 }; 2977 }; 2978 2979 qup_uart3_4pin: qup-uart3-4pin-state { 2980 qup_uart3_4pin_cts: cts-pins { 2981 pins = "gpio41"; 2982 function = "qup3"; 2983 }; 2984 2985 qup_uart3_4pin_rts_tx: rts-tx-pins { 2986 pins = "gpio42", "gpio43"; 2987 function = "qup3"; 2988 }; 2989 2990 qup_uart3_4pin_rx: rx-pins { 2991 pins = "gpio44"; 2992 function = "qup3"; 2993 }; 2994 }; 2995 2996 qup_uart4_default: qup-uart4-default-state { 2997 qup_uart4_tx: tx-pins { 2998 pins = "gpio91"; 2999 function = "qup4"; 3000 }; 3001 3002 qup_uart4_rx: rx-pins { 3003 pins = "gpio92"; 3004 function = "qup4"; 3005 }; 3006 }; 3007 3008 qup_uart5_default: qup-uart5-default-state { 3009 qup_uart5_tx: tx-pins { 3010 pins = "gpio87"; 3011 function = "qup5"; 3012 }; 3013 3014 qup_uart5_rx: rx-pins { 3015 pins = "gpio88"; 3016 function = "qup5"; 3017 }; 3018 }; 3019 3020 qup_uart6_default: qup-uart6-default-state { 3021 qup_uart6_tx: tx-pins { 3022 pins = "gpio47"; 3023 function = "qup6"; 3024 }; 3025 3026 qup_uart6_rx: rx-pins { 3027 pins = "gpio48"; 3028 function = "qup6"; 3029 }; 3030 }; 3031 3032 qup_uart6_4pin: qup-uart6-4pin-state { 3033 qup_uart6_4pin_cts: cts-pins { 3034 pins = "gpio45"; 3035 function = "qup6"; 3036 bias-pull-down; 3037 }; 3038 3039 qup_uart6_4pin_rts_tx: rts-tx-pins { 3040 pins = "gpio46", "gpio47"; 3041 function = "qup6"; 3042 drive-strength = <2>; 3043 bias-disable; 3044 }; 3045 3046 qup_uart6_4pin_rx: rx-pins { 3047 pins = "gpio48"; 3048 function = "qup6"; 3049 bias-pull-up; 3050 }; 3051 }; 3052 3053 qup_uart7_default: qup-uart7-default-state { 3054 qup_uart7_tx: tx-pins { 3055 pins = "gpio95"; 3056 function = "qup7"; 3057 }; 3058 3059 qup_uart7_rx: rx-pins { 3060 pins = "gpio96"; 3061 function = "qup7"; 3062 }; 3063 }; 3064 3065 qup_uart8_default: qup-uart8-default-state { 3066 qup_uart8_tx: tx-pins { 3067 pins = "gpio67"; 3068 function = "qup8"; 3069 }; 3070 3071 qup_uart8_rx: rx-pins { 3072 pins = "gpio68"; 3073 function = "qup8"; 3074 }; 3075 }; 3076 3077 qup_uart9_default: qup-uart9-default-state { 3078 qup_uart9_tx: tx-pins { 3079 pins = "gpio4"; 3080 function = "qup9"; 3081 }; 3082 3083 qup_uart9_rx: rx-pins { 3084 pins = "gpio5"; 3085 function = "qup9"; 3086 }; 3087 }; 3088 3089 qup_uart10_default: qup-uart10-default-state { 3090 qup_uart10_tx: tx-pins { 3091 pins = "gpio53"; 3092 function = "qup10"; 3093 }; 3094 3095 qup_uart10_rx: rx-pins { 3096 pins = "gpio54"; 3097 function = "qup10"; 3098 }; 3099 }; 3100 3101 qup_uart11_default: qup-uart11-default-state { 3102 qup_uart11_tx: tx-pins { 3103 pins = "gpio33"; 3104 function = "qup11"; 3105 }; 3106 3107 qup_uart11_rx: rx-pins { 3108 pins = "gpio34"; 3109 function = "qup11"; 3110 }; 3111 }; 3112 3113 qup_uart12_default: qup-uart12-default-state { 3114 qup_uart12_tx: tx-pins { 3115 pins = "gpio51"; 3116 function = "qup0"; 3117 }; 3118 3119 qup_uart12_rx: rx-pins { 3120 pins = "gpio52"; 3121 function = "qup0"; 3122 }; 3123 }; 3124 3125 qup_uart13_default: qup-uart13-default-state { 3126 qup_uart13_tx: tx-pins { 3127 pins = "gpio107"; 3128 function = "qup13"; 3129 }; 3130 3131 qup_uart13_rx: rx-pins { 3132 pins = "gpio108"; 3133 function = "qup13"; 3134 }; 3135 }; 3136 3137 qup_uart14_default: qup-uart14-default-state { 3138 qup_uart14_tx: tx-pins { 3139 pins = "gpio31"; 3140 function = "qup14"; 3141 }; 3142 3143 qup_uart14_rx: rx-pins { 3144 pins = "gpio32"; 3145 function = "qup14"; 3146 }; 3147 }; 3148 3149 qup_uart15_default: qup-uart15-default-state { 3150 qup_uart15_tx: tx-pins { 3151 pins = "gpio83"; 3152 function = "qup15"; 3153 }; 3154 3155 qup_uart15_rx: rx-pins { 3156 pins = "gpio84"; 3157 function = "qup15"; 3158 }; 3159 }; 3160 3161 quat_mi2s_sleep: quat-mi2s-sleep-state { 3162 pins = "gpio58", "gpio59"; 3163 function = "gpio"; 3164 drive-strength = <2>; 3165 bias-pull-down; 3166 input-enable; 3167 }; 3168 3169 quat_mi2s_active: quat-mi2s-active-state { 3170 pins = "gpio58", "gpio59"; 3171 function = "qua_mi2s"; 3172 drive-strength = <8>; 3173 bias-disable; 3174 output-high; 3175 }; 3176 3177 quat_mi2s_sd0_sleep: quat-mi2s-sd0-sleep-state { 3178 pins = "gpio60"; 3179 function = "gpio"; 3180 drive-strength = <2>; 3181 bias-pull-down; 3182 input-enable; 3183 }; 3184 3185 quat_mi2s_sd0_active: quat-mi2s-sd0-active-state { 3186 pins = "gpio60"; 3187 function = "qua_mi2s"; 3188 drive-strength = <8>; 3189 bias-disable; 3190 }; 3191 3192 quat_mi2s_sd1_sleep: quat-mi2s-sd1-sleep-state { 3193 pins = "gpio61"; 3194 function = "gpio"; 3195 drive-strength = <2>; 3196 bias-pull-down; 3197 input-enable; 3198 }; 3199 3200 quat_mi2s_sd1_active: quat-mi2s-sd1-active-state { 3201 pins = "gpio61"; 3202 function = "qua_mi2s"; 3203 drive-strength = <8>; 3204 bias-disable; 3205 }; 3206 3207 quat_mi2s_sd2_sleep: quat-mi2s-sd2-sleep-state { 3208 pins = "gpio62"; 3209 function = "gpio"; 3210 drive-strength = <2>; 3211 bias-pull-down; 3212 input-enable; 3213 }; 3214 3215 quat_mi2s_sd2_active: quat-mi2s-sd2-active-state { 3216 pins = "gpio62"; 3217 function = "qua_mi2s"; 3218 drive-strength = <8>; 3219 bias-disable; 3220 }; 3221 3222 quat_mi2s_sd3_sleep: quat-mi2s-sd3-sleep-state { 3223 pins = "gpio63"; 3224 function = "gpio"; 3225 drive-strength = <2>; 3226 bias-pull-down; 3227 input-enable; 3228 }; 3229 3230 quat_mi2s_sd3_active: quat-mi2s-sd3-active-state { 3231 pins = "gpio63"; 3232 function = "qua_mi2s"; 3233 drive-strength = <8>; 3234 bias-disable; 3235 }; 3236 }; 3237 3238 mss_pil: remoteproc@4080000 { 3239 compatible = "qcom,sdm845-mss-pil"; 3240 reg = <0 0x04080000 0 0x408>, <0 0x04180000 0 0x48>; 3241 reg-names = "qdsp6", "rmb"; 3242 3243 interrupts-extended = 3244 <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, 3245 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3246 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3247 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3248 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 3249 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 3250 interrupt-names = "wdog", "fatal", "ready", 3251 "handover", "stop-ack", 3252 "shutdown-ack"; 3253 3254 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 3255 <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>, 3256 <&gcc GCC_BOOT_ROM_AHB_CLK>, 3257 <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>, 3258 <&gcc GCC_MSS_SNOC_AXI_CLK>, 3259 <&gcc GCC_MSS_MFAB_AXIS_CLK>, 3260 <&gcc GCC_PRNG_AHB_CLK>, 3261 <&rpmhcc RPMH_CXO_CLK>; 3262 clock-names = "iface", "bus", "mem", "gpll0_mss", 3263 "snoc_axi", "mnoc_axi", "prng", "xo"; 3264 3265 qcom,qmp = <&aoss_qmp>; 3266 3267 qcom,smem-states = <&modem_smp2p_out 0>; 3268 qcom,smem-state-names = "stop"; 3269 3270 resets = <&aoss_reset AOSS_CC_MSS_RESTART>, 3271 <&pdc_reset PDC_MODEM_SYNC_RESET>; 3272 reset-names = "mss_restart", "pdc_reset"; 3273 3274 qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>; 3275 3276 power-domains = <&rpmhpd SDM845_CX>, 3277 <&rpmhpd SDM845_MX>, 3278 <&rpmhpd SDM845_MSS>; 3279 power-domain-names = "cx", "mx", "mss"; 3280 3281 status = "disabled"; 3282 3283 mba { 3284 memory-region = <&mba_region>; 3285 }; 3286 3287 mpss { 3288 memory-region = <&mpss_region>; 3289 }; 3290 3291 metadata { 3292 memory-region = <&mdata_mem>; 3293 }; 3294 3295 glink-edge { 3296 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 3297 label = "modem"; 3298 qcom,remote-pid = <1>; 3299 mboxes = <&apss_shared 12>; 3300 }; 3301 }; 3302 3303 gpucc: clock-controller@5090000 { 3304 compatible = "qcom,sdm845-gpucc"; 3305 reg = <0 0x05090000 0 0x9000>; 3306 #clock-cells = <1>; 3307 #reset-cells = <1>; 3308 #power-domain-cells = <1>; 3309 clocks = <&rpmhcc RPMH_CXO_CLK>, 3310 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 3311 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 3312 clock-names = "bi_tcxo", 3313 "gcc_gpu_gpll0_clk_src", 3314 "gcc_gpu_gpll0_div_clk_src"; 3315 }; 3316 3317 stm@6002000 { 3318 compatible = "arm,coresight-stm", "arm,primecell"; 3319 reg = <0 0x06002000 0 0x1000>, 3320 <0 0x16280000 0 0x180000>; 3321 reg-names = "stm-base", "stm-stimulus-base"; 3322 3323 clocks = <&aoss_qmp>; 3324 clock-names = "apb_pclk"; 3325 3326 out-ports { 3327 port { 3328 stm_out: endpoint { 3329 remote-endpoint = 3330 <&funnel0_in7>; 3331 }; 3332 }; 3333 }; 3334 }; 3335 3336 funnel@6041000 { 3337 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3338 reg = <0 0x06041000 0 0x1000>; 3339 3340 clocks = <&aoss_qmp>; 3341 clock-names = "apb_pclk"; 3342 3343 out-ports { 3344 port { 3345 funnel0_out: endpoint { 3346 remote-endpoint = 3347 <&merge_funnel_in0>; 3348 }; 3349 }; 3350 }; 3351 3352 in-ports { 3353 #address-cells = <1>; 3354 #size-cells = <0>; 3355 3356 port@7 { 3357 reg = <7>; 3358 funnel0_in7: endpoint { 3359 remote-endpoint = <&stm_out>; 3360 }; 3361 }; 3362 }; 3363 }; 3364 3365 funnel@6043000 { 3366 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3367 reg = <0 0x06043000 0 0x1000>; 3368 3369 clocks = <&aoss_qmp>; 3370 clock-names = "apb_pclk"; 3371 3372 out-ports { 3373 port { 3374 funnel2_out: endpoint { 3375 remote-endpoint = 3376 <&merge_funnel_in2>; 3377 }; 3378 }; 3379 }; 3380 3381 in-ports { 3382 #address-cells = <1>; 3383 #size-cells = <0>; 3384 3385 port@5 { 3386 reg = <5>; 3387 funnel2_in5: endpoint { 3388 remote-endpoint = 3389 <&apss_merge_funnel_out>; 3390 }; 3391 }; 3392 }; 3393 }; 3394 3395 funnel@6045000 { 3396 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3397 reg = <0 0x06045000 0 0x1000>; 3398 3399 clocks = <&aoss_qmp>; 3400 clock-names = "apb_pclk"; 3401 3402 out-ports { 3403 port { 3404 merge_funnel_out: endpoint { 3405 remote-endpoint = <&etf_in>; 3406 }; 3407 }; 3408 }; 3409 3410 in-ports { 3411 #address-cells = <1>; 3412 #size-cells = <0>; 3413 3414 port@0 { 3415 reg = <0>; 3416 merge_funnel_in0: endpoint { 3417 remote-endpoint = 3418 <&funnel0_out>; 3419 }; 3420 }; 3421 3422 port@2 { 3423 reg = <2>; 3424 merge_funnel_in2: endpoint { 3425 remote-endpoint = 3426 <&funnel2_out>; 3427 }; 3428 }; 3429 }; 3430 }; 3431 3432 replicator@6046000 { 3433 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 3434 reg = <0 0x06046000 0 0x1000>; 3435 3436 clocks = <&aoss_qmp>; 3437 clock-names = "apb_pclk"; 3438 3439 out-ports { 3440 port { 3441 replicator_out: endpoint { 3442 remote-endpoint = <&etr_in>; 3443 }; 3444 }; 3445 }; 3446 3447 in-ports { 3448 port { 3449 replicator_in: endpoint { 3450 remote-endpoint = <&etf_out>; 3451 }; 3452 }; 3453 }; 3454 }; 3455 3456 etf@6047000 { 3457 compatible = "arm,coresight-tmc", "arm,primecell"; 3458 reg = <0 0x06047000 0 0x1000>; 3459 3460 clocks = <&aoss_qmp>; 3461 clock-names = "apb_pclk"; 3462 3463 out-ports { 3464 port { 3465 etf_out: endpoint { 3466 remote-endpoint = 3467 <&replicator_in>; 3468 }; 3469 }; 3470 }; 3471 3472 in-ports { 3473 #address-cells = <1>; 3474 #size-cells = <0>; 3475 3476 port@1 { 3477 reg = <1>; 3478 etf_in: endpoint { 3479 remote-endpoint = 3480 <&merge_funnel_out>; 3481 }; 3482 }; 3483 }; 3484 }; 3485 3486 etr@6048000 { 3487 compatible = "arm,coresight-tmc", "arm,primecell"; 3488 reg = <0 0x06048000 0 0x1000>; 3489 3490 clocks = <&aoss_qmp>; 3491 clock-names = "apb_pclk"; 3492 arm,scatter-gather; 3493 3494 in-ports { 3495 port { 3496 etr_in: endpoint { 3497 remote-endpoint = 3498 <&replicator_out>; 3499 }; 3500 }; 3501 }; 3502 }; 3503 3504 etm@7040000 { 3505 compatible = "arm,coresight-etm4x", "arm,primecell"; 3506 reg = <0 0x07040000 0 0x1000>; 3507 3508 cpu = <&CPU0>; 3509 3510 clocks = <&aoss_qmp>; 3511 clock-names = "apb_pclk"; 3512 arm,coresight-loses-context-with-cpu; 3513 3514 out-ports { 3515 port { 3516 etm0_out: endpoint { 3517 remote-endpoint = 3518 <&apss_funnel_in0>; 3519 }; 3520 }; 3521 }; 3522 }; 3523 3524 etm@7140000 { 3525 compatible = "arm,coresight-etm4x", "arm,primecell"; 3526 reg = <0 0x07140000 0 0x1000>; 3527 3528 cpu = <&CPU1>; 3529 3530 clocks = <&aoss_qmp>; 3531 clock-names = "apb_pclk"; 3532 arm,coresight-loses-context-with-cpu; 3533 3534 out-ports { 3535 port { 3536 etm1_out: endpoint { 3537 remote-endpoint = 3538 <&apss_funnel_in1>; 3539 }; 3540 }; 3541 }; 3542 }; 3543 3544 etm@7240000 { 3545 compatible = "arm,coresight-etm4x", "arm,primecell"; 3546 reg = <0 0x07240000 0 0x1000>; 3547 3548 cpu = <&CPU2>; 3549 3550 clocks = <&aoss_qmp>; 3551 clock-names = "apb_pclk"; 3552 arm,coresight-loses-context-with-cpu; 3553 3554 out-ports { 3555 port { 3556 etm2_out: endpoint { 3557 remote-endpoint = 3558 <&apss_funnel_in2>; 3559 }; 3560 }; 3561 }; 3562 }; 3563 3564 etm@7340000 { 3565 compatible = "arm,coresight-etm4x", "arm,primecell"; 3566 reg = <0 0x07340000 0 0x1000>; 3567 3568 cpu = <&CPU3>; 3569 3570 clocks = <&aoss_qmp>; 3571 clock-names = "apb_pclk"; 3572 arm,coresight-loses-context-with-cpu; 3573 3574 out-ports { 3575 port { 3576 etm3_out: endpoint { 3577 remote-endpoint = 3578 <&apss_funnel_in3>; 3579 }; 3580 }; 3581 }; 3582 }; 3583 3584 etm@7440000 { 3585 compatible = "arm,coresight-etm4x", "arm,primecell"; 3586 reg = <0 0x07440000 0 0x1000>; 3587 3588 cpu = <&CPU4>; 3589 3590 clocks = <&aoss_qmp>; 3591 clock-names = "apb_pclk"; 3592 arm,coresight-loses-context-with-cpu; 3593 3594 out-ports { 3595 port { 3596 etm4_out: endpoint { 3597 remote-endpoint = 3598 <&apss_funnel_in4>; 3599 }; 3600 }; 3601 }; 3602 }; 3603 3604 etm@7540000 { 3605 compatible = "arm,coresight-etm4x", "arm,primecell"; 3606 reg = <0 0x07540000 0 0x1000>; 3607 3608 cpu = <&CPU5>; 3609 3610 clocks = <&aoss_qmp>; 3611 clock-names = "apb_pclk"; 3612 arm,coresight-loses-context-with-cpu; 3613 3614 out-ports { 3615 port { 3616 etm5_out: endpoint { 3617 remote-endpoint = 3618 <&apss_funnel_in5>; 3619 }; 3620 }; 3621 }; 3622 }; 3623 3624 etm@7640000 { 3625 compatible = "arm,coresight-etm4x", "arm,primecell"; 3626 reg = <0 0x07640000 0 0x1000>; 3627 3628 cpu = <&CPU6>; 3629 3630 clocks = <&aoss_qmp>; 3631 clock-names = "apb_pclk"; 3632 arm,coresight-loses-context-with-cpu; 3633 3634 out-ports { 3635 port { 3636 etm6_out: endpoint { 3637 remote-endpoint = 3638 <&apss_funnel_in6>; 3639 }; 3640 }; 3641 }; 3642 }; 3643 3644 etm@7740000 { 3645 compatible = "arm,coresight-etm4x", "arm,primecell"; 3646 reg = <0 0x07740000 0 0x1000>; 3647 3648 cpu = <&CPU7>; 3649 3650 clocks = <&aoss_qmp>; 3651 clock-names = "apb_pclk"; 3652 arm,coresight-loses-context-with-cpu; 3653 3654 out-ports { 3655 port { 3656 etm7_out: endpoint { 3657 remote-endpoint = 3658 <&apss_funnel_in7>; 3659 }; 3660 }; 3661 }; 3662 }; 3663 3664 funnel@7800000 { /* APSS Funnel */ 3665 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3666 reg = <0 0x07800000 0 0x1000>; 3667 3668 clocks = <&aoss_qmp>; 3669 clock-names = "apb_pclk"; 3670 3671 out-ports { 3672 port { 3673 apss_funnel_out: endpoint { 3674 remote-endpoint = 3675 <&apss_merge_funnel_in>; 3676 }; 3677 }; 3678 }; 3679 3680 in-ports { 3681 #address-cells = <1>; 3682 #size-cells = <0>; 3683 3684 port@0 { 3685 reg = <0>; 3686 apss_funnel_in0: endpoint { 3687 remote-endpoint = 3688 <&etm0_out>; 3689 }; 3690 }; 3691 3692 port@1 { 3693 reg = <1>; 3694 apss_funnel_in1: endpoint { 3695 remote-endpoint = 3696 <&etm1_out>; 3697 }; 3698 }; 3699 3700 port@2 { 3701 reg = <2>; 3702 apss_funnel_in2: endpoint { 3703 remote-endpoint = 3704 <&etm2_out>; 3705 }; 3706 }; 3707 3708 port@3 { 3709 reg = <3>; 3710 apss_funnel_in3: endpoint { 3711 remote-endpoint = 3712 <&etm3_out>; 3713 }; 3714 }; 3715 3716 port@4 { 3717 reg = <4>; 3718 apss_funnel_in4: endpoint { 3719 remote-endpoint = 3720 <&etm4_out>; 3721 }; 3722 }; 3723 3724 port@5 { 3725 reg = <5>; 3726 apss_funnel_in5: endpoint { 3727 remote-endpoint = 3728 <&etm5_out>; 3729 }; 3730 }; 3731 3732 port@6 { 3733 reg = <6>; 3734 apss_funnel_in6: endpoint { 3735 remote-endpoint = 3736 <&etm6_out>; 3737 }; 3738 }; 3739 3740 port@7 { 3741 reg = <7>; 3742 apss_funnel_in7: endpoint { 3743 remote-endpoint = 3744 <&etm7_out>; 3745 }; 3746 }; 3747 }; 3748 }; 3749 3750 funnel@7810000 { 3751 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3752 reg = <0 0x07810000 0 0x1000>; 3753 3754 clocks = <&aoss_qmp>; 3755 clock-names = "apb_pclk"; 3756 3757 out-ports { 3758 port { 3759 apss_merge_funnel_out: endpoint { 3760 remote-endpoint = 3761 <&funnel2_in5>; 3762 }; 3763 }; 3764 }; 3765 3766 in-ports { 3767 port { 3768 apss_merge_funnel_in: endpoint { 3769 remote-endpoint = 3770 <&apss_funnel_out>; 3771 }; 3772 }; 3773 }; 3774 }; 3775 3776 sdhc_2: mmc@8804000 { 3777 compatible = "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5"; 3778 reg = <0 0x08804000 0 0x1000>; 3779 3780 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 3781 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 3782 interrupt-names = "hc_irq", "pwr_irq"; 3783 3784 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3785 <&gcc GCC_SDCC2_APPS_CLK>, 3786 <&rpmhcc RPMH_CXO_CLK>; 3787 clock-names = "iface", "core", "xo"; 3788 iommus = <&apps_smmu 0xa0 0xf>; 3789 power-domains = <&rpmhpd SDM845_CX>; 3790 operating-points-v2 = <&sdhc2_opp_table>; 3791 3792 status = "disabled"; 3793 3794 sdhc2_opp_table: opp-table { 3795 compatible = "operating-points-v2"; 3796 3797 opp-9600000 { 3798 opp-hz = /bits/ 64 <9600000>; 3799 required-opps = <&rpmhpd_opp_min_svs>; 3800 }; 3801 3802 opp-19200000 { 3803 opp-hz = /bits/ 64 <19200000>; 3804 required-opps = <&rpmhpd_opp_low_svs>; 3805 }; 3806 3807 opp-100000000 { 3808 opp-hz = /bits/ 64 <100000000>; 3809 required-opps = <&rpmhpd_opp_svs>; 3810 }; 3811 3812 opp-201500000 { 3813 opp-hz = /bits/ 64 <201500000>; 3814 required-opps = <&rpmhpd_opp_svs_l1>; 3815 }; 3816 }; 3817 }; 3818 3819 qspi: spi@88df000 { 3820 compatible = "qcom,sdm845-qspi", "qcom,qspi-v1"; 3821 reg = <0 0x088df000 0 0x600>; 3822 #address-cells = <1>; 3823 #size-cells = <0>; 3824 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 3825 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 3826 <&gcc GCC_QSPI_CORE_CLK>; 3827 clock-names = "iface", "core"; 3828 power-domains = <&rpmhpd SDM845_CX>; 3829 operating-points-v2 = <&qspi_opp_table>; 3830 status = "disabled"; 3831 }; 3832 3833 slim: slim-ngd@171c0000 { 3834 compatible = "qcom,slim-ngd-v2.1.0"; 3835 reg = <0 0x171c0000 0 0x2c000>; 3836 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 3837 3838 dmas = <&slimbam 3>, <&slimbam 4>; 3839 dma-names = "rx", "tx"; 3840 3841 iommus = <&apps_smmu 0x1806 0x0>; 3842 #address-cells = <1>; 3843 #size-cells = <0>; 3844 status = "disabled"; 3845 }; 3846 3847 lmh_cluster1: lmh@17d70800 { 3848 compatible = "qcom,sdm845-lmh"; 3849 reg = <0 0x17d70800 0 0x400>; 3850 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 3851 cpus = <&CPU4>; 3852 qcom,lmh-temp-arm-millicelsius = <65000>; 3853 qcom,lmh-temp-low-millicelsius = <94500>; 3854 qcom,lmh-temp-high-millicelsius = <95000>; 3855 interrupt-controller; 3856 #interrupt-cells = <1>; 3857 }; 3858 3859 lmh_cluster0: lmh@17d78800 { 3860 compatible = "qcom,sdm845-lmh"; 3861 reg = <0 0x17d78800 0 0x400>; 3862 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 3863 cpus = <&CPU0>; 3864 qcom,lmh-temp-arm-millicelsius = <65000>; 3865 qcom,lmh-temp-low-millicelsius = <94500>; 3866 qcom,lmh-temp-high-millicelsius = <95000>; 3867 interrupt-controller; 3868 #interrupt-cells = <1>; 3869 }; 3870 3871 usb_1_hsphy: phy@88e2000 { 3872 compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy"; 3873 reg = <0 0x088e2000 0 0x400>; 3874 status = "disabled"; 3875 #phy-cells = <0>; 3876 3877 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 3878 <&rpmhcc RPMH_CXO_CLK>; 3879 clock-names = "cfg_ahb", "ref"; 3880 3881 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3882 3883 nvmem-cells = <&qusb2p_hstx_trim>; 3884 }; 3885 3886 usb_2_hsphy: phy@88e3000 { 3887 compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy"; 3888 reg = <0 0x088e3000 0 0x400>; 3889 status = "disabled"; 3890 #phy-cells = <0>; 3891 3892 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 3893 <&rpmhcc RPMH_CXO_CLK>; 3894 clock-names = "cfg_ahb", "ref"; 3895 3896 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3897 3898 nvmem-cells = <&qusb2s_hstx_trim>; 3899 }; 3900 3901 usb_1_qmpphy: phy@88e9000 { 3902 compatible = "qcom,sdm845-qmp-usb3-dp-phy"; 3903 reg = <0 0x088e9000 0 0x18c>, 3904 <0 0x088e8000 0 0x38>, 3905 <0 0x088ea000 0 0x40>; 3906 status = "disabled"; 3907 #address-cells = <2>; 3908 #size-cells = <2>; 3909 ranges; 3910 3911 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3912 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 3913 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 3914 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 3915 clock-names = "aux", "cfg_ahb", "ref", "com_aux"; 3916 3917 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 3918 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; 3919 reset-names = "phy", "common"; 3920 3921 usb_1_ssphy: usb3-phy@88e9200 { 3922 reg = <0 0x088e9200 0 0x128>, 3923 <0 0x088e9400 0 0x200>, 3924 <0 0x088e9c00 0 0x218>, 3925 <0 0x088e9600 0 0x128>, 3926 <0 0x088e9800 0 0x200>, 3927 <0 0x088e9a00 0 0x100>; 3928 #clock-cells = <0>; 3929 #phy-cells = <0>; 3930 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3931 clock-names = "pipe0"; 3932 clock-output-names = "usb3_phy_pipe_clk_src"; 3933 }; 3934 3935 dp_phy: dp-phy@88ea200 { 3936 reg = <0 0x088ea200 0 0x200>, 3937 <0 0x088ea400 0 0x200>, 3938 <0 0x088eaa00 0 0x200>, 3939 <0 0x088ea600 0 0x200>, 3940 <0 0x088ea800 0 0x200>; 3941 #clock-cells = <1>; 3942 #phy-cells = <0>; 3943 }; 3944 }; 3945 3946 usb_2_qmpphy: phy@88eb000 { 3947 compatible = "qcom,sdm845-qmp-usb3-uni-phy"; 3948 reg = <0 0x088eb000 0 0x18c>; 3949 status = "disabled"; 3950 #address-cells = <2>; 3951 #size-cells = <2>; 3952 ranges; 3953 3954 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 3955 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 3956 <&gcc GCC_USB3_SEC_CLKREF_CLK>, 3957 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; 3958 clock-names = "aux", "cfg_ahb", "ref", "com_aux"; 3959 3960 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, 3961 <&gcc GCC_USB3_PHY_SEC_BCR>; 3962 reset-names = "phy", "common"; 3963 3964 usb_2_ssphy: phy@88eb200 { 3965 reg = <0 0x088eb200 0 0x128>, 3966 <0 0x088eb400 0 0x1fc>, 3967 <0 0x088eb800 0 0x218>, 3968 <0 0x088eb600 0 0x70>; 3969 #clock-cells = <0>; 3970 #phy-cells = <0>; 3971 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 3972 clock-names = "pipe0"; 3973 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 3974 }; 3975 }; 3976 3977 usb_1: usb@a6f8800 { 3978 compatible = "qcom,sdm845-dwc3", "qcom,dwc3"; 3979 reg = <0 0x0a6f8800 0 0x400>; 3980 status = "disabled"; 3981 #address-cells = <2>; 3982 #size-cells = <2>; 3983 ranges; 3984 dma-ranges; 3985 3986 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3987 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3988 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3989 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 3990 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 3991 clock-names = "cfg_noc", 3992 "core", 3993 "iface", 3994 "sleep", 3995 "mock_utmi"; 3996 3997 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3998 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3999 assigned-clock-rates = <19200000>, <150000000>; 4000 4001 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 4002 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>, 4003 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>, 4004 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>; 4005 interrupt-names = "hs_phy_irq", "ss_phy_irq", 4006 "dm_hs_phy_irq", "dp_hs_phy_irq"; 4007 4008 power-domains = <&gcc USB30_PRIM_GDSC>; 4009 4010 resets = <&gcc GCC_USB30_PRIM_BCR>; 4011 4012 interconnects = <&aggre2_noc MASTER_USB3_0 0 &mem_noc SLAVE_EBI1 0>, 4013 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; 4014 interconnect-names = "usb-ddr", "apps-usb"; 4015 4016 usb_1_dwc3: usb@a600000 { 4017 compatible = "snps,dwc3"; 4018 reg = <0 0x0a600000 0 0xcd00>; 4019 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 4020 iommus = <&apps_smmu 0x740 0>; 4021 snps,dis_u2_susphy_quirk; 4022 snps,dis_enblslpm_quirk; 4023 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 4024 phy-names = "usb2-phy", "usb3-phy"; 4025 }; 4026 }; 4027 4028 usb_2: usb@a8f8800 { 4029 compatible = "qcom,sdm845-dwc3", "qcom,dwc3"; 4030 reg = <0 0x0a8f8800 0 0x400>; 4031 status = "disabled"; 4032 #address-cells = <2>; 4033 #size-cells = <2>; 4034 ranges; 4035 dma-ranges; 4036 4037 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 4038 <&gcc GCC_USB30_SEC_MASTER_CLK>, 4039 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 4040 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 4041 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>; 4042 clock-names = "cfg_noc", 4043 "core", 4044 "iface", 4045 "sleep", 4046 "mock_utmi"; 4047 4048 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 4049 <&gcc GCC_USB30_SEC_MASTER_CLK>; 4050 assigned-clock-rates = <19200000>, <150000000>; 4051 4052 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 4053 <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>, 4054 <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>, 4055 <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>; 4056 interrupt-names = "hs_phy_irq", "ss_phy_irq", 4057 "dm_hs_phy_irq", "dp_hs_phy_irq"; 4058 4059 power-domains = <&gcc USB30_SEC_GDSC>; 4060 4061 resets = <&gcc GCC_USB30_SEC_BCR>; 4062 4063 interconnects = <&aggre2_noc MASTER_USB3_1 0 &mem_noc SLAVE_EBI1 0>, 4064 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>; 4065 interconnect-names = "usb-ddr", "apps-usb"; 4066 4067 usb_2_dwc3: usb@a800000 { 4068 compatible = "snps,dwc3"; 4069 reg = <0 0x0a800000 0 0xcd00>; 4070 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 4071 iommus = <&apps_smmu 0x760 0>; 4072 snps,dis_u2_susphy_quirk; 4073 snps,dis_enblslpm_quirk; 4074 phys = <&usb_2_hsphy>, <&usb_2_ssphy>; 4075 phy-names = "usb2-phy", "usb3-phy"; 4076 }; 4077 }; 4078 4079 venus: video-codec@aa00000 { 4080 compatible = "qcom,sdm845-venus-v2"; 4081 reg = <0 0x0aa00000 0 0xff000>; 4082 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 4083 power-domains = <&videocc VENUS_GDSC>, 4084 <&videocc VCODEC0_GDSC>, 4085 <&videocc VCODEC1_GDSC>, 4086 <&rpmhpd SDM845_CX>; 4087 power-domain-names = "venus", "vcodec0", "vcodec1", "cx"; 4088 operating-points-v2 = <&venus_opp_table>; 4089 clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>, 4090 <&videocc VIDEO_CC_VENUS_AHB_CLK>, 4091 <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>, 4092 <&videocc VIDEO_CC_VCODEC0_CORE_CLK>, 4093 <&videocc VIDEO_CC_VCODEC0_AXI_CLK>, 4094 <&videocc VIDEO_CC_VCODEC1_CORE_CLK>, 4095 <&videocc VIDEO_CC_VCODEC1_AXI_CLK>; 4096 clock-names = "core", "iface", "bus", 4097 "vcodec0_core", "vcodec0_bus", 4098 "vcodec1_core", "vcodec1_bus"; 4099 iommus = <&apps_smmu 0x10a0 0x8>, 4100 <&apps_smmu 0x10b0 0x0>; 4101 memory-region = <&venus_mem>; 4102 interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mem_noc SLAVE_EBI1 0>, 4103 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>; 4104 interconnect-names = "video-mem", "cpu-cfg"; 4105 4106 status = "disabled"; 4107 4108 video-core0 { 4109 compatible = "venus-decoder"; 4110 }; 4111 4112 video-core1 { 4113 compatible = "venus-encoder"; 4114 }; 4115 4116 venus_opp_table: opp-table { 4117 compatible = "operating-points-v2"; 4118 4119 opp-100000000 { 4120 opp-hz = /bits/ 64 <100000000>; 4121 required-opps = <&rpmhpd_opp_min_svs>; 4122 }; 4123 4124 opp-200000000 { 4125 opp-hz = /bits/ 64 <200000000>; 4126 required-opps = <&rpmhpd_opp_low_svs>; 4127 }; 4128 4129 opp-320000000 { 4130 opp-hz = /bits/ 64 <320000000>; 4131 required-opps = <&rpmhpd_opp_svs>; 4132 }; 4133 4134 opp-380000000 { 4135 opp-hz = /bits/ 64 <380000000>; 4136 required-opps = <&rpmhpd_opp_svs_l1>; 4137 }; 4138 4139 opp-444000000 { 4140 opp-hz = /bits/ 64 <444000000>; 4141 required-opps = <&rpmhpd_opp_nom>; 4142 }; 4143 4144 opp-533000097 { 4145 opp-hz = /bits/ 64 <533000097>; 4146 required-opps = <&rpmhpd_opp_turbo>; 4147 }; 4148 }; 4149 }; 4150 4151 videocc: clock-controller@ab00000 { 4152 compatible = "qcom,sdm845-videocc"; 4153 reg = <0 0x0ab00000 0 0x10000>; 4154 clocks = <&rpmhcc RPMH_CXO_CLK>; 4155 clock-names = "bi_tcxo"; 4156 #clock-cells = <1>; 4157 #power-domain-cells = <1>; 4158 #reset-cells = <1>; 4159 }; 4160 4161 camss: camss@a00000 { 4162 compatible = "qcom,sdm845-camss"; 4163 4164 reg = <0 0x0acb3000 0 0x1000>, 4165 <0 0x0acba000 0 0x1000>, 4166 <0 0x0acc8000 0 0x1000>, 4167 <0 0x0ac65000 0 0x1000>, 4168 <0 0x0ac66000 0 0x1000>, 4169 <0 0x0ac67000 0 0x1000>, 4170 <0 0x0ac68000 0 0x1000>, 4171 <0 0x0acaf000 0 0x4000>, 4172 <0 0x0acb6000 0 0x4000>, 4173 <0 0x0acc4000 0 0x4000>; 4174 reg-names = "csid0", 4175 "csid1", 4176 "csid2", 4177 "csiphy0", 4178 "csiphy1", 4179 "csiphy2", 4180 "csiphy3", 4181 "vfe0", 4182 "vfe1", 4183 "vfe_lite"; 4184 4185 interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>, 4186 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>, 4187 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>, 4188 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>, 4189 <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>, 4190 <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>, 4191 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, 4192 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>, 4193 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>, 4194 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>; 4195 interrupt-names = "csid0", 4196 "csid1", 4197 "csid2", 4198 "csiphy0", 4199 "csiphy1", 4200 "csiphy2", 4201 "csiphy3", 4202 "vfe0", 4203 "vfe1", 4204 "vfe_lite"; 4205 4206 power-domains = <&clock_camcc IFE_0_GDSC>, 4207 <&clock_camcc IFE_1_GDSC>, 4208 <&clock_camcc TITAN_TOP_GDSC>; 4209 4210 clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, 4211 <&clock_camcc CAM_CC_CPAS_AHB_CLK>, 4212 <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, 4213 <&clock_camcc CAM_CC_IFE_0_CSID_CLK>, 4214 <&clock_camcc CAM_CC_IFE_0_CSID_CLK_SRC>, 4215 <&clock_camcc CAM_CC_IFE_1_CSID_CLK>, 4216 <&clock_camcc CAM_CC_IFE_1_CSID_CLK_SRC>, 4217 <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK>, 4218 <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>, 4219 <&clock_camcc CAM_CC_CSIPHY0_CLK>, 4220 <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>, 4221 <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>, 4222 <&clock_camcc CAM_CC_CSIPHY1_CLK>, 4223 <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK>, 4224 <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>, 4225 <&clock_camcc CAM_CC_CSIPHY2_CLK>, 4226 <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK>, 4227 <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>, 4228 <&clock_camcc CAM_CC_CSIPHY3_CLK>, 4229 <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK>, 4230 <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>, 4231 <&gcc GCC_CAMERA_AHB_CLK>, 4232 <&gcc GCC_CAMERA_AXI_CLK>, 4233 <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, 4234 <&clock_camcc CAM_CC_SOC_AHB_CLK>, 4235 <&clock_camcc CAM_CC_IFE_0_AXI_CLK>, 4236 <&clock_camcc CAM_CC_IFE_0_CLK>, 4237 <&clock_camcc CAM_CC_IFE_0_CPHY_RX_CLK>, 4238 <&clock_camcc CAM_CC_IFE_0_CLK_SRC>, 4239 <&clock_camcc CAM_CC_IFE_1_AXI_CLK>, 4240 <&clock_camcc CAM_CC_IFE_1_CLK>, 4241 <&clock_camcc CAM_CC_IFE_1_CPHY_RX_CLK>, 4242 <&clock_camcc CAM_CC_IFE_1_CLK_SRC>, 4243 <&clock_camcc CAM_CC_IFE_LITE_CLK>, 4244 <&clock_camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, 4245 <&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>; 4246 clock-names = "camnoc_axi", 4247 "cpas_ahb", 4248 "cphy_rx_src", 4249 "csi0", 4250 "csi0_src", 4251 "csi1", 4252 "csi1_src", 4253 "csi2", 4254 "csi2_src", 4255 "csiphy0", 4256 "csiphy0_timer", 4257 "csiphy0_timer_src", 4258 "csiphy1", 4259 "csiphy1_timer", 4260 "csiphy1_timer_src", 4261 "csiphy2", 4262 "csiphy2_timer", 4263 "csiphy2_timer_src", 4264 "csiphy3", 4265 "csiphy3_timer", 4266 "csiphy3_timer_src", 4267 "gcc_camera_ahb", 4268 "gcc_camera_axi", 4269 "slow_ahb_src", 4270 "soc_ahb", 4271 "vfe0_axi", 4272 "vfe0", 4273 "vfe0_cphy_rx", 4274 "vfe0_src", 4275 "vfe1_axi", 4276 "vfe1", 4277 "vfe1_cphy_rx", 4278 "vfe1_src", 4279 "vfe_lite", 4280 "vfe_lite_cphy_rx", 4281 "vfe_lite_src"; 4282 4283 iommus = <&apps_smmu 0x0808 0x0>, 4284 <&apps_smmu 0x0810 0x8>, 4285 <&apps_smmu 0x0c08 0x0>, 4286 <&apps_smmu 0x0c10 0x8>; 4287 4288 status = "disabled"; 4289 4290 ports { 4291 #address-cells = <1>; 4292 #size-cells = <0>; 4293 4294 port@0 { 4295 reg = <0>; 4296 }; 4297 4298 port@1 { 4299 reg = <1>; 4300 }; 4301 4302 port@2 { 4303 reg = <2>; 4304 }; 4305 4306 port@3 { 4307 reg = <3>; 4308 }; 4309 }; 4310 }; 4311 4312 cci: cci@ac4a000 { 4313 compatible = "qcom,sdm845-cci", "qcom,msm8996-cci"; 4314 #address-cells = <1>; 4315 #size-cells = <0>; 4316 4317 reg = <0 0x0ac4a000 0 0x4000>; 4318 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>; 4319 power-domains = <&clock_camcc TITAN_TOP_GDSC>; 4320 4321 clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, 4322 <&clock_camcc CAM_CC_SOC_AHB_CLK>, 4323 <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, 4324 <&clock_camcc CAM_CC_CPAS_AHB_CLK>, 4325 <&clock_camcc CAM_CC_CCI_CLK>, 4326 <&clock_camcc CAM_CC_CCI_CLK_SRC>; 4327 clock-names = "camnoc_axi", 4328 "soc_ahb", 4329 "slow_ahb_src", 4330 "cpas_ahb", 4331 "cci", 4332 "cci_src"; 4333 4334 assigned-clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, 4335 <&clock_camcc CAM_CC_CCI_CLK>; 4336 assigned-clock-rates = <80000000>, <37500000>; 4337 4338 pinctrl-names = "default", "sleep"; 4339 pinctrl-0 = <&cci0_default &cci1_default>; 4340 pinctrl-1 = <&cci0_sleep &cci1_sleep>; 4341 4342 status = "disabled"; 4343 4344 cci_i2c0: i2c-bus@0 { 4345 reg = <0>; 4346 clock-frequency = <1000000>; 4347 #address-cells = <1>; 4348 #size-cells = <0>; 4349 }; 4350 4351 cci_i2c1: i2c-bus@1 { 4352 reg = <1>; 4353 clock-frequency = <1000000>; 4354 #address-cells = <1>; 4355 #size-cells = <0>; 4356 }; 4357 }; 4358 4359 clock_camcc: clock-controller@ad00000 { 4360 compatible = "qcom,sdm845-camcc"; 4361 reg = <0 0x0ad00000 0 0x10000>; 4362 #clock-cells = <1>; 4363 #reset-cells = <1>; 4364 #power-domain-cells = <1>; 4365 clocks = <&rpmhcc RPMH_CXO_CLK>; 4366 clock-names = "bi_tcxo"; 4367 }; 4368 4369 mdss: display-subsystem@ae00000 { 4370 compatible = "qcom,sdm845-mdss"; 4371 reg = <0 0x0ae00000 0 0x1000>; 4372 reg-names = "mdss"; 4373 4374 power-domains = <&dispcc MDSS_GDSC>; 4375 4376 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4377 <&dispcc DISP_CC_MDSS_MDP_CLK>; 4378 clock-names = "iface", "core"; 4379 4380 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 4381 interrupt-controller; 4382 #interrupt-cells = <1>; 4383 4384 interconnects = <&mmss_noc MASTER_MDP0 0 &mem_noc SLAVE_EBI1 0>, 4385 <&mmss_noc MASTER_MDP1 0 &mem_noc SLAVE_EBI1 0>; 4386 interconnect-names = "mdp0-mem", "mdp1-mem"; 4387 4388 iommus = <&apps_smmu 0x880 0x8>, 4389 <&apps_smmu 0xc80 0x8>; 4390 4391 status = "disabled"; 4392 4393 #address-cells = <2>; 4394 #size-cells = <2>; 4395 ranges; 4396 4397 mdss_mdp: display-controller@ae01000 { 4398 compatible = "qcom,sdm845-dpu"; 4399 reg = <0 0x0ae01000 0 0x8f000>, 4400 <0 0x0aeb0000 0 0x2008>; 4401 reg-names = "mdp", "vbif"; 4402 4403 clocks = <&gcc GCC_DISP_AXI_CLK>, 4404 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4405 <&dispcc DISP_CC_MDSS_AXI_CLK>, 4406 <&dispcc DISP_CC_MDSS_MDP_CLK>, 4407 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 4408 clock-names = "gcc-bus", "iface", "bus", "core", "vsync"; 4409 4410 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 4411 assigned-clock-rates = <19200000>; 4412 operating-points-v2 = <&mdp_opp_table>; 4413 power-domains = <&rpmhpd SDM845_CX>; 4414 4415 interrupt-parent = <&mdss>; 4416 interrupts = <0>; 4417 4418 ports { 4419 #address-cells = <1>; 4420 #size-cells = <0>; 4421 4422 port@0 { 4423 reg = <0>; 4424 dpu_intf0_out: endpoint { 4425 remote-endpoint = <&dp_in>; 4426 }; 4427 }; 4428 4429 port@1 { 4430 reg = <1>; 4431 dpu_intf1_out: endpoint { 4432 remote-endpoint = <&dsi0_in>; 4433 }; 4434 }; 4435 4436 port@2 { 4437 reg = <2>; 4438 dpu_intf2_out: endpoint { 4439 remote-endpoint = <&dsi1_in>; 4440 }; 4441 }; 4442 }; 4443 4444 mdp_opp_table: opp-table { 4445 compatible = "operating-points-v2"; 4446 4447 opp-19200000 { 4448 opp-hz = /bits/ 64 <19200000>; 4449 required-opps = <&rpmhpd_opp_min_svs>; 4450 }; 4451 4452 opp-171428571 { 4453 opp-hz = /bits/ 64 <171428571>; 4454 required-opps = <&rpmhpd_opp_low_svs>; 4455 }; 4456 4457 opp-344000000 { 4458 opp-hz = /bits/ 64 <344000000>; 4459 required-opps = <&rpmhpd_opp_svs_l1>; 4460 }; 4461 4462 opp-430000000 { 4463 opp-hz = /bits/ 64 <430000000>; 4464 required-opps = <&rpmhpd_opp_nom>; 4465 }; 4466 }; 4467 }; 4468 4469 mdss_dp: displayport-controller@ae90000 { 4470 status = "disabled"; 4471 compatible = "qcom,sdm845-dp"; 4472 4473 reg = <0 0x0ae90000 0 0x200>, 4474 <0 0x0ae90200 0 0x200>, 4475 <0 0x0ae90400 0 0x600>, 4476 <0 0x0ae90a00 0 0x600>, 4477 <0 0x0ae91000 0 0x600>; 4478 4479 interrupt-parent = <&mdss>; 4480 interrupts = <12>; 4481 4482 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4483 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 4484 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 4485 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 4486 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 4487 clock-names = "core_iface", "core_aux", "ctrl_link", 4488 "ctrl_link_iface", "stream_pixel"; 4489 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 4490 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 4491 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>; 4492 phys = <&dp_phy>; 4493 phy-names = "dp"; 4494 4495 operating-points-v2 = <&dp_opp_table>; 4496 power-domains = <&rpmhpd SDM845_CX>; 4497 4498 ports { 4499 #address-cells = <1>; 4500 #size-cells = <0>; 4501 port@0 { 4502 reg = <0>; 4503 dp_in: endpoint { 4504 remote-endpoint = <&dpu_intf0_out>; 4505 }; 4506 }; 4507 4508 port@1 { 4509 reg = <1>; 4510 dp_out: endpoint { }; 4511 }; 4512 }; 4513 4514 dp_opp_table: opp-table { 4515 compatible = "operating-points-v2"; 4516 4517 opp-162000000 { 4518 opp-hz = /bits/ 64 <162000000>; 4519 required-opps = <&rpmhpd_opp_low_svs>; 4520 }; 4521 4522 opp-270000000 { 4523 opp-hz = /bits/ 64 <270000000>; 4524 required-opps = <&rpmhpd_opp_svs>; 4525 }; 4526 4527 opp-540000000 { 4528 opp-hz = /bits/ 64 <540000000>; 4529 required-opps = <&rpmhpd_opp_svs_l1>; 4530 }; 4531 4532 opp-810000000 { 4533 opp-hz = /bits/ 64 <810000000>; 4534 required-opps = <&rpmhpd_opp_nom>; 4535 }; 4536 }; 4537 }; 4538 4539 dsi0: dsi@ae94000 { 4540 compatible = "qcom,sdm845-dsi-ctrl", 4541 "qcom,mdss-dsi-ctrl"; 4542 reg = <0 0x0ae94000 0 0x400>; 4543 reg-names = "dsi_ctrl"; 4544 4545 interrupt-parent = <&mdss>; 4546 interrupts = <4>; 4547 4548 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 4549 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 4550 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 4551 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 4552 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4553 <&dispcc DISP_CC_MDSS_AXI_CLK>; 4554 clock-names = "byte", 4555 "byte_intf", 4556 "pixel", 4557 "core", 4558 "iface", 4559 "bus"; 4560 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 4561 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; 4562 4563 operating-points-v2 = <&dsi_opp_table>; 4564 power-domains = <&rpmhpd SDM845_CX>; 4565 4566 phys = <&dsi0_phy>; 4567 4568 status = "disabled"; 4569 4570 #address-cells = <1>; 4571 #size-cells = <0>; 4572 4573 ports { 4574 #address-cells = <1>; 4575 #size-cells = <0>; 4576 4577 port@0 { 4578 reg = <0>; 4579 dsi0_in: endpoint { 4580 remote-endpoint = <&dpu_intf1_out>; 4581 }; 4582 }; 4583 4584 port@1 { 4585 reg = <1>; 4586 dsi0_out: endpoint { 4587 }; 4588 }; 4589 }; 4590 }; 4591 4592 dsi0_phy: phy@ae94400 { 4593 compatible = "qcom,dsi-phy-10nm"; 4594 reg = <0 0x0ae94400 0 0x200>, 4595 <0 0x0ae94600 0 0x280>, 4596 <0 0x0ae94a00 0 0x1e0>; 4597 reg-names = "dsi_phy", 4598 "dsi_phy_lane", 4599 "dsi_pll"; 4600 4601 #clock-cells = <1>; 4602 #phy-cells = <0>; 4603 4604 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4605 <&rpmhcc RPMH_CXO_CLK>; 4606 clock-names = "iface", "ref"; 4607 4608 status = "disabled"; 4609 }; 4610 4611 dsi1: dsi@ae96000 { 4612 compatible = "qcom,sdm845-dsi-ctrl", 4613 "qcom,mdss-dsi-ctrl"; 4614 reg = <0 0x0ae96000 0 0x400>; 4615 reg-names = "dsi_ctrl"; 4616 4617 interrupt-parent = <&mdss>; 4618 interrupts = <5>; 4619 4620 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 4621 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 4622 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 4623 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 4624 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4625 <&dispcc DISP_CC_MDSS_AXI_CLK>; 4626 clock-names = "byte", 4627 "byte_intf", 4628 "pixel", 4629 "core", 4630 "iface", 4631 "bus"; 4632 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 4633 assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>; 4634 4635 operating-points-v2 = <&dsi_opp_table>; 4636 power-domains = <&rpmhpd SDM845_CX>; 4637 4638 phys = <&dsi1_phy>; 4639 4640 status = "disabled"; 4641 4642 #address-cells = <1>; 4643 #size-cells = <0>; 4644 4645 ports { 4646 #address-cells = <1>; 4647 #size-cells = <0>; 4648 4649 port@0 { 4650 reg = <0>; 4651 dsi1_in: endpoint { 4652 remote-endpoint = <&dpu_intf2_out>; 4653 }; 4654 }; 4655 4656 port@1 { 4657 reg = <1>; 4658 dsi1_out: endpoint { 4659 }; 4660 }; 4661 }; 4662 }; 4663 4664 dsi1_phy: phy@ae96400 { 4665 compatible = "qcom,dsi-phy-10nm"; 4666 reg = <0 0x0ae96400 0 0x200>, 4667 <0 0x0ae96600 0 0x280>, 4668 <0 0x0ae96a00 0 0x10e>; 4669 reg-names = "dsi_phy", 4670 "dsi_phy_lane", 4671 "dsi_pll"; 4672 4673 #clock-cells = <1>; 4674 #phy-cells = <0>; 4675 4676 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4677 <&rpmhcc RPMH_CXO_CLK>; 4678 clock-names = "iface", "ref"; 4679 4680 status = "disabled"; 4681 }; 4682 }; 4683 4684 gpu: gpu@5000000 { 4685 compatible = "qcom,adreno-630.2", "qcom,adreno"; 4686 4687 reg = <0 0x05000000 0 0x40000>, <0 0x509e000 0 0x10>; 4688 reg-names = "kgsl_3d0_reg_memory", "cx_mem"; 4689 4690 /* 4691 * Look ma, no clocks! The GPU clocks and power are 4692 * controlled entirely by the GMU 4693 */ 4694 4695 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 4696 4697 iommus = <&adreno_smmu 0>; 4698 4699 operating-points-v2 = <&gpu_opp_table>; 4700 4701 qcom,gmu = <&gmu>; 4702 4703 interconnects = <&mem_noc MASTER_GFX3D 0 &mem_noc SLAVE_EBI1 0>; 4704 interconnect-names = "gfx-mem"; 4705 4706 status = "disabled"; 4707 4708 gpu_opp_table: opp-table { 4709 compatible = "operating-points-v2"; 4710 4711 opp-710000000 { 4712 opp-hz = /bits/ 64 <710000000>; 4713 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4714 opp-peak-kBps = <7216000>; 4715 }; 4716 4717 opp-675000000 { 4718 opp-hz = /bits/ 64 <675000000>; 4719 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4720 opp-peak-kBps = <7216000>; 4721 }; 4722 4723 opp-596000000 { 4724 opp-hz = /bits/ 64 <596000000>; 4725 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4726 opp-peak-kBps = <6220000>; 4727 }; 4728 4729 opp-520000000 { 4730 opp-hz = /bits/ 64 <520000000>; 4731 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4732 opp-peak-kBps = <6220000>; 4733 }; 4734 4735 opp-414000000 { 4736 opp-hz = /bits/ 64 <414000000>; 4737 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4738 opp-peak-kBps = <4068000>; 4739 }; 4740 4741 opp-342000000 { 4742 opp-hz = /bits/ 64 <342000000>; 4743 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4744 opp-peak-kBps = <2724000>; 4745 }; 4746 4747 opp-257000000 { 4748 opp-hz = /bits/ 64 <257000000>; 4749 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4750 opp-peak-kBps = <1648000>; 4751 }; 4752 }; 4753 }; 4754 4755 adreno_smmu: iommu@5040000 { 4756 compatible = "qcom,sdm845-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2"; 4757 reg = <0 0x05040000 0 0x10000>; 4758 #iommu-cells = <1>; 4759 #global-interrupts = <2>; 4760 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 4761 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 4762 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, 4763 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, 4764 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>, 4765 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>, 4766 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>, 4767 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>, 4768 <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>, 4769 <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>; 4770 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 4771 <&gcc GCC_GPU_CFG_AHB_CLK>; 4772 clock-names = "bus", "iface"; 4773 4774 power-domains = <&gpucc GPU_CX_GDSC>; 4775 }; 4776 4777 gmu: gmu@506a000 { 4778 compatible = "qcom,adreno-gmu-630.2", "qcom,adreno-gmu"; 4779 4780 reg = <0 0x0506a000 0 0x30000>, 4781 <0 0x0b280000 0 0x10000>, 4782 <0 0x0b480000 0 0x10000>; 4783 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; 4784 4785 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 4786 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 4787 interrupt-names = "hfi", "gmu"; 4788 4789 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 4790 <&gpucc GPU_CC_CXO_CLK>, 4791 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 4792 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 4793 clock-names = "gmu", "cxo", "axi", "memnoc"; 4794 4795 power-domains = <&gpucc GPU_CX_GDSC>, 4796 <&gpucc GPU_GX_GDSC>; 4797 power-domain-names = "cx", "gx"; 4798 4799 iommus = <&adreno_smmu 5>; 4800 4801 operating-points-v2 = <&gmu_opp_table>; 4802 4803 status = "disabled"; 4804 4805 gmu_opp_table: opp-table { 4806 compatible = "operating-points-v2"; 4807 4808 opp-400000000 { 4809 opp-hz = /bits/ 64 <400000000>; 4810 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4811 }; 4812 4813 opp-200000000 { 4814 opp-hz = /bits/ 64 <200000000>; 4815 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 4816 }; 4817 }; 4818 }; 4819 4820 dispcc: clock-controller@af00000 { 4821 compatible = "qcom,sdm845-dispcc"; 4822 reg = <0 0x0af00000 0 0x10000>; 4823 clocks = <&rpmhcc RPMH_CXO_CLK>, 4824 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 4825 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, 4826 <&dsi0_phy 0>, 4827 <&dsi0_phy 1>, 4828 <&dsi1_phy 0>, 4829 <&dsi1_phy 1>, 4830 <&dp_phy 0>, 4831 <&dp_phy 1>; 4832 clock-names = "bi_tcxo", 4833 "gcc_disp_gpll0_clk_src", 4834 "gcc_disp_gpll0_div_clk_src", 4835 "dsi0_phy_pll_out_byteclk", 4836 "dsi0_phy_pll_out_dsiclk", 4837 "dsi1_phy_pll_out_byteclk", 4838 "dsi1_phy_pll_out_dsiclk", 4839 "dp_link_clk_divsel_ten", 4840 "dp_vco_divided_clk_src_mux"; 4841 #clock-cells = <1>; 4842 #reset-cells = <1>; 4843 #power-domain-cells = <1>; 4844 }; 4845 4846 pdc_intc: interrupt-controller@b220000 { 4847 compatible = "qcom,sdm845-pdc", "qcom,pdc"; 4848 reg = <0 0x0b220000 0 0x30000>; 4849 qcom,pdc-ranges = <0 480 94>, <94 609 15>, <115 630 7>; 4850 #interrupt-cells = <2>; 4851 interrupt-parent = <&intc>; 4852 interrupt-controller; 4853 }; 4854 4855 pdc_reset: reset-controller@b2e0000 { 4856 compatible = "qcom,sdm845-pdc-global"; 4857 reg = <0 0x0b2e0000 0 0x20000>; 4858 #reset-cells = <1>; 4859 }; 4860 4861 tsens0: thermal-sensor@c263000 { 4862 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; 4863 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 4864 <0 0x0c222000 0 0x1ff>; /* SROT */ 4865 #qcom,sensors = <13>; 4866 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 4867 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 4868 interrupt-names = "uplow", "critical"; 4869 #thermal-sensor-cells = <1>; 4870 }; 4871 4872 tsens1: thermal-sensor@c265000 { 4873 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; 4874 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 4875 <0 0x0c223000 0 0x1ff>; /* SROT */ 4876 #qcom,sensors = <8>; 4877 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 4878 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 4879 interrupt-names = "uplow", "critical"; 4880 #thermal-sensor-cells = <1>; 4881 }; 4882 4883 aoss_reset: reset-controller@c2a0000 { 4884 compatible = "qcom,sdm845-aoss-cc"; 4885 reg = <0 0x0c2a0000 0 0x31000>; 4886 #reset-cells = <1>; 4887 }; 4888 4889 aoss_qmp: power-management@c300000 { 4890 compatible = "qcom,sdm845-aoss-qmp", "qcom,aoss-qmp"; 4891 reg = <0 0x0c300000 0 0x400>; 4892 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; 4893 mboxes = <&apss_shared 0>; 4894 4895 #clock-cells = <0>; 4896 4897 cx_cdev: cx { 4898 #cooling-cells = <2>; 4899 }; 4900 4901 ebi_cdev: ebi { 4902 #cooling-cells = <2>; 4903 }; 4904 }; 4905 4906 sram@c3f0000 { 4907 compatible = "qcom,sdm845-rpmh-stats"; 4908 reg = <0 0x0c3f0000 0 0x400>; 4909 }; 4910 4911 spmi_bus: spmi@c440000 { 4912 compatible = "qcom,spmi-pmic-arb"; 4913 reg = <0 0x0c440000 0 0x1100>, 4914 <0 0x0c600000 0 0x2000000>, 4915 <0 0x0e600000 0 0x100000>, 4916 <0 0x0e700000 0 0xa0000>, 4917 <0 0x0c40a000 0 0x26000>; 4918 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 4919 interrupt-names = "periph_irq"; 4920 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>; 4921 qcom,ee = <0>; 4922 qcom,channel = <0>; 4923 #address-cells = <2>; 4924 #size-cells = <0>; 4925 interrupt-controller; 4926 #interrupt-cells = <4>; 4927 cell-index = <0>; 4928 }; 4929 4930 sram@146bf000 { 4931 compatible = "qcom,sdm845-imem", "syscon", "simple-mfd"; 4932 reg = <0 0x146bf000 0 0x1000>; 4933 4934 #address-cells = <1>; 4935 #size-cells = <1>; 4936 4937 ranges = <0 0 0x146bf000 0x1000>; 4938 4939 pil-reloc@94c { 4940 compatible = "qcom,pil-reloc-info"; 4941 reg = <0x94c 0xc8>; 4942 }; 4943 }; 4944 4945 apps_smmu: iommu@15000000 { 4946 compatible = "qcom,sdm845-smmu-500", "arm,mmu-500"; 4947 reg = <0 0x15000000 0 0x80000>; 4948 #iommu-cells = <2>; 4949 #global-interrupts = <1>; 4950 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 4951 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 4952 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 4953 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 4954 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 4955 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 4956 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 4957 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 4958 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 4959 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 4960 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 4961 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 4962 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 4963 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 4964 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 4965 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 4966 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 4967 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 4968 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 4969 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 4970 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 4971 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 4972 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 4973 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 4974 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 4975 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 4976 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 4977 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 4978 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 4979 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 4980 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 4981 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 4982 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 4983 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 4984 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 4985 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 4986 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 4987 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 4988 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 4989 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 4990 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 4991 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 4992 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 4993 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 4994 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 4995 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 4996 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 4997 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 4998 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 4999 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 5000 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 5001 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 5002 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 5003 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 5004 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 5005 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 5006 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 5007 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 5008 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 5009 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 5010 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 5011 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 5012 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 5013 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 5014 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>; 5015 }; 5016 5017 lpasscc: clock-controller@17014000 { 5018 compatible = "qcom,sdm845-lpasscc"; 5019 reg = <0 0x17014000 0 0x1f004>, <0 0x17300000 0 0x200>; 5020 reg-names = "cc", "qdsp6ss"; 5021 #clock-cells = <1>; 5022 status = "disabled"; 5023 }; 5024 5025 gladiator_noc: interconnect@17900000 { 5026 compatible = "qcom,sdm845-gladiator-noc"; 5027 reg = <0 0x17900000 0 0xd080>; 5028 #interconnect-cells = <2>; 5029 qcom,bcm-voters = <&apps_bcm_voter>; 5030 }; 5031 5032 watchdog@17980000 { 5033 compatible = "qcom,apss-wdt-sdm845", "qcom,kpss-wdt"; 5034 reg = <0 0x17980000 0 0x1000>; 5035 clocks = <&sleep_clk>; 5036 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 5037 }; 5038 5039 apss_shared: mailbox@17990000 { 5040 compatible = "qcom,sdm845-apss-shared"; 5041 reg = <0 0x17990000 0 0x1000>; 5042 #mbox-cells = <1>; 5043 }; 5044 5045 apps_rsc: rsc@179c0000 { 5046 label = "apps_rsc"; 5047 compatible = "qcom,rpmh-rsc"; 5048 reg = <0 0x179c0000 0 0x10000>, 5049 <0 0x179d0000 0 0x10000>, 5050 <0 0x179e0000 0 0x10000>; 5051 reg-names = "drv-0", "drv-1", "drv-2"; 5052 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 5053 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 5054 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 5055 qcom,tcs-offset = <0xd00>; 5056 qcom,drv-id = <2>; 5057 qcom,tcs-config = <ACTIVE_TCS 2>, 5058 <SLEEP_TCS 3>, 5059 <WAKE_TCS 3>, 5060 <CONTROL_TCS 1>; 5061 5062 apps_bcm_voter: bcm-voter { 5063 compatible = "qcom,bcm-voter"; 5064 }; 5065 5066 rpmhcc: clock-controller { 5067 compatible = "qcom,sdm845-rpmh-clk"; 5068 #clock-cells = <1>; 5069 clock-names = "xo"; 5070 clocks = <&xo_board>; 5071 }; 5072 5073 rpmhpd: power-controller { 5074 compatible = "qcom,sdm845-rpmhpd"; 5075 #power-domain-cells = <1>; 5076 operating-points-v2 = <&rpmhpd_opp_table>; 5077 5078 rpmhpd_opp_table: opp-table { 5079 compatible = "operating-points-v2"; 5080 5081 rpmhpd_opp_ret: opp1 { 5082 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 5083 }; 5084 5085 rpmhpd_opp_min_svs: opp2 { 5086 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 5087 }; 5088 5089 rpmhpd_opp_low_svs: opp3 { 5090 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 5091 }; 5092 5093 rpmhpd_opp_svs: opp4 { 5094 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 5095 }; 5096 5097 rpmhpd_opp_svs_l1: opp5 { 5098 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 5099 }; 5100 5101 rpmhpd_opp_nom: opp6 { 5102 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 5103 }; 5104 5105 rpmhpd_opp_nom_l1: opp7 { 5106 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 5107 }; 5108 5109 rpmhpd_opp_nom_l2: opp8 { 5110 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 5111 }; 5112 5113 rpmhpd_opp_turbo: opp9 { 5114 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 5115 }; 5116 5117 rpmhpd_opp_turbo_l1: opp10 { 5118 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 5119 }; 5120 }; 5121 }; 5122 }; 5123 5124 intc: interrupt-controller@17a00000 { 5125 compatible = "arm,gic-v3"; 5126 #address-cells = <2>; 5127 #size-cells = <2>; 5128 ranges; 5129 #interrupt-cells = <3>; 5130 interrupt-controller; 5131 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 5132 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 5133 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 5134 5135 msi-controller@17a40000 { 5136 compatible = "arm,gic-v3-its"; 5137 msi-controller; 5138 #msi-cells = <1>; 5139 reg = <0 0x17a40000 0 0x20000>; 5140 status = "disabled"; 5141 }; 5142 }; 5143 5144 slimbam: dma-controller@17184000 { 5145 compatible = "qcom,bam-v1.7.0"; 5146 qcom,controlled-remotely; 5147 reg = <0 0x17184000 0 0x2a000>; 5148 num-channels = <31>; 5149 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 5150 #dma-cells = <1>; 5151 qcom,ee = <1>; 5152 qcom,num-ees = <2>; 5153 iommus = <&apps_smmu 0x1806 0x0>; 5154 }; 5155 5156 timer@17c90000 { 5157 #address-cells = <1>; 5158 #size-cells = <1>; 5159 ranges = <0 0 0 0x20000000>; 5160 compatible = "arm,armv7-timer-mem"; 5161 reg = <0 0x17c90000 0 0x1000>; 5162 5163 frame@17ca0000 { 5164 frame-number = <0>; 5165 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 5166 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 5167 reg = <0x17ca0000 0x1000>, 5168 <0x17cb0000 0x1000>; 5169 }; 5170 5171 frame@17cc0000 { 5172 frame-number = <1>; 5173 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 5174 reg = <0x17cc0000 0x1000>; 5175 status = "disabled"; 5176 }; 5177 5178 frame@17cd0000 { 5179 frame-number = <2>; 5180 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 5181 reg = <0x17cd0000 0x1000>; 5182 status = "disabled"; 5183 }; 5184 5185 frame@17ce0000 { 5186 frame-number = <3>; 5187 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 5188 reg = <0x17ce0000 0x1000>; 5189 status = "disabled"; 5190 }; 5191 5192 frame@17cf0000 { 5193 frame-number = <4>; 5194 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 5195 reg = <0x17cf0000 0x1000>; 5196 status = "disabled"; 5197 }; 5198 5199 frame@17d00000 { 5200 frame-number = <5>; 5201 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 5202 reg = <0x17d00000 0x1000>; 5203 status = "disabled"; 5204 }; 5205 5206 frame@17d10000 { 5207 frame-number = <6>; 5208 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 5209 reg = <0x17d10000 0x1000>; 5210 status = "disabled"; 5211 }; 5212 }; 5213 5214 osm_l3: interconnect@17d41000 { 5215 compatible = "qcom,sdm845-osm-l3", "qcom,osm-l3"; 5216 reg = <0 0x17d41000 0 0x1400>; 5217 5218 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 5219 clock-names = "xo", "alternate"; 5220 5221 #interconnect-cells = <1>; 5222 }; 5223 5224 cpufreq_hw: cpufreq@17d43000 { 5225 compatible = "qcom,cpufreq-hw"; 5226 reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>; 5227 reg-names = "freq-domain0", "freq-domain1"; 5228 5229 interrupts-extended = <&lmh_cluster0 0>, <&lmh_cluster1 0>; 5230 5231 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 5232 clock-names = "xo", "alternate"; 5233 5234 #freq-domain-cells = <1>; 5235 }; 5236 5237 wifi: wifi@18800000 { 5238 compatible = "qcom,wcn3990-wifi"; 5239 status = "disabled"; 5240 reg = <0 0x18800000 0 0x800000>; 5241 reg-names = "membase"; 5242 memory-region = <&wlan_msa_mem>; 5243 clock-names = "cxo_ref_clk_pin"; 5244 clocks = <&rpmhcc RPMH_RF_CLK2>; 5245 interrupts = 5246 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 5247 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 5248 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 5249 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 5250 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 5251 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 5252 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 5253 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 5254 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 5255 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 5256 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 5257 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 5258 iommus = <&apps_smmu 0x0040 0x1>; 5259 }; 5260 }; 5261 5262 sound: sound { 5263 }; 5264 5265 thermal-zones { 5266 cpu0-thermal { 5267 polling-delay-passive = <250>; 5268 polling-delay = <1000>; 5269 5270 thermal-sensors = <&tsens0 1>; 5271 5272 trips { 5273 cpu0_alert0: trip-point0 { 5274 temperature = <90000>; 5275 hysteresis = <2000>; 5276 type = "passive"; 5277 }; 5278 5279 cpu0_alert1: trip-point1 { 5280 temperature = <95000>; 5281 hysteresis = <2000>; 5282 type = "passive"; 5283 }; 5284 5285 cpu0_crit: cpu-crit { 5286 temperature = <110000>; 5287 hysteresis = <1000>; 5288 type = "critical"; 5289 }; 5290 }; 5291 }; 5292 5293 cpu1-thermal { 5294 polling-delay-passive = <250>; 5295 polling-delay = <1000>; 5296 5297 thermal-sensors = <&tsens0 2>; 5298 5299 trips { 5300 cpu1_alert0: trip-point0 { 5301 temperature = <90000>; 5302 hysteresis = <2000>; 5303 type = "passive"; 5304 }; 5305 5306 cpu1_alert1: trip-point1 { 5307 temperature = <95000>; 5308 hysteresis = <2000>; 5309 type = "passive"; 5310 }; 5311 5312 cpu1_crit: cpu-crit { 5313 temperature = <110000>; 5314 hysteresis = <1000>; 5315 type = "critical"; 5316 }; 5317 }; 5318 }; 5319 5320 cpu2-thermal { 5321 polling-delay-passive = <250>; 5322 polling-delay = <1000>; 5323 5324 thermal-sensors = <&tsens0 3>; 5325 5326 trips { 5327 cpu2_alert0: trip-point0 { 5328 temperature = <90000>; 5329 hysteresis = <2000>; 5330 type = "passive"; 5331 }; 5332 5333 cpu2_alert1: trip-point1 { 5334 temperature = <95000>; 5335 hysteresis = <2000>; 5336 type = "passive"; 5337 }; 5338 5339 cpu2_crit: cpu-crit { 5340 temperature = <110000>; 5341 hysteresis = <1000>; 5342 type = "critical"; 5343 }; 5344 }; 5345 }; 5346 5347 cpu3-thermal { 5348 polling-delay-passive = <250>; 5349 polling-delay = <1000>; 5350 5351 thermal-sensors = <&tsens0 4>; 5352 5353 trips { 5354 cpu3_alert0: trip-point0 { 5355 temperature = <90000>; 5356 hysteresis = <2000>; 5357 type = "passive"; 5358 }; 5359 5360 cpu3_alert1: trip-point1 { 5361 temperature = <95000>; 5362 hysteresis = <2000>; 5363 type = "passive"; 5364 }; 5365 5366 cpu3_crit: cpu-crit { 5367 temperature = <110000>; 5368 hysteresis = <1000>; 5369 type = "critical"; 5370 }; 5371 }; 5372 }; 5373 5374 cpu4-thermal { 5375 polling-delay-passive = <250>; 5376 polling-delay = <1000>; 5377 5378 thermal-sensors = <&tsens0 7>; 5379 5380 trips { 5381 cpu4_alert0: trip-point0 { 5382 temperature = <90000>; 5383 hysteresis = <2000>; 5384 type = "passive"; 5385 }; 5386 5387 cpu4_alert1: trip-point1 { 5388 temperature = <95000>; 5389 hysteresis = <2000>; 5390 type = "passive"; 5391 }; 5392 5393 cpu4_crit: cpu-crit { 5394 temperature = <110000>; 5395 hysteresis = <1000>; 5396 type = "critical"; 5397 }; 5398 }; 5399 }; 5400 5401 cpu5-thermal { 5402 polling-delay-passive = <250>; 5403 polling-delay = <1000>; 5404 5405 thermal-sensors = <&tsens0 8>; 5406 5407 trips { 5408 cpu5_alert0: trip-point0 { 5409 temperature = <90000>; 5410 hysteresis = <2000>; 5411 type = "passive"; 5412 }; 5413 5414 cpu5_alert1: trip-point1 { 5415 temperature = <95000>; 5416 hysteresis = <2000>; 5417 type = "passive"; 5418 }; 5419 5420 cpu5_crit: cpu-crit { 5421 temperature = <110000>; 5422 hysteresis = <1000>; 5423 type = "critical"; 5424 }; 5425 }; 5426 }; 5427 5428 cpu6-thermal { 5429 polling-delay-passive = <250>; 5430 polling-delay = <1000>; 5431 5432 thermal-sensors = <&tsens0 9>; 5433 5434 trips { 5435 cpu6_alert0: trip-point0 { 5436 temperature = <90000>; 5437 hysteresis = <2000>; 5438 type = "passive"; 5439 }; 5440 5441 cpu6_alert1: trip-point1 { 5442 temperature = <95000>; 5443 hysteresis = <2000>; 5444 type = "passive"; 5445 }; 5446 5447 cpu6_crit: cpu-crit { 5448 temperature = <110000>; 5449 hysteresis = <1000>; 5450 type = "critical"; 5451 }; 5452 }; 5453 }; 5454 5455 cpu7-thermal { 5456 polling-delay-passive = <250>; 5457 polling-delay = <1000>; 5458 5459 thermal-sensors = <&tsens0 10>; 5460 5461 trips { 5462 cpu7_alert0: trip-point0 { 5463 temperature = <90000>; 5464 hysteresis = <2000>; 5465 type = "passive"; 5466 }; 5467 5468 cpu7_alert1: trip-point1 { 5469 temperature = <95000>; 5470 hysteresis = <2000>; 5471 type = "passive"; 5472 }; 5473 5474 cpu7_crit: cpu-crit { 5475 temperature = <110000>; 5476 hysteresis = <1000>; 5477 type = "critical"; 5478 }; 5479 }; 5480 }; 5481 5482 aoss0-thermal { 5483 polling-delay-passive = <250>; 5484 polling-delay = <1000>; 5485 5486 thermal-sensors = <&tsens0 0>; 5487 5488 trips { 5489 aoss0_alert0: trip-point0 { 5490 temperature = <90000>; 5491 hysteresis = <2000>; 5492 type = "hot"; 5493 }; 5494 }; 5495 }; 5496 5497 cluster0-thermal { 5498 polling-delay-passive = <250>; 5499 polling-delay = <1000>; 5500 5501 thermal-sensors = <&tsens0 5>; 5502 5503 trips { 5504 cluster0_alert0: trip-point0 { 5505 temperature = <90000>; 5506 hysteresis = <2000>; 5507 type = "hot"; 5508 }; 5509 cluster0_crit: cluster0_crit { 5510 temperature = <110000>; 5511 hysteresis = <2000>; 5512 type = "critical"; 5513 }; 5514 }; 5515 }; 5516 5517 cluster1-thermal { 5518 polling-delay-passive = <250>; 5519 polling-delay = <1000>; 5520 5521 thermal-sensors = <&tsens0 6>; 5522 5523 trips { 5524 cluster1_alert0: trip-point0 { 5525 temperature = <90000>; 5526 hysteresis = <2000>; 5527 type = "hot"; 5528 }; 5529 cluster1_crit: cluster1_crit { 5530 temperature = <110000>; 5531 hysteresis = <2000>; 5532 type = "critical"; 5533 }; 5534 }; 5535 }; 5536 5537 gpu-top-thermal { 5538 polling-delay-passive = <250>; 5539 polling-delay = <1000>; 5540 5541 thermal-sensors = <&tsens0 11>; 5542 5543 trips { 5544 gpu1_alert0: trip-point0 { 5545 temperature = <90000>; 5546 hysteresis = <2000>; 5547 type = "hot"; 5548 }; 5549 }; 5550 }; 5551 5552 gpu-bottom-thermal { 5553 polling-delay-passive = <250>; 5554 polling-delay = <1000>; 5555 5556 thermal-sensors = <&tsens0 12>; 5557 5558 trips { 5559 gpu2_alert0: trip-point0 { 5560 temperature = <90000>; 5561 hysteresis = <2000>; 5562 type = "hot"; 5563 }; 5564 }; 5565 }; 5566 5567 aoss1-thermal { 5568 polling-delay-passive = <250>; 5569 polling-delay = <1000>; 5570 5571 thermal-sensors = <&tsens1 0>; 5572 5573 trips { 5574 aoss1_alert0: trip-point0 { 5575 temperature = <90000>; 5576 hysteresis = <2000>; 5577 type = "hot"; 5578 }; 5579 }; 5580 }; 5581 5582 q6-modem-thermal { 5583 polling-delay-passive = <250>; 5584 polling-delay = <1000>; 5585 5586 thermal-sensors = <&tsens1 1>; 5587 5588 trips { 5589 q6_modem_alert0: trip-point0 { 5590 temperature = <90000>; 5591 hysteresis = <2000>; 5592 type = "hot"; 5593 }; 5594 }; 5595 }; 5596 5597 mem-thermal { 5598 polling-delay-passive = <250>; 5599 polling-delay = <1000>; 5600 5601 thermal-sensors = <&tsens1 2>; 5602 5603 trips { 5604 mem_alert0: trip-point0 { 5605 temperature = <90000>; 5606 hysteresis = <2000>; 5607 type = "hot"; 5608 }; 5609 }; 5610 }; 5611 5612 wlan-thermal { 5613 polling-delay-passive = <250>; 5614 polling-delay = <1000>; 5615 5616 thermal-sensors = <&tsens1 3>; 5617 5618 trips { 5619 wlan_alert0: trip-point0 { 5620 temperature = <90000>; 5621 hysteresis = <2000>; 5622 type = "hot"; 5623 }; 5624 }; 5625 }; 5626 5627 q6-hvx-thermal { 5628 polling-delay-passive = <250>; 5629 polling-delay = <1000>; 5630 5631 thermal-sensors = <&tsens1 4>; 5632 5633 trips { 5634 q6_hvx_alert0: trip-point0 { 5635 temperature = <90000>; 5636 hysteresis = <2000>; 5637 type = "hot"; 5638 }; 5639 }; 5640 }; 5641 5642 camera-thermal { 5643 polling-delay-passive = <250>; 5644 polling-delay = <1000>; 5645 5646 thermal-sensors = <&tsens1 5>; 5647 5648 trips { 5649 camera_alert0: trip-point0 { 5650 temperature = <90000>; 5651 hysteresis = <2000>; 5652 type = "hot"; 5653 }; 5654 }; 5655 }; 5656 5657 video-thermal { 5658 polling-delay-passive = <250>; 5659 polling-delay = <1000>; 5660 5661 thermal-sensors = <&tsens1 6>; 5662 5663 trips { 5664 video_alert0: trip-point0 { 5665 temperature = <90000>; 5666 hysteresis = <2000>; 5667 type = "hot"; 5668 }; 5669 }; 5670 }; 5671 5672 modem-thermal { 5673 polling-delay-passive = <250>; 5674 polling-delay = <1000>; 5675 5676 thermal-sensors = <&tsens1 7>; 5677 5678 trips { 5679 modem_alert0: trip-point0 { 5680 temperature = <90000>; 5681 hysteresis = <2000>; 5682 type = "hot"; 5683 }; 5684 }; 5685 }; 5686 }; 5687 5688 timer { 5689 compatible = "arm,armv8-timer"; 5690 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 5691 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 5692 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 5693 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 5694 }; 5695}; 5696