1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Google Cheza device tree source (common between revisions) 4 * 5 * Copyright 2018 Google LLC. 6 */ 7 8#include <dt-bindings/input/input.h> 9#include <dt-bindings/regulator/qcom,rpmh-regulator.h> 10#include "sdm845.dtsi" 11 12/* PMICs depend on spmi_bus label and so must come after SoC */ 13#include "pm8005.dtsi" 14#include "pm8998.dtsi" 15 16/ { 17 aliases { 18 bluetooth0 = &bluetooth; 19 serial1 = &uart6; 20 serial0 = &uart9; 21 wifi0 = &wifi; 22 }; 23 24 chosen { 25 stdout-path = "serial0:115200n8"; 26 }; 27 28 backlight: backlight { 29 compatible = "pwm-backlight"; 30 pwms = <&cros_ec_pwm 0>; 31 enable-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>; 32 power-supply = <&ppvar_sys>; 33 pinctrl-names = "default"; 34 pinctrl-0 = <&ap_edp_bklten>; 35 }; 36 37 /* FIXED REGULATORS - parents above children */ 38 39 /* This is the top level supply and variable voltage */ 40 ppvar_sys: ppvar-sys-regulator { 41 compatible = "regulator-fixed"; 42 regulator-name = "ppvar_sys"; 43 regulator-always-on; 44 regulator-boot-on; 45 }; 46 47 /* This divides ppvar_sys by 2, so voltage is variable */ 48 src_vph_pwr: src-vph-pwr-regulator { 49 compatible = "regulator-fixed"; 50 regulator-name = "src_vph_pwr"; 51 52 /* EC turns on with switchcap_on_l; always on for AP */ 53 regulator-always-on; 54 regulator-boot-on; 55 56 vin-supply = <&ppvar_sys>; 57 }; 58 59 pp5000_a: pp5000-a-regulator { 60 compatible = "regulator-fixed"; 61 regulator-name = "pp5000_a"; 62 63 /* EC turns on with en_pp5000_a; always on for AP */ 64 regulator-always-on; 65 regulator-boot-on; 66 regulator-min-microvolt = <5000000>; 67 regulator-max-microvolt = <5000000>; 68 69 vin-supply = <&ppvar_sys>; 70 }; 71 72 src_vreg_bob: src-vreg-bob-regulator { 73 compatible = "regulator-fixed"; 74 regulator-name = "src_vreg_bob"; 75 76 /* EC turns on with vbob_en; always on for AP */ 77 regulator-always-on; 78 regulator-boot-on; 79 regulator-min-microvolt = <3600000>; 80 regulator-max-microvolt = <3600000>; 81 82 vin-supply = <&ppvar_sys>; 83 }; 84 85 pp3300_dx_edp: pp3300-dx-edp-regulator { 86 compatible = "regulator-fixed"; 87 regulator-name = "pp3300_dx_edp"; 88 89 regulator-min-microvolt = <3300000>; 90 regulator-max-microvolt = <3300000>; 91 92 gpio = <&tlmm 43 GPIO_ACTIVE_HIGH>; 93 enable-active-high; 94 pinctrl-names = "default"; 95 pinctrl-0 = <&en_pp3300_dx_edp>; 96 }; 97 98 /* 99 * Apparently RPMh does not provide support for PM8998 S4 because it 100 * is always-on; model it as a fixed regulator. 101 */ 102 src_pp1800_s4a: pm8998-smps4 { 103 compatible = "regulator-fixed"; 104 regulator-name = "src_pp1800_s4a"; 105 106 regulator-min-microvolt = <1800000>; 107 regulator-max-microvolt = <1800000>; 108 109 regulator-always-on; 110 regulator-boot-on; 111 112 vin-supply = <&src_vph_pwr>; 113 }; 114 115 /* BOARD-SPECIFIC TOP LEVEL NODES */ 116 117 gpio-keys { 118 compatible = "gpio-keys"; 119 pinctrl-names = "default"; 120 pinctrl-0 = <&pen_eject_odl>; 121 122 switch-pen-insert { 123 label = "Pen Insert"; 124 /* Insert = low, eject = high */ 125 gpios = <&tlmm 119 GPIO_ACTIVE_LOW>; 126 linux,code = <SW_PEN_INSERTED>; 127 linux,input-type = <EV_SW>; 128 wakeup-source; 129 }; 130 }; 131 132 panel: panel { 133 compatible = "innolux,p120zdg-bf1"; 134 power-supply = <&pp3300_dx_edp>; 135 backlight = <&backlight>; 136 no-hpd; 137 138 ports { 139 panel_in: port { 140 panel_in_edp: endpoint { 141 remote-endpoint = <&sn65dsi86_out>; 142 }; 143 }; 144 }; 145 }; 146}; 147 148&psci { 149 /delete-node/ cpu0; 150 /delete-node/ cpu1; 151 /delete-node/ cpu2; 152 /delete-node/ cpu3; 153 /delete-node/ cpu4; 154 /delete-node/ cpu5; 155 /delete-node/ cpu6; 156 /delete-node/ cpu7; 157 /delete-node/ cpu-cluster0; 158}; 159 160&cpus { 161 /delete-node/ domain-idle-states; 162}; 163 164&cpu_idle_states { 165 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 166 compatible = "arm,idle-state"; 167 idle-state-name = "little-power-down"; 168 arm,psci-suspend-param = <0x40000003>; 169 entry-latency-us = <350>; 170 exit-latency-us = <461>; 171 min-residency-us = <1890>; 172 local-timer-stop; 173 }; 174 175 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 176 compatible = "arm,idle-state"; 177 idle-state-name = "little-rail-power-down"; 178 arm,psci-suspend-param = <0x40000004>; 179 entry-latency-us = <360>; 180 exit-latency-us = <531>; 181 min-residency-us = <3934>; 182 local-timer-stop; 183 }; 184 185 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 186 compatible = "arm,idle-state"; 187 idle-state-name = "big-power-down"; 188 arm,psci-suspend-param = <0x40000003>; 189 entry-latency-us = <264>; 190 exit-latency-us = <621>; 191 min-residency-us = <952>; 192 local-timer-stop; 193 }; 194 195 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 196 compatible = "arm,idle-state"; 197 idle-state-name = "big-rail-power-down"; 198 arm,psci-suspend-param = <0x40000004>; 199 entry-latency-us = <702>; 200 exit-latency-us = <1061>; 201 min-residency-us = <4488>; 202 local-timer-stop; 203 }; 204 205 CLUSTER_SLEEP_0: cluster-sleep-0 { 206 compatible = "arm,idle-state"; 207 idle-state-name = "cluster-power-down"; 208 arm,psci-suspend-param = <0x400000F4>; 209 entry-latency-us = <3263>; 210 exit-latency-us = <6562>; 211 min-residency-us = <9987>; 212 local-timer-stop; 213 }; 214}; 215 216&CPU0 { 217 /delete-property/ power-domains; 218 /delete-property/ power-domain-names; 219 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 220 &LITTLE_CPU_SLEEP_1 221 &CLUSTER_SLEEP_0>; 222}; 223 224&CPU1 { 225 /delete-property/ power-domains; 226 /delete-property/ power-domain-names; 227 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 228 &LITTLE_CPU_SLEEP_1 229 &CLUSTER_SLEEP_0>; 230}; 231 232&CPU2 { 233 /delete-property/ power-domains; 234 /delete-property/ power-domain-names; 235 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 236 &LITTLE_CPU_SLEEP_1 237 &CLUSTER_SLEEP_0>; 238}; 239 240&CPU3 { 241 /delete-property/ power-domains; 242 /delete-property/ power-domain-names; 243 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 244 &LITTLE_CPU_SLEEP_1 245 &CLUSTER_SLEEP_0>; 246}; 247 248&CPU4 { 249 /delete-property/ power-domains; 250 /delete-property/ power-domain-names; 251 cpu-idle-states = <&BIG_CPU_SLEEP_0 252 &BIG_CPU_SLEEP_1 253 &CLUSTER_SLEEP_0>; 254}; 255 256&CPU5 { 257 /delete-property/ power-domains; 258 /delete-property/ power-domain-names; 259 cpu-idle-states = <&BIG_CPU_SLEEP_0 260 &BIG_CPU_SLEEP_1 261 &CLUSTER_SLEEP_0>; 262}; 263 264&CPU6 { 265 /delete-property/ power-domains; 266 /delete-property/ power-domain-names; 267 cpu-idle-states = <&BIG_CPU_SLEEP_0 268 &BIG_CPU_SLEEP_1 269 &CLUSTER_SLEEP_0>; 270}; 271 272&CPU7 { 273 /delete-property/ power-domains; 274 /delete-property/ power-domain-names; 275 cpu-idle-states = <&BIG_CPU_SLEEP_0 276 &BIG_CPU_SLEEP_1 277 &CLUSTER_SLEEP_0>; 278}; 279 280/* 281 * Reserved memory changes 282 * 283 * Putting this all together (out of order with the rest of the file) to keep 284 * all modifications to the memory map (from sdm845.dtsi) in one place. 285 */ 286 287/* 288 * Our mpss_region is 8MB bigger than the default one and that conflicts 289 * with venus_mem and cdsp_mem. 290 * 291 * For venus_mem we'll delete and re-create at a different address. 292 * 293 * cdsp_mem isn't used on cheza right now so we won't bother re-creating it; but 294 * that also means we need to delete cdsp_pas. 295 */ 296/delete-node/ &venus_mem; 297/delete-node/ &cdsp_mem; 298/delete-node/ &cdsp_pas; 299/delete-node/ &gpu_mem; 300 301/* Increase the size from 120 MB to 128 MB */ 302&mpss_region { 303 reg = <0 0x8e000000 0 0x8000000>; 304}; 305 306/* Increase the size from 2MB to 8MB */ 307&rmtfs_mem { 308 reg = <0 0x88f00000 0 0x800000>; 309}; 310 311/ { 312 reserved-memory { 313 venus_mem: memory@96000000 { 314 reg = <0 0x96000000 0 0x500000>; 315 no-map; 316 }; 317 }; 318}; 319 320&qspi { 321 status = "okay"; 322 pinctrl-names = "default"; 323 pinctrl-0 = <&qspi_clk &qspi_cs0 &qspi_data01>; 324 325 flash@0 { 326 compatible = "jedec,spi-nor"; 327 reg = <0>; 328 329 /* 330 * In theory chip supports up to 104 MHz and controller up 331 * to 80 MHz, but above 25 MHz wasn't reliable so we'll use 332 * that for now. b:117440651 333 */ 334 spi-max-frequency = <25000000>; 335 spi-tx-bus-width = <2>; 336 spi-rx-bus-width = <2>; 337 }; 338}; 339 340 341&apps_rsc { 342 pm8998-rpmh-regulators { 343 compatible = "qcom,pm8998-rpmh-regulators"; 344 qcom,pmic-id = "a"; 345 346 vdd-s1-supply = <&src_vph_pwr>; 347 vdd-s2-supply = <&src_vph_pwr>; 348 vdd-s3-supply = <&src_vph_pwr>; 349 vdd-s4-supply = <&src_vph_pwr>; 350 vdd-s5-supply = <&src_vph_pwr>; 351 vdd-s6-supply = <&src_vph_pwr>; 352 vdd-s7-supply = <&src_vph_pwr>; 353 vdd-s8-supply = <&src_vph_pwr>; 354 vdd-s9-supply = <&src_vph_pwr>; 355 vdd-s10-supply = <&src_vph_pwr>; 356 vdd-s11-supply = <&src_vph_pwr>; 357 vdd-s12-supply = <&src_vph_pwr>; 358 vdd-s13-supply = <&src_vph_pwr>; 359 vdd-l1-l27-supply = <&src_pp1025_s7a>; 360 vdd-l2-l8-l17-supply = <&src_pp1350_s3a>; 361 vdd-l3-l11-supply = <&src_pp1025_s7a>; 362 vdd-l4-l5-supply = <&src_pp1025_s7a>; 363 vdd-l6-supply = <&src_vph_pwr>; 364 vdd-l7-l12-l14-l15-supply = <&src_pp2040_s5a>; 365 vdd-l9-supply = <&src_pp2040_s5a>; 366 vdd-l10-l23-l25-supply = <&src_vreg_bob>; 367 vdd-l13-l19-l21-supply = <&src_vreg_bob>; 368 vdd-l16-l28-supply = <&src_vreg_bob>; 369 vdd-l18-l22-supply = <&src_vreg_bob>; 370 vdd-l20-l24-supply = <&src_vreg_bob>; 371 vdd-l26-supply = <&src_pp1350_s3a>; 372 vin-lvs-1-2-supply = <&src_pp1800_s4a>; 373 374 src_pp1125_s2a: smps2 { 375 regulator-min-microvolt = <1100000>; 376 regulator-max-microvolt = <1100000>; 377 }; 378 379 src_pp1350_s3a: smps3 { 380 regulator-min-microvolt = <1352000>; 381 regulator-max-microvolt = <1352000>; 382 }; 383 384 src_pp2040_s5a: smps5 { 385 regulator-min-microvolt = <1904000>; 386 regulator-max-microvolt = <2040000>; 387 }; 388 389 src_pp1025_s7a: smps7 { 390 regulator-min-microvolt = <900000>; 391 regulator-max-microvolt = <1028000>; 392 }; 393 394 vdd_qusb_hs0: 395 vdda_hp_pcie_core: 396 vdda_mipi_csi0_0p9: 397 vdda_mipi_csi1_0p9: 398 vdda_mipi_csi2_0p9: 399 vdda_mipi_dsi0_pll: 400 vdda_mipi_dsi1_pll: 401 vdda_qlink_lv: 402 vdda_qlink_lv_ck: 403 vdda_qrefs_0p875: 404 vdda_pcie_core: 405 vdda_pll_cc_ebi01: 406 vdda_pll_cc_ebi23: 407 vdda_sp_sensor: 408 vdda_ufs1_core: 409 vdda_ufs2_core: 410 vdda_usb1_ss_core: 411 vdda_usb2_ss_core: 412 src_pp875_l1a: ldo1 { 413 regulator-min-microvolt = <880000>; 414 regulator-max-microvolt = <880000>; 415 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 416 }; 417 418 vddpx_10: 419 src_pp1200_l2a: ldo2 { 420 regulator-min-microvolt = <1200000>; 421 regulator-max-microvolt = <1200000>; 422 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 423 424 /* TODO: why??? */ 425 regulator-always-on; 426 }; 427 428 pp1000_l3a_sdr845: ldo3 { 429 regulator-min-microvolt = <1000000>; 430 regulator-max-microvolt = <1000000>; 431 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 432 }; 433 434 vdd_wcss_cx: 435 vdd_wcss_mx: 436 vdda_wcss_pll: 437 src_pp800_l5a: ldo5 { 438 regulator-min-microvolt = <800000>; 439 regulator-max-microvolt = <800000>; 440 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 441 }; 442 443 vddpx_13: 444 src_pp1800_l6a: ldo6 { 445 regulator-min-microvolt = <1856000>; 446 regulator-max-microvolt = <1856000>; 447 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 448 }; 449 450 pp1800_l7a_wcn3990: ldo7 { 451 regulator-min-microvolt = <1800000>; 452 regulator-max-microvolt = <1800000>; 453 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 454 }; 455 456 src_pp1200_l8a: ldo8 { 457 regulator-min-microvolt = <1200000>; 458 regulator-max-microvolt = <1248000>; 459 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 460 }; 461 462 pp1800_dx_pen: 463 src_pp1800_l9a: ldo9 { 464 regulator-min-microvolt = <1800000>; 465 regulator-max-microvolt = <1800000>; 466 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 467 }; 468 469 src_pp1800_l10a: ldo10 { 470 regulator-min-microvolt = <1800000>; 471 regulator-max-microvolt = <1800000>; 472 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 473 }; 474 475 pp1000_l11a_sdr845: ldo11 { 476 regulator-min-microvolt = <1000000>; 477 regulator-max-microvolt = <1048000>; 478 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 479 }; 480 481 vdd_qfprom: 482 vdd_qfprom_sp: 483 vdda_apc1_cs_1p8: 484 vdda_gfx_cs_1p8: 485 vdda_qrefs_1p8: 486 vdda_qusb_hs0_1p8: 487 vddpx_11: 488 src_pp1800_l12a: ldo12 { 489 regulator-min-microvolt = <1800000>; 490 regulator-max-microvolt = <1800000>; 491 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 492 }; 493 494 vddpx_2: 495 src_pp2950_l13a: ldo13 { 496 regulator-min-microvolt = <1800000>; 497 regulator-max-microvolt = <2960000>; 498 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 499 }; 500 501 src_pp1800_l14a: ldo14 { 502 regulator-min-microvolt = <1800000>; 503 regulator-max-microvolt = <1800000>; 504 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 505 }; 506 507 src_pp1800_l15a: ldo15 { 508 regulator-min-microvolt = <1800000>; 509 regulator-max-microvolt = <1800000>; 510 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 511 }; 512 513 pp2700_l16a: ldo16 { 514 regulator-min-microvolt = <2704000>; 515 regulator-max-microvolt = <2704000>; 516 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 517 }; 518 519 src_pp1300_l17a: ldo17 { 520 regulator-min-microvolt = <1304000>; 521 regulator-max-microvolt = <1304000>; 522 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 523 }; 524 525 pp2700_l18a: ldo18 { 526 regulator-min-microvolt = <2704000>; 527 regulator-max-microvolt = <2960000>; 528 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 529 }; 530 531 /* 532 * NOTE: this rail should have been called 533 * src_pp3300_l19a in the schematic 534 */ 535 src_pp3000_l19a: ldo19 { 536 regulator-min-microvolt = <3304000>; 537 regulator-max-microvolt = <3304000>; 538 539 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 540 }; 541 542 src_pp2950_l20a: ldo20 { 543 regulator-min-microvolt = <2704000>; 544 regulator-max-microvolt = <2960000>; 545 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 546 }; 547 548 src_pp2950_l21a: ldo21 { 549 regulator-min-microvolt = <2704000>; 550 regulator-max-microvolt = <2960000>; 551 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 552 }; 553 554 pp3300_hub: 555 src_pp3300_l22a: ldo22 { 556 regulator-min-microvolt = <3304000>; 557 regulator-max-microvolt = <3304000>; 558 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 559 /* 560 * HACK: Should add a usb hub node and driver 561 * to turn this on and off at suspend/resume time 562 */ 563 regulator-boot-on; 564 regulator-always-on; 565 }; 566 567 pp3300_l23a_ch1_wcn3990: ldo23 { 568 regulator-min-microvolt = <3000000>; 569 regulator-max-microvolt = <3312000>; 570 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 571 }; 572 573 vdda_qusb_hs0_3p1: 574 src_pp3075_l24a: ldo24 { 575 regulator-min-microvolt = <3088000>; 576 regulator-max-microvolt = <3088000>; 577 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 578 }; 579 580 pp3300_l25a_ch0_wcn3990: ldo25 { 581 regulator-min-microvolt = <3304000>; 582 regulator-max-microvolt = <3304000>; 583 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 584 }; 585 586 pp1200_hub: 587 vdda_hp_pcie_1p2: 588 vdda_hv_ebi0: 589 vdda_hv_ebi1: 590 vdda_hv_ebi2: 591 vdda_hv_ebi3: 592 vdda_mipi_csi_1p25: 593 vdda_mipi_dsi0_1p2: 594 vdda_mipi_dsi1_1p2: 595 vdda_pcie_1p2: 596 vdda_ufs1_1p2: 597 vdda_ufs2_1p2: 598 vdda_usb1_ss_1p2: 599 vdda_usb2_ss_1p2: 600 src_pp1200_l26a: ldo26 { 601 regulator-min-microvolt = <1200000>; 602 regulator-max-microvolt = <1200000>; 603 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 604 }; 605 606 pp3300_dx_pen: 607 src_pp3300_l28a: ldo28 { 608 regulator-min-microvolt = <3304000>; 609 regulator-max-microvolt = <3304000>; 610 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 611 }; 612 613 src_pp1800_lvs1: lvs1 { 614 regulator-min-microvolt = <1800000>; 615 regulator-max-microvolt = <1800000>; 616 }; 617 618 src_pp1800_lvs2: lvs2 { 619 regulator-min-microvolt = <1800000>; 620 regulator-max-microvolt = <1800000>; 621 }; 622 }; 623 624 pm8005-rpmh-regulators { 625 compatible = "qcom,pm8005-rpmh-regulators"; 626 qcom,pmic-id = "c"; 627 628 vdd-s1-supply = <&src_vph_pwr>; 629 vdd-s2-supply = <&src_vph_pwr>; 630 vdd-s3-supply = <&src_vph_pwr>; 631 vdd-s4-supply = <&src_vph_pwr>; 632 633 src_pp600_s3c: smps3 { 634 regulator-min-microvolt = <600000>; 635 regulator-max-microvolt = <600000>; 636 }; 637 }; 638}; 639 640&dsi0 { 641 status = "okay"; 642 vdda-supply = <&vdda_mipi_dsi0_1p2>; 643 644 ports { 645 port@1 { 646 endpoint { 647 remote-endpoint = <&sn65dsi86_in>; 648 data-lanes = <0 1 2 3>; 649 }; 650 }; 651 }; 652}; 653 654&dsi0_phy { 655 status = "okay"; 656 vdds-supply = <&vdda_mipi_dsi0_pll>; 657}; 658 659edp_brij_i2c: &i2c3 { 660 status = "okay"; 661 clock-frequency = <400000>; 662 663 sn65dsi86_bridge: bridge@2d { 664 compatible = "ti,sn65dsi86"; 665 reg = <0x2d>; 666 pinctrl-names = "default"; 667 pinctrl-0 = <&edp_brij_en &edp_brij_irq>; 668 669 interrupt-parent = <&tlmm>; 670 interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; 671 672 enable-gpios = <&tlmm 102 GPIO_ACTIVE_HIGH>; 673 674 vpll-supply = <&src_pp1800_s4a>; 675 vccio-supply = <&src_pp1800_s4a>; 676 vcca-supply = <&src_pp1200_l2a>; 677 vcc-supply = <&src_pp1200_l2a>; 678 679 clocks = <&rpmhcc RPMH_LN_BB_CLK2>; 680 clock-names = "refclk"; 681 682 no-hpd; 683 684 ports { 685 #address-cells = <1>; 686 #size-cells = <0>; 687 688 port@0 { 689 reg = <0>; 690 sn65dsi86_in: endpoint { 691 remote-endpoint = <&dsi0_out>; 692 }; 693 }; 694 695 port@1 { 696 reg = <1>; 697 sn65dsi86_out: endpoint { 698 remote-endpoint = <&panel_in_edp>; 699 }; 700 }; 701 }; 702 }; 703}; 704 705ap_pen_1v8: &i2c11 { 706 status = "okay"; 707 clock-frequency = <400000>; 708 709 digitizer@9 { 710 compatible = "wacom,w9013", "hid-over-i2c"; 711 reg = <0x9>; 712 pinctrl-names = "default"; 713 pinctrl-0 = <&pen_irq_l>, <&pen_pdct_l>, <&pen_rst_l>; 714 715 vdd-supply = <&pp3300_dx_pen>; 716 vddl-supply = <&pp1800_dx_pen>; 717 post-power-on-delay-ms = <100>; 718 719 interrupt-parent = <&tlmm>; 720 interrupts = <24 IRQ_TYPE_LEVEL_LOW>; 721 722 hid-descr-addr = <0x1>; 723 }; 724}; 725 726amp_i2c: &i2c12 { 727 status = "okay"; 728 clock-frequency = <400000>; 729}; 730 731ap_ts_i2c: &i2c14 { 732 status = "okay"; 733 clock-frequency = <400000>; 734 735 touchscreen@10 { 736 compatible = "elan,ekth3500"; 737 reg = <0x10>; 738 pinctrl-names = "default"; 739 pinctrl-0 = <&ts_int_l &ts_reset_l>; 740 741 interrupt-parent = <&tlmm>; 742 interrupts = <125 IRQ_TYPE_LEVEL_LOW>; 743 744 vcc33-supply = <&src_pp3300_l28a>; 745 746 reset-gpios = <&tlmm 118 GPIO_ACTIVE_LOW>; 747 }; 748}; 749 750&gmu { 751 status = "okay"; 752}; 753 754&gpu { 755 status = "okay"; 756}; 757 758&ipa { 759 status = "okay"; 760 modem-init; 761}; 762 763&lpasscc { 764 status = "okay"; 765}; 766 767&mdss { 768 status = "okay"; 769}; 770 771/* 772 * Cheza fw does not properly program the GPU aperture to allow the 773 * GPU to update the SMMU pagetables for context switches. Work 774 * around this by dropping the "qcom,adreno-smmu" compat string. 775 */ 776&adreno_smmu { 777 compatible = "qcom,sdm845-smmu-v2", "qcom,smmu-v2"; 778}; 779 780&mss_pil { 781 status = "okay"; 782 783 iommus = <&apps_smmu 0x781 0x0>, 784 <&apps_smmu 0x724 0x3>; 785}; 786 787&pm8998_pwrkey { 788 status = "disabled"; 789}; 790 791&qupv3_id_0 { 792 status = "okay"; 793 iommus = <&apps_smmu 0x0 0x3>; 794}; 795 796&qupv3_id_1 { 797 status = "okay"; 798 iommus = <&apps_smmu 0x6c0 0x3>; 799}; 800 801&sdhc_2 { 802 status = "okay"; 803 804 pinctrl-names = "default"; 805 pinctrl-0 = <&sdc2_clk &sdc2_cmd &sdc2_data &sd_cd_odl>; 806 807 vmmc-supply = <&src_pp2950_l21a>; 808 vqmmc-supply = <&vddpx_2>; 809 810 cd-gpios = <&tlmm 44 GPIO_ACTIVE_LOW>; 811}; 812 813&spi0 { 814 status = "okay"; 815}; 816 817&spi5 { 818 status = "okay"; 819 820 tpm@0 { 821 compatible = "google,cr50"; 822 reg = <0>; 823 pinctrl-names = "default"; 824 pinctrl-0 = <&h1_ap_int_odl>; 825 spi-max-frequency = <800000>; 826 interrupt-parent = <&tlmm>; 827 interrupts = <129 IRQ_TYPE_EDGE_RISING>; 828 }; 829}; 830 831&spi10 { 832 status = "okay"; 833 834 cros_ec: ec@0 { 835 compatible = "google,cros-ec-spi"; 836 reg = <0>; 837 interrupt-parent = <&tlmm>; 838 interrupts = <122 IRQ_TYPE_LEVEL_LOW>; 839 pinctrl-names = "default"; 840 pinctrl-0 = <&ec_ap_int_l>; 841 spi-max-frequency = <3000000>; 842 843 cros_ec_pwm: pwm { 844 compatible = "google,cros-ec-pwm"; 845 #pwm-cells = <1>; 846 }; 847 848 i2c_tunnel: i2c-tunnel { 849 compatible = "google,cros-ec-i2c-tunnel"; 850 google,remote-bus = <0>; 851 #address-cells = <1>; 852 #size-cells = <0>; 853 }; 854 }; 855}; 856 857#include <arm/cros-ec-keyboard.dtsi> 858#include <arm/cros-ec-sbs.dtsi> 859 860&uart6 { 861 status = "okay"; 862 863 pinctrl-0 = <&qup_uart6_4pin>; 864 865 bluetooth: wcn3990-bt { 866 compatible = "qcom,wcn3990-bt"; 867 vddio-supply = <&src_pp1800_s4a>; 868 vddxo-supply = <&pp1800_l7a_wcn3990>; 869 vddrf-supply = <&src_pp1300_l17a>; 870 vddch0-supply = <&pp3300_l25a_ch0_wcn3990>; 871 max-speed = <3200000>; 872 }; 873}; 874 875&uart9 { 876 status = "okay"; 877}; 878 879&ufs_mem_hc { 880 status = "okay"; 881 882 reset-gpios = <&tlmm 150 GPIO_ACTIVE_LOW>; 883 884 vcc-supply = <&src_pp2950_l20a>; 885 vcc-max-microamp = <600000>; 886}; 887 888&ufs_mem_phy { 889 status = "okay"; 890 891 vdda-phy-supply = <&vdda_ufs1_core>; 892 vdda-pll-supply = <&vdda_ufs1_1p2>; 893}; 894 895&usb_1 { 896 status = "okay"; 897 898 /* We'll use this as USB 2.0 only */ 899 qcom,select-utmi-as-pipe-clk; 900}; 901 902&usb_1_dwc3 { 903 /* 904 * The hardware design intends this port to be hooked up in peripheral 905 * mode, so we'll hardcode it here. Some details: 906 * - SDM845 expects only a single Type C connector so it has only one 907 * native Type C port but cheza has two Type C connectors. 908 * - The only source of DP is the single native Type C port. 909 * - On cheza we want to be able to hook DP up to _either_ of the 910 * two Type C connectors and want to be able to achieve 4 lanes of DP. 911 * - When you configure a Type C port for 4 lanes of DP you lose USB3. 912 * - In order to make everything work, the native Type C port is always 913 * configured as 4-lanes DP so it's always available. 914 * - The extra USB3 port on SDM845 goes to a USB 3 hub which is then 915 * sent to the two Type C connectors. 916 * - The extra USB2 lines from the native Type C port are always 917 * setup as "peripheral" so that we can mux them over to one connector 918 * or the other if someone needs the connector configured as a gadget 919 * (but they only get USB2 speeds). 920 * 921 * All the hardware muxes would allow us to hook things up in different 922 * ways to some potential benefit for static configurations (you could 923 * achieve extra USB2 bandwidth by using two different ports for the 924 * two connectors or possibly even get USB3 peripheral mode), but in 925 * each case you end up forcing to disconnect/reconnect an in-use 926 * USB session in some cases depending on what you hotplug into the 927 * other connector. Thus hardcoding this as peripheral makes sense. 928 */ 929 dr_mode = "peripheral"; 930 931 /* 932 * We always need the high speed pins as 4-lanes DP in case someone 933 * hotplugs a DP peripheral. Thus limit this port to a max of high 934 * speed. 935 */ 936 maximum-speed = "high-speed"; 937 938 /* 939 * We don't need the usb3-phy since we run in highspeed mode always, so 940 * re-define these properties removing the superspeed USB PHY reference. 941 */ 942 phys = <&usb_1_hsphy>; 943 phy-names = "usb2-phy"; 944}; 945 946&usb_1_hsphy { 947 status = "okay"; 948 949 vdd-supply = <&vdda_usb1_ss_core>; 950 vdda-pll-supply = <&vdda_qusb_hs0_1p8>; 951 vdda-phy-dpdm-supply = <&vdda_qusb_hs0_3p1>; 952 953 qcom,imp-res-offset-value = <8>; 954 qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_21_6_MA>; 955 qcom,preemphasis-level = <QUSB2_V2_PREEMPHASIS_5_PERCENT>; 956 qcom,preemphasis-width = <QUSB2_V2_PREEMPHASIS_WIDTH_HALF_BIT>; 957}; 958 959&usb_2 { 960 status = "okay"; 961}; 962 963&usb_2_dwc3 { 964 /* We have this hooked up to a hub and we always use in host mode */ 965 dr_mode = "host"; 966}; 967 968&usb_2_hsphy { 969 status = "okay"; 970 971 vdd-supply = <&vdda_usb2_ss_core>; 972 vdda-pll-supply = <&vdda_qusb_hs0_1p8>; 973 vdda-phy-dpdm-supply = <&vdda_qusb_hs0_3p1>; 974 975 qcom,imp-res-offset-value = <8>; 976 qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_22_8_MA>; 977}; 978 979&usb_2_qmpphy { 980 status = "okay"; 981 982 vdda-phy-supply = <&vdda_usb2_ss_1p2>; 983 vdda-pll-supply = <&vdda_usb2_ss_core>; 984}; 985 986&wifi { 987 status = "okay"; 988 989 vdd-0.8-cx-mx-supply = <&src_pp800_l5a >; 990 vdd-1.8-xo-supply = <&pp1800_l7a_wcn3990>; 991 vdd-1.3-rfa-supply = <&src_pp1300_l17a>; 992 vdd-3.3-ch0-supply = <&pp3300_l25a_ch0_wcn3990>; 993}; 994 995/* PINCTRL - additions to nodes defined in sdm845.dtsi */ 996 997&qspi_cs0 { 998 pinconf { 999 pins = "gpio90"; 1000 bias-disable; 1001 }; 1002}; 1003 1004&qspi_clk { 1005 pinconf { 1006 pins = "gpio95"; 1007 bias-disable; 1008 }; 1009}; 1010 1011&qspi_data01 { 1012 pinconf { 1013 pins = "gpio91", "gpio92"; 1014 1015 /* High-Z when no transfers; nice to park the lines */ 1016 bias-pull-up; 1017 }; 1018}; 1019 1020&qup_i2c3_default { 1021 pinconf { 1022 pins = "gpio41", "gpio42"; 1023 drive-strength = <2>; 1024 1025 /* Has external pullup */ 1026 bias-disable; 1027 }; 1028}; 1029 1030&qup_i2c11_default { 1031 pinconf { 1032 pins = "gpio31", "gpio32"; 1033 drive-strength = <2>; 1034 1035 /* Has external pullup */ 1036 bias-disable; 1037 }; 1038}; 1039 1040&qup_i2c12_default { 1041 pinconf { 1042 pins = "gpio49", "gpio50"; 1043 drive-strength = <2>; 1044 1045 /* Has external pullup */ 1046 bias-disable; 1047 }; 1048}; 1049 1050&qup_i2c14_default { 1051 pinconf { 1052 pins = "gpio33", "gpio34"; 1053 drive-strength = <2>; 1054 1055 /* Has external pullup */ 1056 bias-disable; 1057 }; 1058}; 1059 1060&qup_spi0_default { 1061 pinconf { 1062 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 1063 drive-strength = <2>; 1064 bias-disable; 1065 }; 1066}; 1067 1068&qup_spi5_default { 1069 pinconf { 1070 pins = "gpio85", "gpio86", "gpio87", "gpio88"; 1071 drive-strength = <2>; 1072 bias-disable; 1073 }; 1074}; 1075 1076&qup_spi10_default { 1077 pinconf { 1078 pins = "gpio53", "gpio54", "gpio55", "gpio56"; 1079 drive-strength = <2>; 1080 bias-disable; 1081 }; 1082}; 1083 1084&qup_uart9_default { 1085 pinconf-tx { 1086 pins = "gpio4"; 1087 drive-strength = <2>; 1088 bias-disable; 1089 }; 1090 1091 pinconf-rx { 1092 pins = "gpio5"; 1093 drive-strength = <2>; 1094 bias-pull-up; 1095 }; 1096}; 1097 1098/* PINCTRL - board-specific pinctrl */ 1099&pm8005_gpio { 1100 gpio-line-names = "", 1101 "", 1102 "SLB", 1103 ""; 1104}; 1105 1106&pm8998_adc { 1107 adc-chan@4d { 1108 reg = <ADC5_AMUX_THM1_100K_PU>; 1109 label = "sdm_temp"; 1110 }; 1111 1112 adc-chan@4e { 1113 reg = <ADC5_AMUX_THM2_100K_PU>; 1114 label = "quiet_temp"; 1115 }; 1116 1117 adc-chan@4f { 1118 reg = <ADC5_AMUX_THM3_100K_PU>; 1119 label = "lte_temp_1"; 1120 }; 1121 1122 adc-chan@50 { 1123 reg = <ADC5_AMUX_THM4_100K_PU>; 1124 label = "lte_temp_2"; 1125 }; 1126 1127 adc-chan@51 { 1128 reg = <ADC5_AMUX_THM5_100K_PU>; 1129 label = "charger_temp"; 1130 }; 1131}; 1132 1133&pm8998_gpio { 1134 gpio-line-names = "", 1135 "", 1136 "SW_CTRL", 1137 "", 1138 "", 1139 "", 1140 "", 1141 "", 1142 "", 1143 "", 1144 "", 1145 "", 1146 "", 1147 "", 1148 "", 1149 "", 1150 "", 1151 "", 1152 "", 1153 "", 1154 "", 1155 "CFG_OPT1", 1156 "WCSS_PWR_REQ", 1157 "", 1158 "CFG_OPT2", 1159 "SLB"; 1160}; 1161 1162&tlmm { 1163 /* 1164 * pinctrl settings for pins that have no real owners. 1165 */ 1166 pinctrl-names = "default", "sleep"; 1167 pinctrl-0 = <&bios_flash_wp_r_l>, 1168 <&ap_suspend_l_deassert>; 1169 1170 pinctrl-1 = <&bios_flash_wp_r_l>, 1171 <&ap_suspend_l_assert>; 1172 1173 /* 1174 * Hogs prevent usermode from changing the value. A GPIO can be both 1175 * here and in the pinctrl section. 1176 */ 1177 ap-suspend-l-hog { 1178 gpio-hog; 1179 gpios = <126 GPIO_ACTIVE_LOW>; 1180 output-low; 1181 }; 1182 1183 ap_edp_bklten: ap-edp-bklten { 1184 pinmux { 1185 pins = "gpio37"; 1186 function = "gpio"; 1187 }; 1188 1189 pinconf { 1190 pins = "gpio37"; 1191 drive-strength = <2>; 1192 bias-disable; 1193 }; 1194 }; 1195 1196 bios_flash_wp_r_l: bios-flash-wp-r-l { 1197 pinmux { 1198 pins = "gpio128"; 1199 function = "gpio"; 1200 input-enable; 1201 }; 1202 1203 pinconf { 1204 pins = "gpio128"; 1205 bias-disable; 1206 }; 1207 }; 1208 1209 ec_ap_int_l: ec-ap-int-l { 1210 pinmux { 1211 pins = "gpio122"; 1212 function = "gpio"; 1213 input-enable; 1214 }; 1215 1216 pinconf { 1217 pins = "gpio122"; 1218 bias-pull-up; 1219 }; 1220 }; 1221 1222 edp_brij_en: edp-brij-en { 1223 pinmux { 1224 pins = "gpio102"; 1225 function = "gpio"; 1226 }; 1227 1228 pinconf { 1229 pins = "gpio102"; 1230 drive-strength = <2>; 1231 bias-disable; 1232 }; 1233 }; 1234 1235 edp_brij_irq: edp-brij-irq { 1236 pinmux { 1237 pins = "gpio10"; 1238 function = "gpio"; 1239 }; 1240 1241 pinconf { 1242 pins = "gpio10"; 1243 drive-strength = <2>; 1244 bias-pull-down; 1245 }; 1246 }; 1247 1248 en_pp3300_dx_edp: en-pp3300-dx-edp { 1249 pinmux { 1250 pins = "gpio43"; 1251 function = "gpio"; 1252 }; 1253 1254 pinconf { 1255 pins = "gpio43"; 1256 drive-strength = <2>; 1257 bias-disable; 1258 }; 1259 }; 1260 1261 h1_ap_int_odl: h1-ap-int-odl { 1262 pinmux { 1263 pins = "gpio129"; 1264 function = "gpio"; 1265 input-enable; 1266 }; 1267 1268 pinconf { 1269 pins = "gpio129"; 1270 bias-pull-up; 1271 }; 1272 }; 1273 1274 pen_eject_odl: pen-eject-odl { 1275 pinmux { 1276 pins = "gpio119"; 1277 function = "gpio"; 1278 bias-pull-up; 1279 }; 1280 }; 1281 1282 pen_irq_l: pen-irq-l { 1283 pinmux { 1284 pins = "gpio24"; 1285 function = "gpio"; 1286 }; 1287 1288 pinconf { 1289 pins = "gpio24"; 1290 1291 /* Has external pullup */ 1292 bias-disable; 1293 }; 1294 }; 1295 1296 pen_pdct_l: pen-pdct-l { 1297 pinmux { 1298 pins = "gpio63"; 1299 function = "gpio"; 1300 }; 1301 1302 pinconf { 1303 pins = "gpio63"; 1304 1305 /* Has external pullup */ 1306 bias-disable; 1307 }; 1308 }; 1309 1310 pen_rst_l: pen-rst-l { 1311 pinmux { 1312 pins = "gpio23"; 1313 function = "gpio"; 1314 }; 1315 1316 pinconf { 1317 pins = "gpio23"; 1318 bias-disable; 1319 drive-strength = <2>; 1320 1321 /* 1322 * The pen driver doesn't currently support 1323 * driving this reset line. By specifying 1324 * output-high here we're relying on the fact 1325 * that this pin has a default pulldown at boot 1326 * (which makes sure the pen was in reset if it 1327 * was powered) and then we set it high here to 1328 * take it out of reset. Better would be if the 1329 * pen driver could control this and we could 1330 * remove "output-high" here. 1331 */ 1332 output-high; 1333 }; 1334 }; 1335 1336 sdc2_clk: sdc2-clk { 1337 pinconf { 1338 pins = "sdc2_clk"; 1339 bias-disable; 1340 1341 /* 1342 * It seems that mmc_test reports errors if drive 1343 * strength is not 16. 1344 */ 1345 drive-strength = <16>; 1346 }; 1347 }; 1348 1349 sdc2_cmd: sdc2-cmd { 1350 pinconf { 1351 pins = "sdc2_cmd"; 1352 bias-pull-up; 1353 drive-strength = <16>; 1354 }; 1355 }; 1356 1357 sdc2_data: sdc2-data { 1358 pinconf { 1359 pins = "sdc2_data"; 1360 bias-pull-up; 1361 drive-strength = <16>; 1362 }; 1363 }; 1364 1365 sd_cd_odl: sd-cd-odl { 1366 pinmux { 1367 pins = "gpio44"; 1368 function = "gpio"; 1369 }; 1370 1371 pinconf { 1372 pins = "gpio44"; 1373 bias-pull-up; 1374 }; 1375 }; 1376 1377 ts_int_l: ts-int-l { 1378 pinmux { 1379 pins = "gpio125"; 1380 function = "gpio"; 1381 }; 1382 1383 pinconf { 1384 pins = "gpio125"; 1385 bias-pull-up; 1386 }; 1387 }; 1388 1389 ts_reset_l: ts-reset-l { 1390 pinmux { 1391 pins = "gpio118"; 1392 function = "gpio"; 1393 }; 1394 1395 pinconf { 1396 pins = "gpio118"; 1397 bias-disable; 1398 drive-strength = <2>; 1399 }; 1400 }; 1401 1402 ap_suspend_l_assert: ap_suspend_l_assert { 1403 config { 1404 pins = "gpio126"; 1405 function = "gpio"; 1406 bias-disable; 1407 drive-strength = <2>; 1408 output-low; 1409 }; 1410 }; 1411 1412 ap_suspend_l_deassert: ap_suspend_l_deassert { 1413 config { 1414 pins = "gpio126"; 1415 function = "gpio"; 1416 bias-disable; 1417 drive-strength = <2>; 1418 output-high; 1419 }; 1420 }; 1421}; 1422 1423&venus { 1424 status = "okay"; 1425 1426 video-firmware { 1427 iommus = <&apps_smmu 0x10b2 0x0>; 1428 }; 1429}; 1430