1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Google Cheza device tree source (common between revisions)
4 *
5 * Copyright 2018 Google LLC.
6 */
7
8#include <dt-bindings/input/input.h>
9#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
10#include "sdm845.dtsi"
11
12/* PMICs depend on spmi_bus label and so must come after SoC */
13#include "pm8005.dtsi"
14#include "pm8998.dtsi"
15
16/ {
17	aliases {
18		bluetooth0 = &bluetooth;
19		serial1 = &uart6;
20		serial0 = &uart9;
21		wifi0 = &wifi;
22	};
23
24	chosen {
25		stdout-path = "serial0:115200n8";
26	};
27
28	backlight: backlight {
29		compatible = "pwm-backlight";
30		pwms = <&cros_ec_pwm 0>;
31		enable-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>;
32		power-supply = <&ppvar_sys>;
33		pinctrl-names = "default";
34		pinctrl-0 = <&ap_edp_bklten>;
35	};
36
37	/* FIXED REGULATORS - parents above children */
38
39	/* This is the top level supply and variable voltage */
40	ppvar_sys: ppvar-sys-regulator {
41		compatible = "regulator-fixed";
42		regulator-name = "ppvar_sys";
43		regulator-always-on;
44		regulator-boot-on;
45	};
46
47	/* This divides ppvar_sys by 2, so voltage is variable */
48	src_vph_pwr: src-vph-pwr-regulator {
49		compatible = "regulator-fixed";
50		regulator-name = "src_vph_pwr";
51
52		/* EC turns on with switchcap_on_l; always on for AP */
53		regulator-always-on;
54		regulator-boot-on;
55
56		vin-supply = <&ppvar_sys>;
57	};
58
59	pp5000_a: pp5000-a-regulator {
60		compatible = "regulator-fixed";
61		regulator-name = "pp5000_a";
62
63		/* EC turns on with en_pp5000_a; always on for AP */
64		regulator-always-on;
65		regulator-boot-on;
66		regulator-min-microvolt = <5000000>;
67		regulator-max-microvolt = <5000000>;
68
69		vin-supply = <&ppvar_sys>;
70	};
71
72	src_vreg_bob: src-vreg-bob-regulator {
73		compatible = "regulator-fixed";
74		regulator-name = "src_vreg_bob";
75
76		/* EC turns on with vbob_en; always on for AP */
77		regulator-always-on;
78		regulator-boot-on;
79		regulator-min-microvolt = <3600000>;
80		regulator-max-microvolt = <3600000>;
81
82		vin-supply = <&ppvar_sys>;
83	};
84
85	pp3300_dx_edp: pp3300-dx-edp-regulator {
86		compatible = "regulator-fixed";
87		regulator-name = "pp3300_dx_edp";
88
89		regulator-min-microvolt = <3300000>;
90		regulator-max-microvolt = <3300000>;
91
92		gpio = <&tlmm 43 GPIO_ACTIVE_HIGH>;
93		enable-active-high;
94		pinctrl-names = "default";
95		pinctrl-0 = <&en_pp3300_dx_edp>;
96	};
97
98	/*
99	 * Apparently RPMh does not provide support for PM8998 S4 because it
100	 * is always-on; model it as a fixed regulator.
101	 */
102	src_pp1800_s4a: pm8998-smps4 {
103		compatible = "regulator-fixed";
104		regulator-name = "src_pp1800_s4a";
105
106		regulator-min-microvolt = <1800000>;
107		regulator-max-microvolt = <1800000>;
108
109		regulator-always-on;
110		regulator-boot-on;
111
112		vin-supply = <&src_vph_pwr>;
113	};
114
115	/* BOARD-SPECIFIC TOP LEVEL NODES */
116
117	gpio-keys {
118		compatible = "gpio-keys";
119		pinctrl-names = "default";
120		pinctrl-0 = <&pen_eject_odl>;
121
122		switch-pen-insert {
123			label = "Pen Insert";
124			/* Insert = low, eject = high */
125			gpios = <&tlmm 119 GPIO_ACTIVE_LOW>;
126			linux,code = <SW_PEN_INSERTED>;
127			linux,input-type = <EV_SW>;
128			wakeup-source;
129		};
130	};
131
132	panel: panel {
133		compatible = "innolux,p120zdg-bf1";
134		power-supply = <&pp3300_dx_edp>;
135		backlight = <&backlight>;
136		no-hpd;
137
138		panel_in: port {
139			panel_in_edp: endpoint {
140				remote-endpoint = <&sn65dsi86_out>;
141			};
142		};
143	};
144};
145
146&cpufreq_hw {
147	/delete-property/ interrupts-extended; /* reference to lmh_cluster[01] */
148};
149
150&psci {
151	/delete-node/ power-domain-cpu0;
152	/delete-node/ power-domain-cpu1;
153	/delete-node/ power-domain-cpu2;
154	/delete-node/ power-domain-cpu3;
155	/delete-node/ power-domain-cpu4;
156	/delete-node/ power-domain-cpu5;
157	/delete-node/ power-domain-cpu6;
158	/delete-node/ power-domain-cpu7;
159	/delete-node/ power-domain-cluster;
160};
161
162&cpus {
163	/delete-node/ domain-idle-states;
164};
165
166&cpu_idle_states {
167	LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
168		compatible = "arm,idle-state";
169		idle-state-name = "little-power-down";
170		arm,psci-suspend-param = <0x40000003>;
171		entry-latency-us = <350>;
172		exit-latency-us = <461>;
173		min-residency-us = <1890>;
174		local-timer-stop;
175	};
176
177	LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
178		compatible = "arm,idle-state";
179		idle-state-name = "little-rail-power-down";
180		arm,psci-suspend-param = <0x40000004>;
181		entry-latency-us = <360>;
182		exit-latency-us = <531>;
183		min-residency-us = <3934>;
184		local-timer-stop;
185	};
186
187	BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
188		compatible = "arm,idle-state";
189		idle-state-name = "big-power-down";
190		arm,psci-suspend-param = <0x40000003>;
191		entry-latency-us = <264>;
192		exit-latency-us = <621>;
193		min-residency-us = <952>;
194		local-timer-stop;
195	};
196
197	BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
198		compatible = "arm,idle-state";
199		idle-state-name = "big-rail-power-down";
200		arm,psci-suspend-param = <0x40000004>;
201		entry-latency-us = <702>;
202		exit-latency-us = <1061>;
203		min-residency-us = <4488>;
204		local-timer-stop;
205	};
206
207	CLUSTER_SLEEP_0: cluster-sleep-0 {
208		compatible = "arm,idle-state";
209		idle-state-name = "cluster-power-down";
210		arm,psci-suspend-param = <0x400000F4>;
211		entry-latency-us = <3263>;
212		exit-latency-us = <6562>;
213		min-residency-us = <9987>;
214		local-timer-stop;
215	};
216};
217
218&CPU0 {
219	/delete-property/ power-domains;
220	/delete-property/ power-domain-names;
221	cpu-idle-states = <&LITTLE_CPU_SLEEP_0
222			   &LITTLE_CPU_SLEEP_1
223			   &CLUSTER_SLEEP_0>;
224};
225
226&CPU1 {
227	/delete-property/ power-domains;
228	/delete-property/ power-domain-names;
229	cpu-idle-states = <&LITTLE_CPU_SLEEP_0
230			   &LITTLE_CPU_SLEEP_1
231			   &CLUSTER_SLEEP_0>;
232};
233
234&CPU2 {
235	/delete-property/ power-domains;
236	/delete-property/ power-domain-names;
237	cpu-idle-states = <&LITTLE_CPU_SLEEP_0
238			   &LITTLE_CPU_SLEEP_1
239			   &CLUSTER_SLEEP_0>;
240};
241
242&CPU3 {
243	/delete-property/ power-domains;
244	/delete-property/ power-domain-names;
245	cpu-idle-states = <&LITTLE_CPU_SLEEP_0
246			   &LITTLE_CPU_SLEEP_1
247			   &CLUSTER_SLEEP_0>;
248};
249
250&CPU4 {
251	/delete-property/ power-domains;
252	/delete-property/ power-domain-names;
253	cpu-idle-states = <&BIG_CPU_SLEEP_0
254			   &BIG_CPU_SLEEP_1
255			   &CLUSTER_SLEEP_0>;
256};
257
258&CPU5 {
259	/delete-property/ power-domains;
260	/delete-property/ power-domain-names;
261	cpu-idle-states = <&BIG_CPU_SLEEP_0
262			   &BIG_CPU_SLEEP_1
263			   &CLUSTER_SLEEP_0>;
264};
265
266&CPU6 {
267	/delete-property/ power-domains;
268	/delete-property/ power-domain-names;
269	cpu-idle-states = <&BIG_CPU_SLEEP_0
270			   &BIG_CPU_SLEEP_1
271			   &CLUSTER_SLEEP_0>;
272};
273
274&CPU7 {
275	/delete-property/ power-domains;
276	/delete-property/ power-domain-names;
277	cpu-idle-states = <&BIG_CPU_SLEEP_0
278			   &BIG_CPU_SLEEP_1
279			   &CLUSTER_SLEEP_0>;
280};
281
282&lmh_cluster0 {
283	status = "disabled";
284};
285
286&lmh_cluster1 {
287	status = "disabled";
288};
289
290/*
291 * Reserved memory changes
292 *
293 * Putting this all together (out of order with the rest of the file) to keep
294 * all modifications to the memory map (from sdm845.dtsi) in one place.
295 */
296
297/*
298 * Our mpss_region is 8MB bigger than the default one and that conflicts
299 * with venus_mem and cdsp_mem.
300 *
301 * For venus_mem we'll delete and re-create at a different address.
302 *
303 * cdsp_mem isn't used on cheza right now so we won't bother re-creating it; but
304 * that also means we need to delete cdsp_pas.
305 */
306/delete-node/ &venus_mem;
307/delete-node/ &cdsp_mem;
308/delete-node/ &cdsp_pas;
309/delete-node/ &gpu_mem;
310
311/* Increase the size from 120 MB to 128 MB */
312&mpss_region {
313	reg = <0 0x8e000000 0 0x8000000>;
314};
315
316/* Increase the size from 2MB to 8MB */
317&rmtfs_mem {
318	reg = <0 0x88f00000 0 0x800000>;
319};
320
321/ {
322	reserved-memory {
323		venus_mem: memory@96000000 {
324			reg = <0 0x96000000 0 0x500000>;
325			no-map;
326		};
327	};
328};
329
330&qspi {
331	status = "okay";
332	pinctrl-names = "default", "sleep";
333	pinctrl-0 = <&qspi_clk>, <&qspi_cs0>, <&qspi_data0>, <&qspi_data1>;
334	pinctrl-1 = <&qspi_sleep>;
335
336	flash@0 {
337		compatible = "jedec,spi-nor";
338		reg = <0>;
339
340		/*
341		 * In theory chip supports up to 104 MHz and controller up
342		 * to 80 MHz, but above 25 MHz wasn't reliable so we'll use
343		 * that for now.  b:117440651
344		 */
345		spi-max-frequency = <25000000>;
346		spi-tx-bus-width = <2>;
347		spi-rx-bus-width = <2>;
348	};
349};
350
351
352&apps_rsc {
353	/delete-property/ power-domains;
354
355	regulators-0 {
356		compatible = "qcom,pm8998-rpmh-regulators";
357		qcom,pmic-id = "a";
358
359		vdd-s1-supply = <&src_vph_pwr>;
360		vdd-s2-supply = <&src_vph_pwr>;
361		vdd-s3-supply = <&src_vph_pwr>;
362		vdd-s4-supply = <&src_vph_pwr>;
363		vdd-s5-supply = <&src_vph_pwr>;
364		vdd-s6-supply = <&src_vph_pwr>;
365		vdd-s7-supply = <&src_vph_pwr>;
366		vdd-s8-supply = <&src_vph_pwr>;
367		vdd-s9-supply = <&src_vph_pwr>;
368		vdd-s10-supply = <&src_vph_pwr>;
369		vdd-s11-supply = <&src_vph_pwr>;
370		vdd-s12-supply = <&src_vph_pwr>;
371		vdd-s13-supply = <&src_vph_pwr>;
372		vdd-l1-l27-supply = <&src_pp1025_s7a>;
373		vdd-l2-l8-l17-supply = <&src_pp1350_s3a>;
374		vdd-l3-l11-supply = <&src_pp1025_s7a>;
375		vdd-l4-l5-supply = <&src_pp1025_s7a>;
376		vdd-l6-supply = <&src_vph_pwr>;
377		vdd-l7-l12-l14-l15-supply = <&src_pp2040_s5a>;
378		vdd-l9-supply = <&src_pp2040_s5a>;
379		vdd-l10-l23-l25-supply = <&src_vreg_bob>;
380		vdd-l13-l19-l21-supply = <&src_vreg_bob>;
381		vdd-l16-l28-supply = <&src_vreg_bob>;
382		vdd-l18-l22-supply = <&src_vreg_bob>;
383		vdd-l20-l24-supply = <&src_vreg_bob>;
384		vdd-l26-supply = <&src_pp1350_s3a>;
385		vin-lvs-1-2-supply = <&src_pp1800_s4a>;
386
387		src_pp1125_s2a: smps2 {
388			regulator-min-microvolt = <1100000>;
389			regulator-max-microvolt = <1100000>;
390		};
391
392		src_pp1350_s3a: smps3 {
393			regulator-min-microvolt = <1352000>;
394			regulator-max-microvolt = <1352000>;
395		};
396
397		src_pp2040_s5a: smps5 {
398			regulator-min-microvolt = <1904000>;
399			regulator-max-microvolt = <2040000>;
400		};
401
402		src_pp1025_s7a: smps7 {
403			regulator-min-microvolt = <900000>;
404			regulator-max-microvolt = <1028000>;
405		};
406
407		vdd_qusb_hs0:
408		vdda_hp_pcie_core:
409		vdda_mipi_csi0_0p9:
410		vdda_mipi_csi1_0p9:
411		vdda_mipi_csi2_0p9:
412		vdda_mipi_dsi0_pll:
413		vdda_mipi_dsi1_pll:
414		vdda_qlink_lv:
415		vdda_qlink_lv_ck:
416		vdda_qrefs_0p875:
417		vdda_pcie_core:
418		vdda_pll_cc_ebi01:
419		vdda_pll_cc_ebi23:
420		vdda_sp_sensor:
421		vdda_ufs1_core:
422		vdda_ufs2_core:
423		vdda_usb1_ss_core:
424		vdda_usb2_ss_core:
425		src_pp875_l1a: ldo1 {
426			regulator-min-microvolt = <880000>;
427			regulator-max-microvolt = <880000>;
428			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
429		};
430
431		vddpx_10:
432		src_pp1200_l2a: ldo2 {
433			regulator-min-microvolt = <1200000>;
434			regulator-max-microvolt = <1200000>;
435			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
436
437			/* TODO: why??? */
438			regulator-always-on;
439		};
440
441		pp1000_l3a_sdr845: ldo3 {
442			regulator-min-microvolt = <1000000>;
443			regulator-max-microvolt = <1000000>;
444			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
445		};
446
447		vdd_wcss_cx:
448		vdd_wcss_mx:
449		vdda_wcss_pll:
450		src_pp800_l5a: ldo5 {
451			regulator-min-microvolt = <800000>;
452			regulator-max-microvolt = <800000>;
453			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
454		};
455
456		vddpx_13:
457		src_pp1800_l6a: ldo6 {
458			regulator-min-microvolt = <1856000>;
459			regulator-max-microvolt = <1856000>;
460			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
461		};
462
463		pp1800_l7a_wcn3990: ldo7 {
464			regulator-min-microvolt = <1800000>;
465			regulator-max-microvolt = <1800000>;
466			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
467		};
468
469		src_pp1200_l8a: ldo8 {
470			regulator-min-microvolt = <1200000>;
471			regulator-max-microvolt = <1248000>;
472			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
473		};
474
475		pp1800_dx_pen:
476		src_pp1800_l9a: ldo9 {
477			regulator-min-microvolt = <1800000>;
478			regulator-max-microvolt = <1800000>;
479			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
480		};
481
482		src_pp1800_l10a: ldo10 {
483			regulator-min-microvolt = <1800000>;
484			regulator-max-microvolt = <1800000>;
485			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
486		};
487
488		pp1000_l11a_sdr845: ldo11 {
489			regulator-min-microvolt = <1000000>;
490			regulator-max-microvolt = <1048000>;
491			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
492		};
493
494		vdd_qfprom:
495		vdd_qfprom_sp:
496		vdda_apc1_cs_1p8:
497		vdda_gfx_cs_1p8:
498		vdda_qrefs_1p8:
499		vdda_qusb_hs0_1p8:
500		vddpx_11:
501		src_pp1800_l12a: ldo12 {
502			regulator-min-microvolt = <1800000>;
503			regulator-max-microvolt = <1800000>;
504			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
505		};
506
507		vddpx_2:
508		src_pp2950_l13a: ldo13 {
509			regulator-min-microvolt = <1800000>;
510			regulator-max-microvolt = <2960000>;
511			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
512		};
513
514		src_pp1800_l14a: ldo14 {
515			regulator-min-microvolt = <1800000>;
516			regulator-max-microvolt = <1800000>;
517			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
518		};
519
520		src_pp1800_l15a: ldo15 {
521			regulator-min-microvolt = <1800000>;
522			regulator-max-microvolt = <1800000>;
523			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
524		};
525
526		pp2700_l16a: ldo16 {
527			regulator-min-microvolt = <2704000>;
528			regulator-max-microvolt = <2704000>;
529			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
530		};
531
532		src_pp1300_l17a: ldo17 {
533			regulator-min-microvolt = <1304000>;
534			regulator-max-microvolt = <1304000>;
535			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
536		};
537
538		pp2700_l18a: ldo18 {
539			regulator-min-microvolt = <2704000>;
540			regulator-max-microvolt = <2960000>;
541			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
542		};
543
544		/*
545		 * NOTE: this rail should have been called
546		 * src_pp3300_l19a in the schematic
547		 */
548		src_pp3000_l19a: ldo19 {
549			regulator-min-microvolt = <3304000>;
550			regulator-max-microvolt = <3304000>;
551
552			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
553		};
554
555		src_pp2950_l20a: ldo20 {
556			regulator-min-microvolt = <2704000>;
557			regulator-max-microvolt = <2960000>;
558			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
559		};
560
561		src_pp2950_l21a: ldo21 {
562			regulator-min-microvolt = <2704000>;
563			regulator-max-microvolt = <2960000>;
564			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
565		};
566
567		pp3300_hub:
568		src_pp3300_l22a: ldo22 {
569			regulator-min-microvolt = <3304000>;
570			regulator-max-microvolt = <3304000>;
571			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
572			/*
573			 * HACK: Should add a usb hub node and driver
574			 * to turn this on and off at suspend/resume time
575			 */
576			regulator-boot-on;
577			regulator-always-on;
578		};
579
580		pp3300_l23a_ch1_wcn3990: ldo23 {
581			regulator-min-microvolt = <3000000>;
582			regulator-max-microvolt = <3312000>;
583			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
584		};
585
586		vdda_qusb_hs0_3p1:
587		src_pp3075_l24a: ldo24 {
588			regulator-min-microvolt = <3088000>;
589			regulator-max-microvolt = <3088000>;
590			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
591		};
592
593		pp3300_l25a_ch0_wcn3990: ldo25 {
594			regulator-min-microvolt = <3304000>;
595			regulator-max-microvolt = <3304000>;
596			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
597		};
598
599		pp1200_hub:
600		vdda_hp_pcie_1p2:
601		vdda_hv_ebi0:
602		vdda_hv_ebi1:
603		vdda_hv_ebi2:
604		vdda_hv_ebi3:
605		vdda_mipi_csi_1p25:
606		vdda_mipi_dsi0_1p2:
607		vdda_mipi_dsi1_1p2:
608		vdda_pcie_1p2:
609		vdda_ufs1_1p2:
610		vdda_ufs2_1p2:
611		vdda_usb1_ss_1p2:
612		vdda_usb2_ss_1p2:
613		src_pp1200_l26a: ldo26 {
614			regulator-min-microvolt = <1200000>;
615			regulator-max-microvolt = <1200000>;
616			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
617		};
618
619		pp3300_dx_pen:
620		src_pp3300_l28a: ldo28 {
621			regulator-min-microvolt = <3304000>;
622			regulator-max-microvolt = <3304000>;
623			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
624		};
625
626		src_pp1800_lvs1: lvs1 {
627			regulator-min-microvolt = <1800000>;
628			regulator-max-microvolt = <1800000>;
629		};
630
631		src_pp1800_lvs2: lvs2 {
632			regulator-min-microvolt = <1800000>;
633			regulator-max-microvolt = <1800000>;
634		};
635	};
636
637	regulators-1 {
638		compatible = "qcom,pm8005-rpmh-regulators";
639		qcom,pmic-id = "c";
640
641		vdd-s1-supply = <&src_vph_pwr>;
642		vdd-s2-supply = <&src_vph_pwr>;
643		vdd-s3-supply = <&src_vph_pwr>;
644		vdd-s4-supply = <&src_vph_pwr>;
645
646		src_pp600_s3c: smps3 {
647			regulator-min-microvolt = <600000>;
648			regulator-max-microvolt = <600000>;
649		};
650	};
651};
652
653edp_brij_i2c: &i2c3 {
654	status = "okay";
655	clock-frequency = <400000>;
656
657	sn65dsi86_bridge: bridge@2d {
658		compatible = "ti,sn65dsi86";
659		reg = <0x2d>;
660		pinctrl-names = "default";
661		pinctrl-0 = <&edp_brij_en &edp_brij_irq>;
662
663		interrupt-parent = <&tlmm>;
664		interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
665
666		enable-gpios = <&tlmm 102 GPIO_ACTIVE_HIGH>;
667
668		vpll-supply = <&src_pp1800_s4a>;
669		vccio-supply = <&src_pp1800_s4a>;
670		vcca-supply = <&src_pp1200_l2a>;
671		vcc-supply = <&src_pp1200_l2a>;
672
673		clocks = <&rpmhcc RPMH_LN_BB_CLK2>;
674		clock-names = "refclk";
675
676		no-hpd;
677
678		ports {
679			#address-cells = <1>;
680			#size-cells = <0>;
681
682			port@0 {
683				reg = <0>;
684				sn65dsi86_in: endpoint {
685					remote-endpoint = <&mdss_dsi0_out>;
686				};
687			};
688
689			port@1 {
690				reg = <1>;
691				sn65dsi86_out: endpoint {
692					remote-endpoint = <&panel_in_edp>;
693				};
694			};
695		};
696	};
697};
698
699ap_pen_1v8: &i2c11 {
700	status = "okay";
701	clock-frequency = <400000>;
702
703	digitizer@9 {
704		compatible = "wacom,w9013", "hid-over-i2c";
705		reg = <0x9>;
706		pinctrl-names = "default";
707		pinctrl-0 = <&pen_irq_l>, <&pen_pdct_l>, <&pen_rst_l>;
708
709		vdd-supply = <&pp3300_dx_pen>;
710		vddl-supply = <&pp1800_dx_pen>;
711		post-power-on-delay-ms = <100>;
712
713		interrupt-parent = <&tlmm>;
714		interrupts = <24 IRQ_TYPE_LEVEL_LOW>;
715
716		hid-descr-addr = <0x1>;
717	};
718};
719
720amp_i2c: &i2c12 {
721	status = "okay";
722	clock-frequency = <400000>;
723};
724
725ap_ts_i2c: &i2c14 {
726	status = "okay";
727	clock-frequency = <400000>;
728
729	touchscreen@10 {
730		compatible = "elan,ekth3500";
731		reg = <0x10>;
732		pinctrl-names = "default";
733		pinctrl-0 = <&ts_int_l &ts_reset_l>;
734
735		interrupt-parent = <&tlmm>;
736		interrupts = <125 IRQ_TYPE_LEVEL_LOW>;
737
738		vcc33-supply = <&src_pp3300_l28a>;
739
740		reset-gpios = <&tlmm 118 GPIO_ACTIVE_LOW>;
741	};
742};
743
744&gmu {
745	status = "okay";
746};
747
748&gpu {
749	status = "okay";
750};
751
752&ipa {
753	qcom,gsi-loader = "modem";
754	status = "okay";
755};
756
757&lpasscc {
758	status = "okay";
759};
760
761&mdss {
762	status = "okay";
763};
764
765&mdss_dsi0 {
766	status = "okay";
767	vdda-supply = <&vdda_mipi_dsi0_1p2>;
768
769	ports {
770		port@1 {
771			endpoint {
772				remote-endpoint = <&sn65dsi86_in>;
773				data-lanes = <0 1 2 3>;
774			};
775		};
776	};
777};
778
779&mdss_dsi0_phy {
780	status = "okay";
781	vdds-supply = <&vdda_mipi_dsi0_pll>;
782};
783
784/*
785 * Cheza fw does not properly program the GPU aperture to allow the
786 * GPU to update the SMMU pagetables for context switches.  Work
787 * around this by dropping the "qcom,adreno-smmu" compat string.
788 */
789&adreno_smmu {
790	compatible = "qcom,sdm845-smmu-v2", "qcom,smmu-v2";
791};
792
793&mss_pil {
794	status = "okay";
795
796	iommus = <&apps_smmu 0x781 0x0>,
797		 <&apps_smmu 0x724 0x3>;
798};
799
800&pm8998_pwrkey {
801	status = "disabled";
802};
803
804&qupv3_id_0 {
805	status = "okay";
806	iommus = <&apps_smmu 0x0 0x3>;
807};
808
809&qupv3_id_1 {
810	status = "okay";
811	iommus = <&apps_smmu 0x6c0 0x3>;
812};
813
814&sdhc_2 {
815	status = "okay";
816
817	pinctrl-names = "default";
818	pinctrl-0 = <&sdc2_clk &sdc2_cmd &sdc2_data &sd_cd_odl>;
819
820	vmmc-supply = <&src_pp2950_l21a>;
821	vqmmc-supply = <&vddpx_2>;
822
823	cd-gpios = <&tlmm 44 GPIO_ACTIVE_LOW>;
824};
825
826&spi0 {
827	status = "okay";
828};
829
830&spi5 {
831	status = "okay";
832
833	tpm@0 {
834		compatible = "google,cr50";
835		reg = <0>;
836		pinctrl-names = "default";
837		pinctrl-0 = <&h1_ap_int_odl>;
838		spi-max-frequency = <800000>;
839		interrupt-parent = <&tlmm>;
840		interrupts = <129 IRQ_TYPE_EDGE_RISING>;
841	};
842};
843
844&spi10 {
845	status = "okay";
846
847	cros_ec: ec@0 {
848		compatible = "google,cros-ec-spi";
849		reg = <0>;
850		interrupt-parent = <&tlmm>;
851		interrupts = <122 IRQ_TYPE_LEVEL_LOW>;
852		pinctrl-names = "default";
853		pinctrl-0 = <&ec_ap_int_l>;
854		spi-max-frequency = <3000000>;
855
856		cros_ec_pwm: pwm {
857			compatible = "google,cros-ec-pwm";
858			#pwm-cells = <1>;
859		};
860
861		i2c_tunnel: i2c-tunnel {
862			compatible = "google,cros-ec-i2c-tunnel";
863			google,remote-bus = <0>;
864			#address-cells = <1>;
865			#size-cells = <0>;
866		};
867	};
868};
869
870#include <arm/cros-ec-keyboard.dtsi>
871#include <arm/cros-ec-sbs.dtsi>
872
873&uart6 {
874	status = "okay";
875
876	pinctrl-0 = <&qup_uart6_4pin>;
877
878	bluetooth: bluetooth {
879		compatible = "qcom,wcn3990-bt";
880		vddio-supply = <&src_pp1800_s4a>;
881		vddxo-supply = <&pp1800_l7a_wcn3990>;
882		vddrf-supply = <&src_pp1300_l17a>;
883		vddch0-supply = <&pp3300_l25a_ch0_wcn3990>;
884		max-speed = <3200000>;
885	};
886};
887
888&uart9 {
889	status = "okay";
890};
891
892&ufs_mem_hc {
893	status = "okay";
894
895	reset-gpios = <&tlmm 150 GPIO_ACTIVE_LOW>;
896
897	vcc-supply = <&src_pp2950_l20a>;
898	vcc-max-microamp = <600000>;
899};
900
901&ufs_mem_phy {
902	status = "okay";
903
904	vdda-phy-supply = <&vdda_ufs1_core>;
905	vdda-pll-supply = <&vdda_ufs1_1p2>;
906};
907
908&usb_1 {
909	status = "okay";
910
911	/* We'll use this as USB 2.0 only */
912	qcom,select-utmi-as-pipe-clk;
913};
914
915&usb_1_dwc3 {
916	/*
917	 * The hardware design intends this port to be hooked up in peripheral
918	 * mode, so we'll hardcode it here.  Some details:
919	 * - SDM845 expects only a single Type C connector so it has only one
920	 *   native Type C port but cheza has two Type C connectors.
921	 * - The only source of DP is the single native Type C port.
922	 * - On cheza we want to be able to hook DP up to _either_ of the
923	 *   two Type C connectors and want to be able to achieve 4 lanes of DP.
924	 * - When you configure a Type C port for 4 lanes of DP you lose USB3.
925	 * - In order to make everything work, the native Type C port is always
926	 *   configured as 4-lanes DP so it's always available.
927	 * - The extra USB3 port on SDM845 goes to a USB 3 hub which is then
928	 *   sent to the two Type C connectors.
929	 * - The extra USB2 lines from the native Type C port are always
930	 *   setup as "peripheral" so that we can mux them over to one connector
931	 *   or the other if someone needs the connector configured as a gadget
932	 *   (but they only get USB2 speeds).
933	 *
934	 * All the hardware muxes would allow us to hook things up in different
935	 * ways to some potential benefit for static configurations (you could
936	 * achieve extra USB2 bandwidth by using two different ports for the
937	 * two connectors or possibly even get USB3 peripheral mode), but in
938	 * each case you end up forcing to disconnect/reconnect an in-use
939	 * USB session in some cases depending on what you hotplug into the
940	 * other connector.  Thus hardcoding this as peripheral makes sense.
941	 */
942	dr_mode = "peripheral";
943
944	/*
945	 * We always need the high speed pins as 4-lanes DP in case someone
946	 * hotplugs a DP peripheral.  Thus limit this port to a max of high
947	 * speed.
948	 */
949	maximum-speed = "high-speed";
950
951	/*
952	 * We don't need the usb3-phy since we run in highspeed mode always, so
953	 * re-define these properties removing the superspeed USB PHY reference.
954	 */
955	phys = <&usb_1_hsphy>;
956	phy-names = "usb2-phy";
957};
958
959&usb_1_hsphy {
960	status = "okay";
961
962	vdd-supply = <&vdda_usb1_ss_core>;
963	vdda-pll-supply = <&vdda_qusb_hs0_1p8>;
964	vdda-phy-dpdm-supply = <&vdda_qusb_hs0_3p1>;
965
966	qcom,imp-res-offset-value = <8>;
967	qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_21_6_MA>;
968	qcom,preemphasis-level = <QUSB2_V2_PREEMPHASIS_5_PERCENT>;
969	qcom,preemphasis-width = <QUSB2_V2_PREEMPHASIS_WIDTH_HALF_BIT>;
970};
971
972&usb_2 {
973	status = "okay";
974};
975
976&usb_2_dwc3 {
977	/* We have this hooked up to a hub and we always use in host mode */
978	dr_mode = "host";
979};
980
981&usb_2_hsphy {
982	status = "okay";
983
984	vdd-supply = <&vdda_usb2_ss_core>;
985	vdda-pll-supply = <&vdda_qusb_hs0_1p8>;
986	vdda-phy-dpdm-supply = <&vdda_qusb_hs0_3p1>;
987
988	qcom,imp-res-offset-value = <8>;
989	qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_22_8_MA>;
990};
991
992&usb_2_qmpphy {
993	status = "okay";
994
995	vdda-phy-supply = <&vdda_usb2_ss_1p2>;
996	vdda-pll-supply = <&vdda_usb2_ss_core>;
997};
998
999&wifi {
1000	status = "okay";
1001
1002	vdd-0.8-cx-mx-supply = <&src_pp800_l5a >;
1003	vdd-1.8-xo-supply = <&pp1800_l7a_wcn3990>;
1004	vdd-1.3-rfa-supply = <&src_pp1300_l17a>;
1005	vdd-3.3-ch0-supply = <&pp3300_l25a_ch0_wcn3990>;
1006};
1007
1008/* PINCTRL - additions to nodes defined in sdm845.dtsi */
1009
1010&qspi_cs0 {
1011	bias-disable;		/* External pullup */
1012};
1013
1014&qspi_clk {
1015	bias-disable;		/* Rely on Cr50 internal pulldown */
1016};
1017
1018&qspi_data0 {
1019	bias-disable;		/* Rely on Cr50 internal pulldown */
1020};
1021
1022&qspi_data1 {
1023	bias-pull-down;
1024};
1025
1026&qup_i2c3_default {
1027	drive-strength = <2>;
1028
1029	/* Has external pullup */
1030	bias-disable;
1031};
1032
1033&qup_i2c11_default {
1034	drive-strength = <2>;
1035
1036	/* Has external pullup */
1037	bias-disable;
1038};
1039
1040&qup_i2c12_default {
1041	drive-strength = <2>;
1042
1043	/* Has external pullup */
1044	bias-disable;
1045};
1046
1047&qup_i2c14_default {
1048	drive-strength = <2>;
1049
1050	/* Has external pullup */
1051	bias-disable;
1052};
1053
1054&qup_spi0_default {
1055	drive-strength = <2>;
1056	bias-disable;
1057};
1058
1059&qup_spi5_default {
1060	drive-strength = <2>;
1061	bias-disable;
1062};
1063
1064&qup_spi10_default {
1065	drive-strength = <2>;
1066	bias-disable;
1067};
1068
1069&qup_uart9_rx {
1070	drive-strength = <2>;
1071	bias-pull-up;
1072};
1073
1074&qup_uart9_tx {
1075	drive-strength = <2>;
1076	bias-disable;
1077};
1078
1079/* PINCTRL - board-specific pinctrl */
1080&pm8005_gpios {
1081	gpio-line-names = "",
1082			  "",
1083			  "SLB",
1084			  "";
1085};
1086
1087&pm8998_adc {
1088	channel@4d {
1089		reg = <ADC5_AMUX_THM1_100K_PU>;
1090		label = "sdm_temp";
1091	};
1092
1093	channel@4e {
1094		reg = <ADC5_AMUX_THM2_100K_PU>;
1095		label = "quiet_temp";
1096	};
1097
1098	channel@4f {
1099		reg = <ADC5_AMUX_THM3_100K_PU>;
1100		label = "lte_temp_1";
1101	};
1102
1103	channel@50 {
1104		reg = <ADC5_AMUX_THM4_100K_PU>;
1105		label = "lte_temp_2";
1106	};
1107
1108	channel@51 {
1109		reg = <ADC5_AMUX_THM5_100K_PU>;
1110		label = "charger_temp";
1111	};
1112};
1113
1114&pm8998_gpios {
1115	gpio-line-names = "",
1116			  "",
1117			  "SW_CTRL",
1118			  "",
1119			  "",
1120			  "",
1121			  "",
1122			  "",
1123			  "",
1124			  "",
1125			  "",
1126			  "",
1127			  "",
1128			  "",
1129			  "",
1130			  "",
1131			  "",
1132			  "",
1133			  "",
1134			  "",
1135			  "",
1136			  "CFG_OPT1",
1137			  "WCSS_PWR_REQ",
1138			  "",
1139			  "CFG_OPT2",
1140			  "SLB";
1141};
1142
1143&tlmm {
1144	/*
1145	 * pinctrl settings for pins that have no real owners.
1146	 */
1147	pinctrl-names = "default", "sleep";
1148	pinctrl-0 = <&bios_flash_wp_r_l>,
1149		    <&ap_suspend_l_deassert>;
1150
1151	pinctrl-1 = <&bios_flash_wp_r_l>,
1152		    <&ap_suspend_l_assert>;
1153
1154	/*
1155	 * Hogs prevent usermode from changing the value. A GPIO can be both
1156	 * here and in the pinctrl section.
1157	 */
1158	ap-suspend-l-hog {
1159		gpio-hog;
1160		gpios = <126 GPIO_ACTIVE_LOW>;
1161		output-low;
1162	};
1163
1164	ap_edp_bklten: ap-edp-bklten-state {
1165		pins = "gpio37";
1166		function = "gpio";
1167		drive-strength = <2>;
1168		bias-disable;
1169	};
1170
1171	bios_flash_wp_r_l: bios-flash-wp-r-l-state {
1172		pins = "gpio128";
1173		function = "gpio";
1174		bias-disable;
1175	};
1176
1177	ec_ap_int_l: ec-ap-int-l-state {
1178	       pins = "gpio122";
1179	       function = "gpio";
1180	       bias-pull-up;
1181	};
1182
1183	edp_brij_en: edp-brij-en-state {
1184		pins = "gpio102";
1185		function = "gpio";
1186		drive-strength = <2>;
1187		bias-disable;
1188	};
1189
1190	edp_brij_irq: edp-brij-irq-state {
1191		pins = "gpio10";
1192		function = "gpio";
1193		drive-strength = <2>;
1194		bias-pull-down;
1195	};
1196
1197	en_pp3300_dx_edp: en-pp3300-dx-edp-state {
1198		pins = "gpio43";
1199		function = "gpio";
1200		drive-strength = <2>;
1201		bias-disable;
1202	};
1203
1204	h1_ap_int_odl: h1-ap-int-odl-state {
1205		pins = "gpio129";
1206		function = "gpio";
1207		bias-pull-up;
1208	};
1209
1210	pen_eject_odl: pen-eject-odl-state {
1211		pins = "gpio119";
1212		function = "gpio";
1213		bias-pull-up;
1214	};
1215
1216	pen_irq_l: pen-irq-l-state {
1217		pins = "gpio24";
1218		function = "gpio";
1219
1220		/* Has external pullup */
1221		bias-disable;
1222	};
1223
1224	pen_pdct_l: pen-pdct-l-state {
1225		pins = "gpio63";
1226		function = "gpio";
1227
1228		/* Has external pullup */
1229		bias-disable;
1230	};
1231
1232	pen_rst_l: pen-rst-l-state {
1233		pins = "gpio23";
1234		function = "gpio";
1235		bias-disable;
1236		drive-strength = <2>;
1237
1238		/*
1239		 * The pen driver doesn't currently support
1240		 * driving this reset line.  By specifying
1241		 * output-high here we're relying on the fact
1242		 * that this pin has a default pulldown at boot
1243		 * (which makes sure the pen was in reset if it
1244		 * was powered) and then we set it high here to
1245		 * take it out of reset.  Better would be if the
1246		 * pen driver could control this and we could
1247		 * remove "output-high" here.
1248		 */
1249		output-high;
1250	};
1251
1252	qspi_sleep: qspi-sleep-state {
1253		pins = "gpio90", "gpio91", "gpio92", "gpio95";
1254
1255		/*
1256		 * When we're not actively transferring we want pins as GPIOs
1257		 * with output disabled so that the quad SPI IP block stops
1258		 * driving them. We rely on the normal pulls configured in
1259		 * the active state and don't redefine them here. Also note
1260		 * that we don't need the reverse (output-enable) in the
1261		 * normal mode since the "output-enable" only matters for
1262		 * GPIO function.
1263		 */
1264		function = "gpio";
1265		output-disable;
1266	};
1267
1268	sdc2_clk: sdc2-clk-state {
1269		pins = "sdc2_clk";
1270		bias-disable;
1271
1272		/*
1273		 * It seems that mmc_test reports errors if drive
1274		 * strength is not 16.
1275		 */
1276		drive-strength = <16>;
1277	};
1278
1279	sdc2_cmd: sdc2-cmd-state {
1280		pins = "sdc2_cmd";
1281		bias-pull-up;
1282		drive-strength = <16>;
1283	};
1284
1285	sdc2_data: sdc2-data-state {
1286		pins = "sdc2_data";
1287		bias-pull-up;
1288		drive-strength = <16>;
1289	};
1290
1291	sd_cd_odl: sd-cd-odl-state {
1292		pins = "gpio44";
1293		function = "gpio";
1294		bias-pull-up;
1295	};
1296
1297	ts_int_l: ts-int-l-state {
1298		pins = "gpio125";
1299		function = "gpio";
1300		bias-pull-up;
1301	};
1302
1303	ts_reset_l: ts-reset-l-state {
1304		pins = "gpio118";
1305		function = "gpio";
1306		bias-disable;
1307		drive-strength = <2>;
1308	};
1309
1310	ap_suspend_l_assert: ap-suspend-l-assert-state {
1311		pins = "gpio126";
1312		function = "gpio";
1313		bias-disable;
1314		drive-strength = <2>;
1315		output-low;
1316	};
1317
1318	ap_suspend_l_deassert: ap-suspend-l-deassert-state {
1319		pins = "gpio126";
1320		function = "gpio";
1321		bias-disable;
1322		drive-strength = <2>;
1323		output-high;
1324	};
1325};
1326
1327&venus {
1328	status = "okay";
1329
1330	video-firmware {
1331		iommus = <&apps_smmu 0x10b2 0x0>;
1332	};
1333};
1334