1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Google Cheza device tree source (common between revisions) 4 * 5 * Copyright 2018 Google LLC. 6 */ 7 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/input/input.h> 10#include <dt-bindings/regulator/qcom,rpmh-regulator.h> 11#include "sdm845.dtsi" 12 13/* PMICs depend on spmi_bus label and so must come after SoC */ 14#include "pm8005.dtsi" 15#include "pm8998.dtsi" 16 17/ { 18 aliases { 19 bluetooth0 = &bluetooth; 20 hsuart0 = &uart6; 21 serial0 = &uart9; 22 wifi0 = &wifi; 23 }; 24 25 chosen { 26 stdout-path = "serial0:115200n8"; 27 }; 28 29 backlight: backlight { 30 compatible = "pwm-backlight"; 31 pwms = <&cros_ec_pwm 0>; 32 enable-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>; 33 power-supply = <&ppvar_sys>; 34 pinctrl-names = "default"; 35 pinctrl-0 = <&ap_edp_bklten>; 36 }; 37 38 /* FIXED REGULATORS - parents above children */ 39 40 /* This is the top level supply and variable voltage */ 41 ppvar_sys: ppvar-sys-regulator { 42 compatible = "regulator-fixed"; 43 regulator-name = "ppvar_sys"; 44 regulator-always-on; 45 regulator-boot-on; 46 }; 47 48 /* This divides ppvar_sys by 2, so voltage is variable */ 49 src_vph_pwr: src-vph-pwr-regulator { 50 compatible = "regulator-fixed"; 51 regulator-name = "src_vph_pwr"; 52 53 /* EC turns on with switchcap_on_l; always on for AP */ 54 regulator-always-on; 55 regulator-boot-on; 56 57 vin-supply = <&ppvar_sys>; 58 }; 59 60 pp5000_a: pp5000-a-regulator { 61 compatible = "regulator-fixed"; 62 regulator-name = "pp5000_a"; 63 64 /* EC turns on with en_pp5000_a; always on for AP */ 65 regulator-always-on; 66 regulator-boot-on; 67 regulator-min-microvolt = <5000000>; 68 regulator-max-microvolt = <5000000>; 69 70 vin-supply = <&ppvar_sys>; 71 }; 72 73 src_vreg_bob: src-vreg-bob-regulator { 74 compatible = "regulator-fixed"; 75 regulator-name = "src_vreg_bob"; 76 77 /* EC turns on with vbob_en; always on for AP */ 78 regulator-always-on; 79 regulator-boot-on; 80 regulator-min-microvolt = <3600000>; 81 regulator-max-microvolt = <3600000>; 82 83 vin-supply = <&ppvar_sys>; 84 }; 85 86 pp3300_dx_edp: pp3300-dx-edp-regulator { 87 compatible = "regulator-fixed"; 88 regulator-name = "pp3300_dx_edp"; 89 90 regulator-min-microvolt = <3300000>; 91 regulator-max-microvolt = <3300000>; 92 93 gpio = <&tlmm 43 GPIO_ACTIVE_HIGH>; 94 enable-active-high; 95 pinctrl-names = "default"; 96 pinctrl-0 = <&en_pp3300_dx_edp>; 97 }; 98 99 /* 100 * Apparently RPMh does not provide support for PM8998 S4 because it 101 * is always-on; model it as a fixed regulator. 102 */ 103 src_pp1800_s4a: pm8998-smps4 { 104 compatible = "regulator-fixed"; 105 regulator-name = "src_pp1800_s4a"; 106 107 regulator-min-microvolt = <1800000>; 108 regulator-max-microvolt = <1800000>; 109 110 regulator-always-on; 111 regulator-boot-on; 112 113 vin-supply = <&src_vph_pwr>; 114 }; 115 116 /* BOARD-SPECIFIC TOP LEVEL NODES */ 117 118 gpio-keys { 119 compatible = "gpio-keys"; 120 pinctrl-names = "default"; 121 pinctrl-0 = <&pen_eject_odl>; 122 123 pen-insert { 124 label = "Pen Insert"; 125 /* Insert = low, eject = high */ 126 gpios = <&tlmm 119 GPIO_ACTIVE_LOW>; 127 linux,code = <SW_PEN_INSERTED>; 128 linux,input-type = <EV_SW>; 129 wakeup-source; 130 }; 131 }; 132 133 panel: panel { 134 compatible ="innolux,p120zdg-bf1"; 135 power-supply = <&pp3300_dx_edp>; 136 backlight = <&backlight>; 137 no-hpd; 138 139 ports { 140 panel_in: port { 141 panel_in_edp: endpoint { 142 remote-endpoint = <&sn65dsi86_out>; 143 }; 144 }; 145 }; 146 }; 147}; 148 149/* 150 * Reserved memory changes 151 * 152 * Putting this all together (out of order with the rest of the file) to keep 153 * all modifications to the memory map (from sdm845.dtsi) in one place. 154 */ 155 156/* 157 * Our mpss_region is 8MB bigger than the default one and that conflicts 158 * with venus_mem and cdsp_mem. 159 * 160 * For venus_mem we'll delete and re-create at a different address. 161 * 162 * cdsp_mem isn't used on cheza right now so we won't bother re-creating it; but 163 * that also means we need to delete cdsp_pas. 164 */ 165/delete-node/ &venus_mem; 166/delete-node/ &cdsp_mem; 167/delete-node/ &cdsp_pas; 168/delete-node/ &gpu_mem; 169 170/* Increase the size from 120 MB to 128 MB */ 171&mpss_region { 172 reg = <0 0x8e000000 0 0x8000000>; 173}; 174 175/* Increase the size from 2MB to 8MB */ 176&rmtfs_mem { 177 reg = <0 0x88f00000 0 0x800000>; 178}; 179 180/ { 181 reserved-memory { 182 venus_mem: memory@96000000 { 183 reg = <0 0x96000000 0 0x500000>; 184 no-map; 185 }; 186 }; 187}; 188 189&qspi { 190 status = "okay"; 191 pinctrl-names = "default"; 192 pinctrl-0 = <&qspi_clk &qspi_cs0 &qspi_data01>; 193 194 flash@0 { 195 compatible = "jedec,spi-nor"; 196 reg = <0>; 197 198 /* 199 * In theory chip supports up to 104 MHz and controller up 200 * to 80 MHz, but above 25 MHz wasn't reliable so we'll use 201 * that for now. b:117440651 202 */ 203 spi-max-frequency = <25000000>; 204 spi-tx-bus-width = <2>; 205 spi-rx-bus-width = <2>; 206 }; 207}; 208 209 210&apps_rsc { 211 pm8998-rpmh-regulators { 212 compatible = "qcom,pm8998-rpmh-regulators"; 213 qcom,pmic-id = "a"; 214 215 vdd-s1-supply = <&src_vph_pwr>; 216 vdd-s2-supply = <&src_vph_pwr>; 217 vdd-s3-supply = <&src_vph_pwr>; 218 vdd-s4-supply = <&src_vph_pwr>; 219 vdd-s5-supply = <&src_vph_pwr>; 220 vdd-s6-supply = <&src_vph_pwr>; 221 vdd-s7-supply = <&src_vph_pwr>; 222 vdd-s8-supply = <&src_vph_pwr>; 223 vdd-s9-supply = <&src_vph_pwr>; 224 vdd-s10-supply = <&src_vph_pwr>; 225 vdd-s11-supply = <&src_vph_pwr>; 226 vdd-s12-supply = <&src_vph_pwr>; 227 vdd-s13-supply = <&src_vph_pwr>; 228 vdd-l1-l27-supply = <&src_pp1025_s7a>; 229 vdd-l2-l8-l17-supply = <&src_pp1350_s3a>; 230 vdd-l3-l11-supply = <&src_pp1025_s7a>; 231 vdd-l4-l5-supply = <&src_pp1025_s7a>; 232 vdd-l6-supply = <&src_vph_pwr>; 233 vdd-l7-l12-l14-l15-supply = <&src_pp2040_s5a>; 234 vdd-l9-supply = <&src_pp2040_s5a>; 235 vdd-l10-l23-l25-supply = <&src_vreg_bob>; 236 vdd-l13-l19-l21-supply = <&src_vreg_bob>; 237 vdd-l16-l28-supply = <&src_vreg_bob>; 238 vdd-l18-l22-supply = <&src_vreg_bob>; 239 vdd-l20-l24-supply = <&src_vreg_bob>; 240 vdd-l26-supply = <&src_pp1350_s3a>; 241 vin-lvs-1-2-supply = <&src_pp1800_s4a>; 242 243 src_pp1125_s2a: smps2 { 244 regulator-min-microvolt = <1100000>; 245 regulator-max-microvolt = <1100000>; 246 }; 247 248 src_pp1350_s3a: smps3 { 249 regulator-min-microvolt = <1352000>; 250 regulator-max-microvolt = <1352000>; 251 }; 252 253 src_pp2040_s5a: smps5 { 254 regulator-min-microvolt = <1904000>; 255 regulator-max-microvolt = <2040000>; 256 }; 257 258 src_pp1025_s7a: smps7 { 259 regulator-min-microvolt = <900000>; 260 regulator-max-microvolt = <1028000>; 261 }; 262 263 vdd_qusb_hs0: 264 vdda_hp_pcie_core: 265 vdda_mipi_csi0_0p9: 266 vdda_mipi_csi1_0p9: 267 vdda_mipi_csi2_0p9: 268 vdda_mipi_dsi0_pll: 269 vdda_mipi_dsi1_pll: 270 vdda_qlink_lv: 271 vdda_qlink_lv_ck: 272 vdda_qrefs_0p875: 273 vdda_pcie_core: 274 vdda_pll_cc_ebi01: 275 vdda_pll_cc_ebi23: 276 vdda_sp_sensor: 277 vdda_ufs1_core: 278 vdda_ufs2_core: 279 vdda_usb1_ss_core: 280 vdda_usb2_ss_core: 281 src_pp875_l1a: ldo1 { 282 regulator-min-microvolt = <880000>; 283 regulator-max-microvolt = <880000>; 284 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 285 }; 286 287 vddpx_10: 288 src_pp1200_l2a: ldo2 { 289 regulator-min-microvolt = <1200000>; 290 regulator-max-microvolt = <1200000>; 291 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 292 293 /* TODO: why??? */ 294 regulator-always-on; 295 }; 296 297 pp1000_l3a_sdr845: ldo3 { 298 regulator-min-microvolt = <1000000>; 299 regulator-max-microvolt = <1000000>; 300 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 301 }; 302 303 vdd_wcss_cx: 304 vdd_wcss_mx: 305 vdda_wcss_pll: 306 src_pp800_l5a: ldo5 { 307 regulator-min-microvolt = <800000>; 308 regulator-max-microvolt = <800000>; 309 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 310 }; 311 312 vddpx_13: 313 src_pp1800_l6a: ldo6 { 314 regulator-min-microvolt = <1856000>; 315 regulator-max-microvolt = <1856000>; 316 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 317 }; 318 319 pp1800_l7a_wcn3990: ldo7 { 320 regulator-min-microvolt = <1800000>; 321 regulator-max-microvolt = <1800000>; 322 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 323 }; 324 325 src_pp1200_l8a: ldo8 { 326 regulator-min-microvolt = <1200000>; 327 regulator-max-microvolt = <1248000>; 328 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 329 }; 330 331 pp1800_dx_pen: 332 src_pp1800_l9a: ldo9 { 333 regulator-min-microvolt = <1800000>; 334 regulator-max-microvolt = <1800000>; 335 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 336 }; 337 338 src_pp1800_l10a: ldo10 { 339 regulator-min-microvolt = <1800000>; 340 regulator-max-microvolt = <1800000>; 341 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 342 }; 343 344 pp1000_l11a_sdr845: ldo11 { 345 regulator-min-microvolt = <1000000>; 346 regulator-max-microvolt = <1048000>; 347 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 348 }; 349 350 vdd_qfprom: 351 vdd_qfprom_sp: 352 vdda_apc1_cs_1p8: 353 vdda_gfx_cs_1p8: 354 vdda_qrefs_1p8: 355 vdda_qusb_hs0_1p8: 356 vddpx_11: 357 src_pp1800_l12a: ldo12 { 358 regulator-min-microvolt = <1800000>; 359 regulator-max-microvolt = <1800000>; 360 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 361 }; 362 363 vddpx_2: 364 src_pp2950_l13a: ldo13 { 365 regulator-min-microvolt = <1800000>; 366 regulator-max-microvolt = <2960000>; 367 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 368 }; 369 370 src_pp1800_l14a: ldo14 { 371 regulator-min-microvolt = <1800000>; 372 regulator-max-microvolt = <1800000>; 373 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 374 }; 375 376 src_pp1800_l15a: ldo15 { 377 regulator-min-microvolt = <1800000>; 378 regulator-max-microvolt = <1800000>; 379 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 380 }; 381 382 pp2700_l16a: ldo16 { 383 regulator-min-microvolt = <2704000>; 384 regulator-max-microvolt = <2704000>; 385 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 386 }; 387 388 src_pp1300_l17a: ldo17 { 389 regulator-min-microvolt = <1304000>; 390 regulator-max-microvolt = <1304000>; 391 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 392 }; 393 394 pp2700_l18a: ldo18 { 395 regulator-min-microvolt = <2704000>; 396 regulator-max-microvolt = <2960000>; 397 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 398 }; 399 400 /* 401 * NOTE: this rail should have been called 402 * src_pp3300_l19a in the schematic 403 */ 404 src_pp3000_l19a: ldo19 { 405 regulator-min-microvolt = <3304000>; 406 regulator-max-microvolt = <3304000>; 407 408 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 409 }; 410 411 src_pp2950_l20a: ldo20 { 412 regulator-min-microvolt = <2704000>; 413 regulator-max-microvolt = <2960000>; 414 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 415 }; 416 417 src_pp2950_l21a: ldo21 { 418 regulator-min-microvolt = <2704000>; 419 regulator-max-microvolt = <2960000>; 420 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 421 }; 422 423 pp3300_hub: 424 src_pp3300_l22a: ldo22 { 425 regulator-min-microvolt = <3304000>; 426 regulator-max-microvolt = <3304000>; 427 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 428 /* 429 * HACK: Should add a usb hub node and driver 430 * to turn this on and off at suspend/resume time 431 */ 432 regulator-boot-on; 433 regulator-always-on; 434 }; 435 436 pp3300_l23a_ch1_wcn3990: ldo23 { 437 regulator-min-microvolt = <3000000>; 438 regulator-max-microvolt = <3312000>; 439 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 440 }; 441 442 vdda_qusb_hs0_3p1: 443 src_pp3075_l24a: ldo24 { 444 regulator-min-microvolt = <3088000>; 445 regulator-max-microvolt = <3088000>; 446 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 447 }; 448 449 pp3300_l25a_ch0_wcn3990: ldo25 { 450 regulator-min-microvolt = <3304000>; 451 regulator-max-microvolt = <3304000>; 452 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 453 }; 454 455 pp1200_hub: 456 vdda_hp_pcie_1p2: 457 vdda_hv_ebi0: 458 vdda_hv_ebi1: 459 vdda_hv_ebi2: 460 vdda_hv_ebi3: 461 vdda_mipi_csi_1p25: 462 vdda_mipi_dsi0_1p2: 463 vdda_mipi_dsi1_1p2: 464 vdda_pcie_1p2: 465 vdda_ufs1_1p2: 466 vdda_ufs2_1p2: 467 vdda_usb1_ss_1p2: 468 vdda_usb2_ss_1p2: 469 src_pp1200_l26a: ldo26 { 470 regulator-min-microvolt = <1200000>; 471 regulator-max-microvolt = <1200000>; 472 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 473 }; 474 475 pp3300_dx_pen: 476 src_pp3300_l28a: ldo28 { 477 regulator-min-microvolt = <3304000>; 478 regulator-max-microvolt = <3304000>; 479 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 480 }; 481 482 src_pp1800_lvs1: lvs1 { 483 regulator-min-microvolt = <1800000>; 484 regulator-max-microvolt = <1800000>; 485 }; 486 487 src_pp1800_lvs2: lvs2 { 488 regulator-min-microvolt = <1800000>; 489 regulator-max-microvolt = <1800000>; 490 }; 491 }; 492 493 pm8005-rpmh-regulators { 494 compatible = "qcom,pm8005-rpmh-regulators"; 495 qcom,pmic-id = "c"; 496 497 vdd-s1-supply = <&src_vph_pwr>; 498 vdd-s2-supply = <&src_vph_pwr>; 499 vdd-s3-supply = <&src_vph_pwr>; 500 vdd-s4-supply = <&src_vph_pwr>; 501 502 src_pp600_s3c: smps3 { 503 regulator-min-microvolt = <600000>; 504 regulator-max-microvolt = <600000>; 505 }; 506 }; 507}; 508 509&dsi0 { 510 status = "okay"; 511 vdda-supply = <&vdda_mipi_dsi0_1p2>; 512 513 ports { 514 port@1 { 515 endpoint { 516 remote-endpoint = <&sn65dsi86_in>; 517 data-lanes = <0 1 2 3>; 518 }; 519 }; 520 }; 521}; 522 523&dsi0_phy { 524 status = "okay"; 525 vdds-supply = <&vdda_mipi_dsi0_pll>; 526}; 527 528edp_brij_i2c: &i2c3 { 529 status = "okay"; 530 clock-frequency = <400000>; 531 532 sn65dsi86_bridge: bridge@2d { 533 compatible = "ti,sn65dsi86"; 534 reg = <0x2d>; 535 pinctrl-names = "default"; 536 pinctrl-0 = <&edp_brij_en &edp_brij_irq>; 537 538 interrupt-parent = <&tlmm>; 539 interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; 540 541 enable-gpios = <&tlmm 102 GPIO_ACTIVE_HIGH>; 542 543 vpll-supply = <&src_pp1800_s4a>; 544 vccio-supply = <&src_pp1800_s4a>; 545 vcca-supply = <&src_pp1200_l2a>; 546 vcc-supply = <&src_pp1200_l2a>; 547 548 clocks = <&rpmhcc RPMH_LN_BB_CLK2>; 549 clock-names = "refclk"; 550 551 no-hpd; 552 553 ports { 554 #address-cells = <1>; 555 #size-cells = <0>; 556 557 port@0 { 558 reg = <0>; 559 sn65dsi86_in: endpoint { 560 remote-endpoint = <&dsi0_out>; 561 }; 562 }; 563 564 port@1 { 565 reg = <1>; 566 sn65dsi86_out: endpoint { 567 remote-endpoint = <&panel_in_edp>; 568 }; 569 }; 570 }; 571 }; 572}; 573 574ap_pen_1v8: &i2c11 { 575 status = "okay"; 576 clock-frequency = <400000>; 577 578 digitizer@9 { 579 compatible = "wacom,w9013", "hid-over-i2c"; 580 reg = <0x9>; 581 pinctrl-names = "default"; 582 pinctrl-0 = <&pen_irq_l>, <&pen_pdct_l>, <&pen_rst_l>; 583 584 vdd-supply = <&pp3300_dx_pen>; 585 vddl-supply = <&pp1800_dx_pen>; 586 post-power-on-delay-ms = <100>; 587 588 interrupt-parent = <&tlmm>; 589 interrupts = <24 IRQ_TYPE_LEVEL_LOW>; 590 591 hid-descr-addr = <0x1>; 592 }; 593}; 594 595amp_i2c: &i2c12 { 596 status = "okay"; 597 clock-frequency = <400000>; 598}; 599 600ap_ts_i2c: &i2c14 { 601 status = "okay"; 602 clock-frequency = <400000>; 603 604 touchscreen@10 { 605 compatible = "elan,ekth3500"; 606 reg = <0x10>; 607 pinctrl-names = "default"; 608 pinctrl-0 = <&ts_int_l &ts_reset_l>; 609 610 interrupt-parent = <&tlmm>; 611 interrupts = <125 IRQ_TYPE_LEVEL_LOW>; 612 613 vcc33-supply = <&src_pp3300_l28a>; 614 615 reset-gpios = <&tlmm 118 GPIO_ACTIVE_LOW>; 616 }; 617}; 618 619&ipa { 620 status = "okay"; 621 modem-init; 622}; 623 624&lpasscc { 625 status = "okay"; 626}; 627 628&mdss { 629 status = "okay"; 630}; 631 632&mdss_mdp { 633 status = "okay"; 634}; 635 636&mss_pil { 637 iommus = <&apps_smmu 0x780 0x1>, 638 <&apps_smmu 0x724 0x3>; 639}; 640 641&pm8998_pwrkey { 642 status = "disabled"; 643}; 644 645&qupv3_id_0 { 646 status = "okay"; 647}; 648 649&qupv3_id_1 { 650 status = "okay"; 651}; 652 653&sdhc_2 { 654 status = "okay"; 655 656 pinctrl-names = "default"; 657 pinctrl-0 = <&sdc2_clk &sdc2_cmd &sdc2_data &sd_cd_odl>; 658 659 vmmc-supply = <&src_pp2950_l21a>; 660 vqmmc-supply = <&vddpx_2>; 661 662 cd-gpios = <&tlmm 44 GPIO_ACTIVE_LOW>; 663}; 664 665&spi0 { 666 status = "okay"; 667}; 668 669&spi5 { 670 status = "okay"; 671 672 tpm@0 { 673 compatible = "google,cr50"; 674 reg = <0>; 675 pinctrl-names = "default"; 676 pinctrl-0 = <&h1_ap_int_odl>; 677 spi-max-frequency = <800000>; 678 interrupt-parent = <&tlmm>; 679 interrupts = <129 IRQ_TYPE_EDGE_RISING>; 680 }; 681}; 682 683&spi10 { 684 status = "okay"; 685 686 cros_ec: ec@0 { 687 compatible = "google,cros-ec-spi"; 688 reg = <0>; 689 interrupt-parent = <&tlmm>; 690 interrupts = <122 IRQ_TYPE_LEVEL_LOW>; 691 pinctrl-names = "default"; 692 pinctrl-0 = <&ec_ap_int_l>; 693 spi-max-frequency = <3000000>; 694 695 cros_ec_pwm: ec-pwm { 696 compatible = "google,cros-ec-pwm"; 697 #pwm-cells = <1>; 698 }; 699 700 i2c_tunnel: i2c-tunnel { 701 compatible = "google,cros-ec-i2c-tunnel"; 702 google,remote-bus = <0>; 703 #address-cells = <1>; 704 #size-cells = <0>; 705 }; 706 707 pdupdate { 708 compatible = "google,cros-ec-pd-update"; 709 }; 710 }; 711}; 712 713#include <arm/cros-ec-keyboard.dtsi> 714#include <arm/cros-ec-sbs.dtsi> 715 716&uart6 { 717 status = "okay"; 718 719 bluetooth: wcn3990-bt { 720 compatible = "qcom,wcn3990-bt"; 721 vddio-supply = <&src_pp1800_s4a>; 722 vddxo-supply = <&pp1800_l7a_wcn3990>; 723 vddrf-supply = <&src_pp1300_l17a>; 724 vddch0-supply = <&pp3300_l25a_ch0_wcn3990>; 725 max-speed = <3200000>; 726 }; 727}; 728 729&uart9 { 730 status = "okay"; 731}; 732 733&ufs_mem_hc { 734 status = "okay"; 735 736 reset-gpios = <&tlmm 150 GPIO_ACTIVE_LOW>; 737 738 vcc-supply = <&src_pp2950_l20a>; 739 vcc-max-microamp = <600000>; 740}; 741 742&ufs_mem_phy { 743 status = "okay"; 744 745 vdda-phy-supply = <&vdda_ufs1_core>; 746 vdda-pll-supply = <&vdda_ufs1_1p2>; 747}; 748 749&usb_1 { 750 status = "okay"; 751 752 /* We'll use this as USB 2.0 only */ 753 qcom,select-utmi-as-pipe-clk; 754}; 755 756&usb_1_dwc3 { 757 /* 758 * The hardware design intends this port to be hooked up in peripheral 759 * mode, so we'll hardcode it here. Some details: 760 * - SDM845 expects only a single Type C connector so it has only one 761 * native Type C port but cheza has two Type C connectors. 762 * - The only source of DP is the single native Type C port. 763 * - On cheza we want to be able to hook DP up to _either_ of the 764 * two Type C connectors and want to be able to achieve 4 lanes of DP. 765 * - When you configure a Type C port for 4 lanes of DP you lose USB3. 766 * - In order to make everything work, the native Type C port is always 767 * configured as 4-lanes DP so it's always available. 768 * - The extra USB3 port on SDM845 goes to a USB 3 hub which is then 769 * sent to the two Type C connectors. 770 * - The extra USB2 lines from the native Type C port are always 771 * setup as "peripheral" so that we can mux them over to one connector 772 * or the other if someone needs the connector configured as a gadget 773 * (but they only get USB2 speeds). 774 * 775 * All the hardware muxes would allow us to hook things up in different 776 * ways to some potential benefit for static configurations (you could 777 * achieve extra USB2 bandwidth by using two different ports for the 778 * two connectors or possibly even get USB3 peripheral mode), but in 779 * each case you end up forcing to disconnect/reconnect an in-use 780 * USB session in some cases depending on what you hotplug into the 781 * other connector. Thus hardcoding this as peripheral makes sense. 782 */ 783 dr_mode = "peripheral"; 784 785 /* 786 * We always need the high speed pins as 4-lanes DP in case someone 787 * hotplugs a DP peripheral. Thus limit this port to a max of high 788 * speed. 789 */ 790 maximum-speed = "high-speed"; 791 792 /* 793 * We don't need the usb3-phy since we run in highspeed mode always, so 794 * re-define these properties removing the superspeed USB PHY reference. 795 */ 796 phys = <&usb_1_hsphy>; 797 phy-names = "usb2-phy"; 798}; 799 800&usb_1_hsphy { 801 status = "okay"; 802 803 vdd-supply = <&vdda_usb1_ss_core>; 804 vdda-pll-supply = <&vdda_qusb_hs0_1p8>; 805 vdda-phy-dpdm-supply = <&vdda_qusb_hs0_3p1>; 806 807 qcom,imp-res-offset-value = <8>; 808 qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_21_6_MA>; 809 qcom,preemphasis-level = <QUSB2_V2_PREEMPHASIS_5_PERCENT>; 810 qcom,preemphasis-width = <QUSB2_V2_PREEMPHASIS_WIDTH_HALF_BIT>; 811}; 812 813&usb_2 { 814 status = "okay"; 815}; 816 817&usb_2_dwc3 { 818 /* We have this hooked up to a hub and we always use in host mode */ 819 dr_mode = "host"; 820}; 821 822&usb_2_hsphy { 823 status = "okay"; 824 825 vdd-supply = <&vdda_usb2_ss_core>; 826 vdda-pll-supply = <&vdda_qusb_hs0_1p8>; 827 vdda-phy-dpdm-supply = <&vdda_qusb_hs0_3p1>; 828 829 qcom,imp-res-offset-value = <8>; 830 qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_22_8_MA>; 831}; 832 833&usb_2_qmpphy { 834 status = "okay"; 835 836 vdda-phy-supply = <&vdda_usb2_ss_1p2>; 837 vdda-pll-supply = <&vdda_usb2_ss_core>; 838}; 839 840&wifi { 841 status = "okay"; 842 843 vdd-0.8-cx-mx-supply = <&src_pp800_l5a >; 844 vdd-1.8-xo-supply = <&pp1800_l7a_wcn3990>; 845 vdd-1.3-rfa-supply = <&src_pp1300_l17a>; 846 vdd-3.3-ch0-supply = <&pp3300_l25a_ch0_wcn3990>; 847}; 848 849/* PINCTRL - additions to nodes defined in sdm845.dtsi */ 850 851&qspi_cs0 { 852 pinconf { 853 pins = "gpio90"; 854 bias-disable; 855 }; 856}; 857 858&qspi_clk { 859 pinconf { 860 pins = "gpio95"; 861 bias-disable; 862 }; 863}; 864 865&qspi_data01 { 866 pinconf { 867 pins = "gpio91", "gpio92"; 868 869 /* High-Z when no transfers; nice to park the lines */ 870 bias-pull-up; 871 }; 872}; 873 874&qup_i2c3_default { 875 pinconf { 876 pins = "gpio41", "gpio42"; 877 drive-strength = <2>; 878 879 /* Has external pullup */ 880 bias-disable; 881 }; 882}; 883 884&qup_i2c11_default { 885 pinconf { 886 pins = "gpio31", "gpio32"; 887 drive-strength = <2>; 888 889 /* Has external pullup */ 890 bias-disable; 891 }; 892}; 893 894&qup_i2c12_default { 895 pinconf { 896 pins = "gpio49", "gpio50"; 897 drive-strength = <2>; 898 899 /* Has external pullup */ 900 bias-disable; 901 }; 902}; 903 904&qup_i2c14_default { 905 pinconf { 906 pins = "gpio33", "gpio34"; 907 drive-strength = <2>; 908 909 /* Has external pullup */ 910 bias-disable; 911 }; 912}; 913 914&qup_spi0_default { 915 pinconf { 916 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 917 drive-strength = <2>; 918 bias-disable; 919 }; 920}; 921 922&qup_spi5_default { 923 pinconf { 924 pins = "gpio85", "gpio86", "gpio87", "gpio88"; 925 drive-strength = <2>; 926 bias-disable; 927 }; 928}; 929 930&qup_spi10_default { 931 pinconf { 932 pins = "gpio53", "gpio54", "gpio55", "gpio56"; 933 drive-strength = <2>; 934 bias-disable; 935 }; 936}; 937 938&qup_uart6_default { 939 /* Change pinmux to all 4 pins since CTS and RTS are connected */ 940 pinmux { 941 pins = "gpio45", "gpio46", 942 "gpio47", "gpio48"; 943 }; 944 945 pinconf-cts { 946 /* 947 * Configure a pull-down on 45 (CTS) to match the pull of 948 * the Bluetooth module. 949 */ 950 pins = "gpio45"; 951 bias-pull-down; 952 }; 953 954 pinconf-rts-tx { 955 /* We'll drive 46 (RTS) and 47 (TX), so no pull */ 956 pins = "gpio46", "gpio47"; 957 drive-strength = <2>; 958 bias-disable; 959 }; 960 961 pinconf-rx { 962 /* 963 * Configure a pull-up on 48 (RX). This is needed to avoid 964 * garbage data when the TX pin of the Bluetooth module is 965 * in tri-state (module powered off or not driving the 966 * signal yet). 967 */ 968 pins = "gpio48"; 969 bias-pull-up; 970 }; 971}; 972 973&qup_uart9_default { 974 pinconf-tx { 975 pins = "gpio4"; 976 drive-strength = <2>; 977 bias-disable; 978 }; 979 980 pinconf-rx { 981 pins = "gpio5"; 982 drive-strength = <2>; 983 bias-pull-up; 984 }; 985}; 986 987/* PINCTRL - board-specific pinctrl */ 988&pm8005_gpio { 989 gpio-line-names = "", 990 "", 991 "SLB", 992 ""; 993}; 994 995&pm8998_adc { 996 adc-chan@4d { 997 reg = <ADC5_AMUX_THM1_100K_PU>; 998 label = "sdm_temp"; 999 }; 1000 1001 adc-chan@4e { 1002 reg = <ADC5_AMUX_THM2_100K_PU>; 1003 label = "quiet_temp"; 1004 }; 1005 1006 adc-chan@4f { 1007 reg = <ADC5_AMUX_THM3_100K_PU>; 1008 label = "lte_temp_1"; 1009 }; 1010 1011 adc-chan@50 { 1012 reg = <ADC5_AMUX_THM4_100K_PU>; 1013 label = "lte_temp_2"; 1014 }; 1015 1016 adc-chan@51 { 1017 reg = <ADC5_AMUX_THM5_100K_PU>; 1018 label = "charger_temp"; 1019 }; 1020}; 1021 1022&pm8998_gpio { 1023 gpio-line-names = "", 1024 "", 1025 "SW_CTRL", 1026 "", 1027 "", 1028 "", 1029 "", 1030 "", 1031 "", 1032 "", 1033 "", 1034 "", 1035 "", 1036 "", 1037 "", 1038 "", 1039 "", 1040 "", 1041 "", 1042 "", 1043 "", 1044 "CFG_OPT1", 1045 "WCSS_PWR_REQ", 1046 "", 1047 "CFG_OPT2", 1048 "SLB"; 1049}; 1050 1051&tlmm { 1052 /* 1053 * pinctrl settings for pins that have no real owners. 1054 */ 1055 pinctrl-names = "default", "sleep"; 1056 pinctrl-0 = <&bios_flash_wp_r_l>, 1057 <&ap_suspend_l_deassert>; 1058 1059 pinctrl-1 = <&bios_flash_wp_r_l>, 1060 <&ap_suspend_l_assert>; 1061 1062 /* 1063 * Hogs prevent usermode from changing the value. A GPIO can be both 1064 * here and in the pinctrl section. 1065 */ 1066 ap-suspend-l-hog { 1067 gpio-hog; 1068 gpios = <126 GPIO_ACTIVE_LOW>; 1069 output-low; 1070 }; 1071 1072 ap_edp_bklten: ap-edp-bklten { 1073 pinmux { 1074 pins = "gpio37"; 1075 function = "gpio"; 1076 }; 1077 1078 pinconf { 1079 pins = "gpio37"; 1080 drive-strength = <2>; 1081 bias-disable; 1082 }; 1083 }; 1084 1085 bios_flash_wp_r_l: bios-flash-wp-r-l { 1086 pinmux { 1087 pins = "gpio128"; 1088 function = "gpio"; 1089 input-enable; 1090 }; 1091 1092 pinconf { 1093 pins = "gpio128"; 1094 bias-disable; 1095 }; 1096 }; 1097 1098 ec_ap_int_l: ec-ap-int-l { 1099 pinmux { 1100 pins = "gpio122"; 1101 function = "gpio"; 1102 input-enable; 1103 }; 1104 1105 pinconf { 1106 pins = "gpio122"; 1107 bias-pull-up; 1108 }; 1109 }; 1110 1111 edp_brij_en: edp-brij-en { 1112 pinmux { 1113 pins = "gpio102"; 1114 function = "gpio"; 1115 }; 1116 1117 pinconf { 1118 pins = "gpio102"; 1119 drive-strength = <2>; 1120 bias-disable; 1121 }; 1122 }; 1123 1124 edp_brij_irq: edp-brij-irq { 1125 pinmux { 1126 pins = "gpio10"; 1127 function = "gpio"; 1128 }; 1129 1130 pinconf { 1131 pins = "gpio10"; 1132 drive-strength = <2>; 1133 bias-pull-down; 1134 }; 1135 }; 1136 1137 en_pp3300_dx_edp: en-pp3300-dx-edp { 1138 pinmux { 1139 pins = "gpio43"; 1140 function = "gpio"; 1141 }; 1142 1143 pinconf { 1144 pins = "gpio43"; 1145 drive-strength = <2>; 1146 bias-disable; 1147 }; 1148 }; 1149 1150 h1_ap_int_odl: h1-ap-int-odl { 1151 pinmux { 1152 pins = "gpio129"; 1153 function = "gpio"; 1154 input-enable; 1155 }; 1156 1157 pinconf { 1158 pins = "gpio129"; 1159 bias-pull-up; 1160 }; 1161 }; 1162 1163 pen_eject_odl: pen-eject-odl { 1164 pinmux { 1165 pins = "gpio119"; 1166 function = "gpio"; 1167 bias-pull-up; 1168 }; 1169 }; 1170 1171 pen_irq_l: pen-irq-l { 1172 pinmux { 1173 pins = "gpio24"; 1174 function = "gpio"; 1175 }; 1176 1177 pinconf { 1178 pins = "gpio24"; 1179 1180 /* Has external pullup */ 1181 bias-disable; 1182 }; 1183 }; 1184 1185 pen_pdct_l: pen-pdct-l { 1186 pinmux { 1187 pins = "gpio63"; 1188 function = "gpio"; 1189 }; 1190 1191 pinconf { 1192 pins = "gpio63"; 1193 1194 /* Has external pullup */ 1195 bias-disable; 1196 }; 1197 }; 1198 1199 pen_rst_l: pen-rst-l { 1200 pinmux { 1201 pins = "gpio23"; 1202 function = "gpio"; 1203 }; 1204 1205 pinconf { 1206 pins = "gpio23"; 1207 bias-disable; 1208 drive-strength = <2>; 1209 1210 /* 1211 * The pen driver doesn't currently support 1212 * driving this reset line. By specifying 1213 * output-high here we're relying on the fact 1214 * that this pin has a default pulldown at boot 1215 * (which makes sure the pen was in reset if it 1216 * was powered) and then we set it high here to 1217 * take it out of reset. Better would be if the 1218 * pen driver could control this and we could 1219 * remove "output-high" here. 1220 */ 1221 output-high; 1222 }; 1223 }; 1224 1225 sdc2_clk: sdc2-clk { 1226 pinconf { 1227 pins = "sdc2_clk"; 1228 bias-disable; 1229 1230 /* 1231 * It seems that mmc_test reports errors if drive 1232 * strength is not 16. 1233 */ 1234 drive-strength = <16>; 1235 }; 1236 }; 1237 1238 sdc2_cmd: sdc2-cmd { 1239 pinconf { 1240 pins = "sdc2_cmd"; 1241 bias-pull-up; 1242 drive-strength = <16>; 1243 }; 1244 }; 1245 1246 sdc2_data: sdc2-data { 1247 pinconf { 1248 pins = "sdc2_data"; 1249 bias-pull-up; 1250 drive-strength = <16>; 1251 }; 1252 }; 1253 1254 sd_cd_odl: sd-cd-odl { 1255 pinmux { 1256 pins = "gpio44"; 1257 function = "gpio"; 1258 }; 1259 1260 pinconf { 1261 pins = "gpio44"; 1262 bias-pull-up; 1263 }; 1264 }; 1265 1266 ts_int_l: ts-int-l { 1267 pinmux { 1268 pins = "gpio125"; 1269 function = "gpio"; 1270 }; 1271 1272 pinconf { 1273 pins = "gpio125"; 1274 bias-pull-up; 1275 }; 1276 }; 1277 1278 ts_reset_l: ts-reset-l { 1279 pinmux { 1280 pins = "gpio118"; 1281 function = "gpio"; 1282 }; 1283 1284 pinconf { 1285 pins = "gpio118"; 1286 bias-disable; 1287 drive-strength = <2>; 1288 }; 1289 }; 1290 1291 ap_suspend_l_assert: ap_suspend_l_assert { 1292 config { 1293 pins = "gpio126"; 1294 function = "gpio"; 1295 bias-no-pull; 1296 drive-strength = <2>; 1297 output-low; 1298 }; 1299 }; 1300 1301 ap_suspend_l_deassert: ap_suspend_l_deassert { 1302 config { 1303 pins = "gpio126"; 1304 function = "gpio"; 1305 bias-no-pull; 1306 drive-strength = <2>; 1307 output-high; 1308 }; 1309 }; 1310}; 1311 1312&venus { 1313 video-firmware { 1314 iommus = <&apps_smmu 0x10b2 0x0>; 1315 }; 1316}; 1317