179e7739fSRob Clark// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
279e7739fSRob Clark/*
379e7739fSRob Clark * Google Cheza device tree source (common between revisions)
479e7739fSRob Clark *
579e7739fSRob Clark * Copyright 2018 Google LLC.
679e7739fSRob Clark */
779e7739fSRob Clark
879e7739fSRob Clark#include <dt-bindings/input/input.h>
979e7739fSRob Clark#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
1079e7739fSRob Clark#include "sdm845.dtsi"
1179e7739fSRob Clark
1279e7739fSRob Clark/* PMICs depend on spmi_bus label and so must come after SoC */
1379e7739fSRob Clark#include "pm8005.dtsi"
1479e7739fSRob Clark#include "pm8998.dtsi"
1579e7739fSRob Clark
1679e7739fSRob Clark/ {
1779e7739fSRob Clark	aliases {
1879e7739fSRob Clark		bluetooth0 = &bluetooth;
194772c030SCaleb Connolly		serial1 = &uart6;
2079e7739fSRob Clark		serial0 = &uart9;
2179e7739fSRob Clark		wifi0 = &wifi;
2279e7739fSRob Clark	};
2379e7739fSRob Clark
2479e7739fSRob Clark	chosen {
2579e7739fSRob Clark		stdout-path = "serial0:115200n8";
2679e7739fSRob Clark	};
2779e7739fSRob Clark
2879e7739fSRob Clark	backlight: backlight {
2979e7739fSRob Clark		compatible = "pwm-backlight";
3079e7739fSRob Clark		pwms = <&cros_ec_pwm 0>;
3179e7739fSRob Clark		enable-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>;
3279e7739fSRob Clark		power-supply = <&ppvar_sys>;
3379e7739fSRob Clark		pinctrl-names = "default";
3479e7739fSRob Clark		pinctrl-0 = <&ap_edp_bklten>;
3579e7739fSRob Clark	};
3679e7739fSRob Clark
3779e7739fSRob Clark	/* FIXED REGULATORS - parents above children */
3879e7739fSRob Clark
3979e7739fSRob Clark	/* This is the top level supply and variable voltage */
4079e7739fSRob Clark	ppvar_sys: ppvar-sys-regulator {
4179e7739fSRob Clark		compatible = "regulator-fixed";
4279e7739fSRob Clark		regulator-name = "ppvar_sys";
4379e7739fSRob Clark		regulator-always-on;
4479e7739fSRob Clark		regulator-boot-on;
4579e7739fSRob Clark	};
4679e7739fSRob Clark
4779e7739fSRob Clark	/* This divides ppvar_sys by 2, so voltage is variable */
4879e7739fSRob Clark	src_vph_pwr: src-vph-pwr-regulator {
4979e7739fSRob Clark		compatible = "regulator-fixed";
5079e7739fSRob Clark		regulator-name = "src_vph_pwr";
5179e7739fSRob Clark
5279e7739fSRob Clark		/* EC turns on with switchcap_on_l; always on for AP */
5379e7739fSRob Clark		regulator-always-on;
5479e7739fSRob Clark		regulator-boot-on;
5579e7739fSRob Clark
5679e7739fSRob Clark		vin-supply = <&ppvar_sys>;
5779e7739fSRob Clark	};
5879e7739fSRob Clark
5979e7739fSRob Clark	pp5000_a: pp5000-a-regulator {
6079e7739fSRob Clark		compatible = "regulator-fixed";
6179e7739fSRob Clark		regulator-name = "pp5000_a";
6279e7739fSRob Clark
6379e7739fSRob Clark		/* EC turns on with en_pp5000_a; always on for AP */
6479e7739fSRob Clark		regulator-always-on;
6579e7739fSRob Clark		regulator-boot-on;
6679e7739fSRob Clark		regulator-min-microvolt = <5000000>;
6779e7739fSRob Clark		regulator-max-microvolt = <5000000>;
6879e7739fSRob Clark
6979e7739fSRob Clark		vin-supply = <&ppvar_sys>;
7079e7739fSRob Clark	};
7179e7739fSRob Clark
7279e7739fSRob Clark	src_vreg_bob: src-vreg-bob-regulator {
7379e7739fSRob Clark		compatible = "regulator-fixed";
7479e7739fSRob Clark		regulator-name = "src_vreg_bob";
7579e7739fSRob Clark
7679e7739fSRob Clark		/* EC turns on with vbob_en; always on for AP */
7779e7739fSRob Clark		regulator-always-on;
7879e7739fSRob Clark		regulator-boot-on;
7979e7739fSRob Clark		regulator-min-microvolt = <3600000>;
8079e7739fSRob Clark		regulator-max-microvolt = <3600000>;
8179e7739fSRob Clark
8279e7739fSRob Clark		vin-supply = <&ppvar_sys>;
8379e7739fSRob Clark	};
8479e7739fSRob Clark
8579e7739fSRob Clark	pp3300_dx_edp: pp3300-dx-edp-regulator {
8679e7739fSRob Clark		compatible = "regulator-fixed";
8779e7739fSRob Clark		regulator-name = "pp3300_dx_edp";
8879e7739fSRob Clark
8979e7739fSRob Clark		regulator-min-microvolt = <3300000>;
9079e7739fSRob Clark		regulator-max-microvolt = <3300000>;
9179e7739fSRob Clark
9279e7739fSRob Clark		gpio = <&tlmm 43 GPIO_ACTIVE_HIGH>;
9379e7739fSRob Clark		enable-active-high;
9479e7739fSRob Clark		pinctrl-names = "default";
9579e7739fSRob Clark		pinctrl-0 = <&en_pp3300_dx_edp>;
9679e7739fSRob Clark	};
9779e7739fSRob Clark
9879e7739fSRob Clark	/*
9979e7739fSRob Clark	 * Apparently RPMh does not provide support for PM8998 S4 because it
10079e7739fSRob Clark	 * is always-on; model it as a fixed regulator.
10179e7739fSRob Clark	 */
10279e7739fSRob Clark	src_pp1800_s4a: pm8998-smps4 {
10379e7739fSRob Clark		compatible = "regulator-fixed";
10479e7739fSRob Clark		regulator-name = "src_pp1800_s4a";
10579e7739fSRob Clark
10679e7739fSRob Clark		regulator-min-microvolt = <1800000>;
10779e7739fSRob Clark		regulator-max-microvolt = <1800000>;
10879e7739fSRob Clark
10979e7739fSRob Clark		regulator-always-on;
11079e7739fSRob Clark		regulator-boot-on;
11179e7739fSRob Clark
11279e7739fSRob Clark		vin-supply = <&src_vph_pwr>;
11379e7739fSRob Clark	};
11479e7739fSRob Clark
11579e7739fSRob Clark	/* BOARD-SPECIFIC TOP LEVEL NODES */
11679e7739fSRob Clark
11779e7739fSRob Clark	gpio-keys {
11879e7739fSRob Clark		compatible = "gpio-keys";
11979e7739fSRob Clark		pinctrl-names = "default";
12079e7739fSRob Clark		pinctrl-0 = <&pen_eject_odl>;
12179e7739fSRob Clark
122b08f5cbdSKrzysztof Kozlowski		switch-pen-insert {
12379e7739fSRob Clark			label = "Pen Insert";
12479e7739fSRob Clark			/* Insert = low, eject = high */
12579e7739fSRob Clark			gpios = <&tlmm 119 GPIO_ACTIVE_LOW>;
12679e7739fSRob Clark			linux,code = <SW_PEN_INSERTED>;
12779e7739fSRob Clark			linux,input-type = <EV_SW>;
12879e7739fSRob Clark			wakeup-source;
12979e7739fSRob Clark		};
13079e7739fSRob Clark	};
13179e7739fSRob Clark
13279e7739fSRob Clark	panel: panel {
13379e7739fSRob Clark		compatible = "innolux,p120zdg-bf1";
13479e7739fSRob Clark		power-supply = <&pp3300_dx_edp>;
13579e7739fSRob Clark		backlight = <&backlight>;
13679e7739fSRob Clark		no-hpd;
13779e7739fSRob Clark
13879e7739fSRob Clark		ports {
13979e7739fSRob Clark			panel_in: port {
14079e7739fSRob Clark				panel_in_edp: endpoint {
14179e7739fSRob Clark					remote-endpoint = <&sn65dsi86_out>;
14279e7739fSRob Clark				};
14379e7739fSRob Clark			};
14479e7739fSRob Clark		};
14579e7739fSRob Clark	};
14679e7739fSRob Clark};
14779e7739fSRob Clark
148a1ade6caSAbel Vesa&psci {
149a1ade6caSAbel Vesa	/delete-node/ cpu0;
150a1ade6caSAbel Vesa	/delete-node/ cpu1;
151a1ade6caSAbel Vesa	/delete-node/ cpu2;
152a1ade6caSAbel Vesa	/delete-node/ cpu3;
153a1ade6caSAbel Vesa	/delete-node/ cpu4;
154a1ade6caSAbel Vesa	/delete-node/ cpu5;
155a1ade6caSAbel Vesa	/delete-node/ cpu6;
156a1ade6caSAbel Vesa	/delete-node/ cpu7;
157a1ade6caSAbel Vesa	/delete-node/ cpu-cluster0;
158a1ade6caSAbel Vesa};
159a1ade6caSAbel Vesa
160a1ade6caSAbel Vesa&cpus {
161a1ade6caSAbel Vesa	/delete-node/ domain-idle-states;
162a1ade6caSAbel Vesa};
163a1ade6caSAbel Vesa
164a1ade6caSAbel Vesa&cpu_idle_states {
165a1ade6caSAbel Vesa	LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
166a1ade6caSAbel Vesa		compatible = "arm,idle-state";
167a1ade6caSAbel Vesa		idle-state-name = "little-power-down";
168a1ade6caSAbel Vesa		arm,psci-suspend-param = <0x40000003>;
169a1ade6caSAbel Vesa		entry-latency-us = <350>;
170a1ade6caSAbel Vesa		exit-latency-us = <461>;
171a1ade6caSAbel Vesa		min-residency-us = <1890>;
172a1ade6caSAbel Vesa		local-timer-stop;
173a1ade6caSAbel Vesa	};
174a1ade6caSAbel Vesa
175a1ade6caSAbel Vesa	LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
176a1ade6caSAbel Vesa		compatible = "arm,idle-state";
177a1ade6caSAbel Vesa		idle-state-name = "little-rail-power-down";
178a1ade6caSAbel Vesa		arm,psci-suspend-param = <0x40000004>;
179a1ade6caSAbel Vesa		entry-latency-us = <360>;
180a1ade6caSAbel Vesa		exit-latency-us = <531>;
181a1ade6caSAbel Vesa		min-residency-us = <3934>;
182a1ade6caSAbel Vesa		local-timer-stop;
183a1ade6caSAbel Vesa	};
184a1ade6caSAbel Vesa
185a1ade6caSAbel Vesa	BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
186a1ade6caSAbel Vesa		compatible = "arm,idle-state";
187a1ade6caSAbel Vesa		idle-state-name = "big-power-down";
188a1ade6caSAbel Vesa		arm,psci-suspend-param = <0x40000003>;
189a1ade6caSAbel Vesa		entry-latency-us = <264>;
190a1ade6caSAbel Vesa		exit-latency-us = <621>;
191a1ade6caSAbel Vesa		min-residency-us = <952>;
192a1ade6caSAbel Vesa		local-timer-stop;
193a1ade6caSAbel Vesa	};
194a1ade6caSAbel Vesa
195a1ade6caSAbel Vesa	BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
196a1ade6caSAbel Vesa		compatible = "arm,idle-state";
197a1ade6caSAbel Vesa		idle-state-name = "big-rail-power-down";
198a1ade6caSAbel Vesa		arm,psci-suspend-param = <0x40000004>;
199a1ade6caSAbel Vesa		entry-latency-us = <702>;
200a1ade6caSAbel Vesa		exit-latency-us = <1061>;
201a1ade6caSAbel Vesa		min-residency-us = <4488>;
202a1ade6caSAbel Vesa		local-timer-stop;
203a1ade6caSAbel Vesa	};
204a1ade6caSAbel Vesa
205a1ade6caSAbel Vesa	CLUSTER_SLEEP_0: cluster-sleep-0 {
206a1ade6caSAbel Vesa		compatible = "arm,idle-state";
207a1ade6caSAbel Vesa		idle-state-name = "cluster-power-down";
208a1ade6caSAbel Vesa		arm,psci-suspend-param = <0x400000F4>;
209a1ade6caSAbel Vesa		entry-latency-us = <3263>;
210a1ade6caSAbel Vesa		exit-latency-us = <6562>;
211a1ade6caSAbel Vesa		min-residency-us = <9987>;
212a1ade6caSAbel Vesa		local-timer-stop;
213a1ade6caSAbel Vesa	};
214a1ade6caSAbel Vesa};
215a1ade6caSAbel Vesa
216a1ade6caSAbel Vesa&CPU0 {
217a1ade6caSAbel Vesa	/delete-property/ power-domains;
218a1ade6caSAbel Vesa	/delete-property/ power-domain-names;
219a1ade6caSAbel Vesa	cpu-idle-states = <&LITTLE_CPU_SLEEP_0
220a1ade6caSAbel Vesa			   &LITTLE_CPU_SLEEP_1
221a1ade6caSAbel Vesa			   &CLUSTER_SLEEP_0>;
222a1ade6caSAbel Vesa};
223a1ade6caSAbel Vesa
224a1ade6caSAbel Vesa&CPU1 {
225a1ade6caSAbel Vesa	/delete-property/ power-domains;
226a1ade6caSAbel Vesa	/delete-property/ power-domain-names;
227a1ade6caSAbel Vesa	cpu-idle-states = <&LITTLE_CPU_SLEEP_0
228a1ade6caSAbel Vesa			   &LITTLE_CPU_SLEEP_1
229a1ade6caSAbel Vesa			   &CLUSTER_SLEEP_0>;
230a1ade6caSAbel Vesa};
231a1ade6caSAbel Vesa
232a1ade6caSAbel Vesa&CPU2 {
233a1ade6caSAbel Vesa	/delete-property/ power-domains;
234a1ade6caSAbel Vesa	/delete-property/ power-domain-names;
235a1ade6caSAbel Vesa	cpu-idle-states = <&LITTLE_CPU_SLEEP_0
236a1ade6caSAbel Vesa			   &LITTLE_CPU_SLEEP_1
237a1ade6caSAbel Vesa			   &CLUSTER_SLEEP_0>;
238a1ade6caSAbel Vesa};
239a1ade6caSAbel Vesa
240a1ade6caSAbel Vesa&CPU3 {
241a1ade6caSAbel Vesa	/delete-property/ power-domains;
242a1ade6caSAbel Vesa	/delete-property/ power-domain-names;
243a1ade6caSAbel Vesa	cpu-idle-states = <&LITTLE_CPU_SLEEP_0
244a1ade6caSAbel Vesa			   &LITTLE_CPU_SLEEP_1
245a1ade6caSAbel Vesa			   &CLUSTER_SLEEP_0>;
246a1ade6caSAbel Vesa};
247a1ade6caSAbel Vesa
248a1ade6caSAbel Vesa&CPU4 {
249a1ade6caSAbel Vesa	/delete-property/ power-domains;
250a1ade6caSAbel Vesa	/delete-property/ power-domain-names;
251a1ade6caSAbel Vesa	cpu-idle-states = <&BIG_CPU_SLEEP_0
252a1ade6caSAbel Vesa			   &BIG_CPU_SLEEP_1
253a1ade6caSAbel Vesa			   &CLUSTER_SLEEP_0>;
254a1ade6caSAbel Vesa};
255a1ade6caSAbel Vesa
256a1ade6caSAbel Vesa&CPU5 {
257a1ade6caSAbel Vesa	/delete-property/ power-domains;
258a1ade6caSAbel Vesa	/delete-property/ power-domain-names;
259a1ade6caSAbel Vesa	cpu-idle-states = <&BIG_CPU_SLEEP_0
260a1ade6caSAbel Vesa			   &BIG_CPU_SLEEP_1
261a1ade6caSAbel Vesa			   &CLUSTER_SLEEP_0>;
262a1ade6caSAbel Vesa};
263a1ade6caSAbel Vesa
264a1ade6caSAbel Vesa&CPU6 {
265a1ade6caSAbel Vesa	/delete-property/ power-domains;
266a1ade6caSAbel Vesa	/delete-property/ power-domain-names;
267a1ade6caSAbel Vesa	cpu-idle-states = <&BIG_CPU_SLEEP_0
268a1ade6caSAbel Vesa			   &BIG_CPU_SLEEP_1
269a1ade6caSAbel Vesa			   &CLUSTER_SLEEP_0>;
270a1ade6caSAbel Vesa};
271a1ade6caSAbel Vesa
272a1ade6caSAbel Vesa&CPU7 {
273a1ade6caSAbel Vesa	/delete-property/ power-domains;
274a1ade6caSAbel Vesa	/delete-property/ power-domain-names;
275a1ade6caSAbel Vesa	cpu-idle-states = <&BIG_CPU_SLEEP_0
276a1ade6caSAbel Vesa			   &BIG_CPU_SLEEP_1
277a1ade6caSAbel Vesa			   &CLUSTER_SLEEP_0>;
278a1ade6caSAbel Vesa};
279a1ade6caSAbel Vesa
28079e7739fSRob Clark/*
28179e7739fSRob Clark * Reserved memory changes
28279e7739fSRob Clark *
28379e7739fSRob Clark * Putting this all together (out of order with the rest of the file) to keep
28479e7739fSRob Clark * all modifications to the memory map (from sdm845.dtsi) in one place.
28579e7739fSRob Clark */
28679e7739fSRob Clark
28779e7739fSRob Clark/*
28879e7739fSRob Clark * Our mpss_region is 8MB bigger than the default one and that conflicts
28979e7739fSRob Clark * with venus_mem and cdsp_mem.
29079e7739fSRob Clark *
29179e7739fSRob Clark * For venus_mem we'll delete and re-create at a different address.
29279e7739fSRob Clark *
29379e7739fSRob Clark * cdsp_mem isn't used on cheza right now so we won't bother re-creating it; but
29479e7739fSRob Clark * that also means we need to delete cdsp_pas.
29579e7739fSRob Clark */
29679e7739fSRob Clark/delete-node/ &venus_mem;
29779e7739fSRob Clark/delete-node/ &cdsp_mem;
29879e7739fSRob Clark/delete-node/ &cdsp_pas;
29943b0a4b4SRob Clark/delete-node/ &gpu_mem;
30079e7739fSRob Clark
30179e7739fSRob Clark/* Increase the size from 120 MB to 128 MB */
30279e7739fSRob Clark&mpss_region {
30379e7739fSRob Clark	reg = <0 0x8e000000 0 0x8000000>;
30479e7739fSRob Clark};
30579e7739fSRob Clark
30679e7739fSRob Clark/* Increase the size from 2MB to 8MB */
30779e7739fSRob Clark&rmtfs_mem {
30879e7739fSRob Clark	reg = <0 0x88f00000 0 0x800000>;
30979e7739fSRob Clark};
31079e7739fSRob Clark
31179e7739fSRob Clark/ {
31279e7739fSRob Clark	reserved-memory {
31379e7739fSRob Clark		venus_mem: memory@96000000 {
31479e7739fSRob Clark			reg = <0 0x96000000 0 0x500000>;
31579e7739fSRob Clark			no-map;
31679e7739fSRob Clark		};
31779e7739fSRob Clark	};
31879e7739fSRob Clark};
31979e7739fSRob Clark
32079e7739fSRob Clark&qspi {
32179e7739fSRob Clark	status = "okay";
32279e7739fSRob Clark	pinctrl-names = "default";
32379e7739fSRob Clark	pinctrl-0 = <&qspi_clk &qspi_cs0 &qspi_data01>;
32479e7739fSRob Clark
32579e7739fSRob Clark	flash@0 {
32679e7739fSRob Clark		compatible = "jedec,spi-nor";
32779e7739fSRob Clark		reg = <0>;
32879e7739fSRob Clark
32979e7739fSRob Clark		/*
33079e7739fSRob Clark		 * In theory chip supports up to 104 MHz and controller up
33179e7739fSRob Clark		 * to 80 MHz, but above 25 MHz wasn't reliable so we'll use
33279e7739fSRob Clark		 * that for now.  b:117440651
33379e7739fSRob Clark		 */
33479e7739fSRob Clark		spi-max-frequency = <25000000>;
33579e7739fSRob Clark		spi-tx-bus-width = <2>;
33679e7739fSRob Clark		spi-rx-bus-width = <2>;
33779e7739fSRob Clark	};
33879e7739fSRob Clark};
33979e7739fSRob Clark
34079e7739fSRob Clark
34179e7739fSRob Clark&apps_rsc {
342*86dd19bbSKrzysztof Kozlowski	regulators-0 {
34379e7739fSRob Clark		compatible = "qcom,pm8998-rpmh-regulators";
34479e7739fSRob Clark		qcom,pmic-id = "a";
34579e7739fSRob Clark
34679e7739fSRob Clark		vdd-s1-supply = <&src_vph_pwr>;
34779e7739fSRob Clark		vdd-s2-supply = <&src_vph_pwr>;
34879e7739fSRob Clark		vdd-s3-supply = <&src_vph_pwr>;
34979e7739fSRob Clark		vdd-s4-supply = <&src_vph_pwr>;
35079e7739fSRob Clark		vdd-s5-supply = <&src_vph_pwr>;
35179e7739fSRob Clark		vdd-s6-supply = <&src_vph_pwr>;
35279e7739fSRob Clark		vdd-s7-supply = <&src_vph_pwr>;
35379e7739fSRob Clark		vdd-s8-supply = <&src_vph_pwr>;
35479e7739fSRob Clark		vdd-s9-supply = <&src_vph_pwr>;
35579e7739fSRob Clark		vdd-s10-supply = <&src_vph_pwr>;
35679e7739fSRob Clark		vdd-s11-supply = <&src_vph_pwr>;
35779e7739fSRob Clark		vdd-s12-supply = <&src_vph_pwr>;
35879e7739fSRob Clark		vdd-s13-supply = <&src_vph_pwr>;
35979e7739fSRob Clark		vdd-l1-l27-supply = <&src_pp1025_s7a>;
36079e7739fSRob Clark		vdd-l2-l8-l17-supply = <&src_pp1350_s3a>;
36179e7739fSRob Clark		vdd-l3-l11-supply = <&src_pp1025_s7a>;
36279e7739fSRob Clark		vdd-l4-l5-supply = <&src_pp1025_s7a>;
36379e7739fSRob Clark		vdd-l6-supply = <&src_vph_pwr>;
36479e7739fSRob Clark		vdd-l7-l12-l14-l15-supply = <&src_pp2040_s5a>;
36579e7739fSRob Clark		vdd-l9-supply = <&src_pp2040_s5a>;
36679e7739fSRob Clark		vdd-l10-l23-l25-supply = <&src_vreg_bob>;
36779e7739fSRob Clark		vdd-l13-l19-l21-supply = <&src_vreg_bob>;
36879e7739fSRob Clark		vdd-l16-l28-supply = <&src_vreg_bob>;
36979e7739fSRob Clark		vdd-l18-l22-supply = <&src_vreg_bob>;
37079e7739fSRob Clark		vdd-l20-l24-supply = <&src_vreg_bob>;
37179e7739fSRob Clark		vdd-l26-supply = <&src_pp1350_s3a>;
37279e7739fSRob Clark		vin-lvs-1-2-supply = <&src_pp1800_s4a>;
37379e7739fSRob Clark
37479e7739fSRob Clark		src_pp1125_s2a: smps2 {
37579e7739fSRob Clark			regulator-min-microvolt = <1100000>;
37679e7739fSRob Clark			regulator-max-microvolt = <1100000>;
37779e7739fSRob Clark		};
37879e7739fSRob Clark
37979e7739fSRob Clark		src_pp1350_s3a: smps3 {
38079e7739fSRob Clark			regulator-min-microvolt = <1352000>;
38179e7739fSRob Clark			regulator-max-microvolt = <1352000>;
38279e7739fSRob Clark		};
38379e7739fSRob Clark
38479e7739fSRob Clark		src_pp2040_s5a: smps5 {
38579e7739fSRob Clark			regulator-min-microvolt = <1904000>;
38679e7739fSRob Clark			regulator-max-microvolt = <2040000>;
38779e7739fSRob Clark		};
38879e7739fSRob Clark
38979e7739fSRob Clark		src_pp1025_s7a: smps7 {
39079e7739fSRob Clark			regulator-min-microvolt = <900000>;
39179e7739fSRob Clark			regulator-max-microvolt = <1028000>;
39279e7739fSRob Clark		};
39379e7739fSRob Clark
39479e7739fSRob Clark		vdd_qusb_hs0:
39579e7739fSRob Clark		vdda_hp_pcie_core:
39679e7739fSRob Clark		vdda_mipi_csi0_0p9:
39779e7739fSRob Clark		vdda_mipi_csi1_0p9:
39879e7739fSRob Clark		vdda_mipi_csi2_0p9:
39979e7739fSRob Clark		vdda_mipi_dsi0_pll:
40079e7739fSRob Clark		vdda_mipi_dsi1_pll:
40179e7739fSRob Clark		vdda_qlink_lv:
40279e7739fSRob Clark		vdda_qlink_lv_ck:
40379e7739fSRob Clark		vdda_qrefs_0p875:
40479e7739fSRob Clark		vdda_pcie_core:
40579e7739fSRob Clark		vdda_pll_cc_ebi01:
40679e7739fSRob Clark		vdda_pll_cc_ebi23:
40779e7739fSRob Clark		vdda_sp_sensor:
40879e7739fSRob Clark		vdda_ufs1_core:
40979e7739fSRob Clark		vdda_ufs2_core:
41079e7739fSRob Clark		vdda_usb1_ss_core:
41179e7739fSRob Clark		vdda_usb2_ss_core:
41279e7739fSRob Clark		src_pp875_l1a: ldo1 {
41379e7739fSRob Clark			regulator-min-microvolt = <880000>;
41479e7739fSRob Clark			regulator-max-microvolt = <880000>;
41579e7739fSRob Clark			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
41679e7739fSRob Clark		};
41779e7739fSRob Clark
41879e7739fSRob Clark		vddpx_10:
41979e7739fSRob Clark		src_pp1200_l2a: ldo2 {
42079e7739fSRob Clark			regulator-min-microvolt = <1200000>;
42179e7739fSRob Clark			regulator-max-microvolt = <1200000>;
42279e7739fSRob Clark			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
42379e7739fSRob Clark
42479e7739fSRob Clark			/* TODO: why??? */
42579e7739fSRob Clark			regulator-always-on;
42679e7739fSRob Clark		};
42779e7739fSRob Clark
42879e7739fSRob Clark		pp1000_l3a_sdr845: ldo3 {
42979e7739fSRob Clark			regulator-min-microvolt = <1000000>;
43079e7739fSRob Clark			regulator-max-microvolt = <1000000>;
43179e7739fSRob Clark			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
43279e7739fSRob Clark		};
43379e7739fSRob Clark
43479e7739fSRob Clark		vdd_wcss_cx:
43579e7739fSRob Clark		vdd_wcss_mx:
43679e7739fSRob Clark		vdda_wcss_pll:
43779e7739fSRob Clark		src_pp800_l5a: ldo5 {
43879e7739fSRob Clark			regulator-min-microvolt = <800000>;
43979e7739fSRob Clark			regulator-max-microvolt = <800000>;
44079e7739fSRob Clark			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
44179e7739fSRob Clark		};
44279e7739fSRob Clark
44379e7739fSRob Clark		vddpx_13:
44479e7739fSRob Clark		src_pp1800_l6a: ldo6 {
44579e7739fSRob Clark			regulator-min-microvolt = <1856000>;
44679e7739fSRob Clark			regulator-max-microvolt = <1856000>;
44779e7739fSRob Clark			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
44879e7739fSRob Clark		};
44979e7739fSRob Clark
45079e7739fSRob Clark		pp1800_l7a_wcn3990: ldo7 {
45179e7739fSRob Clark			regulator-min-microvolt = <1800000>;
45279e7739fSRob Clark			regulator-max-microvolt = <1800000>;
45379e7739fSRob Clark			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
45479e7739fSRob Clark		};
45579e7739fSRob Clark
45679e7739fSRob Clark		src_pp1200_l8a: ldo8 {
45779e7739fSRob Clark			regulator-min-microvolt = <1200000>;
45879e7739fSRob Clark			regulator-max-microvolt = <1248000>;
45979e7739fSRob Clark			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
46079e7739fSRob Clark		};
46179e7739fSRob Clark
46279e7739fSRob Clark		pp1800_dx_pen:
46379e7739fSRob Clark		src_pp1800_l9a: ldo9 {
46479e7739fSRob Clark			regulator-min-microvolt = <1800000>;
46579e7739fSRob Clark			regulator-max-microvolt = <1800000>;
46679e7739fSRob Clark			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
46779e7739fSRob Clark		};
46879e7739fSRob Clark
46979e7739fSRob Clark		src_pp1800_l10a: ldo10 {
47079e7739fSRob Clark			regulator-min-microvolt = <1800000>;
47179e7739fSRob Clark			regulator-max-microvolt = <1800000>;
47279e7739fSRob Clark			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
47379e7739fSRob Clark		};
47479e7739fSRob Clark
47579e7739fSRob Clark		pp1000_l11a_sdr845: ldo11 {
47679e7739fSRob Clark			regulator-min-microvolt = <1000000>;
47779e7739fSRob Clark			regulator-max-microvolt = <1048000>;
47879e7739fSRob Clark			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
47979e7739fSRob Clark		};
48079e7739fSRob Clark
48179e7739fSRob Clark		vdd_qfprom:
48279e7739fSRob Clark		vdd_qfprom_sp:
48379e7739fSRob Clark		vdda_apc1_cs_1p8:
48479e7739fSRob Clark		vdda_gfx_cs_1p8:
48579e7739fSRob Clark		vdda_qrefs_1p8:
48679e7739fSRob Clark		vdda_qusb_hs0_1p8:
48779e7739fSRob Clark		vddpx_11:
48879e7739fSRob Clark		src_pp1800_l12a: ldo12 {
48979e7739fSRob Clark			regulator-min-microvolt = <1800000>;
49079e7739fSRob Clark			regulator-max-microvolt = <1800000>;
49179e7739fSRob Clark			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
49279e7739fSRob Clark		};
49379e7739fSRob Clark
49479e7739fSRob Clark		vddpx_2:
49579e7739fSRob Clark		src_pp2950_l13a: ldo13 {
49679e7739fSRob Clark			regulator-min-microvolt = <1800000>;
49779e7739fSRob Clark			regulator-max-microvolt = <2960000>;
49879e7739fSRob Clark			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
49979e7739fSRob Clark		};
50079e7739fSRob Clark
50179e7739fSRob Clark		src_pp1800_l14a: ldo14 {
50279e7739fSRob Clark			regulator-min-microvolt = <1800000>;
50379e7739fSRob Clark			regulator-max-microvolt = <1800000>;
50479e7739fSRob Clark			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
50579e7739fSRob Clark		};
50679e7739fSRob Clark
50779e7739fSRob Clark		src_pp1800_l15a: ldo15 {
50879e7739fSRob Clark			regulator-min-microvolt = <1800000>;
50979e7739fSRob Clark			regulator-max-microvolt = <1800000>;
51079e7739fSRob Clark			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
51179e7739fSRob Clark		};
51279e7739fSRob Clark
51379e7739fSRob Clark		pp2700_l16a: ldo16 {
51479e7739fSRob Clark			regulator-min-microvolt = <2704000>;
51579e7739fSRob Clark			regulator-max-microvolt = <2704000>;
51679e7739fSRob Clark			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
51779e7739fSRob Clark		};
51879e7739fSRob Clark
51979e7739fSRob Clark		src_pp1300_l17a: ldo17 {
52079e7739fSRob Clark			regulator-min-microvolt = <1304000>;
52179e7739fSRob Clark			regulator-max-microvolt = <1304000>;
52279e7739fSRob Clark			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
52379e7739fSRob Clark		};
52479e7739fSRob Clark
52579e7739fSRob Clark		pp2700_l18a: ldo18 {
52679e7739fSRob Clark			regulator-min-microvolt = <2704000>;
52779e7739fSRob Clark			regulator-max-microvolt = <2960000>;
52879e7739fSRob Clark			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
52979e7739fSRob Clark		};
53079e7739fSRob Clark
53179e7739fSRob Clark		/*
53279e7739fSRob Clark		 * NOTE: this rail should have been called
53379e7739fSRob Clark		 * src_pp3300_l19a in the schematic
53479e7739fSRob Clark		 */
53579e7739fSRob Clark		src_pp3000_l19a: ldo19 {
53679e7739fSRob Clark			regulator-min-microvolt = <3304000>;
53779e7739fSRob Clark			regulator-max-microvolt = <3304000>;
53879e7739fSRob Clark
53979e7739fSRob Clark			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
54079e7739fSRob Clark		};
54179e7739fSRob Clark
54279e7739fSRob Clark		src_pp2950_l20a: ldo20 {
54379e7739fSRob Clark			regulator-min-microvolt = <2704000>;
54479e7739fSRob Clark			regulator-max-microvolt = <2960000>;
54579e7739fSRob Clark			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
54679e7739fSRob Clark		};
54779e7739fSRob Clark
54879e7739fSRob Clark		src_pp2950_l21a: ldo21 {
54979e7739fSRob Clark			regulator-min-microvolt = <2704000>;
55079e7739fSRob Clark			regulator-max-microvolt = <2960000>;
55179e7739fSRob Clark			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
55279e7739fSRob Clark		};
55379e7739fSRob Clark
55479e7739fSRob Clark		pp3300_hub:
55579e7739fSRob Clark		src_pp3300_l22a: ldo22 {
55679e7739fSRob Clark			regulator-min-microvolt = <3304000>;
55779e7739fSRob Clark			regulator-max-microvolt = <3304000>;
55879e7739fSRob Clark			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
55979e7739fSRob Clark			/*
56079e7739fSRob Clark			 * HACK: Should add a usb hub node and driver
56179e7739fSRob Clark			 * to turn this on and off at suspend/resume time
56279e7739fSRob Clark			 */
56379e7739fSRob Clark			regulator-boot-on;
56479e7739fSRob Clark			regulator-always-on;
56579e7739fSRob Clark		};
56679e7739fSRob Clark
56779e7739fSRob Clark		pp3300_l23a_ch1_wcn3990: ldo23 {
56879e7739fSRob Clark			regulator-min-microvolt = <3000000>;
56979e7739fSRob Clark			regulator-max-microvolt = <3312000>;
57079e7739fSRob Clark			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
57179e7739fSRob Clark		};
57279e7739fSRob Clark
57379e7739fSRob Clark		vdda_qusb_hs0_3p1:
57479e7739fSRob Clark		src_pp3075_l24a: ldo24 {
57579e7739fSRob Clark			regulator-min-microvolt = <3088000>;
57679e7739fSRob Clark			regulator-max-microvolt = <3088000>;
57779e7739fSRob Clark			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
57879e7739fSRob Clark		};
57979e7739fSRob Clark
58079e7739fSRob Clark		pp3300_l25a_ch0_wcn3990: ldo25 {
58179e7739fSRob Clark			regulator-min-microvolt = <3304000>;
58279e7739fSRob Clark			regulator-max-microvolt = <3304000>;
58379e7739fSRob Clark			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
58479e7739fSRob Clark		};
58579e7739fSRob Clark
58679e7739fSRob Clark		pp1200_hub:
58779e7739fSRob Clark		vdda_hp_pcie_1p2:
58879e7739fSRob Clark		vdda_hv_ebi0:
58979e7739fSRob Clark		vdda_hv_ebi1:
59079e7739fSRob Clark		vdda_hv_ebi2:
59179e7739fSRob Clark		vdda_hv_ebi3:
59279e7739fSRob Clark		vdda_mipi_csi_1p25:
59379e7739fSRob Clark		vdda_mipi_dsi0_1p2:
59479e7739fSRob Clark		vdda_mipi_dsi1_1p2:
59579e7739fSRob Clark		vdda_pcie_1p2:
59679e7739fSRob Clark		vdda_ufs1_1p2:
59779e7739fSRob Clark		vdda_ufs2_1p2:
59879e7739fSRob Clark		vdda_usb1_ss_1p2:
59979e7739fSRob Clark		vdda_usb2_ss_1p2:
60079e7739fSRob Clark		src_pp1200_l26a: ldo26 {
60179e7739fSRob Clark			regulator-min-microvolt = <1200000>;
60279e7739fSRob Clark			regulator-max-microvolt = <1200000>;
60379e7739fSRob Clark			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
60479e7739fSRob Clark		};
60579e7739fSRob Clark
60679e7739fSRob Clark		pp3300_dx_pen:
60779e7739fSRob Clark		src_pp3300_l28a: ldo28 {
60879e7739fSRob Clark			regulator-min-microvolt = <3304000>;
60979e7739fSRob Clark			regulator-max-microvolt = <3304000>;
61079e7739fSRob Clark			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
61179e7739fSRob Clark		};
61279e7739fSRob Clark
61379e7739fSRob Clark		src_pp1800_lvs1: lvs1 {
61479e7739fSRob Clark			regulator-min-microvolt = <1800000>;
61579e7739fSRob Clark			regulator-max-microvolt = <1800000>;
61679e7739fSRob Clark		};
61779e7739fSRob Clark
61879e7739fSRob Clark		src_pp1800_lvs2: lvs2 {
61979e7739fSRob Clark			regulator-min-microvolt = <1800000>;
62079e7739fSRob Clark			regulator-max-microvolt = <1800000>;
62179e7739fSRob Clark		};
62279e7739fSRob Clark	};
62379e7739fSRob Clark
624*86dd19bbSKrzysztof Kozlowski	regulators-1 {
62579e7739fSRob Clark		compatible = "qcom,pm8005-rpmh-regulators";
62679e7739fSRob Clark		qcom,pmic-id = "c";
62779e7739fSRob Clark
62879e7739fSRob Clark		vdd-s1-supply = <&src_vph_pwr>;
62979e7739fSRob Clark		vdd-s2-supply = <&src_vph_pwr>;
63079e7739fSRob Clark		vdd-s3-supply = <&src_vph_pwr>;
63179e7739fSRob Clark		vdd-s4-supply = <&src_vph_pwr>;
63279e7739fSRob Clark
63379e7739fSRob Clark		src_pp600_s3c: smps3 {
63479e7739fSRob Clark			regulator-min-microvolt = <600000>;
63579e7739fSRob Clark			regulator-max-microvolt = <600000>;
63679e7739fSRob Clark		};
63779e7739fSRob Clark	};
63879e7739fSRob Clark};
63979e7739fSRob Clark
64079e7739fSRob Clark&dsi0 {
64179e7739fSRob Clark	status = "okay";
64279e7739fSRob Clark	vdda-supply = <&vdda_mipi_dsi0_1p2>;
64379e7739fSRob Clark
64479e7739fSRob Clark	ports {
64579e7739fSRob Clark		port@1 {
64679e7739fSRob Clark			endpoint {
64779e7739fSRob Clark				remote-endpoint = <&sn65dsi86_in>;
64879e7739fSRob Clark				data-lanes = <0 1 2 3>;
64979e7739fSRob Clark			};
65079e7739fSRob Clark		};
65179e7739fSRob Clark	};
65279e7739fSRob Clark};
65379e7739fSRob Clark
65479e7739fSRob Clark&dsi0_phy {
65579e7739fSRob Clark	status = "okay";
65679e7739fSRob Clark	vdds-supply = <&vdda_mipi_dsi0_pll>;
65779e7739fSRob Clark};
65879e7739fSRob Clark
65979e7739fSRob Clarkedp_brij_i2c: &i2c3 {
66079e7739fSRob Clark	status = "okay";
66179e7739fSRob Clark	clock-frequency = <400000>;
66279e7739fSRob Clark
66379e7739fSRob Clark	sn65dsi86_bridge: bridge@2d {
66479e7739fSRob Clark		compatible = "ti,sn65dsi86";
66579e7739fSRob Clark		reg = <0x2d>;
66679e7739fSRob Clark		pinctrl-names = "default";
66779e7739fSRob Clark		pinctrl-0 = <&edp_brij_en &edp_brij_irq>;
66879e7739fSRob Clark
66979e7739fSRob Clark		interrupt-parent = <&tlmm>;
67079e7739fSRob Clark		interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
67179e7739fSRob Clark
67279e7739fSRob Clark		enable-gpios = <&tlmm 102 GPIO_ACTIVE_HIGH>;
67379e7739fSRob Clark
67479e7739fSRob Clark		vpll-supply = <&src_pp1800_s4a>;
67579e7739fSRob Clark		vccio-supply = <&src_pp1800_s4a>;
67679e7739fSRob Clark		vcca-supply = <&src_pp1200_l2a>;
67779e7739fSRob Clark		vcc-supply = <&src_pp1200_l2a>;
67879e7739fSRob Clark
67979e7739fSRob Clark		clocks = <&rpmhcc RPMH_LN_BB_CLK2>;
68079e7739fSRob Clark		clock-names = "refclk";
68179e7739fSRob Clark
6820d1ce0d1SDouglas Anderson		no-hpd;
6830d1ce0d1SDouglas Anderson
68479e7739fSRob Clark		ports {
68579e7739fSRob Clark			#address-cells = <1>;
68679e7739fSRob Clark			#size-cells = <0>;
68779e7739fSRob Clark
68879e7739fSRob Clark			port@0 {
68979e7739fSRob Clark				reg = <0>;
69079e7739fSRob Clark				sn65dsi86_in: endpoint {
69179e7739fSRob Clark					remote-endpoint = <&dsi0_out>;
69279e7739fSRob Clark				};
69379e7739fSRob Clark			};
69479e7739fSRob Clark
69579e7739fSRob Clark			port@1 {
69679e7739fSRob Clark				reg = <1>;
69779e7739fSRob Clark				sn65dsi86_out: endpoint {
69879e7739fSRob Clark					remote-endpoint = <&panel_in_edp>;
69979e7739fSRob Clark				};
70079e7739fSRob Clark			};
70179e7739fSRob Clark		};
70279e7739fSRob Clark	};
70379e7739fSRob Clark};
70479e7739fSRob Clark
70579e7739fSRob Clarkap_pen_1v8: &i2c11 {
70679e7739fSRob Clark	status = "okay";
70779e7739fSRob Clark	clock-frequency = <400000>;
70879e7739fSRob Clark
70979e7739fSRob Clark	digitizer@9 {
71079e7739fSRob Clark		compatible = "wacom,w9013", "hid-over-i2c";
71179e7739fSRob Clark		reg = <0x9>;
71279e7739fSRob Clark		pinctrl-names = "default";
71379e7739fSRob Clark		pinctrl-0 = <&pen_irq_l>, <&pen_pdct_l>, <&pen_rst_l>;
71479e7739fSRob Clark
71579e7739fSRob Clark		vdd-supply = <&pp3300_dx_pen>;
71679e7739fSRob Clark		vddl-supply = <&pp1800_dx_pen>;
71779e7739fSRob Clark		post-power-on-delay-ms = <100>;
71879e7739fSRob Clark
71979e7739fSRob Clark		interrupt-parent = <&tlmm>;
72079e7739fSRob Clark		interrupts = <24 IRQ_TYPE_LEVEL_LOW>;
72179e7739fSRob Clark
72279e7739fSRob Clark		hid-descr-addr = <0x1>;
72379e7739fSRob Clark	};
72479e7739fSRob Clark};
72579e7739fSRob Clark
72679e7739fSRob Clarkamp_i2c: &i2c12 {
72779e7739fSRob Clark	status = "okay";
72879e7739fSRob Clark	clock-frequency = <400000>;
72979e7739fSRob Clark};
73079e7739fSRob Clark
73179e7739fSRob Clarkap_ts_i2c: &i2c14 {
73279e7739fSRob Clark	status = "okay";
73379e7739fSRob Clark	clock-frequency = <400000>;
73479e7739fSRob Clark
73579e7739fSRob Clark	touchscreen@10 {
73679e7739fSRob Clark		compatible = "elan,ekth3500";
73779e7739fSRob Clark		reg = <0x10>;
73879e7739fSRob Clark		pinctrl-names = "default";
73979e7739fSRob Clark		pinctrl-0 = <&ts_int_l &ts_reset_l>;
74079e7739fSRob Clark
74179e7739fSRob Clark		interrupt-parent = <&tlmm>;
74279e7739fSRob Clark		interrupts = <125 IRQ_TYPE_LEVEL_LOW>;
74379e7739fSRob Clark
74479e7739fSRob Clark		vcc33-supply = <&src_pp3300_l28a>;
74579e7739fSRob Clark
74679e7739fSRob Clark		reset-gpios = <&tlmm 118 GPIO_ACTIVE_LOW>;
74779e7739fSRob Clark	};
74879e7739fSRob Clark};
74979e7739fSRob Clark
7507f761609SKonrad Dybcio&gmu {
7517f761609SKonrad Dybcio	status = "okay";
7527f761609SKonrad Dybcio};
7537f761609SKonrad Dybcio
7547f761609SKonrad Dybcio&gpu {
7557f761609SKonrad Dybcio	status = "okay";
7567f761609SKonrad Dybcio};
7577f761609SKonrad Dybcio
758392a5855SAlex Elder&ipa {
759a9a9e857SAlex Elder	qcom,gsi-loader = "modem";
760392a5855SAlex Elder	status = "okay";
761392a5855SAlex Elder};
762392a5855SAlex Elder
76379e7739fSRob Clark&lpasscc {
76479e7739fSRob Clark	status = "okay";
76579e7739fSRob Clark};
76679e7739fSRob Clark
76779e7739fSRob Clark&mdss {
76879e7739fSRob Clark	status = "okay";
76979e7739fSRob Clark};
77079e7739fSRob Clark
7717e5258b0SJordan Crouse/*
7727e5258b0SJordan Crouse * Cheza fw does not properly program the GPU aperture to allow the
7737e5258b0SJordan Crouse * GPU to update the SMMU pagetables for context switches.  Work
7747e5258b0SJordan Crouse * around this by dropping the "qcom,adreno-smmu" compat string.
7757e5258b0SJordan Crouse */
7767e5258b0SJordan Crouse&adreno_smmu {
7777e5258b0SJordan Crouse	compatible = "qcom,sdm845-smmu-v2", "qcom,smmu-v2";
7787e5258b0SJordan Crouse};
7797e5258b0SJordan Crouse
78068aee4afSSibi Sankar&mss_pil {
7817f761609SKonrad Dybcio	status = "okay";
7827f761609SKonrad Dybcio
78308257610SSibi Sankar	iommus = <&apps_smmu 0x781 0x0>,
78468aee4afSSibi Sankar		 <&apps_smmu 0x724 0x3>;
78568aee4afSSibi Sankar};
78668aee4afSSibi Sankar
78731a233a5SStephen Boyd&pm8998_pwrkey {
78831a233a5SStephen Boyd	status = "disabled";
78931a233a5SStephen Boyd};
79031a233a5SStephen Boyd
79179e7739fSRob Clark&qupv3_id_0 {
79279e7739fSRob Clark	status = "okay";
7934785cff7SStephen Boyd	iommus = <&apps_smmu 0x0 0x3>;
79479e7739fSRob Clark};
79579e7739fSRob Clark
79679e7739fSRob Clark&qupv3_id_1 {
79779e7739fSRob Clark	status = "okay";
7984785cff7SStephen Boyd	iommus = <&apps_smmu 0x6c0 0x3>;
79979e7739fSRob Clark};
80079e7739fSRob Clark
80179e7739fSRob Clark&sdhc_2 {
80279e7739fSRob Clark	status = "okay";
80379e7739fSRob Clark
80479e7739fSRob Clark	pinctrl-names = "default";
80579e7739fSRob Clark	pinctrl-0 = <&sdc2_clk &sdc2_cmd &sdc2_data &sd_cd_odl>;
80679e7739fSRob Clark
80779e7739fSRob Clark	vmmc-supply = <&src_pp2950_l21a>;
80879e7739fSRob Clark	vqmmc-supply = <&vddpx_2>;
80979e7739fSRob Clark
81079e7739fSRob Clark	cd-gpios = <&tlmm 44 GPIO_ACTIVE_LOW>;
81179e7739fSRob Clark};
81279e7739fSRob Clark
81379e7739fSRob Clark&spi0 {
81479e7739fSRob Clark	status = "okay";
81579e7739fSRob Clark};
81679e7739fSRob Clark
81739523c56SStephen Boyd&spi5 {
81839523c56SStephen Boyd	status = "okay";
81939523c56SStephen Boyd
82039523c56SStephen Boyd	tpm@0 {
82139523c56SStephen Boyd		compatible = "google,cr50";
82239523c56SStephen Boyd		reg = <0>;
82339523c56SStephen Boyd		pinctrl-names = "default";
82439523c56SStephen Boyd		pinctrl-0 = <&h1_ap_int_odl>;
82539523c56SStephen Boyd		spi-max-frequency = <800000>;
82639523c56SStephen Boyd		interrupt-parent = <&tlmm>;
82739523c56SStephen Boyd		interrupts = <129 IRQ_TYPE_EDGE_RISING>;
82839523c56SStephen Boyd	};
82939523c56SStephen Boyd};
83039523c56SStephen Boyd
83179e7739fSRob Clark&spi10 {
83279e7739fSRob Clark	status = "okay";
83379e7739fSRob Clark
83479e7739fSRob Clark	cros_ec: ec@0 {
83579e7739fSRob Clark		compatible = "google,cros-ec-spi";
83679e7739fSRob Clark		reg = <0>;
83779e7739fSRob Clark		interrupt-parent = <&tlmm>;
83879e7739fSRob Clark		interrupts = <122 IRQ_TYPE_LEVEL_LOW>;
83979e7739fSRob Clark		pinctrl-names = "default";
84079e7739fSRob Clark		pinctrl-0 = <&ec_ap_int_l>;
84179e7739fSRob Clark		spi-max-frequency = <3000000>;
84279e7739fSRob Clark
8431e49defbSKrzysztof Kozlowski		cros_ec_pwm: pwm {
84479e7739fSRob Clark			compatible = "google,cros-ec-pwm";
84579e7739fSRob Clark			#pwm-cells = <1>;
84679e7739fSRob Clark		};
84779e7739fSRob Clark
84879e7739fSRob Clark		i2c_tunnel: i2c-tunnel {
84979e7739fSRob Clark			compatible = "google,cros-ec-i2c-tunnel";
85079e7739fSRob Clark			google,remote-bus = <0>;
85179e7739fSRob Clark			#address-cells = <1>;
85279e7739fSRob Clark			#size-cells = <0>;
85379e7739fSRob Clark		};
85479e7739fSRob Clark	};
85579e7739fSRob Clark};
85679e7739fSRob Clark
85779e7739fSRob Clark#include <arm/cros-ec-keyboard.dtsi>
85879e7739fSRob Clark#include <arm/cros-ec-sbs.dtsi>
85979e7739fSRob Clark
86079e7739fSRob Clark&uart6 {
86179e7739fSRob Clark	status = "okay";
86279e7739fSRob Clark
863691dfbf5SCaleb Connolly	pinctrl-0 = <&qup_uart6_4pin>;
864691dfbf5SCaleb Connolly
865f7aaaf30SKrzysztof Kozlowski	bluetooth: bluetooth {
86679e7739fSRob Clark		compatible = "qcom,wcn3990-bt";
86779e7739fSRob Clark		vddio-supply = <&src_pp1800_s4a>;
86879e7739fSRob Clark		vddxo-supply = <&pp1800_l7a_wcn3990>;
86979e7739fSRob Clark		vddrf-supply = <&src_pp1300_l17a>;
87079e7739fSRob Clark		vddch0-supply = <&pp3300_l25a_ch0_wcn3990>;
87179e7739fSRob Clark		max-speed = <3200000>;
87279e7739fSRob Clark	};
87379e7739fSRob Clark};
87479e7739fSRob Clark
87579e7739fSRob Clark&uart9 {
87679e7739fSRob Clark	status = "okay";
87779e7739fSRob Clark};
87879e7739fSRob Clark
87979e7739fSRob Clark&ufs_mem_hc {
88079e7739fSRob Clark	status = "okay";
88110e99d47SStephen Boyd
88210e99d47SStephen Boyd	reset-gpios = <&tlmm 150 GPIO_ACTIVE_LOW>;
88379e7739fSRob Clark
88479e7739fSRob Clark	vcc-supply = <&src_pp2950_l20a>;
88579e7739fSRob Clark	vcc-max-microamp = <600000>;
88679e7739fSRob Clark};
88779e7739fSRob Clark
88879e7739fSRob Clark&ufs_mem_phy {
88979e7739fSRob Clark	status = "okay";
89079e7739fSRob Clark
89179e7739fSRob Clark	vdda-phy-supply = <&vdda_ufs1_core>;
89279e7739fSRob Clark	vdda-pll-supply = <&vdda_ufs1_1p2>;
89379e7739fSRob Clark};
89479e7739fSRob Clark
89579e7739fSRob Clark&usb_1 {
89679e7739fSRob Clark	status = "okay";
89779e7739fSRob Clark
89879e7739fSRob Clark	/* We'll use this as USB 2.0 only */
89979e7739fSRob Clark	qcom,select-utmi-as-pipe-clk;
90079e7739fSRob Clark};
90179e7739fSRob Clark
90279e7739fSRob Clark&usb_1_dwc3 {
90379e7739fSRob Clark	/*
90479e7739fSRob Clark	 * The hardware design intends this port to be hooked up in peripheral
90579e7739fSRob Clark	 * mode, so we'll hardcode it here.  Some details:
90679e7739fSRob Clark	 * - SDM845 expects only a single Type C connector so it has only one
90779e7739fSRob Clark	 *   native Type C port but cheza has two Type C connectors.
90879e7739fSRob Clark	 * - The only source of DP is the single native Type C port.
90979e7739fSRob Clark	 * - On cheza we want to be able to hook DP up to _either_ of the
91079e7739fSRob Clark	 *   two Type C connectors and want to be able to achieve 4 lanes of DP.
91179e7739fSRob Clark	 * - When you configure a Type C port for 4 lanes of DP you lose USB3.
91279e7739fSRob Clark	 * - In order to make everything work, the native Type C port is always
91379e7739fSRob Clark	 *   configured as 4-lanes DP so it's always available.
91479e7739fSRob Clark	 * - The extra USB3 port on SDM845 goes to a USB 3 hub which is then
91579e7739fSRob Clark	 *   sent to the two Type C connectors.
91679e7739fSRob Clark	 * - The extra USB2 lines from the native Type C port are always
91779e7739fSRob Clark	 *   setup as "peripheral" so that we can mux them over to one connector
91879e7739fSRob Clark	 *   or the other if someone needs the connector configured as a gadget
91979e7739fSRob Clark	 *   (but they only get USB2 speeds).
92079e7739fSRob Clark	 *
92179e7739fSRob Clark	 * All the hardware muxes would allow us to hook things up in different
92279e7739fSRob Clark	 * ways to some potential benefit for static configurations (you could
92379e7739fSRob Clark	 * achieve extra USB2 bandwidth by using two different ports for the
924e3c5bc56SGeert Uytterhoeven	 * two connectors or possibly even get USB3 peripheral mode), but in
92579e7739fSRob Clark	 * each case you end up forcing to disconnect/reconnect an in-use
92679e7739fSRob Clark	 * USB session in some cases depending on what you hotplug into the
92779e7739fSRob Clark	 * other connector.  Thus hardcoding this as peripheral makes sense.
92879e7739fSRob Clark	 */
92979e7739fSRob Clark	dr_mode = "peripheral";
93079e7739fSRob Clark
93179e7739fSRob Clark	/*
93279e7739fSRob Clark	 * We always need the high speed pins as 4-lanes DP in case someone
93379e7739fSRob Clark	 * hotplugs a DP peripheral.  Thus limit this port to a max of high
93479e7739fSRob Clark	 * speed.
93579e7739fSRob Clark	 */
93679e7739fSRob Clark	maximum-speed = "high-speed";
93779e7739fSRob Clark
93879e7739fSRob Clark	/*
93979e7739fSRob Clark	 * We don't need the usb3-phy since we run in highspeed mode always, so
94079e7739fSRob Clark	 * re-define these properties removing the superspeed USB PHY reference.
94179e7739fSRob Clark	 */
94279e7739fSRob Clark	phys = <&usb_1_hsphy>;
94379e7739fSRob Clark	phy-names = "usb2-phy";
94479e7739fSRob Clark};
94579e7739fSRob Clark
94679e7739fSRob Clark&usb_1_hsphy {
94779e7739fSRob Clark	status = "okay";
94879e7739fSRob Clark
94979e7739fSRob Clark	vdd-supply = <&vdda_usb1_ss_core>;
95079e7739fSRob Clark	vdda-pll-supply = <&vdda_qusb_hs0_1p8>;
95179e7739fSRob Clark	vdda-phy-dpdm-supply = <&vdda_qusb_hs0_3p1>;
95279e7739fSRob Clark
95379e7739fSRob Clark	qcom,imp-res-offset-value = <8>;
95479e7739fSRob Clark	qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_21_6_MA>;
95579e7739fSRob Clark	qcom,preemphasis-level = <QUSB2_V2_PREEMPHASIS_5_PERCENT>;
95679e7739fSRob Clark	qcom,preemphasis-width = <QUSB2_V2_PREEMPHASIS_WIDTH_HALF_BIT>;
95779e7739fSRob Clark};
95879e7739fSRob Clark
95979e7739fSRob Clark&usb_2 {
96079e7739fSRob Clark	status = "okay";
96179e7739fSRob Clark};
96279e7739fSRob Clark
96379e7739fSRob Clark&usb_2_dwc3 {
96479e7739fSRob Clark	/* We have this hooked up to a hub and we always use in host mode */
96579e7739fSRob Clark	dr_mode = "host";
96679e7739fSRob Clark};
96779e7739fSRob Clark
96879e7739fSRob Clark&usb_2_hsphy {
96979e7739fSRob Clark	status = "okay";
97079e7739fSRob Clark
97179e7739fSRob Clark	vdd-supply = <&vdda_usb2_ss_core>;
97279e7739fSRob Clark	vdda-pll-supply = <&vdda_qusb_hs0_1p8>;
97379e7739fSRob Clark	vdda-phy-dpdm-supply = <&vdda_qusb_hs0_3p1>;
97479e7739fSRob Clark
97579e7739fSRob Clark	qcom,imp-res-offset-value = <8>;
97679e7739fSRob Clark	qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_22_8_MA>;
97779e7739fSRob Clark};
97879e7739fSRob Clark
97979e7739fSRob Clark&usb_2_qmpphy {
98079e7739fSRob Clark	status = "okay";
98179e7739fSRob Clark
98279e7739fSRob Clark	vdda-phy-supply = <&vdda_usb2_ss_1p2>;
98379e7739fSRob Clark	vdda-pll-supply = <&vdda_usb2_ss_core>;
98479e7739fSRob Clark};
98579e7739fSRob Clark
98679e7739fSRob Clark&wifi {
98779e7739fSRob Clark	status = "okay";
98879e7739fSRob Clark
98979e7739fSRob Clark	vdd-0.8-cx-mx-supply = <&src_pp800_l5a >;
99079e7739fSRob Clark	vdd-1.8-xo-supply = <&pp1800_l7a_wcn3990>;
99179e7739fSRob Clark	vdd-1.3-rfa-supply = <&src_pp1300_l17a>;
99279e7739fSRob Clark	vdd-3.3-ch0-supply = <&pp3300_l25a_ch0_wcn3990>;
99379e7739fSRob Clark};
99479e7739fSRob Clark
99579e7739fSRob Clark/* PINCTRL - additions to nodes defined in sdm845.dtsi */
99679e7739fSRob Clark
99779e7739fSRob Clark&qspi_cs0 {
99879e7739fSRob Clark	bias-disable;
99979e7739fSRob Clark};
100079e7739fSRob Clark
100179e7739fSRob Clark&qspi_clk {
100279e7739fSRob Clark	bias-disable;
100379e7739fSRob Clark};
100479e7739fSRob Clark
100579e7739fSRob Clark&qspi_data01 {
100679e7739fSRob Clark	/* High-Z when no transfers; nice to park the lines */
100779e7739fSRob Clark	bias-pull-up;
100879e7739fSRob Clark};
100979e7739fSRob Clark
101079e7739fSRob Clark&qup_i2c3_default {
101179e7739fSRob Clark	drive-strength = <2>;
101279e7739fSRob Clark
101379e7739fSRob Clark	/* Has external pullup */
101479e7739fSRob Clark	bias-disable;
101579e7739fSRob Clark};
101679e7739fSRob Clark
101779e7739fSRob Clark&qup_i2c11_default {
101879e7739fSRob Clark	drive-strength = <2>;
101979e7739fSRob Clark
102079e7739fSRob Clark	/* Has external pullup */
102179e7739fSRob Clark	bias-disable;
102279e7739fSRob Clark};
102379e7739fSRob Clark
102479e7739fSRob Clark&qup_i2c12_default {
102579e7739fSRob Clark	drive-strength = <2>;
102679e7739fSRob Clark
102779e7739fSRob Clark	/* Has external pullup */
102879e7739fSRob Clark	bias-disable;
102979e7739fSRob Clark};
103079e7739fSRob Clark
103179e7739fSRob Clark&qup_i2c14_default {
103279e7739fSRob Clark	drive-strength = <2>;
103379e7739fSRob Clark
103479e7739fSRob Clark	/* Has external pullup */
103579e7739fSRob Clark	bias-disable;
103679e7739fSRob Clark};
103779e7739fSRob Clark
103879e7739fSRob Clark&qup_spi0_default {
103979e7739fSRob Clark	drive-strength = <2>;
104079e7739fSRob Clark	bias-disable;
104179e7739fSRob Clark};
104279e7739fSRob Clark
104379e7739fSRob Clark&qup_spi5_default {
104479e7739fSRob Clark	drive-strength = <2>;
104579e7739fSRob Clark	bias-disable;
104679e7739fSRob Clark};
104779e7739fSRob Clark
104879e7739fSRob Clark&qup_spi10_default {
104979e7739fSRob Clark	drive-strength = <2>;
105079e7739fSRob Clark	bias-disable;
105179e7739fSRob Clark};
105279e7739fSRob Clark
1053d05e3428SKrzysztof Kozlowski&qup_uart9_rx {
105479e7739fSRob Clark	drive-strength = <2>;
105579e7739fSRob Clark	bias-pull-up;
105679e7739fSRob Clark};
1057d05e3428SKrzysztof Kozlowski
1058d05e3428SKrzysztof Kozlowski&qup_uart9_tx {
1059d05e3428SKrzysztof Kozlowski	drive-strength = <2>;
1060d05e3428SKrzysztof Kozlowski	bias-disable;
106179e7739fSRob Clark};
106279e7739fSRob Clark
106379e7739fSRob Clark/* PINCTRL - board-specific pinctrl */
1064ea25d61bSMarijn Suijten&pm8005_gpios {
106579e7739fSRob Clark	gpio-line-names = "",
106679e7739fSRob Clark			  "",
106779e7739fSRob Clark			  "SLB",
106879e7739fSRob Clark			  "";
106979e7739fSRob Clark};
107079e7739fSRob Clark
107179e7739fSRob Clark&pm8998_adc {
10722833d79cSVinod Koul	adc-chan@4d {
107379e7739fSRob Clark		reg = <ADC5_AMUX_THM1_100K_PU>;
107479e7739fSRob Clark		label = "sdm_temp";
107579e7739fSRob Clark	};
107679e7739fSRob Clark
10772833d79cSVinod Koul	adc-chan@4e {
107879e7739fSRob Clark		reg = <ADC5_AMUX_THM2_100K_PU>;
107979e7739fSRob Clark		label = "quiet_temp";
108079e7739fSRob Clark	};
108179e7739fSRob Clark
10822833d79cSVinod Koul	adc-chan@4f {
108379e7739fSRob Clark		reg = <ADC5_AMUX_THM3_100K_PU>;
108479e7739fSRob Clark		label = "lte_temp_1";
108579e7739fSRob Clark	};
108679e7739fSRob Clark
10872833d79cSVinod Koul	adc-chan@50 {
108879e7739fSRob Clark		reg = <ADC5_AMUX_THM4_100K_PU>;
108979e7739fSRob Clark		label = "lte_temp_2";
109079e7739fSRob Clark	};
109179e7739fSRob Clark
10922833d79cSVinod Koul	adc-chan@51 {
109379e7739fSRob Clark		reg = <ADC5_AMUX_THM5_100K_PU>;
109479e7739fSRob Clark		label = "charger_temp";
109579e7739fSRob Clark	};
109679e7739fSRob Clark};
109779e7739fSRob Clark
1098ea25d61bSMarijn Suijten&pm8998_gpios {
109979e7739fSRob Clark	gpio-line-names = "",
110079e7739fSRob Clark			  "",
110179e7739fSRob Clark			  "SW_CTRL",
110279e7739fSRob Clark			  "",
110379e7739fSRob Clark			  "",
110479e7739fSRob Clark			  "",
110579e7739fSRob Clark			  "",
110679e7739fSRob Clark			  "",
110779e7739fSRob Clark			  "",
110879e7739fSRob Clark			  "",
110979e7739fSRob Clark			  "",
111079e7739fSRob Clark			  "",
111179e7739fSRob Clark			  "",
111279e7739fSRob Clark			  "",
111379e7739fSRob Clark			  "",
111479e7739fSRob Clark			  "",
111579e7739fSRob Clark			  "",
111679e7739fSRob Clark			  "",
111779e7739fSRob Clark			  "",
111879e7739fSRob Clark			  "",
111979e7739fSRob Clark			  "",
112079e7739fSRob Clark			  "CFG_OPT1",
112179e7739fSRob Clark			  "WCSS_PWR_REQ",
112279e7739fSRob Clark			  "",
112379e7739fSRob Clark			  "CFG_OPT2",
112479e7739fSRob Clark			  "SLB";
112579e7739fSRob Clark};
112679e7739fSRob Clark
112779e7739fSRob Clark&tlmm {
112879e7739fSRob Clark	/*
112979e7739fSRob Clark	 * pinctrl settings for pins that have no real owners.
113079e7739fSRob Clark	 */
113179e7739fSRob Clark	pinctrl-names = "default", "sleep";
113279e7739fSRob Clark	pinctrl-0 = <&bios_flash_wp_r_l>,
113379e7739fSRob Clark		    <&ap_suspend_l_deassert>;
113479e7739fSRob Clark
113579e7739fSRob Clark	pinctrl-1 = <&bios_flash_wp_r_l>,
113679e7739fSRob Clark		    <&ap_suspend_l_assert>;
113779e7739fSRob Clark
113879e7739fSRob Clark	/*
113979e7739fSRob Clark	 * Hogs prevent usermode from changing the value. A GPIO can be both
114079e7739fSRob Clark	 * here and in the pinctrl section.
114179e7739fSRob Clark	 */
114279e7739fSRob Clark	ap-suspend-l-hog {
114379e7739fSRob Clark		gpio-hog;
114479e7739fSRob Clark		gpios = <126 GPIO_ACTIVE_LOW>;
114579e7739fSRob Clark		output-low;
114679e7739fSRob Clark	};
114779e7739fSRob Clark
1148d05e3428SKrzysztof Kozlowski	ap_edp_bklten: ap-edp-bklten-state {
114979e7739fSRob Clark		pins = "gpio37";
115079e7739fSRob Clark		function = "gpio";
115179e7739fSRob Clark		drive-strength = <2>;
115279e7739fSRob Clark		bias-disable;
115379e7739fSRob Clark	};
115479e7739fSRob Clark
1155d05e3428SKrzysztof Kozlowski	bios_flash_wp_r_l: bios-flash-wp-r-l-state {
115679e7739fSRob Clark		pins = "gpio128";
115779e7739fSRob Clark		function = "gpio";
115879e7739fSRob Clark		input-enable;
115979e7739fSRob Clark		bias-disable;
116079e7739fSRob Clark	};
116179e7739fSRob Clark
1162d05e3428SKrzysztof Kozlowski	ec_ap_int_l: ec-ap-int-l-state {
116379e7739fSRob Clark	       pins = "gpio122";
116479e7739fSRob Clark	       function = "gpio";
116579e7739fSRob Clark	       input-enable;
116679e7739fSRob Clark	       bias-pull-up;
116779e7739fSRob Clark	};
116879e7739fSRob Clark
1169d05e3428SKrzysztof Kozlowski	edp_brij_en: edp-brij-en-state {
117079e7739fSRob Clark		pins = "gpio102";
117179e7739fSRob Clark		function = "gpio";
117279e7739fSRob Clark		drive-strength = <2>;
117379e7739fSRob Clark		bias-disable;
117479e7739fSRob Clark	};
117579e7739fSRob Clark
1176d05e3428SKrzysztof Kozlowski	edp_brij_irq: edp-brij-irq-state {
117779e7739fSRob Clark		pins = "gpio10";
117879e7739fSRob Clark		function = "gpio";
117979e7739fSRob Clark		drive-strength = <2>;
118079e7739fSRob Clark		bias-pull-down;
118179e7739fSRob Clark	};
118279e7739fSRob Clark
1183d05e3428SKrzysztof Kozlowski	en_pp3300_dx_edp: en-pp3300-dx-edp-state {
118479e7739fSRob Clark		pins = "gpio43";
118579e7739fSRob Clark		function = "gpio";
118679e7739fSRob Clark		drive-strength = <2>;
118779e7739fSRob Clark		bias-disable;
118879e7739fSRob Clark	};
118979e7739fSRob Clark
1190d05e3428SKrzysztof Kozlowski	h1_ap_int_odl: h1-ap-int-odl-state {
119179e7739fSRob Clark		pins = "gpio129";
119279e7739fSRob Clark		function = "gpio";
119379e7739fSRob Clark		input-enable;
119479e7739fSRob Clark		bias-pull-up;
119579e7739fSRob Clark	};
119679e7739fSRob Clark
1197d05e3428SKrzysztof Kozlowski	pen_eject_odl: pen-eject-odl-state {
119879e7739fSRob Clark		pins = "gpio119";
119979e7739fSRob Clark		function = "gpio";
120079e7739fSRob Clark		bias-pull-up;
120179e7739fSRob Clark	};
120279e7739fSRob Clark
1203d05e3428SKrzysztof Kozlowski	pen_irq_l: pen-irq-l-state {
120479e7739fSRob Clark		pins = "gpio24";
120579e7739fSRob Clark		function = "gpio";
120679e7739fSRob Clark
120779e7739fSRob Clark		/* Has external pullup */
120879e7739fSRob Clark		bias-disable;
120979e7739fSRob Clark	};
121079e7739fSRob Clark
1211d05e3428SKrzysztof Kozlowski	pen_pdct_l: pen-pdct-l-state {
121279e7739fSRob Clark		pins = "gpio63";
121379e7739fSRob Clark		function = "gpio";
121479e7739fSRob Clark
121579e7739fSRob Clark		/* Has external pullup */
121679e7739fSRob Clark		bias-disable;
121779e7739fSRob Clark	};
121879e7739fSRob Clark
1219d05e3428SKrzysztof Kozlowski	pen_rst_l: pen-rst-l-state {
122079e7739fSRob Clark		pins = "gpio23";
122179e7739fSRob Clark		function = "gpio";
122279e7739fSRob Clark		bias-disable;
122379e7739fSRob Clark		drive-strength = <2>;
122479e7739fSRob Clark
122579e7739fSRob Clark		/*
122679e7739fSRob Clark		 * The pen driver doesn't currently support
122779e7739fSRob Clark		 * driving this reset line.  By specifying
122879e7739fSRob Clark		 * output-high here we're relying on the fact
122979e7739fSRob Clark		 * that this pin has a default pulldown at boot
123079e7739fSRob Clark		 * (which makes sure the pen was in reset if it
123179e7739fSRob Clark		 * was powered) and then we set it high here to
123279e7739fSRob Clark		 * take it out of reset.  Better would be if the
123379e7739fSRob Clark		 * pen driver could control this and we could
123479e7739fSRob Clark		 * remove "output-high" here.
123579e7739fSRob Clark		 */
123679e7739fSRob Clark		output-high;
123779e7739fSRob Clark	};
123879e7739fSRob Clark
1239d05e3428SKrzysztof Kozlowski	sdc2_clk: sdc2-clk-state {
124079e7739fSRob Clark		pins = "sdc2_clk";
124179e7739fSRob Clark		bias-disable;
124279e7739fSRob Clark
124379e7739fSRob Clark		/*
124479e7739fSRob Clark		 * It seems that mmc_test reports errors if drive
124579e7739fSRob Clark		 * strength is not 16.
124679e7739fSRob Clark		 */
124779e7739fSRob Clark		drive-strength = <16>;
124879e7739fSRob Clark	};
124979e7739fSRob Clark
1250d05e3428SKrzysztof Kozlowski	sdc2_cmd: sdc2-cmd-state {
125179e7739fSRob Clark		pins = "sdc2_cmd";
125279e7739fSRob Clark		bias-pull-up;
125379e7739fSRob Clark		drive-strength = <16>;
125479e7739fSRob Clark	};
125579e7739fSRob Clark
1256d05e3428SKrzysztof Kozlowski	sdc2_data: sdc2-data-state {
125779e7739fSRob Clark		pins = "sdc2_data";
125879e7739fSRob Clark		bias-pull-up;
125979e7739fSRob Clark		drive-strength = <16>;
126079e7739fSRob Clark	};
126179e7739fSRob Clark
1262d05e3428SKrzysztof Kozlowski	sd_cd_odl: sd-cd-odl-state {
126379e7739fSRob Clark		pins = "gpio44";
126479e7739fSRob Clark		function = "gpio";
126579e7739fSRob Clark		bias-pull-up;
126679e7739fSRob Clark	};
126779e7739fSRob Clark
1268d05e3428SKrzysztof Kozlowski	ts_int_l: ts-int-l-state {
126979e7739fSRob Clark		pins = "gpio125";
127079e7739fSRob Clark		function = "gpio";
127179e7739fSRob Clark		bias-pull-up;
127279e7739fSRob Clark	};
127379e7739fSRob Clark
1274d05e3428SKrzysztof Kozlowski	ts_reset_l: ts-reset-l-state {
127579e7739fSRob Clark		pins = "gpio118";
127679e7739fSRob Clark		function = "gpio";
127779e7739fSRob Clark		bias-disable;
127879e7739fSRob Clark		drive-strength = <2>;
127979e7739fSRob Clark	};
128079e7739fSRob Clark
1281d05e3428SKrzysztof Kozlowski	ap_suspend_l_assert: ap-suspend-l-assert-state {
128279e7739fSRob Clark		pins = "gpio126";
128379e7739fSRob Clark		function = "gpio";
12849bce41faSKrzysztof Kozlowski		bias-disable;
128579e7739fSRob Clark		drive-strength = <2>;
128679e7739fSRob Clark		output-low;
128779e7739fSRob Clark	};
128879e7739fSRob Clark
1289d05e3428SKrzysztof Kozlowski	ap_suspend_l_deassert: ap-suspend-l-deassert-state {
129079e7739fSRob Clark		pins = "gpio126";
129179e7739fSRob Clark		function = "gpio";
12929bce41faSKrzysztof Kozlowski		bias-disable;
129379e7739fSRob Clark		drive-strength = <2>;
129479e7739fSRob Clark		output-high;
129579e7739fSRob Clark	};
129679e7739fSRob Clark};
129748a0585bSAlexandre Courbot
129848a0585bSAlexandre Courbot&venus {
12997f761609SKonrad Dybcio	status = "okay";
13007f761609SKonrad Dybcio
130148a0585bSAlexandre Courbot	video-firmware {
130248a0585bSAlexandre Courbot		iommus = <&apps_smmu 0x10b2 0x0>;
130348a0585bSAlexandre Courbot	};
130448a0585bSAlexandre Courbot};
1305