xref: /openbmc/linux/arch/arm64/boot/dts/qcom/sdm660.dtsi (revision e961f8c6) 
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2018, Craig Tatlor.
4 * Copyright (c) 2020, Alexey Minnekhanov <alexey.min@gmail.com>
5 * Copyright (c) 2020, AngeloGioacchino Del Regno <kholk11@gmail.com>
6 * Copyright (c) 2020, Konrad Dybcio <konradybcio@gmail.com>
7 * Copyright (c) 2020, Martin Botka <martin.botka1@gmail.com>
8 */
9
10#include "sdm630.dtsi"
11
12&adreno_gpu {
13	compatible = "qcom,adreno-512.0", "qcom,adreno";
14	operating-points-v2 = <&gpu_sdm660_opp_table>;
15
16	gpu_sdm660_opp_table: opp-table {
17		compatible = "operating-points-v2";
18
19		/*
20		 * 775MHz is only available on the highest speed bin
21		 * Though it cannot be used for now due to interconnect
22		 * framework not supporting multiple frequencies
23		 * at the same opp-level
24
25		opp-750000000 {
26			opp-hz = /bits/ 64 <750000000>;
27			opp-level = <RPM_SMD_LEVEL_TURBO>;
28			opp-peak-kBps = <5412000>;
29			opp-supported-hw = <0xCHECKME>;
30		};
31
32		* These OPPs are correct, but we are lacking support for the
33		* GPU regulator. Hence, disable them for now to prevent the
34		* platform from hanging on high graphics loads.
35
36		opp-700000000 {
37			opp-hz = /bits/ 64 <700000000>;
38			opp-level = <RPM_SMD_LEVEL_TURBO>;
39			opp-peak-kBps = <5184000>;
40			opp-supported-hw = <0xff>;
41		};
42
43		opp-647000000 {
44			opp-hz = /bits/ 64 <647000000>;
45			opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
46			opp-peak-kBps = <4068000>;
47			opp-supported-hw = <0xff>;
48		};
49
50		opp-588000000 {
51			opp-hz = /bits/ 64 <588000000>;
52			opp-level = <RPM_SMD_LEVEL_NOM>;
53			opp-peak-kBps = <3072000>;
54			opp-supported-hw = <0xff>;
55		};
56
57		opp-465000000 {
58			opp-hz = /bits/ 64 <465000000>;
59			opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
60			opp-peak-kBps = <2724000>;
61			opp-supported-hw = <0xff>;
62		};
63
64		opp-370000000 {
65			opp-hz = /bits/ 64 <370000000>;
66			opp-level = <RPM_SMD_LEVEL_SVS>;
67			opp-peak-kBps = <2188000>;
68			opp-supported-hw = <0xff>;
69		};
70		*/
71
72		opp-266000000 {
73			opp-hz = /bits/ 64 <266000000>;
74			opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
75			opp-peak-kBps = <1648000>;
76			opp-supported-hw = <0xff>;
77		};
78
79		opp-160000000 {
80			opp-hz = /bits/ 64 <160000000>;
81			opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
82			opp-peak-kBps = <1200000>;
83			opp-supported-hw = <0xff>;
84		};
85	};
86};
87
88&CPU0 {
89	compatible = "qcom,kryo260";
90	capacity-dmips-mhz = <1024>;
91	/delete-property/ operating-points-v2;
92};
93
94&CPU1 {
95	compatible = "qcom,kryo260";
96	capacity-dmips-mhz = <1024>;
97	/delete-property/ operating-points-v2;
98};
99
100&CPU2 {
101	compatible = "qcom,kryo260";
102	capacity-dmips-mhz = <1024>;
103	/delete-property/ operating-points-v2;
104};
105
106&CPU3 {
107	compatible = "qcom,kryo260";
108	capacity-dmips-mhz = <1024>;
109	/delete-property/ operating-points-v2;
110};
111
112&CPU4 {
113	compatible = "qcom,kryo260";
114	capacity-dmips-mhz = <640>;
115	/delete-property/ operating-points-v2;
116};
117
118&CPU5 {
119	compatible = "qcom,kryo260";
120	capacity-dmips-mhz = <640>;
121	/delete-property/ operating-points-v2;
122};
123
124&CPU6 {
125	compatible = "qcom,kryo260";
126	capacity-dmips-mhz = <640>;
127	/delete-property/ operating-points-v2;
128};
129
130&CPU7 {
131	compatible = "qcom,kryo260";
132	capacity-dmips-mhz = <640>;
133	/delete-property/ operating-points-v2;
134};
135
136&gcc {
137	compatible = "qcom,gcc-sdm660";
138};
139
140&gpucc {
141	compatible = "qcom,gpucc-sdm660";
142};
143
144&mdp {
145	compatible = "qcom,sdm660-mdp5", "qcom,mdp5";
146
147	ports {
148		port@1 {
149			reg = <1>;
150			mdp5_intf2_out: endpoint {
151				remote-endpoint = <&mdss_dsi1_in>;
152			};
153		};
154	};
155};
156
157&mdss {
158	mdss_dsi1: dsi@c996000 {
159		compatible = "qcom,sdm660-dsi-ctrl",
160			     "qcom,mdss-dsi-ctrl";
161		reg = <0x0c996000 0x400>;
162		reg-names = "dsi_ctrl";
163
164		/* DSI1 shares the OPP table with DSI0 */
165		operating-points-v2 = <&dsi_opp_table>;
166		power-domains = <&rpmpd SDM660_VDDCX>;
167
168		interrupt-parent = <&mdss>;
169		interrupts = <5>;
170
171		assigned-clocks = <&mmcc BYTE1_CLK_SRC>,
172					<&mmcc PCLK1_CLK_SRC>;
173		assigned-clock-parents = <&mdss_dsi1_phy 0>,
174						<&mdss_dsi1_phy 1>;
175
176		clocks = <&mmcc MDSS_MDP_CLK>,
177				<&mmcc MDSS_BYTE1_CLK>,
178				<&mmcc MDSS_BYTE1_INTF_CLK>,
179				<&mmcc MNOC_AHB_CLK>,
180				<&mmcc MDSS_AHB_CLK>,
181				<&mmcc MDSS_AXI_CLK>,
182				<&mmcc MISC_AHB_CLK>,
183				<&mmcc MDSS_PCLK1_CLK>,
184				<&mmcc MDSS_ESC1_CLK>;
185		clock-names = "mdp_core",
186					"byte",
187					"byte_intf",
188					"mnoc",
189					"iface",
190					"bus",
191					"core_mmss",
192					"pixel",
193					"core";
194
195		phys = <&mdss_dsi1_phy>;
196
197		status = "disabled";
198
199		ports {
200			#address-cells = <1>;
201			#size-cells = <0>;
202
203			port@0 {
204				reg = <0>;
205				mdss_dsi1_in: endpoint {
206					remote-endpoint = <&mdp5_intf2_out>;
207				};
208			};
209
210			port@1 {
211				reg = <1>;
212				mdss_dsi1_out: endpoint {
213				};
214			};
215		};
216	};
217
218	mdss_dsi1_phy: phy@c996400 {
219		compatible = "qcom,dsi-phy-14nm-660";
220		reg = <0x0c996400 0x100>,
221				<0x0c996500 0x300>,
222				<0x0c996800 0x188>;
223		reg-names = "dsi_phy",
224				"dsi_phy_lane",
225				"dsi_pll";
226
227		#clock-cells = <1>;
228		#phy-cells = <0>;
229
230		clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
231		clock-names = "iface", "ref";
232		status = "disabled";
233	};
234};
235
236&mmcc {
237	compatible = "qcom,mmcc-sdm660";
238	clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
239			<&sleep_clk>,
240			<&gcc GCC_MMSS_GPLL0_CLK>,
241			<&gcc GCC_MMSS_GPLL0_DIV_CLK>,
242			<&mdss_dsi0_phy 1>,
243			<&mdss_dsi0_phy 0>,
244			<&mdss_dsi1_phy 1>,
245			<&mdss_dsi1_phy 0>,
246			<0>,
247			<0>;
248};
249
250&tlmm {
251	compatible = "qcom,sdm660-pinctrl";
252};
253
254&tsens {
255	#qcom,sensors = <14>;
256};
257