1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2020, Konrad Dybcio 4 */ 5 6#include <dt-bindings/clock/qcom,gcc-sdm660.h> 7#include <dt-bindings/clock/qcom,rpmcc.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10 11/ { 12 interrupt-parent = <&intc>; 13 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 chosen { }; 18 19 clocks { 20 xo_board: xo_board { 21 compatible = "fixed-clock"; 22 #clock-cells = <0>; 23 clock-frequency = <19200000>; 24 clock-output-names = "xo_board"; 25 }; 26 27 sleep_clk: sleep_clk { 28 compatible = "fixed-clock"; 29 #clock-cells = <0>; 30 clock-frequency = <32764>; 31 clock-output-names = "sleep_clk"; 32 }; 33 }; 34 35 cpus { 36 #address-cells = <2>; 37 #size-cells = <0>; 38 39 CPU0: cpu@100 { 40 device_type = "cpu"; 41 compatible = "arm,cortex-a53"; 42 reg = <0x0 0x100>; 43 enable-method = "psci"; 44 cpu-idle-states = <&PERF_CPU_SLEEP_0 45 &PERF_CPU_SLEEP_1 46 &PERF_CLUSTER_SLEEP_0 47 &PERF_CLUSTER_SLEEP_1 48 &PERF_CLUSTER_SLEEP_2>; 49 capacity-dmips-mhz = <1126>; 50 #cooling-cells = <2>; 51 next-level-cache = <&L2_1>; 52 L2_1: l2-cache { 53 compatible = "cache"; 54 cache-level = <2>; 55 }; 56 }; 57 58 CPU1: cpu@101 { 59 device_type = "cpu"; 60 compatible = "arm,cortex-a53"; 61 reg = <0x0 0x101>; 62 enable-method = "psci"; 63 cpu-idle-states = <&PERF_CPU_SLEEP_0 64 &PERF_CPU_SLEEP_1 65 &PERF_CLUSTER_SLEEP_0 66 &PERF_CLUSTER_SLEEP_1 67 &PERF_CLUSTER_SLEEP_2>; 68 capacity-dmips-mhz = <1126>; 69 #cooling-cells = <2>; 70 next-level-cache = <&L2_1>; 71 }; 72 73 CPU2: cpu@102 { 74 device_type = "cpu"; 75 compatible = "arm,cortex-a53"; 76 reg = <0x0 0x102>; 77 enable-method = "psci"; 78 cpu-idle-states = <&PERF_CPU_SLEEP_0 79 &PERF_CPU_SLEEP_1 80 &PERF_CLUSTER_SLEEP_0 81 &PERF_CLUSTER_SLEEP_1 82 &PERF_CLUSTER_SLEEP_2>; 83 capacity-dmips-mhz = <1126>; 84 #cooling-cells = <2>; 85 next-level-cache = <&L2_1>; 86 }; 87 88 CPU3: cpu@103 { 89 device_type = "cpu"; 90 compatible = "arm,cortex-a53"; 91 reg = <0x0 0x103>; 92 enable-method = "psci"; 93 cpu-idle-states = <&PERF_CPU_SLEEP_0 94 &PERF_CPU_SLEEP_1 95 &PERF_CLUSTER_SLEEP_0 96 &PERF_CLUSTER_SLEEP_1 97 &PERF_CLUSTER_SLEEP_2>; 98 capacity-dmips-mhz = <1126>; 99 #cooling-cells = <2>; 100 next-level-cache = <&L2_1>; 101 }; 102 103 CPU4: cpu@0 { 104 device_type = "cpu"; 105 compatible = "arm,cortex-a53"; 106 reg = <0x0 0x0>; 107 enable-method = "psci"; 108 cpu-idle-states = <&PWR_CPU_SLEEP_0 109 &PWR_CPU_SLEEP_1 110 &PWR_CLUSTER_SLEEP_0 111 &PWR_CLUSTER_SLEEP_1 112 &PWR_CLUSTER_SLEEP_2>; 113 capacity-dmips-mhz = <1024>; 114 #cooling-cells = <2>; 115 next-level-cache = <&L2_0>; 116 L2_0: l2-cache { 117 compatible = "cache"; 118 cache-level = <2>; 119 }; 120 }; 121 122 CPU5: cpu@1 { 123 device_type = "cpu"; 124 compatible = "arm,cortex-a53"; 125 reg = <0x0 0x1>; 126 enable-method = "psci"; 127 cpu-idle-states = <&PWR_CPU_SLEEP_0 128 &PWR_CPU_SLEEP_1 129 &PWR_CLUSTER_SLEEP_0 130 &PWR_CLUSTER_SLEEP_1 131 &PWR_CLUSTER_SLEEP_2>; 132 capacity-dmips-mhz = <1024>; 133 #cooling-cells = <2>; 134 next-level-cache = <&L2_0>; 135 }; 136 137 CPU6: cpu@2 { 138 device_type = "cpu"; 139 compatible = "arm,cortex-a53"; 140 reg = <0x0 0x2>; 141 enable-method = "psci"; 142 cpu-idle-states = <&PWR_CPU_SLEEP_0 143 &PWR_CPU_SLEEP_1 144 &PWR_CLUSTER_SLEEP_0 145 &PWR_CLUSTER_SLEEP_1 146 &PWR_CLUSTER_SLEEP_2>; 147 capacity-dmips-mhz = <1024>; 148 #cooling-cells = <2>; 149 next-level-cache = <&L2_0>; 150 }; 151 152 CPU7: cpu@3 { 153 device_type = "cpu"; 154 compatible = "arm,cortex-a53"; 155 reg = <0x0 0x3>; 156 enable-method = "psci"; 157 cpu-idle-states = <&PWR_CPU_SLEEP_0 158 &PWR_CPU_SLEEP_1 159 &PWR_CLUSTER_SLEEP_0 160 &PWR_CLUSTER_SLEEP_1 161 &PWR_CLUSTER_SLEEP_2>; 162 capacity-dmips-mhz = <1024>; 163 #cooling-cells = <2>; 164 next-level-cache = <&L2_0>; 165 }; 166 167 cpu-map { 168 cluster0 { 169 core0 { 170 cpu = <&CPU4>; 171 }; 172 173 core1 { 174 cpu = <&CPU5>; 175 }; 176 177 core2 { 178 cpu = <&CPU6>; 179 }; 180 181 core3 { 182 cpu = <&CPU7>; 183 }; 184 }; 185 186 cluster1 { 187 core0 { 188 cpu = <&CPU0>; 189 }; 190 191 core1 { 192 cpu = <&CPU1>; 193 }; 194 195 core2 { 196 cpu = <&CPU2>; 197 }; 198 199 core3 { 200 cpu = <&CPU3>; 201 }; 202 }; 203 }; 204 205 idle-states { 206 entry-method = "psci"; 207 208 PWR_CPU_SLEEP_0: cpu-sleep-0-0 { 209 compatible = "arm,idle-state"; 210 idle-state-name = "pwr-retention"; 211 arm,psci-suspend-param = <0x40000002>; 212 entry-latency-us = <338>; 213 exit-latency-us = <423>; 214 min-residency-us = <200>; 215 }; 216 217 PWR_CPU_SLEEP_1: cpu-sleep-0-1 { 218 compatible = "arm,idle-state"; 219 idle-state-name = "pwr-power-collapse"; 220 arm,psci-suspend-param = <0x40000003>; 221 entry-latency-us = <515>; 222 exit-latency-us = <1821>; 223 min-residency-us = <1000>; 224 local-timer-stop; 225 }; 226 227 PERF_CPU_SLEEP_0: cpu-sleep-1-0 { 228 compatible = "arm,idle-state"; 229 idle-state-name = "perf-retention"; 230 arm,psci-suspend-param = <0x40000002>; 231 entry-latency-us = <154>; 232 exit-latency-us = <87>; 233 min-residency-us = <200>; 234 }; 235 236 PERF_CPU_SLEEP_1: cpu-sleep-1-1 { 237 compatible = "arm,idle-state"; 238 idle-state-name = "perf-power-collapse"; 239 arm,psci-suspend-param = <0x40000003>; 240 entry-latency-us = <262>; 241 exit-latency-us = <301>; 242 min-residency-us = <1000>; 243 local-timer-stop; 244 }; 245 246 PWR_CLUSTER_SLEEP_0: cluster-sleep-0-0 { 247 compatible = "arm,idle-state"; 248 idle-state-name = "pwr-cluster-dynamic-retention"; 249 arm,psci-suspend-param = <0x400000F2>; 250 entry-latency-us = <284>; 251 exit-latency-us = <384>; 252 min-residency-us = <9987>; 253 local-timer-stop; 254 }; 255 256 PWR_CLUSTER_SLEEP_1: cluster-sleep-0-1 { 257 compatible = "arm,idle-state"; 258 idle-state-name = "pwr-cluster-retention"; 259 arm,psci-suspend-param = <0x400000F3>; 260 entry-latency-us = <338>; 261 exit-latency-us = <423>; 262 min-residency-us = <9987>; 263 local-timer-stop; 264 }; 265 266 PWR_CLUSTER_SLEEP_2: cluster-sleep-0-2 { 267 compatible = "arm,idle-state"; 268 idle-state-name = "pwr-cluster-retention"; 269 arm,psci-suspend-param = <0x400000F4>; 270 entry-latency-us = <515>; 271 exit-latency-us = <1821>; 272 min-residency-us = <9987>; 273 local-timer-stop; 274 }; 275 276 PERF_CLUSTER_SLEEP_0: cluster-sleep-1-0 { 277 compatible = "arm,idle-state"; 278 idle-state-name = "perf-cluster-dynamic-retention"; 279 arm,psci-suspend-param = <0x400000F2>; 280 entry-latency-us = <272>; 281 exit-latency-us = <329>; 282 min-residency-us = <9987>; 283 local-timer-stop; 284 }; 285 286 PERF_CLUSTER_SLEEP_1: cluster-sleep-1-1 { 287 compatible = "arm,idle-state"; 288 idle-state-name = "perf-cluster-retention"; 289 arm,psci-suspend-param = <0x400000F3>; 290 entry-latency-us = <332>; 291 exit-latency-us = <368>; 292 min-residency-us = <9987>; 293 local-timer-stop; 294 }; 295 296 PERF_CLUSTER_SLEEP_2: cluster-sleep-1-2 { 297 compatible = "arm,idle-state"; 298 idle-state-name = "perf-cluster-retention"; 299 arm,psci-suspend-param = <0x400000F4>; 300 entry-latency-us = <545>; 301 exit-latency-us = <1609>; 302 min-residency-us = <9987>; 303 local-timer-stop; 304 }; 305 }; 306 }; 307 308 firmware { 309 scm { 310 compatible = "qcom,scm-msm8998", "qcom,scm"; 311 }; 312 }; 313 314 memory { 315 device_type = "memory"; 316 /* We expect the bootloader to fill in the reg */ 317 reg = <0 0 0 0>; 318 }; 319 320 pmu { 321 compatible = "arm,armv8-pmuv3"; 322 interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>; 323 }; 324 325 psci { 326 compatible = "arm,psci-1.0"; 327 method = "smc"; 328 }; 329 330 reserved-memory { 331 #address-cells = <2>; 332 #size-cells = <2>; 333 ranges; 334 335 wlan_msa_guard: wlan-msa-guard@85600000 { 336 reg = <0x0 0x85600000 0x0 0x100000>; 337 no-map; 338 }; 339 340 wlan_msa_mem: wlan-msa-mem@85700000 { 341 reg = <0x0 0x85700000 0x0 0x100000>; 342 no-map; 343 }; 344 345 qhee_code: qhee-code@85800000 { 346 reg = <0x0 0x85800000 0x0 0x3700000>; 347 no-map; 348 }; 349 350 smem_region: smem-mem@86000000 { 351 reg = <0 0x86000000 0 0x200000>; 352 no-map; 353 }; 354 355 tz_mem: memory@86200000 { 356 reg = <0x0 0x86200000 0x0 0x3300000>; 357 no-map; 358 }; 359 360 modem_fw_mem: modem-fw-region@8ac00000 { 361 reg = <0x0 0x8ac00000 0x0 0x7e00000>; 362 no-map; 363 }; 364 365 adsp_fw_mem: adsp-fw-region@92a00000 { 366 reg = <0x0 0x92a00000 0x0 0x1e00000>; 367 no-map; 368 }; 369 370 pil_mba_mem: pil-mba-region@94800000 { 371 reg = <0x0 0x94800000 0x0 0x200000>; 372 no-map; 373 }; 374 375 buffer_mem: buffer-region@94a00000 { 376 reg = <0x0 0x94a00000 0x0 0x100000>; 377 no-map; 378 }; 379 380 venus_fw_mem: venus-fw-region@9f800000 { 381 reg = <0x0 0x9f800000 0x0 0x800000>; 382 no-map; 383 }; 384 385 secure_region2: secure-region2@f7c00000 { 386 reg = <0x0 0xf7c00000 0x0 0x5c00000>; 387 no-map; 388 }; 389 390 adsp_mem: adsp-region@f6000000 { 391 reg = <0x0 0xf6000000 0x0 0x800000>; 392 no-map; 393 }; 394 395 qseecom_ta_mem: qseecom-ta-region@fec00000 { 396 reg = <0x0 0xfec00000 0x0 0x1000000>; 397 no-map; 398 }; 399 400 qseecom_mem: qseecom-region@f6800000 { 401 reg = <0x0 0xf6800000 0x0 0x1400000>; 402 no-map; 403 }; 404 405 secure_display_memory: secure-region@f5c00000 { 406 reg = <0x0 0xf5c00000 0x0 0x5c00000>; 407 no-map; 408 }; 409 410 cont_splash_mem: cont-splash-region@9d400000 { 411 reg = <0x0 0x9d400000 0x0 0x23ff000>; 412 no-map; 413 }; 414 }; 415 416 rpm-glink { 417 compatible = "qcom,glink-rpm"; 418 419 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 420 qcom,rpm-msg-ram = <&rpm_msg_ram>; 421 mboxes = <&apcs_glb 0>; 422 423 rpm_requests: rpm-requests { 424 compatible = "qcom,rpm-sdm660"; 425 qcom,glink-channels = "rpm_requests"; 426 427 rpmcc: clock-controller { 428 compatible = "qcom,rpmcc-sdm660", "qcom,rpmcc"; 429 #clock-cells = <1>; 430 }; 431 }; 432 }; 433 434 smem: smem { 435 compatible = "qcom,smem"; 436 memory-region = <&smem_region>; 437 hwlocks = <&tcsr_mutex 3>; 438 }; 439 440 soc { 441 #address-cells = <1>; 442 #size-cells = <1>; 443 ranges = <0 0 0 0xffffffff>; 444 compatible = "simple-bus"; 445 446 gcc: clock-controller@100000 { 447 compatible = "qcom,gcc-sdm630"; 448 #clock-cells = <1>; 449 #reset-cells = <1>; 450 #power-domain-cells = <1>; 451 reg = <0x00100000 0x94000>; 452 453 clock-names = "xo", "sleep_clk"; 454 clocks = <&xo_board>, 455 <&sleep_clk>; 456 }; 457 458 rpm_msg_ram: memory@778000 { 459 compatible = "qcom,rpm-msg-ram"; 460 reg = <0x00778000 0x7000>; 461 }; 462 463 qfprom: qfprom@780000 { 464 compatible = "qcom,qfprom"; 465 reg = <0x00780000 0x621c>; 466 #address-cells = <1>; 467 #size-cells = <1>; 468 }; 469 470 rng: rng@793000 { 471 compatible = "qcom,prng-ee"; 472 reg = <0x00793000 0x1000>; 473 clocks = <&gcc GCC_PRNG_AHB_CLK>; 474 clock-names = "core"; 475 }; 476 477 restart@10ac000 { 478 compatible = "qcom,pshold"; 479 reg = <0x010ac000 0x4>; 480 }; 481 482 anoc2_smmu: iommu@16c0000 { 483 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2"; 484 reg = <0x016c0000 0x40000>; 485 #iommu-cells = <1>; 486 487 #global-interrupts = <2>; 488 interrupts = 489 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 490 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 491 492 <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>, 493 <GIC_SPI 374 IRQ_TYPE_LEVEL_LOW>, 494 <GIC_SPI 375 IRQ_TYPE_LEVEL_LOW>, 495 <GIC_SPI 376 IRQ_TYPE_LEVEL_LOW>, 496 <GIC_SPI 377 IRQ_TYPE_LEVEL_LOW>, 497 <GIC_SPI 378 IRQ_TYPE_LEVEL_LOW>, 498 <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>, 499 <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>, 500 <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>, 501 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>, 502 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>, 503 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>, 504 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>, 505 <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, 506 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>, 507 <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>, 508 <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>, 509 <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, 510 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, 511 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, 512 <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>, 513 <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>, 514 <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, 515 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>, 516 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>, 517 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>, 518 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, 519 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, 520 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>; 521 }; 522 523 tcsr_mutex_regs: syscon@1f40000 { 524 compatible = "syscon"; 525 reg = <0x01f40000 0x20000>; 526 }; 527 528 tlmm: pinctrl@3000000 { 529 compatible = "qcom,sdm630-pinctrl"; 530 reg = <0x03000000 0xc00000>; 531 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 532 gpio-controller; 533 #gpio-cells = <0x2>; 534 interrupt-controller; 535 #interrupt-cells = <0x2>; 536 537 blsp1_uart1_default: blsp1-uart1-default { 538 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 539 drive-strength = <2>; 540 bias-disable; 541 }; 542 543 blsp1_uart1_sleep: blsp1-uart1-sleep { 544 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 545 drive-strength = <2>; 546 bias-disable; 547 }; 548 549 blsp1_uart2_default: blsp1-uart2-default { 550 pins = "gpio4", "gpio5"; 551 drive-strength = <2>; 552 bias-disable; 553 }; 554 555 blsp2_uart1_tx_active: blsp2-uart1-tx-active { 556 pins = "gpio16"; 557 drive-strength = <2>; 558 bias-disable; 559 }; 560 561 blsp2_uart1_tx_sleep: blsp2-uart1-tx-sleep { 562 pins = "gpio16"; 563 drive-strength = <2>; 564 bias-pull-up; 565 }; 566 567 blsp2_uart1_rxcts_active: blsp2-uart1-rxcts-active { 568 pins = "gpio17", "gpio18"; 569 drive-strength = <2>; 570 bias-disable; 571 }; 572 573 blsp2_uart1_rxcts_sleep: blsp2-uart1-rxcts-sleep { 574 pins = "gpio17", "gpio18"; 575 drive-strength = <2>; 576 bias-no-pull; 577 }; 578 579 blsp2_uart1_rfr_active: blsp2-uart1-rfr-active { 580 pins = "gpio19"; 581 drive-strength = <2>; 582 bias-disable; 583 }; 584 585 blsp2_uart1_rfr_sleep: blsp2-uart1-rfr-sleep { 586 pins = "gpio19"; 587 drive-strength = <2>; 588 bias-no-pull; 589 }; 590 591 i2c1_default: i2c1-default { 592 pins = "gpio2", "gpio3"; 593 drive-strength = <2>; 594 bias-disable; 595 }; 596 597 i2c1_sleep: i2c1-sleep { 598 pins = "gpio2", "gpio3"; 599 drive-strength = <2>; 600 bias-pull-up; 601 }; 602 603 i2c2_default: i2c2-default { 604 pins = "gpio6", "gpio7"; 605 drive-strength = <2>; 606 bias-disable; 607 }; 608 609 i2c2_sleep: i2c2-sleep { 610 pins = "gpio6", "gpio7"; 611 drive-strength = <2>; 612 bias-pull-up; 613 }; 614 615 i2c3_default: i2c3-default { 616 pins = "gpio10", "gpio11"; 617 drive-strength = <2>; 618 bias-disable; 619 }; 620 621 i2c3_sleep: i2c3-sleep { 622 pins = "gpio10", "gpio11"; 623 drive-strength = <2>; 624 bias-pull-up; 625 }; 626 627 i2c4_default: i2c4-default { 628 pins = "gpio14", "gpio15"; 629 drive-strength = <2>; 630 bias-disable; 631 }; 632 633 i2c4_sleep: i2c4-sleep { 634 pins = "gpio14", "gpio15"; 635 drive-strength = <2>; 636 bias-pull-up; 637 }; 638 639 i2c5_default: i2c5-default { 640 pins = "gpio18", "gpio19"; 641 drive-strength = <2>; 642 bias-disable; 643 }; 644 645 i2c5_sleep: i2c5-sleep { 646 pins = "gpio18", "gpio19"; 647 drive-strength = <2>; 648 bias-pull-up; 649 }; 650 651 i2c6_default: i2c6-default { 652 pins = "gpio22", "gpio23"; 653 drive-strength = <2>; 654 bias-disable; 655 }; 656 657 i2c6_sleep: i2c6-sleep { 658 pins = "gpio22", "gpio23"; 659 drive-strength = <2>; 660 bias-pull-up; 661 }; 662 663 i2c7_default: i2c7-default { 664 pins = "gpio26", "gpio27"; 665 drive-strength = <2>; 666 bias-disable; 667 }; 668 669 i2c7_sleep: i2c7-sleep { 670 pins = "gpio26", "gpio27"; 671 drive-strength = <2>; 672 bias-pull-up; 673 }; 674 675 i2c8_default: i2c8-default { 676 pins = "gpio30", "gpio31"; 677 drive-strength = <2>; 678 bias-disable; 679 }; 680 681 i2c8_sleep: i2c8-sleep { 682 pins = "gpio30", "gpio31"; 683 drive-strength = <2>; 684 bias-pull-up; 685 }; 686 687 sdc1_clk_on: sdc1-clk-on { 688 pins = "sdc1_clk"; 689 bias-disable; 690 drive-strength = <16>; 691 }; 692 693 sdc1_clk_off: sdc1-clk-off { 694 pins = "sdc1_clk"; 695 bias-disable; 696 drive-strength = <2>; 697 }; 698 699 sdc1_cmd_on: sdc1-cmd-on { 700 pins = "sdc1_cmd"; 701 bias-pull-up; 702 drive-strength = <10>; 703 }; 704 705 sdc1_cmd_off: sdc1-cmd-off { 706 pins = "sdc1_cmd"; 707 bias-pull-up; 708 drive-strength = <2>; 709 }; 710 711 sdc1_data_on: sdc1-data-on { 712 pins = "sdc1_data"; 713 bias-pull-up; 714 drive-strength = <8>; 715 }; 716 717 sdc1_data_off: sdc1-data-off { 718 pins = "sdc1_data"; 719 bias-pull-up; 720 drive-strength = <2>; 721 }; 722 723 sdc1_rclk_on: sdc1-rclk-on { 724 pins = "sdc1_rclk"; 725 bias-pull-down; 726 }; 727 728 sdc1_rclk_off: sdc1-rclk-off { 729 pins = "sdc1_rclk"; 730 bias-pull-down; 731 }; 732 }; 733 734 kgsl_smmu: iommu@5040000 { 735 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2"; 736 reg = <0x05040000 0x10000>; 737 #iommu-cells = <1>; 738 739 #global-interrupts = <2>; 740 interrupts = 741 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 742 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 743 744 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 745 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 746 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 747 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 748 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 749 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 750 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>, 751 <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>; 752 }; 753 754 lpass_smmu: iommu@5100000 { 755 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2"; 756 reg = <0x05100000 0x40000>; 757 #iommu-cells = <1>; 758 759 #global-interrupts = <2>; 760 interrupts = 761 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 762 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 763 764 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, 765 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>, 766 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>, 767 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 768 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 769 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 770 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 771 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 772 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 773 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 774 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 775 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 776 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 777 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, 778 <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>, 779 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 780 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>; 781 }; 782 783 spmi_bus: spmi@800f000 { 784 compatible = "qcom,spmi-pmic-arb"; 785 reg = <0x0800f000 0x1000>, 786 <0x08400000 0x1000000>, 787 <0x09400000 0x1000000>, 788 <0x0a400000 0x220000>, 789 <0x0800a000 0x3000>; 790 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 791 interrupt-names = "periph_irq"; 792 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>; 793 qcom,ee = <0>; 794 qcom,channel = <0>; 795 #address-cells = <2>; 796 #size-cells = <0>; 797 interrupt-controller; 798 #interrupt-cells = <4>; 799 cell-index = <0>; 800 }; 801 802 sdhc_1: sdhci@c0c4000 { 803 compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5"; 804 reg = <0x0c0c4000 0x1000>, 805 <0x0c0c5000 0x1000>; 806 reg-names = "hc", "cqhci"; 807 808 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 809 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 810 interrupt-names = "hc_irq", "pwr_irq"; 811 812 clocks = <&gcc GCC_SDCC1_APPS_CLK>, 813 <&gcc GCC_SDCC1_AHB_CLK>, 814 <&xo_board>; 815 clock-names = "core", "iface", "xo"; 816 817 pinctrl-names = "default", "sleep"; 818 pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>; 819 pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>; 820 821 bus-width = <8>; 822 non-removable; 823 824 status = "disabled"; 825 }; 826 827 blsp1_dma: dma@c144000 { 828 compatible = "qcom,bam-v1.7.0"; 829 reg = <0x0c144000 0x1f000>; 830 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 831 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 832 clock-names = "bam_clk"; 833 #dma-cells = <1>; 834 qcom,ee = <0>; 835 qcom,controlled-remotely; 836 num-channels = <18>; 837 qcom,num-ees = <4>; 838 }; 839 840 blsp1_uart1: serial@c16f000 { 841 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 842 reg = <0x0c16f000 0x200>; 843 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 844 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, 845 <&gcc GCC_BLSP1_AHB_CLK>; 846 clock-names = "core", "iface"; 847 dmas = <&blsp1_dma 0>, <&blsp1_dma 1>; 848 dma-names = "tx", "rx"; 849 pinctrl-names = "default", "sleep"; 850 pinctrl-0 = <&blsp1_uart1_default>; 851 pinctrl-1 = <&blsp1_uart1_sleep>; 852 status = "disabled"; 853 }; 854 855 blsp1_uart2: serial@c170000 { 856 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 857 reg = <0x0c170000 0x1000>; 858 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 859 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, 860 <&gcc GCC_BLSP1_AHB_CLK>; 861 clock-names = "core", "iface"; 862 dmas = <&blsp1_dma 2>, <&blsp1_dma 3>; 863 dma-names = "tx", "rx"; 864 pinctrl-names = "default"; 865 pinctrl-0 = <&blsp1_uart2_default>; 866 status = "disabled"; 867 }; 868 869 blsp_i2c1: i2c@c175000 { 870 compatible = "qcom,i2c-qup-v2.2.1"; 871 reg = <0x0c175000 0x600>; 872 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 873 874 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, 875 <&gcc GCC_BLSP1_AHB_CLK>; 876 clock-names = "core", "iface"; 877 clock-frequency = <400000>; 878 879 pinctrl-names = "default", "sleep"; 880 pinctrl-0 = <&i2c1_default>; 881 pinctrl-1 = <&i2c1_sleep>; 882 #address-cells = <1>; 883 #size-cells = <0>; 884 status = "disabled"; 885 }; 886 887 blsp_i2c2: i2c@c176000 { 888 compatible = "qcom,i2c-qup-v2.2.1"; 889 reg = <0x0c176000 0x600>; 890 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 891 892 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 893 <&gcc GCC_BLSP1_AHB_CLK>; 894 clock-names = "core", "iface"; 895 clock-frequency = <400000>; 896 897 pinctrl-names = "default", "sleep"; 898 pinctrl-0 = <&i2c2_default>; 899 pinctrl-1 = <&i2c2_sleep>; 900 #address-cells = <1>; 901 #size-cells = <0>; 902 status = "disabled"; 903 }; 904 905 blsp_i2c3: i2c@c177000 { 906 compatible = "qcom,i2c-qup-v2.2.1"; 907 reg = <0x0c177000 0x600>; 908 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 909 910 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 911 <&gcc GCC_BLSP1_AHB_CLK>; 912 clock-names = "core", "iface"; 913 clock-frequency = <400000>; 914 915 pinctrl-names = "default", "sleep"; 916 pinctrl-0 = <&i2c3_default>; 917 pinctrl-1 = <&i2c3_sleep>; 918 #address-cells = <1>; 919 #size-cells = <0>; 920 status = "disabled"; 921 }; 922 923 blsp_i2c4: i2c@c178000 { 924 compatible = "qcom,i2c-qup-v2.2.1"; 925 reg = <0x0c178000 0x600>; 926 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 927 928 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, 929 <&gcc GCC_BLSP1_AHB_CLK>; 930 clock-names = "core", "iface"; 931 clock-frequency = <400000>; 932 933 pinctrl-names = "default", "sleep"; 934 pinctrl-0 = <&i2c4_default>; 935 pinctrl-1 = <&i2c4_sleep>; 936 #address-cells = <1>; 937 #size-cells = <0>; 938 status = "disabled"; 939 }; 940 941 blsp2_dma: dma@c184000 { 942 compatible = "qcom,bam-v1.7.0"; 943 reg = <0x0c184000 0x1f000>; 944 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 945 clocks = <&gcc GCC_BLSP2_AHB_CLK>; 946 clock-names = "bam_clk"; 947 #dma-cells = <1>; 948 qcom,ee = <0>; 949 qcom,controlled-remotely; 950 num-channels = <18>; 951 qcom,num-ees = <4>; 952 }; 953 954 blsp2_uart1: serial@c1af000 { 955 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 956 reg = <0x0c1af000 0x200>; 957 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 958 clocks = <&gcc GCC_BLSP2_UART1_APPS_CLK>, 959 <&gcc GCC_BLSP2_AHB_CLK>; 960 clock-names = "core", "iface"; 961 dmas = <&blsp2_dma 0>, <&blsp2_dma 1>; 962 dma-names = "tx", "rx"; 963 pinctrl-names = "default", "sleep"; 964 pinctrl-0 = <&blsp2_uart1_tx_active &blsp2_uart1_rxcts_active 965 &blsp2_uart1_rfr_active>; 966 pinctrl-1 = <&blsp2_uart1_tx_sleep &blsp2_uart1_rxcts_sleep 967 &blsp2_uart1_rfr_sleep>; 968 status = "disabled"; 969 }; 970 971 blsp_i2c5: i2c@c1b5000 { 972 compatible = "qcom,i2c-qup-v2.2.1"; 973 reg = <0x0c1b5000 0x600>; 974 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 975 976 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, 977 <&gcc GCC_BLSP2_AHB_CLK>; 978 clock-names = "core", "iface"; 979 clock-frequency = <400000>; 980 981 pinctrl-names = "default", "sleep"; 982 pinctrl-0 = <&i2c5_default>; 983 pinctrl-1 = <&i2c5_sleep>; 984 #address-cells = <1>; 985 #size-cells = <0>; 986 status = "disabled"; 987 }; 988 989 blsp_i2c6: i2c@c1b6000 { 990 compatible = "qcom,i2c-qup-v2.2.1"; 991 reg = <0x0c1b6000 0x600>; 992 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 993 994 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, 995 <&gcc GCC_BLSP2_AHB_CLK>; 996 clock-names = "core", "iface"; 997 clock-frequency = <400000>; 998 999 pinctrl-names = "default", "sleep"; 1000 pinctrl-0 = <&i2c6_default>; 1001 pinctrl-1 = <&i2c6_sleep>; 1002 #address-cells = <1>; 1003 #size-cells = <0>; 1004 status = "disabled"; 1005 }; 1006 1007 blsp_i2c7: i2c@c1b7000 { 1008 compatible = "qcom,i2c-qup-v2.2.1"; 1009 reg = <0x0c1b7000 0x600>; 1010 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 1011 1012 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>, 1013 <&gcc GCC_BLSP2_AHB_CLK>; 1014 clock-names = "core", "iface"; 1015 clock-frequency = <400000>; 1016 1017 pinctrl-names = "default", "sleep"; 1018 pinctrl-0 = <&i2c7_default>; 1019 pinctrl-1 = <&i2c7_sleep>; 1020 #address-cells = <1>; 1021 #size-cells = <0>; 1022 status = "disabled"; 1023 }; 1024 1025 blsp_i2c8: i2c@c1b8000 { 1026 compatible = "qcom,i2c-qup-v2.2.1"; 1027 reg = <0x0c1b8000 0x600>; 1028 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 1029 1030 clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>, 1031 <&gcc GCC_BLSP2_AHB_CLK>; 1032 clock-names = "core", "iface"; 1033 clock-frequency = <400000>; 1034 1035 pinctrl-names = "default", "sleep"; 1036 pinctrl-0 = <&i2c8_default>; 1037 pinctrl-1 = <&i2c8_sleep>; 1038 #address-cells = <1>; 1039 #size-cells = <0>; 1040 status = "disabled"; 1041 }; 1042 1043 mmss_smmu: iommu@cd00000 { 1044 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2"; 1045 reg = <0x0cd00000 0x40000>; 1046 #iommu-cells = <1>; 1047 1048 #global-interrupts = <2>; 1049 interrupts = 1050 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 1051 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 1052 1053 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 1054 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 1055 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, 1056 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 1057 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 1058 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 1059 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 1060 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 1061 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 1062 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 1063 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 1064 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 1065 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 1066 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 1067 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 1068 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 1069 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 1070 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 1071 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 1072 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, 1073 <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, 1074 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 1075 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 1076 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>; 1077 }; 1078 1079 apcs_glb: mailbox@17911000 { 1080 compatible = "qcom,sdm660-apcs-hmss-global"; 1081 reg = <0x17911000 0x1000>; 1082 1083 #mbox-cells = <1>; 1084 }; 1085 1086 timer@17920000 { 1087 #address-cells = <1>; 1088 #size-cells = <1>; 1089 ranges; 1090 compatible = "arm,armv7-timer-mem"; 1091 reg = <0x17920000 0x1000>; 1092 clock-frequency = <19200000>; 1093 1094 frame@17921000 { 1095 frame-number = <0>; 1096 interrupts = <0 8 0x4>, 1097 <0 7 0x4>; 1098 reg = <0x17921000 0x1000>, 1099 <0x17922000 0x1000>; 1100 }; 1101 1102 frame@17923000 { 1103 frame-number = <1>; 1104 interrupts = <0 9 0x4>; 1105 reg = <0x17923000 0x1000>; 1106 status = "disabled"; 1107 }; 1108 1109 frame@17924000 { 1110 frame-number = <2>; 1111 interrupts = <0 10 0x4>; 1112 reg = <0x17924000 0x1000>; 1113 status = "disabled"; 1114 }; 1115 1116 frame@17925000 { 1117 frame-number = <3>; 1118 interrupts = <0 11 0x4>; 1119 reg = <0x17925000 0x1000>; 1120 status = "disabled"; 1121 }; 1122 1123 frame@17926000 { 1124 frame-number = <4>; 1125 interrupts = <0 12 0x4>; 1126 reg = <0x17926000 0x1000>; 1127 status = "disabled"; 1128 }; 1129 1130 frame@17927000 { 1131 frame-number = <5>; 1132 interrupts = <0 13 0x4>; 1133 reg = <0x17927000 0x1000>; 1134 status = "disabled"; 1135 }; 1136 1137 frame@17928000 { 1138 frame-number = <6>; 1139 interrupts = <0 14 0x4>; 1140 reg = <0x17928000 0x1000>; 1141 status = "disabled"; 1142 }; 1143 }; 1144 1145 intc: interrupt-controller@17a00000 { 1146 compatible = "arm,gic-v3"; 1147 reg = <0x17a00000 0x10000>, /* GICD */ 1148 <0x17b00000 0x100000>; /* GICR * 8 */ 1149 #interrupt-cells = <3>; 1150 #address-cells = <1>; 1151 #size-cells = <1>; 1152 ranges; 1153 interrupt-controller; 1154 #redistributor-regions = <1>; 1155 redistributor-stride = <0x0 0x20000>; 1156 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 1157 }; 1158 }; 1159 1160 tcsr_mutex: hwlock { 1161 compatible = "qcom,tcsr-mutex"; 1162 syscon = <&tcsr_mutex_regs 0 0x1000>; 1163 #hwlock-cells = <1>; 1164 }; 1165 1166 timer { 1167 compatible = "arm,armv8-timer"; 1168 interrupts = <GIC_PPI 1 0xf08>, 1169 <GIC_PPI 2 0xf08>, 1170 <GIC_PPI 3 0xf08>, 1171 <GIC_PPI 0 0xf08>; 1172 }; 1173}; 1174 1175