1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2020, Konrad Dybcio <konradybcio@gmail.com> 4 * Copyright (c) 2020, AngeloGioacchino Del Regno <kholk11@gmail.com> 5 */ 6 7#include <dt-bindings/clock/qcom,gcc-sdm660.h> 8#include <dt-bindings/clock/qcom,gpucc-sdm660.h> 9#include <dt-bindings/clock/qcom,mmcc-sdm660.h> 10#include <dt-bindings/clock/qcom,rpmcc.h> 11#include <dt-bindings/interconnect/qcom,sdm660.h> 12#include <dt-bindings/power/qcom-rpmpd.h> 13#include <dt-bindings/gpio/gpio.h> 14#include <dt-bindings/interrupt-controller/arm-gic.h> 15#include <dt-bindings/soc/qcom,apr.h> 16 17/ { 18 interrupt-parent = <&intc>; 19 20 #address-cells = <2>; 21 #size-cells = <2>; 22 23 aliases { 24 mmc1 = &sdhc_1; 25 mmc2 = &sdhc_2; 26 }; 27 28 chosen { }; 29 30 clocks { 31 xo_board: xo-board { 32 compatible = "fixed-clock"; 33 #clock-cells = <0>; 34 clock-frequency = <19200000>; 35 clock-output-names = "xo_board"; 36 }; 37 38 sleep_clk: sleep-clk { 39 compatible = "fixed-clock"; 40 #clock-cells = <0>; 41 clock-frequency = <32764>; 42 clock-output-names = "sleep_clk"; 43 }; 44 }; 45 46 cpus { 47 #address-cells = <2>; 48 #size-cells = <0>; 49 50 CPU0: cpu@100 { 51 device_type = "cpu"; 52 compatible = "arm,cortex-a53"; 53 reg = <0x0 0x100>; 54 enable-method = "psci"; 55 cpu-idle-states = <&PERF_CPU_SLEEP_0 56 &PERF_CPU_SLEEP_1 57 &PERF_CLUSTER_SLEEP_0 58 &PERF_CLUSTER_SLEEP_1 59 &PERF_CLUSTER_SLEEP_2>; 60 capacity-dmips-mhz = <1126>; 61 #cooling-cells = <2>; 62 next-level-cache = <&L2_1>; 63 L2_1: l2-cache { 64 compatible = "cache"; 65 cache-level = <2>; 66 }; 67 }; 68 69 CPU1: cpu@101 { 70 device_type = "cpu"; 71 compatible = "arm,cortex-a53"; 72 reg = <0x0 0x101>; 73 enable-method = "psci"; 74 cpu-idle-states = <&PERF_CPU_SLEEP_0 75 &PERF_CPU_SLEEP_1 76 &PERF_CLUSTER_SLEEP_0 77 &PERF_CLUSTER_SLEEP_1 78 &PERF_CLUSTER_SLEEP_2>; 79 capacity-dmips-mhz = <1126>; 80 #cooling-cells = <2>; 81 next-level-cache = <&L2_1>; 82 }; 83 84 CPU2: cpu@102 { 85 device_type = "cpu"; 86 compatible = "arm,cortex-a53"; 87 reg = <0x0 0x102>; 88 enable-method = "psci"; 89 cpu-idle-states = <&PERF_CPU_SLEEP_0 90 &PERF_CPU_SLEEP_1 91 &PERF_CLUSTER_SLEEP_0 92 &PERF_CLUSTER_SLEEP_1 93 &PERF_CLUSTER_SLEEP_2>; 94 capacity-dmips-mhz = <1126>; 95 #cooling-cells = <2>; 96 next-level-cache = <&L2_1>; 97 }; 98 99 CPU3: cpu@103 { 100 device_type = "cpu"; 101 compatible = "arm,cortex-a53"; 102 reg = <0x0 0x103>; 103 enable-method = "psci"; 104 cpu-idle-states = <&PERF_CPU_SLEEP_0 105 &PERF_CPU_SLEEP_1 106 &PERF_CLUSTER_SLEEP_0 107 &PERF_CLUSTER_SLEEP_1 108 &PERF_CLUSTER_SLEEP_2>; 109 capacity-dmips-mhz = <1126>; 110 #cooling-cells = <2>; 111 next-level-cache = <&L2_1>; 112 }; 113 114 CPU4: cpu@0 { 115 device_type = "cpu"; 116 compatible = "arm,cortex-a53"; 117 reg = <0x0 0x0>; 118 enable-method = "psci"; 119 cpu-idle-states = <&PWR_CPU_SLEEP_0 120 &PWR_CPU_SLEEP_1 121 &PWR_CLUSTER_SLEEP_0 122 &PWR_CLUSTER_SLEEP_1 123 &PWR_CLUSTER_SLEEP_2>; 124 capacity-dmips-mhz = <1024>; 125 #cooling-cells = <2>; 126 next-level-cache = <&L2_0>; 127 L2_0: l2-cache { 128 compatible = "cache"; 129 cache-level = <2>; 130 }; 131 }; 132 133 CPU5: cpu@1 { 134 device_type = "cpu"; 135 compatible = "arm,cortex-a53"; 136 reg = <0x0 0x1>; 137 enable-method = "psci"; 138 cpu-idle-states = <&PWR_CPU_SLEEP_0 139 &PWR_CPU_SLEEP_1 140 &PWR_CLUSTER_SLEEP_0 141 &PWR_CLUSTER_SLEEP_1 142 &PWR_CLUSTER_SLEEP_2>; 143 capacity-dmips-mhz = <1024>; 144 #cooling-cells = <2>; 145 next-level-cache = <&L2_0>; 146 }; 147 148 CPU6: cpu@2 { 149 device_type = "cpu"; 150 compatible = "arm,cortex-a53"; 151 reg = <0x0 0x2>; 152 enable-method = "psci"; 153 cpu-idle-states = <&PWR_CPU_SLEEP_0 154 &PWR_CPU_SLEEP_1 155 &PWR_CLUSTER_SLEEP_0 156 &PWR_CLUSTER_SLEEP_1 157 &PWR_CLUSTER_SLEEP_2>; 158 capacity-dmips-mhz = <1024>; 159 #cooling-cells = <2>; 160 next-level-cache = <&L2_0>; 161 }; 162 163 CPU7: cpu@3 { 164 device_type = "cpu"; 165 compatible = "arm,cortex-a53"; 166 reg = <0x0 0x3>; 167 enable-method = "psci"; 168 cpu-idle-states = <&PWR_CPU_SLEEP_0 169 &PWR_CPU_SLEEP_1 170 &PWR_CLUSTER_SLEEP_0 171 &PWR_CLUSTER_SLEEP_1 172 &PWR_CLUSTER_SLEEP_2>; 173 capacity-dmips-mhz = <1024>; 174 #cooling-cells = <2>; 175 next-level-cache = <&L2_0>; 176 }; 177 178 cpu-map { 179 cluster0 { 180 core0 { 181 cpu = <&CPU4>; 182 }; 183 184 core1 { 185 cpu = <&CPU5>; 186 }; 187 188 core2 { 189 cpu = <&CPU6>; 190 }; 191 192 core3 { 193 cpu = <&CPU7>; 194 }; 195 }; 196 197 cluster1 { 198 core0 { 199 cpu = <&CPU0>; 200 }; 201 202 core1 { 203 cpu = <&CPU1>; 204 }; 205 206 core2 { 207 cpu = <&CPU2>; 208 }; 209 210 core3 { 211 cpu = <&CPU3>; 212 }; 213 }; 214 }; 215 216 idle-states { 217 entry-method = "psci"; 218 219 PWR_CPU_SLEEP_0: cpu-sleep-0-0 { 220 compatible = "arm,idle-state"; 221 idle-state-name = "pwr-retention"; 222 arm,psci-suspend-param = <0x40000002>; 223 entry-latency-us = <338>; 224 exit-latency-us = <423>; 225 min-residency-us = <200>; 226 }; 227 228 PWR_CPU_SLEEP_1: cpu-sleep-0-1 { 229 compatible = "arm,idle-state"; 230 idle-state-name = "pwr-power-collapse"; 231 arm,psci-suspend-param = <0x40000003>; 232 entry-latency-us = <515>; 233 exit-latency-us = <1821>; 234 min-residency-us = <1000>; 235 local-timer-stop; 236 }; 237 238 PERF_CPU_SLEEP_0: cpu-sleep-1-0 { 239 compatible = "arm,idle-state"; 240 idle-state-name = "perf-retention"; 241 arm,psci-suspend-param = <0x40000002>; 242 entry-latency-us = <154>; 243 exit-latency-us = <87>; 244 min-residency-us = <200>; 245 }; 246 247 PERF_CPU_SLEEP_1: cpu-sleep-1-1 { 248 compatible = "arm,idle-state"; 249 idle-state-name = "perf-power-collapse"; 250 arm,psci-suspend-param = <0x40000003>; 251 entry-latency-us = <262>; 252 exit-latency-us = <301>; 253 min-residency-us = <1000>; 254 local-timer-stop; 255 }; 256 257 PWR_CLUSTER_SLEEP_0: cluster-sleep-0-0 { 258 compatible = "arm,idle-state"; 259 idle-state-name = "pwr-cluster-dynamic-retention"; 260 arm,psci-suspend-param = <0x400000F2>; 261 entry-latency-us = <284>; 262 exit-latency-us = <384>; 263 min-residency-us = <9987>; 264 local-timer-stop; 265 }; 266 267 PWR_CLUSTER_SLEEP_1: cluster-sleep-0-1 { 268 compatible = "arm,idle-state"; 269 idle-state-name = "pwr-cluster-retention"; 270 arm,psci-suspend-param = <0x400000F3>; 271 entry-latency-us = <338>; 272 exit-latency-us = <423>; 273 min-residency-us = <9987>; 274 local-timer-stop; 275 }; 276 277 PWR_CLUSTER_SLEEP_2: cluster-sleep-0-2 { 278 compatible = "arm,idle-state"; 279 idle-state-name = "pwr-cluster-retention"; 280 arm,psci-suspend-param = <0x400000F4>; 281 entry-latency-us = <515>; 282 exit-latency-us = <1821>; 283 min-residency-us = <9987>; 284 local-timer-stop; 285 }; 286 287 PERF_CLUSTER_SLEEP_0: cluster-sleep-1-0 { 288 compatible = "arm,idle-state"; 289 idle-state-name = "perf-cluster-dynamic-retention"; 290 arm,psci-suspend-param = <0x400000F2>; 291 entry-latency-us = <272>; 292 exit-latency-us = <329>; 293 min-residency-us = <9987>; 294 local-timer-stop; 295 }; 296 297 PERF_CLUSTER_SLEEP_1: cluster-sleep-1-1 { 298 compatible = "arm,idle-state"; 299 idle-state-name = "perf-cluster-retention"; 300 arm,psci-suspend-param = <0x400000F3>; 301 entry-latency-us = <332>; 302 exit-latency-us = <368>; 303 min-residency-us = <9987>; 304 local-timer-stop; 305 }; 306 307 PERF_CLUSTER_SLEEP_2: cluster-sleep-1-2 { 308 compatible = "arm,idle-state"; 309 idle-state-name = "perf-cluster-retention"; 310 arm,psci-suspend-param = <0x400000F4>; 311 entry-latency-us = <545>; 312 exit-latency-us = <1609>; 313 min-residency-us = <9987>; 314 local-timer-stop; 315 }; 316 }; 317 }; 318 319 firmware { 320 scm { 321 compatible = "qcom,scm-msm8998", "qcom,scm"; 322 }; 323 }; 324 325 memory@80000000 { 326 device_type = "memory"; 327 /* We expect the bootloader to fill in the reg */ 328 reg = <0x0 0x80000000 0x0 0x0>; 329 }; 330 331 pmu { 332 compatible = "arm,armv8-pmuv3"; 333 interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>; 334 }; 335 336 psci { 337 compatible = "arm,psci-1.0"; 338 method = "smc"; 339 }; 340 341 reserved-memory { 342 #address-cells = <2>; 343 #size-cells = <2>; 344 ranges; 345 346 wlan_msa_guard: wlan-msa-guard@85600000 { 347 reg = <0x0 0x85600000 0x0 0x100000>; 348 no-map; 349 }; 350 351 wlan_msa_mem: wlan-msa-mem@85700000 { 352 reg = <0x0 0x85700000 0x0 0x100000>; 353 no-map; 354 }; 355 356 qhee_code: qhee-code@85800000 { 357 reg = <0x0 0x85800000 0x0 0x600000>; 358 no-map; 359 }; 360 361 rmtfs_mem: memory@85e00000 { 362 compatible = "qcom,rmtfs-mem"; 363 reg = <0x0 0x85e00000 0x0 0x200000>; 364 no-map; 365 366 qcom,client-id = <1>; 367 qcom,vmid = <15>; 368 }; 369 370 smem_region: smem-mem@86000000 { 371 reg = <0 0x86000000 0 0x200000>; 372 no-map; 373 }; 374 375 tz_mem: memory@86200000 { 376 reg = <0x0 0x86200000 0x0 0x3300000>; 377 no-map; 378 }; 379 380 mpss_region: mpss@8ac00000 { 381 reg = <0x0 0x8ac00000 0x0 0x7e00000>; 382 no-map; 383 }; 384 385 adsp_region: adsp@92a00000 { 386 reg = <0x0 0x92a00000 0x0 0x1e00000>; 387 no-map; 388 }; 389 390 mba_region: mba@94800000 { 391 reg = <0x0 0x94800000 0x0 0x200000>; 392 no-map; 393 }; 394 395 buffer_mem: tzbuffer@94a00000 { 396 reg = <0x0 0x94a00000 0x0 0x100000>; 397 no-map; 398 }; 399 400 venus_region: venus@9f800000 { 401 reg = <0x0 0x9f800000 0x0 0x800000>; 402 no-map; 403 }; 404 405 adsp_mem: adsp-region@f6000000 { 406 reg = <0x0 0xf6000000 0x0 0x800000>; 407 no-map; 408 }; 409 410 qseecom_mem: qseecom-region@f6800000 { 411 reg = <0x0 0xf6800000 0x0 0x1400000>; 412 no-map; 413 }; 414 415 zap_shader_region: gpu@fed00000 { 416 compatible = "shared-dma-pool"; 417 reg = <0x0 0xfed00000 0x0 0xa00000>; 418 no-map; 419 }; 420 }; 421 422 rpm-glink { 423 compatible = "qcom,glink-rpm"; 424 425 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 426 qcom,rpm-msg-ram = <&rpm_msg_ram>; 427 mboxes = <&apcs_glb 0>; 428 429 rpm_requests: rpm-requests { 430 compatible = "qcom,rpm-sdm660"; 431 qcom,glink-channels = "rpm_requests"; 432 433 rpmcc: clock-controller { 434 compatible = "qcom,rpmcc-sdm660", "qcom,rpmcc"; 435 #clock-cells = <1>; 436 }; 437 438 rpmpd: power-controller { 439 compatible = "qcom,sdm660-rpmpd"; 440 #power-domain-cells = <1>; 441 operating-points-v2 = <&rpmpd_opp_table>; 442 443 rpmpd_opp_table: opp-table { 444 compatible = "operating-points-v2"; 445 446 rpmpd_opp_ret: opp1 { 447 opp-level = <RPM_SMD_LEVEL_RETENTION>; 448 }; 449 450 rpmpd_opp_ret_plus: opp2 { 451 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>; 452 }; 453 454 rpmpd_opp_min_svs: opp3 { 455 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 456 }; 457 458 rpmpd_opp_low_svs: opp4 { 459 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 460 }; 461 462 rpmpd_opp_svs: opp5 { 463 opp-level = <RPM_SMD_LEVEL_SVS>; 464 }; 465 466 rpmpd_opp_svs_plus: opp6 { 467 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 468 }; 469 470 rpmpd_opp_nom: opp7 { 471 opp-level = <RPM_SMD_LEVEL_NOM>; 472 }; 473 474 rpmpd_opp_nom_plus: opp8 { 475 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 476 }; 477 478 rpmpd_opp_turbo: opp9 { 479 opp-level = <RPM_SMD_LEVEL_TURBO>; 480 }; 481 }; 482 }; 483 }; 484 }; 485 486 smem: smem { 487 compatible = "qcom,smem"; 488 memory-region = <&smem_region>; 489 hwlocks = <&tcsr_mutex 3>; 490 }; 491 492 smp2p-adsp { 493 compatible = "qcom,smp2p"; 494 qcom,smem = <443>, <429>; 495 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 496 mboxes = <&apcs_glb 10>; 497 qcom,local-pid = <0>; 498 qcom,remote-pid = <2>; 499 500 adsp_smp2p_out: master-kernel { 501 qcom,entry-name = "master-kernel"; 502 #qcom,smem-state-cells = <1>; 503 }; 504 505 adsp_smp2p_in: slave-kernel { 506 qcom,entry-name = "slave-kernel"; 507 interrupt-controller; 508 #interrupt-cells = <2>; 509 }; 510 }; 511 512 smp2p-mpss { 513 compatible = "qcom,smp2p"; 514 qcom,smem = <435>, <428>; 515 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 516 mboxes = <&apcs_glb 14>; 517 qcom,local-pid = <0>; 518 qcom,remote-pid = <1>; 519 520 modem_smp2p_out: master-kernel { 521 qcom,entry-name = "master-kernel"; 522 #qcom,smem-state-cells = <1>; 523 }; 524 525 modem_smp2p_in: slave-kernel { 526 qcom,entry-name = "slave-kernel"; 527 interrupt-controller; 528 #interrupt-cells = <2>; 529 }; 530 }; 531 532 soc { 533 #address-cells = <1>; 534 #size-cells = <1>; 535 ranges = <0 0 0 0xffffffff>; 536 compatible = "simple-bus"; 537 538 gcc: clock-controller@100000 { 539 compatible = "qcom,gcc-sdm630"; 540 #clock-cells = <1>; 541 #reset-cells = <1>; 542 #power-domain-cells = <1>; 543 reg = <0x00100000 0x94000>; 544 545 clock-names = "xo", "sleep_clk"; 546 clocks = <&xo_board>, 547 <&sleep_clk>; 548 }; 549 550 rpm_msg_ram: sram@778000 { 551 compatible = "qcom,rpm-msg-ram"; 552 reg = <0x00778000 0x7000>; 553 }; 554 555 qfprom: qfprom@780000 { 556 compatible = "qcom,sdm630-qfprom", "qcom,qfprom"; 557 reg = <0x00780000 0x621c>; 558 #address-cells = <1>; 559 #size-cells = <1>; 560 561 qusb2_hstx_trim: hstx-trim@240 { 562 reg = <0x243 0x1>; 563 bits = <1 3>; 564 }; 565 566 gpu_speed_bin: gpu-speed-bin@41a0 { 567 reg = <0x41a2 0x1>; 568 bits = <5 7>; 569 }; 570 }; 571 572 rng: rng@793000 { 573 compatible = "qcom,prng-ee"; 574 reg = <0x00793000 0x1000>; 575 clocks = <&gcc GCC_PRNG_AHB_CLK>; 576 clock-names = "core"; 577 }; 578 579 bimc: interconnect@1008000 { 580 compatible = "qcom,sdm660-bimc"; 581 reg = <0x01008000 0x78000>; 582 #interconnect-cells = <1>; 583 clock-names = "bus", "bus_a"; 584 clocks = <&rpmcc RPM_SMD_BIMC_CLK>, 585 <&rpmcc RPM_SMD_BIMC_A_CLK>; 586 }; 587 588 restart@10ac000 { 589 compatible = "qcom,pshold"; 590 reg = <0x010ac000 0x4>; 591 }; 592 593 cnoc: interconnect@1500000 { 594 compatible = "qcom,sdm660-cnoc"; 595 reg = <0x01500000 0x10000>; 596 #interconnect-cells = <1>; 597 clock-names = "bus", "bus_a"; 598 clocks = <&rpmcc RPM_SMD_CNOC_CLK>, 599 <&rpmcc RPM_SMD_CNOC_A_CLK>; 600 }; 601 602 snoc: interconnect@1626000 { 603 compatible = "qcom,sdm660-snoc"; 604 reg = <0x01626000 0x7090>; 605 #interconnect-cells = <1>; 606 clock-names = "bus", "bus_a"; 607 clocks = <&rpmcc RPM_SMD_SNOC_CLK>, 608 <&rpmcc RPM_SMD_SNOC_A_CLK>; 609 }; 610 611 anoc2_smmu: iommu@16c0000 { 612 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2"; 613 reg = <0x016c0000 0x40000>; 614 615 assigned-clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>; 616 assigned-clock-rates = <1000>; 617 clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>; 618 clock-names = "bus"; 619 #global-interrupts = <2>; 620 #iommu-cells = <1>; 621 622 interrupts = 623 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 624 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 625 626 <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>, 627 <GIC_SPI 374 IRQ_TYPE_LEVEL_LOW>, 628 <GIC_SPI 375 IRQ_TYPE_LEVEL_LOW>, 629 <GIC_SPI 376 IRQ_TYPE_LEVEL_LOW>, 630 <GIC_SPI 377 IRQ_TYPE_LEVEL_LOW>, 631 <GIC_SPI 378 IRQ_TYPE_LEVEL_LOW>, 632 <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>, 633 <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>, 634 <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>, 635 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>, 636 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>, 637 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>, 638 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>, 639 <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, 640 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>, 641 <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>, 642 <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>, 643 <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, 644 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, 645 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, 646 <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>, 647 <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>, 648 <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, 649 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>, 650 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>, 651 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>, 652 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, 653 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, 654 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>; 655 656 status = "disabled"; 657 }; 658 659 a2noc: interconnect@1704000 { 660 compatible = "qcom,sdm660-a2noc"; 661 reg = <0x01704000 0xc100>; 662 #interconnect-cells = <1>; 663 clock-names = "bus", 664 "bus_a", 665 "ipa", 666 "ufs_axi", 667 "aggre2_ufs_axi", 668 "aggre2_usb3_axi", 669 "cfg_noc_usb2_axi"; 670 clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>, 671 <&rpmcc RPM_SMD_AGGR2_NOC_A_CLK>, 672 <&rpmcc RPM_SMD_IPA_CLK>, 673 <&gcc GCC_UFS_AXI_CLK>, 674 <&gcc GCC_AGGRE2_UFS_AXI_CLK>, 675 <&gcc GCC_AGGRE2_USB3_AXI_CLK>, 676 <&gcc GCC_CFG_NOC_USB2_AXI_CLK>; 677 }; 678 679 mnoc: interconnect@1745000 { 680 compatible = "qcom,sdm660-mnoc"; 681 reg = <0x01745000 0xA010>; 682 #interconnect-cells = <1>; 683 clock-names = "bus", "bus_a", "iface"; 684 clocks = <&rpmcc RPM_SMD_MMSSNOC_AXI_CLK>, 685 <&rpmcc RPM_SMD_MMSSNOC_AXI_CLK_A>, 686 <&mmcc AHB_CLK_SRC>; 687 }; 688 689 tsens: thermal-sensor@10ae000 { 690 compatible = "qcom,sdm630-tsens", "qcom,tsens-v2"; 691 reg = <0x010ae000 0x1000>, /* TM */ 692 <0x010ad000 0x1000>; /* SROT */ 693 #qcom,sensors = <12>; 694 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 695 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>; 696 interrupt-names = "uplow", "critical"; 697 #thermal-sensor-cells = <1>; 698 }; 699 700 tcsr_mutex: hwlock@1f40000 { 701 compatible = "qcom,tcsr-mutex"; 702 reg = <0x01f40000 0x20000>; 703 #hwlock-cells = <1>; 704 }; 705 706 tcsr_regs_1: syscon@1f60000 { 707 compatible = "qcom,sdm630-tcsr", "syscon"; 708 reg = <0x01f60000 0x20000>; 709 }; 710 711 tlmm: pinctrl@3100000 { 712 compatible = "qcom,sdm630-pinctrl"; 713 reg = <0x03100000 0x400000>, 714 <0x03500000 0x400000>, 715 <0x03900000 0x400000>; 716 reg-names = "south", "center", "north"; 717 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 718 gpio-controller; 719 gpio-ranges = <&tlmm 0 0 114>; 720 #gpio-cells = <2>; 721 interrupt-controller; 722 #interrupt-cells = <2>; 723 724 blsp1_uart1_default: blsp1-uart1-default-state { 725 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 726 function = "blsp_uart1"; 727 drive-strength = <2>; 728 bias-disable; 729 }; 730 731 blsp1_uart1_sleep: blsp1-uart1-sleep-state { 732 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 733 function = "gpio"; 734 drive-strength = <2>; 735 bias-disable; 736 }; 737 738 blsp1_uart2_default: blsp1-uart2-default-state { 739 pins = "gpio4", "gpio5"; 740 function = "blsp_uart2"; 741 drive-strength = <2>; 742 bias-disable; 743 }; 744 745 blsp2_uart1_default: blsp2-uart1-active-state { 746 tx-rts-pins { 747 pins = "gpio16", "gpio19"; 748 function = "blsp_uart5"; 749 drive-strength = <2>; 750 bias-disable; 751 }; 752 753 rx-pins { 754 /* 755 * Avoid garbage data while BT module 756 * is powered off or not driving signal 757 */ 758 pins = "gpio17"; 759 function = "blsp_uart5"; 760 drive-strength = <2>; 761 bias-pull-up; 762 }; 763 764 cts-pins { 765 /* Match the pull of the BT module */ 766 pins = "gpio18"; 767 function = "blsp_uart5"; 768 drive-strength = <2>; 769 bias-pull-down; 770 }; 771 }; 772 773 blsp2_uart1_sleep: blsp2-uart1-sleep-state { 774 tx-pins { 775 pins = "gpio16"; 776 function = "gpio"; 777 drive-strength = <2>; 778 bias-pull-up; 779 }; 780 781 rx-cts-rts-pins { 782 pins = "gpio17", "gpio18", "gpio19"; 783 function = "gpio"; 784 drive-strength = <2>; 785 bias-disable; 786 }; 787 }; 788 789 i2c1_default: i2c1-default-state { 790 pins = "gpio2", "gpio3"; 791 function = "blsp_i2c1"; 792 drive-strength = <2>; 793 bias-disable; 794 }; 795 796 i2c1_sleep: i2c1-sleep-state { 797 pins = "gpio2", "gpio3"; 798 function = "blsp_i2c1"; 799 drive-strength = <2>; 800 bias-pull-up; 801 }; 802 803 i2c2_default: i2c2-default-state { 804 pins = "gpio6", "gpio7"; 805 function = "blsp_i2c2"; 806 drive-strength = <2>; 807 bias-disable; 808 }; 809 810 i2c2_sleep: i2c2-sleep-state { 811 pins = "gpio6", "gpio7"; 812 function = "blsp_i2c2"; 813 drive-strength = <2>; 814 bias-pull-up; 815 }; 816 817 i2c3_default: i2c3-default-state { 818 pins = "gpio10", "gpio11"; 819 function = "blsp_i2c3"; 820 drive-strength = <2>; 821 bias-disable; 822 }; 823 824 i2c3_sleep: i2c3-sleep-state { 825 pins = "gpio10", "gpio11"; 826 function = "blsp_i2c3"; 827 drive-strength = <2>; 828 bias-pull-up; 829 }; 830 831 i2c4_default: i2c4-default-state { 832 pins = "gpio14", "gpio15"; 833 function = "blsp_i2c4"; 834 drive-strength = <2>; 835 bias-disable; 836 }; 837 838 i2c4_sleep: i2c4-sleep-state { 839 pins = "gpio14", "gpio15"; 840 function = "blsp_i2c4"; 841 drive-strength = <2>; 842 bias-pull-up; 843 }; 844 845 i2c5_default: i2c5-default-state { 846 pins = "gpio18", "gpio19"; 847 function = "blsp_i2c5"; 848 drive-strength = <2>; 849 bias-disable; 850 }; 851 852 i2c5_sleep: i2c5-sleep-state { 853 pins = "gpio18", "gpio19"; 854 function = "blsp_i2c5"; 855 drive-strength = <2>; 856 bias-pull-up; 857 }; 858 859 i2c6_default: i2c6-default-state { 860 pins = "gpio22", "gpio23"; 861 function = "blsp_i2c6"; 862 drive-strength = <2>; 863 bias-disable; 864 }; 865 866 i2c6_sleep: i2c6-sleep-state { 867 pins = "gpio22", "gpio23"; 868 function = "blsp_i2c6"; 869 drive-strength = <2>; 870 bias-pull-up; 871 }; 872 873 i2c7_default: i2c7-default-state { 874 pins = "gpio26", "gpio27"; 875 function = "blsp_i2c7"; 876 drive-strength = <2>; 877 bias-disable; 878 }; 879 880 i2c7_sleep: i2c7-sleep-state { 881 pins = "gpio26", "gpio27"; 882 function = "blsp_i2c7"; 883 drive-strength = <2>; 884 bias-pull-up; 885 }; 886 887 i2c8_default: i2c8-default-state { 888 pins = "gpio30", "gpio31"; 889 function = "blsp_i2c8_a"; 890 drive-strength = <2>; 891 bias-disable; 892 }; 893 894 i2c8_sleep: i2c8-sleep-state { 895 pins = "gpio30", "gpio31"; 896 function = "blsp_i2c8_a"; 897 drive-strength = <2>; 898 bias-pull-up; 899 }; 900 901 cci0_default: cci0-default-state { 902 pins = "gpio36","gpio37"; 903 function = "cci_i2c"; 904 bias-pull-up; 905 drive-strength = <2>; 906 }; 907 908 cci1_default: cci1-default-state { 909 pins = "gpio38","gpio39"; 910 function = "cci_i2c"; 911 bias-pull-up; 912 drive-strength = <2>; 913 }; 914 915 sdc1_state_on: sdc1-on-state { 916 clk-pins { 917 pins = "sdc1_clk"; 918 bias-disable; 919 drive-strength = <16>; 920 }; 921 922 cmd-pins { 923 pins = "sdc1_cmd"; 924 bias-pull-up; 925 drive-strength = <10>; 926 }; 927 928 data-pins { 929 pins = "sdc1_data"; 930 bias-pull-up; 931 drive-strength = <10>; 932 }; 933 934 rclk-pins { 935 pins = "sdc1_rclk"; 936 bias-pull-down; 937 }; 938 }; 939 940 sdc1_state_off: sdc1-off-state { 941 clk-pins { 942 pins = "sdc1_clk"; 943 bias-disable; 944 drive-strength = <2>; 945 }; 946 947 cmd-pins { 948 pins = "sdc1_cmd"; 949 bias-pull-up; 950 drive-strength = <2>; 951 }; 952 953 data-pins { 954 pins = "sdc1_data"; 955 bias-pull-up; 956 drive-strength = <2>; 957 }; 958 959 rclk-pins { 960 pins = "sdc1_rclk"; 961 bias-pull-down; 962 }; 963 }; 964 965 sdc2_state_on: sdc2-on-state { 966 clk-pins { 967 pins = "sdc2_clk"; 968 bias-disable; 969 drive-strength = <16>; 970 }; 971 972 cmd-pins { 973 pins = "sdc2_cmd"; 974 bias-pull-up; 975 drive-strength = <10>; 976 }; 977 978 data-pins { 979 pins = "sdc2_data"; 980 bias-pull-up; 981 drive-strength = <10>; 982 }; 983 }; 984 985 sdc2_state_off: sdc2-off-state { 986 clk-pins { 987 pins = "sdc2_clk"; 988 bias-disable; 989 drive-strength = <2>; 990 }; 991 992 cmd-pins { 993 pins = "sdc2_cmd"; 994 bias-pull-up; 995 drive-strength = <2>; 996 }; 997 998 data-pins { 999 pins = "sdc2_data"; 1000 bias-pull-up; 1001 drive-strength = <2>; 1002 }; 1003 }; 1004 }; 1005 1006 adreno_gpu: gpu@5000000 { 1007 compatible = "qcom,adreno-508.0", "qcom,adreno"; 1008 1009 reg = <0x05000000 0x40000>; 1010 reg-names = "kgsl_3d0_reg_memory"; 1011 1012 interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>; 1013 1014 clocks = <&gcc GCC_GPU_CFG_AHB_CLK>, 1015 <&gpucc GPUCC_RBBMTIMER_CLK>, 1016 <&gcc GCC_BIMC_GFX_CLK>, 1017 <&gcc GCC_GPU_BIMC_GFX_CLK>, 1018 <&gpucc GPUCC_RBCPR_CLK>, 1019 <&gpucc GPUCC_GFX3D_CLK>; 1020 1021 clock-names = "iface", 1022 "rbbmtimer", 1023 "mem", 1024 "mem_iface", 1025 "rbcpr", 1026 "core"; 1027 1028 power-domains = <&rpmpd SDM660_VDDMX>; 1029 iommus = <&kgsl_smmu 0>; 1030 1031 nvmem-cells = <&gpu_speed_bin>; 1032 nvmem-cell-names = "speed_bin"; 1033 1034 interconnects = <&bimc MASTER_OXILI &bimc SLAVE_EBI>; 1035 interconnect-names = "gfx-mem"; 1036 1037 operating-points-v2 = <&gpu_sdm630_opp_table>; 1038 1039 status = "disabled"; 1040 1041 gpu_sdm630_opp_table: opp-table { 1042 compatible = "operating-points-v2"; 1043 opp-775000000 { 1044 opp-hz = /bits/ 64 <775000000>; 1045 opp-level = <RPM_SMD_LEVEL_TURBO>; 1046 opp-peak-kBps = <5412000>; 1047 opp-supported-hw = <0xA2>; 1048 }; 1049 opp-647000000 { 1050 opp-hz = /bits/ 64 <647000000>; 1051 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 1052 opp-peak-kBps = <4068000>; 1053 opp-supported-hw = <0xFF>; 1054 }; 1055 opp-588000000 { 1056 opp-hz = /bits/ 64 <588000000>; 1057 opp-level = <RPM_SMD_LEVEL_NOM>; 1058 opp-peak-kBps = <3072000>; 1059 opp-supported-hw = <0xFF>; 1060 }; 1061 opp-465000000 { 1062 opp-hz = /bits/ 64 <465000000>; 1063 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 1064 opp-peak-kBps = <2724000>; 1065 opp-supported-hw = <0xFF>; 1066 }; 1067 opp-370000000 { 1068 opp-hz = /bits/ 64 <370000000>; 1069 opp-level = <RPM_SMD_LEVEL_SVS>; 1070 opp-peak-kBps = <2188000>; 1071 opp-supported-hw = <0xFF>; 1072 }; 1073 opp-240000000 { 1074 opp-hz = /bits/ 64 <240000000>; 1075 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 1076 opp-peak-kBps = <1648000>; 1077 opp-supported-hw = <0xFF>; 1078 }; 1079 opp-160000000 { 1080 opp-hz = /bits/ 64 <160000000>; 1081 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 1082 opp-peak-kBps = <1200000>; 1083 opp-supported-hw = <0xFF>; 1084 }; 1085 }; 1086 }; 1087 1088 kgsl_smmu: iommu@5040000 { 1089 compatible = "qcom,sdm630-smmu-v2", 1090 "qcom,adreno-smmu", "qcom,smmu-v2"; 1091 reg = <0x05040000 0x10000>; 1092 1093 /* 1094 * GX GDSC parent is CX. We need to bring up CX for SMMU 1095 * but we need both up for Adreno. On the other hand, we 1096 * need to manage the GX rpmpd domain in the adreno driver. 1097 * Enable CX/GX GDSCs here so that we can manage just the GX 1098 * RPM Power Domain in the Adreno driver. 1099 */ 1100 power-domains = <&gpucc GPU_GX_GDSC>; 1101 clocks = <&gcc GCC_GPU_CFG_AHB_CLK>, 1102 <&gcc GCC_BIMC_GFX_CLK>, 1103 <&gcc GCC_GPU_BIMC_GFX_CLK>; 1104 clock-names = "iface", "mem", "mem_iface"; 1105 #global-interrupts = <2>; 1106 #iommu-cells = <1>; 1107 1108 interrupts = 1109 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 1110 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 1111 1112 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 1113 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 1114 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 1115 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 1116 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1117 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1118 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>, 1119 <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>; 1120 1121 status = "disabled"; 1122 }; 1123 1124 gpucc: clock-controller@5065000 { 1125 compatible = "qcom,gpucc-sdm630"; 1126 #clock-cells = <1>; 1127 #reset-cells = <1>; 1128 #power-domain-cells = <1>; 1129 reg = <0x05065000 0x9038>; 1130 1131 clocks = <&xo_board>, 1132 <&gcc GCC_GPU_GPLL0_CLK>, 1133 <&gcc GCC_GPU_GPLL0_DIV_CLK>; 1134 clock-names = "xo", 1135 "gcc_gpu_gpll0_clk", 1136 "gcc_gpu_gpll0_div_clk"; 1137 status = "disabled"; 1138 }; 1139 1140 lpass_smmu: iommu@5100000 { 1141 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2"; 1142 reg = <0x05100000 0x40000>; 1143 #iommu-cells = <1>; 1144 1145 #global-interrupts = <2>; 1146 interrupts = 1147 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 1148 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 1149 1150 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, 1151 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>, 1152 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>, 1153 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 1154 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 1155 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 1156 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 1157 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 1158 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 1159 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 1160 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 1161 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 1162 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 1163 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, 1164 <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>, 1165 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 1166 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>; 1167 1168 status = "disabled"; 1169 }; 1170 1171 sram@290000 { 1172 compatible = "qcom,rpm-stats"; 1173 reg = <0x00290000 0x10000>; 1174 }; 1175 1176 spmi_bus: spmi@800f000 { 1177 compatible = "qcom,spmi-pmic-arb"; 1178 reg = <0x0800f000 0x1000>, 1179 <0x08400000 0x1000000>, 1180 <0x09400000 0x1000000>, 1181 <0x0a400000 0x220000>, 1182 <0x0800a000 0x3000>; 1183 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1184 interrupt-names = "periph_irq"; 1185 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>; 1186 qcom,ee = <0>; 1187 qcom,channel = <0>; 1188 #address-cells = <2>; 1189 #size-cells = <0>; 1190 interrupt-controller; 1191 #interrupt-cells = <4>; 1192 cell-index = <0>; 1193 }; 1194 1195 usb3: usb@a8f8800 { 1196 compatible = "qcom,sdm660-dwc3", "qcom,dwc3"; 1197 reg = <0x0a8f8800 0x400>; 1198 status = "disabled"; 1199 #address-cells = <1>; 1200 #size-cells = <1>; 1201 ranges; 1202 1203 clocks = <&gcc GCC_CFG_NOC_USB3_AXI_CLK>, 1204 <&gcc GCC_USB30_MASTER_CLK>, 1205 <&gcc GCC_AGGRE2_USB3_AXI_CLK>, 1206 <&gcc GCC_USB30_SLEEP_CLK>, 1207 <&gcc GCC_USB30_MOCK_UTMI_CLK>, 1208 <&rpmcc RPM_SMD_AGGR2_NOC_CLK>; 1209 clock-names = "cfg_noc", 1210 "core", 1211 "iface", 1212 "sleep", 1213 "mock_utmi", 1214 "bus"; 1215 1216 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, 1217 <&gcc GCC_USB30_MASTER_CLK>, 1218 <&rpmcc RPM_SMD_AGGR2_NOC_CLK>; 1219 assigned-clock-rates = <19200000>, <120000000>, 1220 <19200000>; 1221 1222 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, 1223 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 1224 interrupt-names = "hs_phy_irq", "ss_phy_irq"; 1225 1226 power-domains = <&gcc USB_30_GDSC>; 1227 qcom,select-utmi-as-pipe-clk; 1228 1229 resets = <&gcc GCC_USB_30_BCR>; 1230 1231 usb3_dwc3: usb@a800000 { 1232 compatible = "snps,dwc3"; 1233 reg = <0x0a800000 0xc8d0>; 1234 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 1235 snps,dis_u2_susphy_quirk; 1236 snps,dis_enblslpm_quirk; 1237 1238 /* 1239 * SDM630 technically supports USB3 but I 1240 * haven't seen any devices making use of it. 1241 */ 1242 maximum-speed = "high-speed"; 1243 phys = <&qusb2phy0>; 1244 phy-names = "usb2-phy"; 1245 snps,hird-threshold = /bits/ 8 <0>; 1246 }; 1247 }; 1248 1249 qusb2phy0: phy@c012000 { 1250 compatible = "qcom,sdm660-qusb2-phy"; 1251 reg = <0x0c012000 0x180>; 1252 #phy-cells = <0>; 1253 1254 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 1255 <&gcc GCC_RX0_USB2_CLKREF_CLK>; 1256 clock-names = "cfg_ahb", "ref"; 1257 1258 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 1259 nvmem-cells = <&qusb2_hstx_trim>; 1260 status = "disabled"; 1261 }; 1262 1263 qusb2phy1: phy@c014000 { 1264 compatible = "qcom,sdm660-qusb2-phy"; 1265 reg = <0x0c014000 0x180>; 1266 #phy-cells = <0>; 1267 1268 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 1269 <&gcc GCC_RX1_USB2_CLKREF_CLK>; 1270 clock-names = "cfg_ahb", "ref"; 1271 1272 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 1273 nvmem-cells = <&qusb2_hstx_trim>; 1274 status = "disabled"; 1275 }; 1276 1277 sdhc_2: mmc@c084000 { 1278 compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5"; 1279 reg = <0x0c084000 0x1000>; 1280 reg-names = "hc"; 1281 1282 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1283 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 1284 interrupt-names = "hc_irq", "pwr_irq"; 1285 1286 bus-width = <4>; 1287 1288 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 1289 <&gcc GCC_SDCC2_APPS_CLK>, 1290 <&xo_board>; 1291 clock-names = "iface", "core", "xo"; 1292 1293 1294 interconnects = <&a2noc 3 &a2noc 10>, 1295 <&gnoc 0 &cnoc 28>; 1296 interconnect-names = "sdhc-ddr","cpu-sdhc"; 1297 operating-points-v2 = <&sdhc2_opp_table>; 1298 1299 pinctrl-names = "default", "sleep"; 1300 pinctrl-0 = <&sdc2_state_on>; 1301 pinctrl-1 = <&sdc2_state_off>; 1302 power-domains = <&rpmpd SDM660_VDDCX>; 1303 1304 status = "disabled"; 1305 1306 sdhc2_opp_table: opp-table { 1307 compatible = "operating-points-v2"; 1308 1309 opp-50000000 { 1310 opp-hz = /bits/ 64 <50000000>; 1311 required-opps = <&rpmpd_opp_low_svs>; 1312 opp-peak-kBps = <200000 140000>; 1313 opp-avg-kBps = <130718 133320>; 1314 }; 1315 opp-100000000 { 1316 opp-hz = /bits/ 64 <100000000>; 1317 required-opps = <&rpmpd_opp_svs>; 1318 opp-peak-kBps = <250000 160000>; 1319 opp-avg-kBps = <196078 150000>; 1320 }; 1321 opp-200000000 { 1322 opp-hz = /bits/ 64 <200000000>; 1323 required-opps = <&rpmpd_opp_nom>; 1324 opp-peak-kBps = <4096000 4096000>; 1325 opp-avg-kBps = <1338562 1338562>; 1326 }; 1327 }; 1328 }; 1329 1330 sdhc_1: mmc@c0c4000 { 1331 compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5"; 1332 reg = <0x0c0c4000 0x1000>, 1333 <0x0c0c5000 0x1000>, 1334 <0x0c0c8000 0x8000>; 1335 reg-names = "hc", "cqhci", "ice"; 1336 1337 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1338 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1339 interrupt-names = "hc_irq", "pwr_irq"; 1340 1341 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 1342 <&gcc GCC_SDCC1_APPS_CLK>, 1343 <&xo_board>, 1344 <&gcc GCC_SDCC1_ICE_CORE_CLK>; 1345 clock-names = "iface", "core", "xo", "ice"; 1346 1347 interconnects = <&a2noc 2 &a2noc 10>, 1348 <&gnoc 0 &cnoc 27>; 1349 interconnect-names = "sdhc-ddr", "cpu-sdhc"; 1350 operating-points-v2 = <&sdhc1_opp_table>; 1351 pinctrl-names = "default", "sleep"; 1352 pinctrl-0 = <&sdc1_state_on>; 1353 pinctrl-1 = <&sdc1_state_off>; 1354 power-domains = <&rpmpd SDM660_VDDCX>; 1355 1356 bus-width = <8>; 1357 non-removable; 1358 1359 status = "disabled"; 1360 1361 sdhc1_opp_table: opp-table { 1362 compatible = "operating-points-v2"; 1363 1364 opp-50000000 { 1365 opp-hz = /bits/ 64 <50000000>; 1366 required-opps = <&rpmpd_opp_low_svs>; 1367 opp-peak-kBps = <200000 140000>; 1368 opp-avg-kBps = <130718 133320>; 1369 }; 1370 opp-100000000 { 1371 opp-hz = /bits/ 64 <100000000>; 1372 required-opps = <&rpmpd_opp_svs>; 1373 opp-peak-kBps = <250000 160000>; 1374 opp-avg-kBps = <196078 150000>; 1375 }; 1376 opp-384000000 { 1377 opp-hz = /bits/ 64 <384000000>; 1378 required-opps = <&rpmpd_opp_nom>; 1379 opp-peak-kBps = <4096000 4096000>; 1380 opp-avg-kBps = <1338562 1338562>; 1381 }; 1382 }; 1383 }; 1384 1385 usb2: usb@c2f8800 { 1386 compatible = "qcom,sdm660-dwc3", "qcom,dwc3"; 1387 reg = <0x0c2f8800 0x400>; 1388 status = "disabled"; 1389 #address-cells = <1>; 1390 #size-cells = <1>; 1391 ranges; 1392 1393 clocks = <&gcc GCC_CFG_NOC_USB2_AXI_CLK>, 1394 <&gcc GCC_USB20_MASTER_CLK>, 1395 <&gcc GCC_USB20_MOCK_UTMI_CLK>, 1396 <&gcc GCC_USB20_SLEEP_CLK>; 1397 clock-names = "cfg_noc", "core", 1398 "mock_utmi", "sleep"; 1399 1400 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, 1401 <&gcc GCC_USB20_MASTER_CLK>; 1402 assigned-clock-rates = <19200000>, <60000000>; 1403 1404 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>; 1405 interrupt-names = "hs_phy_irq"; 1406 1407 qcom,select-utmi-as-pipe-clk; 1408 1409 resets = <&gcc GCC_USB_20_BCR>; 1410 1411 usb2_dwc3: usb@c200000 { 1412 compatible = "snps,dwc3"; 1413 reg = <0x0c200000 0xc8d0>; 1414 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 1415 snps,dis_u2_susphy_quirk; 1416 snps,dis_enblslpm_quirk; 1417 1418 /* This is the HS-only host */ 1419 maximum-speed = "high-speed"; 1420 phys = <&qusb2phy1>; 1421 phy-names = "usb2-phy"; 1422 snps,hird-threshold = /bits/ 8 <0>; 1423 }; 1424 }; 1425 1426 mmcc: clock-controller@c8c0000 { 1427 compatible = "qcom,mmcc-sdm630"; 1428 reg = <0x0c8c0000 0x40000>; 1429 #clock-cells = <1>; 1430 #reset-cells = <1>; 1431 #power-domain-cells = <1>; 1432 clock-names = "xo", 1433 "sleep_clk", 1434 "gpll0", 1435 "gpll0_div", 1436 "dsi0pll", 1437 "dsi0pllbyte", 1438 "dsi1pll", 1439 "dsi1pllbyte", 1440 "dp_link_2x_clk_divsel_five", 1441 "dp_vco_divided_clk_src_mux"; 1442 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 1443 <&sleep_clk>, 1444 <&gcc GCC_MMSS_GPLL0_CLK>, 1445 <&gcc GCC_MMSS_GPLL0_DIV_CLK>, 1446 <&dsi0_phy 1>, 1447 <&dsi0_phy 0>, 1448 <0>, 1449 <0>, 1450 <0>, 1451 <0>; 1452 }; 1453 1454 dsi_opp_table: opp-table-dsi { 1455 compatible = "operating-points-v2"; 1456 1457 opp-131250000 { 1458 opp-hz = /bits/ 64 <131250000>; 1459 required-opps = <&rpmpd_opp_svs>; 1460 }; 1461 1462 opp-210000000 { 1463 opp-hz = /bits/ 64 <210000000>; 1464 required-opps = <&rpmpd_opp_svs_plus>; 1465 }; 1466 1467 opp-262500000 { 1468 opp-hz = /bits/ 64 <262500000>; 1469 required-opps = <&rpmpd_opp_nom>; 1470 }; 1471 }; 1472 1473 mdss: mdss@c900000 { 1474 compatible = "qcom,mdss"; 1475 reg = <0x0c900000 0x1000>, 1476 <0x0c9b0000 0x1040>; 1477 reg-names = "mdss_phys", "vbif_phys"; 1478 1479 power-domains = <&mmcc MDSS_GDSC>; 1480 1481 clocks = <&mmcc MDSS_AHB_CLK>, 1482 <&mmcc MDSS_AXI_CLK>, 1483 <&mmcc MDSS_VSYNC_CLK>, 1484 <&mmcc MDSS_MDP_CLK>; 1485 clock-names = "iface", 1486 "bus", 1487 "vsync", 1488 "core"; 1489 1490 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 1491 1492 interrupt-controller; 1493 #interrupt-cells = <1>; 1494 1495 #address-cells = <1>; 1496 #size-cells = <1>; 1497 ranges; 1498 status = "disabled"; 1499 1500 mdp: mdp@c901000 { 1501 compatible = "qcom,mdp5"; 1502 reg = <0x0c901000 0x89000>; 1503 reg-names = "mdp_phys"; 1504 1505 interrupt-parent = <&mdss>; 1506 interrupts = <0>; 1507 1508 assigned-clocks = <&mmcc MDSS_MDP_CLK>, 1509 <&mmcc MDSS_VSYNC_CLK>; 1510 assigned-clock-rates = <300000000>, 1511 <19200000>; 1512 clocks = <&mmcc MDSS_AHB_CLK>, 1513 <&mmcc MDSS_AXI_CLK>, 1514 <&mmcc MDSS_MDP_CLK>, 1515 <&mmcc MDSS_VSYNC_CLK>; 1516 clock-names = "iface", 1517 "bus", 1518 "core", 1519 "vsync"; 1520 1521 interconnects = <&mnoc 2 &bimc 5>, 1522 <&mnoc 3 &bimc 5>, 1523 <&gnoc 0 &mnoc 17>; 1524 interconnect-names = "mdp0-mem", 1525 "mdp1-mem", 1526 "rotator-mem"; 1527 iommus = <&mmss_smmu 0>; 1528 operating-points-v2 = <&mdp_opp_table>; 1529 power-domains = <&rpmpd SDM660_VDDCX>; 1530 1531 ports { 1532 #address-cells = <1>; 1533 #size-cells = <0>; 1534 1535 port@0 { 1536 reg = <0>; 1537 mdp5_intf1_out: endpoint { 1538 remote-endpoint = <&dsi0_in>; 1539 }; 1540 }; 1541 }; 1542 1543 mdp_opp_table: opp-table { 1544 compatible = "operating-points-v2"; 1545 1546 opp-150000000 { 1547 opp-hz = /bits/ 64 <150000000>; 1548 opp-peak-kBps = <320000 320000 76800>; 1549 required-opps = <&rpmpd_opp_low_svs>; 1550 }; 1551 opp-275000000 { 1552 opp-hz = /bits/ 64 <275000000>; 1553 opp-peak-kBps = <6400000 6400000 160000>; 1554 required-opps = <&rpmpd_opp_svs>; 1555 }; 1556 opp-300000000 { 1557 opp-hz = /bits/ 64 <300000000>; 1558 opp-peak-kBps = <6400000 6400000 190000>; 1559 required-opps = <&rpmpd_opp_svs_plus>; 1560 }; 1561 opp-330000000 { 1562 opp-hz = /bits/ 64 <330000000>; 1563 opp-peak-kBps = <6400000 6400000 240000>; 1564 required-opps = <&rpmpd_opp_nom>; 1565 }; 1566 opp-412500000 { 1567 opp-hz = /bits/ 64 <412500000>; 1568 opp-peak-kBps = <6400000 6400000 320000>; 1569 required-opps = <&rpmpd_opp_turbo>; 1570 }; 1571 }; 1572 }; 1573 1574 dsi0: dsi@c994000 { 1575 compatible = "qcom,mdss-dsi-ctrl"; 1576 reg = <0x0c994000 0x400>; 1577 reg-names = "dsi_ctrl"; 1578 1579 operating-points-v2 = <&dsi_opp_table>; 1580 power-domains = <&rpmpd SDM660_VDDCX>; 1581 1582 interrupt-parent = <&mdss>; 1583 interrupts = <4>; 1584 1585 assigned-clocks = <&mmcc BYTE0_CLK_SRC>, 1586 <&mmcc PCLK0_CLK_SRC>; 1587 assigned-clock-parents = <&dsi0_phy 0>, 1588 <&dsi0_phy 1>; 1589 1590 clocks = <&mmcc MDSS_MDP_CLK>, 1591 <&mmcc MDSS_BYTE0_CLK>, 1592 <&mmcc MDSS_BYTE0_INTF_CLK>, 1593 <&mmcc MNOC_AHB_CLK>, 1594 <&mmcc MDSS_AHB_CLK>, 1595 <&mmcc MDSS_AXI_CLK>, 1596 <&mmcc MISC_AHB_CLK>, 1597 <&mmcc MDSS_PCLK0_CLK>, 1598 <&mmcc MDSS_ESC0_CLK>; 1599 clock-names = "mdp_core", 1600 "byte", 1601 "byte_intf", 1602 "mnoc", 1603 "iface", 1604 "bus", 1605 "core_mmss", 1606 "pixel", 1607 "core"; 1608 1609 phys = <&dsi0_phy>; 1610 1611 status = "disabled"; 1612 1613 ports { 1614 #address-cells = <1>; 1615 #size-cells = <0>; 1616 1617 port@0 { 1618 reg = <0>; 1619 dsi0_in: endpoint { 1620 remote-endpoint = <&mdp5_intf1_out>; 1621 }; 1622 }; 1623 1624 port@1 { 1625 reg = <1>; 1626 dsi0_out: endpoint { 1627 }; 1628 }; 1629 }; 1630 }; 1631 1632 dsi0_phy: phy@c994400 { 1633 compatible = "qcom,dsi-phy-14nm-660"; 1634 reg = <0x0c994400 0x100>, 1635 <0x0c994500 0x300>, 1636 <0x0c994800 0x188>; 1637 reg-names = "dsi_phy", 1638 "dsi_phy_lane", 1639 "dsi_pll"; 1640 1641 #clock-cells = <1>; 1642 #phy-cells = <0>; 1643 1644 clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>; 1645 clock-names = "iface", "ref"; 1646 status = "disabled"; 1647 }; 1648 }; 1649 1650 blsp1_dma: dma-controller@c144000 { 1651 compatible = "qcom,bam-v1.7.0"; 1652 reg = <0x0c144000 0x1f000>; 1653 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 1654 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 1655 clock-names = "bam_clk"; 1656 #dma-cells = <1>; 1657 qcom,ee = <0>; 1658 qcom,controlled-remotely; 1659 num-channels = <18>; 1660 qcom,num-ees = <4>; 1661 }; 1662 1663 blsp1_uart1: serial@c16f000 { 1664 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1665 reg = <0x0c16f000 0x200>; 1666 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1667 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, 1668 <&gcc GCC_BLSP1_AHB_CLK>; 1669 clock-names = "core", "iface"; 1670 dmas = <&blsp1_dma 0>, <&blsp1_dma 1>; 1671 dma-names = "tx", "rx"; 1672 pinctrl-names = "default", "sleep"; 1673 pinctrl-0 = <&blsp1_uart1_default>; 1674 pinctrl-1 = <&blsp1_uart1_sleep>; 1675 status = "disabled"; 1676 }; 1677 1678 blsp1_uart2: serial@c170000 { 1679 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1680 reg = <0x0c170000 0x1000>; 1681 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1682 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, 1683 <&gcc GCC_BLSP1_AHB_CLK>; 1684 clock-names = "core", "iface"; 1685 dmas = <&blsp1_dma 2>, <&blsp1_dma 3>; 1686 dma-names = "tx", "rx"; 1687 pinctrl-names = "default"; 1688 pinctrl-0 = <&blsp1_uart2_default>; 1689 status = "disabled"; 1690 }; 1691 1692 blsp_i2c1: i2c@c175000 { 1693 compatible = "qcom,i2c-qup-v2.2.1"; 1694 reg = <0x0c175000 0x600>; 1695 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1696 1697 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, 1698 <&gcc GCC_BLSP1_AHB_CLK>; 1699 clock-names = "core", "iface"; 1700 clock-frequency = <400000>; 1701 dmas = <&blsp1_dma 4>, <&blsp1_dma 5>; 1702 dma-names = "tx", "rx"; 1703 1704 pinctrl-names = "default", "sleep"; 1705 pinctrl-0 = <&i2c1_default>; 1706 pinctrl-1 = <&i2c1_sleep>; 1707 #address-cells = <1>; 1708 #size-cells = <0>; 1709 status = "disabled"; 1710 }; 1711 1712 blsp_i2c2: i2c@c176000 { 1713 compatible = "qcom,i2c-qup-v2.2.1"; 1714 reg = <0x0c176000 0x600>; 1715 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1716 1717 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 1718 <&gcc GCC_BLSP1_AHB_CLK>; 1719 clock-names = "core", "iface"; 1720 clock-frequency = <400000>; 1721 dmas = <&blsp1_dma 6>, <&blsp1_dma 7>; 1722 dma-names = "tx", "rx"; 1723 1724 pinctrl-names = "default", "sleep"; 1725 pinctrl-0 = <&i2c2_default>; 1726 pinctrl-1 = <&i2c2_sleep>; 1727 #address-cells = <1>; 1728 #size-cells = <0>; 1729 status = "disabled"; 1730 }; 1731 1732 blsp_i2c3: i2c@c177000 { 1733 compatible = "qcom,i2c-qup-v2.2.1"; 1734 reg = <0x0c177000 0x600>; 1735 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1736 1737 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 1738 <&gcc GCC_BLSP1_AHB_CLK>; 1739 clock-names = "core", "iface"; 1740 clock-frequency = <400000>; 1741 dmas = <&blsp1_dma 8>, <&blsp1_dma 9>; 1742 dma-names = "tx", "rx"; 1743 1744 pinctrl-names = "default", "sleep"; 1745 pinctrl-0 = <&i2c3_default>; 1746 pinctrl-1 = <&i2c3_sleep>; 1747 #address-cells = <1>; 1748 #size-cells = <0>; 1749 status = "disabled"; 1750 }; 1751 1752 blsp_i2c4: i2c@c178000 { 1753 compatible = "qcom,i2c-qup-v2.2.1"; 1754 reg = <0x0c178000 0x600>; 1755 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1756 1757 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, 1758 <&gcc GCC_BLSP1_AHB_CLK>; 1759 clock-names = "core", "iface"; 1760 clock-frequency = <400000>; 1761 dmas = <&blsp1_dma 10>, <&blsp1_dma 11>; 1762 dma-names = "tx", "rx"; 1763 1764 pinctrl-names = "default", "sleep"; 1765 pinctrl-0 = <&i2c4_default>; 1766 pinctrl-1 = <&i2c4_sleep>; 1767 #address-cells = <1>; 1768 #size-cells = <0>; 1769 status = "disabled"; 1770 }; 1771 1772 blsp2_dma: dma-controller@c184000 { 1773 compatible = "qcom,bam-v1.7.0"; 1774 reg = <0x0c184000 0x1f000>; 1775 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 1776 clocks = <&gcc GCC_BLSP2_AHB_CLK>; 1777 clock-names = "bam_clk"; 1778 #dma-cells = <1>; 1779 qcom,ee = <0>; 1780 qcom,controlled-remotely; 1781 num-channels = <18>; 1782 qcom,num-ees = <4>; 1783 }; 1784 1785 blsp2_uart1: serial@c1af000 { 1786 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1787 reg = <0x0c1af000 0x200>; 1788 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 1789 clocks = <&gcc GCC_BLSP2_UART1_APPS_CLK>, 1790 <&gcc GCC_BLSP2_AHB_CLK>; 1791 clock-names = "core", "iface"; 1792 dmas = <&blsp2_dma 0>, <&blsp2_dma 1>; 1793 dma-names = "tx", "rx"; 1794 pinctrl-names = "default", "sleep"; 1795 pinctrl-0 = <&blsp2_uart1_default>; 1796 pinctrl-1 = <&blsp2_uart1_sleep>; 1797 status = "disabled"; 1798 }; 1799 1800 blsp_i2c5: i2c@c1b5000 { 1801 compatible = "qcom,i2c-qup-v2.2.1"; 1802 reg = <0x0c1b5000 0x600>; 1803 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 1804 1805 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, 1806 <&gcc GCC_BLSP2_AHB_CLK>; 1807 clock-names = "core", "iface"; 1808 clock-frequency = <400000>; 1809 dmas = <&blsp2_dma 4>, <&blsp2_dma 5>; 1810 dma-names = "tx", "rx"; 1811 1812 pinctrl-names = "default", "sleep"; 1813 pinctrl-0 = <&i2c5_default>; 1814 pinctrl-1 = <&i2c5_sleep>; 1815 #address-cells = <1>; 1816 #size-cells = <0>; 1817 status = "disabled"; 1818 }; 1819 1820 blsp_i2c6: i2c@c1b6000 { 1821 compatible = "qcom,i2c-qup-v2.2.1"; 1822 reg = <0x0c1b6000 0x600>; 1823 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 1824 1825 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, 1826 <&gcc GCC_BLSP2_AHB_CLK>; 1827 clock-names = "core", "iface"; 1828 clock-frequency = <400000>; 1829 dmas = <&blsp2_dma 6>, <&blsp2_dma 7>; 1830 dma-names = "tx", "rx"; 1831 1832 pinctrl-names = "default", "sleep"; 1833 pinctrl-0 = <&i2c6_default>; 1834 pinctrl-1 = <&i2c6_sleep>; 1835 #address-cells = <1>; 1836 #size-cells = <0>; 1837 status = "disabled"; 1838 }; 1839 1840 blsp_i2c7: i2c@c1b7000 { 1841 compatible = "qcom,i2c-qup-v2.2.1"; 1842 reg = <0x0c1b7000 0x600>; 1843 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 1844 1845 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>, 1846 <&gcc GCC_BLSP2_AHB_CLK>; 1847 clock-names = "core", "iface"; 1848 clock-frequency = <400000>; 1849 dmas = <&blsp2_dma 8>, <&blsp2_dma 9>; 1850 dma-names = "tx", "rx"; 1851 1852 pinctrl-names = "default", "sleep"; 1853 pinctrl-0 = <&i2c7_default>; 1854 pinctrl-1 = <&i2c7_sleep>; 1855 #address-cells = <1>; 1856 #size-cells = <0>; 1857 status = "disabled"; 1858 }; 1859 1860 blsp_i2c8: i2c@c1b8000 { 1861 compatible = "qcom,i2c-qup-v2.2.1"; 1862 reg = <0x0c1b8000 0x600>; 1863 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 1864 1865 clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>, 1866 <&gcc GCC_BLSP2_AHB_CLK>; 1867 clock-names = "core", "iface"; 1868 clock-frequency = <400000>; 1869 dmas = <&blsp2_dma 10>, <&blsp2_dma 11>; 1870 dma-names = "tx", "rx"; 1871 1872 pinctrl-names = "default", "sleep"; 1873 pinctrl-0 = <&i2c8_default>; 1874 pinctrl-1 = <&i2c8_sleep>; 1875 #address-cells = <1>; 1876 #size-cells = <0>; 1877 status = "disabled"; 1878 }; 1879 1880 sram@146bf000 { 1881 compatible = "qcom,sdm630-imem", "syscon", "simple-mfd"; 1882 reg = <0x146bf000 0x1000>; 1883 1884 #address-cells = <1>; 1885 #size-cells = <1>; 1886 1887 ranges = <0 0x146bf000 0x1000>; 1888 1889 pil-reloc@94c { 1890 compatible = "qcom,pil-reloc-info"; 1891 reg = <0x94c 0xc8>; 1892 }; 1893 }; 1894 1895 camss: camss@ca00000 { 1896 compatible = "qcom,sdm660-camss"; 1897 reg = <0x0ca00020 0x10>, 1898 <0x0ca30000 0x100>, 1899 <0x0ca30400 0x100>, 1900 <0x0ca30800 0x100>, 1901 <0x0ca30c00 0x100>, 1902 <0x0c824000 0x1000>, 1903 <0x0ca00120 0x4>, 1904 <0x0c825000 0x1000>, 1905 <0x0ca00124 0x4>, 1906 <0x0c826000 0x1000>, 1907 <0x0ca00128 0x4>, 1908 <0x0ca31000 0x500>, 1909 <0x0ca10000 0x1000>, 1910 <0x0ca14000 0x1000>; 1911 reg-names = "csi_clk_mux", 1912 "csid0", 1913 "csid1", 1914 "csid2", 1915 "csid3", 1916 "csiphy0", 1917 "csiphy0_clk_mux", 1918 "csiphy1", 1919 "csiphy1_clk_mux", 1920 "csiphy2", 1921 "csiphy2_clk_mux", 1922 "ispif", 1923 "vfe0", 1924 "vfe1"; 1925 interrupts = <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>, 1926 <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>, 1927 <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>, 1928 <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>, 1929 <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>, 1930 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>, 1931 <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>, 1932 <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>, 1933 <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>, 1934 <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>; 1935 interrupt-names = "csid0", 1936 "csid1", 1937 "csid2", 1938 "csid3", 1939 "csiphy0", 1940 "csiphy1", 1941 "csiphy2", 1942 "ispif", 1943 "vfe0", 1944 "vfe1"; 1945 clocks = <&mmcc CAMSS_AHB_CLK>, 1946 <&mmcc CAMSS_CPHY_CSID0_CLK>, 1947 <&mmcc CAMSS_CPHY_CSID1_CLK>, 1948 <&mmcc CAMSS_CPHY_CSID2_CLK>, 1949 <&mmcc CAMSS_CPHY_CSID3_CLK>, 1950 <&mmcc CAMSS_CSI0_AHB_CLK>, 1951 <&mmcc CAMSS_CSI0_CLK>, 1952 <&mmcc CAMSS_CPHY_CSID0_CLK>, 1953 <&mmcc CAMSS_CSI0PIX_CLK>, 1954 <&mmcc CAMSS_CSI0RDI_CLK>, 1955 <&mmcc CAMSS_CSI1_AHB_CLK>, 1956 <&mmcc CAMSS_CSI1_CLK>, 1957 <&mmcc CAMSS_CPHY_CSID1_CLK>, 1958 <&mmcc CAMSS_CSI1PIX_CLK>, 1959 <&mmcc CAMSS_CSI1RDI_CLK>, 1960 <&mmcc CAMSS_CSI2_AHB_CLK>, 1961 <&mmcc CAMSS_CSI2_CLK>, 1962 <&mmcc CAMSS_CPHY_CSID2_CLK>, 1963 <&mmcc CAMSS_CSI2PIX_CLK>, 1964 <&mmcc CAMSS_CSI2RDI_CLK>, 1965 <&mmcc CAMSS_CSI3_AHB_CLK>, 1966 <&mmcc CAMSS_CSI3_CLK>, 1967 <&mmcc CAMSS_CPHY_CSID3_CLK>, 1968 <&mmcc CAMSS_CSI3PIX_CLK>, 1969 <&mmcc CAMSS_CSI3RDI_CLK>, 1970 <&mmcc CAMSS_CSI0PHYTIMER_CLK>, 1971 <&mmcc CAMSS_CSI1PHYTIMER_CLK>, 1972 <&mmcc CAMSS_CSI2PHYTIMER_CLK>, 1973 <&mmcc CSIPHY_AHB2CRIF_CLK>, 1974 <&mmcc CAMSS_CSI_VFE0_CLK>, 1975 <&mmcc CAMSS_CSI_VFE1_CLK>, 1976 <&mmcc CAMSS_ISPIF_AHB_CLK>, 1977 <&mmcc THROTTLE_CAMSS_AXI_CLK>, 1978 <&mmcc CAMSS_TOP_AHB_CLK>, 1979 <&mmcc CAMSS_VFE0_AHB_CLK>, 1980 <&mmcc CAMSS_VFE0_CLK>, 1981 <&mmcc CAMSS_VFE0_STREAM_CLK>, 1982 <&mmcc CAMSS_VFE1_AHB_CLK>, 1983 <&mmcc CAMSS_VFE1_CLK>, 1984 <&mmcc CAMSS_VFE1_STREAM_CLK>, 1985 <&mmcc CAMSS_VFE_VBIF_AHB_CLK>, 1986 <&mmcc CAMSS_VFE_VBIF_AXI_CLK>; 1987 clock-names = "ahb", 1988 "cphy_csid0", 1989 "cphy_csid1", 1990 "cphy_csid2", 1991 "cphy_csid3", 1992 "csi0_ahb", 1993 "csi0", 1994 "csi0_phy", 1995 "csi0_pix", 1996 "csi0_rdi", 1997 "csi1_ahb", 1998 "csi1", 1999 "csi1_phy", 2000 "csi1_pix", 2001 "csi1_rdi", 2002 "csi2_ahb", 2003 "csi2", 2004 "csi2_phy", 2005 "csi2_pix", 2006 "csi2_rdi", 2007 "csi3_ahb", 2008 "csi3", 2009 "csi3_phy", 2010 "csi3_pix", 2011 "csi3_rdi", 2012 "csiphy0_timer", 2013 "csiphy1_timer", 2014 "csiphy2_timer", 2015 "csiphy_ahb2crif", 2016 "csi_vfe0", 2017 "csi_vfe1", 2018 "ispif_ahb", 2019 "throttle_axi", 2020 "top_ahb", 2021 "vfe0_ahb", 2022 "vfe0", 2023 "vfe0_stream", 2024 "vfe1_ahb", 2025 "vfe1", 2026 "vfe1_stream", 2027 "vfe_ahb", 2028 "vfe_axi"; 2029 interconnects = <&mnoc 5 &bimc 5>; 2030 interconnect-names = "vfe-mem"; 2031 iommus = <&mmss_smmu 0xc00>, 2032 <&mmss_smmu 0xc01>, 2033 <&mmss_smmu 0xc02>, 2034 <&mmss_smmu 0xc03>; 2035 power-domains = <&mmcc CAMSS_VFE0_GDSC>, 2036 <&mmcc CAMSS_VFE1_GDSC>; 2037 status = "disabled"; 2038 2039 ports { 2040 #address-cells = <1>; 2041 #size-cells = <0>; 2042 }; 2043 }; 2044 2045 cci: cci@ca0c000 { 2046 compatible = "qcom,msm8996-cci"; 2047 #address-cells = <1>; 2048 #size-cells = <0>; 2049 reg = <0x0ca0c000 0x1000>; 2050 interrupts = <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>; 2051 2052 assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>, 2053 <&mmcc CAMSS_CCI_CLK>; 2054 assigned-clock-rates = <80800000>, <37500000>; 2055 clocks = <&mmcc CAMSS_TOP_AHB_CLK>, 2056 <&mmcc CAMSS_CCI_AHB_CLK>, 2057 <&mmcc CAMSS_CCI_CLK>, 2058 <&mmcc CAMSS_AHB_CLK>; 2059 clock-names = "camss_top_ahb", 2060 "cci_ahb", 2061 "cci", 2062 "camss_ahb"; 2063 2064 pinctrl-names = "default"; 2065 pinctrl-0 = <&cci0_default &cci1_default>; 2066 power-domains = <&mmcc CAMSS_TOP_GDSC>; 2067 status = "disabled"; 2068 2069 cci_i2c0: i2c-bus@0 { 2070 reg = <0>; 2071 clock-frequency = <400000>; 2072 #address-cells = <1>; 2073 #size-cells = <0>; 2074 }; 2075 2076 cci_i2c1: i2c-bus@1 { 2077 reg = <1>; 2078 clock-frequency = <400000>; 2079 #address-cells = <1>; 2080 #size-cells = <0>; 2081 }; 2082 }; 2083 2084 venus: video-codec@cc00000 { 2085 compatible = "qcom,sdm660-venus"; 2086 reg = <0x0cc00000 0xff000>; 2087 clocks = <&mmcc VIDEO_CORE_CLK>, 2088 <&mmcc VIDEO_AHB_CLK>, 2089 <&mmcc VIDEO_AXI_CLK>, 2090 <&mmcc THROTTLE_VIDEO_AXI_CLK>; 2091 clock-names = "core", "iface", "bus", "bus_throttle"; 2092 interconnects = <&gnoc 0 &mnoc 13>, 2093 <&mnoc 4 &bimc 5>; 2094 interconnect-names = "cpu-cfg", "video-mem"; 2095 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 2096 iommus = <&mmss_smmu 0x400>, 2097 <&mmss_smmu 0x401>, 2098 <&mmss_smmu 0x40a>, 2099 <&mmss_smmu 0x407>, 2100 <&mmss_smmu 0x40e>, 2101 <&mmss_smmu 0x40f>, 2102 <&mmss_smmu 0x408>, 2103 <&mmss_smmu 0x409>, 2104 <&mmss_smmu 0x40b>, 2105 <&mmss_smmu 0x40c>, 2106 <&mmss_smmu 0x40d>, 2107 <&mmss_smmu 0x410>, 2108 <&mmss_smmu 0x421>, 2109 <&mmss_smmu 0x428>, 2110 <&mmss_smmu 0x429>, 2111 <&mmss_smmu 0x42b>, 2112 <&mmss_smmu 0x42c>, 2113 <&mmss_smmu 0x42d>, 2114 <&mmss_smmu 0x411>, 2115 <&mmss_smmu 0x431>; 2116 memory-region = <&venus_region>; 2117 power-domains = <&mmcc VENUS_GDSC>; 2118 status = "disabled"; 2119 2120 video-decoder { 2121 compatible = "venus-decoder"; 2122 clocks = <&mmcc VIDEO_SUBCORE0_CLK>; 2123 clock-names = "vcodec0_core"; 2124 power-domains = <&mmcc VENUS_CORE0_GDSC>; 2125 }; 2126 2127 video-encoder { 2128 compatible = "venus-encoder"; 2129 clocks = <&mmcc VIDEO_SUBCORE0_CLK>; 2130 clock-names = "vcodec0_core"; 2131 power-domains = <&mmcc VENUS_CORE0_GDSC>; 2132 }; 2133 }; 2134 2135 mmss_smmu: iommu@cd00000 { 2136 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2"; 2137 reg = <0x0cd00000 0x40000>; 2138 2139 clocks = <&mmcc MNOC_AHB_CLK>, 2140 <&mmcc BIMC_SMMU_AHB_CLK>, 2141 <&rpmcc RPM_SMD_MMSSNOC_AXI_CLK>, 2142 <&mmcc BIMC_SMMU_AXI_CLK>; 2143 clock-names = "iface-mm", "iface-smmu", 2144 "bus-mm", "bus-smmu"; 2145 #global-interrupts = <2>; 2146 #iommu-cells = <1>; 2147 2148 interrupts = 2149 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 2150 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 2151 2152 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 2153 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 2154 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, 2155 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 2156 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 2157 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 2158 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 2159 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 2160 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 2161 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 2162 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 2163 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 2164 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 2165 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 2166 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 2167 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 2168 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 2169 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 2170 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 2171 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, 2172 <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, 2173 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 2174 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 2175 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>; 2176 2177 status = "disabled"; 2178 }; 2179 2180 adsp_pil: remoteproc@15700000 { 2181 compatible = "qcom,sdm660-adsp-pas"; 2182 reg = <0x15700000 0x4040>; 2183 2184 interrupts-extended = 2185 <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 2186 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2187 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2188 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2189 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2190 interrupt-names = "wdog", "fatal", "ready", 2191 "handover", "stop-ack"; 2192 2193 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 2194 clock-names = "xo"; 2195 2196 memory-region = <&adsp_region>; 2197 power-domains = <&rpmpd SDM660_VDDCX>; 2198 power-domain-names = "cx"; 2199 2200 qcom,smem-states = <&adsp_smp2p_out 0>; 2201 qcom,smem-state-names = "stop"; 2202 2203 glink-edge { 2204 interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>; 2205 2206 label = "lpass"; 2207 mboxes = <&apcs_glb 9>; 2208 qcom,remote-pid = <2>; 2209 2210 apr { 2211 compatible = "qcom,apr-v2"; 2212 qcom,glink-channels = "apr_audio_svc"; 2213 qcom,domain = <APR_DOMAIN_ADSP>; 2214 #address-cells = <1>; 2215 #size-cells = <0>; 2216 2217 service@3 { 2218 reg = <APR_SVC_ADSP_CORE>; 2219 compatible = "qcom,q6core"; 2220 }; 2221 2222 q6afe: service@4 { 2223 compatible = "qcom,q6afe"; 2224 reg = <APR_SVC_AFE>; 2225 q6afedai: dais { 2226 compatible = "qcom,q6afe-dais"; 2227 #address-cells = <1>; 2228 #size-cells = <0>; 2229 #sound-dai-cells = <1>; 2230 }; 2231 }; 2232 2233 q6asm: service@7 { 2234 compatible = "qcom,q6asm"; 2235 reg = <APR_SVC_ASM>; 2236 q6asmdai: dais { 2237 compatible = "qcom,q6asm-dais"; 2238 #address-cells = <1>; 2239 #size-cells = <0>; 2240 #sound-dai-cells = <1>; 2241 iommus = <&lpass_smmu 1>; 2242 }; 2243 }; 2244 2245 q6adm: service@8 { 2246 compatible = "qcom,q6adm"; 2247 reg = <APR_SVC_ADM>; 2248 q6routing: routing { 2249 compatible = "qcom,q6adm-routing"; 2250 #sound-dai-cells = <0>; 2251 }; 2252 }; 2253 }; 2254 }; 2255 }; 2256 2257 gnoc: interconnect@17900000 { 2258 compatible = "qcom,sdm660-gnoc"; 2259 reg = <0x17900000 0xe000>; 2260 #interconnect-cells = <1>; 2261 /* 2262 * This one apparently features no clocks, 2263 * so let's not mess with the driver needlessly 2264 */ 2265 clock-names = "bus", "bus_a"; 2266 clocks = <&xo_board>, <&xo_board>; 2267 }; 2268 2269 apcs_glb: mailbox@17911000 { 2270 compatible = "qcom,sdm660-apcs-hmss-global"; 2271 reg = <0x17911000 0x1000>; 2272 2273 #mbox-cells = <1>; 2274 }; 2275 2276 timer@17920000 { 2277 #address-cells = <1>; 2278 #size-cells = <1>; 2279 ranges; 2280 compatible = "arm,armv7-timer-mem"; 2281 reg = <0x17920000 0x1000>; 2282 clock-frequency = <19200000>; 2283 2284 frame@17921000 { 2285 frame-number = <0>; 2286 interrupts = <0 8 0x4>, 2287 <0 7 0x4>; 2288 reg = <0x17921000 0x1000>, 2289 <0x17922000 0x1000>; 2290 }; 2291 2292 frame@17923000 { 2293 frame-number = <1>; 2294 interrupts = <0 9 0x4>; 2295 reg = <0x17923000 0x1000>; 2296 status = "disabled"; 2297 }; 2298 2299 frame@17924000 { 2300 frame-number = <2>; 2301 interrupts = <0 10 0x4>; 2302 reg = <0x17924000 0x1000>; 2303 status = "disabled"; 2304 }; 2305 2306 frame@17925000 { 2307 frame-number = <3>; 2308 interrupts = <0 11 0x4>; 2309 reg = <0x17925000 0x1000>; 2310 status = "disabled"; 2311 }; 2312 2313 frame@17926000 { 2314 frame-number = <4>; 2315 interrupts = <0 12 0x4>; 2316 reg = <0x17926000 0x1000>; 2317 status = "disabled"; 2318 }; 2319 2320 frame@17927000 { 2321 frame-number = <5>; 2322 interrupts = <0 13 0x4>; 2323 reg = <0x17927000 0x1000>; 2324 status = "disabled"; 2325 }; 2326 2327 frame@17928000 { 2328 frame-number = <6>; 2329 interrupts = <0 14 0x4>; 2330 reg = <0x17928000 0x1000>; 2331 status = "disabled"; 2332 }; 2333 }; 2334 2335 intc: interrupt-controller@17a00000 { 2336 compatible = "arm,gic-v3"; 2337 reg = <0x17a00000 0x10000>, /* GICD */ 2338 <0x17b00000 0x100000>; /* GICR * 8 */ 2339 #interrupt-cells = <3>; 2340 #address-cells = <1>; 2341 #size-cells = <1>; 2342 ranges; 2343 interrupt-controller; 2344 #redistributor-regions = <1>; 2345 redistributor-stride = <0x0 0x20000>; 2346 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 2347 }; 2348 }; 2349 2350 sound: sound { 2351 }; 2352 2353 thermal-zones { 2354 aoss-thermal { 2355 polling-delay-passive = <250>; 2356 polling-delay = <1000>; 2357 2358 thermal-sensors = <&tsens 0>; 2359 2360 trips { 2361 aoss_alert0: trip-point0 { 2362 temperature = <105000>; 2363 hysteresis = <1000>; 2364 type = "hot"; 2365 }; 2366 }; 2367 }; 2368 2369 cpuss0-thermal { 2370 polling-delay-passive = <250>; 2371 polling-delay = <1000>; 2372 2373 thermal-sensors = <&tsens 1>; 2374 2375 trips { 2376 cpuss0_alert0: trip-point0 { 2377 temperature = <125000>; 2378 hysteresis = <1000>; 2379 type = "hot"; 2380 }; 2381 }; 2382 }; 2383 2384 cpuss1-thermal { 2385 polling-delay-passive = <250>; 2386 polling-delay = <1000>; 2387 2388 thermal-sensors = <&tsens 2>; 2389 2390 trips { 2391 cpuss1_alert0: trip-point0 { 2392 temperature = <125000>; 2393 hysteresis = <1000>; 2394 type = "hot"; 2395 }; 2396 }; 2397 }; 2398 2399 cpu0-thermal { 2400 polling-delay-passive = <250>; 2401 polling-delay = <1000>; 2402 2403 thermal-sensors = <&tsens 3>; 2404 2405 trips { 2406 cpu0_alert0: trip-point0 { 2407 temperature = <70000>; 2408 hysteresis = <1000>; 2409 type = "passive"; 2410 }; 2411 2412 cpu0_crit: cpu_crit { 2413 temperature = <110000>; 2414 hysteresis = <1000>; 2415 type = "critical"; 2416 }; 2417 }; 2418 }; 2419 2420 cpu1-thermal { 2421 polling-delay-passive = <250>; 2422 polling-delay = <1000>; 2423 2424 thermal-sensors = <&tsens 4>; 2425 2426 trips { 2427 cpu1_alert0: trip-point0 { 2428 temperature = <70000>; 2429 hysteresis = <1000>; 2430 type = "passive"; 2431 }; 2432 2433 cpu1_crit: cpu_crit { 2434 temperature = <110000>; 2435 hysteresis = <1000>; 2436 type = "critical"; 2437 }; 2438 }; 2439 }; 2440 2441 cpu2-thermal { 2442 polling-delay-passive = <250>; 2443 polling-delay = <1000>; 2444 2445 thermal-sensors = <&tsens 5>; 2446 2447 trips { 2448 cpu2_alert0: trip-point0 { 2449 temperature = <70000>; 2450 hysteresis = <1000>; 2451 type = "passive"; 2452 }; 2453 2454 cpu2_crit: cpu_crit { 2455 temperature = <110000>; 2456 hysteresis = <1000>; 2457 type = "critical"; 2458 }; 2459 }; 2460 }; 2461 2462 cpu3-thermal { 2463 polling-delay-passive = <250>; 2464 polling-delay = <1000>; 2465 2466 thermal-sensors = <&tsens 6>; 2467 2468 trips { 2469 cpu3_alert0: trip-point0 { 2470 temperature = <70000>; 2471 hysteresis = <1000>; 2472 type = "passive"; 2473 }; 2474 2475 cpu3_crit: cpu_crit { 2476 temperature = <110000>; 2477 hysteresis = <1000>; 2478 type = "critical"; 2479 }; 2480 }; 2481 }; 2482 2483 /* 2484 * According to what downstream DTS says, 2485 * the entire power efficient cluster has 2486 * only a single thermal sensor. 2487 */ 2488 2489 pwr-cluster-thermal { 2490 polling-delay-passive = <250>; 2491 polling-delay = <1000>; 2492 2493 thermal-sensors = <&tsens 7>; 2494 2495 trips { 2496 pwr_cluster_alert0: trip-point0 { 2497 temperature = <70000>; 2498 hysteresis = <1000>; 2499 type = "passive"; 2500 }; 2501 2502 pwr_cluster_crit: cpu_crit { 2503 temperature = <110000>; 2504 hysteresis = <1000>; 2505 type = "critical"; 2506 }; 2507 }; 2508 }; 2509 2510 gpu-thermal { 2511 polling-delay-passive = <250>; 2512 polling-delay = <1000>; 2513 2514 thermal-sensors = <&tsens 8>; 2515 2516 trips { 2517 gpu_alert0: trip-point0 { 2518 temperature = <90000>; 2519 hysteresis = <1000>; 2520 type = "hot"; 2521 }; 2522 }; 2523 }; 2524 }; 2525 2526 timer { 2527 compatible = "arm,armv8-timer"; 2528 interrupts = <GIC_PPI 1 0xf08>, 2529 <GIC_PPI 2 0xf08>, 2530 <GIC_PPI 3 0xf08>, 2531 <GIC_PPI 0 0xf08>; 2532 }; 2533}; 2534 2535