1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2020, Konrad Dybcio <konradybcio@gmail.com> 4 * Copyright (c) 2020, AngeloGioacchino Del Regno <kholk11@gmail.com> 5 */ 6 7#include <dt-bindings/clock/qcom,gcc-sdm660.h> 8#include <dt-bindings/clock/qcom,gpucc-sdm660.h> 9#include <dt-bindings/clock/qcom,mmcc-sdm660.h> 10#include <dt-bindings/clock/qcom,rpmcc.h> 11#include <dt-bindings/interconnect/qcom,sdm660.h> 12#include <dt-bindings/power/qcom-rpmpd.h> 13#include <dt-bindings/gpio/gpio.h> 14#include <dt-bindings/interrupt-controller/arm-gic.h> 15#include <dt-bindings/soc/qcom,apr.h> 16 17/ { 18 interrupt-parent = <&intc>; 19 20 #address-cells = <2>; 21 #size-cells = <2>; 22 23 aliases { 24 mmc1 = &sdhc_1; 25 mmc2 = &sdhc_2; 26 }; 27 28 chosen { }; 29 30 clocks { 31 xo_board: xo-board { 32 compatible = "fixed-clock"; 33 #clock-cells = <0>; 34 clock-frequency = <19200000>; 35 clock-output-names = "xo_board"; 36 }; 37 38 sleep_clk: sleep-clk { 39 compatible = "fixed-clock"; 40 #clock-cells = <0>; 41 clock-frequency = <32764>; 42 clock-output-names = "sleep_clk"; 43 }; 44 }; 45 46 cpus { 47 #address-cells = <2>; 48 #size-cells = <0>; 49 50 CPU0: cpu@100 { 51 device_type = "cpu"; 52 compatible = "arm,cortex-a53"; 53 reg = <0x0 0x100>; 54 enable-method = "psci"; 55 cpu-idle-states = <&PERF_CPU_SLEEP_0 56 &PERF_CPU_SLEEP_1 57 &PERF_CLUSTER_SLEEP_0 58 &PERF_CLUSTER_SLEEP_1 59 &PERF_CLUSTER_SLEEP_2>; 60 capacity-dmips-mhz = <1126>; 61 #cooling-cells = <2>; 62 next-level-cache = <&L2_1>; 63 L2_1: l2-cache { 64 compatible = "cache"; 65 cache-level = <2>; 66 }; 67 }; 68 69 CPU1: cpu@101 { 70 device_type = "cpu"; 71 compatible = "arm,cortex-a53"; 72 reg = <0x0 0x101>; 73 enable-method = "psci"; 74 cpu-idle-states = <&PERF_CPU_SLEEP_0 75 &PERF_CPU_SLEEP_1 76 &PERF_CLUSTER_SLEEP_0 77 &PERF_CLUSTER_SLEEP_1 78 &PERF_CLUSTER_SLEEP_2>; 79 capacity-dmips-mhz = <1126>; 80 #cooling-cells = <2>; 81 next-level-cache = <&L2_1>; 82 }; 83 84 CPU2: cpu@102 { 85 device_type = "cpu"; 86 compatible = "arm,cortex-a53"; 87 reg = <0x0 0x102>; 88 enable-method = "psci"; 89 cpu-idle-states = <&PERF_CPU_SLEEP_0 90 &PERF_CPU_SLEEP_1 91 &PERF_CLUSTER_SLEEP_0 92 &PERF_CLUSTER_SLEEP_1 93 &PERF_CLUSTER_SLEEP_2>; 94 capacity-dmips-mhz = <1126>; 95 #cooling-cells = <2>; 96 next-level-cache = <&L2_1>; 97 }; 98 99 CPU3: cpu@103 { 100 device_type = "cpu"; 101 compatible = "arm,cortex-a53"; 102 reg = <0x0 0x103>; 103 enable-method = "psci"; 104 cpu-idle-states = <&PERF_CPU_SLEEP_0 105 &PERF_CPU_SLEEP_1 106 &PERF_CLUSTER_SLEEP_0 107 &PERF_CLUSTER_SLEEP_1 108 &PERF_CLUSTER_SLEEP_2>; 109 capacity-dmips-mhz = <1126>; 110 #cooling-cells = <2>; 111 next-level-cache = <&L2_1>; 112 }; 113 114 CPU4: cpu@0 { 115 device_type = "cpu"; 116 compatible = "arm,cortex-a53"; 117 reg = <0x0 0x0>; 118 enable-method = "psci"; 119 cpu-idle-states = <&PWR_CPU_SLEEP_0 120 &PWR_CPU_SLEEP_1 121 &PWR_CLUSTER_SLEEP_0 122 &PWR_CLUSTER_SLEEP_1 123 &PWR_CLUSTER_SLEEP_2>; 124 capacity-dmips-mhz = <1024>; 125 #cooling-cells = <2>; 126 next-level-cache = <&L2_0>; 127 L2_0: l2-cache { 128 compatible = "cache"; 129 cache-level = <2>; 130 }; 131 }; 132 133 CPU5: cpu@1 { 134 device_type = "cpu"; 135 compatible = "arm,cortex-a53"; 136 reg = <0x0 0x1>; 137 enable-method = "psci"; 138 cpu-idle-states = <&PWR_CPU_SLEEP_0 139 &PWR_CPU_SLEEP_1 140 &PWR_CLUSTER_SLEEP_0 141 &PWR_CLUSTER_SLEEP_1 142 &PWR_CLUSTER_SLEEP_2>; 143 capacity-dmips-mhz = <1024>; 144 #cooling-cells = <2>; 145 next-level-cache = <&L2_0>; 146 }; 147 148 CPU6: cpu@2 { 149 device_type = "cpu"; 150 compatible = "arm,cortex-a53"; 151 reg = <0x0 0x2>; 152 enable-method = "psci"; 153 cpu-idle-states = <&PWR_CPU_SLEEP_0 154 &PWR_CPU_SLEEP_1 155 &PWR_CLUSTER_SLEEP_0 156 &PWR_CLUSTER_SLEEP_1 157 &PWR_CLUSTER_SLEEP_2>; 158 capacity-dmips-mhz = <1024>; 159 #cooling-cells = <2>; 160 next-level-cache = <&L2_0>; 161 }; 162 163 CPU7: cpu@3 { 164 device_type = "cpu"; 165 compatible = "arm,cortex-a53"; 166 reg = <0x0 0x3>; 167 enable-method = "psci"; 168 cpu-idle-states = <&PWR_CPU_SLEEP_0 169 &PWR_CPU_SLEEP_1 170 &PWR_CLUSTER_SLEEP_0 171 &PWR_CLUSTER_SLEEP_1 172 &PWR_CLUSTER_SLEEP_2>; 173 capacity-dmips-mhz = <1024>; 174 #cooling-cells = <2>; 175 next-level-cache = <&L2_0>; 176 }; 177 178 cpu-map { 179 cluster0 { 180 core0 { 181 cpu = <&CPU4>; 182 }; 183 184 core1 { 185 cpu = <&CPU5>; 186 }; 187 188 core2 { 189 cpu = <&CPU6>; 190 }; 191 192 core3 { 193 cpu = <&CPU7>; 194 }; 195 }; 196 197 cluster1 { 198 core0 { 199 cpu = <&CPU0>; 200 }; 201 202 core1 { 203 cpu = <&CPU1>; 204 }; 205 206 core2 { 207 cpu = <&CPU2>; 208 }; 209 210 core3 { 211 cpu = <&CPU3>; 212 }; 213 }; 214 }; 215 216 idle-states { 217 entry-method = "psci"; 218 219 PWR_CPU_SLEEP_0: cpu-sleep-0-0 { 220 compatible = "arm,idle-state"; 221 idle-state-name = "pwr-retention"; 222 arm,psci-suspend-param = <0x40000002>; 223 entry-latency-us = <338>; 224 exit-latency-us = <423>; 225 min-residency-us = <200>; 226 }; 227 228 PWR_CPU_SLEEP_1: cpu-sleep-0-1 { 229 compatible = "arm,idle-state"; 230 idle-state-name = "pwr-power-collapse"; 231 arm,psci-suspend-param = <0x40000003>; 232 entry-latency-us = <515>; 233 exit-latency-us = <1821>; 234 min-residency-us = <1000>; 235 local-timer-stop; 236 }; 237 238 PERF_CPU_SLEEP_0: cpu-sleep-1-0 { 239 compatible = "arm,idle-state"; 240 idle-state-name = "perf-retention"; 241 arm,psci-suspend-param = <0x40000002>; 242 entry-latency-us = <154>; 243 exit-latency-us = <87>; 244 min-residency-us = <200>; 245 }; 246 247 PERF_CPU_SLEEP_1: cpu-sleep-1-1 { 248 compatible = "arm,idle-state"; 249 idle-state-name = "perf-power-collapse"; 250 arm,psci-suspend-param = <0x40000003>; 251 entry-latency-us = <262>; 252 exit-latency-us = <301>; 253 min-residency-us = <1000>; 254 local-timer-stop; 255 }; 256 257 PWR_CLUSTER_SLEEP_0: cluster-sleep-0-0 { 258 compatible = "arm,idle-state"; 259 idle-state-name = "pwr-cluster-dynamic-retention"; 260 arm,psci-suspend-param = <0x400000F2>; 261 entry-latency-us = <284>; 262 exit-latency-us = <384>; 263 min-residency-us = <9987>; 264 local-timer-stop; 265 }; 266 267 PWR_CLUSTER_SLEEP_1: cluster-sleep-0-1 { 268 compatible = "arm,idle-state"; 269 idle-state-name = "pwr-cluster-retention"; 270 arm,psci-suspend-param = <0x400000F3>; 271 entry-latency-us = <338>; 272 exit-latency-us = <423>; 273 min-residency-us = <9987>; 274 local-timer-stop; 275 }; 276 277 PWR_CLUSTER_SLEEP_2: cluster-sleep-0-2 { 278 compatible = "arm,idle-state"; 279 idle-state-name = "pwr-cluster-retention"; 280 arm,psci-suspend-param = <0x400000F4>; 281 entry-latency-us = <515>; 282 exit-latency-us = <1821>; 283 min-residency-us = <9987>; 284 local-timer-stop; 285 }; 286 287 PERF_CLUSTER_SLEEP_0: cluster-sleep-1-0 { 288 compatible = "arm,idle-state"; 289 idle-state-name = "perf-cluster-dynamic-retention"; 290 arm,psci-suspend-param = <0x400000F2>; 291 entry-latency-us = <272>; 292 exit-latency-us = <329>; 293 min-residency-us = <9987>; 294 local-timer-stop; 295 }; 296 297 PERF_CLUSTER_SLEEP_1: cluster-sleep-1-1 { 298 compatible = "arm,idle-state"; 299 idle-state-name = "perf-cluster-retention"; 300 arm,psci-suspend-param = <0x400000F3>; 301 entry-latency-us = <332>; 302 exit-latency-us = <368>; 303 min-residency-us = <9987>; 304 local-timer-stop; 305 }; 306 307 PERF_CLUSTER_SLEEP_2: cluster-sleep-1-2 { 308 compatible = "arm,idle-state"; 309 idle-state-name = "perf-cluster-retention"; 310 arm,psci-suspend-param = <0x400000F4>; 311 entry-latency-us = <545>; 312 exit-latency-us = <1609>; 313 min-residency-us = <9987>; 314 local-timer-stop; 315 }; 316 }; 317 }; 318 319 firmware { 320 scm { 321 compatible = "qcom,scm-msm8998", "qcom,scm"; 322 }; 323 }; 324 325 memory@80000000 { 326 device_type = "memory"; 327 /* We expect the bootloader to fill in the reg */ 328 reg = <0x0 0x80000000 0x0 0x0>; 329 }; 330 331 pmu { 332 compatible = "arm,armv8-pmuv3"; 333 interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>; 334 }; 335 336 psci { 337 compatible = "arm,psci-1.0"; 338 method = "smc"; 339 }; 340 341 reserved-memory { 342 #address-cells = <2>; 343 #size-cells = <2>; 344 ranges; 345 346 wlan_msa_guard: wlan-msa-guard@85600000 { 347 reg = <0x0 0x85600000 0x0 0x100000>; 348 no-map; 349 }; 350 351 wlan_msa_mem: wlan-msa-mem@85700000 { 352 reg = <0x0 0x85700000 0x0 0x100000>; 353 no-map; 354 }; 355 356 qhee_code: qhee-code@85800000 { 357 reg = <0x0 0x85800000 0x0 0x600000>; 358 no-map; 359 }; 360 361 rmtfs_mem: memory@85e00000 { 362 compatible = "qcom,rmtfs-mem"; 363 reg = <0x0 0x85e00000 0x0 0x200000>; 364 no-map; 365 366 qcom,client-id = <1>; 367 qcom,vmid = <15>; 368 }; 369 370 smem_region: smem-mem@86000000 { 371 reg = <0 0x86000000 0 0x200000>; 372 no-map; 373 }; 374 375 tz_mem: memory@86200000 { 376 reg = <0x0 0x86200000 0x0 0x3300000>; 377 no-map; 378 }; 379 380 mpss_region: mpss@8ac00000 { 381 reg = <0x0 0x8ac00000 0x0 0x7e00000>; 382 no-map; 383 }; 384 385 adsp_region: adsp@92a00000 { 386 reg = <0x0 0x92a00000 0x0 0x1e00000>; 387 no-map; 388 }; 389 390 mba_region: mba@94800000 { 391 reg = <0x0 0x94800000 0x0 0x200000>; 392 no-map; 393 }; 394 395 buffer_mem: tzbuffer@94a00000 { 396 reg = <0x0 0x94a00000 0x0 0x100000>; 397 no-map; 398 }; 399 400 venus_region: venus@9f800000 { 401 reg = <0x0 0x9f800000 0x0 0x800000>; 402 no-map; 403 }; 404 405 adsp_mem: adsp-region@f6000000 { 406 reg = <0x0 0xf6000000 0x0 0x800000>; 407 no-map; 408 }; 409 410 qseecom_mem: qseecom-region@f6800000 { 411 reg = <0x0 0xf6800000 0x0 0x1400000>; 412 no-map; 413 }; 414 415 zap_shader_region: gpu@fed00000 { 416 compatible = "shared-dma-pool"; 417 reg = <0x0 0xfed00000 0x0 0xa00000>; 418 no-map; 419 }; 420 }; 421 422 rpm-glink { 423 compatible = "qcom,glink-rpm"; 424 425 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 426 qcom,rpm-msg-ram = <&rpm_msg_ram>; 427 mboxes = <&apcs_glb 0>; 428 429 rpm_requests: rpm-requests { 430 compatible = "qcom,rpm-sdm660"; 431 qcom,glink-channels = "rpm_requests"; 432 433 rpmcc: clock-controller { 434 compatible = "qcom,rpmcc-sdm660", "qcom,rpmcc"; 435 #clock-cells = <1>; 436 }; 437 438 rpmpd: power-controller { 439 compatible = "qcom,sdm660-rpmpd"; 440 #power-domain-cells = <1>; 441 operating-points-v2 = <&rpmpd_opp_table>; 442 443 rpmpd_opp_table: opp-table { 444 compatible = "operating-points-v2"; 445 446 rpmpd_opp_ret: opp1 { 447 opp-level = <RPM_SMD_LEVEL_RETENTION>; 448 }; 449 450 rpmpd_opp_ret_plus: opp2 { 451 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>; 452 }; 453 454 rpmpd_opp_min_svs: opp3 { 455 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 456 }; 457 458 rpmpd_opp_low_svs: opp4 { 459 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 460 }; 461 462 rpmpd_opp_svs: opp5 { 463 opp-level = <RPM_SMD_LEVEL_SVS>; 464 }; 465 466 rpmpd_opp_svs_plus: opp6 { 467 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 468 }; 469 470 rpmpd_opp_nom: opp7 { 471 opp-level = <RPM_SMD_LEVEL_NOM>; 472 }; 473 474 rpmpd_opp_nom_plus: opp8 { 475 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 476 }; 477 478 rpmpd_opp_turbo: opp9 { 479 opp-level = <RPM_SMD_LEVEL_TURBO>; 480 }; 481 }; 482 }; 483 }; 484 }; 485 486 smem: smem { 487 compatible = "qcom,smem"; 488 memory-region = <&smem_region>; 489 hwlocks = <&tcsr_mutex 3>; 490 }; 491 492 smp2p-adsp { 493 compatible = "qcom,smp2p"; 494 qcom,smem = <443>, <429>; 495 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 496 mboxes = <&apcs_glb 10>; 497 qcom,local-pid = <0>; 498 qcom,remote-pid = <2>; 499 500 adsp_smp2p_out: master-kernel { 501 qcom,entry-name = "master-kernel"; 502 #qcom,smem-state-cells = <1>; 503 }; 504 505 adsp_smp2p_in: slave-kernel { 506 qcom,entry-name = "slave-kernel"; 507 interrupt-controller; 508 #interrupt-cells = <2>; 509 }; 510 }; 511 512 smp2p-mpss { 513 compatible = "qcom,smp2p"; 514 qcom,smem = <435>, <428>; 515 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 516 mboxes = <&apcs_glb 14>; 517 qcom,local-pid = <0>; 518 qcom,remote-pid = <1>; 519 520 modem_smp2p_out: master-kernel { 521 qcom,entry-name = "master-kernel"; 522 #qcom,smem-state-cells = <1>; 523 }; 524 525 modem_smp2p_in: slave-kernel { 526 qcom,entry-name = "slave-kernel"; 527 interrupt-controller; 528 #interrupt-cells = <2>; 529 }; 530 }; 531 532 soc { 533 #address-cells = <1>; 534 #size-cells = <1>; 535 ranges = <0 0 0 0xffffffff>; 536 compatible = "simple-bus"; 537 538 gcc: clock-controller@100000 { 539 compatible = "qcom,gcc-sdm630"; 540 #clock-cells = <1>; 541 #reset-cells = <1>; 542 #power-domain-cells = <1>; 543 reg = <0x00100000 0x94000>; 544 545 clock-names = "xo", "sleep_clk"; 546 clocks = <&xo_board>, 547 <&sleep_clk>; 548 }; 549 550 rpm_msg_ram: sram@778000 { 551 compatible = "qcom,rpm-msg-ram"; 552 reg = <0x00778000 0x7000>; 553 }; 554 555 qfprom: qfprom@780000 { 556 compatible = "qcom,sdm630-qfprom", "qcom,qfprom"; 557 reg = <0x00780000 0x621c>; 558 #address-cells = <1>; 559 #size-cells = <1>; 560 561 qusb2_hstx_trim: hstx-trim@240 { 562 reg = <0x243 0x1>; 563 bits = <1 3>; 564 }; 565 566 gpu_speed_bin: gpu-speed-bin@41a0 { 567 reg = <0x41a2 0x1>; 568 bits = <5 7>; 569 }; 570 }; 571 572 rng: rng@793000 { 573 compatible = "qcom,prng-ee"; 574 reg = <0x00793000 0x1000>; 575 clocks = <&gcc GCC_PRNG_AHB_CLK>; 576 clock-names = "core"; 577 }; 578 579 bimc: interconnect@1008000 { 580 compatible = "qcom,sdm660-bimc"; 581 reg = <0x01008000 0x78000>; 582 #interconnect-cells = <1>; 583 clock-names = "bus", "bus_a"; 584 clocks = <&rpmcc RPM_SMD_BIMC_CLK>, 585 <&rpmcc RPM_SMD_BIMC_A_CLK>; 586 }; 587 588 restart@10ac000 { 589 compatible = "qcom,pshold"; 590 reg = <0x010ac000 0x4>; 591 }; 592 593 cnoc: interconnect@1500000 { 594 compatible = "qcom,sdm660-cnoc"; 595 reg = <0x01500000 0x10000>; 596 #interconnect-cells = <1>; 597 clock-names = "bus", "bus_a"; 598 clocks = <&rpmcc RPM_SMD_CNOC_CLK>, 599 <&rpmcc RPM_SMD_CNOC_A_CLK>; 600 }; 601 602 snoc: interconnect@1626000 { 603 compatible = "qcom,sdm660-snoc"; 604 reg = <0x01626000 0x7090>; 605 #interconnect-cells = <1>; 606 clock-names = "bus", "bus_a"; 607 clocks = <&rpmcc RPM_SMD_SNOC_CLK>, 608 <&rpmcc RPM_SMD_SNOC_A_CLK>; 609 }; 610 611 anoc2_smmu: iommu@16c0000 { 612 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2"; 613 reg = <0x016c0000 0x40000>; 614 615 assigned-clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>; 616 assigned-clock-rates = <1000>; 617 clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>; 618 clock-names = "bus"; 619 #global-interrupts = <2>; 620 #iommu-cells = <1>; 621 622 interrupts = 623 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 624 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 625 626 <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>, 627 <GIC_SPI 374 IRQ_TYPE_LEVEL_LOW>, 628 <GIC_SPI 375 IRQ_TYPE_LEVEL_LOW>, 629 <GIC_SPI 376 IRQ_TYPE_LEVEL_LOW>, 630 <GIC_SPI 377 IRQ_TYPE_LEVEL_LOW>, 631 <GIC_SPI 378 IRQ_TYPE_LEVEL_LOW>, 632 <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>, 633 <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>, 634 <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>, 635 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>, 636 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>, 637 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>, 638 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>, 639 <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, 640 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>, 641 <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>, 642 <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>, 643 <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, 644 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, 645 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, 646 <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>, 647 <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>, 648 <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, 649 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>, 650 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>, 651 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>, 652 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, 653 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, 654 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>; 655 656 status = "disabled"; 657 }; 658 659 a2noc: interconnect@1704000 { 660 compatible = "qcom,sdm660-a2noc"; 661 reg = <0x01704000 0xc100>; 662 #interconnect-cells = <1>; 663 clock-names = "bus", 664 "bus_a", 665 "ipa", 666 "ufs_axi", 667 "aggre2_ufs_axi", 668 "aggre2_usb3_axi", 669 "cfg_noc_usb2_axi"; 670 clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>, 671 <&rpmcc RPM_SMD_AGGR2_NOC_A_CLK>, 672 <&rpmcc RPM_SMD_IPA_CLK>, 673 <&gcc GCC_UFS_AXI_CLK>, 674 <&gcc GCC_AGGRE2_UFS_AXI_CLK>, 675 <&gcc GCC_AGGRE2_USB3_AXI_CLK>, 676 <&gcc GCC_CFG_NOC_USB2_AXI_CLK>; 677 }; 678 679 mnoc: interconnect@1745000 { 680 compatible = "qcom,sdm660-mnoc"; 681 reg = <0x01745000 0xA010>; 682 #interconnect-cells = <1>; 683 clock-names = "bus", "bus_a", "iface"; 684 clocks = <&rpmcc RPM_SMD_MMSSNOC_AXI_CLK>, 685 <&rpmcc RPM_SMD_MMSSNOC_AXI_CLK_A>, 686 <&mmcc AHB_CLK_SRC>; 687 }; 688 689 tsens: thermal-sensor@10ae000 { 690 compatible = "qcom,sdm630-tsens", "qcom,tsens-v2"; 691 reg = <0x010ae000 0x1000>, /* TM */ 692 <0x010ad000 0x1000>; /* SROT */ 693 #qcom,sensors = <12>; 694 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 695 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>; 696 interrupt-names = "uplow", "critical"; 697 #thermal-sensor-cells = <1>; 698 }; 699 700 tcsr_mutex: hwlock@1f40000 { 701 compatible = "qcom,tcsr-mutex"; 702 reg = <0x01f40000 0x20000>; 703 #hwlock-cells = <1>; 704 }; 705 706 tcsr_regs_1: syscon@1f60000 { 707 compatible = "qcom,sdm630-tcsr", "syscon"; 708 reg = <0x01f60000 0x20000>; 709 }; 710 711 tlmm: pinctrl@3100000 { 712 compatible = "qcom,sdm630-pinctrl"; 713 reg = <0x03100000 0x400000>, 714 <0x03500000 0x400000>, 715 <0x03900000 0x400000>; 716 reg-names = "south", "center", "north"; 717 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 718 gpio-controller; 719 gpio-ranges = <&tlmm 0 0 114>; 720 #gpio-cells = <2>; 721 interrupt-controller; 722 #interrupt-cells = <2>; 723 724 blsp1_uart1_default: blsp1-uart1-default { 725 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 726 drive-strength = <2>; 727 bias-disable; 728 }; 729 730 blsp1_uart1_sleep: blsp1-uart1-sleep { 731 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 732 drive-strength = <2>; 733 bias-disable; 734 }; 735 736 blsp1_uart2_default: blsp1-uart2-default { 737 pins = "gpio4", "gpio5"; 738 drive-strength = <2>; 739 bias-disable; 740 }; 741 742 blsp2_uart1_default: blsp2-uart1-active { 743 tx-rts { 744 pins = "gpio16", "gpio19"; 745 function = "blsp_uart5"; 746 drive-strength = <2>; 747 bias-disable; 748 }; 749 750 rx { 751 /* 752 * Avoid garbage data while BT module 753 * is powered off or not driving signal 754 */ 755 pins = "gpio17"; 756 function = "blsp_uart5"; 757 drive-strength = <2>; 758 bias-pull-up; 759 }; 760 761 cts { 762 /* Match the pull of the BT module */ 763 pins = "gpio18"; 764 function = "blsp_uart5"; 765 drive-strength = <2>; 766 bias-pull-down; 767 }; 768 }; 769 770 blsp2_uart1_sleep: blsp2-uart1-sleep { 771 tx { 772 pins = "gpio16"; 773 function = "gpio"; 774 drive-strength = <2>; 775 bias-pull-up; 776 }; 777 778 rx-cts-rts { 779 pins = "gpio17", "gpio18", "gpio19"; 780 function = "gpio"; 781 drive-strength = <2>; 782 bias-no-pull; 783 }; 784 }; 785 786 i2c1_default: i2c1-default { 787 pins = "gpio2", "gpio3"; 788 function = "blsp_i2c1"; 789 drive-strength = <2>; 790 bias-disable; 791 }; 792 793 i2c1_sleep: i2c1-sleep { 794 pins = "gpio2", "gpio3"; 795 function = "blsp_i2c1"; 796 drive-strength = <2>; 797 bias-pull-up; 798 }; 799 800 i2c2_default: i2c2-default { 801 pins = "gpio6", "gpio7"; 802 function = "blsp_i2c2"; 803 drive-strength = <2>; 804 bias-disable; 805 }; 806 807 i2c2_sleep: i2c2-sleep { 808 pins = "gpio6", "gpio7"; 809 function = "blsp_i2c2"; 810 drive-strength = <2>; 811 bias-pull-up; 812 }; 813 814 i2c3_default: i2c3-default { 815 pins = "gpio10", "gpio11"; 816 function = "blsp_i2c3"; 817 drive-strength = <2>; 818 bias-disable; 819 }; 820 821 i2c3_sleep: i2c3-sleep { 822 pins = "gpio10", "gpio11"; 823 function = "blsp_i2c3"; 824 drive-strength = <2>; 825 bias-pull-up; 826 }; 827 828 i2c4_default: i2c4-default { 829 pins = "gpio14", "gpio15"; 830 function = "blsp_i2c4"; 831 drive-strength = <2>; 832 bias-disable; 833 }; 834 835 i2c4_sleep: i2c4-sleep { 836 pins = "gpio14", "gpio15"; 837 function = "blsp_i2c4"; 838 drive-strength = <2>; 839 bias-pull-up; 840 }; 841 842 i2c5_default: i2c5-default { 843 pins = "gpio18", "gpio19"; 844 function = "blsp_i2c5"; 845 drive-strength = <2>; 846 bias-disable; 847 }; 848 849 i2c5_sleep: i2c5-sleep { 850 pins = "gpio18", "gpio19"; 851 function = "blsp_i2c5"; 852 drive-strength = <2>; 853 bias-pull-up; 854 }; 855 856 i2c6_default: i2c6-default { 857 pins = "gpio22", "gpio23"; 858 function = "blsp_i2c6"; 859 drive-strength = <2>; 860 bias-disable; 861 }; 862 863 i2c6_sleep: i2c6-sleep { 864 pins = "gpio22", "gpio23"; 865 function = "blsp_i2c6"; 866 drive-strength = <2>; 867 bias-pull-up; 868 }; 869 870 i2c7_default: i2c7-default { 871 pins = "gpio26", "gpio27"; 872 function = "blsp_i2c7"; 873 drive-strength = <2>; 874 bias-disable; 875 }; 876 877 i2c7_sleep: i2c7-sleep { 878 pins = "gpio26", "gpio27"; 879 function = "blsp_i2c7"; 880 drive-strength = <2>; 881 bias-pull-up; 882 }; 883 884 i2c8_default: i2c8-default { 885 pins = "gpio30", "gpio31"; 886 function = "blsp_i2c8"; 887 drive-strength = <2>; 888 bias-disable; 889 }; 890 891 i2c8_sleep: i2c8-sleep { 892 pins = "gpio30", "gpio31"; 893 function = "blsp_i2c8"; 894 drive-strength = <2>; 895 bias-pull-up; 896 }; 897 898 cci0_default: cci0_default { 899 pinmux { 900 pins = "gpio36","gpio37"; 901 function = "cci_i2c"; 902 }; 903 904 pinconf { 905 pins = "gpio36","gpio37"; 906 bias-pull-up; 907 drive-strength = <2>; 908 }; 909 }; 910 911 cci1_default: cci1_default { 912 pinmux { 913 pins = "gpio38","gpio39"; 914 function = "cci_i2c"; 915 }; 916 917 pinconf { 918 pins = "gpio38","gpio39"; 919 bias-pull-up; 920 drive-strength = <2>; 921 }; 922 }; 923 924 sdc1_state_on: sdc1-on { 925 clk { 926 pins = "sdc1_clk"; 927 bias-disable; 928 drive-strength = <16>; 929 }; 930 931 cmd { 932 pins = "sdc1_cmd"; 933 bias-pull-up; 934 drive-strength = <10>; 935 }; 936 937 data { 938 pins = "sdc1_data"; 939 bias-pull-up; 940 drive-strength = <10>; 941 }; 942 943 rclk { 944 pins = "sdc1_rclk"; 945 bias-pull-down; 946 }; 947 }; 948 949 sdc1_state_off: sdc1-off { 950 clk { 951 pins = "sdc1_clk"; 952 bias-disable; 953 drive-strength = <2>; 954 }; 955 956 cmd { 957 pins = "sdc1_cmd"; 958 bias-pull-up; 959 drive-strength = <2>; 960 }; 961 962 data { 963 pins = "sdc1_data"; 964 bias-pull-up; 965 drive-strength = <2>; 966 }; 967 968 rclk { 969 pins = "sdc1_rclk"; 970 bias-pull-down; 971 }; 972 }; 973 974 sdc2_state_on: sdc2-on { 975 clk { 976 pins = "sdc2_clk"; 977 bias-disable; 978 drive-strength = <16>; 979 }; 980 981 cmd { 982 pins = "sdc2_cmd"; 983 bias-pull-up; 984 drive-strength = <10>; 985 }; 986 987 data { 988 pins = "sdc2_data"; 989 bias-pull-up; 990 drive-strength = <10>; 991 }; 992 }; 993 994 sdc2_state_off: sdc2-off { 995 clk { 996 pins = "sdc2_clk"; 997 bias-disable; 998 drive-strength = <2>; 999 }; 1000 1001 cmd { 1002 pins = "sdc2_cmd"; 1003 bias-pull-up; 1004 drive-strength = <2>; 1005 }; 1006 1007 data { 1008 pins = "sdc2_data"; 1009 bias-pull-up; 1010 drive-strength = <2>; 1011 }; 1012 }; 1013 }; 1014 1015 adreno_gpu: gpu@5000000 { 1016 compatible = "qcom,adreno-508.0", "qcom,adreno"; 1017 1018 reg = <0x05000000 0x40000>; 1019 reg-names = "kgsl_3d0_reg_memory"; 1020 1021 interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>; 1022 1023 clocks = <&gcc GCC_GPU_CFG_AHB_CLK>, 1024 <&gpucc GPUCC_RBBMTIMER_CLK>, 1025 <&gcc GCC_BIMC_GFX_CLK>, 1026 <&gcc GCC_GPU_BIMC_GFX_CLK>, 1027 <&gpucc GPUCC_RBCPR_CLK>, 1028 <&gpucc GPUCC_GFX3D_CLK>; 1029 1030 clock-names = "iface", 1031 "rbbmtimer", 1032 "mem", 1033 "mem_iface", 1034 "rbcpr", 1035 "core"; 1036 1037 power-domains = <&rpmpd SDM660_VDDMX>; 1038 iommus = <&kgsl_smmu 0>; 1039 1040 nvmem-cells = <&gpu_speed_bin>; 1041 nvmem-cell-names = "speed_bin"; 1042 1043 interconnects = <&bimc MASTER_OXILI &bimc SLAVE_EBI>; 1044 interconnect-names = "gfx-mem"; 1045 1046 operating-points-v2 = <&gpu_sdm630_opp_table>; 1047 1048 status = "disabled"; 1049 1050 gpu_sdm630_opp_table: opp-table { 1051 compatible = "operating-points-v2"; 1052 opp-775000000 { 1053 opp-hz = /bits/ 64 <775000000>; 1054 opp-level = <RPM_SMD_LEVEL_TURBO>; 1055 opp-peak-kBps = <5412000>; 1056 opp-supported-hw = <0xA2>; 1057 }; 1058 opp-647000000 { 1059 opp-hz = /bits/ 64 <647000000>; 1060 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 1061 opp-peak-kBps = <4068000>; 1062 opp-supported-hw = <0xFF>; 1063 }; 1064 opp-588000000 { 1065 opp-hz = /bits/ 64 <588000000>; 1066 opp-level = <RPM_SMD_LEVEL_NOM>; 1067 opp-peak-kBps = <3072000>; 1068 opp-supported-hw = <0xFF>; 1069 }; 1070 opp-465000000 { 1071 opp-hz = /bits/ 64 <465000000>; 1072 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 1073 opp-peak-kBps = <2724000>; 1074 opp-supported-hw = <0xFF>; 1075 }; 1076 opp-370000000 { 1077 opp-hz = /bits/ 64 <370000000>; 1078 opp-level = <RPM_SMD_LEVEL_SVS>; 1079 opp-peak-kBps = <2188000>; 1080 opp-supported-hw = <0xFF>; 1081 }; 1082 opp-240000000 { 1083 opp-hz = /bits/ 64 <240000000>; 1084 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 1085 opp-peak-kBps = <1648000>; 1086 opp-supported-hw = <0xFF>; 1087 }; 1088 opp-160000000 { 1089 opp-hz = /bits/ 64 <160000000>; 1090 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 1091 opp-peak-kBps = <1200000>; 1092 opp-supported-hw = <0xFF>; 1093 }; 1094 }; 1095 }; 1096 1097 kgsl_smmu: iommu@5040000 { 1098 compatible = "qcom,sdm630-smmu-v2", 1099 "qcom,adreno-smmu", "qcom,smmu-v2"; 1100 reg = <0x05040000 0x10000>; 1101 1102 /* 1103 * GX GDSC parent is CX. We need to bring up CX for SMMU 1104 * but we need both up for Adreno. On the other hand, we 1105 * need to manage the GX rpmpd domain in the adreno driver. 1106 * Enable CX/GX GDSCs here so that we can manage just the GX 1107 * RPM Power Domain in the Adreno driver. 1108 */ 1109 power-domains = <&gpucc GPU_GX_GDSC>; 1110 clocks = <&gcc GCC_GPU_CFG_AHB_CLK>, 1111 <&gcc GCC_BIMC_GFX_CLK>, 1112 <&gcc GCC_GPU_BIMC_GFX_CLK>; 1113 clock-names = "iface", "mem", "mem_iface"; 1114 #global-interrupts = <2>; 1115 #iommu-cells = <1>; 1116 1117 interrupts = 1118 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 1119 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 1120 1121 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 1122 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 1123 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 1124 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 1125 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1126 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1127 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>, 1128 <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>; 1129 1130 status = "disabled"; 1131 }; 1132 1133 gpucc: clock-controller@5065000 { 1134 compatible = "qcom,gpucc-sdm630"; 1135 #clock-cells = <1>; 1136 #reset-cells = <1>; 1137 #power-domain-cells = <1>; 1138 reg = <0x05065000 0x9038>; 1139 1140 clocks = <&xo_board>, 1141 <&gcc GCC_GPU_GPLL0_CLK>, 1142 <&gcc GCC_GPU_GPLL0_DIV_CLK>; 1143 clock-names = "xo", 1144 "gcc_gpu_gpll0_clk", 1145 "gcc_gpu_gpll0_div_clk"; 1146 status = "disabled"; 1147 }; 1148 1149 lpass_smmu: iommu@5100000 { 1150 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2"; 1151 reg = <0x05100000 0x40000>; 1152 #iommu-cells = <1>; 1153 1154 #global-interrupts = <2>; 1155 interrupts = 1156 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 1157 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 1158 1159 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, 1160 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>, 1161 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>, 1162 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 1163 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 1164 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 1165 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 1166 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 1167 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 1168 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 1169 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 1170 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 1171 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 1172 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, 1173 <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>, 1174 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 1175 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>; 1176 1177 status = "disabled"; 1178 }; 1179 1180 sram@290000 { 1181 compatible = "qcom,rpm-stats"; 1182 reg = <0x00290000 0x10000>; 1183 }; 1184 1185 spmi_bus: spmi@800f000 { 1186 compatible = "qcom,spmi-pmic-arb"; 1187 reg = <0x0800f000 0x1000>, 1188 <0x08400000 0x1000000>, 1189 <0x09400000 0x1000000>, 1190 <0x0a400000 0x220000>, 1191 <0x0800a000 0x3000>; 1192 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1193 interrupt-names = "periph_irq"; 1194 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>; 1195 qcom,ee = <0>; 1196 qcom,channel = <0>; 1197 #address-cells = <2>; 1198 #size-cells = <0>; 1199 interrupt-controller; 1200 #interrupt-cells = <4>; 1201 cell-index = <0>; 1202 }; 1203 1204 usb3: usb@a8f8800 { 1205 compatible = "qcom,sdm660-dwc3", "qcom,dwc3"; 1206 reg = <0x0a8f8800 0x400>; 1207 status = "disabled"; 1208 #address-cells = <1>; 1209 #size-cells = <1>; 1210 ranges; 1211 1212 clocks = <&gcc GCC_CFG_NOC_USB3_AXI_CLK>, 1213 <&gcc GCC_USB30_MASTER_CLK>, 1214 <&gcc GCC_AGGRE2_USB3_AXI_CLK>, 1215 <&gcc GCC_USB30_SLEEP_CLK>, 1216 <&gcc GCC_USB30_MOCK_UTMI_CLK>, 1217 <&rpmcc RPM_SMD_AGGR2_NOC_CLK>; 1218 clock-names = "cfg_noc", 1219 "core", 1220 "iface", 1221 "sleep", 1222 "mock_utmi", 1223 "bus"; 1224 1225 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, 1226 <&gcc GCC_USB30_MASTER_CLK>, 1227 <&rpmcc RPM_SMD_AGGR2_NOC_CLK>; 1228 assigned-clock-rates = <19200000>, <120000000>, 1229 <19200000>; 1230 1231 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, 1232 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 1233 interrupt-names = "hs_phy_irq", "ss_phy_irq"; 1234 1235 power-domains = <&gcc USB_30_GDSC>; 1236 qcom,select-utmi-as-pipe-clk; 1237 1238 resets = <&gcc GCC_USB_30_BCR>; 1239 1240 usb3_dwc3: usb@a800000 { 1241 compatible = "snps,dwc3"; 1242 reg = <0x0a800000 0xc8d0>; 1243 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 1244 snps,dis_u2_susphy_quirk; 1245 snps,dis_enblslpm_quirk; 1246 1247 /* 1248 * SDM630 technically supports USB3 but I 1249 * haven't seen any devices making use of it. 1250 */ 1251 maximum-speed = "high-speed"; 1252 phys = <&qusb2phy0>; 1253 phy-names = "usb2-phy"; 1254 snps,hird-threshold = /bits/ 8 <0>; 1255 }; 1256 }; 1257 1258 qusb2phy0: phy@c012000 { 1259 compatible = "qcom,sdm660-qusb2-phy"; 1260 reg = <0x0c012000 0x180>; 1261 #phy-cells = <0>; 1262 1263 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 1264 <&gcc GCC_RX0_USB2_CLKREF_CLK>; 1265 clock-names = "cfg_ahb", "ref"; 1266 1267 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 1268 nvmem-cells = <&qusb2_hstx_trim>; 1269 status = "disabled"; 1270 }; 1271 1272 qusb2phy1: phy@c014000 { 1273 compatible = "qcom,sdm660-qusb2-phy"; 1274 reg = <0x0c014000 0x180>; 1275 #phy-cells = <0>; 1276 1277 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 1278 <&gcc GCC_RX1_USB2_CLKREF_CLK>; 1279 clock-names = "cfg_ahb", "ref"; 1280 1281 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 1282 nvmem-cells = <&qusb2_hstx_trim>; 1283 status = "disabled"; 1284 }; 1285 1286 sdhc_2: mmc@c084000 { 1287 compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5"; 1288 reg = <0x0c084000 0x1000>; 1289 reg-names = "hc"; 1290 1291 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1292 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 1293 interrupt-names = "hc_irq", "pwr_irq"; 1294 1295 bus-width = <4>; 1296 1297 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 1298 <&gcc GCC_SDCC2_APPS_CLK>, 1299 <&xo_board>; 1300 clock-names = "iface", "core", "xo"; 1301 1302 1303 interconnects = <&a2noc 3 &a2noc 10>, 1304 <&gnoc 0 &cnoc 28>; 1305 interconnect-names = "sdhc-ddr","cpu-sdhc"; 1306 operating-points-v2 = <&sdhc2_opp_table>; 1307 1308 pinctrl-names = "default", "sleep"; 1309 pinctrl-0 = <&sdc2_state_on>; 1310 pinctrl-1 = <&sdc2_state_off>; 1311 power-domains = <&rpmpd SDM660_VDDCX>; 1312 1313 status = "disabled"; 1314 1315 sdhc2_opp_table: opp-table { 1316 compatible = "operating-points-v2"; 1317 1318 opp-50000000 { 1319 opp-hz = /bits/ 64 <50000000>; 1320 required-opps = <&rpmpd_opp_low_svs>; 1321 opp-peak-kBps = <200000 140000>; 1322 opp-avg-kBps = <130718 133320>; 1323 }; 1324 opp-100000000 { 1325 opp-hz = /bits/ 64 <100000000>; 1326 required-opps = <&rpmpd_opp_svs>; 1327 opp-peak-kBps = <250000 160000>; 1328 opp-avg-kBps = <196078 150000>; 1329 }; 1330 opp-200000000 { 1331 opp-hz = /bits/ 64 <200000000>; 1332 required-opps = <&rpmpd_opp_nom>; 1333 opp-peak-kBps = <4096000 4096000>; 1334 opp-avg-kBps = <1338562 1338562>; 1335 }; 1336 }; 1337 }; 1338 1339 sdhc_1: mmc@c0c4000 { 1340 compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5"; 1341 reg = <0x0c0c4000 0x1000>, 1342 <0x0c0c5000 0x1000>, 1343 <0x0c0c8000 0x8000>; 1344 reg-names = "hc", "cqhci", "ice"; 1345 1346 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1347 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1348 interrupt-names = "hc_irq", "pwr_irq"; 1349 1350 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 1351 <&gcc GCC_SDCC1_APPS_CLK>, 1352 <&xo_board>, 1353 <&gcc GCC_SDCC1_ICE_CORE_CLK>; 1354 clock-names = "iface", "core", "xo", "ice"; 1355 1356 interconnects = <&a2noc 2 &a2noc 10>, 1357 <&gnoc 0 &cnoc 27>; 1358 interconnect-names = "sdhc-ddr", "cpu-sdhc"; 1359 operating-points-v2 = <&sdhc1_opp_table>; 1360 pinctrl-names = "default", "sleep"; 1361 pinctrl-0 = <&sdc1_state_on>; 1362 pinctrl-1 = <&sdc1_state_off>; 1363 power-domains = <&rpmpd SDM660_VDDCX>; 1364 1365 bus-width = <8>; 1366 non-removable; 1367 1368 status = "disabled"; 1369 1370 sdhc1_opp_table: opp-table { 1371 compatible = "operating-points-v2"; 1372 1373 opp-50000000 { 1374 opp-hz = /bits/ 64 <50000000>; 1375 required-opps = <&rpmpd_opp_low_svs>; 1376 opp-peak-kBps = <200000 140000>; 1377 opp-avg-kBps = <130718 133320>; 1378 }; 1379 opp-100000000 { 1380 opp-hz = /bits/ 64 <100000000>; 1381 required-opps = <&rpmpd_opp_svs>; 1382 opp-peak-kBps = <250000 160000>; 1383 opp-avg-kBps = <196078 150000>; 1384 }; 1385 opp-384000000 { 1386 opp-hz = /bits/ 64 <384000000>; 1387 required-opps = <&rpmpd_opp_nom>; 1388 opp-peak-kBps = <4096000 4096000>; 1389 opp-avg-kBps = <1338562 1338562>; 1390 }; 1391 }; 1392 }; 1393 1394 usb2: usb@c2f8800 { 1395 compatible = "qcom,sdm660-dwc3", "qcom,dwc3"; 1396 reg = <0x0c2f8800 0x400>; 1397 status = "disabled"; 1398 #address-cells = <1>; 1399 #size-cells = <1>; 1400 ranges; 1401 1402 clocks = <&gcc GCC_CFG_NOC_USB2_AXI_CLK>, 1403 <&gcc GCC_USB20_MASTER_CLK>, 1404 <&gcc GCC_USB20_MOCK_UTMI_CLK>, 1405 <&gcc GCC_USB20_SLEEP_CLK>; 1406 clock-names = "cfg_noc", "core", 1407 "mock_utmi", "sleep"; 1408 1409 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, 1410 <&gcc GCC_USB20_MASTER_CLK>; 1411 assigned-clock-rates = <19200000>, <60000000>; 1412 1413 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>; 1414 interrupt-names = "hs_phy_irq"; 1415 1416 qcom,select-utmi-as-pipe-clk; 1417 1418 resets = <&gcc GCC_USB_20_BCR>; 1419 1420 usb2_dwc3: usb@c200000 { 1421 compatible = "snps,dwc3"; 1422 reg = <0x0c200000 0xc8d0>; 1423 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 1424 snps,dis_u2_susphy_quirk; 1425 snps,dis_enblslpm_quirk; 1426 1427 /* This is the HS-only host */ 1428 maximum-speed = "high-speed"; 1429 phys = <&qusb2phy1>; 1430 phy-names = "usb2-phy"; 1431 snps,hird-threshold = /bits/ 8 <0>; 1432 }; 1433 }; 1434 1435 mmcc: clock-controller@c8c0000 { 1436 compatible = "qcom,mmcc-sdm630"; 1437 reg = <0x0c8c0000 0x40000>; 1438 #clock-cells = <1>; 1439 #reset-cells = <1>; 1440 #power-domain-cells = <1>; 1441 clock-names = "xo", 1442 "sleep_clk", 1443 "gpll0", 1444 "gpll0_div", 1445 "dsi0pll", 1446 "dsi0pllbyte", 1447 "dsi1pll", 1448 "dsi1pllbyte", 1449 "dp_link_2x_clk_divsel_five", 1450 "dp_vco_divided_clk_src_mux"; 1451 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 1452 <&sleep_clk>, 1453 <&gcc GCC_MMSS_GPLL0_CLK>, 1454 <&gcc GCC_MMSS_GPLL0_DIV_CLK>, 1455 <&dsi0_phy 1>, 1456 <&dsi0_phy 0>, 1457 <0>, 1458 <0>, 1459 <0>, 1460 <0>; 1461 }; 1462 1463 dsi_opp_table: opp-table-dsi { 1464 compatible = "operating-points-v2"; 1465 1466 opp-131250000 { 1467 opp-hz = /bits/ 64 <131250000>; 1468 required-opps = <&rpmpd_opp_svs>; 1469 }; 1470 1471 opp-210000000 { 1472 opp-hz = /bits/ 64 <210000000>; 1473 required-opps = <&rpmpd_opp_svs_plus>; 1474 }; 1475 1476 opp-262500000 { 1477 opp-hz = /bits/ 64 <262500000>; 1478 required-opps = <&rpmpd_opp_nom>; 1479 }; 1480 }; 1481 1482 mdss: mdss@c900000 { 1483 compatible = "qcom,mdss"; 1484 reg = <0x0c900000 0x1000>, 1485 <0x0c9b0000 0x1040>; 1486 reg-names = "mdss_phys", "vbif_phys"; 1487 1488 power-domains = <&mmcc MDSS_GDSC>; 1489 1490 clocks = <&mmcc MDSS_AHB_CLK>, 1491 <&mmcc MDSS_AXI_CLK>, 1492 <&mmcc MDSS_VSYNC_CLK>, 1493 <&mmcc MDSS_MDP_CLK>; 1494 clock-names = "iface", 1495 "bus", 1496 "vsync", 1497 "core"; 1498 1499 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 1500 1501 interrupt-controller; 1502 #interrupt-cells = <1>; 1503 1504 #address-cells = <1>; 1505 #size-cells = <1>; 1506 ranges; 1507 status = "disabled"; 1508 1509 mdp: mdp@c901000 { 1510 compatible = "qcom,mdp5"; 1511 reg = <0x0c901000 0x89000>; 1512 reg-names = "mdp_phys"; 1513 1514 interrupt-parent = <&mdss>; 1515 interrupts = <0>; 1516 1517 assigned-clocks = <&mmcc MDSS_MDP_CLK>, 1518 <&mmcc MDSS_VSYNC_CLK>; 1519 assigned-clock-rates = <300000000>, 1520 <19200000>; 1521 clocks = <&mmcc MDSS_AHB_CLK>, 1522 <&mmcc MDSS_AXI_CLK>, 1523 <&mmcc MDSS_MDP_CLK>, 1524 <&mmcc MDSS_VSYNC_CLK>; 1525 clock-names = "iface", 1526 "bus", 1527 "core", 1528 "vsync"; 1529 1530 interconnects = <&mnoc 2 &bimc 5>, 1531 <&mnoc 3 &bimc 5>, 1532 <&gnoc 0 &mnoc 17>; 1533 interconnect-names = "mdp0-mem", 1534 "mdp1-mem", 1535 "rotator-mem"; 1536 iommus = <&mmss_smmu 0>; 1537 operating-points-v2 = <&mdp_opp_table>; 1538 power-domains = <&rpmpd SDM660_VDDCX>; 1539 1540 ports { 1541 #address-cells = <1>; 1542 #size-cells = <0>; 1543 1544 port@0 { 1545 reg = <0>; 1546 mdp5_intf1_out: endpoint { 1547 remote-endpoint = <&dsi0_in>; 1548 }; 1549 }; 1550 }; 1551 1552 mdp_opp_table: opp-table { 1553 compatible = "operating-points-v2"; 1554 1555 opp-150000000 { 1556 opp-hz = /bits/ 64 <150000000>; 1557 opp-peak-kBps = <320000 320000 76800>; 1558 required-opps = <&rpmpd_opp_low_svs>; 1559 }; 1560 opp-275000000 { 1561 opp-hz = /bits/ 64 <275000000>; 1562 opp-peak-kBps = <6400000 6400000 160000>; 1563 required-opps = <&rpmpd_opp_svs>; 1564 }; 1565 opp-300000000 { 1566 opp-hz = /bits/ 64 <300000000>; 1567 opp-peak-kBps = <6400000 6400000 190000>; 1568 required-opps = <&rpmpd_opp_svs_plus>; 1569 }; 1570 opp-330000000 { 1571 opp-hz = /bits/ 64 <330000000>; 1572 opp-peak-kBps = <6400000 6400000 240000>; 1573 required-opps = <&rpmpd_opp_nom>; 1574 }; 1575 opp-412500000 { 1576 opp-hz = /bits/ 64 <412500000>; 1577 opp-peak-kBps = <6400000 6400000 320000>; 1578 required-opps = <&rpmpd_opp_turbo>; 1579 }; 1580 }; 1581 }; 1582 1583 dsi0: dsi@c994000 { 1584 compatible = "qcom,mdss-dsi-ctrl"; 1585 reg = <0x0c994000 0x400>; 1586 reg-names = "dsi_ctrl"; 1587 1588 operating-points-v2 = <&dsi_opp_table>; 1589 power-domains = <&rpmpd SDM660_VDDCX>; 1590 1591 interrupt-parent = <&mdss>; 1592 interrupts = <4>; 1593 1594 assigned-clocks = <&mmcc BYTE0_CLK_SRC>, 1595 <&mmcc PCLK0_CLK_SRC>; 1596 assigned-clock-parents = <&dsi0_phy 0>, 1597 <&dsi0_phy 1>; 1598 1599 clocks = <&mmcc MDSS_MDP_CLK>, 1600 <&mmcc MDSS_BYTE0_CLK>, 1601 <&mmcc MDSS_BYTE0_INTF_CLK>, 1602 <&mmcc MNOC_AHB_CLK>, 1603 <&mmcc MDSS_AHB_CLK>, 1604 <&mmcc MDSS_AXI_CLK>, 1605 <&mmcc MISC_AHB_CLK>, 1606 <&mmcc MDSS_PCLK0_CLK>, 1607 <&mmcc MDSS_ESC0_CLK>; 1608 clock-names = "mdp_core", 1609 "byte", 1610 "byte_intf", 1611 "mnoc", 1612 "iface", 1613 "bus", 1614 "core_mmss", 1615 "pixel", 1616 "core"; 1617 1618 phys = <&dsi0_phy>; 1619 phy-names = "dsi"; 1620 1621 status = "disabled"; 1622 1623 ports { 1624 #address-cells = <1>; 1625 #size-cells = <0>; 1626 1627 port@0 { 1628 reg = <0>; 1629 dsi0_in: endpoint { 1630 remote-endpoint = <&mdp5_intf1_out>; 1631 }; 1632 }; 1633 1634 port@1 { 1635 reg = <1>; 1636 dsi0_out: endpoint { 1637 }; 1638 }; 1639 }; 1640 }; 1641 1642 dsi0_phy: dsi-phy@c994400 { 1643 compatible = "qcom,dsi-phy-14nm-660"; 1644 reg = <0x0c994400 0x100>, 1645 <0x0c994500 0x300>, 1646 <0x0c994800 0x188>; 1647 reg-names = "dsi_phy", 1648 "dsi_phy_lane", 1649 "dsi_pll"; 1650 1651 #clock-cells = <1>; 1652 #phy-cells = <0>; 1653 1654 clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>; 1655 clock-names = "iface", "ref"; 1656 status = "disabled"; 1657 }; 1658 }; 1659 1660 blsp1_dma: dma-controller@c144000 { 1661 compatible = "qcom,bam-v1.7.0"; 1662 reg = <0x0c144000 0x1f000>; 1663 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 1664 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 1665 clock-names = "bam_clk"; 1666 #dma-cells = <1>; 1667 qcom,ee = <0>; 1668 qcom,controlled-remotely; 1669 num-channels = <18>; 1670 qcom,num-ees = <4>; 1671 }; 1672 1673 blsp1_uart1: serial@c16f000 { 1674 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1675 reg = <0x0c16f000 0x200>; 1676 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1677 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, 1678 <&gcc GCC_BLSP1_AHB_CLK>; 1679 clock-names = "core", "iface"; 1680 dmas = <&blsp1_dma 0>, <&blsp1_dma 1>; 1681 dma-names = "tx", "rx"; 1682 pinctrl-names = "default", "sleep"; 1683 pinctrl-0 = <&blsp1_uart1_default>; 1684 pinctrl-1 = <&blsp1_uart1_sleep>; 1685 status = "disabled"; 1686 }; 1687 1688 blsp1_uart2: serial@c170000 { 1689 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1690 reg = <0x0c170000 0x1000>; 1691 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1692 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, 1693 <&gcc GCC_BLSP1_AHB_CLK>; 1694 clock-names = "core", "iface"; 1695 dmas = <&blsp1_dma 2>, <&blsp1_dma 3>; 1696 dma-names = "tx", "rx"; 1697 pinctrl-names = "default"; 1698 pinctrl-0 = <&blsp1_uart2_default>; 1699 status = "disabled"; 1700 }; 1701 1702 blsp_i2c1: i2c@c175000 { 1703 compatible = "qcom,i2c-qup-v2.2.1"; 1704 reg = <0x0c175000 0x600>; 1705 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1706 1707 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, 1708 <&gcc GCC_BLSP1_AHB_CLK>; 1709 clock-names = "core", "iface"; 1710 clock-frequency = <400000>; 1711 dmas = <&blsp1_dma 4>, <&blsp1_dma 5>; 1712 dma-names = "tx", "rx"; 1713 1714 pinctrl-names = "default", "sleep"; 1715 pinctrl-0 = <&i2c1_default>; 1716 pinctrl-1 = <&i2c1_sleep>; 1717 #address-cells = <1>; 1718 #size-cells = <0>; 1719 status = "disabled"; 1720 }; 1721 1722 blsp_i2c2: i2c@c176000 { 1723 compatible = "qcom,i2c-qup-v2.2.1"; 1724 reg = <0x0c176000 0x600>; 1725 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1726 1727 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 1728 <&gcc GCC_BLSP1_AHB_CLK>; 1729 clock-names = "core", "iface"; 1730 clock-frequency = <400000>; 1731 dmas = <&blsp1_dma 6>, <&blsp1_dma 7>; 1732 dma-names = "tx", "rx"; 1733 1734 pinctrl-names = "default", "sleep"; 1735 pinctrl-0 = <&i2c2_default>; 1736 pinctrl-1 = <&i2c2_sleep>; 1737 #address-cells = <1>; 1738 #size-cells = <0>; 1739 status = "disabled"; 1740 }; 1741 1742 blsp_i2c3: i2c@c177000 { 1743 compatible = "qcom,i2c-qup-v2.2.1"; 1744 reg = <0x0c177000 0x600>; 1745 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1746 1747 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 1748 <&gcc GCC_BLSP1_AHB_CLK>; 1749 clock-names = "core", "iface"; 1750 clock-frequency = <400000>; 1751 dmas = <&blsp1_dma 8>, <&blsp1_dma 9>; 1752 dma-names = "tx", "rx"; 1753 1754 pinctrl-names = "default", "sleep"; 1755 pinctrl-0 = <&i2c3_default>; 1756 pinctrl-1 = <&i2c3_sleep>; 1757 #address-cells = <1>; 1758 #size-cells = <0>; 1759 status = "disabled"; 1760 }; 1761 1762 blsp_i2c4: i2c@c178000 { 1763 compatible = "qcom,i2c-qup-v2.2.1"; 1764 reg = <0x0c178000 0x600>; 1765 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1766 1767 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, 1768 <&gcc GCC_BLSP1_AHB_CLK>; 1769 clock-names = "core", "iface"; 1770 clock-frequency = <400000>; 1771 dmas = <&blsp1_dma 10>, <&blsp1_dma 11>; 1772 dma-names = "tx", "rx"; 1773 1774 pinctrl-names = "default", "sleep"; 1775 pinctrl-0 = <&i2c4_default>; 1776 pinctrl-1 = <&i2c4_sleep>; 1777 #address-cells = <1>; 1778 #size-cells = <0>; 1779 status = "disabled"; 1780 }; 1781 1782 blsp2_dma: dma-controller@c184000 { 1783 compatible = "qcom,bam-v1.7.0"; 1784 reg = <0x0c184000 0x1f000>; 1785 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 1786 clocks = <&gcc GCC_BLSP2_AHB_CLK>; 1787 clock-names = "bam_clk"; 1788 #dma-cells = <1>; 1789 qcom,ee = <0>; 1790 qcom,controlled-remotely; 1791 num-channels = <18>; 1792 qcom,num-ees = <4>; 1793 }; 1794 1795 blsp2_uart1: serial@c1af000 { 1796 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1797 reg = <0x0c1af000 0x200>; 1798 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 1799 clocks = <&gcc GCC_BLSP2_UART1_APPS_CLK>, 1800 <&gcc GCC_BLSP2_AHB_CLK>; 1801 clock-names = "core", "iface"; 1802 dmas = <&blsp2_dma 0>, <&blsp2_dma 1>; 1803 dma-names = "tx", "rx"; 1804 pinctrl-names = "default", "sleep"; 1805 pinctrl-0 = <&blsp2_uart1_default>; 1806 pinctrl-1 = <&blsp2_uart1_sleep>; 1807 status = "disabled"; 1808 }; 1809 1810 blsp_i2c5: i2c@c1b5000 { 1811 compatible = "qcom,i2c-qup-v2.2.1"; 1812 reg = <0x0c1b5000 0x600>; 1813 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 1814 1815 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, 1816 <&gcc GCC_BLSP2_AHB_CLK>; 1817 clock-names = "core", "iface"; 1818 clock-frequency = <400000>; 1819 dmas = <&blsp2_dma 4>, <&blsp2_dma 5>; 1820 dma-names = "tx", "rx"; 1821 1822 pinctrl-names = "default", "sleep"; 1823 pinctrl-0 = <&i2c5_default>; 1824 pinctrl-1 = <&i2c5_sleep>; 1825 #address-cells = <1>; 1826 #size-cells = <0>; 1827 status = "disabled"; 1828 }; 1829 1830 blsp_i2c6: i2c@c1b6000 { 1831 compatible = "qcom,i2c-qup-v2.2.1"; 1832 reg = <0x0c1b6000 0x600>; 1833 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 1834 1835 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, 1836 <&gcc GCC_BLSP2_AHB_CLK>; 1837 clock-names = "core", "iface"; 1838 clock-frequency = <400000>; 1839 dmas = <&blsp2_dma 6>, <&blsp2_dma 7>; 1840 dma-names = "tx", "rx"; 1841 1842 pinctrl-names = "default", "sleep"; 1843 pinctrl-0 = <&i2c6_default>; 1844 pinctrl-1 = <&i2c6_sleep>; 1845 #address-cells = <1>; 1846 #size-cells = <0>; 1847 status = "disabled"; 1848 }; 1849 1850 blsp_i2c7: i2c@c1b7000 { 1851 compatible = "qcom,i2c-qup-v2.2.1"; 1852 reg = <0x0c1b7000 0x600>; 1853 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 1854 1855 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>, 1856 <&gcc GCC_BLSP2_AHB_CLK>; 1857 clock-names = "core", "iface"; 1858 clock-frequency = <400000>; 1859 dmas = <&blsp2_dma 8>, <&blsp2_dma 9>; 1860 dma-names = "tx", "rx"; 1861 1862 pinctrl-names = "default", "sleep"; 1863 pinctrl-0 = <&i2c7_default>; 1864 pinctrl-1 = <&i2c7_sleep>; 1865 #address-cells = <1>; 1866 #size-cells = <0>; 1867 status = "disabled"; 1868 }; 1869 1870 blsp_i2c8: i2c@c1b8000 { 1871 compatible = "qcom,i2c-qup-v2.2.1"; 1872 reg = <0x0c1b8000 0x600>; 1873 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 1874 1875 clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>, 1876 <&gcc GCC_BLSP2_AHB_CLK>; 1877 clock-names = "core", "iface"; 1878 clock-frequency = <400000>; 1879 dmas = <&blsp2_dma 10>, <&blsp2_dma 11>; 1880 dma-names = "tx", "rx"; 1881 1882 pinctrl-names = "default", "sleep"; 1883 pinctrl-0 = <&i2c8_default>; 1884 pinctrl-1 = <&i2c8_sleep>; 1885 #address-cells = <1>; 1886 #size-cells = <0>; 1887 status = "disabled"; 1888 }; 1889 1890 sram@146bf000 { 1891 compatible = "qcom,sdm630-imem", "syscon", "simple-mfd"; 1892 reg = <0x146bf000 0x1000>; 1893 1894 #address-cells = <1>; 1895 #size-cells = <1>; 1896 1897 ranges = <0 0x146bf000 0x1000>; 1898 1899 pil-reloc@94c { 1900 compatible = "qcom,pil-reloc-info"; 1901 reg = <0x94c 0xc8>; 1902 }; 1903 }; 1904 1905 camss: camss@ca00000 { 1906 compatible = "qcom,sdm660-camss"; 1907 reg = <0x0ca00020 0x10>, 1908 <0x0ca30000 0x100>, 1909 <0x0ca30400 0x100>, 1910 <0x0ca30800 0x100>, 1911 <0x0ca30c00 0x100>, 1912 <0x0c824000 0x1000>, 1913 <0x0ca00120 0x4>, 1914 <0x0c825000 0x1000>, 1915 <0x0ca00124 0x4>, 1916 <0x0c826000 0x1000>, 1917 <0x0ca00128 0x4>, 1918 <0x0ca31000 0x500>, 1919 <0x0ca10000 0x1000>, 1920 <0x0ca14000 0x1000>; 1921 reg-names = "csi_clk_mux", 1922 "csid0", 1923 "csid1", 1924 "csid2", 1925 "csid3", 1926 "csiphy0", 1927 "csiphy0_clk_mux", 1928 "csiphy1", 1929 "csiphy1_clk_mux", 1930 "csiphy2", 1931 "csiphy2_clk_mux", 1932 "ispif", 1933 "vfe0", 1934 "vfe1"; 1935 interrupts = <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>, 1936 <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>, 1937 <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>, 1938 <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>, 1939 <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>, 1940 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>, 1941 <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>, 1942 <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>, 1943 <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>, 1944 <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>; 1945 interrupt-names = "csid0", 1946 "csid1", 1947 "csid2", 1948 "csid3", 1949 "csiphy0", 1950 "csiphy1", 1951 "csiphy2", 1952 "ispif", 1953 "vfe0", 1954 "vfe1"; 1955 clocks = <&mmcc CAMSS_AHB_CLK>, 1956 <&mmcc CAMSS_CPHY_CSID0_CLK>, 1957 <&mmcc CAMSS_CPHY_CSID1_CLK>, 1958 <&mmcc CAMSS_CPHY_CSID2_CLK>, 1959 <&mmcc CAMSS_CPHY_CSID3_CLK>, 1960 <&mmcc CAMSS_CSI0_AHB_CLK>, 1961 <&mmcc CAMSS_CSI0_CLK>, 1962 <&mmcc CAMSS_CPHY_CSID0_CLK>, 1963 <&mmcc CAMSS_CSI0PIX_CLK>, 1964 <&mmcc CAMSS_CSI0RDI_CLK>, 1965 <&mmcc CAMSS_CSI1_AHB_CLK>, 1966 <&mmcc CAMSS_CSI1_CLK>, 1967 <&mmcc CAMSS_CPHY_CSID1_CLK>, 1968 <&mmcc CAMSS_CSI1PIX_CLK>, 1969 <&mmcc CAMSS_CSI1RDI_CLK>, 1970 <&mmcc CAMSS_CSI2_AHB_CLK>, 1971 <&mmcc CAMSS_CSI2_CLK>, 1972 <&mmcc CAMSS_CPHY_CSID2_CLK>, 1973 <&mmcc CAMSS_CSI2PIX_CLK>, 1974 <&mmcc CAMSS_CSI2RDI_CLK>, 1975 <&mmcc CAMSS_CSI3_AHB_CLK>, 1976 <&mmcc CAMSS_CSI3_CLK>, 1977 <&mmcc CAMSS_CPHY_CSID3_CLK>, 1978 <&mmcc CAMSS_CSI3PIX_CLK>, 1979 <&mmcc CAMSS_CSI3RDI_CLK>, 1980 <&mmcc CAMSS_CSI0PHYTIMER_CLK>, 1981 <&mmcc CAMSS_CSI1PHYTIMER_CLK>, 1982 <&mmcc CAMSS_CSI2PHYTIMER_CLK>, 1983 <&mmcc CSIPHY_AHB2CRIF_CLK>, 1984 <&mmcc CAMSS_CSI_VFE0_CLK>, 1985 <&mmcc CAMSS_CSI_VFE1_CLK>, 1986 <&mmcc CAMSS_ISPIF_AHB_CLK>, 1987 <&mmcc THROTTLE_CAMSS_AXI_CLK>, 1988 <&mmcc CAMSS_TOP_AHB_CLK>, 1989 <&mmcc CAMSS_VFE0_AHB_CLK>, 1990 <&mmcc CAMSS_VFE0_CLK>, 1991 <&mmcc CAMSS_VFE0_STREAM_CLK>, 1992 <&mmcc CAMSS_VFE1_AHB_CLK>, 1993 <&mmcc CAMSS_VFE1_CLK>, 1994 <&mmcc CAMSS_VFE1_STREAM_CLK>, 1995 <&mmcc CAMSS_VFE_VBIF_AHB_CLK>, 1996 <&mmcc CAMSS_VFE_VBIF_AXI_CLK>; 1997 clock-names = "ahb", 1998 "cphy_csid0", 1999 "cphy_csid1", 2000 "cphy_csid2", 2001 "cphy_csid3", 2002 "csi0_ahb", 2003 "csi0", 2004 "csi0_phy", 2005 "csi0_pix", 2006 "csi0_rdi", 2007 "csi1_ahb", 2008 "csi1", 2009 "csi1_phy", 2010 "csi1_pix", 2011 "csi1_rdi", 2012 "csi2_ahb", 2013 "csi2", 2014 "csi2_phy", 2015 "csi2_pix", 2016 "csi2_rdi", 2017 "csi3_ahb", 2018 "csi3", 2019 "csi3_phy", 2020 "csi3_pix", 2021 "csi3_rdi", 2022 "csiphy0_timer", 2023 "csiphy1_timer", 2024 "csiphy2_timer", 2025 "csiphy_ahb2crif", 2026 "csi_vfe0", 2027 "csi_vfe1", 2028 "ispif_ahb", 2029 "throttle_axi", 2030 "top_ahb", 2031 "vfe0_ahb", 2032 "vfe0", 2033 "vfe0_stream", 2034 "vfe1_ahb", 2035 "vfe1", 2036 "vfe1_stream", 2037 "vfe_ahb", 2038 "vfe_axi"; 2039 interconnects = <&mnoc 5 &bimc 5>; 2040 interconnect-names = "vfe-mem"; 2041 iommus = <&mmss_smmu 0xc00>, 2042 <&mmss_smmu 0xc01>, 2043 <&mmss_smmu 0xc02>, 2044 <&mmss_smmu 0xc03>; 2045 power-domains = <&mmcc CAMSS_VFE0_GDSC>, 2046 <&mmcc CAMSS_VFE1_GDSC>; 2047 status = "disabled"; 2048 2049 ports { 2050 #address-cells = <1>; 2051 #size-cells = <0>; 2052 }; 2053 }; 2054 2055 cci: cci@ca0c000 { 2056 compatible = "qcom,msm8996-cci"; 2057 #address-cells = <1>; 2058 #size-cells = <0>; 2059 reg = <0x0ca0c000 0x1000>; 2060 interrupts = <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>; 2061 2062 assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>, 2063 <&mmcc CAMSS_CCI_CLK>; 2064 assigned-clock-rates = <80800000>, <37500000>; 2065 clocks = <&mmcc CAMSS_TOP_AHB_CLK>, 2066 <&mmcc CAMSS_CCI_AHB_CLK>, 2067 <&mmcc CAMSS_CCI_CLK>, 2068 <&mmcc CAMSS_AHB_CLK>; 2069 clock-names = "camss_top_ahb", 2070 "cci_ahb", 2071 "cci", 2072 "camss_ahb"; 2073 2074 pinctrl-names = "default"; 2075 pinctrl-0 = <&cci0_default &cci1_default>; 2076 power-domains = <&mmcc CAMSS_TOP_GDSC>; 2077 status = "disabled"; 2078 2079 cci_i2c0: i2c-bus@0 { 2080 reg = <0>; 2081 clock-frequency = <400000>; 2082 #address-cells = <1>; 2083 #size-cells = <0>; 2084 }; 2085 2086 cci_i2c1: i2c-bus@1 { 2087 reg = <1>; 2088 clock-frequency = <400000>; 2089 #address-cells = <1>; 2090 #size-cells = <0>; 2091 }; 2092 }; 2093 2094 venus: video-codec@cc00000 { 2095 compatible = "qcom,sdm660-venus"; 2096 reg = <0x0cc00000 0xff000>; 2097 clocks = <&mmcc VIDEO_CORE_CLK>, 2098 <&mmcc VIDEO_AHB_CLK>, 2099 <&mmcc VIDEO_AXI_CLK>, 2100 <&mmcc THROTTLE_VIDEO_AXI_CLK>; 2101 clock-names = "core", "iface", "bus", "bus_throttle"; 2102 interconnects = <&gnoc 0 &mnoc 13>, 2103 <&mnoc 4 &bimc 5>; 2104 interconnect-names = "cpu-cfg", "video-mem"; 2105 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 2106 iommus = <&mmss_smmu 0x400>, 2107 <&mmss_smmu 0x401>, 2108 <&mmss_smmu 0x40a>, 2109 <&mmss_smmu 0x407>, 2110 <&mmss_smmu 0x40e>, 2111 <&mmss_smmu 0x40f>, 2112 <&mmss_smmu 0x408>, 2113 <&mmss_smmu 0x409>, 2114 <&mmss_smmu 0x40b>, 2115 <&mmss_smmu 0x40c>, 2116 <&mmss_smmu 0x40d>, 2117 <&mmss_smmu 0x410>, 2118 <&mmss_smmu 0x421>, 2119 <&mmss_smmu 0x428>, 2120 <&mmss_smmu 0x429>, 2121 <&mmss_smmu 0x42b>, 2122 <&mmss_smmu 0x42c>, 2123 <&mmss_smmu 0x42d>, 2124 <&mmss_smmu 0x411>, 2125 <&mmss_smmu 0x431>; 2126 memory-region = <&venus_region>; 2127 power-domains = <&mmcc VENUS_GDSC>; 2128 status = "disabled"; 2129 2130 video-decoder { 2131 compatible = "venus-decoder"; 2132 clocks = <&mmcc VIDEO_SUBCORE0_CLK>; 2133 clock-names = "vcodec0_core"; 2134 power-domains = <&mmcc VENUS_CORE0_GDSC>; 2135 }; 2136 2137 video-encoder { 2138 compatible = "venus-encoder"; 2139 clocks = <&mmcc VIDEO_SUBCORE0_CLK>; 2140 clock-names = "vcodec0_core"; 2141 power-domains = <&mmcc VENUS_CORE0_GDSC>; 2142 }; 2143 }; 2144 2145 mmss_smmu: iommu@cd00000 { 2146 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2"; 2147 reg = <0x0cd00000 0x40000>; 2148 2149 clocks = <&mmcc MNOC_AHB_CLK>, 2150 <&mmcc BIMC_SMMU_AHB_CLK>, 2151 <&rpmcc RPM_SMD_MMSSNOC_AXI_CLK>, 2152 <&mmcc BIMC_SMMU_AXI_CLK>; 2153 clock-names = "iface-mm", "iface-smmu", 2154 "bus-mm", "bus-smmu"; 2155 #global-interrupts = <2>; 2156 #iommu-cells = <1>; 2157 2158 interrupts = 2159 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 2160 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 2161 2162 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 2163 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 2164 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, 2165 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 2166 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 2167 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 2168 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 2169 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 2170 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 2171 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 2172 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 2173 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 2174 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 2175 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 2176 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 2177 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 2178 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 2179 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 2180 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 2181 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, 2182 <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, 2183 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 2184 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 2185 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>; 2186 2187 status = "disabled"; 2188 }; 2189 2190 adsp_pil: remoteproc@15700000 { 2191 compatible = "qcom,sdm660-adsp-pas"; 2192 reg = <0x15700000 0x4040>; 2193 2194 interrupts-extended = 2195 <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 2196 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2197 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2198 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2199 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2200 interrupt-names = "wdog", "fatal", "ready", 2201 "handover", "stop-ack"; 2202 2203 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 2204 clock-names = "xo"; 2205 2206 memory-region = <&adsp_region>; 2207 power-domains = <&rpmpd SDM660_VDDCX>; 2208 power-domain-names = "cx"; 2209 2210 qcom,smem-states = <&adsp_smp2p_out 0>; 2211 qcom,smem-state-names = "stop"; 2212 2213 glink-edge { 2214 interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>; 2215 2216 label = "lpass"; 2217 mboxes = <&apcs_glb 9>; 2218 qcom,remote-pid = <2>; 2219 2220 apr { 2221 compatible = "qcom,apr-v2"; 2222 qcom,glink-channels = "apr_audio_svc"; 2223 qcom,domain = <APR_DOMAIN_ADSP>; 2224 #address-cells = <1>; 2225 #size-cells = <0>; 2226 2227 q6core { 2228 reg = <APR_SVC_ADSP_CORE>; 2229 compatible = "qcom,q6core"; 2230 }; 2231 2232 q6afe: apr-service@4 { 2233 compatible = "qcom,q6afe"; 2234 reg = <APR_SVC_AFE>; 2235 q6afedai: dais { 2236 compatible = "qcom,q6afe-dais"; 2237 #address-cells = <1>; 2238 #size-cells = <0>; 2239 #sound-dai-cells = <1>; 2240 }; 2241 }; 2242 2243 q6asm: apr-service@7 { 2244 compatible = "qcom,q6asm"; 2245 reg = <APR_SVC_ASM>; 2246 q6asmdai: dais { 2247 compatible = "qcom,q6asm-dais"; 2248 #address-cells = <1>; 2249 #size-cells = <0>; 2250 #sound-dai-cells = <1>; 2251 iommus = <&lpass_smmu 1>; 2252 }; 2253 }; 2254 2255 q6adm: apr-service@8 { 2256 compatible = "qcom,q6adm"; 2257 reg = <APR_SVC_ADM>; 2258 q6routing: routing { 2259 compatible = "qcom,q6adm-routing"; 2260 #sound-dai-cells = <0>; 2261 }; 2262 }; 2263 }; 2264 }; 2265 }; 2266 2267 gnoc: interconnect@17900000 { 2268 compatible = "qcom,sdm660-gnoc"; 2269 reg = <0x17900000 0xe000>; 2270 #interconnect-cells = <1>; 2271 /* 2272 * This one apparently features no clocks, 2273 * so let's not mess with the driver needlessly 2274 */ 2275 clock-names = "bus", "bus_a"; 2276 clocks = <&xo_board>, <&xo_board>; 2277 }; 2278 2279 apcs_glb: mailbox@17911000 { 2280 compatible = "qcom,sdm660-apcs-hmss-global"; 2281 reg = <0x17911000 0x1000>; 2282 2283 #mbox-cells = <1>; 2284 }; 2285 2286 timer@17920000 { 2287 #address-cells = <1>; 2288 #size-cells = <1>; 2289 ranges; 2290 compatible = "arm,armv7-timer-mem"; 2291 reg = <0x17920000 0x1000>; 2292 clock-frequency = <19200000>; 2293 2294 frame@17921000 { 2295 frame-number = <0>; 2296 interrupts = <0 8 0x4>, 2297 <0 7 0x4>; 2298 reg = <0x17921000 0x1000>, 2299 <0x17922000 0x1000>; 2300 }; 2301 2302 frame@17923000 { 2303 frame-number = <1>; 2304 interrupts = <0 9 0x4>; 2305 reg = <0x17923000 0x1000>; 2306 status = "disabled"; 2307 }; 2308 2309 frame@17924000 { 2310 frame-number = <2>; 2311 interrupts = <0 10 0x4>; 2312 reg = <0x17924000 0x1000>; 2313 status = "disabled"; 2314 }; 2315 2316 frame@17925000 { 2317 frame-number = <3>; 2318 interrupts = <0 11 0x4>; 2319 reg = <0x17925000 0x1000>; 2320 status = "disabled"; 2321 }; 2322 2323 frame@17926000 { 2324 frame-number = <4>; 2325 interrupts = <0 12 0x4>; 2326 reg = <0x17926000 0x1000>; 2327 status = "disabled"; 2328 }; 2329 2330 frame@17927000 { 2331 frame-number = <5>; 2332 interrupts = <0 13 0x4>; 2333 reg = <0x17927000 0x1000>; 2334 status = "disabled"; 2335 }; 2336 2337 frame@17928000 { 2338 frame-number = <6>; 2339 interrupts = <0 14 0x4>; 2340 reg = <0x17928000 0x1000>; 2341 status = "disabled"; 2342 }; 2343 }; 2344 2345 intc: interrupt-controller@17a00000 { 2346 compatible = "arm,gic-v3"; 2347 reg = <0x17a00000 0x10000>, /* GICD */ 2348 <0x17b00000 0x100000>; /* GICR * 8 */ 2349 #interrupt-cells = <3>; 2350 #address-cells = <1>; 2351 #size-cells = <1>; 2352 ranges; 2353 interrupt-controller; 2354 #redistributor-regions = <1>; 2355 redistributor-stride = <0x0 0x20000>; 2356 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 2357 }; 2358 }; 2359 2360 sound: sound { 2361 }; 2362 2363 thermal-zones { 2364 aoss-thermal { 2365 polling-delay-passive = <250>; 2366 polling-delay = <1000>; 2367 2368 thermal-sensors = <&tsens 0>; 2369 2370 trips { 2371 aoss_alert0: trip-point0 { 2372 temperature = <105000>; 2373 hysteresis = <1000>; 2374 type = "hot"; 2375 }; 2376 }; 2377 }; 2378 2379 cpuss0-thermal { 2380 polling-delay-passive = <250>; 2381 polling-delay = <1000>; 2382 2383 thermal-sensors = <&tsens 1>; 2384 2385 trips { 2386 cpuss0_alert0: trip-point0 { 2387 temperature = <125000>; 2388 hysteresis = <1000>; 2389 type = "hot"; 2390 }; 2391 }; 2392 }; 2393 2394 cpuss1-thermal { 2395 polling-delay-passive = <250>; 2396 polling-delay = <1000>; 2397 2398 thermal-sensors = <&tsens 2>; 2399 2400 trips { 2401 cpuss1_alert0: trip-point0 { 2402 temperature = <125000>; 2403 hysteresis = <1000>; 2404 type = "hot"; 2405 }; 2406 }; 2407 }; 2408 2409 cpu0-thermal { 2410 polling-delay-passive = <250>; 2411 polling-delay = <1000>; 2412 2413 thermal-sensors = <&tsens 3>; 2414 2415 trips { 2416 cpu0_alert0: trip-point0 { 2417 temperature = <70000>; 2418 hysteresis = <1000>; 2419 type = "passive"; 2420 }; 2421 2422 cpu0_crit: cpu_crit { 2423 temperature = <110000>; 2424 hysteresis = <1000>; 2425 type = "critical"; 2426 }; 2427 }; 2428 }; 2429 2430 cpu1-thermal { 2431 polling-delay-passive = <250>; 2432 polling-delay = <1000>; 2433 2434 thermal-sensors = <&tsens 4>; 2435 2436 trips { 2437 cpu1_alert0: trip-point0 { 2438 temperature = <70000>; 2439 hysteresis = <1000>; 2440 type = "passive"; 2441 }; 2442 2443 cpu1_crit: cpu_crit { 2444 temperature = <110000>; 2445 hysteresis = <1000>; 2446 type = "critical"; 2447 }; 2448 }; 2449 }; 2450 2451 cpu2-thermal { 2452 polling-delay-passive = <250>; 2453 polling-delay = <1000>; 2454 2455 thermal-sensors = <&tsens 5>; 2456 2457 trips { 2458 cpu2_alert0: trip-point0 { 2459 temperature = <70000>; 2460 hysteresis = <1000>; 2461 type = "passive"; 2462 }; 2463 2464 cpu2_crit: cpu_crit { 2465 temperature = <110000>; 2466 hysteresis = <1000>; 2467 type = "critical"; 2468 }; 2469 }; 2470 }; 2471 2472 cpu3-thermal { 2473 polling-delay-passive = <250>; 2474 polling-delay = <1000>; 2475 2476 thermal-sensors = <&tsens 6>; 2477 2478 trips { 2479 cpu3_alert0: trip-point0 { 2480 temperature = <70000>; 2481 hysteresis = <1000>; 2482 type = "passive"; 2483 }; 2484 2485 cpu3_crit: cpu_crit { 2486 temperature = <110000>; 2487 hysteresis = <1000>; 2488 type = "critical"; 2489 }; 2490 }; 2491 }; 2492 2493 /* 2494 * According to what downstream DTS says, 2495 * the entire power efficient cluster has 2496 * only a single thermal sensor. 2497 */ 2498 2499 pwr-cluster-thermal { 2500 polling-delay-passive = <250>; 2501 polling-delay = <1000>; 2502 2503 thermal-sensors = <&tsens 7>; 2504 2505 trips { 2506 pwr_cluster_alert0: trip-point0 { 2507 temperature = <70000>; 2508 hysteresis = <1000>; 2509 type = "passive"; 2510 }; 2511 2512 pwr_cluster_crit: cpu_crit { 2513 temperature = <110000>; 2514 hysteresis = <1000>; 2515 type = "critical"; 2516 }; 2517 }; 2518 }; 2519 2520 gpu-thermal { 2521 polling-delay-passive = <250>; 2522 polling-delay = <1000>; 2523 2524 thermal-sensors = <&tsens 8>; 2525 2526 trips { 2527 gpu_alert0: trip-point0 { 2528 temperature = <90000>; 2529 hysteresis = <1000>; 2530 type = "hot"; 2531 }; 2532 }; 2533 }; 2534 }; 2535 2536 timer { 2537 compatible = "arm,armv8-timer"; 2538 interrupts = <GIC_PPI 1 0xf08>, 2539 <GIC_PPI 2 0xf08>, 2540 <GIC_PPI 3 0xf08>, 2541 <GIC_PPI 0 0xf08>; 2542 }; 2543}; 2544 2545