1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2020, Konrad Dybcio <konradybcio@gmail.com> 4 * Copyright (c) 2020, AngeloGioacchino Del Regno <kholk11@gmail.com> 5 */ 6 7#include <dt-bindings/clock/qcom,gcc-sdm660.h> 8#include <dt-bindings/clock/qcom,gpucc-sdm660.h> 9#include <dt-bindings/clock/qcom,mmcc-sdm660.h> 10#include <dt-bindings/clock/qcom,rpmcc.h> 11#include <dt-bindings/interconnect/qcom,sdm660.h> 12#include <dt-bindings/power/qcom-rpmpd.h> 13#include <dt-bindings/gpio/gpio.h> 14#include <dt-bindings/interrupt-controller/arm-gic.h> 15#include <dt-bindings/soc/qcom,apr.h> 16 17/ { 18 interrupt-parent = <&intc>; 19 20 #address-cells = <2>; 21 #size-cells = <2>; 22 23 aliases { 24 mmc1 = &sdhc_1; 25 mmc2 = &sdhc_2; 26 }; 27 28 chosen { }; 29 30 clocks { 31 xo_board: xo-board { 32 compatible = "fixed-clock"; 33 #clock-cells = <0>; 34 clock-frequency = <19200000>; 35 clock-output-names = "xo_board"; 36 }; 37 38 sleep_clk: sleep-clk { 39 compatible = "fixed-clock"; 40 #clock-cells = <0>; 41 clock-frequency = <32764>; 42 clock-output-names = "sleep_clk"; 43 }; 44 }; 45 46 cpus { 47 #address-cells = <2>; 48 #size-cells = <0>; 49 50 CPU0: cpu@100 { 51 device_type = "cpu"; 52 compatible = "arm,cortex-a53"; 53 reg = <0x0 0x100>; 54 enable-method = "psci"; 55 cpu-idle-states = <&PERF_CPU_SLEEP_0 56 &PERF_CPU_SLEEP_1 57 &PERF_CLUSTER_SLEEP_0 58 &PERF_CLUSTER_SLEEP_1 59 &PERF_CLUSTER_SLEEP_2>; 60 capacity-dmips-mhz = <1126>; 61 #cooling-cells = <2>; 62 next-level-cache = <&L2_1>; 63 L2_1: l2-cache { 64 compatible = "cache"; 65 cache-level = <2>; 66 }; 67 }; 68 69 CPU1: cpu@101 { 70 device_type = "cpu"; 71 compatible = "arm,cortex-a53"; 72 reg = <0x0 0x101>; 73 enable-method = "psci"; 74 cpu-idle-states = <&PERF_CPU_SLEEP_0 75 &PERF_CPU_SLEEP_1 76 &PERF_CLUSTER_SLEEP_0 77 &PERF_CLUSTER_SLEEP_1 78 &PERF_CLUSTER_SLEEP_2>; 79 capacity-dmips-mhz = <1126>; 80 #cooling-cells = <2>; 81 next-level-cache = <&L2_1>; 82 }; 83 84 CPU2: cpu@102 { 85 device_type = "cpu"; 86 compatible = "arm,cortex-a53"; 87 reg = <0x0 0x102>; 88 enable-method = "psci"; 89 cpu-idle-states = <&PERF_CPU_SLEEP_0 90 &PERF_CPU_SLEEP_1 91 &PERF_CLUSTER_SLEEP_0 92 &PERF_CLUSTER_SLEEP_1 93 &PERF_CLUSTER_SLEEP_2>; 94 capacity-dmips-mhz = <1126>; 95 #cooling-cells = <2>; 96 next-level-cache = <&L2_1>; 97 }; 98 99 CPU3: cpu@103 { 100 device_type = "cpu"; 101 compatible = "arm,cortex-a53"; 102 reg = <0x0 0x103>; 103 enable-method = "psci"; 104 cpu-idle-states = <&PERF_CPU_SLEEP_0 105 &PERF_CPU_SLEEP_1 106 &PERF_CLUSTER_SLEEP_0 107 &PERF_CLUSTER_SLEEP_1 108 &PERF_CLUSTER_SLEEP_2>; 109 capacity-dmips-mhz = <1126>; 110 #cooling-cells = <2>; 111 next-level-cache = <&L2_1>; 112 }; 113 114 CPU4: cpu@0 { 115 device_type = "cpu"; 116 compatible = "arm,cortex-a53"; 117 reg = <0x0 0x0>; 118 enable-method = "psci"; 119 cpu-idle-states = <&PWR_CPU_SLEEP_0 120 &PWR_CPU_SLEEP_1 121 &PWR_CLUSTER_SLEEP_0 122 &PWR_CLUSTER_SLEEP_1 123 &PWR_CLUSTER_SLEEP_2>; 124 capacity-dmips-mhz = <1024>; 125 #cooling-cells = <2>; 126 next-level-cache = <&L2_0>; 127 L2_0: l2-cache { 128 compatible = "cache"; 129 cache-level = <2>; 130 }; 131 }; 132 133 CPU5: cpu@1 { 134 device_type = "cpu"; 135 compatible = "arm,cortex-a53"; 136 reg = <0x0 0x1>; 137 enable-method = "psci"; 138 cpu-idle-states = <&PWR_CPU_SLEEP_0 139 &PWR_CPU_SLEEP_1 140 &PWR_CLUSTER_SLEEP_0 141 &PWR_CLUSTER_SLEEP_1 142 &PWR_CLUSTER_SLEEP_2>; 143 capacity-dmips-mhz = <1024>; 144 #cooling-cells = <2>; 145 next-level-cache = <&L2_0>; 146 }; 147 148 CPU6: cpu@2 { 149 device_type = "cpu"; 150 compatible = "arm,cortex-a53"; 151 reg = <0x0 0x2>; 152 enable-method = "psci"; 153 cpu-idle-states = <&PWR_CPU_SLEEP_0 154 &PWR_CPU_SLEEP_1 155 &PWR_CLUSTER_SLEEP_0 156 &PWR_CLUSTER_SLEEP_1 157 &PWR_CLUSTER_SLEEP_2>; 158 capacity-dmips-mhz = <1024>; 159 #cooling-cells = <2>; 160 next-level-cache = <&L2_0>; 161 }; 162 163 CPU7: cpu@3 { 164 device_type = "cpu"; 165 compatible = "arm,cortex-a53"; 166 reg = <0x0 0x3>; 167 enable-method = "psci"; 168 cpu-idle-states = <&PWR_CPU_SLEEP_0 169 &PWR_CPU_SLEEP_1 170 &PWR_CLUSTER_SLEEP_0 171 &PWR_CLUSTER_SLEEP_1 172 &PWR_CLUSTER_SLEEP_2>; 173 capacity-dmips-mhz = <1024>; 174 #cooling-cells = <2>; 175 next-level-cache = <&L2_0>; 176 }; 177 178 cpu-map { 179 cluster0 { 180 core0 { 181 cpu = <&CPU4>; 182 }; 183 184 core1 { 185 cpu = <&CPU5>; 186 }; 187 188 core2 { 189 cpu = <&CPU6>; 190 }; 191 192 core3 { 193 cpu = <&CPU7>; 194 }; 195 }; 196 197 cluster1 { 198 core0 { 199 cpu = <&CPU0>; 200 }; 201 202 core1 { 203 cpu = <&CPU1>; 204 }; 205 206 core2 { 207 cpu = <&CPU2>; 208 }; 209 210 core3 { 211 cpu = <&CPU3>; 212 }; 213 }; 214 }; 215 216 idle-states { 217 entry-method = "psci"; 218 219 PWR_CPU_SLEEP_0: cpu-sleep-0-0 { 220 compatible = "arm,idle-state"; 221 idle-state-name = "pwr-retention"; 222 arm,psci-suspend-param = <0x40000002>; 223 entry-latency-us = <338>; 224 exit-latency-us = <423>; 225 min-residency-us = <200>; 226 }; 227 228 PWR_CPU_SLEEP_1: cpu-sleep-0-1 { 229 compatible = "arm,idle-state"; 230 idle-state-name = "pwr-power-collapse"; 231 arm,psci-suspend-param = <0x40000003>; 232 entry-latency-us = <515>; 233 exit-latency-us = <1821>; 234 min-residency-us = <1000>; 235 local-timer-stop; 236 }; 237 238 PERF_CPU_SLEEP_0: cpu-sleep-1-0 { 239 compatible = "arm,idle-state"; 240 idle-state-name = "perf-retention"; 241 arm,psci-suspend-param = <0x40000002>; 242 entry-latency-us = <154>; 243 exit-latency-us = <87>; 244 min-residency-us = <200>; 245 }; 246 247 PERF_CPU_SLEEP_1: cpu-sleep-1-1 { 248 compatible = "arm,idle-state"; 249 idle-state-name = "perf-power-collapse"; 250 arm,psci-suspend-param = <0x40000003>; 251 entry-latency-us = <262>; 252 exit-latency-us = <301>; 253 min-residency-us = <1000>; 254 local-timer-stop; 255 }; 256 257 PWR_CLUSTER_SLEEP_0: cluster-sleep-0-0 { 258 compatible = "arm,idle-state"; 259 idle-state-name = "pwr-cluster-dynamic-retention"; 260 arm,psci-suspend-param = <0x400000F2>; 261 entry-latency-us = <284>; 262 exit-latency-us = <384>; 263 min-residency-us = <9987>; 264 local-timer-stop; 265 }; 266 267 PWR_CLUSTER_SLEEP_1: cluster-sleep-0-1 { 268 compatible = "arm,idle-state"; 269 idle-state-name = "pwr-cluster-retention"; 270 arm,psci-suspend-param = <0x400000F3>; 271 entry-latency-us = <338>; 272 exit-latency-us = <423>; 273 min-residency-us = <9987>; 274 local-timer-stop; 275 }; 276 277 PWR_CLUSTER_SLEEP_2: cluster-sleep-0-2 { 278 compatible = "arm,idle-state"; 279 idle-state-name = "pwr-cluster-retention"; 280 arm,psci-suspend-param = <0x400000F4>; 281 entry-latency-us = <515>; 282 exit-latency-us = <1821>; 283 min-residency-us = <9987>; 284 local-timer-stop; 285 }; 286 287 PERF_CLUSTER_SLEEP_0: cluster-sleep-1-0 { 288 compatible = "arm,idle-state"; 289 idle-state-name = "perf-cluster-dynamic-retention"; 290 arm,psci-suspend-param = <0x400000F2>; 291 entry-latency-us = <272>; 292 exit-latency-us = <329>; 293 min-residency-us = <9987>; 294 local-timer-stop; 295 }; 296 297 PERF_CLUSTER_SLEEP_1: cluster-sleep-1-1 { 298 compatible = "arm,idle-state"; 299 idle-state-name = "perf-cluster-retention"; 300 arm,psci-suspend-param = <0x400000F3>; 301 entry-latency-us = <332>; 302 exit-latency-us = <368>; 303 min-residency-us = <9987>; 304 local-timer-stop; 305 }; 306 307 PERF_CLUSTER_SLEEP_2: cluster-sleep-1-2 { 308 compatible = "arm,idle-state"; 309 idle-state-name = "perf-cluster-retention"; 310 arm,psci-suspend-param = <0x400000F4>; 311 entry-latency-us = <545>; 312 exit-latency-us = <1609>; 313 min-residency-us = <9987>; 314 local-timer-stop; 315 }; 316 }; 317 }; 318 319 firmware { 320 scm { 321 compatible = "qcom,scm-msm8998", "qcom,scm"; 322 }; 323 }; 324 325 memory@80000000 { 326 device_type = "memory"; 327 /* We expect the bootloader to fill in the reg */ 328 reg = <0x0 0x80000000 0x0 0x0>; 329 }; 330 331 pmu { 332 compatible = "arm,armv8-pmuv3"; 333 interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>; 334 }; 335 336 psci { 337 compatible = "arm,psci-1.0"; 338 method = "smc"; 339 }; 340 341 reserved-memory { 342 #address-cells = <2>; 343 #size-cells = <2>; 344 ranges; 345 346 wlan_msa_guard: wlan-msa-guard@85600000 { 347 reg = <0x0 0x85600000 0x0 0x100000>; 348 no-map; 349 }; 350 351 wlan_msa_mem: wlan-msa-mem@85700000 { 352 reg = <0x0 0x85700000 0x0 0x100000>; 353 no-map; 354 }; 355 356 qhee_code: qhee-code@85800000 { 357 reg = <0x0 0x85800000 0x0 0x600000>; 358 no-map; 359 }; 360 361 rmtfs_mem: memory@85e00000 { 362 compatible = "qcom,rmtfs-mem"; 363 reg = <0x0 0x85e00000 0x0 0x200000>; 364 no-map; 365 366 qcom,client-id = <1>; 367 qcom,vmid = <15>; 368 }; 369 370 smem_region: smem-mem@86000000 { 371 reg = <0 0x86000000 0 0x200000>; 372 no-map; 373 }; 374 375 tz_mem: memory@86200000 { 376 reg = <0x0 0x86200000 0x0 0x3300000>; 377 no-map; 378 }; 379 380 mpss_region: mpss@8ac00000 { 381 reg = <0x0 0x8ac00000 0x0 0x7e00000>; 382 no-map; 383 }; 384 385 adsp_region: adsp@92a00000 { 386 reg = <0x0 0x92a00000 0x0 0x1e00000>; 387 no-map; 388 }; 389 390 mba_region: mba@94800000 { 391 reg = <0x0 0x94800000 0x0 0x200000>; 392 no-map; 393 }; 394 395 buffer_mem: tzbuffer@94a00000 { 396 reg = <0x0 0x94a00000 0x0 0x100000>; 397 no-map; 398 }; 399 400 venus_region: venus@9f800000 { 401 reg = <0x0 0x9f800000 0x0 0x800000>; 402 no-map; 403 }; 404 405 adsp_mem: adsp-region@f6000000 { 406 reg = <0x0 0xf6000000 0x0 0x800000>; 407 no-map; 408 }; 409 410 qseecom_mem: qseecom-region@f6800000 { 411 reg = <0x0 0xf6800000 0x0 0x1400000>; 412 no-map; 413 }; 414 415 zap_shader_region: gpu@fed00000 { 416 compatible = "shared-dma-pool"; 417 reg = <0x0 0xfed00000 0x0 0xa00000>; 418 no-map; 419 }; 420 }; 421 422 rpm-glink { 423 compatible = "qcom,glink-rpm"; 424 425 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 426 qcom,rpm-msg-ram = <&rpm_msg_ram>; 427 mboxes = <&apcs_glb 0>; 428 429 rpm_requests: rpm-requests { 430 compatible = "qcom,rpm-sdm660"; 431 qcom,glink-channels = "rpm_requests"; 432 433 rpmcc: clock-controller { 434 compatible = "qcom,rpmcc-sdm660", "qcom,rpmcc"; 435 #clock-cells = <1>; 436 }; 437 438 rpmpd: power-controller { 439 compatible = "qcom,sdm660-rpmpd"; 440 #power-domain-cells = <1>; 441 operating-points-v2 = <&rpmpd_opp_table>; 442 443 rpmpd_opp_table: opp-table { 444 compatible = "operating-points-v2"; 445 446 rpmpd_opp_ret: opp1 { 447 opp-level = <RPM_SMD_LEVEL_RETENTION>; 448 }; 449 450 rpmpd_opp_ret_plus: opp2 { 451 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>; 452 }; 453 454 rpmpd_opp_min_svs: opp3 { 455 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 456 }; 457 458 rpmpd_opp_low_svs: opp4 { 459 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 460 }; 461 462 rpmpd_opp_svs: opp5 { 463 opp-level = <RPM_SMD_LEVEL_SVS>; 464 }; 465 466 rpmpd_opp_svs_plus: opp6 { 467 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 468 }; 469 470 rpmpd_opp_nom: opp7 { 471 opp-level = <RPM_SMD_LEVEL_NOM>; 472 }; 473 474 rpmpd_opp_nom_plus: opp8 { 475 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 476 }; 477 478 rpmpd_opp_turbo: opp9 { 479 opp-level = <RPM_SMD_LEVEL_TURBO>; 480 }; 481 }; 482 }; 483 }; 484 }; 485 486 smem: smem { 487 compatible = "qcom,smem"; 488 memory-region = <&smem_region>; 489 hwlocks = <&tcsr_mutex 3>; 490 }; 491 492 smp2p-adsp { 493 compatible = "qcom,smp2p"; 494 qcom,smem = <443>, <429>; 495 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 496 mboxes = <&apcs_glb 10>; 497 qcom,local-pid = <0>; 498 qcom,remote-pid = <2>; 499 500 adsp_smp2p_out: master-kernel { 501 qcom,entry-name = "master-kernel"; 502 #qcom,smem-state-cells = <1>; 503 }; 504 505 adsp_smp2p_in: slave-kernel { 506 qcom,entry-name = "slave-kernel"; 507 interrupt-controller; 508 #interrupt-cells = <2>; 509 }; 510 }; 511 512 smp2p-mpss { 513 compatible = "qcom,smp2p"; 514 qcom,smem = <435>, <428>; 515 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 516 mboxes = <&apcs_glb 14>; 517 qcom,local-pid = <0>; 518 qcom,remote-pid = <1>; 519 520 modem_smp2p_out: master-kernel { 521 qcom,entry-name = "master-kernel"; 522 #qcom,smem-state-cells = <1>; 523 }; 524 525 modem_smp2p_in: slave-kernel { 526 qcom,entry-name = "slave-kernel"; 527 interrupt-controller; 528 #interrupt-cells = <2>; 529 }; 530 }; 531 532 soc { 533 #address-cells = <1>; 534 #size-cells = <1>; 535 ranges = <0 0 0 0xffffffff>; 536 compatible = "simple-bus"; 537 538 gcc: clock-controller@100000 { 539 compatible = "qcom,gcc-sdm630"; 540 #clock-cells = <1>; 541 #reset-cells = <1>; 542 #power-domain-cells = <1>; 543 reg = <0x00100000 0x94000>; 544 545 clock-names = "xo", "sleep_clk"; 546 clocks = <&xo_board>, 547 <&sleep_clk>; 548 }; 549 550 rpm_msg_ram: sram@778000 { 551 compatible = "qcom,rpm-msg-ram"; 552 reg = <0x00778000 0x7000>; 553 }; 554 555 qfprom: qfprom@780000 { 556 compatible = "qcom,sdm630-qfprom", "qcom,qfprom"; 557 reg = <0x00780000 0x621c>; 558 #address-cells = <1>; 559 #size-cells = <1>; 560 561 qusb2_hstx_trim: hstx-trim@240 { 562 reg = <0x243 0x1>; 563 bits = <1 3>; 564 }; 565 566 gpu_speed_bin: gpu-speed-bin@41a0 { 567 reg = <0x41a2 0x1>; 568 bits = <5 7>; 569 }; 570 }; 571 572 rng: rng@793000 { 573 compatible = "qcom,prng-ee"; 574 reg = <0x00793000 0x1000>; 575 clocks = <&gcc GCC_PRNG_AHB_CLK>; 576 clock-names = "core"; 577 }; 578 579 bimc: interconnect@1008000 { 580 compatible = "qcom,sdm660-bimc"; 581 reg = <0x01008000 0x78000>; 582 #interconnect-cells = <1>; 583 clock-names = "bus", "bus_a"; 584 clocks = <&rpmcc RPM_SMD_BIMC_CLK>, 585 <&rpmcc RPM_SMD_BIMC_A_CLK>; 586 }; 587 588 restart@10ac000 { 589 compatible = "qcom,pshold"; 590 reg = <0x010ac000 0x4>; 591 }; 592 593 cnoc: interconnect@1500000 { 594 compatible = "qcom,sdm660-cnoc"; 595 reg = <0x01500000 0x10000>; 596 #interconnect-cells = <1>; 597 clock-names = "bus", "bus_a"; 598 clocks = <&rpmcc RPM_SMD_CNOC_CLK>, 599 <&rpmcc RPM_SMD_CNOC_A_CLK>; 600 }; 601 602 snoc: interconnect@1626000 { 603 compatible = "qcom,sdm660-snoc"; 604 reg = <0x01626000 0x7090>; 605 #interconnect-cells = <1>; 606 clock-names = "bus", "bus_a"; 607 clocks = <&rpmcc RPM_SMD_SNOC_CLK>, 608 <&rpmcc RPM_SMD_SNOC_A_CLK>; 609 }; 610 611 anoc2_smmu: iommu@16c0000 { 612 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2"; 613 reg = <0x016c0000 0x40000>; 614 615 assigned-clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>; 616 assigned-clock-rates = <1000>; 617 clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>; 618 clock-names = "bus"; 619 #global-interrupts = <2>; 620 #iommu-cells = <1>; 621 622 interrupts = 623 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 624 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 625 626 <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>, 627 <GIC_SPI 374 IRQ_TYPE_LEVEL_LOW>, 628 <GIC_SPI 375 IRQ_TYPE_LEVEL_LOW>, 629 <GIC_SPI 376 IRQ_TYPE_LEVEL_LOW>, 630 <GIC_SPI 377 IRQ_TYPE_LEVEL_LOW>, 631 <GIC_SPI 378 IRQ_TYPE_LEVEL_LOW>, 632 <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>, 633 <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>, 634 <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>, 635 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>, 636 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>, 637 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>, 638 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>, 639 <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, 640 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>, 641 <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>, 642 <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>, 643 <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, 644 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, 645 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, 646 <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>, 647 <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>, 648 <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, 649 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>, 650 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>, 651 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>, 652 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, 653 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, 654 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>; 655 656 status = "disabled"; 657 }; 658 659 a2noc: interconnect@1704000 { 660 compatible = "qcom,sdm660-a2noc"; 661 reg = <0x01704000 0xc100>; 662 #interconnect-cells = <1>; 663 clock-names = "bus", 664 "bus_a", 665 "ipa", 666 "ufs_axi", 667 "aggre2_ufs_axi", 668 "aggre2_usb3_axi", 669 "cfg_noc_usb2_axi"; 670 clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>, 671 <&rpmcc RPM_SMD_AGGR2_NOC_A_CLK>, 672 <&rpmcc RPM_SMD_IPA_CLK>, 673 <&gcc GCC_UFS_AXI_CLK>, 674 <&gcc GCC_AGGRE2_UFS_AXI_CLK>, 675 <&gcc GCC_AGGRE2_USB3_AXI_CLK>, 676 <&gcc GCC_CFG_NOC_USB2_AXI_CLK>; 677 }; 678 679 mnoc: interconnect@1745000 { 680 compatible = "qcom,sdm660-mnoc"; 681 reg = <0x01745000 0xA010>; 682 #interconnect-cells = <1>; 683 clock-names = "bus", "bus_a", "iface"; 684 clocks = <&rpmcc RPM_SMD_MMSSNOC_AXI_CLK>, 685 <&rpmcc RPM_SMD_MMSSNOC_AXI_CLK_A>, 686 <&mmcc AHB_CLK_SRC>; 687 }; 688 689 tsens: thermal-sensor@10ae000 { 690 compatible = "qcom,sdm630-tsens", "qcom,tsens-v2"; 691 reg = <0x010ae000 0x1000>, /* TM */ 692 <0x010ad000 0x1000>; /* SROT */ 693 #qcom,sensors = <12>; 694 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 695 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>; 696 interrupt-names = "uplow", "critical"; 697 #thermal-sensor-cells = <1>; 698 }; 699 700 tcsr_mutex: hwlock@1f40000 { 701 compatible = "qcom,tcsr-mutex"; 702 reg = <0x01f40000 0x20000>; 703 #hwlock-cells = <1>; 704 }; 705 706 tcsr_regs_1: syscon@1f60000 { 707 compatible = "qcom,sdm630-tcsr", "syscon"; 708 reg = <0x01f60000 0x20000>; 709 }; 710 711 tlmm: pinctrl@3100000 { 712 compatible = "qcom,sdm630-pinctrl"; 713 reg = <0x03100000 0x400000>, 714 <0x03500000 0x400000>, 715 <0x03900000 0x400000>; 716 reg-names = "south", "center", "north"; 717 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 718 gpio-controller; 719 gpio-ranges = <&tlmm 0 0 114>; 720 #gpio-cells = <2>; 721 interrupt-controller; 722 #interrupt-cells = <2>; 723 724 blsp1_uart1_default: blsp1-uart1-default { 725 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 726 function = "blsp_uart1"; 727 drive-strength = <2>; 728 bias-disable; 729 }; 730 731 blsp1_uart1_sleep: blsp1-uart1-sleep { 732 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 733 drive-strength = <2>; 734 bias-disable; 735 }; 736 737 blsp1_uart2_default: blsp1-uart2-default { 738 pins = "gpio4", "gpio5"; 739 function = "blsp_uart2"; 740 drive-strength = <2>; 741 bias-disable; 742 }; 743 744 blsp2_uart1_default: blsp2-uart1-active { 745 tx-rts { 746 pins = "gpio16", "gpio19"; 747 function = "blsp_uart5"; 748 drive-strength = <2>; 749 bias-disable; 750 }; 751 752 rx { 753 /* 754 * Avoid garbage data while BT module 755 * is powered off or not driving signal 756 */ 757 pins = "gpio17"; 758 function = "blsp_uart5"; 759 drive-strength = <2>; 760 bias-pull-up; 761 }; 762 763 cts { 764 /* Match the pull of the BT module */ 765 pins = "gpio18"; 766 function = "blsp_uart5"; 767 drive-strength = <2>; 768 bias-pull-down; 769 }; 770 }; 771 772 blsp2_uart1_sleep: blsp2-uart1-sleep { 773 tx { 774 pins = "gpio16"; 775 function = "gpio"; 776 drive-strength = <2>; 777 bias-pull-up; 778 }; 779 780 rx-cts-rts { 781 pins = "gpio17", "gpio18", "gpio19"; 782 function = "gpio"; 783 drive-strength = <2>; 784 bias-disable; 785 }; 786 }; 787 788 i2c1_default: i2c1-default { 789 pins = "gpio2", "gpio3"; 790 function = "blsp_i2c1"; 791 drive-strength = <2>; 792 bias-disable; 793 }; 794 795 i2c1_sleep: i2c1-sleep { 796 pins = "gpio2", "gpio3"; 797 function = "blsp_i2c1"; 798 drive-strength = <2>; 799 bias-pull-up; 800 }; 801 802 i2c2_default: i2c2-default { 803 pins = "gpio6", "gpio7"; 804 function = "blsp_i2c2"; 805 drive-strength = <2>; 806 bias-disable; 807 }; 808 809 i2c2_sleep: i2c2-sleep { 810 pins = "gpio6", "gpio7"; 811 function = "blsp_i2c2"; 812 drive-strength = <2>; 813 bias-pull-up; 814 }; 815 816 i2c3_default: i2c3-default { 817 pins = "gpio10", "gpio11"; 818 function = "blsp_i2c3"; 819 drive-strength = <2>; 820 bias-disable; 821 }; 822 823 i2c3_sleep: i2c3-sleep { 824 pins = "gpio10", "gpio11"; 825 function = "blsp_i2c3"; 826 drive-strength = <2>; 827 bias-pull-up; 828 }; 829 830 i2c4_default: i2c4-default { 831 pins = "gpio14", "gpio15"; 832 function = "blsp_i2c4"; 833 drive-strength = <2>; 834 bias-disable; 835 }; 836 837 i2c4_sleep: i2c4-sleep { 838 pins = "gpio14", "gpio15"; 839 function = "blsp_i2c4"; 840 drive-strength = <2>; 841 bias-pull-up; 842 }; 843 844 i2c5_default: i2c5-default { 845 pins = "gpio18", "gpio19"; 846 function = "blsp_i2c5"; 847 drive-strength = <2>; 848 bias-disable; 849 }; 850 851 i2c5_sleep: i2c5-sleep { 852 pins = "gpio18", "gpio19"; 853 function = "blsp_i2c5"; 854 drive-strength = <2>; 855 bias-pull-up; 856 }; 857 858 i2c6_default: i2c6-default { 859 pins = "gpio22", "gpio23"; 860 function = "blsp_i2c6"; 861 drive-strength = <2>; 862 bias-disable; 863 }; 864 865 i2c6_sleep: i2c6-sleep { 866 pins = "gpio22", "gpio23"; 867 function = "blsp_i2c6"; 868 drive-strength = <2>; 869 bias-pull-up; 870 }; 871 872 i2c7_default: i2c7-default { 873 pins = "gpio26", "gpio27"; 874 function = "blsp_i2c7"; 875 drive-strength = <2>; 876 bias-disable; 877 }; 878 879 i2c7_sleep: i2c7-sleep { 880 pins = "gpio26", "gpio27"; 881 function = "blsp_i2c7"; 882 drive-strength = <2>; 883 bias-pull-up; 884 }; 885 886 i2c8_default: i2c8-default { 887 pins = "gpio30", "gpio31"; 888 function = "blsp_i2c8"; 889 drive-strength = <2>; 890 bias-disable; 891 }; 892 893 i2c8_sleep: i2c8-sleep { 894 pins = "gpio30", "gpio31"; 895 function = "blsp_i2c8"; 896 drive-strength = <2>; 897 bias-pull-up; 898 }; 899 900 cci0_default: cci0_default { 901 pinmux { 902 pins = "gpio36","gpio37"; 903 function = "cci_i2c"; 904 }; 905 906 pinconf { 907 pins = "gpio36","gpio37"; 908 bias-pull-up; 909 drive-strength = <2>; 910 }; 911 }; 912 913 cci1_default: cci1_default { 914 pinmux { 915 pins = "gpio38","gpio39"; 916 function = "cci_i2c"; 917 }; 918 919 pinconf { 920 pins = "gpio38","gpio39"; 921 bias-pull-up; 922 drive-strength = <2>; 923 }; 924 }; 925 926 sdc1_state_on: sdc1-on { 927 clk { 928 pins = "sdc1_clk"; 929 bias-disable; 930 drive-strength = <16>; 931 }; 932 933 cmd { 934 pins = "sdc1_cmd"; 935 bias-pull-up; 936 drive-strength = <10>; 937 }; 938 939 data { 940 pins = "sdc1_data"; 941 bias-pull-up; 942 drive-strength = <10>; 943 }; 944 945 rclk { 946 pins = "sdc1_rclk"; 947 bias-pull-down; 948 }; 949 }; 950 951 sdc1_state_off: sdc1-off { 952 clk { 953 pins = "sdc1_clk"; 954 bias-disable; 955 drive-strength = <2>; 956 }; 957 958 cmd { 959 pins = "sdc1_cmd"; 960 bias-pull-up; 961 drive-strength = <2>; 962 }; 963 964 data { 965 pins = "sdc1_data"; 966 bias-pull-up; 967 drive-strength = <2>; 968 }; 969 970 rclk { 971 pins = "sdc1_rclk"; 972 bias-pull-down; 973 }; 974 }; 975 976 sdc2_state_on: sdc2-on { 977 clk { 978 pins = "sdc2_clk"; 979 bias-disable; 980 drive-strength = <16>; 981 }; 982 983 cmd { 984 pins = "sdc2_cmd"; 985 bias-pull-up; 986 drive-strength = <10>; 987 }; 988 989 data { 990 pins = "sdc2_data"; 991 bias-pull-up; 992 drive-strength = <10>; 993 }; 994 }; 995 996 sdc2_state_off: sdc2-off { 997 clk { 998 pins = "sdc2_clk"; 999 bias-disable; 1000 drive-strength = <2>; 1001 }; 1002 1003 cmd { 1004 pins = "sdc2_cmd"; 1005 bias-pull-up; 1006 drive-strength = <2>; 1007 }; 1008 1009 data { 1010 pins = "sdc2_data"; 1011 bias-pull-up; 1012 drive-strength = <2>; 1013 }; 1014 }; 1015 }; 1016 1017 adreno_gpu: gpu@5000000 { 1018 compatible = "qcom,adreno-508.0", "qcom,adreno"; 1019 1020 reg = <0x05000000 0x40000>; 1021 reg-names = "kgsl_3d0_reg_memory"; 1022 1023 interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>; 1024 1025 clocks = <&gcc GCC_GPU_CFG_AHB_CLK>, 1026 <&gpucc GPUCC_RBBMTIMER_CLK>, 1027 <&gcc GCC_BIMC_GFX_CLK>, 1028 <&gcc GCC_GPU_BIMC_GFX_CLK>, 1029 <&gpucc GPUCC_RBCPR_CLK>, 1030 <&gpucc GPUCC_GFX3D_CLK>; 1031 1032 clock-names = "iface", 1033 "rbbmtimer", 1034 "mem", 1035 "mem_iface", 1036 "rbcpr", 1037 "core"; 1038 1039 power-domains = <&rpmpd SDM660_VDDMX>; 1040 iommus = <&kgsl_smmu 0>; 1041 1042 nvmem-cells = <&gpu_speed_bin>; 1043 nvmem-cell-names = "speed_bin"; 1044 1045 interconnects = <&bimc MASTER_OXILI &bimc SLAVE_EBI>; 1046 interconnect-names = "gfx-mem"; 1047 1048 operating-points-v2 = <&gpu_sdm630_opp_table>; 1049 1050 status = "disabled"; 1051 1052 gpu_sdm630_opp_table: opp-table { 1053 compatible = "operating-points-v2"; 1054 opp-775000000 { 1055 opp-hz = /bits/ 64 <775000000>; 1056 opp-level = <RPM_SMD_LEVEL_TURBO>; 1057 opp-peak-kBps = <5412000>; 1058 opp-supported-hw = <0xA2>; 1059 }; 1060 opp-647000000 { 1061 opp-hz = /bits/ 64 <647000000>; 1062 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 1063 opp-peak-kBps = <4068000>; 1064 opp-supported-hw = <0xFF>; 1065 }; 1066 opp-588000000 { 1067 opp-hz = /bits/ 64 <588000000>; 1068 opp-level = <RPM_SMD_LEVEL_NOM>; 1069 opp-peak-kBps = <3072000>; 1070 opp-supported-hw = <0xFF>; 1071 }; 1072 opp-465000000 { 1073 opp-hz = /bits/ 64 <465000000>; 1074 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 1075 opp-peak-kBps = <2724000>; 1076 opp-supported-hw = <0xFF>; 1077 }; 1078 opp-370000000 { 1079 opp-hz = /bits/ 64 <370000000>; 1080 opp-level = <RPM_SMD_LEVEL_SVS>; 1081 opp-peak-kBps = <2188000>; 1082 opp-supported-hw = <0xFF>; 1083 }; 1084 opp-240000000 { 1085 opp-hz = /bits/ 64 <240000000>; 1086 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 1087 opp-peak-kBps = <1648000>; 1088 opp-supported-hw = <0xFF>; 1089 }; 1090 opp-160000000 { 1091 opp-hz = /bits/ 64 <160000000>; 1092 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 1093 opp-peak-kBps = <1200000>; 1094 opp-supported-hw = <0xFF>; 1095 }; 1096 }; 1097 }; 1098 1099 kgsl_smmu: iommu@5040000 { 1100 compatible = "qcom,sdm630-smmu-v2", 1101 "qcom,adreno-smmu", "qcom,smmu-v2"; 1102 reg = <0x05040000 0x10000>; 1103 1104 /* 1105 * GX GDSC parent is CX. We need to bring up CX for SMMU 1106 * but we need both up for Adreno. On the other hand, we 1107 * need to manage the GX rpmpd domain in the adreno driver. 1108 * Enable CX/GX GDSCs here so that we can manage just the GX 1109 * RPM Power Domain in the Adreno driver. 1110 */ 1111 power-domains = <&gpucc GPU_GX_GDSC>; 1112 clocks = <&gcc GCC_GPU_CFG_AHB_CLK>, 1113 <&gcc GCC_BIMC_GFX_CLK>, 1114 <&gcc GCC_GPU_BIMC_GFX_CLK>; 1115 clock-names = "iface", "mem", "mem_iface"; 1116 #global-interrupts = <2>; 1117 #iommu-cells = <1>; 1118 1119 interrupts = 1120 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 1121 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 1122 1123 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 1124 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 1125 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 1126 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 1127 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1128 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1129 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>, 1130 <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>; 1131 1132 status = "disabled"; 1133 }; 1134 1135 gpucc: clock-controller@5065000 { 1136 compatible = "qcom,gpucc-sdm630"; 1137 #clock-cells = <1>; 1138 #reset-cells = <1>; 1139 #power-domain-cells = <1>; 1140 reg = <0x05065000 0x9038>; 1141 1142 clocks = <&xo_board>, 1143 <&gcc GCC_GPU_GPLL0_CLK>, 1144 <&gcc GCC_GPU_GPLL0_DIV_CLK>; 1145 clock-names = "xo", 1146 "gcc_gpu_gpll0_clk", 1147 "gcc_gpu_gpll0_div_clk"; 1148 status = "disabled"; 1149 }; 1150 1151 lpass_smmu: iommu@5100000 { 1152 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2"; 1153 reg = <0x05100000 0x40000>; 1154 #iommu-cells = <1>; 1155 1156 #global-interrupts = <2>; 1157 interrupts = 1158 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 1159 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 1160 1161 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, 1162 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>, 1163 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>, 1164 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 1165 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 1166 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 1167 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 1168 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 1169 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 1170 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 1171 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 1172 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 1173 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 1174 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, 1175 <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>, 1176 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 1177 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>; 1178 1179 status = "disabled"; 1180 }; 1181 1182 sram@290000 { 1183 compatible = "qcom,rpm-stats"; 1184 reg = <0x00290000 0x10000>; 1185 }; 1186 1187 spmi_bus: spmi@800f000 { 1188 compatible = "qcom,spmi-pmic-arb"; 1189 reg = <0x0800f000 0x1000>, 1190 <0x08400000 0x1000000>, 1191 <0x09400000 0x1000000>, 1192 <0x0a400000 0x220000>, 1193 <0x0800a000 0x3000>; 1194 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1195 interrupt-names = "periph_irq"; 1196 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>; 1197 qcom,ee = <0>; 1198 qcom,channel = <0>; 1199 #address-cells = <2>; 1200 #size-cells = <0>; 1201 interrupt-controller; 1202 #interrupt-cells = <4>; 1203 cell-index = <0>; 1204 }; 1205 1206 usb3: usb@a8f8800 { 1207 compatible = "qcom,sdm660-dwc3", "qcom,dwc3"; 1208 reg = <0x0a8f8800 0x400>; 1209 status = "disabled"; 1210 #address-cells = <1>; 1211 #size-cells = <1>; 1212 ranges; 1213 1214 clocks = <&gcc GCC_CFG_NOC_USB3_AXI_CLK>, 1215 <&gcc GCC_USB30_MASTER_CLK>, 1216 <&gcc GCC_AGGRE2_USB3_AXI_CLK>, 1217 <&gcc GCC_USB30_SLEEP_CLK>, 1218 <&gcc GCC_USB30_MOCK_UTMI_CLK>, 1219 <&rpmcc RPM_SMD_AGGR2_NOC_CLK>; 1220 clock-names = "cfg_noc", 1221 "core", 1222 "iface", 1223 "sleep", 1224 "mock_utmi", 1225 "bus"; 1226 1227 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, 1228 <&gcc GCC_USB30_MASTER_CLK>, 1229 <&rpmcc RPM_SMD_AGGR2_NOC_CLK>; 1230 assigned-clock-rates = <19200000>, <120000000>, 1231 <19200000>; 1232 1233 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, 1234 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 1235 interrupt-names = "hs_phy_irq", "ss_phy_irq"; 1236 1237 power-domains = <&gcc USB_30_GDSC>; 1238 qcom,select-utmi-as-pipe-clk; 1239 1240 resets = <&gcc GCC_USB_30_BCR>; 1241 1242 usb3_dwc3: usb@a800000 { 1243 compatible = "snps,dwc3"; 1244 reg = <0x0a800000 0xc8d0>; 1245 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 1246 snps,dis_u2_susphy_quirk; 1247 snps,dis_enblslpm_quirk; 1248 1249 /* 1250 * SDM630 technically supports USB3 but I 1251 * haven't seen any devices making use of it. 1252 */ 1253 maximum-speed = "high-speed"; 1254 phys = <&qusb2phy0>; 1255 phy-names = "usb2-phy"; 1256 snps,hird-threshold = /bits/ 8 <0>; 1257 }; 1258 }; 1259 1260 qusb2phy0: phy@c012000 { 1261 compatible = "qcom,sdm660-qusb2-phy"; 1262 reg = <0x0c012000 0x180>; 1263 #phy-cells = <0>; 1264 1265 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 1266 <&gcc GCC_RX0_USB2_CLKREF_CLK>; 1267 clock-names = "cfg_ahb", "ref"; 1268 1269 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 1270 nvmem-cells = <&qusb2_hstx_trim>; 1271 status = "disabled"; 1272 }; 1273 1274 qusb2phy1: phy@c014000 { 1275 compatible = "qcom,sdm660-qusb2-phy"; 1276 reg = <0x0c014000 0x180>; 1277 #phy-cells = <0>; 1278 1279 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 1280 <&gcc GCC_RX1_USB2_CLKREF_CLK>; 1281 clock-names = "cfg_ahb", "ref"; 1282 1283 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 1284 nvmem-cells = <&qusb2_hstx_trim>; 1285 status = "disabled"; 1286 }; 1287 1288 sdhc_2: mmc@c084000 { 1289 compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5"; 1290 reg = <0x0c084000 0x1000>; 1291 reg-names = "hc"; 1292 1293 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1294 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 1295 interrupt-names = "hc_irq", "pwr_irq"; 1296 1297 bus-width = <4>; 1298 1299 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 1300 <&gcc GCC_SDCC2_APPS_CLK>, 1301 <&xo_board>; 1302 clock-names = "iface", "core", "xo"; 1303 1304 1305 interconnects = <&a2noc 3 &a2noc 10>, 1306 <&gnoc 0 &cnoc 28>; 1307 interconnect-names = "sdhc-ddr","cpu-sdhc"; 1308 operating-points-v2 = <&sdhc2_opp_table>; 1309 1310 pinctrl-names = "default", "sleep"; 1311 pinctrl-0 = <&sdc2_state_on>; 1312 pinctrl-1 = <&sdc2_state_off>; 1313 power-domains = <&rpmpd SDM660_VDDCX>; 1314 1315 status = "disabled"; 1316 1317 sdhc2_opp_table: opp-table { 1318 compatible = "operating-points-v2"; 1319 1320 opp-50000000 { 1321 opp-hz = /bits/ 64 <50000000>; 1322 required-opps = <&rpmpd_opp_low_svs>; 1323 opp-peak-kBps = <200000 140000>; 1324 opp-avg-kBps = <130718 133320>; 1325 }; 1326 opp-100000000 { 1327 opp-hz = /bits/ 64 <100000000>; 1328 required-opps = <&rpmpd_opp_svs>; 1329 opp-peak-kBps = <250000 160000>; 1330 opp-avg-kBps = <196078 150000>; 1331 }; 1332 opp-200000000 { 1333 opp-hz = /bits/ 64 <200000000>; 1334 required-opps = <&rpmpd_opp_nom>; 1335 opp-peak-kBps = <4096000 4096000>; 1336 opp-avg-kBps = <1338562 1338562>; 1337 }; 1338 }; 1339 }; 1340 1341 sdhc_1: mmc@c0c4000 { 1342 compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5"; 1343 reg = <0x0c0c4000 0x1000>, 1344 <0x0c0c5000 0x1000>, 1345 <0x0c0c8000 0x8000>; 1346 reg-names = "hc", "cqhci", "ice"; 1347 1348 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1349 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1350 interrupt-names = "hc_irq", "pwr_irq"; 1351 1352 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 1353 <&gcc GCC_SDCC1_APPS_CLK>, 1354 <&xo_board>, 1355 <&gcc GCC_SDCC1_ICE_CORE_CLK>; 1356 clock-names = "iface", "core", "xo", "ice"; 1357 1358 interconnects = <&a2noc 2 &a2noc 10>, 1359 <&gnoc 0 &cnoc 27>; 1360 interconnect-names = "sdhc-ddr", "cpu-sdhc"; 1361 operating-points-v2 = <&sdhc1_opp_table>; 1362 pinctrl-names = "default", "sleep"; 1363 pinctrl-0 = <&sdc1_state_on>; 1364 pinctrl-1 = <&sdc1_state_off>; 1365 power-domains = <&rpmpd SDM660_VDDCX>; 1366 1367 bus-width = <8>; 1368 non-removable; 1369 1370 status = "disabled"; 1371 1372 sdhc1_opp_table: opp-table { 1373 compatible = "operating-points-v2"; 1374 1375 opp-50000000 { 1376 opp-hz = /bits/ 64 <50000000>; 1377 required-opps = <&rpmpd_opp_low_svs>; 1378 opp-peak-kBps = <200000 140000>; 1379 opp-avg-kBps = <130718 133320>; 1380 }; 1381 opp-100000000 { 1382 opp-hz = /bits/ 64 <100000000>; 1383 required-opps = <&rpmpd_opp_svs>; 1384 opp-peak-kBps = <250000 160000>; 1385 opp-avg-kBps = <196078 150000>; 1386 }; 1387 opp-384000000 { 1388 opp-hz = /bits/ 64 <384000000>; 1389 required-opps = <&rpmpd_opp_nom>; 1390 opp-peak-kBps = <4096000 4096000>; 1391 opp-avg-kBps = <1338562 1338562>; 1392 }; 1393 }; 1394 }; 1395 1396 usb2: usb@c2f8800 { 1397 compatible = "qcom,sdm660-dwc3", "qcom,dwc3"; 1398 reg = <0x0c2f8800 0x400>; 1399 status = "disabled"; 1400 #address-cells = <1>; 1401 #size-cells = <1>; 1402 ranges; 1403 1404 clocks = <&gcc GCC_CFG_NOC_USB2_AXI_CLK>, 1405 <&gcc GCC_USB20_MASTER_CLK>, 1406 <&gcc GCC_USB20_MOCK_UTMI_CLK>, 1407 <&gcc GCC_USB20_SLEEP_CLK>; 1408 clock-names = "cfg_noc", "core", 1409 "mock_utmi", "sleep"; 1410 1411 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, 1412 <&gcc GCC_USB20_MASTER_CLK>; 1413 assigned-clock-rates = <19200000>, <60000000>; 1414 1415 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>; 1416 interrupt-names = "hs_phy_irq"; 1417 1418 qcom,select-utmi-as-pipe-clk; 1419 1420 resets = <&gcc GCC_USB_20_BCR>; 1421 1422 usb2_dwc3: usb@c200000 { 1423 compatible = "snps,dwc3"; 1424 reg = <0x0c200000 0xc8d0>; 1425 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 1426 snps,dis_u2_susphy_quirk; 1427 snps,dis_enblslpm_quirk; 1428 1429 /* This is the HS-only host */ 1430 maximum-speed = "high-speed"; 1431 phys = <&qusb2phy1>; 1432 phy-names = "usb2-phy"; 1433 snps,hird-threshold = /bits/ 8 <0>; 1434 }; 1435 }; 1436 1437 mmcc: clock-controller@c8c0000 { 1438 compatible = "qcom,mmcc-sdm630"; 1439 reg = <0x0c8c0000 0x40000>; 1440 #clock-cells = <1>; 1441 #reset-cells = <1>; 1442 #power-domain-cells = <1>; 1443 clock-names = "xo", 1444 "sleep_clk", 1445 "gpll0", 1446 "gpll0_div", 1447 "dsi0pll", 1448 "dsi0pllbyte", 1449 "dsi1pll", 1450 "dsi1pllbyte", 1451 "dp_link_2x_clk_divsel_five", 1452 "dp_vco_divided_clk_src_mux"; 1453 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 1454 <&sleep_clk>, 1455 <&gcc GCC_MMSS_GPLL0_CLK>, 1456 <&gcc GCC_MMSS_GPLL0_DIV_CLK>, 1457 <&dsi0_phy 1>, 1458 <&dsi0_phy 0>, 1459 <0>, 1460 <0>, 1461 <0>, 1462 <0>; 1463 }; 1464 1465 dsi_opp_table: opp-table-dsi { 1466 compatible = "operating-points-v2"; 1467 1468 opp-131250000 { 1469 opp-hz = /bits/ 64 <131250000>; 1470 required-opps = <&rpmpd_opp_svs>; 1471 }; 1472 1473 opp-210000000 { 1474 opp-hz = /bits/ 64 <210000000>; 1475 required-opps = <&rpmpd_opp_svs_plus>; 1476 }; 1477 1478 opp-262500000 { 1479 opp-hz = /bits/ 64 <262500000>; 1480 required-opps = <&rpmpd_opp_nom>; 1481 }; 1482 }; 1483 1484 mdss: mdss@c900000 { 1485 compatible = "qcom,mdss"; 1486 reg = <0x0c900000 0x1000>, 1487 <0x0c9b0000 0x1040>; 1488 reg-names = "mdss_phys", "vbif_phys"; 1489 1490 power-domains = <&mmcc MDSS_GDSC>; 1491 1492 clocks = <&mmcc MDSS_AHB_CLK>, 1493 <&mmcc MDSS_AXI_CLK>, 1494 <&mmcc MDSS_VSYNC_CLK>, 1495 <&mmcc MDSS_MDP_CLK>; 1496 clock-names = "iface", 1497 "bus", 1498 "vsync", 1499 "core"; 1500 1501 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 1502 1503 interrupt-controller; 1504 #interrupt-cells = <1>; 1505 1506 #address-cells = <1>; 1507 #size-cells = <1>; 1508 ranges; 1509 status = "disabled"; 1510 1511 mdp: mdp@c901000 { 1512 compatible = "qcom,mdp5"; 1513 reg = <0x0c901000 0x89000>; 1514 reg-names = "mdp_phys"; 1515 1516 interrupt-parent = <&mdss>; 1517 interrupts = <0>; 1518 1519 assigned-clocks = <&mmcc MDSS_MDP_CLK>, 1520 <&mmcc MDSS_VSYNC_CLK>; 1521 assigned-clock-rates = <300000000>, 1522 <19200000>; 1523 clocks = <&mmcc MDSS_AHB_CLK>, 1524 <&mmcc MDSS_AXI_CLK>, 1525 <&mmcc MDSS_MDP_CLK>, 1526 <&mmcc MDSS_VSYNC_CLK>; 1527 clock-names = "iface", 1528 "bus", 1529 "core", 1530 "vsync"; 1531 1532 interconnects = <&mnoc 2 &bimc 5>, 1533 <&mnoc 3 &bimc 5>, 1534 <&gnoc 0 &mnoc 17>; 1535 interconnect-names = "mdp0-mem", 1536 "mdp1-mem", 1537 "rotator-mem"; 1538 iommus = <&mmss_smmu 0>; 1539 operating-points-v2 = <&mdp_opp_table>; 1540 power-domains = <&rpmpd SDM660_VDDCX>; 1541 1542 ports { 1543 #address-cells = <1>; 1544 #size-cells = <0>; 1545 1546 port@0 { 1547 reg = <0>; 1548 mdp5_intf1_out: endpoint { 1549 remote-endpoint = <&dsi0_in>; 1550 }; 1551 }; 1552 }; 1553 1554 mdp_opp_table: opp-table { 1555 compatible = "operating-points-v2"; 1556 1557 opp-150000000 { 1558 opp-hz = /bits/ 64 <150000000>; 1559 opp-peak-kBps = <320000 320000 76800>; 1560 required-opps = <&rpmpd_opp_low_svs>; 1561 }; 1562 opp-275000000 { 1563 opp-hz = /bits/ 64 <275000000>; 1564 opp-peak-kBps = <6400000 6400000 160000>; 1565 required-opps = <&rpmpd_opp_svs>; 1566 }; 1567 opp-300000000 { 1568 opp-hz = /bits/ 64 <300000000>; 1569 opp-peak-kBps = <6400000 6400000 190000>; 1570 required-opps = <&rpmpd_opp_svs_plus>; 1571 }; 1572 opp-330000000 { 1573 opp-hz = /bits/ 64 <330000000>; 1574 opp-peak-kBps = <6400000 6400000 240000>; 1575 required-opps = <&rpmpd_opp_nom>; 1576 }; 1577 opp-412500000 { 1578 opp-hz = /bits/ 64 <412500000>; 1579 opp-peak-kBps = <6400000 6400000 320000>; 1580 required-opps = <&rpmpd_opp_turbo>; 1581 }; 1582 }; 1583 }; 1584 1585 dsi0: dsi@c994000 { 1586 compatible = "qcom,mdss-dsi-ctrl"; 1587 reg = <0x0c994000 0x400>; 1588 reg-names = "dsi_ctrl"; 1589 1590 operating-points-v2 = <&dsi_opp_table>; 1591 power-domains = <&rpmpd SDM660_VDDCX>; 1592 1593 interrupt-parent = <&mdss>; 1594 interrupts = <4>; 1595 1596 assigned-clocks = <&mmcc BYTE0_CLK_SRC>, 1597 <&mmcc PCLK0_CLK_SRC>; 1598 assigned-clock-parents = <&dsi0_phy 0>, 1599 <&dsi0_phy 1>; 1600 1601 clocks = <&mmcc MDSS_MDP_CLK>, 1602 <&mmcc MDSS_BYTE0_CLK>, 1603 <&mmcc MDSS_BYTE0_INTF_CLK>, 1604 <&mmcc MNOC_AHB_CLK>, 1605 <&mmcc MDSS_AHB_CLK>, 1606 <&mmcc MDSS_AXI_CLK>, 1607 <&mmcc MISC_AHB_CLK>, 1608 <&mmcc MDSS_PCLK0_CLK>, 1609 <&mmcc MDSS_ESC0_CLK>; 1610 clock-names = "mdp_core", 1611 "byte", 1612 "byte_intf", 1613 "mnoc", 1614 "iface", 1615 "bus", 1616 "core_mmss", 1617 "pixel", 1618 "core"; 1619 1620 phys = <&dsi0_phy>; 1621 1622 status = "disabled"; 1623 1624 ports { 1625 #address-cells = <1>; 1626 #size-cells = <0>; 1627 1628 port@0 { 1629 reg = <0>; 1630 dsi0_in: endpoint { 1631 remote-endpoint = <&mdp5_intf1_out>; 1632 }; 1633 }; 1634 1635 port@1 { 1636 reg = <1>; 1637 dsi0_out: endpoint { 1638 }; 1639 }; 1640 }; 1641 }; 1642 1643 dsi0_phy: phy@c994400 { 1644 compatible = "qcom,dsi-phy-14nm-660"; 1645 reg = <0x0c994400 0x100>, 1646 <0x0c994500 0x300>, 1647 <0x0c994800 0x188>; 1648 reg-names = "dsi_phy", 1649 "dsi_phy_lane", 1650 "dsi_pll"; 1651 1652 #clock-cells = <1>; 1653 #phy-cells = <0>; 1654 1655 clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>; 1656 clock-names = "iface", "ref"; 1657 status = "disabled"; 1658 }; 1659 }; 1660 1661 blsp1_dma: dma-controller@c144000 { 1662 compatible = "qcom,bam-v1.7.0"; 1663 reg = <0x0c144000 0x1f000>; 1664 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 1665 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 1666 clock-names = "bam_clk"; 1667 #dma-cells = <1>; 1668 qcom,ee = <0>; 1669 qcom,controlled-remotely; 1670 num-channels = <18>; 1671 qcom,num-ees = <4>; 1672 }; 1673 1674 blsp1_uart1: serial@c16f000 { 1675 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1676 reg = <0x0c16f000 0x200>; 1677 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1678 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, 1679 <&gcc GCC_BLSP1_AHB_CLK>; 1680 clock-names = "core", "iface"; 1681 dmas = <&blsp1_dma 0>, <&blsp1_dma 1>; 1682 dma-names = "tx", "rx"; 1683 pinctrl-names = "default", "sleep"; 1684 pinctrl-0 = <&blsp1_uart1_default>; 1685 pinctrl-1 = <&blsp1_uart1_sleep>; 1686 status = "disabled"; 1687 }; 1688 1689 blsp1_uart2: serial@c170000 { 1690 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1691 reg = <0x0c170000 0x1000>; 1692 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1693 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, 1694 <&gcc GCC_BLSP1_AHB_CLK>; 1695 clock-names = "core", "iface"; 1696 dmas = <&blsp1_dma 2>, <&blsp1_dma 3>; 1697 dma-names = "tx", "rx"; 1698 pinctrl-names = "default"; 1699 pinctrl-0 = <&blsp1_uart2_default>; 1700 status = "disabled"; 1701 }; 1702 1703 blsp_i2c1: i2c@c175000 { 1704 compatible = "qcom,i2c-qup-v2.2.1"; 1705 reg = <0x0c175000 0x600>; 1706 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1707 1708 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, 1709 <&gcc GCC_BLSP1_AHB_CLK>; 1710 clock-names = "core", "iface"; 1711 clock-frequency = <400000>; 1712 dmas = <&blsp1_dma 4>, <&blsp1_dma 5>; 1713 dma-names = "tx", "rx"; 1714 1715 pinctrl-names = "default", "sleep"; 1716 pinctrl-0 = <&i2c1_default>; 1717 pinctrl-1 = <&i2c1_sleep>; 1718 #address-cells = <1>; 1719 #size-cells = <0>; 1720 status = "disabled"; 1721 }; 1722 1723 blsp_i2c2: i2c@c176000 { 1724 compatible = "qcom,i2c-qup-v2.2.1"; 1725 reg = <0x0c176000 0x600>; 1726 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1727 1728 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 1729 <&gcc GCC_BLSP1_AHB_CLK>; 1730 clock-names = "core", "iface"; 1731 clock-frequency = <400000>; 1732 dmas = <&blsp1_dma 6>, <&blsp1_dma 7>; 1733 dma-names = "tx", "rx"; 1734 1735 pinctrl-names = "default", "sleep"; 1736 pinctrl-0 = <&i2c2_default>; 1737 pinctrl-1 = <&i2c2_sleep>; 1738 #address-cells = <1>; 1739 #size-cells = <0>; 1740 status = "disabled"; 1741 }; 1742 1743 blsp_i2c3: i2c@c177000 { 1744 compatible = "qcom,i2c-qup-v2.2.1"; 1745 reg = <0x0c177000 0x600>; 1746 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1747 1748 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 1749 <&gcc GCC_BLSP1_AHB_CLK>; 1750 clock-names = "core", "iface"; 1751 clock-frequency = <400000>; 1752 dmas = <&blsp1_dma 8>, <&blsp1_dma 9>; 1753 dma-names = "tx", "rx"; 1754 1755 pinctrl-names = "default", "sleep"; 1756 pinctrl-0 = <&i2c3_default>; 1757 pinctrl-1 = <&i2c3_sleep>; 1758 #address-cells = <1>; 1759 #size-cells = <0>; 1760 status = "disabled"; 1761 }; 1762 1763 blsp_i2c4: i2c@c178000 { 1764 compatible = "qcom,i2c-qup-v2.2.1"; 1765 reg = <0x0c178000 0x600>; 1766 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1767 1768 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, 1769 <&gcc GCC_BLSP1_AHB_CLK>; 1770 clock-names = "core", "iface"; 1771 clock-frequency = <400000>; 1772 dmas = <&blsp1_dma 10>, <&blsp1_dma 11>; 1773 dma-names = "tx", "rx"; 1774 1775 pinctrl-names = "default", "sleep"; 1776 pinctrl-0 = <&i2c4_default>; 1777 pinctrl-1 = <&i2c4_sleep>; 1778 #address-cells = <1>; 1779 #size-cells = <0>; 1780 status = "disabled"; 1781 }; 1782 1783 blsp2_dma: dma-controller@c184000 { 1784 compatible = "qcom,bam-v1.7.0"; 1785 reg = <0x0c184000 0x1f000>; 1786 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 1787 clocks = <&gcc GCC_BLSP2_AHB_CLK>; 1788 clock-names = "bam_clk"; 1789 #dma-cells = <1>; 1790 qcom,ee = <0>; 1791 qcom,controlled-remotely; 1792 num-channels = <18>; 1793 qcom,num-ees = <4>; 1794 }; 1795 1796 blsp2_uart1: serial@c1af000 { 1797 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1798 reg = <0x0c1af000 0x200>; 1799 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 1800 clocks = <&gcc GCC_BLSP2_UART1_APPS_CLK>, 1801 <&gcc GCC_BLSP2_AHB_CLK>; 1802 clock-names = "core", "iface"; 1803 dmas = <&blsp2_dma 0>, <&blsp2_dma 1>; 1804 dma-names = "tx", "rx"; 1805 pinctrl-names = "default", "sleep"; 1806 pinctrl-0 = <&blsp2_uart1_default>; 1807 pinctrl-1 = <&blsp2_uart1_sleep>; 1808 status = "disabled"; 1809 }; 1810 1811 blsp_i2c5: i2c@c1b5000 { 1812 compatible = "qcom,i2c-qup-v2.2.1"; 1813 reg = <0x0c1b5000 0x600>; 1814 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 1815 1816 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, 1817 <&gcc GCC_BLSP2_AHB_CLK>; 1818 clock-names = "core", "iface"; 1819 clock-frequency = <400000>; 1820 dmas = <&blsp2_dma 4>, <&blsp2_dma 5>; 1821 dma-names = "tx", "rx"; 1822 1823 pinctrl-names = "default", "sleep"; 1824 pinctrl-0 = <&i2c5_default>; 1825 pinctrl-1 = <&i2c5_sleep>; 1826 #address-cells = <1>; 1827 #size-cells = <0>; 1828 status = "disabled"; 1829 }; 1830 1831 blsp_i2c6: i2c@c1b6000 { 1832 compatible = "qcom,i2c-qup-v2.2.1"; 1833 reg = <0x0c1b6000 0x600>; 1834 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 1835 1836 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, 1837 <&gcc GCC_BLSP2_AHB_CLK>; 1838 clock-names = "core", "iface"; 1839 clock-frequency = <400000>; 1840 dmas = <&blsp2_dma 6>, <&blsp2_dma 7>; 1841 dma-names = "tx", "rx"; 1842 1843 pinctrl-names = "default", "sleep"; 1844 pinctrl-0 = <&i2c6_default>; 1845 pinctrl-1 = <&i2c6_sleep>; 1846 #address-cells = <1>; 1847 #size-cells = <0>; 1848 status = "disabled"; 1849 }; 1850 1851 blsp_i2c7: i2c@c1b7000 { 1852 compatible = "qcom,i2c-qup-v2.2.1"; 1853 reg = <0x0c1b7000 0x600>; 1854 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 1855 1856 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>, 1857 <&gcc GCC_BLSP2_AHB_CLK>; 1858 clock-names = "core", "iface"; 1859 clock-frequency = <400000>; 1860 dmas = <&blsp2_dma 8>, <&blsp2_dma 9>; 1861 dma-names = "tx", "rx"; 1862 1863 pinctrl-names = "default", "sleep"; 1864 pinctrl-0 = <&i2c7_default>; 1865 pinctrl-1 = <&i2c7_sleep>; 1866 #address-cells = <1>; 1867 #size-cells = <0>; 1868 status = "disabled"; 1869 }; 1870 1871 blsp_i2c8: i2c@c1b8000 { 1872 compatible = "qcom,i2c-qup-v2.2.1"; 1873 reg = <0x0c1b8000 0x600>; 1874 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 1875 1876 clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>, 1877 <&gcc GCC_BLSP2_AHB_CLK>; 1878 clock-names = "core", "iface"; 1879 clock-frequency = <400000>; 1880 dmas = <&blsp2_dma 10>, <&blsp2_dma 11>; 1881 dma-names = "tx", "rx"; 1882 1883 pinctrl-names = "default", "sleep"; 1884 pinctrl-0 = <&i2c8_default>; 1885 pinctrl-1 = <&i2c8_sleep>; 1886 #address-cells = <1>; 1887 #size-cells = <0>; 1888 status = "disabled"; 1889 }; 1890 1891 sram@146bf000 { 1892 compatible = "qcom,sdm630-imem", "syscon", "simple-mfd"; 1893 reg = <0x146bf000 0x1000>; 1894 1895 #address-cells = <1>; 1896 #size-cells = <1>; 1897 1898 ranges = <0 0x146bf000 0x1000>; 1899 1900 pil-reloc@94c { 1901 compatible = "qcom,pil-reloc-info"; 1902 reg = <0x94c 0xc8>; 1903 }; 1904 }; 1905 1906 camss: camss@ca00000 { 1907 compatible = "qcom,sdm660-camss"; 1908 reg = <0x0ca00020 0x10>, 1909 <0x0ca30000 0x100>, 1910 <0x0ca30400 0x100>, 1911 <0x0ca30800 0x100>, 1912 <0x0ca30c00 0x100>, 1913 <0x0c824000 0x1000>, 1914 <0x0ca00120 0x4>, 1915 <0x0c825000 0x1000>, 1916 <0x0ca00124 0x4>, 1917 <0x0c826000 0x1000>, 1918 <0x0ca00128 0x4>, 1919 <0x0ca31000 0x500>, 1920 <0x0ca10000 0x1000>, 1921 <0x0ca14000 0x1000>; 1922 reg-names = "csi_clk_mux", 1923 "csid0", 1924 "csid1", 1925 "csid2", 1926 "csid3", 1927 "csiphy0", 1928 "csiphy0_clk_mux", 1929 "csiphy1", 1930 "csiphy1_clk_mux", 1931 "csiphy2", 1932 "csiphy2_clk_mux", 1933 "ispif", 1934 "vfe0", 1935 "vfe1"; 1936 interrupts = <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>, 1937 <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>, 1938 <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>, 1939 <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>, 1940 <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>, 1941 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>, 1942 <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>, 1943 <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>, 1944 <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>, 1945 <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>; 1946 interrupt-names = "csid0", 1947 "csid1", 1948 "csid2", 1949 "csid3", 1950 "csiphy0", 1951 "csiphy1", 1952 "csiphy2", 1953 "ispif", 1954 "vfe0", 1955 "vfe1"; 1956 clocks = <&mmcc CAMSS_AHB_CLK>, 1957 <&mmcc CAMSS_CPHY_CSID0_CLK>, 1958 <&mmcc CAMSS_CPHY_CSID1_CLK>, 1959 <&mmcc CAMSS_CPHY_CSID2_CLK>, 1960 <&mmcc CAMSS_CPHY_CSID3_CLK>, 1961 <&mmcc CAMSS_CSI0_AHB_CLK>, 1962 <&mmcc CAMSS_CSI0_CLK>, 1963 <&mmcc CAMSS_CPHY_CSID0_CLK>, 1964 <&mmcc CAMSS_CSI0PIX_CLK>, 1965 <&mmcc CAMSS_CSI0RDI_CLK>, 1966 <&mmcc CAMSS_CSI1_AHB_CLK>, 1967 <&mmcc CAMSS_CSI1_CLK>, 1968 <&mmcc CAMSS_CPHY_CSID1_CLK>, 1969 <&mmcc CAMSS_CSI1PIX_CLK>, 1970 <&mmcc CAMSS_CSI1RDI_CLK>, 1971 <&mmcc CAMSS_CSI2_AHB_CLK>, 1972 <&mmcc CAMSS_CSI2_CLK>, 1973 <&mmcc CAMSS_CPHY_CSID2_CLK>, 1974 <&mmcc CAMSS_CSI2PIX_CLK>, 1975 <&mmcc CAMSS_CSI2RDI_CLK>, 1976 <&mmcc CAMSS_CSI3_AHB_CLK>, 1977 <&mmcc CAMSS_CSI3_CLK>, 1978 <&mmcc CAMSS_CPHY_CSID3_CLK>, 1979 <&mmcc CAMSS_CSI3PIX_CLK>, 1980 <&mmcc CAMSS_CSI3RDI_CLK>, 1981 <&mmcc CAMSS_CSI0PHYTIMER_CLK>, 1982 <&mmcc CAMSS_CSI1PHYTIMER_CLK>, 1983 <&mmcc CAMSS_CSI2PHYTIMER_CLK>, 1984 <&mmcc CSIPHY_AHB2CRIF_CLK>, 1985 <&mmcc CAMSS_CSI_VFE0_CLK>, 1986 <&mmcc CAMSS_CSI_VFE1_CLK>, 1987 <&mmcc CAMSS_ISPIF_AHB_CLK>, 1988 <&mmcc THROTTLE_CAMSS_AXI_CLK>, 1989 <&mmcc CAMSS_TOP_AHB_CLK>, 1990 <&mmcc CAMSS_VFE0_AHB_CLK>, 1991 <&mmcc CAMSS_VFE0_CLK>, 1992 <&mmcc CAMSS_VFE0_STREAM_CLK>, 1993 <&mmcc CAMSS_VFE1_AHB_CLK>, 1994 <&mmcc CAMSS_VFE1_CLK>, 1995 <&mmcc CAMSS_VFE1_STREAM_CLK>, 1996 <&mmcc CAMSS_VFE_VBIF_AHB_CLK>, 1997 <&mmcc CAMSS_VFE_VBIF_AXI_CLK>; 1998 clock-names = "ahb", 1999 "cphy_csid0", 2000 "cphy_csid1", 2001 "cphy_csid2", 2002 "cphy_csid3", 2003 "csi0_ahb", 2004 "csi0", 2005 "csi0_phy", 2006 "csi0_pix", 2007 "csi0_rdi", 2008 "csi1_ahb", 2009 "csi1", 2010 "csi1_phy", 2011 "csi1_pix", 2012 "csi1_rdi", 2013 "csi2_ahb", 2014 "csi2", 2015 "csi2_phy", 2016 "csi2_pix", 2017 "csi2_rdi", 2018 "csi3_ahb", 2019 "csi3", 2020 "csi3_phy", 2021 "csi3_pix", 2022 "csi3_rdi", 2023 "csiphy0_timer", 2024 "csiphy1_timer", 2025 "csiphy2_timer", 2026 "csiphy_ahb2crif", 2027 "csi_vfe0", 2028 "csi_vfe1", 2029 "ispif_ahb", 2030 "throttle_axi", 2031 "top_ahb", 2032 "vfe0_ahb", 2033 "vfe0", 2034 "vfe0_stream", 2035 "vfe1_ahb", 2036 "vfe1", 2037 "vfe1_stream", 2038 "vfe_ahb", 2039 "vfe_axi"; 2040 interconnects = <&mnoc 5 &bimc 5>; 2041 interconnect-names = "vfe-mem"; 2042 iommus = <&mmss_smmu 0xc00>, 2043 <&mmss_smmu 0xc01>, 2044 <&mmss_smmu 0xc02>, 2045 <&mmss_smmu 0xc03>; 2046 power-domains = <&mmcc CAMSS_VFE0_GDSC>, 2047 <&mmcc CAMSS_VFE1_GDSC>; 2048 status = "disabled"; 2049 2050 ports { 2051 #address-cells = <1>; 2052 #size-cells = <0>; 2053 }; 2054 }; 2055 2056 cci: cci@ca0c000 { 2057 compatible = "qcom,msm8996-cci"; 2058 #address-cells = <1>; 2059 #size-cells = <0>; 2060 reg = <0x0ca0c000 0x1000>; 2061 interrupts = <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>; 2062 2063 assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>, 2064 <&mmcc CAMSS_CCI_CLK>; 2065 assigned-clock-rates = <80800000>, <37500000>; 2066 clocks = <&mmcc CAMSS_TOP_AHB_CLK>, 2067 <&mmcc CAMSS_CCI_AHB_CLK>, 2068 <&mmcc CAMSS_CCI_CLK>, 2069 <&mmcc CAMSS_AHB_CLK>; 2070 clock-names = "camss_top_ahb", 2071 "cci_ahb", 2072 "cci", 2073 "camss_ahb"; 2074 2075 pinctrl-names = "default"; 2076 pinctrl-0 = <&cci0_default &cci1_default>; 2077 power-domains = <&mmcc CAMSS_TOP_GDSC>; 2078 status = "disabled"; 2079 2080 cci_i2c0: i2c-bus@0 { 2081 reg = <0>; 2082 clock-frequency = <400000>; 2083 #address-cells = <1>; 2084 #size-cells = <0>; 2085 }; 2086 2087 cci_i2c1: i2c-bus@1 { 2088 reg = <1>; 2089 clock-frequency = <400000>; 2090 #address-cells = <1>; 2091 #size-cells = <0>; 2092 }; 2093 }; 2094 2095 venus: video-codec@cc00000 { 2096 compatible = "qcom,sdm660-venus"; 2097 reg = <0x0cc00000 0xff000>; 2098 clocks = <&mmcc VIDEO_CORE_CLK>, 2099 <&mmcc VIDEO_AHB_CLK>, 2100 <&mmcc VIDEO_AXI_CLK>, 2101 <&mmcc THROTTLE_VIDEO_AXI_CLK>; 2102 clock-names = "core", "iface", "bus", "bus_throttle"; 2103 interconnects = <&gnoc 0 &mnoc 13>, 2104 <&mnoc 4 &bimc 5>; 2105 interconnect-names = "cpu-cfg", "video-mem"; 2106 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 2107 iommus = <&mmss_smmu 0x400>, 2108 <&mmss_smmu 0x401>, 2109 <&mmss_smmu 0x40a>, 2110 <&mmss_smmu 0x407>, 2111 <&mmss_smmu 0x40e>, 2112 <&mmss_smmu 0x40f>, 2113 <&mmss_smmu 0x408>, 2114 <&mmss_smmu 0x409>, 2115 <&mmss_smmu 0x40b>, 2116 <&mmss_smmu 0x40c>, 2117 <&mmss_smmu 0x40d>, 2118 <&mmss_smmu 0x410>, 2119 <&mmss_smmu 0x421>, 2120 <&mmss_smmu 0x428>, 2121 <&mmss_smmu 0x429>, 2122 <&mmss_smmu 0x42b>, 2123 <&mmss_smmu 0x42c>, 2124 <&mmss_smmu 0x42d>, 2125 <&mmss_smmu 0x411>, 2126 <&mmss_smmu 0x431>; 2127 memory-region = <&venus_region>; 2128 power-domains = <&mmcc VENUS_GDSC>; 2129 status = "disabled"; 2130 2131 video-decoder { 2132 compatible = "venus-decoder"; 2133 clocks = <&mmcc VIDEO_SUBCORE0_CLK>; 2134 clock-names = "vcodec0_core"; 2135 power-domains = <&mmcc VENUS_CORE0_GDSC>; 2136 }; 2137 2138 video-encoder { 2139 compatible = "venus-encoder"; 2140 clocks = <&mmcc VIDEO_SUBCORE0_CLK>; 2141 clock-names = "vcodec0_core"; 2142 power-domains = <&mmcc VENUS_CORE0_GDSC>; 2143 }; 2144 }; 2145 2146 mmss_smmu: iommu@cd00000 { 2147 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2"; 2148 reg = <0x0cd00000 0x40000>; 2149 2150 clocks = <&mmcc MNOC_AHB_CLK>, 2151 <&mmcc BIMC_SMMU_AHB_CLK>, 2152 <&rpmcc RPM_SMD_MMSSNOC_AXI_CLK>, 2153 <&mmcc BIMC_SMMU_AXI_CLK>; 2154 clock-names = "iface-mm", "iface-smmu", 2155 "bus-mm", "bus-smmu"; 2156 #global-interrupts = <2>; 2157 #iommu-cells = <1>; 2158 2159 interrupts = 2160 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 2161 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 2162 2163 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 2164 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 2165 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, 2166 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 2167 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 2168 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 2169 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 2170 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 2171 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 2172 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 2173 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 2174 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 2175 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 2176 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 2177 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 2178 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 2179 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 2180 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 2181 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 2182 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, 2183 <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, 2184 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 2185 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 2186 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>; 2187 2188 status = "disabled"; 2189 }; 2190 2191 adsp_pil: remoteproc@15700000 { 2192 compatible = "qcom,sdm660-adsp-pas"; 2193 reg = <0x15700000 0x4040>; 2194 2195 interrupts-extended = 2196 <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 2197 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2198 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2199 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2200 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2201 interrupt-names = "wdog", "fatal", "ready", 2202 "handover", "stop-ack"; 2203 2204 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 2205 clock-names = "xo"; 2206 2207 memory-region = <&adsp_region>; 2208 power-domains = <&rpmpd SDM660_VDDCX>; 2209 power-domain-names = "cx"; 2210 2211 qcom,smem-states = <&adsp_smp2p_out 0>; 2212 qcom,smem-state-names = "stop"; 2213 2214 glink-edge { 2215 interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>; 2216 2217 label = "lpass"; 2218 mboxes = <&apcs_glb 9>; 2219 qcom,remote-pid = <2>; 2220 2221 apr { 2222 compatible = "qcom,apr-v2"; 2223 qcom,glink-channels = "apr_audio_svc"; 2224 qcom,domain = <APR_DOMAIN_ADSP>; 2225 #address-cells = <1>; 2226 #size-cells = <0>; 2227 2228 service@3 { 2229 reg = <APR_SVC_ADSP_CORE>; 2230 compatible = "qcom,q6core"; 2231 }; 2232 2233 q6afe: service@4 { 2234 compatible = "qcom,q6afe"; 2235 reg = <APR_SVC_AFE>; 2236 q6afedai: dais { 2237 compatible = "qcom,q6afe-dais"; 2238 #address-cells = <1>; 2239 #size-cells = <0>; 2240 #sound-dai-cells = <1>; 2241 }; 2242 }; 2243 2244 q6asm: service@7 { 2245 compatible = "qcom,q6asm"; 2246 reg = <APR_SVC_ASM>; 2247 q6asmdai: dais { 2248 compatible = "qcom,q6asm-dais"; 2249 #address-cells = <1>; 2250 #size-cells = <0>; 2251 #sound-dai-cells = <1>; 2252 iommus = <&lpass_smmu 1>; 2253 }; 2254 }; 2255 2256 q6adm: service@8 { 2257 compatible = "qcom,q6adm"; 2258 reg = <APR_SVC_ADM>; 2259 q6routing: routing { 2260 compatible = "qcom,q6adm-routing"; 2261 #sound-dai-cells = <0>; 2262 }; 2263 }; 2264 }; 2265 }; 2266 }; 2267 2268 gnoc: interconnect@17900000 { 2269 compatible = "qcom,sdm660-gnoc"; 2270 reg = <0x17900000 0xe000>; 2271 #interconnect-cells = <1>; 2272 /* 2273 * This one apparently features no clocks, 2274 * so let's not mess with the driver needlessly 2275 */ 2276 clock-names = "bus", "bus_a"; 2277 clocks = <&xo_board>, <&xo_board>; 2278 }; 2279 2280 apcs_glb: mailbox@17911000 { 2281 compatible = "qcom,sdm660-apcs-hmss-global"; 2282 reg = <0x17911000 0x1000>; 2283 2284 #mbox-cells = <1>; 2285 }; 2286 2287 timer@17920000 { 2288 #address-cells = <1>; 2289 #size-cells = <1>; 2290 ranges; 2291 compatible = "arm,armv7-timer-mem"; 2292 reg = <0x17920000 0x1000>; 2293 clock-frequency = <19200000>; 2294 2295 frame@17921000 { 2296 frame-number = <0>; 2297 interrupts = <0 8 0x4>, 2298 <0 7 0x4>; 2299 reg = <0x17921000 0x1000>, 2300 <0x17922000 0x1000>; 2301 }; 2302 2303 frame@17923000 { 2304 frame-number = <1>; 2305 interrupts = <0 9 0x4>; 2306 reg = <0x17923000 0x1000>; 2307 status = "disabled"; 2308 }; 2309 2310 frame@17924000 { 2311 frame-number = <2>; 2312 interrupts = <0 10 0x4>; 2313 reg = <0x17924000 0x1000>; 2314 status = "disabled"; 2315 }; 2316 2317 frame@17925000 { 2318 frame-number = <3>; 2319 interrupts = <0 11 0x4>; 2320 reg = <0x17925000 0x1000>; 2321 status = "disabled"; 2322 }; 2323 2324 frame@17926000 { 2325 frame-number = <4>; 2326 interrupts = <0 12 0x4>; 2327 reg = <0x17926000 0x1000>; 2328 status = "disabled"; 2329 }; 2330 2331 frame@17927000 { 2332 frame-number = <5>; 2333 interrupts = <0 13 0x4>; 2334 reg = <0x17927000 0x1000>; 2335 status = "disabled"; 2336 }; 2337 2338 frame@17928000 { 2339 frame-number = <6>; 2340 interrupts = <0 14 0x4>; 2341 reg = <0x17928000 0x1000>; 2342 status = "disabled"; 2343 }; 2344 }; 2345 2346 intc: interrupt-controller@17a00000 { 2347 compatible = "arm,gic-v3"; 2348 reg = <0x17a00000 0x10000>, /* GICD */ 2349 <0x17b00000 0x100000>; /* GICR * 8 */ 2350 #interrupt-cells = <3>; 2351 #address-cells = <1>; 2352 #size-cells = <1>; 2353 ranges; 2354 interrupt-controller; 2355 #redistributor-regions = <1>; 2356 redistributor-stride = <0x0 0x20000>; 2357 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 2358 }; 2359 }; 2360 2361 sound: sound { 2362 }; 2363 2364 thermal-zones { 2365 aoss-thermal { 2366 polling-delay-passive = <250>; 2367 polling-delay = <1000>; 2368 2369 thermal-sensors = <&tsens 0>; 2370 2371 trips { 2372 aoss_alert0: trip-point0 { 2373 temperature = <105000>; 2374 hysteresis = <1000>; 2375 type = "hot"; 2376 }; 2377 }; 2378 }; 2379 2380 cpuss0-thermal { 2381 polling-delay-passive = <250>; 2382 polling-delay = <1000>; 2383 2384 thermal-sensors = <&tsens 1>; 2385 2386 trips { 2387 cpuss0_alert0: trip-point0 { 2388 temperature = <125000>; 2389 hysteresis = <1000>; 2390 type = "hot"; 2391 }; 2392 }; 2393 }; 2394 2395 cpuss1-thermal { 2396 polling-delay-passive = <250>; 2397 polling-delay = <1000>; 2398 2399 thermal-sensors = <&tsens 2>; 2400 2401 trips { 2402 cpuss1_alert0: trip-point0 { 2403 temperature = <125000>; 2404 hysteresis = <1000>; 2405 type = "hot"; 2406 }; 2407 }; 2408 }; 2409 2410 cpu0-thermal { 2411 polling-delay-passive = <250>; 2412 polling-delay = <1000>; 2413 2414 thermal-sensors = <&tsens 3>; 2415 2416 trips { 2417 cpu0_alert0: trip-point0 { 2418 temperature = <70000>; 2419 hysteresis = <1000>; 2420 type = "passive"; 2421 }; 2422 2423 cpu0_crit: cpu_crit { 2424 temperature = <110000>; 2425 hysteresis = <1000>; 2426 type = "critical"; 2427 }; 2428 }; 2429 }; 2430 2431 cpu1-thermal { 2432 polling-delay-passive = <250>; 2433 polling-delay = <1000>; 2434 2435 thermal-sensors = <&tsens 4>; 2436 2437 trips { 2438 cpu1_alert0: trip-point0 { 2439 temperature = <70000>; 2440 hysteresis = <1000>; 2441 type = "passive"; 2442 }; 2443 2444 cpu1_crit: cpu_crit { 2445 temperature = <110000>; 2446 hysteresis = <1000>; 2447 type = "critical"; 2448 }; 2449 }; 2450 }; 2451 2452 cpu2-thermal { 2453 polling-delay-passive = <250>; 2454 polling-delay = <1000>; 2455 2456 thermal-sensors = <&tsens 5>; 2457 2458 trips { 2459 cpu2_alert0: trip-point0 { 2460 temperature = <70000>; 2461 hysteresis = <1000>; 2462 type = "passive"; 2463 }; 2464 2465 cpu2_crit: cpu_crit { 2466 temperature = <110000>; 2467 hysteresis = <1000>; 2468 type = "critical"; 2469 }; 2470 }; 2471 }; 2472 2473 cpu3-thermal { 2474 polling-delay-passive = <250>; 2475 polling-delay = <1000>; 2476 2477 thermal-sensors = <&tsens 6>; 2478 2479 trips { 2480 cpu3_alert0: trip-point0 { 2481 temperature = <70000>; 2482 hysteresis = <1000>; 2483 type = "passive"; 2484 }; 2485 2486 cpu3_crit: cpu_crit { 2487 temperature = <110000>; 2488 hysteresis = <1000>; 2489 type = "critical"; 2490 }; 2491 }; 2492 }; 2493 2494 /* 2495 * According to what downstream DTS says, 2496 * the entire power efficient cluster has 2497 * only a single thermal sensor. 2498 */ 2499 2500 pwr-cluster-thermal { 2501 polling-delay-passive = <250>; 2502 polling-delay = <1000>; 2503 2504 thermal-sensors = <&tsens 7>; 2505 2506 trips { 2507 pwr_cluster_alert0: trip-point0 { 2508 temperature = <70000>; 2509 hysteresis = <1000>; 2510 type = "passive"; 2511 }; 2512 2513 pwr_cluster_crit: cpu_crit { 2514 temperature = <110000>; 2515 hysteresis = <1000>; 2516 type = "critical"; 2517 }; 2518 }; 2519 }; 2520 2521 gpu-thermal { 2522 polling-delay-passive = <250>; 2523 polling-delay = <1000>; 2524 2525 thermal-sensors = <&tsens 8>; 2526 2527 trips { 2528 gpu_alert0: trip-point0 { 2529 temperature = <90000>; 2530 hysteresis = <1000>; 2531 type = "hot"; 2532 }; 2533 }; 2534 }; 2535 }; 2536 2537 timer { 2538 compatible = "arm,armv8-timer"; 2539 interrupts = <GIC_PPI 1 0xf08>, 2540 <GIC_PPI 2 0xf08>, 2541 <GIC_PPI 3 0xf08>, 2542 <GIC_PPI 0 0xf08>; 2543 }; 2544}; 2545 2546