1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2020, Konrad Dybcio <konradybcio@gmail.com> 4 * Copyright (c) 2020, AngeloGioacchino Del Regno <kholk11@gmail.com> 5 */ 6 7#include <dt-bindings/clock/qcom,gcc-sdm660.h> 8#include <dt-bindings/clock/qcom,gpucc-sdm660.h> 9#include <dt-bindings/clock/qcom,mmcc-sdm660.h> 10#include <dt-bindings/clock/qcom,rpmcc.h> 11#include <dt-bindings/interconnect/qcom,sdm660.h> 12#include <dt-bindings/power/qcom-rpmpd.h> 13#include <dt-bindings/gpio/gpio.h> 14#include <dt-bindings/interrupt-controller/arm-gic.h> 15#include <dt-bindings/soc/qcom,apr.h> 16 17/ { 18 interrupt-parent = <&intc>; 19 20 #address-cells = <2>; 21 #size-cells = <2>; 22 23 aliases { 24 mmc1 = &sdhc_1; 25 mmc2 = &sdhc_2; 26 }; 27 28 chosen { }; 29 30 clocks { 31 xo_board: xo-board { 32 compatible = "fixed-clock"; 33 #clock-cells = <0>; 34 clock-frequency = <19200000>; 35 clock-output-names = "xo_board"; 36 }; 37 38 sleep_clk: sleep-clk { 39 compatible = "fixed-clock"; 40 #clock-cells = <0>; 41 clock-frequency = <32764>; 42 clock-output-names = "sleep_clk"; 43 }; 44 }; 45 46 cpus { 47 #address-cells = <2>; 48 #size-cells = <0>; 49 50 CPU0: cpu@100 { 51 device_type = "cpu"; 52 compatible = "arm,cortex-a53"; 53 reg = <0x0 0x100>; 54 enable-method = "psci"; 55 cpu-idle-states = <&PERF_CPU_SLEEP_0 56 &PERF_CPU_SLEEP_1 57 &PERF_CLUSTER_SLEEP_0 58 &PERF_CLUSTER_SLEEP_1 59 &PERF_CLUSTER_SLEEP_2>; 60 capacity-dmips-mhz = <1126>; 61 #cooling-cells = <2>; 62 next-level-cache = <&L2_1>; 63 L2_1: l2-cache { 64 compatible = "cache"; 65 cache-level = <2>; 66 cache-unified; 67 }; 68 }; 69 70 CPU1: cpu@101 { 71 device_type = "cpu"; 72 compatible = "arm,cortex-a53"; 73 reg = <0x0 0x101>; 74 enable-method = "psci"; 75 cpu-idle-states = <&PERF_CPU_SLEEP_0 76 &PERF_CPU_SLEEP_1 77 &PERF_CLUSTER_SLEEP_0 78 &PERF_CLUSTER_SLEEP_1 79 &PERF_CLUSTER_SLEEP_2>; 80 capacity-dmips-mhz = <1126>; 81 #cooling-cells = <2>; 82 next-level-cache = <&L2_1>; 83 }; 84 85 CPU2: cpu@102 { 86 device_type = "cpu"; 87 compatible = "arm,cortex-a53"; 88 reg = <0x0 0x102>; 89 enable-method = "psci"; 90 cpu-idle-states = <&PERF_CPU_SLEEP_0 91 &PERF_CPU_SLEEP_1 92 &PERF_CLUSTER_SLEEP_0 93 &PERF_CLUSTER_SLEEP_1 94 &PERF_CLUSTER_SLEEP_2>; 95 capacity-dmips-mhz = <1126>; 96 #cooling-cells = <2>; 97 next-level-cache = <&L2_1>; 98 }; 99 100 CPU3: cpu@103 { 101 device_type = "cpu"; 102 compatible = "arm,cortex-a53"; 103 reg = <0x0 0x103>; 104 enable-method = "psci"; 105 cpu-idle-states = <&PERF_CPU_SLEEP_0 106 &PERF_CPU_SLEEP_1 107 &PERF_CLUSTER_SLEEP_0 108 &PERF_CLUSTER_SLEEP_1 109 &PERF_CLUSTER_SLEEP_2>; 110 capacity-dmips-mhz = <1126>; 111 #cooling-cells = <2>; 112 next-level-cache = <&L2_1>; 113 }; 114 115 CPU4: cpu@0 { 116 device_type = "cpu"; 117 compatible = "arm,cortex-a53"; 118 reg = <0x0 0x0>; 119 enable-method = "psci"; 120 cpu-idle-states = <&PWR_CPU_SLEEP_0 121 &PWR_CPU_SLEEP_1 122 &PWR_CLUSTER_SLEEP_0 123 &PWR_CLUSTER_SLEEP_1 124 &PWR_CLUSTER_SLEEP_2>; 125 capacity-dmips-mhz = <1024>; 126 #cooling-cells = <2>; 127 next-level-cache = <&L2_0>; 128 L2_0: l2-cache { 129 compatible = "cache"; 130 cache-level = <2>; 131 cache-unified; 132 }; 133 }; 134 135 CPU5: cpu@1 { 136 device_type = "cpu"; 137 compatible = "arm,cortex-a53"; 138 reg = <0x0 0x1>; 139 enable-method = "psci"; 140 cpu-idle-states = <&PWR_CPU_SLEEP_0 141 &PWR_CPU_SLEEP_1 142 &PWR_CLUSTER_SLEEP_0 143 &PWR_CLUSTER_SLEEP_1 144 &PWR_CLUSTER_SLEEP_2>; 145 capacity-dmips-mhz = <1024>; 146 #cooling-cells = <2>; 147 next-level-cache = <&L2_0>; 148 }; 149 150 CPU6: cpu@2 { 151 device_type = "cpu"; 152 compatible = "arm,cortex-a53"; 153 reg = <0x0 0x2>; 154 enable-method = "psci"; 155 cpu-idle-states = <&PWR_CPU_SLEEP_0 156 &PWR_CPU_SLEEP_1 157 &PWR_CLUSTER_SLEEP_0 158 &PWR_CLUSTER_SLEEP_1 159 &PWR_CLUSTER_SLEEP_2>; 160 capacity-dmips-mhz = <1024>; 161 #cooling-cells = <2>; 162 next-level-cache = <&L2_0>; 163 }; 164 165 CPU7: cpu@3 { 166 device_type = "cpu"; 167 compatible = "arm,cortex-a53"; 168 reg = <0x0 0x3>; 169 enable-method = "psci"; 170 cpu-idle-states = <&PWR_CPU_SLEEP_0 171 &PWR_CPU_SLEEP_1 172 &PWR_CLUSTER_SLEEP_0 173 &PWR_CLUSTER_SLEEP_1 174 &PWR_CLUSTER_SLEEP_2>; 175 capacity-dmips-mhz = <1024>; 176 #cooling-cells = <2>; 177 next-level-cache = <&L2_0>; 178 }; 179 180 cpu-map { 181 cluster0 { 182 core0 { 183 cpu = <&CPU4>; 184 }; 185 186 core1 { 187 cpu = <&CPU5>; 188 }; 189 190 core2 { 191 cpu = <&CPU6>; 192 }; 193 194 core3 { 195 cpu = <&CPU7>; 196 }; 197 }; 198 199 cluster1 { 200 core0 { 201 cpu = <&CPU0>; 202 }; 203 204 core1 { 205 cpu = <&CPU1>; 206 }; 207 208 core2 { 209 cpu = <&CPU2>; 210 }; 211 212 core3 { 213 cpu = <&CPU3>; 214 }; 215 }; 216 }; 217 218 idle-states { 219 entry-method = "psci"; 220 221 PWR_CPU_SLEEP_0: cpu-sleep-0-0 { 222 compatible = "arm,idle-state"; 223 idle-state-name = "pwr-retention"; 224 arm,psci-suspend-param = <0x40000002>; 225 entry-latency-us = <338>; 226 exit-latency-us = <423>; 227 min-residency-us = <200>; 228 }; 229 230 PWR_CPU_SLEEP_1: cpu-sleep-0-1 { 231 compatible = "arm,idle-state"; 232 idle-state-name = "pwr-power-collapse"; 233 arm,psci-suspend-param = <0x40000003>; 234 entry-latency-us = <515>; 235 exit-latency-us = <1821>; 236 min-residency-us = <1000>; 237 local-timer-stop; 238 }; 239 240 PERF_CPU_SLEEP_0: cpu-sleep-1-0 { 241 compatible = "arm,idle-state"; 242 idle-state-name = "perf-retention"; 243 arm,psci-suspend-param = <0x40000002>; 244 entry-latency-us = <154>; 245 exit-latency-us = <87>; 246 min-residency-us = <200>; 247 }; 248 249 PERF_CPU_SLEEP_1: cpu-sleep-1-1 { 250 compatible = "arm,idle-state"; 251 idle-state-name = "perf-power-collapse"; 252 arm,psci-suspend-param = <0x40000003>; 253 entry-latency-us = <262>; 254 exit-latency-us = <301>; 255 min-residency-us = <1000>; 256 local-timer-stop; 257 }; 258 259 PWR_CLUSTER_SLEEP_0: cluster-sleep-0-0 { 260 compatible = "arm,idle-state"; 261 idle-state-name = "pwr-cluster-dynamic-retention"; 262 arm,psci-suspend-param = <0x400000F2>; 263 entry-latency-us = <284>; 264 exit-latency-us = <384>; 265 min-residency-us = <9987>; 266 local-timer-stop; 267 }; 268 269 PWR_CLUSTER_SLEEP_1: cluster-sleep-0-1 { 270 compatible = "arm,idle-state"; 271 idle-state-name = "pwr-cluster-retention"; 272 arm,psci-suspend-param = <0x400000F3>; 273 entry-latency-us = <338>; 274 exit-latency-us = <423>; 275 min-residency-us = <9987>; 276 local-timer-stop; 277 }; 278 279 PWR_CLUSTER_SLEEP_2: cluster-sleep-0-2 { 280 compatible = "arm,idle-state"; 281 idle-state-name = "pwr-cluster-retention"; 282 arm,psci-suspend-param = <0x400000F4>; 283 entry-latency-us = <515>; 284 exit-latency-us = <1821>; 285 min-residency-us = <9987>; 286 local-timer-stop; 287 }; 288 289 PERF_CLUSTER_SLEEP_0: cluster-sleep-1-0 { 290 compatible = "arm,idle-state"; 291 idle-state-name = "perf-cluster-dynamic-retention"; 292 arm,psci-suspend-param = <0x400000F2>; 293 entry-latency-us = <272>; 294 exit-latency-us = <329>; 295 min-residency-us = <9987>; 296 local-timer-stop; 297 }; 298 299 PERF_CLUSTER_SLEEP_1: cluster-sleep-1-1 { 300 compatible = "arm,idle-state"; 301 idle-state-name = "perf-cluster-retention"; 302 arm,psci-suspend-param = <0x400000F3>; 303 entry-latency-us = <332>; 304 exit-latency-us = <368>; 305 min-residency-us = <9987>; 306 local-timer-stop; 307 }; 308 309 PERF_CLUSTER_SLEEP_2: cluster-sleep-1-2 { 310 compatible = "arm,idle-state"; 311 idle-state-name = "perf-cluster-retention"; 312 arm,psci-suspend-param = <0x400000F4>; 313 entry-latency-us = <545>; 314 exit-latency-us = <1609>; 315 min-residency-us = <9987>; 316 local-timer-stop; 317 }; 318 }; 319 }; 320 321 firmware { 322 scm { 323 compatible = "qcom,scm-msm8998", "qcom,scm"; 324 }; 325 }; 326 327 memory@80000000 { 328 device_type = "memory"; 329 /* We expect the bootloader to fill in the reg */ 330 reg = <0x0 0x80000000 0x0 0x0>; 331 }; 332 333 dsi_opp_table: opp-table-dsi { 334 compatible = "operating-points-v2"; 335 336 opp-131250000 { 337 opp-hz = /bits/ 64 <131250000>; 338 required-opps = <&rpmpd_opp_svs>; 339 }; 340 341 opp-210000000 { 342 opp-hz = /bits/ 64 <210000000>; 343 required-opps = <&rpmpd_opp_svs_plus>; 344 }; 345 346 opp-262500000 { 347 opp-hz = /bits/ 64 <262500000>; 348 required-opps = <&rpmpd_opp_nom>; 349 }; 350 }; 351 352 pmu { 353 compatible = "arm,armv8-pmuv3"; 354 interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>; 355 }; 356 357 psci { 358 compatible = "arm,psci-1.0"; 359 method = "smc"; 360 }; 361 362 reserved-memory { 363 #address-cells = <2>; 364 #size-cells = <2>; 365 ranges; 366 367 wlan_msa_guard: wlan-msa-guard@85600000 { 368 reg = <0x0 0x85600000 0x0 0x100000>; 369 no-map; 370 }; 371 372 wlan_msa_mem: wlan-msa-mem@85700000 { 373 reg = <0x0 0x85700000 0x0 0x100000>; 374 no-map; 375 }; 376 377 qhee_code: qhee-code@85800000 { 378 reg = <0x0 0x85800000 0x0 0x600000>; 379 no-map; 380 }; 381 382 rmtfs_mem: memory@85e00000 { 383 compatible = "qcom,rmtfs-mem"; 384 reg = <0x0 0x85e00000 0x0 0x200000>; 385 no-map; 386 387 qcom,client-id = <1>; 388 qcom,vmid = <15>; 389 }; 390 391 smem_region: smem-mem@86000000 { 392 reg = <0 0x86000000 0 0x200000>; 393 no-map; 394 }; 395 396 tz_mem: memory@86200000 { 397 reg = <0x0 0x86200000 0x0 0x3300000>; 398 no-map; 399 }; 400 401 mpss_region: mpss@8ac00000 { 402 reg = <0x0 0x8ac00000 0x0 0x7e00000>; 403 no-map; 404 }; 405 406 adsp_region: adsp@92a00000 { 407 reg = <0x0 0x92a00000 0x0 0x1e00000>; 408 no-map; 409 }; 410 411 mba_region: mba@94800000 { 412 reg = <0x0 0x94800000 0x0 0x200000>; 413 no-map; 414 }; 415 416 buffer_mem: tzbuffer@94a00000 { 417 reg = <0x0 0x94a00000 0x0 0x100000>; 418 no-map; 419 }; 420 421 venus_region: venus@9f800000 { 422 reg = <0x0 0x9f800000 0x0 0x800000>; 423 no-map; 424 }; 425 426 adsp_mem: adsp-region@f6000000 { 427 reg = <0x0 0xf6000000 0x0 0x800000>; 428 no-map; 429 }; 430 431 qseecom_mem: qseecom-region@f6800000 { 432 reg = <0x0 0xf6800000 0x0 0x1400000>; 433 no-map; 434 }; 435 436 zap_shader_region: gpu@fed00000 { 437 compatible = "shared-dma-pool"; 438 reg = <0x0 0xfed00000 0x0 0xa00000>; 439 no-map; 440 }; 441 }; 442 443 rpm-glink { 444 compatible = "qcom,glink-rpm"; 445 446 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 447 qcom,rpm-msg-ram = <&rpm_msg_ram>; 448 mboxes = <&apcs_glb 0>; 449 450 rpm_requests: rpm-requests { 451 compatible = "qcom,rpm-sdm660"; 452 qcom,glink-channels = "rpm_requests"; 453 454 rpmcc: clock-controller { 455 compatible = "qcom,rpmcc-sdm660", "qcom,rpmcc"; 456 #clock-cells = <1>; 457 }; 458 459 rpmpd: power-controller { 460 compatible = "qcom,sdm660-rpmpd"; 461 #power-domain-cells = <1>; 462 operating-points-v2 = <&rpmpd_opp_table>; 463 464 rpmpd_opp_table: opp-table { 465 compatible = "operating-points-v2"; 466 467 rpmpd_opp_ret: opp1 { 468 opp-level = <RPM_SMD_LEVEL_RETENTION>; 469 }; 470 471 rpmpd_opp_ret_plus: opp2 { 472 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>; 473 }; 474 475 rpmpd_opp_min_svs: opp3 { 476 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 477 }; 478 479 rpmpd_opp_low_svs: opp4 { 480 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 481 }; 482 483 rpmpd_opp_svs: opp5 { 484 opp-level = <RPM_SMD_LEVEL_SVS>; 485 }; 486 487 rpmpd_opp_svs_plus: opp6 { 488 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 489 }; 490 491 rpmpd_opp_nom: opp7 { 492 opp-level = <RPM_SMD_LEVEL_NOM>; 493 }; 494 495 rpmpd_opp_nom_plus: opp8 { 496 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 497 }; 498 499 rpmpd_opp_turbo: opp9 { 500 opp-level = <RPM_SMD_LEVEL_TURBO>; 501 }; 502 }; 503 }; 504 }; 505 }; 506 507 smem: smem { 508 compatible = "qcom,smem"; 509 memory-region = <&smem_region>; 510 hwlocks = <&tcsr_mutex 3>; 511 }; 512 513 smp2p-adsp { 514 compatible = "qcom,smp2p"; 515 qcom,smem = <443>, <429>; 516 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 517 mboxes = <&apcs_glb 10>; 518 qcom,local-pid = <0>; 519 qcom,remote-pid = <2>; 520 521 adsp_smp2p_out: master-kernel { 522 qcom,entry-name = "master-kernel"; 523 #qcom,smem-state-cells = <1>; 524 }; 525 526 adsp_smp2p_in: slave-kernel { 527 qcom,entry-name = "slave-kernel"; 528 interrupt-controller; 529 #interrupt-cells = <2>; 530 }; 531 }; 532 533 smp2p-mpss { 534 compatible = "qcom,smp2p"; 535 qcom,smem = <435>, <428>; 536 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 537 mboxes = <&apcs_glb 14>; 538 qcom,local-pid = <0>; 539 qcom,remote-pid = <1>; 540 541 modem_smp2p_out: master-kernel { 542 qcom,entry-name = "master-kernel"; 543 #qcom,smem-state-cells = <1>; 544 }; 545 546 modem_smp2p_in: slave-kernel { 547 qcom,entry-name = "slave-kernel"; 548 interrupt-controller; 549 #interrupt-cells = <2>; 550 }; 551 }; 552 553 soc { 554 #address-cells = <1>; 555 #size-cells = <1>; 556 ranges = <0 0 0 0xffffffff>; 557 compatible = "simple-bus"; 558 559 gcc: clock-controller@100000 { 560 compatible = "qcom,gcc-sdm630"; 561 #clock-cells = <1>; 562 #reset-cells = <1>; 563 #power-domain-cells = <1>; 564 reg = <0x00100000 0x94000>; 565 566 clock-names = "xo", "sleep_clk"; 567 clocks = <&xo_board>, 568 <&sleep_clk>; 569 }; 570 571 rpm_msg_ram: sram@778000 { 572 compatible = "qcom,rpm-msg-ram"; 573 reg = <0x00778000 0x7000>; 574 }; 575 576 qfprom: qfprom@780000 { 577 compatible = "qcom,sdm630-qfprom", "qcom,qfprom"; 578 reg = <0x00780000 0x621c>; 579 #address-cells = <1>; 580 #size-cells = <1>; 581 582 qusb2_hstx_trim: hstx-trim@240 { 583 reg = <0x243 0x1>; 584 bits = <1 3>; 585 }; 586 587 gpu_speed_bin: gpu-speed-bin@41a0 { 588 reg = <0x41a2 0x1>; 589 bits = <5 7>; 590 }; 591 }; 592 593 rng: rng@793000 { 594 compatible = "qcom,prng-ee"; 595 reg = <0x00793000 0x1000>; 596 clocks = <&gcc GCC_PRNG_AHB_CLK>; 597 clock-names = "core"; 598 }; 599 600 bimc: interconnect@1008000 { 601 compatible = "qcom,sdm660-bimc"; 602 reg = <0x01008000 0x78000>; 603 #interconnect-cells = <1>; 604 clock-names = "bus", "bus_a"; 605 clocks = <&rpmcc RPM_SMD_BIMC_CLK>, 606 <&rpmcc RPM_SMD_BIMC_A_CLK>; 607 }; 608 609 restart@10ac000 { 610 compatible = "qcom,pshold"; 611 reg = <0x010ac000 0x4>; 612 }; 613 614 cnoc: interconnect@1500000 { 615 compatible = "qcom,sdm660-cnoc"; 616 reg = <0x01500000 0x10000>; 617 #interconnect-cells = <1>; 618 clock-names = "bus", "bus_a"; 619 clocks = <&rpmcc RPM_SMD_CNOC_CLK>, 620 <&rpmcc RPM_SMD_CNOC_A_CLK>; 621 }; 622 623 snoc: interconnect@1626000 { 624 compatible = "qcom,sdm660-snoc"; 625 reg = <0x01626000 0x7090>; 626 #interconnect-cells = <1>; 627 clock-names = "bus", "bus_a"; 628 clocks = <&rpmcc RPM_SMD_SNOC_CLK>, 629 <&rpmcc RPM_SMD_SNOC_A_CLK>; 630 }; 631 632 anoc2_smmu: iommu@16c0000 { 633 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2"; 634 reg = <0x016c0000 0x40000>; 635 636 assigned-clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>; 637 assigned-clock-rates = <1000>; 638 clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>; 639 clock-names = "bus"; 640 #global-interrupts = <2>; 641 #iommu-cells = <1>; 642 643 interrupts = 644 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 645 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 646 647 <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>, 648 <GIC_SPI 374 IRQ_TYPE_LEVEL_LOW>, 649 <GIC_SPI 375 IRQ_TYPE_LEVEL_LOW>, 650 <GIC_SPI 376 IRQ_TYPE_LEVEL_LOW>, 651 <GIC_SPI 377 IRQ_TYPE_LEVEL_LOW>, 652 <GIC_SPI 378 IRQ_TYPE_LEVEL_LOW>, 653 <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>, 654 <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>, 655 <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>, 656 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>, 657 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>, 658 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>, 659 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>, 660 <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, 661 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>, 662 <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>, 663 <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>, 664 <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, 665 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, 666 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, 667 <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>, 668 <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>, 669 <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, 670 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>, 671 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>, 672 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>, 673 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, 674 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, 675 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>; 676 677 status = "disabled"; 678 }; 679 680 a2noc: interconnect@1704000 { 681 compatible = "qcom,sdm660-a2noc"; 682 reg = <0x01704000 0xc100>; 683 #interconnect-cells = <1>; 684 clock-names = "bus", 685 "bus_a", 686 "ipa", 687 "ufs_axi", 688 "aggre2_ufs_axi", 689 "aggre2_usb3_axi", 690 "cfg_noc_usb2_axi"; 691 clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>, 692 <&rpmcc RPM_SMD_AGGR2_NOC_A_CLK>, 693 <&rpmcc RPM_SMD_IPA_CLK>, 694 <&gcc GCC_UFS_AXI_CLK>, 695 <&gcc GCC_AGGRE2_UFS_AXI_CLK>, 696 <&gcc GCC_AGGRE2_USB3_AXI_CLK>, 697 <&gcc GCC_CFG_NOC_USB2_AXI_CLK>; 698 }; 699 700 mnoc: interconnect@1745000 { 701 compatible = "qcom,sdm660-mnoc"; 702 reg = <0x01745000 0xa010>; 703 #interconnect-cells = <1>; 704 clock-names = "bus", "bus_a", "iface"; 705 clocks = <&rpmcc RPM_SMD_MMSSNOC_AXI_CLK>, 706 <&rpmcc RPM_SMD_MMSSNOC_AXI_CLK_A>, 707 <&mmcc AHB_CLK_SRC>; 708 }; 709 710 tsens: thermal-sensor@10ae000 { 711 compatible = "qcom,sdm630-tsens", "qcom,tsens-v2"; 712 reg = <0x010ae000 0x1000>, /* TM */ 713 <0x010ad000 0x1000>; /* SROT */ 714 #qcom,sensors = <12>; 715 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 716 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>; 717 interrupt-names = "uplow", "critical"; 718 #thermal-sensor-cells = <1>; 719 }; 720 721 tcsr_mutex: hwlock@1f40000 { 722 compatible = "qcom,tcsr-mutex"; 723 reg = <0x01f40000 0x20000>; 724 #hwlock-cells = <1>; 725 }; 726 727 tcsr_regs_1: syscon@1f60000 { 728 compatible = "qcom,sdm630-tcsr", "syscon"; 729 reg = <0x01f60000 0x20000>; 730 }; 731 732 tlmm: pinctrl@3100000 { 733 compatible = "qcom,sdm630-pinctrl"; 734 reg = <0x03100000 0x400000>, 735 <0x03500000 0x400000>, 736 <0x03900000 0x400000>; 737 reg-names = "south", "center", "north"; 738 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 739 gpio-controller; 740 gpio-ranges = <&tlmm 0 0 114>; 741 #gpio-cells = <2>; 742 interrupt-controller; 743 #interrupt-cells = <2>; 744 745 blsp1_uart1_default: blsp1-uart1-default-state { 746 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 747 function = "blsp_uart1"; 748 drive-strength = <2>; 749 bias-disable; 750 }; 751 752 blsp1_uart1_sleep: blsp1-uart1-sleep-state { 753 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 754 function = "gpio"; 755 drive-strength = <2>; 756 bias-disable; 757 }; 758 759 blsp1_uart2_default: blsp1-uart2-default-state { 760 pins = "gpio4", "gpio5"; 761 function = "blsp_uart2"; 762 drive-strength = <2>; 763 bias-disable; 764 }; 765 766 blsp2_uart1_default: blsp2-uart1-active-state { 767 tx-rts-pins { 768 pins = "gpio16", "gpio19"; 769 function = "blsp_uart5"; 770 drive-strength = <2>; 771 bias-disable; 772 }; 773 774 rx-pins { 775 /* 776 * Avoid garbage data while BT module 777 * is powered off or not driving signal 778 */ 779 pins = "gpio17"; 780 function = "blsp_uart5"; 781 drive-strength = <2>; 782 bias-pull-up; 783 }; 784 785 cts-pins { 786 /* Match the pull of the BT module */ 787 pins = "gpio18"; 788 function = "blsp_uart5"; 789 drive-strength = <2>; 790 bias-pull-down; 791 }; 792 }; 793 794 blsp2_uart1_sleep: blsp2-uart1-sleep-state { 795 tx-pins { 796 pins = "gpio16"; 797 function = "gpio"; 798 drive-strength = <2>; 799 bias-pull-up; 800 }; 801 802 rx-cts-rts-pins { 803 pins = "gpio17", "gpio18", "gpio19"; 804 function = "gpio"; 805 drive-strength = <2>; 806 bias-disable; 807 }; 808 }; 809 810 i2c1_default: i2c1-default-state { 811 pins = "gpio2", "gpio3"; 812 function = "blsp_i2c1"; 813 drive-strength = <2>; 814 bias-disable; 815 }; 816 817 i2c1_sleep: i2c1-sleep-state { 818 pins = "gpio2", "gpio3"; 819 function = "blsp_i2c1"; 820 drive-strength = <2>; 821 bias-pull-up; 822 }; 823 824 i2c2_default: i2c2-default-state { 825 pins = "gpio6", "gpio7"; 826 function = "blsp_i2c2"; 827 drive-strength = <2>; 828 bias-disable; 829 }; 830 831 i2c2_sleep: i2c2-sleep-state { 832 pins = "gpio6", "gpio7"; 833 function = "blsp_i2c2"; 834 drive-strength = <2>; 835 bias-pull-up; 836 }; 837 838 i2c3_default: i2c3-default-state { 839 pins = "gpio10", "gpio11"; 840 function = "blsp_i2c3"; 841 drive-strength = <2>; 842 bias-disable; 843 }; 844 845 i2c3_sleep: i2c3-sleep-state { 846 pins = "gpio10", "gpio11"; 847 function = "blsp_i2c3"; 848 drive-strength = <2>; 849 bias-pull-up; 850 }; 851 852 i2c4_default: i2c4-default-state { 853 pins = "gpio14", "gpio15"; 854 function = "blsp_i2c4"; 855 drive-strength = <2>; 856 bias-disable; 857 }; 858 859 i2c4_sleep: i2c4-sleep-state { 860 pins = "gpio14", "gpio15"; 861 function = "blsp_i2c4"; 862 drive-strength = <2>; 863 bias-pull-up; 864 }; 865 866 i2c5_default: i2c5-default-state { 867 pins = "gpio18", "gpio19"; 868 function = "blsp_i2c5"; 869 drive-strength = <2>; 870 bias-disable; 871 }; 872 873 i2c5_sleep: i2c5-sleep-state { 874 pins = "gpio18", "gpio19"; 875 function = "blsp_i2c5"; 876 drive-strength = <2>; 877 bias-pull-up; 878 }; 879 880 i2c6_default: i2c6-default-state { 881 pins = "gpio22", "gpio23"; 882 function = "blsp_i2c6"; 883 drive-strength = <2>; 884 bias-disable; 885 }; 886 887 i2c6_sleep: i2c6-sleep-state { 888 pins = "gpio22", "gpio23"; 889 function = "blsp_i2c6"; 890 drive-strength = <2>; 891 bias-pull-up; 892 }; 893 894 i2c7_default: i2c7-default-state { 895 pins = "gpio26", "gpio27"; 896 function = "blsp_i2c7"; 897 drive-strength = <2>; 898 bias-disable; 899 }; 900 901 i2c7_sleep: i2c7-sleep-state { 902 pins = "gpio26", "gpio27"; 903 function = "blsp_i2c7"; 904 drive-strength = <2>; 905 bias-pull-up; 906 }; 907 908 i2c8_default: i2c8-default-state { 909 pins = "gpio30", "gpio31"; 910 function = "blsp_i2c8_a"; 911 drive-strength = <2>; 912 bias-disable; 913 }; 914 915 i2c8_sleep: i2c8-sleep-state { 916 pins = "gpio30", "gpio31"; 917 function = "blsp_i2c8_a"; 918 drive-strength = <2>; 919 bias-pull-up; 920 }; 921 922 cci0_default: cci0-default-state { 923 pins = "gpio36","gpio37"; 924 function = "cci_i2c"; 925 bias-pull-up; 926 drive-strength = <2>; 927 }; 928 929 cci1_default: cci1-default-state { 930 pins = "gpio38","gpio39"; 931 function = "cci_i2c"; 932 bias-pull-up; 933 drive-strength = <2>; 934 }; 935 936 sdc1_state_on: sdc1-on-state { 937 clk-pins { 938 pins = "sdc1_clk"; 939 bias-disable; 940 drive-strength = <16>; 941 }; 942 943 cmd-pins { 944 pins = "sdc1_cmd"; 945 bias-pull-up; 946 drive-strength = <10>; 947 }; 948 949 data-pins { 950 pins = "sdc1_data"; 951 bias-pull-up; 952 drive-strength = <10>; 953 }; 954 955 rclk-pins { 956 pins = "sdc1_rclk"; 957 bias-pull-down; 958 }; 959 }; 960 961 sdc1_state_off: sdc1-off-state { 962 clk-pins { 963 pins = "sdc1_clk"; 964 bias-disable; 965 drive-strength = <2>; 966 }; 967 968 cmd-pins { 969 pins = "sdc1_cmd"; 970 bias-pull-up; 971 drive-strength = <2>; 972 }; 973 974 data-pins { 975 pins = "sdc1_data"; 976 bias-pull-up; 977 drive-strength = <2>; 978 }; 979 980 rclk-pins { 981 pins = "sdc1_rclk"; 982 bias-pull-down; 983 }; 984 }; 985 986 sdc2_state_on: sdc2-on-state { 987 clk-pins { 988 pins = "sdc2_clk"; 989 bias-disable; 990 drive-strength = <16>; 991 }; 992 993 cmd-pins { 994 pins = "sdc2_cmd"; 995 bias-pull-up; 996 drive-strength = <10>; 997 }; 998 999 data-pins { 1000 pins = "sdc2_data"; 1001 bias-pull-up; 1002 drive-strength = <10>; 1003 }; 1004 }; 1005 1006 sdc2_state_off: sdc2-off-state { 1007 clk-pins { 1008 pins = "sdc2_clk"; 1009 bias-disable; 1010 drive-strength = <2>; 1011 }; 1012 1013 cmd-pins { 1014 pins = "sdc2_cmd"; 1015 bias-pull-up; 1016 drive-strength = <2>; 1017 }; 1018 1019 data-pins { 1020 pins = "sdc2_data"; 1021 bias-pull-up; 1022 drive-strength = <2>; 1023 }; 1024 }; 1025 }; 1026 1027 adreno_gpu: gpu@5000000 { 1028 compatible = "qcom,adreno-508.0", "qcom,adreno"; 1029 1030 reg = <0x05000000 0x40000>; 1031 reg-names = "kgsl_3d0_reg_memory"; 1032 1033 interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>; 1034 1035 clocks = <&gcc GCC_GPU_CFG_AHB_CLK>, 1036 <&gpucc GPUCC_RBBMTIMER_CLK>, 1037 <&gcc GCC_BIMC_GFX_CLK>, 1038 <&gcc GCC_GPU_BIMC_GFX_CLK>, 1039 <&gpucc GPUCC_RBCPR_CLK>, 1040 <&gpucc GPUCC_GFX3D_CLK>; 1041 1042 clock-names = "iface", 1043 "rbbmtimer", 1044 "mem", 1045 "mem_iface", 1046 "rbcpr", 1047 "core"; 1048 1049 power-domains = <&rpmpd SDM660_VDDMX>; 1050 iommus = <&kgsl_smmu 0>; 1051 1052 nvmem-cells = <&gpu_speed_bin>; 1053 nvmem-cell-names = "speed_bin"; 1054 1055 interconnects = <&bimc MASTER_OXILI &bimc SLAVE_EBI>; 1056 interconnect-names = "gfx-mem"; 1057 1058 operating-points-v2 = <&gpu_sdm630_opp_table>; 1059 1060 status = "disabled"; 1061 1062 gpu_sdm630_opp_table: opp-table { 1063 compatible = "operating-points-v2"; 1064 opp-775000000 { 1065 opp-hz = /bits/ 64 <775000000>; 1066 opp-level = <RPM_SMD_LEVEL_TURBO>; 1067 opp-peak-kBps = <5412000>; 1068 opp-supported-hw = <0xa2>; 1069 }; 1070 opp-647000000 { 1071 opp-hz = /bits/ 64 <647000000>; 1072 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 1073 opp-peak-kBps = <4068000>; 1074 opp-supported-hw = <0xff>; 1075 }; 1076 opp-588000000 { 1077 opp-hz = /bits/ 64 <588000000>; 1078 opp-level = <RPM_SMD_LEVEL_NOM>; 1079 opp-peak-kBps = <3072000>; 1080 opp-supported-hw = <0xff>; 1081 }; 1082 opp-465000000 { 1083 opp-hz = /bits/ 64 <465000000>; 1084 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 1085 opp-peak-kBps = <2724000>; 1086 opp-supported-hw = <0xff>; 1087 }; 1088 opp-370000000 { 1089 opp-hz = /bits/ 64 <370000000>; 1090 opp-level = <RPM_SMD_LEVEL_SVS>; 1091 opp-peak-kBps = <2188000>; 1092 opp-supported-hw = <0xff>; 1093 }; 1094 opp-240000000 { 1095 opp-hz = /bits/ 64 <240000000>; 1096 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 1097 opp-peak-kBps = <1648000>; 1098 opp-supported-hw = <0xff>; 1099 }; 1100 opp-160000000 { 1101 opp-hz = /bits/ 64 <160000000>; 1102 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 1103 opp-peak-kBps = <1200000>; 1104 opp-supported-hw = <0xff>; 1105 }; 1106 }; 1107 }; 1108 1109 kgsl_smmu: iommu@5040000 { 1110 compatible = "qcom,sdm630-smmu-v2", 1111 "qcom,adreno-smmu", "qcom,smmu-v2"; 1112 reg = <0x05040000 0x10000>; 1113 1114 /* 1115 * GX GDSC parent is CX. We need to bring up CX for SMMU 1116 * but we need both up for Adreno. On the other hand, we 1117 * need to manage the GX rpmpd domain in the adreno driver. 1118 * Enable CX/GX GDSCs here so that we can manage just the GX 1119 * RPM Power Domain in the Adreno driver. 1120 */ 1121 power-domains = <&gpucc GPU_GX_GDSC>; 1122 clocks = <&gcc GCC_GPU_CFG_AHB_CLK>, 1123 <&gcc GCC_BIMC_GFX_CLK>, 1124 <&gcc GCC_GPU_BIMC_GFX_CLK>; 1125 clock-names = "iface", "mem", "mem_iface"; 1126 #global-interrupts = <2>; 1127 #iommu-cells = <1>; 1128 1129 interrupts = 1130 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 1131 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 1132 1133 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 1134 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 1135 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 1136 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 1137 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1138 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1139 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>, 1140 <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>; 1141 1142 status = "disabled"; 1143 }; 1144 1145 gpucc: clock-controller@5065000 { 1146 compatible = "qcom,gpucc-sdm630"; 1147 #clock-cells = <1>; 1148 #reset-cells = <1>; 1149 #power-domain-cells = <1>; 1150 reg = <0x05065000 0x9038>; 1151 1152 clocks = <&xo_board>, 1153 <&gcc GCC_GPU_GPLL0_CLK>, 1154 <&gcc GCC_GPU_GPLL0_DIV_CLK>; 1155 clock-names = "xo", 1156 "gcc_gpu_gpll0_clk", 1157 "gcc_gpu_gpll0_div_clk"; 1158 status = "disabled"; 1159 }; 1160 1161 lpass_smmu: iommu@5100000 { 1162 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2"; 1163 reg = <0x05100000 0x40000>; 1164 #iommu-cells = <1>; 1165 1166 #global-interrupts = <2>; 1167 interrupts = 1168 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 1169 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 1170 1171 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, 1172 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>, 1173 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>, 1174 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 1175 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 1176 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 1177 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 1178 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 1179 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 1180 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 1181 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 1182 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 1183 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 1184 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, 1185 <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>, 1186 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 1187 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>; 1188 1189 status = "disabled"; 1190 }; 1191 1192 sram@290000 { 1193 compatible = "qcom,rpm-stats"; 1194 reg = <0x00290000 0x10000>; 1195 }; 1196 1197 spmi_bus: spmi@800f000 { 1198 compatible = "qcom,spmi-pmic-arb"; 1199 reg = <0x0800f000 0x1000>, 1200 <0x08400000 0x1000000>, 1201 <0x09400000 0x1000000>, 1202 <0x0a400000 0x220000>, 1203 <0x0800a000 0x3000>; 1204 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1205 interrupt-names = "periph_irq"; 1206 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>; 1207 qcom,ee = <0>; 1208 qcom,channel = <0>; 1209 #address-cells = <2>; 1210 #size-cells = <0>; 1211 interrupt-controller; 1212 #interrupt-cells = <4>; 1213 }; 1214 1215 usb3: usb@a8f8800 { 1216 compatible = "qcom,sdm660-dwc3", "qcom,dwc3"; 1217 reg = <0x0a8f8800 0x400>; 1218 status = "disabled"; 1219 #address-cells = <1>; 1220 #size-cells = <1>; 1221 ranges; 1222 1223 clocks = <&gcc GCC_CFG_NOC_USB3_AXI_CLK>, 1224 <&gcc GCC_USB30_MASTER_CLK>, 1225 <&gcc GCC_AGGRE2_USB3_AXI_CLK>, 1226 <&gcc GCC_USB30_SLEEP_CLK>, 1227 <&gcc GCC_USB30_MOCK_UTMI_CLK>, 1228 <&rpmcc RPM_SMD_AGGR2_NOC_CLK>; 1229 clock-names = "cfg_noc", 1230 "core", 1231 "iface", 1232 "sleep", 1233 "mock_utmi", 1234 "bus"; 1235 1236 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, 1237 <&gcc GCC_USB30_MASTER_CLK>, 1238 <&rpmcc RPM_SMD_AGGR2_NOC_CLK>; 1239 assigned-clock-rates = <19200000>, <120000000>, 1240 <19200000>; 1241 1242 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, 1243 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 1244 interrupt-names = "hs_phy_irq", "ss_phy_irq"; 1245 1246 power-domains = <&gcc USB_30_GDSC>; 1247 qcom,select-utmi-as-pipe-clk; 1248 1249 resets = <&gcc GCC_USB_30_BCR>; 1250 1251 usb3_dwc3: usb@a800000 { 1252 compatible = "snps,dwc3"; 1253 reg = <0x0a800000 0xc8d0>; 1254 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 1255 snps,dis_u2_susphy_quirk; 1256 snps,dis_enblslpm_quirk; 1257 1258 /* 1259 * SDM630 technically supports USB3 but I 1260 * haven't seen any devices making use of it. 1261 */ 1262 maximum-speed = "high-speed"; 1263 phys = <&qusb2phy0>; 1264 phy-names = "usb2-phy"; 1265 snps,hird-threshold = /bits/ 8 <0>; 1266 }; 1267 }; 1268 1269 qusb2phy0: phy@c012000 { 1270 compatible = "qcom,sdm660-qusb2-phy"; 1271 reg = <0x0c012000 0x180>; 1272 #phy-cells = <0>; 1273 1274 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 1275 <&gcc GCC_RX0_USB2_CLKREF_CLK>; 1276 clock-names = "cfg_ahb", "ref"; 1277 1278 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 1279 nvmem-cells = <&qusb2_hstx_trim>; 1280 status = "disabled"; 1281 }; 1282 1283 qusb2phy1: phy@c014000 { 1284 compatible = "qcom,sdm660-qusb2-phy"; 1285 reg = <0x0c014000 0x180>; 1286 #phy-cells = <0>; 1287 1288 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 1289 <&gcc GCC_RX1_USB2_CLKREF_CLK>; 1290 clock-names = "cfg_ahb", "ref"; 1291 1292 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 1293 nvmem-cells = <&qusb2_hstx_trim>; 1294 status = "disabled"; 1295 }; 1296 1297 sdhc_2: mmc@c084000 { 1298 compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5"; 1299 reg = <0x0c084000 0x1000>; 1300 reg-names = "hc"; 1301 1302 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1303 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 1304 interrupt-names = "hc_irq", "pwr_irq"; 1305 1306 bus-width = <4>; 1307 1308 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 1309 <&gcc GCC_SDCC2_APPS_CLK>, 1310 <&xo_board>; 1311 clock-names = "iface", "core", "xo"; 1312 1313 1314 interconnects = <&a2noc 3 &a2noc 10>, 1315 <&gnoc 0 &cnoc 28>; 1316 interconnect-names = "sdhc-ddr","cpu-sdhc"; 1317 operating-points-v2 = <&sdhc2_opp_table>; 1318 1319 pinctrl-names = "default", "sleep"; 1320 pinctrl-0 = <&sdc2_state_on>; 1321 pinctrl-1 = <&sdc2_state_off>; 1322 power-domains = <&rpmpd SDM660_VDDCX>; 1323 1324 status = "disabled"; 1325 1326 sdhc2_opp_table: opp-table { 1327 compatible = "operating-points-v2"; 1328 1329 opp-50000000 { 1330 opp-hz = /bits/ 64 <50000000>; 1331 required-opps = <&rpmpd_opp_low_svs>; 1332 opp-peak-kBps = <200000 140000>; 1333 opp-avg-kBps = <130718 133320>; 1334 }; 1335 opp-100000000 { 1336 opp-hz = /bits/ 64 <100000000>; 1337 required-opps = <&rpmpd_opp_svs>; 1338 opp-peak-kBps = <250000 160000>; 1339 opp-avg-kBps = <196078 150000>; 1340 }; 1341 opp-200000000 { 1342 opp-hz = /bits/ 64 <200000000>; 1343 required-opps = <&rpmpd_opp_nom>; 1344 opp-peak-kBps = <4096000 4096000>; 1345 opp-avg-kBps = <1338562 1338562>; 1346 }; 1347 }; 1348 }; 1349 1350 sdhc_1: mmc@c0c4000 { 1351 compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5"; 1352 reg = <0x0c0c4000 0x1000>, 1353 <0x0c0c5000 0x1000>, 1354 <0x0c0c8000 0x8000>; 1355 reg-names = "hc", "cqhci", "ice"; 1356 1357 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1358 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1359 interrupt-names = "hc_irq", "pwr_irq"; 1360 1361 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 1362 <&gcc GCC_SDCC1_APPS_CLK>, 1363 <&xo_board>, 1364 <&gcc GCC_SDCC1_ICE_CORE_CLK>; 1365 clock-names = "iface", "core", "xo", "ice"; 1366 1367 interconnects = <&a2noc 2 &a2noc 10>, 1368 <&gnoc 0 &cnoc 27>; 1369 interconnect-names = "sdhc-ddr", "cpu-sdhc"; 1370 operating-points-v2 = <&sdhc1_opp_table>; 1371 pinctrl-names = "default", "sleep"; 1372 pinctrl-0 = <&sdc1_state_on>; 1373 pinctrl-1 = <&sdc1_state_off>; 1374 power-domains = <&rpmpd SDM660_VDDCX>; 1375 1376 bus-width = <8>; 1377 non-removable; 1378 1379 status = "disabled"; 1380 1381 sdhc1_opp_table: opp-table { 1382 compatible = "operating-points-v2"; 1383 1384 opp-50000000 { 1385 opp-hz = /bits/ 64 <50000000>; 1386 required-opps = <&rpmpd_opp_low_svs>; 1387 opp-peak-kBps = <200000 140000>; 1388 opp-avg-kBps = <130718 133320>; 1389 }; 1390 opp-100000000 { 1391 opp-hz = /bits/ 64 <100000000>; 1392 required-opps = <&rpmpd_opp_svs>; 1393 opp-peak-kBps = <250000 160000>; 1394 opp-avg-kBps = <196078 150000>; 1395 }; 1396 opp-384000000 { 1397 opp-hz = /bits/ 64 <384000000>; 1398 required-opps = <&rpmpd_opp_nom>; 1399 opp-peak-kBps = <4096000 4096000>; 1400 opp-avg-kBps = <1338562 1338562>; 1401 }; 1402 }; 1403 }; 1404 1405 usb2: usb@c2f8800 { 1406 compatible = "qcom,sdm660-dwc3", "qcom,dwc3"; 1407 reg = <0x0c2f8800 0x400>; 1408 status = "disabled"; 1409 #address-cells = <1>; 1410 #size-cells = <1>; 1411 ranges; 1412 1413 clocks = <&gcc GCC_CFG_NOC_USB2_AXI_CLK>, 1414 <&gcc GCC_USB20_MASTER_CLK>, 1415 <&gcc GCC_USB20_MOCK_UTMI_CLK>, 1416 <&gcc GCC_USB20_SLEEP_CLK>; 1417 clock-names = "cfg_noc", "core", 1418 "mock_utmi", "sleep"; 1419 1420 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, 1421 <&gcc GCC_USB20_MASTER_CLK>; 1422 assigned-clock-rates = <19200000>, <60000000>; 1423 1424 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>; 1425 interrupt-names = "hs_phy_irq"; 1426 1427 qcom,select-utmi-as-pipe-clk; 1428 1429 resets = <&gcc GCC_USB_20_BCR>; 1430 1431 usb2_dwc3: usb@c200000 { 1432 compatible = "snps,dwc3"; 1433 reg = <0x0c200000 0xc8d0>; 1434 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 1435 snps,dis_u2_susphy_quirk; 1436 snps,dis_enblslpm_quirk; 1437 1438 /* This is the HS-only host */ 1439 maximum-speed = "high-speed"; 1440 phys = <&qusb2phy1>; 1441 phy-names = "usb2-phy"; 1442 snps,hird-threshold = /bits/ 8 <0>; 1443 }; 1444 }; 1445 1446 mmcc: clock-controller@c8c0000 { 1447 compatible = "qcom,mmcc-sdm630"; 1448 reg = <0x0c8c0000 0x40000>; 1449 #clock-cells = <1>; 1450 #reset-cells = <1>; 1451 #power-domain-cells = <1>; 1452 clock-names = "xo", 1453 "sleep_clk", 1454 "gpll0", 1455 "gpll0_div", 1456 "dsi0pll", 1457 "dsi0pllbyte", 1458 "dsi1pll", 1459 "dsi1pllbyte", 1460 "dp_link_2x_clk_divsel_five", 1461 "dp_vco_divided_clk_src_mux"; 1462 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 1463 <&sleep_clk>, 1464 <&gcc GCC_MMSS_GPLL0_CLK>, 1465 <&gcc GCC_MMSS_GPLL0_DIV_CLK>, 1466 <&dsi0_phy 1>, 1467 <&dsi0_phy 0>, 1468 <0>, 1469 <0>, 1470 <0>, 1471 <0>; 1472 }; 1473 1474 mdss: display-subsystem@c900000 { 1475 compatible = "qcom,mdss"; 1476 reg = <0x0c900000 0x1000>, 1477 <0x0c9b0000 0x1040>; 1478 reg-names = "mdss_phys", "vbif_phys"; 1479 1480 power-domains = <&mmcc MDSS_GDSC>; 1481 1482 clocks = <&mmcc MDSS_AHB_CLK>, 1483 <&mmcc MDSS_AXI_CLK>, 1484 <&mmcc MDSS_VSYNC_CLK>, 1485 <&mmcc MDSS_MDP_CLK>; 1486 clock-names = "iface", 1487 "bus", 1488 "vsync", 1489 "core"; 1490 1491 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 1492 1493 interrupt-controller; 1494 #interrupt-cells = <1>; 1495 1496 #address-cells = <1>; 1497 #size-cells = <1>; 1498 ranges; 1499 status = "disabled"; 1500 1501 mdp: display-controller@c901000 { 1502 compatible = "qcom,sdm630-mdp5", "qcom,mdp5"; 1503 reg = <0x0c901000 0x89000>; 1504 reg-names = "mdp_phys"; 1505 1506 interrupt-parent = <&mdss>; 1507 interrupts = <0>; 1508 1509 assigned-clocks = <&mmcc MDSS_MDP_CLK>, 1510 <&mmcc MDSS_VSYNC_CLK>; 1511 assigned-clock-rates = <300000000>, 1512 <19200000>; 1513 clocks = <&mmcc MDSS_AHB_CLK>, 1514 <&mmcc MDSS_AXI_CLK>, 1515 <&mmcc MDSS_MDP_CLK>, 1516 <&mmcc MDSS_VSYNC_CLK>; 1517 clock-names = "iface", 1518 "bus", 1519 "core", 1520 "vsync"; 1521 1522 interconnects = <&mnoc 2 &bimc 5>, 1523 <&mnoc 3 &bimc 5>, 1524 <&gnoc 0 &mnoc 17>; 1525 interconnect-names = "mdp0-mem", 1526 "mdp1-mem", 1527 "rotator-mem"; 1528 iommus = <&mmss_smmu 0>; 1529 operating-points-v2 = <&mdp_opp_table>; 1530 power-domains = <&rpmpd SDM660_VDDCX>; 1531 1532 ports { 1533 #address-cells = <1>; 1534 #size-cells = <0>; 1535 1536 port@0 { 1537 reg = <0>; 1538 mdp5_intf1_out: endpoint { 1539 remote-endpoint = <&dsi0_in>; 1540 }; 1541 }; 1542 }; 1543 1544 mdp_opp_table: opp-table { 1545 compatible = "operating-points-v2"; 1546 1547 opp-150000000 { 1548 opp-hz = /bits/ 64 <150000000>; 1549 opp-peak-kBps = <320000 320000 76800>; 1550 required-opps = <&rpmpd_opp_low_svs>; 1551 }; 1552 opp-275000000 { 1553 opp-hz = /bits/ 64 <275000000>; 1554 opp-peak-kBps = <6400000 6400000 160000>; 1555 required-opps = <&rpmpd_opp_svs>; 1556 }; 1557 opp-300000000 { 1558 opp-hz = /bits/ 64 <300000000>; 1559 opp-peak-kBps = <6400000 6400000 190000>; 1560 required-opps = <&rpmpd_opp_svs_plus>; 1561 }; 1562 opp-330000000 { 1563 opp-hz = /bits/ 64 <330000000>; 1564 opp-peak-kBps = <6400000 6400000 240000>; 1565 required-opps = <&rpmpd_opp_nom>; 1566 }; 1567 opp-412500000 { 1568 opp-hz = /bits/ 64 <412500000>; 1569 opp-peak-kBps = <6400000 6400000 320000>; 1570 required-opps = <&rpmpd_opp_turbo>; 1571 }; 1572 }; 1573 }; 1574 1575 dsi0: dsi@c994000 { 1576 compatible = "qcom,sdm660-dsi-ctrl", 1577 "qcom,mdss-dsi-ctrl"; 1578 reg = <0x0c994000 0x400>; 1579 reg-names = "dsi_ctrl"; 1580 1581 operating-points-v2 = <&dsi_opp_table>; 1582 power-domains = <&rpmpd SDM660_VDDCX>; 1583 1584 interrupt-parent = <&mdss>; 1585 interrupts = <4>; 1586 1587 assigned-clocks = <&mmcc BYTE0_CLK_SRC>, 1588 <&mmcc PCLK0_CLK_SRC>; 1589 assigned-clock-parents = <&dsi0_phy 0>, 1590 <&dsi0_phy 1>; 1591 1592 clocks = <&mmcc MDSS_MDP_CLK>, 1593 <&mmcc MDSS_BYTE0_CLK>, 1594 <&mmcc MDSS_BYTE0_INTF_CLK>, 1595 <&mmcc MNOC_AHB_CLK>, 1596 <&mmcc MDSS_AHB_CLK>, 1597 <&mmcc MDSS_AXI_CLK>, 1598 <&mmcc MISC_AHB_CLK>, 1599 <&mmcc MDSS_PCLK0_CLK>, 1600 <&mmcc MDSS_ESC0_CLK>; 1601 clock-names = "mdp_core", 1602 "byte", 1603 "byte_intf", 1604 "mnoc", 1605 "iface", 1606 "bus", 1607 "core_mmss", 1608 "pixel", 1609 "core"; 1610 1611 phys = <&dsi0_phy>; 1612 1613 status = "disabled"; 1614 1615 ports { 1616 #address-cells = <1>; 1617 #size-cells = <0>; 1618 1619 port@0 { 1620 reg = <0>; 1621 dsi0_in: endpoint { 1622 remote-endpoint = <&mdp5_intf1_out>; 1623 }; 1624 }; 1625 1626 port@1 { 1627 reg = <1>; 1628 dsi0_out: endpoint { 1629 }; 1630 }; 1631 }; 1632 }; 1633 1634 dsi0_phy: phy@c994400 { 1635 compatible = "qcom,dsi-phy-14nm-660"; 1636 reg = <0x0c994400 0x100>, 1637 <0x0c994500 0x300>, 1638 <0x0c994800 0x188>; 1639 reg-names = "dsi_phy", 1640 "dsi_phy_lane", 1641 "dsi_pll"; 1642 1643 #clock-cells = <1>; 1644 #phy-cells = <0>; 1645 1646 clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>; 1647 clock-names = "iface", "ref"; 1648 status = "disabled"; 1649 }; 1650 }; 1651 1652 blsp1_dma: dma-controller@c144000 { 1653 compatible = "qcom,bam-v1.7.0"; 1654 reg = <0x0c144000 0x1f000>; 1655 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 1656 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 1657 clock-names = "bam_clk"; 1658 #dma-cells = <1>; 1659 qcom,ee = <0>; 1660 qcom,controlled-remotely; 1661 num-channels = <18>; 1662 qcom,num-ees = <4>; 1663 }; 1664 1665 blsp1_uart1: serial@c16f000 { 1666 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1667 reg = <0x0c16f000 0x200>; 1668 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1669 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, 1670 <&gcc GCC_BLSP1_AHB_CLK>; 1671 clock-names = "core", "iface"; 1672 dmas = <&blsp1_dma 0>, <&blsp1_dma 1>; 1673 dma-names = "tx", "rx"; 1674 pinctrl-names = "default", "sleep"; 1675 pinctrl-0 = <&blsp1_uart1_default>; 1676 pinctrl-1 = <&blsp1_uart1_sleep>; 1677 status = "disabled"; 1678 }; 1679 1680 blsp1_uart2: serial@c170000 { 1681 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1682 reg = <0x0c170000 0x1000>; 1683 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1684 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, 1685 <&gcc GCC_BLSP1_AHB_CLK>; 1686 clock-names = "core", "iface"; 1687 dmas = <&blsp1_dma 2>, <&blsp1_dma 3>; 1688 dma-names = "tx", "rx"; 1689 pinctrl-names = "default"; 1690 pinctrl-0 = <&blsp1_uart2_default>; 1691 status = "disabled"; 1692 }; 1693 1694 blsp_i2c1: i2c@c175000 { 1695 compatible = "qcom,i2c-qup-v2.2.1"; 1696 reg = <0x0c175000 0x600>; 1697 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1698 1699 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, 1700 <&gcc GCC_BLSP1_AHB_CLK>; 1701 clock-names = "core", "iface"; 1702 clock-frequency = <400000>; 1703 dmas = <&blsp1_dma 4>, <&blsp1_dma 5>; 1704 dma-names = "tx", "rx"; 1705 1706 pinctrl-names = "default", "sleep"; 1707 pinctrl-0 = <&i2c1_default>; 1708 pinctrl-1 = <&i2c1_sleep>; 1709 #address-cells = <1>; 1710 #size-cells = <0>; 1711 status = "disabled"; 1712 }; 1713 1714 blsp_i2c2: i2c@c176000 { 1715 compatible = "qcom,i2c-qup-v2.2.1"; 1716 reg = <0x0c176000 0x600>; 1717 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1718 1719 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 1720 <&gcc GCC_BLSP1_AHB_CLK>; 1721 clock-names = "core", "iface"; 1722 clock-frequency = <400000>; 1723 dmas = <&blsp1_dma 6>, <&blsp1_dma 7>; 1724 dma-names = "tx", "rx"; 1725 1726 pinctrl-names = "default", "sleep"; 1727 pinctrl-0 = <&i2c2_default>; 1728 pinctrl-1 = <&i2c2_sleep>; 1729 #address-cells = <1>; 1730 #size-cells = <0>; 1731 status = "disabled"; 1732 }; 1733 1734 blsp_i2c3: i2c@c177000 { 1735 compatible = "qcom,i2c-qup-v2.2.1"; 1736 reg = <0x0c177000 0x600>; 1737 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1738 1739 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 1740 <&gcc GCC_BLSP1_AHB_CLK>; 1741 clock-names = "core", "iface"; 1742 clock-frequency = <400000>; 1743 dmas = <&blsp1_dma 8>, <&blsp1_dma 9>; 1744 dma-names = "tx", "rx"; 1745 1746 pinctrl-names = "default", "sleep"; 1747 pinctrl-0 = <&i2c3_default>; 1748 pinctrl-1 = <&i2c3_sleep>; 1749 #address-cells = <1>; 1750 #size-cells = <0>; 1751 status = "disabled"; 1752 }; 1753 1754 blsp_i2c4: i2c@c178000 { 1755 compatible = "qcom,i2c-qup-v2.2.1"; 1756 reg = <0x0c178000 0x600>; 1757 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1758 1759 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, 1760 <&gcc GCC_BLSP1_AHB_CLK>; 1761 clock-names = "core", "iface"; 1762 clock-frequency = <400000>; 1763 dmas = <&blsp1_dma 10>, <&blsp1_dma 11>; 1764 dma-names = "tx", "rx"; 1765 1766 pinctrl-names = "default", "sleep"; 1767 pinctrl-0 = <&i2c4_default>; 1768 pinctrl-1 = <&i2c4_sleep>; 1769 #address-cells = <1>; 1770 #size-cells = <0>; 1771 status = "disabled"; 1772 }; 1773 1774 blsp2_dma: dma-controller@c184000 { 1775 compatible = "qcom,bam-v1.7.0"; 1776 reg = <0x0c184000 0x1f000>; 1777 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 1778 clocks = <&gcc GCC_BLSP2_AHB_CLK>; 1779 clock-names = "bam_clk"; 1780 #dma-cells = <1>; 1781 qcom,ee = <0>; 1782 qcom,controlled-remotely; 1783 num-channels = <18>; 1784 qcom,num-ees = <4>; 1785 }; 1786 1787 blsp2_uart1: serial@c1af000 { 1788 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1789 reg = <0x0c1af000 0x200>; 1790 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 1791 clocks = <&gcc GCC_BLSP2_UART1_APPS_CLK>, 1792 <&gcc GCC_BLSP2_AHB_CLK>; 1793 clock-names = "core", "iface"; 1794 dmas = <&blsp2_dma 0>, <&blsp2_dma 1>; 1795 dma-names = "tx", "rx"; 1796 pinctrl-names = "default", "sleep"; 1797 pinctrl-0 = <&blsp2_uart1_default>; 1798 pinctrl-1 = <&blsp2_uart1_sleep>; 1799 status = "disabled"; 1800 }; 1801 1802 blsp_i2c5: i2c@c1b5000 { 1803 compatible = "qcom,i2c-qup-v2.2.1"; 1804 reg = <0x0c1b5000 0x600>; 1805 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 1806 1807 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, 1808 <&gcc GCC_BLSP2_AHB_CLK>; 1809 clock-names = "core", "iface"; 1810 clock-frequency = <400000>; 1811 dmas = <&blsp2_dma 4>, <&blsp2_dma 5>; 1812 dma-names = "tx", "rx"; 1813 1814 pinctrl-names = "default", "sleep"; 1815 pinctrl-0 = <&i2c5_default>; 1816 pinctrl-1 = <&i2c5_sleep>; 1817 #address-cells = <1>; 1818 #size-cells = <0>; 1819 status = "disabled"; 1820 }; 1821 1822 blsp_i2c6: i2c@c1b6000 { 1823 compatible = "qcom,i2c-qup-v2.2.1"; 1824 reg = <0x0c1b6000 0x600>; 1825 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 1826 1827 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, 1828 <&gcc GCC_BLSP2_AHB_CLK>; 1829 clock-names = "core", "iface"; 1830 clock-frequency = <400000>; 1831 dmas = <&blsp2_dma 6>, <&blsp2_dma 7>; 1832 dma-names = "tx", "rx"; 1833 1834 pinctrl-names = "default", "sleep"; 1835 pinctrl-0 = <&i2c6_default>; 1836 pinctrl-1 = <&i2c6_sleep>; 1837 #address-cells = <1>; 1838 #size-cells = <0>; 1839 status = "disabled"; 1840 }; 1841 1842 blsp_i2c7: i2c@c1b7000 { 1843 compatible = "qcom,i2c-qup-v2.2.1"; 1844 reg = <0x0c1b7000 0x600>; 1845 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 1846 1847 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>, 1848 <&gcc GCC_BLSP2_AHB_CLK>; 1849 clock-names = "core", "iface"; 1850 clock-frequency = <400000>; 1851 dmas = <&blsp2_dma 8>, <&blsp2_dma 9>; 1852 dma-names = "tx", "rx"; 1853 1854 pinctrl-names = "default", "sleep"; 1855 pinctrl-0 = <&i2c7_default>; 1856 pinctrl-1 = <&i2c7_sleep>; 1857 #address-cells = <1>; 1858 #size-cells = <0>; 1859 status = "disabled"; 1860 }; 1861 1862 blsp_i2c8: i2c@c1b8000 { 1863 compatible = "qcom,i2c-qup-v2.2.1"; 1864 reg = <0x0c1b8000 0x600>; 1865 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 1866 1867 clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>, 1868 <&gcc GCC_BLSP2_AHB_CLK>; 1869 clock-names = "core", "iface"; 1870 clock-frequency = <400000>; 1871 dmas = <&blsp2_dma 10>, <&blsp2_dma 11>; 1872 dma-names = "tx", "rx"; 1873 1874 pinctrl-names = "default", "sleep"; 1875 pinctrl-0 = <&i2c8_default>; 1876 pinctrl-1 = <&i2c8_sleep>; 1877 #address-cells = <1>; 1878 #size-cells = <0>; 1879 status = "disabled"; 1880 }; 1881 1882 sram@146bf000 { 1883 compatible = "qcom,sdm630-imem", "syscon", "simple-mfd"; 1884 reg = <0x146bf000 0x1000>; 1885 1886 #address-cells = <1>; 1887 #size-cells = <1>; 1888 1889 ranges = <0 0x146bf000 0x1000>; 1890 1891 pil-reloc@94c { 1892 compatible = "qcom,pil-reloc-info"; 1893 reg = <0x94c 0xc8>; 1894 }; 1895 }; 1896 1897 camss: camss@ca00000 { 1898 compatible = "qcom,sdm660-camss"; 1899 reg = <0x0ca00020 0x10>, 1900 <0x0ca30000 0x100>, 1901 <0x0ca30400 0x100>, 1902 <0x0ca30800 0x100>, 1903 <0x0ca30c00 0x100>, 1904 <0x0c824000 0x1000>, 1905 <0x0ca00120 0x4>, 1906 <0x0c825000 0x1000>, 1907 <0x0ca00124 0x4>, 1908 <0x0c826000 0x1000>, 1909 <0x0ca00128 0x4>, 1910 <0x0ca31000 0x500>, 1911 <0x0ca10000 0x1000>, 1912 <0x0ca14000 0x1000>; 1913 reg-names = "csi_clk_mux", 1914 "csid0", 1915 "csid1", 1916 "csid2", 1917 "csid3", 1918 "csiphy0", 1919 "csiphy0_clk_mux", 1920 "csiphy1", 1921 "csiphy1_clk_mux", 1922 "csiphy2", 1923 "csiphy2_clk_mux", 1924 "ispif", 1925 "vfe0", 1926 "vfe1"; 1927 interrupts = <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>, 1928 <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>, 1929 <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>, 1930 <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>, 1931 <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>, 1932 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>, 1933 <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>, 1934 <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>, 1935 <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>, 1936 <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>; 1937 interrupt-names = "csid0", 1938 "csid1", 1939 "csid2", 1940 "csid3", 1941 "csiphy0", 1942 "csiphy1", 1943 "csiphy2", 1944 "ispif", 1945 "vfe0", 1946 "vfe1"; 1947 clocks = <&mmcc CAMSS_AHB_CLK>, 1948 <&mmcc CAMSS_CPHY_CSID0_CLK>, 1949 <&mmcc CAMSS_CPHY_CSID1_CLK>, 1950 <&mmcc CAMSS_CPHY_CSID2_CLK>, 1951 <&mmcc CAMSS_CPHY_CSID3_CLK>, 1952 <&mmcc CAMSS_CSI0_AHB_CLK>, 1953 <&mmcc CAMSS_CSI0_CLK>, 1954 <&mmcc CAMSS_CPHY_CSID0_CLK>, 1955 <&mmcc CAMSS_CSI0PIX_CLK>, 1956 <&mmcc CAMSS_CSI0RDI_CLK>, 1957 <&mmcc CAMSS_CSI1_AHB_CLK>, 1958 <&mmcc CAMSS_CSI1_CLK>, 1959 <&mmcc CAMSS_CPHY_CSID1_CLK>, 1960 <&mmcc CAMSS_CSI1PIX_CLK>, 1961 <&mmcc CAMSS_CSI1RDI_CLK>, 1962 <&mmcc CAMSS_CSI2_AHB_CLK>, 1963 <&mmcc CAMSS_CSI2_CLK>, 1964 <&mmcc CAMSS_CPHY_CSID2_CLK>, 1965 <&mmcc CAMSS_CSI2PIX_CLK>, 1966 <&mmcc CAMSS_CSI2RDI_CLK>, 1967 <&mmcc CAMSS_CSI3_AHB_CLK>, 1968 <&mmcc CAMSS_CSI3_CLK>, 1969 <&mmcc CAMSS_CPHY_CSID3_CLK>, 1970 <&mmcc CAMSS_CSI3PIX_CLK>, 1971 <&mmcc CAMSS_CSI3RDI_CLK>, 1972 <&mmcc CAMSS_CSI0PHYTIMER_CLK>, 1973 <&mmcc CAMSS_CSI1PHYTIMER_CLK>, 1974 <&mmcc CAMSS_CSI2PHYTIMER_CLK>, 1975 <&mmcc CSIPHY_AHB2CRIF_CLK>, 1976 <&mmcc CAMSS_CSI_VFE0_CLK>, 1977 <&mmcc CAMSS_CSI_VFE1_CLK>, 1978 <&mmcc CAMSS_ISPIF_AHB_CLK>, 1979 <&mmcc THROTTLE_CAMSS_AXI_CLK>, 1980 <&mmcc CAMSS_TOP_AHB_CLK>, 1981 <&mmcc CAMSS_VFE0_AHB_CLK>, 1982 <&mmcc CAMSS_VFE0_CLK>, 1983 <&mmcc CAMSS_VFE0_STREAM_CLK>, 1984 <&mmcc CAMSS_VFE1_AHB_CLK>, 1985 <&mmcc CAMSS_VFE1_CLK>, 1986 <&mmcc CAMSS_VFE1_STREAM_CLK>, 1987 <&mmcc CAMSS_VFE_VBIF_AHB_CLK>, 1988 <&mmcc CAMSS_VFE_VBIF_AXI_CLK>; 1989 clock-names = "ahb", 1990 "cphy_csid0", 1991 "cphy_csid1", 1992 "cphy_csid2", 1993 "cphy_csid3", 1994 "csi0_ahb", 1995 "csi0", 1996 "csi0_phy", 1997 "csi0_pix", 1998 "csi0_rdi", 1999 "csi1_ahb", 2000 "csi1", 2001 "csi1_phy", 2002 "csi1_pix", 2003 "csi1_rdi", 2004 "csi2_ahb", 2005 "csi2", 2006 "csi2_phy", 2007 "csi2_pix", 2008 "csi2_rdi", 2009 "csi3_ahb", 2010 "csi3", 2011 "csi3_phy", 2012 "csi3_pix", 2013 "csi3_rdi", 2014 "csiphy0_timer", 2015 "csiphy1_timer", 2016 "csiphy2_timer", 2017 "csiphy_ahb2crif", 2018 "csi_vfe0", 2019 "csi_vfe1", 2020 "ispif_ahb", 2021 "throttle_axi", 2022 "top_ahb", 2023 "vfe0_ahb", 2024 "vfe0", 2025 "vfe0_stream", 2026 "vfe1_ahb", 2027 "vfe1", 2028 "vfe1_stream", 2029 "vfe_ahb", 2030 "vfe_axi"; 2031 interconnects = <&mnoc 5 &bimc 5>; 2032 interconnect-names = "vfe-mem"; 2033 iommus = <&mmss_smmu 0xc00>, 2034 <&mmss_smmu 0xc01>, 2035 <&mmss_smmu 0xc02>, 2036 <&mmss_smmu 0xc03>; 2037 power-domains = <&mmcc CAMSS_VFE0_GDSC>, 2038 <&mmcc CAMSS_VFE1_GDSC>; 2039 status = "disabled"; 2040 2041 ports { 2042 #address-cells = <1>; 2043 #size-cells = <0>; 2044 }; 2045 }; 2046 2047 cci: cci@ca0c000 { 2048 compatible = "qcom,msm8996-cci"; 2049 #address-cells = <1>; 2050 #size-cells = <0>; 2051 reg = <0x0ca0c000 0x1000>; 2052 interrupts = <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>; 2053 2054 assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>, 2055 <&mmcc CAMSS_CCI_CLK>; 2056 assigned-clock-rates = <80800000>, <37500000>; 2057 clocks = <&mmcc CAMSS_TOP_AHB_CLK>, 2058 <&mmcc CAMSS_CCI_AHB_CLK>, 2059 <&mmcc CAMSS_CCI_CLK>, 2060 <&mmcc CAMSS_AHB_CLK>; 2061 clock-names = "camss_top_ahb", 2062 "cci_ahb", 2063 "cci", 2064 "camss_ahb"; 2065 2066 pinctrl-names = "default"; 2067 pinctrl-0 = <&cci0_default &cci1_default>; 2068 power-domains = <&mmcc CAMSS_TOP_GDSC>; 2069 status = "disabled"; 2070 2071 cci_i2c0: i2c-bus@0 { 2072 reg = <0>; 2073 clock-frequency = <400000>; 2074 #address-cells = <1>; 2075 #size-cells = <0>; 2076 }; 2077 2078 cci_i2c1: i2c-bus@1 { 2079 reg = <1>; 2080 clock-frequency = <400000>; 2081 #address-cells = <1>; 2082 #size-cells = <0>; 2083 }; 2084 }; 2085 2086 venus: video-codec@cc00000 { 2087 compatible = "qcom,sdm660-venus"; 2088 reg = <0x0cc00000 0xff000>; 2089 clocks = <&mmcc VIDEO_CORE_CLK>, 2090 <&mmcc VIDEO_AHB_CLK>, 2091 <&mmcc VIDEO_AXI_CLK>, 2092 <&mmcc THROTTLE_VIDEO_AXI_CLK>; 2093 clock-names = "core", "iface", "bus", "bus_throttle"; 2094 interconnects = <&gnoc 0 &mnoc 13>, 2095 <&mnoc 4 &bimc 5>; 2096 interconnect-names = "cpu-cfg", "video-mem"; 2097 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 2098 iommus = <&mmss_smmu 0x400>, 2099 <&mmss_smmu 0x401>, 2100 <&mmss_smmu 0x40a>, 2101 <&mmss_smmu 0x407>, 2102 <&mmss_smmu 0x40e>, 2103 <&mmss_smmu 0x40f>, 2104 <&mmss_smmu 0x408>, 2105 <&mmss_smmu 0x409>, 2106 <&mmss_smmu 0x40b>, 2107 <&mmss_smmu 0x40c>, 2108 <&mmss_smmu 0x40d>, 2109 <&mmss_smmu 0x410>, 2110 <&mmss_smmu 0x421>, 2111 <&mmss_smmu 0x428>, 2112 <&mmss_smmu 0x429>, 2113 <&mmss_smmu 0x42b>, 2114 <&mmss_smmu 0x42c>, 2115 <&mmss_smmu 0x42d>, 2116 <&mmss_smmu 0x411>, 2117 <&mmss_smmu 0x431>; 2118 memory-region = <&venus_region>; 2119 power-domains = <&mmcc VENUS_GDSC>; 2120 status = "disabled"; 2121 2122 video-decoder { 2123 compatible = "venus-decoder"; 2124 clocks = <&mmcc VIDEO_SUBCORE0_CLK>; 2125 clock-names = "vcodec0_core"; 2126 power-domains = <&mmcc VENUS_CORE0_GDSC>; 2127 }; 2128 2129 video-encoder { 2130 compatible = "venus-encoder"; 2131 clocks = <&mmcc VIDEO_SUBCORE0_CLK>; 2132 clock-names = "vcodec0_core"; 2133 power-domains = <&mmcc VENUS_CORE0_GDSC>; 2134 }; 2135 }; 2136 2137 mmss_smmu: iommu@cd00000 { 2138 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2"; 2139 reg = <0x0cd00000 0x40000>; 2140 2141 clocks = <&mmcc MNOC_AHB_CLK>, 2142 <&mmcc BIMC_SMMU_AHB_CLK>, 2143 <&rpmcc RPM_SMD_MMSSNOC_AXI_CLK>, 2144 <&mmcc BIMC_SMMU_AXI_CLK>; 2145 clock-names = "iface-mm", "iface-smmu", 2146 "bus-mm", "bus-smmu"; 2147 #global-interrupts = <2>; 2148 #iommu-cells = <1>; 2149 2150 interrupts = 2151 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 2152 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 2153 2154 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 2155 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 2156 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, 2157 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 2158 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 2159 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 2160 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 2161 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 2162 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 2163 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 2164 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 2165 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 2166 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 2167 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 2168 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 2169 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 2170 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 2171 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 2172 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 2173 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, 2174 <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, 2175 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 2176 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 2177 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>; 2178 2179 status = "disabled"; 2180 }; 2181 2182 adsp_pil: remoteproc@15700000 { 2183 compatible = "qcom,sdm660-adsp-pas"; 2184 reg = <0x15700000 0x4040>; 2185 2186 interrupts-extended = 2187 <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 2188 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2189 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2190 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2191 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2192 interrupt-names = "wdog", "fatal", "ready", 2193 "handover", "stop-ack"; 2194 2195 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 2196 clock-names = "xo"; 2197 2198 memory-region = <&adsp_region>; 2199 power-domains = <&rpmpd SDM660_VDDCX>; 2200 power-domain-names = "cx"; 2201 2202 qcom,smem-states = <&adsp_smp2p_out 0>; 2203 qcom,smem-state-names = "stop"; 2204 2205 glink-edge { 2206 interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>; 2207 2208 label = "lpass"; 2209 mboxes = <&apcs_glb 9>; 2210 qcom,remote-pid = <2>; 2211 2212 apr { 2213 compatible = "qcom,apr-v2"; 2214 qcom,glink-channels = "apr_audio_svc"; 2215 qcom,domain = <APR_DOMAIN_ADSP>; 2216 #address-cells = <1>; 2217 #size-cells = <0>; 2218 2219 service@3 { 2220 reg = <APR_SVC_ADSP_CORE>; 2221 compatible = "qcom,q6core"; 2222 }; 2223 2224 q6afe: service@4 { 2225 compatible = "qcom,q6afe"; 2226 reg = <APR_SVC_AFE>; 2227 q6afedai: dais { 2228 compatible = "qcom,q6afe-dais"; 2229 #address-cells = <1>; 2230 #size-cells = <0>; 2231 #sound-dai-cells = <1>; 2232 }; 2233 }; 2234 2235 q6asm: service@7 { 2236 compatible = "qcom,q6asm"; 2237 reg = <APR_SVC_ASM>; 2238 q6asmdai: dais { 2239 compatible = "qcom,q6asm-dais"; 2240 #address-cells = <1>; 2241 #size-cells = <0>; 2242 #sound-dai-cells = <1>; 2243 iommus = <&lpass_smmu 1>; 2244 }; 2245 }; 2246 2247 q6adm: service@8 { 2248 compatible = "qcom,q6adm"; 2249 reg = <APR_SVC_ADM>; 2250 q6routing: routing { 2251 compatible = "qcom,q6adm-routing"; 2252 #sound-dai-cells = <0>; 2253 }; 2254 }; 2255 }; 2256 }; 2257 }; 2258 2259 gnoc: interconnect@17900000 { 2260 compatible = "qcom,sdm660-gnoc"; 2261 reg = <0x17900000 0xe000>; 2262 #interconnect-cells = <1>; 2263 /* 2264 * This one apparently features no clocks, 2265 * so let's not mess with the driver needlessly 2266 */ 2267 clock-names = "bus", "bus_a"; 2268 clocks = <&xo_board>, <&xo_board>; 2269 }; 2270 2271 apcs_glb: mailbox@17911000 { 2272 compatible = "qcom,sdm660-apcs-hmss-global", 2273 "qcom,msm8994-apcs-kpss-global"; 2274 reg = <0x17911000 0x1000>; 2275 2276 #mbox-cells = <1>; 2277 }; 2278 2279 timer@17920000 { 2280 #address-cells = <1>; 2281 #size-cells = <1>; 2282 ranges; 2283 compatible = "arm,armv7-timer-mem"; 2284 reg = <0x17920000 0x1000>; 2285 clock-frequency = <19200000>; 2286 2287 frame@17921000 { 2288 frame-number = <0>; 2289 interrupts = <0 8 0x4>, 2290 <0 7 0x4>; 2291 reg = <0x17921000 0x1000>, 2292 <0x17922000 0x1000>; 2293 }; 2294 2295 frame@17923000 { 2296 frame-number = <1>; 2297 interrupts = <0 9 0x4>; 2298 reg = <0x17923000 0x1000>; 2299 status = "disabled"; 2300 }; 2301 2302 frame@17924000 { 2303 frame-number = <2>; 2304 interrupts = <0 10 0x4>; 2305 reg = <0x17924000 0x1000>; 2306 status = "disabled"; 2307 }; 2308 2309 frame@17925000 { 2310 frame-number = <3>; 2311 interrupts = <0 11 0x4>; 2312 reg = <0x17925000 0x1000>; 2313 status = "disabled"; 2314 }; 2315 2316 frame@17926000 { 2317 frame-number = <4>; 2318 interrupts = <0 12 0x4>; 2319 reg = <0x17926000 0x1000>; 2320 status = "disabled"; 2321 }; 2322 2323 frame@17927000 { 2324 frame-number = <5>; 2325 interrupts = <0 13 0x4>; 2326 reg = <0x17927000 0x1000>; 2327 status = "disabled"; 2328 }; 2329 2330 frame@17928000 { 2331 frame-number = <6>; 2332 interrupts = <0 14 0x4>; 2333 reg = <0x17928000 0x1000>; 2334 status = "disabled"; 2335 }; 2336 }; 2337 2338 intc: interrupt-controller@17a00000 { 2339 compatible = "arm,gic-v3"; 2340 reg = <0x17a00000 0x10000>, /* GICD */ 2341 <0x17b00000 0x100000>; /* GICR * 8 */ 2342 #interrupt-cells = <3>; 2343 #address-cells = <1>; 2344 #size-cells = <1>; 2345 ranges; 2346 interrupt-controller; 2347 #redistributor-regions = <1>; 2348 redistributor-stride = <0x0 0x20000>; 2349 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 2350 }; 2351 }; 2352 2353 sound: sound { 2354 }; 2355 2356 thermal-zones { 2357 aoss-thermal { 2358 polling-delay-passive = <250>; 2359 polling-delay = <1000>; 2360 2361 thermal-sensors = <&tsens 0>; 2362 2363 trips { 2364 aoss_alert0: trip-point0 { 2365 temperature = <105000>; 2366 hysteresis = <1000>; 2367 type = "hot"; 2368 }; 2369 }; 2370 }; 2371 2372 cpuss0-thermal { 2373 polling-delay-passive = <250>; 2374 polling-delay = <1000>; 2375 2376 thermal-sensors = <&tsens 1>; 2377 2378 trips { 2379 cpuss0_alert0: trip-point0 { 2380 temperature = <125000>; 2381 hysteresis = <1000>; 2382 type = "hot"; 2383 }; 2384 }; 2385 }; 2386 2387 cpuss1-thermal { 2388 polling-delay-passive = <250>; 2389 polling-delay = <1000>; 2390 2391 thermal-sensors = <&tsens 2>; 2392 2393 trips { 2394 cpuss1_alert0: trip-point0 { 2395 temperature = <125000>; 2396 hysteresis = <1000>; 2397 type = "hot"; 2398 }; 2399 }; 2400 }; 2401 2402 cpu0-thermal { 2403 polling-delay-passive = <250>; 2404 polling-delay = <1000>; 2405 2406 thermal-sensors = <&tsens 3>; 2407 2408 trips { 2409 cpu0_alert0: trip-point0 { 2410 temperature = <70000>; 2411 hysteresis = <1000>; 2412 type = "passive"; 2413 }; 2414 2415 cpu0_crit: cpu-crit { 2416 temperature = <110000>; 2417 hysteresis = <1000>; 2418 type = "critical"; 2419 }; 2420 }; 2421 }; 2422 2423 cpu1-thermal { 2424 polling-delay-passive = <250>; 2425 polling-delay = <1000>; 2426 2427 thermal-sensors = <&tsens 4>; 2428 2429 trips { 2430 cpu1_alert0: trip-point0 { 2431 temperature = <70000>; 2432 hysteresis = <1000>; 2433 type = "passive"; 2434 }; 2435 2436 cpu1_crit: cpu-crit { 2437 temperature = <110000>; 2438 hysteresis = <1000>; 2439 type = "critical"; 2440 }; 2441 }; 2442 }; 2443 2444 cpu2-thermal { 2445 polling-delay-passive = <250>; 2446 polling-delay = <1000>; 2447 2448 thermal-sensors = <&tsens 5>; 2449 2450 trips { 2451 cpu2_alert0: trip-point0 { 2452 temperature = <70000>; 2453 hysteresis = <1000>; 2454 type = "passive"; 2455 }; 2456 2457 cpu2_crit: cpu-crit { 2458 temperature = <110000>; 2459 hysteresis = <1000>; 2460 type = "critical"; 2461 }; 2462 }; 2463 }; 2464 2465 cpu3-thermal { 2466 polling-delay-passive = <250>; 2467 polling-delay = <1000>; 2468 2469 thermal-sensors = <&tsens 6>; 2470 2471 trips { 2472 cpu3_alert0: trip-point0 { 2473 temperature = <70000>; 2474 hysteresis = <1000>; 2475 type = "passive"; 2476 }; 2477 2478 cpu3_crit: cpu-crit { 2479 temperature = <110000>; 2480 hysteresis = <1000>; 2481 type = "critical"; 2482 }; 2483 }; 2484 }; 2485 2486 /* 2487 * According to what downstream DTS says, 2488 * the entire power efficient cluster has 2489 * only a single thermal sensor. 2490 */ 2491 2492 pwr-cluster-thermal { 2493 polling-delay-passive = <250>; 2494 polling-delay = <1000>; 2495 2496 thermal-sensors = <&tsens 7>; 2497 2498 trips { 2499 pwr_cluster_alert0: trip-point0 { 2500 temperature = <70000>; 2501 hysteresis = <1000>; 2502 type = "passive"; 2503 }; 2504 2505 pwr_cluster_crit: cpu-crit { 2506 temperature = <110000>; 2507 hysteresis = <1000>; 2508 type = "critical"; 2509 }; 2510 }; 2511 }; 2512 2513 gpu-thermal { 2514 polling-delay-passive = <250>; 2515 polling-delay = <1000>; 2516 2517 thermal-sensors = <&tsens 8>; 2518 2519 trips { 2520 gpu_alert0: trip-point0 { 2521 temperature = <90000>; 2522 hysteresis = <1000>; 2523 type = "hot"; 2524 }; 2525 }; 2526 }; 2527 }; 2528 2529 timer { 2530 compatible = "arm,armv8-timer"; 2531 interrupts = <GIC_PPI 1 0xf08>, 2532 <GIC_PPI 2 0xf08>, 2533 <GIC_PPI 3 0xf08>, 2534 <GIC_PPI 0 0xf08>; 2535 }; 2536}; 2537 2538