1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2020, Konrad Dybcio <konradybcio@gmail.com> 4 * Copyright (c) 2020, AngeloGioacchino Del Regno <kholk11@gmail.com> 5 */ 6 7#include <dt-bindings/clock/qcom,gcc-sdm660.h> 8#include <dt-bindings/clock/qcom,gpucc-sdm660.h> 9#include <dt-bindings/clock/qcom,mmcc-sdm660.h> 10#include <dt-bindings/clock/qcom,rpmcc.h> 11#include <dt-bindings/power/qcom-rpmpd.h> 12#include <dt-bindings/gpio/gpio.h> 13#include <dt-bindings/interrupt-controller/arm-gic.h> 14#include <dt-bindings/soc/qcom,apr.h> 15 16/ { 17 interrupt-parent = <&intc>; 18 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 chosen { }; 23 24 clocks { 25 xo_board: xo-board { 26 compatible = "fixed-clock"; 27 #clock-cells = <0>; 28 clock-frequency = <19200000>; 29 clock-output-names = "xo_board"; 30 }; 31 32 sleep_clk: sleep-clk { 33 compatible = "fixed-clock"; 34 #clock-cells = <0>; 35 clock-frequency = <32764>; 36 clock-output-names = "sleep_clk"; 37 }; 38 }; 39 40 cpus { 41 #address-cells = <2>; 42 #size-cells = <0>; 43 44 CPU0: cpu@100 { 45 device_type = "cpu"; 46 compatible = "arm,cortex-a53"; 47 reg = <0x0 0x100>; 48 enable-method = "psci"; 49 cpu-idle-states = <&PERF_CPU_SLEEP_0 50 &PERF_CPU_SLEEP_1 51 &PERF_CLUSTER_SLEEP_0 52 &PERF_CLUSTER_SLEEP_1 53 &PERF_CLUSTER_SLEEP_2>; 54 capacity-dmips-mhz = <1126>; 55 #cooling-cells = <2>; 56 next-level-cache = <&L2_1>; 57 L2_1: l2-cache { 58 compatible = "cache"; 59 cache-level = <2>; 60 }; 61 }; 62 63 CPU1: cpu@101 { 64 device_type = "cpu"; 65 compatible = "arm,cortex-a53"; 66 reg = <0x0 0x101>; 67 enable-method = "psci"; 68 cpu-idle-states = <&PERF_CPU_SLEEP_0 69 &PERF_CPU_SLEEP_1 70 &PERF_CLUSTER_SLEEP_0 71 &PERF_CLUSTER_SLEEP_1 72 &PERF_CLUSTER_SLEEP_2>; 73 capacity-dmips-mhz = <1126>; 74 #cooling-cells = <2>; 75 next-level-cache = <&L2_1>; 76 }; 77 78 CPU2: cpu@102 { 79 device_type = "cpu"; 80 compatible = "arm,cortex-a53"; 81 reg = <0x0 0x102>; 82 enable-method = "psci"; 83 cpu-idle-states = <&PERF_CPU_SLEEP_0 84 &PERF_CPU_SLEEP_1 85 &PERF_CLUSTER_SLEEP_0 86 &PERF_CLUSTER_SLEEP_1 87 &PERF_CLUSTER_SLEEP_2>; 88 capacity-dmips-mhz = <1126>; 89 #cooling-cells = <2>; 90 next-level-cache = <&L2_1>; 91 }; 92 93 CPU3: cpu@103 { 94 device_type = "cpu"; 95 compatible = "arm,cortex-a53"; 96 reg = <0x0 0x103>; 97 enable-method = "psci"; 98 cpu-idle-states = <&PERF_CPU_SLEEP_0 99 &PERF_CPU_SLEEP_1 100 &PERF_CLUSTER_SLEEP_0 101 &PERF_CLUSTER_SLEEP_1 102 &PERF_CLUSTER_SLEEP_2>; 103 capacity-dmips-mhz = <1126>; 104 #cooling-cells = <2>; 105 next-level-cache = <&L2_1>; 106 }; 107 108 CPU4: cpu@0 { 109 device_type = "cpu"; 110 compatible = "arm,cortex-a53"; 111 reg = <0x0 0x0>; 112 enable-method = "psci"; 113 cpu-idle-states = <&PWR_CPU_SLEEP_0 114 &PWR_CPU_SLEEP_1 115 &PWR_CLUSTER_SLEEP_0 116 &PWR_CLUSTER_SLEEP_1 117 &PWR_CLUSTER_SLEEP_2>; 118 capacity-dmips-mhz = <1024>; 119 #cooling-cells = <2>; 120 next-level-cache = <&L2_0>; 121 L2_0: l2-cache { 122 compatible = "cache"; 123 cache-level = <2>; 124 }; 125 }; 126 127 CPU5: cpu@1 { 128 device_type = "cpu"; 129 compatible = "arm,cortex-a53"; 130 reg = <0x0 0x1>; 131 enable-method = "psci"; 132 cpu-idle-states = <&PWR_CPU_SLEEP_0 133 &PWR_CPU_SLEEP_1 134 &PWR_CLUSTER_SLEEP_0 135 &PWR_CLUSTER_SLEEP_1 136 &PWR_CLUSTER_SLEEP_2>; 137 capacity-dmips-mhz = <1024>; 138 #cooling-cells = <2>; 139 next-level-cache = <&L2_0>; 140 }; 141 142 CPU6: cpu@2 { 143 device_type = "cpu"; 144 compatible = "arm,cortex-a53"; 145 reg = <0x0 0x2>; 146 enable-method = "psci"; 147 cpu-idle-states = <&PWR_CPU_SLEEP_0 148 &PWR_CPU_SLEEP_1 149 &PWR_CLUSTER_SLEEP_0 150 &PWR_CLUSTER_SLEEP_1 151 &PWR_CLUSTER_SLEEP_2>; 152 capacity-dmips-mhz = <1024>; 153 #cooling-cells = <2>; 154 next-level-cache = <&L2_0>; 155 }; 156 157 CPU7: cpu@3 { 158 device_type = "cpu"; 159 compatible = "arm,cortex-a53"; 160 reg = <0x0 0x3>; 161 enable-method = "psci"; 162 cpu-idle-states = <&PWR_CPU_SLEEP_0 163 &PWR_CPU_SLEEP_1 164 &PWR_CLUSTER_SLEEP_0 165 &PWR_CLUSTER_SLEEP_1 166 &PWR_CLUSTER_SLEEP_2>; 167 capacity-dmips-mhz = <1024>; 168 #cooling-cells = <2>; 169 next-level-cache = <&L2_0>; 170 }; 171 172 cpu-map { 173 cluster0 { 174 core0 { 175 cpu = <&CPU4>; 176 }; 177 178 core1 { 179 cpu = <&CPU5>; 180 }; 181 182 core2 { 183 cpu = <&CPU6>; 184 }; 185 186 core3 { 187 cpu = <&CPU7>; 188 }; 189 }; 190 191 cluster1 { 192 core0 { 193 cpu = <&CPU0>; 194 }; 195 196 core1 { 197 cpu = <&CPU1>; 198 }; 199 200 core2 { 201 cpu = <&CPU2>; 202 }; 203 204 core3 { 205 cpu = <&CPU3>; 206 }; 207 }; 208 }; 209 210 idle-states { 211 entry-method = "psci"; 212 213 PWR_CPU_SLEEP_0: cpu-sleep-0-0 { 214 compatible = "arm,idle-state"; 215 idle-state-name = "pwr-retention"; 216 arm,psci-suspend-param = <0x40000002>; 217 entry-latency-us = <338>; 218 exit-latency-us = <423>; 219 min-residency-us = <200>; 220 }; 221 222 PWR_CPU_SLEEP_1: cpu-sleep-0-1 { 223 compatible = "arm,idle-state"; 224 idle-state-name = "pwr-power-collapse"; 225 arm,psci-suspend-param = <0x40000003>; 226 entry-latency-us = <515>; 227 exit-latency-us = <1821>; 228 min-residency-us = <1000>; 229 local-timer-stop; 230 }; 231 232 PERF_CPU_SLEEP_0: cpu-sleep-1-0 { 233 compatible = "arm,idle-state"; 234 idle-state-name = "perf-retention"; 235 arm,psci-suspend-param = <0x40000002>; 236 entry-latency-us = <154>; 237 exit-latency-us = <87>; 238 min-residency-us = <200>; 239 }; 240 241 PERF_CPU_SLEEP_1: cpu-sleep-1-1 { 242 compatible = "arm,idle-state"; 243 idle-state-name = "perf-power-collapse"; 244 arm,psci-suspend-param = <0x40000003>; 245 entry-latency-us = <262>; 246 exit-latency-us = <301>; 247 min-residency-us = <1000>; 248 local-timer-stop; 249 }; 250 251 PWR_CLUSTER_SLEEP_0: cluster-sleep-0-0 { 252 compatible = "arm,idle-state"; 253 idle-state-name = "pwr-cluster-dynamic-retention"; 254 arm,psci-suspend-param = <0x400000F2>; 255 entry-latency-us = <284>; 256 exit-latency-us = <384>; 257 min-residency-us = <9987>; 258 local-timer-stop; 259 }; 260 261 PWR_CLUSTER_SLEEP_1: cluster-sleep-0-1 { 262 compatible = "arm,idle-state"; 263 idle-state-name = "pwr-cluster-retention"; 264 arm,psci-suspend-param = <0x400000F3>; 265 entry-latency-us = <338>; 266 exit-latency-us = <423>; 267 min-residency-us = <9987>; 268 local-timer-stop; 269 }; 270 271 PWR_CLUSTER_SLEEP_2: cluster-sleep-0-2 { 272 compatible = "arm,idle-state"; 273 idle-state-name = "pwr-cluster-retention"; 274 arm,psci-suspend-param = <0x400000F4>; 275 entry-latency-us = <515>; 276 exit-latency-us = <1821>; 277 min-residency-us = <9987>; 278 local-timer-stop; 279 }; 280 281 PERF_CLUSTER_SLEEP_0: cluster-sleep-1-0 { 282 compatible = "arm,idle-state"; 283 idle-state-name = "perf-cluster-dynamic-retention"; 284 arm,psci-suspend-param = <0x400000F2>; 285 entry-latency-us = <272>; 286 exit-latency-us = <329>; 287 min-residency-us = <9987>; 288 local-timer-stop; 289 }; 290 291 PERF_CLUSTER_SLEEP_1: cluster-sleep-1-1 { 292 compatible = "arm,idle-state"; 293 idle-state-name = "perf-cluster-retention"; 294 arm,psci-suspend-param = <0x400000F3>; 295 entry-latency-us = <332>; 296 exit-latency-us = <368>; 297 min-residency-us = <9987>; 298 local-timer-stop; 299 }; 300 301 PERF_CLUSTER_SLEEP_2: cluster-sleep-1-2 { 302 compatible = "arm,idle-state"; 303 idle-state-name = "perf-cluster-retention"; 304 arm,psci-suspend-param = <0x400000F4>; 305 entry-latency-us = <545>; 306 exit-latency-us = <1609>; 307 min-residency-us = <9987>; 308 local-timer-stop; 309 }; 310 }; 311 }; 312 313 firmware { 314 scm { 315 compatible = "qcom,scm-msm8998", "qcom,scm"; 316 }; 317 }; 318 319 memory@80000000 { 320 device_type = "memory"; 321 /* We expect the bootloader to fill in the reg */ 322 reg = <0x0 0x80000000 0x0 0x0>; 323 }; 324 325 pmu { 326 compatible = "arm,armv8-pmuv3"; 327 interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>; 328 }; 329 330 psci { 331 compatible = "arm,psci-1.0"; 332 method = "smc"; 333 }; 334 335 reserved-memory { 336 #address-cells = <2>; 337 #size-cells = <2>; 338 ranges; 339 340 wlan_msa_guard: wlan-msa-guard@85600000 { 341 reg = <0x0 0x85600000 0x0 0x100000>; 342 no-map; 343 }; 344 345 wlan_msa_mem: wlan-msa-mem@85700000 { 346 reg = <0x0 0x85700000 0x0 0x100000>; 347 no-map; 348 }; 349 350 qhee_code: qhee-code@85800000 { 351 reg = <0x0 0x85800000 0x0 0x600000>; 352 no-map; 353 }; 354 355 rmtfs_mem: memory@85e00000 { 356 compatible = "qcom,rmtfs-mem"; 357 reg = <0x0 0x85e00000 0x0 0x200000>; 358 no-map; 359 360 qcom,client-id = <1>; 361 qcom,vmid = <15>; 362 }; 363 364 smem_region: smem-mem@86000000 { 365 reg = <0 0x86000000 0 0x200000>; 366 no-map; 367 }; 368 369 tz_mem: memory@86200000 { 370 reg = <0x0 0x86200000 0x0 0x3300000>; 371 no-map; 372 }; 373 374 mpss_region: mpss@8ac00000 { 375 reg = <0x0 0x8ac00000 0x0 0x7e00000>; 376 no-map; 377 }; 378 379 adsp_region: adsp@92a00000 { 380 reg = <0x0 0x92a00000 0x0 0x1e00000>; 381 no-map; 382 }; 383 384 mba_region: mba@94800000 { 385 reg = <0x0 0x94800000 0x0 0x200000>; 386 no-map; 387 }; 388 389 buffer_mem: tzbuffer@94a00000 { 390 reg = <0x0 0x94a00000 0x0 0x100000>; 391 no-map; 392 }; 393 394 venus_region: venus@9f800000 { 395 reg = <0x0 0x9f800000 0x0 0x800000>; 396 no-map; 397 }; 398 399 adsp_mem: adsp-region@f6000000 { 400 reg = <0x0 0xf6000000 0x0 0x800000>; 401 no-map; 402 }; 403 404 qseecom_mem: qseecom-region@f6800000 { 405 reg = <0x0 0xf6800000 0x0 0x1400000>; 406 no-map; 407 }; 408 409 zap_shader_region: gpu@fed00000 { 410 compatible = "shared-dma-pool"; 411 reg = <0x0 0xfed00000 0x0 0xa00000>; 412 no-map; 413 }; 414 }; 415 416 rpm-glink { 417 compatible = "qcom,glink-rpm"; 418 419 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 420 qcom,rpm-msg-ram = <&rpm_msg_ram>; 421 mboxes = <&apcs_glb 0>; 422 423 rpm_requests: rpm-requests { 424 compatible = "qcom,rpm-sdm660"; 425 qcom,glink-channels = "rpm_requests"; 426 427 rpmcc: clock-controller { 428 compatible = "qcom,rpmcc-sdm660", "qcom,rpmcc"; 429 #clock-cells = <1>; 430 }; 431 432 rpmpd: power-controller { 433 compatible = "qcom,sdm660-rpmpd"; 434 #power-domain-cells = <1>; 435 operating-points-v2 = <&rpmpd_opp_table>; 436 437 rpmpd_opp_table: opp-table { 438 compatible = "operating-points-v2"; 439 440 rpmpd_opp_ret: opp1 { 441 opp-level = <RPM_SMD_LEVEL_RETENTION>; 442 }; 443 444 rpmpd_opp_ret_plus: opp2 { 445 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>; 446 }; 447 448 rpmpd_opp_min_svs: opp3 { 449 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 450 }; 451 452 rpmpd_opp_low_svs: opp4 { 453 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 454 }; 455 456 rpmpd_opp_svs: opp5 { 457 opp-level = <RPM_SMD_LEVEL_SVS>; 458 }; 459 460 rpmpd_opp_svs_plus: opp6 { 461 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 462 }; 463 464 rpmpd_opp_nom: opp7 { 465 opp-level = <RPM_SMD_LEVEL_NOM>; 466 }; 467 468 rpmpd_opp_nom_plus: opp8 { 469 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 470 }; 471 472 rpmpd_opp_turbo: opp9 { 473 opp-level = <RPM_SMD_LEVEL_TURBO>; 474 }; 475 }; 476 }; 477 }; 478 }; 479 480 smem: smem { 481 compatible = "qcom,smem"; 482 memory-region = <&smem_region>; 483 hwlocks = <&tcsr_mutex 3>; 484 }; 485 486 smp2p-adsp { 487 compatible = "qcom,smp2p"; 488 qcom,smem = <443>, <429>; 489 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 490 mboxes = <&apcs_glb 10>; 491 qcom,local-pid = <0>; 492 qcom,remote-pid = <2>; 493 494 adsp_smp2p_out: master-kernel { 495 qcom,entry-name = "master-kernel"; 496 #qcom,smem-state-cells = <1>; 497 }; 498 499 adsp_smp2p_in: slave-kernel { 500 qcom,entry-name = "slave-kernel"; 501 interrupt-controller; 502 #interrupt-cells = <2>; 503 }; 504 }; 505 506 smp2p-mpss { 507 compatible = "qcom,smp2p"; 508 qcom,smem = <435>, <428>; 509 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 510 mboxes = <&apcs_glb 14>; 511 qcom,local-pid = <0>; 512 qcom,remote-pid = <1>; 513 514 modem_smp2p_out: master-kernel { 515 qcom,entry-name = "master-kernel"; 516 #qcom,smem-state-cells = <1>; 517 }; 518 519 modem_smp2p_in: slave-kernel { 520 qcom,entry-name = "slave-kernel"; 521 interrupt-controller; 522 #interrupt-cells = <2>; 523 }; 524 }; 525 526 soc { 527 #address-cells = <1>; 528 #size-cells = <1>; 529 ranges = <0 0 0 0xffffffff>; 530 compatible = "simple-bus"; 531 532 gcc: clock-controller@100000 { 533 compatible = "qcom,gcc-sdm630"; 534 #clock-cells = <1>; 535 #reset-cells = <1>; 536 #power-domain-cells = <1>; 537 reg = <0x00100000 0x94000>; 538 539 clock-names = "xo", "sleep_clk"; 540 clocks = <&xo_board>, 541 <&sleep_clk>; 542 }; 543 544 rpm_msg_ram: memory@778000 { 545 compatible = "qcom,rpm-msg-ram"; 546 reg = <0x00778000 0x7000>; 547 }; 548 549 qfprom: qfprom@780000 { 550 compatible = "qcom,qfprom"; 551 reg = <0x00780000 0x621c>; 552 #address-cells = <1>; 553 #size-cells = <1>; 554 555 qusb2_hstx_trim: hstx-trim@240 { 556 reg = <0x240 0x1>; 557 bits = <25 3>; 558 }; 559 560 gpu_speed_bin: gpu-speed-bin@41a0 { 561 reg = <0x41a0 0x1>; 562 bits = <21 7>; 563 }; 564 }; 565 566 rng: rng@793000 { 567 compatible = "qcom,prng-ee"; 568 reg = <0x00793000 0x1000>; 569 clocks = <&gcc GCC_PRNG_AHB_CLK>; 570 clock-names = "core"; 571 }; 572 573 bimc: interconnect@1008000 { 574 compatible = "qcom,sdm660-bimc"; 575 reg = <0x01008000 0x78000>; 576 #interconnect-cells = <1>; 577 clock-names = "bus", "bus_a"; 578 clocks = <&rpmcc RPM_SMD_BIMC_CLK>, 579 <&rpmcc RPM_SMD_BIMC_A_CLK>; 580 }; 581 582 restart@10ac000 { 583 compatible = "qcom,pshold"; 584 reg = <0x010ac000 0x4>; 585 }; 586 587 cnoc: interconnect@1500000 { 588 compatible = "qcom,sdm660-cnoc"; 589 reg = <0x01500000 0x10000>; 590 #interconnect-cells = <1>; 591 clock-names = "bus", "bus_a"; 592 clocks = <&rpmcc RPM_SMD_CNOC_CLK>, 593 <&rpmcc RPM_SMD_CNOC_A_CLK>; 594 }; 595 596 snoc: interconnect@1626000 { 597 compatible = "qcom,sdm660-snoc"; 598 reg = <0x01626000 0x7090>; 599 #interconnect-cells = <1>; 600 clock-names = "bus", "bus_a"; 601 clocks = <&rpmcc RPM_SMD_SNOC_CLK>, 602 <&rpmcc RPM_SMD_SNOC_A_CLK>; 603 }; 604 605 anoc2_smmu: iommu@16c0000 { 606 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2"; 607 reg = <0x016c0000 0x40000>; 608 609 assigned-clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>; 610 assigned-clock-rates = <1000>; 611 clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>; 612 clock-names = "bus"; 613 #global-interrupts = <2>; 614 #iommu-cells = <1>; 615 616 interrupts = 617 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 618 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 619 620 <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>, 621 <GIC_SPI 374 IRQ_TYPE_LEVEL_LOW>, 622 <GIC_SPI 375 IRQ_TYPE_LEVEL_LOW>, 623 <GIC_SPI 376 IRQ_TYPE_LEVEL_LOW>, 624 <GIC_SPI 377 IRQ_TYPE_LEVEL_LOW>, 625 <GIC_SPI 378 IRQ_TYPE_LEVEL_LOW>, 626 <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>, 627 <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>, 628 <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>, 629 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>, 630 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>, 631 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>, 632 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>, 633 <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, 634 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>, 635 <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>, 636 <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>, 637 <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, 638 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, 639 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, 640 <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>, 641 <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>, 642 <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, 643 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>, 644 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>, 645 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>, 646 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, 647 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, 648 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>; 649 650 status = "disabled"; 651 }; 652 653 a2noc: interconnect@1704000 { 654 compatible = "qcom,sdm660-a2noc"; 655 reg = <0x01704000 0xc100>; 656 #interconnect-cells = <1>; 657 clock-names = "bus", "bus_a"; 658 clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>, 659 <&rpmcc RPM_SMD_AGGR2_NOC_A_CLK>; 660 }; 661 662 mnoc: interconnect@1745000 { 663 compatible = "qcom,sdm660-mnoc"; 664 reg = <0x01745000 0xA010>; 665 #interconnect-cells = <1>; 666 clock-names = "bus", "bus_a", "iface"; 667 clocks = <&rpmcc RPM_SMD_MMSSNOC_AXI_CLK>, 668 <&rpmcc RPM_SMD_MMSSNOC_AXI_CLK_A>, 669 <&mmcc AHB_CLK_SRC>; 670 }; 671 672 tsens: thermal-sensor@10ae000 { 673 compatible = "qcom,sdm630-tsens", "qcom,tsens-v2"; 674 reg = <0x010ae000 0x1000>, /* TM */ 675 <0x010ad000 0x1000>; /* SROT */ 676 #qcom,sensors = <12>; 677 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 678 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>; 679 interrupt-names = "uplow", "critical"; 680 #thermal-sensor-cells = <1>; 681 }; 682 683 tcsr_mutex_regs: syscon@1f40000 { 684 compatible = "syscon"; 685 reg = <0x01f40000 0x40000>; 686 }; 687 688 tlmm: pinctrl@3100000 { 689 compatible = "qcom,sdm630-pinctrl"; 690 reg = <0x03100000 0x400000>, 691 <0x03500000 0x400000>, 692 <0x03900000 0x400000>; 693 reg-names = "south", "center", "north"; 694 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 695 gpio-controller; 696 gpio-ranges = <&tlmm 0 0 114>; 697 #gpio-cells = <2>; 698 interrupt-controller; 699 #interrupt-cells = <2>; 700 701 blsp1_uart1_default: blsp1-uart1-default { 702 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 703 drive-strength = <2>; 704 bias-disable; 705 }; 706 707 blsp1_uart1_sleep: blsp1-uart1-sleep { 708 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 709 drive-strength = <2>; 710 bias-disable; 711 }; 712 713 blsp1_uart2_default: blsp1-uart2-default { 714 pins = "gpio4", "gpio5"; 715 drive-strength = <2>; 716 bias-disable; 717 }; 718 719 blsp2_uart1_default: blsp2-uart1-active { 720 tx-rts { 721 pins = "gpio16", "gpio19"; 722 function = "blsp_uart5"; 723 drive-strength = <2>; 724 bias-disable; 725 }; 726 727 rx { 728 /* 729 * Avoid garbage data while BT module 730 * is powered off or not driving signal 731 */ 732 pins = "gpio17"; 733 function = "blsp_uart5"; 734 drive-strength = <2>; 735 bias-pull-up; 736 }; 737 738 cts { 739 /* Match the pull of the BT module */ 740 pins = "gpio18"; 741 function = "blsp_uart5"; 742 drive-strength = <2>; 743 bias-pull-down; 744 }; 745 }; 746 747 blsp2_uart1_sleep: blsp2-uart1-sleep { 748 tx { 749 pins = "gpio16"; 750 function = "gpio"; 751 drive-strength = <2>; 752 bias-pull-up; 753 }; 754 755 rx-cts-rts { 756 pins = "gpio17", "gpio18", "gpio19"; 757 function = "gpio"; 758 drive-strength = <2>; 759 bias-no-pull; 760 }; 761 }; 762 763 i2c1_default: i2c1-default { 764 pins = "gpio2", "gpio3"; 765 function = "blsp_i2c1"; 766 drive-strength = <2>; 767 bias-disable; 768 }; 769 770 i2c1_sleep: i2c1-sleep { 771 pins = "gpio2", "gpio3"; 772 function = "blsp_i2c1"; 773 drive-strength = <2>; 774 bias-pull-up; 775 }; 776 777 i2c2_default: i2c2-default { 778 pins = "gpio6", "gpio7"; 779 function = "blsp_i2c2"; 780 drive-strength = <2>; 781 bias-disable; 782 }; 783 784 i2c2_sleep: i2c2-sleep { 785 pins = "gpio6", "gpio7"; 786 function = "blsp_i2c2"; 787 drive-strength = <2>; 788 bias-pull-up; 789 }; 790 791 i2c3_default: i2c3-default { 792 pins = "gpio10", "gpio11"; 793 function = "blsp_i2c3"; 794 drive-strength = <2>; 795 bias-disable; 796 }; 797 798 i2c3_sleep: i2c3-sleep { 799 pins = "gpio10", "gpio11"; 800 function = "blsp_i2c3"; 801 drive-strength = <2>; 802 bias-pull-up; 803 }; 804 805 i2c4_default: i2c4-default { 806 pins = "gpio14", "gpio15"; 807 function = "blsp_i2c4"; 808 drive-strength = <2>; 809 bias-disable; 810 }; 811 812 i2c4_sleep: i2c4-sleep { 813 pins = "gpio14", "gpio15"; 814 function = "blsp_i2c4"; 815 drive-strength = <2>; 816 bias-pull-up; 817 }; 818 819 i2c5_default: i2c5-default { 820 pins = "gpio18", "gpio19"; 821 function = "blsp_i2c5"; 822 drive-strength = <2>; 823 bias-disable; 824 }; 825 826 i2c5_sleep: i2c5-sleep { 827 pins = "gpio18", "gpio19"; 828 function = "blsp_i2c5"; 829 drive-strength = <2>; 830 bias-pull-up; 831 }; 832 833 i2c6_default: i2c6-default { 834 pins = "gpio22", "gpio23"; 835 function = "blsp_i2c6"; 836 drive-strength = <2>; 837 bias-disable; 838 }; 839 840 i2c6_sleep: i2c6-sleep { 841 pins = "gpio22", "gpio23"; 842 function = "blsp_i2c6"; 843 drive-strength = <2>; 844 bias-pull-up; 845 }; 846 847 i2c7_default: i2c7-default { 848 pins = "gpio26", "gpio27"; 849 function = "blsp_i2c7"; 850 drive-strength = <2>; 851 bias-disable; 852 }; 853 854 i2c7_sleep: i2c7-sleep { 855 pins = "gpio26", "gpio27"; 856 function = "blsp_i2c7"; 857 drive-strength = <2>; 858 bias-pull-up; 859 }; 860 861 i2c8_default: i2c8-default { 862 pins = "gpio30", "gpio31"; 863 function = "blsp_i2c8"; 864 drive-strength = <2>; 865 bias-disable; 866 }; 867 868 i2c8_sleep: i2c8-sleep { 869 pins = "gpio30", "gpio31"; 870 function = "blsp_i2c8"; 871 drive-strength = <2>; 872 bias-pull-up; 873 }; 874 875 cci0_default: cci0_default { 876 pinmux { 877 pins = "gpio36","gpio37"; 878 function = "cci_i2c"; 879 }; 880 881 pinconf { 882 pins = "gpio36","gpio37"; 883 bias-pull-up; 884 drive-strength = <2>; 885 }; 886 }; 887 888 cci1_default: cci1_default { 889 pinmux { 890 pins = "gpio38","gpio39"; 891 function = "cci_i2c"; 892 }; 893 894 pinconf { 895 pins = "gpio38","gpio39"; 896 bias-pull-up; 897 drive-strength = <2>; 898 }; 899 }; 900 901 sdc1_state_on: sdc1-on { 902 clk { 903 pins = "sdc1_clk"; 904 bias-disable; 905 drive-strength = <16>; 906 }; 907 908 cmd { 909 pins = "sdc1_cmd"; 910 bias-pull-up; 911 drive-strength = <10>; 912 }; 913 914 data { 915 pins = "sdc1_data"; 916 bias-pull-up; 917 drive-strength = <10>; 918 }; 919 920 rclk { 921 pins = "sdc1_rclk"; 922 bias-pull-down; 923 }; 924 }; 925 926 sdc1_state_off: sdc1-off { 927 clk { 928 pins = "sdc1_clk"; 929 bias-disable; 930 drive-strength = <2>; 931 }; 932 933 cmd { 934 pins = "sdc1_cmd"; 935 bias-pull-up; 936 drive-strength = <2>; 937 }; 938 939 data { 940 pins = "sdc1_data"; 941 bias-pull-up; 942 drive-strength = <2>; 943 }; 944 945 rclk { 946 pins = "sdc1_rclk"; 947 bias-pull-down; 948 }; 949 }; 950 951 sdc2_state_on: sdc2-on { 952 clk { 953 pins = "sdc2_clk"; 954 bias-disable; 955 drive-strength = <16>; 956 }; 957 958 cmd { 959 pins = "sdc2_cmd"; 960 bias-pull-up; 961 drive-strength = <10>; 962 }; 963 964 data { 965 pins = "sdc2_data"; 966 bias-pull-up; 967 drive-strength = <10>; 968 }; 969 970 sd-cd { 971 pins = "gpio54"; 972 bias-pull-up; 973 drive-strength = <2>; 974 }; 975 }; 976 977 sdc2_state_off: sdc2-off { 978 clk { 979 pins = "sdc2_clk"; 980 bias-disable; 981 drive-strength = <2>; 982 }; 983 984 cmd { 985 pins = "sdc2_cmd"; 986 bias-pull-up; 987 drive-strength = <2>; 988 }; 989 990 data { 991 pins = "sdc2_data"; 992 bias-pull-up; 993 drive-strength = <2>; 994 }; 995 996 sd-cd { 997 pins = "gpio54"; 998 bias-disable; 999 drive-strength = <2>; 1000 }; 1001 }; 1002 }; 1003 1004 adreno_gpu: gpu@5000000 { 1005 compatible = "qcom,adreno-508.0", "qcom,adreno"; 1006 #stream-id-cells = <16>; 1007 1008 reg = <0x05000000 0x40000>; 1009 reg-names = "kgsl_3d0_reg_memory"; 1010 1011 interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>; 1012 1013 clocks = <&gcc GCC_GPU_CFG_AHB_CLK>, 1014 <&gpucc GPUCC_RBBMTIMER_CLK>, 1015 <&gcc GCC_BIMC_GFX_CLK>, 1016 <&gcc GCC_GPU_BIMC_GFX_CLK>, 1017 <&gpucc GPUCC_RBCPR_CLK>, 1018 <&gpucc GPUCC_GFX3D_CLK>; 1019 1020 clock-names = "iface", 1021 "rbbmtimer", 1022 "mem", 1023 "mem_iface", 1024 "rbcpr", 1025 "core"; 1026 1027 power-domains = <&rpmpd SDM660_VDDMX>; 1028 iommus = <&kgsl_smmu 0>; 1029 1030 nvmem-cells = <&gpu_speed_bin>; 1031 nvmem-cell-names = "speed_bin"; 1032 1033 interconnects = <&gnoc 1 &bimc 5>; 1034 interconnect-names = "gfx-mem"; 1035 1036 operating-points-v2 = <&gpu_sdm630_opp_table>; 1037 1038 gpu_sdm630_opp_table: opp-table { 1039 compatible = "operating-points-v2"; 1040 opp-775000000 { 1041 opp-hz = /bits/ 64 <775000000>; 1042 opp-level = <RPM_SMD_LEVEL_TURBO>; 1043 opp-peak-kBps = <5412000>; 1044 opp-supported-hw = <0xA2>; 1045 }; 1046 opp-647000000 { 1047 opp-hz = /bits/ 64 <647000000>; 1048 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 1049 opp-peak-kBps = <4068000>; 1050 opp-supported-hw = <0xFF>; 1051 }; 1052 opp-588000000 { 1053 opp-hz = /bits/ 64 <588000000>; 1054 opp-level = <RPM_SMD_LEVEL_NOM>; 1055 opp-peak-kBps = <3072000>; 1056 opp-supported-hw = <0xFF>; 1057 }; 1058 opp-465000000 { 1059 opp-hz = /bits/ 64 <465000000>; 1060 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 1061 opp-peak-kBps = <2724000>; 1062 opp-supported-hw = <0xFF>; 1063 }; 1064 opp-370000000 { 1065 opp-hz = /bits/ 64 <370000000>; 1066 opp-level = <RPM_SMD_LEVEL_SVS>; 1067 opp-peak-kBps = <2188000>; 1068 opp-supported-hw = <0xFF>; 1069 }; 1070 opp-240000000 { 1071 opp-hz = /bits/ 64 <240000000>; 1072 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 1073 opp-peak-kBps = <1648000>; 1074 opp-supported-hw = <0xFF>; 1075 }; 1076 opp-160000000 { 1077 opp-hz = /bits/ 64 <160000000>; 1078 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 1079 opp-peak-kBps = <1200000>; 1080 opp-supported-hw = <0xFF>; 1081 }; 1082 }; 1083 }; 1084 1085 kgsl_smmu: iommu@5040000 { 1086 compatible = "qcom,sdm630-smmu-v2", 1087 "qcom,adreno-smmu", "qcom,smmu-v2"; 1088 reg = <0x05040000 0x10000>; 1089 1090 /* 1091 * GX GDSC parent is CX. We need to bring up CX for SMMU 1092 * but we need both up for Adreno. On the other hand, we 1093 * need to manage the GX rpmpd domain in the adreno driver. 1094 * Enable CX/GX GDSCs here so that we can manage just the GX 1095 * RPM Power Domain in the Adreno driver. 1096 */ 1097 power-domains = <&gpucc GPU_GX_GDSC>; 1098 clocks = <&gcc GCC_GPU_CFG_AHB_CLK>, 1099 <&gcc GCC_BIMC_GFX_CLK>, 1100 <&gcc GCC_GPU_BIMC_GFX_CLK>; 1101 clock-names = "iface", "mem", "mem_iface"; 1102 #global-interrupts = <2>; 1103 #iommu-cells = <1>; 1104 1105 interrupts = 1106 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 1107 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 1108 1109 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 1110 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 1111 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 1112 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 1113 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1114 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1115 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>, 1116 <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>; 1117 1118 status = "disabled"; 1119 }; 1120 1121 gpucc: clock-controller@5065000 { 1122 compatible = "qcom,gpucc-sdm630"; 1123 #clock-cells = <1>; 1124 #reset-cells = <1>; 1125 #power-domain-cells = <1>; 1126 reg = <0x05065000 0x9038>; 1127 1128 clocks = <&xo_board>, 1129 <&gcc GCC_GPU_GPLL0_CLK>, 1130 <&gcc GCC_GPU_GPLL0_DIV_CLK>; 1131 clock-names = "xo", 1132 "gcc_gpu_gpll0_clk", 1133 "gcc_gpu_gpll0_div_clk"; 1134 status = "disabled"; 1135 }; 1136 1137 lpass_smmu: iommu@5100000 { 1138 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2"; 1139 reg = <0x05100000 0x40000>; 1140 #iommu-cells = <1>; 1141 1142 #global-interrupts = <2>; 1143 interrupts = 1144 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 1145 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 1146 1147 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, 1148 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>, 1149 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>, 1150 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 1151 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 1152 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 1153 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 1154 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 1155 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 1156 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 1157 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 1158 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 1159 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 1160 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, 1161 <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>, 1162 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 1163 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>; 1164 1165 status = "disabled"; 1166 }; 1167 1168 sram@290000 { 1169 compatible = "qcom,rpm-stats"; 1170 reg = <0x00290000 0x10000>; 1171 }; 1172 1173 spmi_bus: spmi@800f000 { 1174 compatible = "qcom,spmi-pmic-arb"; 1175 reg = <0x0800f000 0x1000>, 1176 <0x08400000 0x1000000>, 1177 <0x09400000 0x1000000>, 1178 <0x0a400000 0x220000>, 1179 <0x0800a000 0x3000>; 1180 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1181 interrupt-names = "periph_irq"; 1182 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>; 1183 qcom,ee = <0>; 1184 qcom,channel = <0>; 1185 #address-cells = <2>; 1186 #size-cells = <0>; 1187 interrupt-controller; 1188 #interrupt-cells = <4>; 1189 cell-index = <0>; 1190 }; 1191 1192 usb3: usb@a8f8800 { 1193 compatible = "qcom,sdm660-dwc3", "qcom,dwc3"; 1194 reg = <0x0a8f8800 0x400>; 1195 status = "disabled"; 1196 #address-cells = <1>; 1197 #size-cells = <1>; 1198 ranges; 1199 1200 clocks = <&gcc GCC_CFG_NOC_USB3_AXI_CLK>, 1201 <&gcc GCC_USB30_MASTER_CLK>, 1202 <&gcc GCC_AGGRE2_USB3_AXI_CLK>, 1203 <&rpmcc RPM_SMD_AGGR2_NOC_CLK>, 1204 <&gcc GCC_USB30_MOCK_UTMI_CLK>, 1205 <&gcc GCC_USB30_SLEEP_CLK>; 1206 clock-names = "cfg_noc", "core", "iface", "bus", 1207 "mock_utmi", "sleep"; 1208 1209 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, 1210 <&gcc GCC_USB30_MASTER_CLK>, 1211 <&rpmcc RPM_SMD_AGGR2_NOC_CLK>; 1212 assigned-clock-rates = <19200000>, <120000000>, 1213 <19200000>; 1214 1215 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, 1216 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 1217 interrupt-names = "hs_phy_irq", "ss_phy_irq"; 1218 1219 power-domains = <&gcc USB_30_GDSC>; 1220 qcom,select-utmi-as-pipe-clk; 1221 1222 resets = <&gcc GCC_USB_30_BCR>; 1223 1224 usb3_dwc3: usb@a800000 { 1225 compatible = "snps,dwc3"; 1226 reg = <0x0a800000 0xc8d0>; 1227 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 1228 snps,dis_u2_susphy_quirk; 1229 snps,dis_enblslpm_quirk; 1230 1231 /* 1232 * SDM630 technically supports USB3 but I 1233 * haven't seen any devices making use of it. 1234 */ 1235 maximum-speed = "high-speed"; 1236 phys = <&qusb2phy>; 1237 phy-names = "usb2-phy"; 1238 snps,hird-threshold = /bits/ 8 <0>; 1239 }; 1240 }; 1241 1242 qusb2phy: phy@c012000 { 1243 compatible = "qcom,sdm660-qusb2-phy"; 1244 reg = <0x0c012000 0x180>; 1245 #phy-cells = <0>; 1246 1247 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 1248 <&gcc GCC_RX1_USB2_CLKREF_CLK>; 1249 clock-names = "cfg_ahb", "ref"; 1250 1251 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 1252 nvmem-cells = <&qusb2_hstx_trim>; 1253 status = "disabled"; 1254 }; 1255 1256 sdhc_2: sdhci@c084000 { 1257 compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5"; 1258 reg = <0x0c084000 0x1000>; 1259 reg-names = "hc"; 1260 1261 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1262 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 1263 interrupt-names = "hc_irq", "pwr_irq"; 1264 1265 bus-width = <4>; 1266 clocks = <&gcc GCC_SDCC2_APPS_CLK>, 1267 <&gcc GCC_SDCC2_AHB_CLK>, 1268 <&xo_board>; 1269 clock-names = "core", "iface", "xo"; 1270 1271 interconnects = <&a2noc 3 &a2noc 10>, 1272 <&gnoc 0 &cnoc 28>; 1273 operating-points-v2 = <&sdhc2_opp_table>; 1274 1275 pinctrl-names = "default", "sleep"; 1276 pinctrl-0 = <&sdc2_state_on>; 1277 pinctrl-1 = <&sdc2_state_off>; 1278 power-domains = <&rpmpd SDM660_VDDCX>; 1279 1280 status = "disabled"; 1281 1282 sdhc2_opp_table: opp-table { 1283 compatible = "operating-points-v2"; 1284 1285 opp-50000000 { 1286 opp-hz = /bits/ 64 <50000000>; 1287 required-opps = <&rpmpd_opp_low_svs>; 1288 opp-peak-kBps = <200000 140000>; 1289 opp-avg-kBps = <130718 133320>; 1290 }; 1291 opp-100000000 { 1292 opp-hz = /bits/ 64 <100000000>; 1293 required-opps = <&rpmpd_opp_svs>; 1294 opp-peak-kBps = <250000 160000>; 1295 opp-avg-kBps = <196078 150000>; 1296 }; 1297 opp-200000000 { 1298 opp-hz = /bits/ 64 <200000000>; 1299 required-opps = <&rpmpd_opp_nom>; 1300 opp-peak-kBps = <4096000 4096000>; 1301 opp-avg-kBps = <1338562 1338562>; 1302 }; 1303 }; 1304 }; 1305 1306 sdhc_1: sdhci@c0c4000 { 1307 compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5"; 1308 reg = <0x0c0c4000 0x1000>, 1309 <0x0c0c5000 0x1000>, 1310 <0x0c0c8000 0x8000>; 1311 reg-names = "hc", "cqhci", "ice"; 1312 1313 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1314 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1315 interrupt-names = "hc_irq", "pwr_irq"; 1316 1317 clocks = <&gcc GCC_SDCC1_APPS_CLK>, 1318 <&gcc GCC_SDCC1_AHB_CLK>, 1319 <&xo_board>, 1320 <&gcc GCC_SDCC1_ICE_CORE_CLK>; 1321 clock-names = "core", "iface", "xo", "ice"; 1322 1323 interconnects = <&a2noc 2 &a2noc 10>, 1324 <&gnoc 0 &cnoc 27>; 1325 interconnect-names = "sdhc1-ddr", "cpu-sdhc1"; 1326 operating-points-v2 = <&sdhc1_opp_table>; 1327 pinctrl-names = "default", "sleep"; 1328 pinctrl-0 = <&sdc1_state_on>; 1329 pinctrl-1 = <&sdc1_state_off>; 1330 power-domains = <&rpmpd SDM660_VDDCX>; 1331 1332 bus-width = <8>; 1333 non-removable; 1334 1335 status = "disabled"; 1336 1337 sdhc1_opp_table: opp-table { 1338 compatible = "operating-points-v2"; 1339 1340 opp-50000000 { 1341 opp-hz = /bits/ 64 <50000000>; 1342 required-opps = <&rpmpd_opp_low_svs>; 1343 opp-peak-kBps = <200000 140000>; 1344 opp-avg-kBps = <130718 133320>; 1345 }; 1346 opp-100000000 { 1347 opp-hz = /bits/ 64 <100000000>; 1348 required-opps = <&rpmpd_opp_svs>; 1349 opp-peak-kBps = <250000 160000>; 1350 opp-avg-kBps = <196078 150000>; 1351 }; 1352 opp-384000000 { 1353 opp-hz = /bits/ 64 <384000000>; 1354 required-opps = <&rpmpd_opp_nom>; 1355 opp-peak-kBps = <4096000 4096000>; 1356 opp-avg-kBps = <1338562 1338562>; 1357 }; 1358 }; 1359 }; 1360 1361 mmcc: clock-controller@c8c0000 { 1362 compatible = "qcom,mmcc-sdm630"; 1363 reg = <0x0c8c0000 0x40000>; 1364 #clock-cells = <1>; 1365 #reset-cells = <1>; 1366 #power-domain-cells = <1>; 1367 clock-names = "xo", 1368 "sleep_clk", 1369 "gpll0", 1370 "gpll0_div", 1371 "dsi0pll", 1372 "dsi0pllbyte", 1373 "dsi1pll", 1374 "dsi1pllbyte", 1375 "dp_link_2x_clk_divsel_five", 1376 "dp_vco_divided_clk_src_mux"; 1377 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 1378 <&sleep_clk>, 1379 <&gcc GCC_MMSS_GPLL0_CLK>, 1380 <&gcc GCC_MMSS_GPLL0_DIV_CLK>, 1381 <&dsi0_phy 1>, 1382 <&dsi0_phy 0>, 1383 <0>, 1384 <0>, 1385 <0>, 1386 <0>; 1387 }; 1388 1389 dsi_opp_table: dsi-opp-table { 1390 compatible = "operating-points-v2"; 1391 1392 opp-131250000 { 1393 opp-hz = /bits/ 64 <131250000>; 1394 required-opps = <&rpmpd_opp_svs>; 1395 }; 1396 1397 opp-210000000 { 1398 opp-hz = /bits/ 64 <210000000>; 1399 required-opps = <&rpmpd_opp_svs_plus>; 1400 }; 1401 1402 opp-262500000 { 1403 opp-hz = /bits/ 64 <262500000>; 1404 required-opps = <&rpmpd_opp_nom>; 1405 }; 1406 }; 1407 1408 mdss: mdss@c900000 { 1409 compatible = "qcom,mdss"; 1410 reg = <0x0c900000 0x1000>, 1411 <0x0c9b0000 0x1040>; 1412 reg-names = "mdss_phys", "vbif_phys"; 1413 1414 power-domains = <&mmcc MDSS_GDSC>; 1415 1416 clocks = <&mmcc MDSS_AHB_CLK>, 1417 <&mmcc MDSS_AXI_CLK>, 1418 <&mmcc MDSS_VSYNC_CLK>, 1419 <&mmcc MDSS_MDP_CLK>; 1420 clock-names = "iface", 1421 "bus", 1422 "vsync", 1423 "core"; 1424 1425 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 1426 1427 interrupt-controller; 1428 #interrupt-cells = <1>; 1429 1430 #address-cells = <1>; 1431 #size-cells = <1>; 1432 ranges; 1433 status = "disabled"; 1434 1435 mdp: mdp@c901000 { 1436 compatible = "qcom,mdp5"; 1437 reg = <0x0c901000 0x89000>; 1438 reg-names = "mdp_phys"; 1439 1440 interrupt-parent = <&mdss>; 1441 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; 1442 1443 assigned-clocks = <&mmcc MDSS_MDP_CLK>, 1444 <&mmcc MDSS_VSYNC_CLK>; 1445 assigned-clock-rates = <300000000>, 1446 <19200000>; 1447 clocks = <&mmcc MDSS_AHB_CLK>, 1448 <&mmcc MDSS_AXI_CLK>, 1449 <&mmcc MDSS_MDP_CLK>, 1450 <&mmcc MDSS_VSYNC_CLK>; 1451 clock-names = "iface", 1452 "bus", 1453 "core", 1454 "vsync"; 1455 1456 interconnects = <&mnoc 2 &bimc 5>, 1457 <&mnoc 3 &bimc 5>, 1458 <&gnoc 0 &mnoc 17>; 1459 interconnect-names = "mdp0-mem", 1460 "mdp1-mem", 1461 "rotator-mem"; 1462 iommus = <&mmss_smmu 0>; 1463 operating-points-v2 = <&mdp_opp_table>; 1464 power-domains = <&rpmpd SDM660_VDDCX>; 1465 1466 ports { 1467 #address-cells = <1>; 1468 #size-cells = <0>; 1469 1470 port@0 { 1471 reg = <0>; 1472 mdp5_intf1_out: endpoint { 1473 remote-endpoint = <&dsi0_in>; 1474 }; 1475 }; 1476 }; 1477 1478 mdp_opp_table: mdp-opp { 1479 compatible = "operating-points-v2"; 1480 1481 opp-150000000 { 1482 opp-hz = /bits/ 64 <150000000>; 1483 opp-peak-kBps = <320000 320000 76800>; 1484 required-opps = <&rpmpd_opp_low_svs>; 1485 }; 1486 opp-275000000 { 1487 opp-hz = /bits/ 64 <275000000>; 1488 opp-peak-kBps = <6400000 6400000 160000>; 1489 required-opps = <&rpmpd_opp_svs>; 1490 }; 1491 opp-300000000 { 1492 opp-hz = /bits/ 64 <300000000>; 1493 opp-peak-kBps = <6400000 6400000 190000>; 1494 required-opps = <&rpmpd_opp_svs_plus>; 1495 }; 1496 opp-330000000 { 1497 opp-hz = /bits/ 64 <330000000>; 1498 opp-peak-kBps = <6400000 6400000 240000>; 1499 required-opps = <&rpmpd_opp_nom>; 1500 }; 1501 opp-412500000 { 1502 opp-hz = /bits/ 64 <412500000>; 1503 opp-peak-kBps = <6400000 6400000 320000>; 1504 required-opps = <&rpmpd_opp_turbo>; 1505 }; 1506 }; 1507 }; 1508 1509 dsi0: dsi@c994000 { 1510 compatible = "qcom,mdss-dsi-ctrl"; 1511 reg = <0x0c994000 0x400>; 1512 reg-names = "dsi_ctrl"; 1513 1514 operating-points-v2 = <&dsi_opp_table>; 1515 power-domains = <&rpmpd SDM660_VDDCX>; 1516 1517 interrupt-parent = <&mdss>; 1518 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; 1519 1520 assigned-clocks = <&mmcc BYTE0_CLK_SRC>, 1521 <&mmcc PCLK0_CLK_SRC>; 1522 assigned-clock-parents = <&dsi0_phy 0>, 1523 <&dsi0_phy 1>; 1524 1525 clocks = <&mmcc MDSS_MDP_CLK>, 1526 <&mmcc MDSS_BYTE0_CLK>, 1527 <&mmcc MDSS_BYTE0_INTF_CLK>, 1528 <&mmcc MNOC_AHB_CLK>, 1529 <&mmcc MDSS_AHB_CLK>, 1530 <&mmcc MDSS_AXI_CLK>, 1531 <&mmcc MISC_AHB_CLK>, 1532 <&mmcc MDSS_PCLK0_CLK>, 1533 <&mmcc MDSS_ESC0_CLK>; 1534 clock-names = "mdp_core", 1535 "byte", 1536 "byte_intf", 1537 "mnoc", 1538 "iface", 1539 "bus", 1540 "core_mmss", 1541 "pixel", 1542 "core"; 1543 1544 phys = <&dsi0_phy>; 1545 phy-names = "dsi"; 1546 1547 ports { 1548 #address-cells = <1>; 1549 #size-cells = <0>; 1550 1551 port@0 { 1552 reg = <0>; 1553 dsi0_in: endpoint { 1554 remote-endpoint = <&mdp5_intf1_out>; 1555 }; 1556 }; 1557 1558 port@1 { 1559 reg = <1>; 1560 dsi0_out: endpoint { 1561 }; 1562 }; 1563 }; 1564 }; 1565 1566 dsi0_phy: dsi-phy@c994400 { 1567 compatible = "qcom,dsi-phy-14nm-660"; 1568 reg = <0x0c994400 0x100>, 1569 <0x0c994500 0x300>, 1570 <0x0c994800 0x188>; 1571 reg-names = "dsi_phy", 1572 "dsi_phy_lane", 1573 "dsi_pll"; 1574 1575 #clock-cells = <1>; 1576 #phy-cells = <0>; 1577 1578 clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>; 1579 clock-names = "iface", "ref"; 1580 }; 1581 }; 1582 1583 blsp1_dma: dma-controller@c144000 { 1584 compatible = "qcom,bam-v1.7.0"; 1585 reg = <0x0c144000 0x1f000>; 1586 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 1587 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 1588 clock-names = "bam_clk"; 1589 #dma-cells = <1>; 1590 qcom,ee = <0>; 1591 qcom,controlled-remotely; 1592 num-channels = <18>; 1593 qcom,num-ees = <4>; 1594 }; 1595 1596 blsp1_uart1: serial@c16f000 { 1597 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1598 reg = <0x0c16f000 0x200>; 1599 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1600 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, 1601 <&gcc GCC_BLSP1_AHB_CLK>; 1602 clock-names = "core", "iface"; 1603 dmas = <&blsp1_dma 0>, <&blsp1_dma 1>; 1604 dma-names = "tx", "rx"; 1605 pinctrl-names = "default", "sleep"; 1606 pinctrl-0 = <&blsp1_uart1_default>; 1607 pinctrl-1 = <&blsp1_uart1_sleep>; 1608 status = "disabled"; 1609 }; 1610 1611 blsp1_uart2: serial@c170000 { 1612 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1613 reg = <0x0c170000 0x1000>; 1614 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1615 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, 1616 <&gcc GCC_BLSP1_AHB_CLK>; 1617 clock-names = "core", "iface"; 1618 dmas = <&blsp1_dma 2>, <&blsp1_dma 3>; 1619 dma-names = "tx", "rx"; 1620 pinctrl-names = "default"; 1621 pinctrl-0 = <&blsp1_uart2_default>; 1622 status = "disabled"; 1623 }; 1624 1625 blsp_i2c1: i2c@c175000 { 1626 compatible = "qcom,i2c-qup-v2.2.1"; 1627 reg = <0x0c175000 0x600>; 1628 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1629 1630 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, 1631 <&gcc GCC_BLSP1_AHB_CLK>; 1632 clock-names = "core", "iface"; 1633 clock-frequency = <400000>; 1634 dmas = <&blsp1_dma 4>, <&blsp1_dma 5>; 1635 dma-names = "tx", "rx"; 1636 1637 pinctrl-names = "default", "sleep"; 1638 pinctrl-0 = <&i2c1_default>; 1639 pinctrl-1 = <&i2c1_sleep>; 1640 #address-cells = <1>; 1641 #size-cells = <0>; 1642 status = "disabled"; 1643 }; 1644 1645 blsp_i2c2: i2c@c176000 { 1646 compatible = "qcom,i2c-qup-v2.2.1"; 1647 reg = <0x0c176000 0x600>; 1648 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1649 1650 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 1651 <&gcc GCC_BLSP1_AHB_CLK>; 1652 clock-names = "core", "iface"; 1653 clock-frequency = <400000>; 1654 dmas = <&blsp1_dma 6>, <&blsp1_dma 7>; 1655 dma-names = "tx", "rx"; 1656 1657 pinctrl-names = "default", "sleep"; 1658 pinctrl-0 = <&i2c2_default>; 1659 pinctrl-1 = <&i2c2_sleep>; 1660 #address-cells = <1>; 1661 #size-cells = <0>; 1662 status = "disabled"; 1663 }; 1664 1665 blsp_i2c3: i2c@c177000 { 1666 compatible = "qcom,i2c-qup-v2.2.1"; 1667 reg = <0x0c177000 0x600>; 1668 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1669 1670 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 1671 <&gcc GCC_BLSP1_AHB_CLK>; 1672 clock-names = "core", "iface"; 1673 clock-frequency = <400000>; 1674 dmas = <&blsp1_dma 8>, <&blsp1_dma 9>; 1675 dma-names = "tx", "rx"; 1676 1677 pinctrl-names = "default", "sleep"; 1678 pinctrl-0 = <&i2c3_default>; 1679 pinctrl-1 = <&i2c3_sleep>; 1680 #address-cells = <1>; 1681 #size-cells = <0>; 1682 status = "disabled"; 1683 }; 1684 1685 blsp_i2c4: i2c@c178000 { 1686 compatible = "qcom,i2c-qup-v2.2.1"; 1687 reg = <0x0c178000 0x600>; 1688 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1689 1690 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, 1691 <&gcc GCC_BLSP1_AHB_CLK>; 1692 clock-names = "core", "iface"; 1693 clock-frequency = <400000>; 1694 dmas = <&blsp1_dma 10>, <&blsp1_dma 11>; 1695 dma-names = "tx", "rx"; 1696 1697 pinctrl-names = "default", "sleep"; 1698 pinctrl-0 = <&i2c4_default>; 1699 pinctrl-1 = <&i2c4_sleep>; 1700 #address-cells = <1>; 1701 #size-cells = <0>; 1702 status = "disabled"; 1703 }; 1704 1705 blsp2_dma: dma-controller@c184000 { 1706 compatible = "qcom,bam-v1.7.0"; 1707 reg = <0x0c184000 0x1f000>; 1708 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 1709 clocks = <&gcc GCC_BLSP2_AHB_CLK>; 1710 clock-names = "bam_clk"; 1711 #dma-cells = <1>; 1712 qcom,ee = <0>; 1713 qcom,controlled-remotely; 1714 num-channels = <18>; 1715 qcom,num-ees = <4>; 1716 }; 1717 1718 blsp2_uart1: serial@c1af000 { 1719 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1720 reg = <0x0c1af000 0x200>; 1721 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 1722 clocks = <&gcc GCC_BLSP2_UART1_APPS_CLK>, 1723 <&gcc GCC_BLSP2_AHB_CLK>; 1724 clock-names = "core", "iface"; 1725 dmas = <&blsp2_dma 0>, <&blsp2_dma 1>; 1726 dma-names = "tx", "rx"; 1727 pinctrl-names = "default", "sleep"; 1728 pinctrl-0 = <&blsp2_uart1_default>; 1729 pinctrl-1 = <&blsp2_uart1_sleep>; 1730 status = "disabled"; 1731 }; 1732 1733 blsp_i2c5: i2c@c1b5000 { 1734 compatible = "qcom,i2c-qup-v2.2.1"; 1735 reg = <0x0c1b5000 0x600>; 1736 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 1737 1738 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, 1739 <&gcc GCC_BLSP2_AHB_CLK>; 1740 clock-names = "core", "iface"; 1741 clock-frequency = <400000>; 1742 dmas = <&blsp2_dma 4>, <&blsp2_dma 5>; 1743 dma-names = "tx", "rx"; 1744 1745 pinctrl-names = "default", "sleep"; 1746 pinctrl-0 = <&i2c5_default>; 1747 pinctrl-1 = <&i2c5_sleep>; 1748 #address-cells = <1>; 1749 #size-cells = <0>; 1750 status = "disabled"; 1751 }; 1752 1753 blsp_i2c6: i2c@c1b6000 { 1754 compatible = "qcom,i2c-qup-v2.2.1"; 1755 reg = <0x0c1b6000 0x600>; 1756 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 1757 1758 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, 1759 <&gcc GCC_BLSP2_AHB_CLK>; 1760 clock-names = "core", "iface"; 1761 clock-frequency = <400000>; 1762 dmas = <&blsp2_dma 6>, <&blsp2_dma 7>; 1763 dma-names = "tx", "rx"; 1764 1765 pinctrl-names = "default", "sleep"; 1766 pinctrl-0 = <&i2c6_default>; 1767 pinctrl-1 = <&i2c6_sleep>; 1768 #address-cells = <1>; 1769 #size-cells = <0>; 1770 status = "disabled"; 1771 }; 1772 1773 blsp_i2c7: i2c@c1b7000 { 1774 compatible = "qcom,i2c-qup-v2.2.1"; 1775 reg = <0x0c1b7000 0x600>; 1776 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 1777 1778 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>, 1779 <&gcc GCC_BLSP2_AHB_CLK>; 1780 clock-names = "core", "iface"; 1781 clock-frequency = <400000>; 1782 dmas = <&blsp2_dma 8>, <&blsp2_dma 9>; 1783 dma-names = "tx", "rx"; 1784 1785 pinctrl-names = "default", "sleep"; 1786 pinctrl-0 = <&i2c7_default>; 1787 pinctrl-1 = <&i2c7_sleep>; 1788 #address-cells = <1>; 1789 #size-cells = <0>; 1790 status = "disabled"; 1791 }; 1792 1793 blsp_i2c8: i2c@c1b8000 { 1794 compatible = "qcom,i2c-qup-v2.2.1"; 1795 reg = <0x0c1b8000 0x600>; 1796 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 1797 1798 clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>, 1799 <&gcc GCC_BLSP2_AHB_CLK>; 1800 clock-names = "core", "iface"; 1801 clock-frequency = <400000>; 1802 dmas = <&blsp2_dma 10>, <&blsp2_dma 11>; 1803 dma-names = "tx", "rx"; 1804 1805 pinctrl-names = "default", "sleep"; 1806 pinctrl-0 = <&i2c8_default>; 1807 pinctrl-1 = <&i2c8_sleep>; 1808 #address-cells = <1>; 1809 #size-cells = <0>; 1810 status = "disabled"; 1811 }; 1812 1813 imem@146bf000 { 1814 compatible = "simple-mfd"; 1815 reg = <0x146bf000 0x1000>; 1816 1817 #address-cells = <1>; 1818 #size-cells = <1>; 1819 1820 ranges = <0 0x146bf000 0x1000>; 1821 1822 pil-reloc@94c { 1823 compatible = "qcom,pil-reloc-info"; 1824 reg = <0x94c 0xc8>; 1825 }; 1826 }; 1827 1828 camss: camss@ca00000 { 1829 compatible = "qcom,sdm660-camss"; 1830 reg = <0x0c824000 0x1000>, 1831 <0x0ca00120 0x4>, 1832 <0x0c825000 0x1000>, 1833 <0x0ca00124 0x4>, 1834 <0x0c826000 0x1000>, 1835 <0x0ca00128 0x4>, 1836 <0x0ca30000 0x100>, 1837 <0x0ca30400 0x100>, 1838 <0x0ca30800 0x100>, 1839 <0x0ca30c00 0x100>, 1840 <0x0ca31000 0x500>, 1841 <0x0ca00020 0x10>, 1842 <0x0ca10000 0x1000>, 1843 <0x0ca14000 0x1000>; 1844 reg-names = "csiphy0", 1845 "csiphy0_clk_mux", 1846 "csiphy1", 1847 "csiphy1_clk_mux", 1848 "csiphy2", 1849 "csiphy2_clk_mux", 1850 "csid0", 1851 "csid1", 1852 "csid2", 1853 "csid3", 1854 "ispif", 1855 "csi_clk_mux", 1856 "vfe0", 1857 "vfe1"; 1858 interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>, 1859 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>, 1860 <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>, 1861 <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>, 1862 <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>, 1863 <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>, 1864 <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>, 1865 <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>, 1866 <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>, 1867 <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>; 1868 interrupt-names = "csiphy0", 1869 "csiphy1", 1870 "csiphy2", 1871 "csid0", 1872 "csid1", 1873 "csid2", 1874 "csid3", 1875 "ispif", 1876 "vfe0", 1877 "vfe1"; 1878 clocks = <&mmcc CAMSS_TOP_AHB_CLK>, 1879 <&mmcc THROTTLE_CAMSS_AXI_CLK>, 1880 <&mmcc CAMSS_ISPIF_AHB_CLK>, 1881 <&mmcc CAMSS_CSI0PHYTIMER_CLK>, 1882 <&mmcc CAMSS_CSI1PHYTIMER_CLK>, 1883 <&mmcc CAMSS_CSI2PHYTIMER_CLK>, 1884 <&mmcc CAMSS_CSI0_AHB_CLK>, 1885 <&mmcc CAMSS_CSI0_CLK>, 1886 <&mmcc CAMSS_CPHY_CSID0_CLK>, 1887 <&mmcc CAMSS_CSI0PIX_CLK>, 1888 <&mmcc CAMSS_CSI0RDI_CLK>, 1889 <&mmcc CAMSS_CSI1_AHB_CLK>, 1890 <&mmcc CAMSS_CSI1_CLK>, 1891 <&mmcc CAMSS_CPHY_CSID1_CLK>, 1892 <&mmcc CAMSS_CSI1PIX_CLK>, 1893 <&mmcc CAMSS_CSI1RDI_CLK>, 1894 <&mmcc CAMSS_CSI2_AHB_CLK>, 1895 <&mmcc CAMSS_CSI2_CLK>, 1896 <&mmcc CAMSS_CPHY_CSID2_CLK>, 1897 <&mmcc CAMSS_CSI2PIX_CLK>, 1898 <&mmcc CAMSS_CSI2RDI_CLK>, 1899 <&mmcc CAMSS_CSI3_AHB_CLK>, 1900 <&mmcc CAMSS_CSI3_CLK>, 1901 <&mmcc CAMSS_CPHY_CSID3_CLK>, 1902 <&mmcc CAMSS_CSI3PIX_CLK>, 1903 <&mmcc CAMSS_CSI3RDI_CLK>, 1904 <&mmcc CAMSS_AHB_CLK>, 1905 <&mmcc CAMSS_VFE0_CLK>, 1906 <&mmcc CAMSS_CSI_VFE0_CLK>, 1907 <&mmcc CAMSS_VFE0_AHB_CLK>, 1908 <&mmcc CAMSS_VFE0_STREAM_CLK>, 1909 <&mmcc CAMSS_VFE1_CLK>, 1910 <&mmcc CAMSS_CSI_VFE1_CLK>, 1911 <&mmcc CAMSS_VFE1_AHB_CLK>, 1912 <&mmcc CAMSS_VFE1_STREAM_CLK>, 1913 <&mmcc CAMSS_VFE_VBIF_AHB_CLK>, 1914 <&mmcc CAMSS_VFE_VBIF_AXI_CLK>, 1915 <&mmcc CSIPHY_AHB2CRIF_CLK>, 1916 <&mmcc CAMSS_CPHY_CSID0_CLK>, 1917 <&mmcc CAMSS_CPHY_CSID1_CLK>, 1918 <&mmcc CAMSS_CPHY_CSID2_CLK>, 1919 <&mmcc CAMSS_CPHY_CSID3_CLK>; 1920 clock-names = "top_ahb", 1921 "throttle_axi", 1922 "ispif_ahb", 1923 "csiphy0_timer", 1924 "csiphy1_timer", 1925 "csiphy2_timer", 1926 "csi0_ahb", 1927 "csi0", 1928 "csi0_phy", 1929 "csi0_pix", 1930 "csi0_rdi", 1931 "csi1_ahb", 1932 "csi1", 1933 "csi1_phy", 1934 "csi1_pix", 1935 "csi1_rdi", 1936 "csi2_ahb", 1937 "csi2", 1938 "csi2_phy", 1939 "csi2_pix", 1940 "csi2_rdi", 1941 "csi3_ahb", 1942 "csi3", 1943 "csi3_phy", 1944 "csi3_pix", 1945 "csi3_rdi", 1946 "ahb", 1947 "vfe0", 1948 "csi_vfe0", 1949 "vfe0_ahb", 1950 "vfe0_stream", 1951 "vfe1", 1952 "csi_vfe1", 1953 "vfe1_ahb", 1954 "vfe1_stream", 1955 "vfe_ahb", 1956 "vfe_axi", 1957 "csiphy_ahb2crif", 1958 "cphy_csid0", 1959 "cphy_csid1", 1960 "cphy_csid2", 1961 "cphy_csid3"; 1962 interconnects = <&mnoc 5 &bimc 5>; 1963 interconnect-names = "vfe-mem"; 1964 iommus = <&mmss_smmu 0xc00>, 1965 <&mmss_smmu 0xc01>, 1966 <&mmss_smmu 0xc02>, 1967 <&mmss_smmu 0xc03>; 1968 power-domains = <&mmcc CAMSS_VFE0_GDSC>, 1969 <&mmcc CAMSS_VFE1_GDSC>; 1970 status = "disabled"; 1971 1972 ports { 1973 #address-cells = <1>; 1974 #size-cells = <0>; 1975 }; 1976 }; 1977 1978 cci: cci@ca0c000 { 1979 compatible = "qcom,msm8996-cci"; 1980 #address-cells = <1>; 1981 #size-cells = <0>; 1982 reg = <0x0ca0c000 0x1000>; 1983 interrupts = <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>; 1984 1985 assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>, 1986 <&mmcc CAMSS_CCI_CLK>; 1987 assigned-clock-rates = <80800000>, <37500000>; 1988 clocks = <&mmcc CAMSS_TOP_AHB_CLK>, 1989 <&mmcc CAMSS_CCI_AHB_CLK>, 1990 <&mmcc CAMSS_CCI_CLK>, 1991 <&mmcc CAMSS_AHB_CLK>; 1992 clock-names = "camss_top_ahb", 1993 "cci_ahb", 1994 "cci", 1995 "camss_ahb"; 1996 1997 pinctrl-names = "default"; 1998 pinctrl-0 = <&cci0_default &cci1_default>; 1999 power-domains = <&mmcc CAMSS_TOP_GDSC>; 2000 status = "disabled"; 2001 2002 cci_i2c0: i2c-bus@0 { 2003 reg = <0>; 2004 clock-frequency = <400000>; 2005 #address-cells = <1>; 2006 #size-cells = <0>; 2007 }; 2008 2009 cci_i2c1: i2c-bus@1 { 2010 reg = <1>; 2011 clock-frequency = <400000>; 2012 #address-cells = <1>; 2013 #size-cells = <0>; 2014 }; 2015 }; 2016 2017 mmss_smmu: iommu@cd00000 { 2018 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2"; 2019 reg = <0x0cd00000 0x40000>; 2020 2021 clocks = <&mmcc MNOC_AHB_CLK>, 2022 <&mmcc BIMC_SMMU_AHB_CLK>, 2023 <&rpmcc RPM_SMD_MMSSNOC_AXI_CLK>, 2024 <&mmcc BIMC_SMMU_AXI_CLK>; 2025 clock-names = "iface-mm", "iface-smmu", 2026 "bus-mm", "bus-smmu"; 2027 #global-interrupts = <2>; 2028 #iommu-cells = <1>; 2029 2030 interrupts = 2031 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 2032 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 2033 2034 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 2035 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 2036 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, 2037 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 2038 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 2039 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 2040 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 2041 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 2042 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 2043 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 2044 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 2045 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 2046 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 2047 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 2048 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 2049 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 2050 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 2051 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 2052 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 2053 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, 2054 <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, 2055 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 2056 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 2057 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>; 2058 2059 status = "disabled"; 2060 }; 2061 2062 adsp_pil: remoteproc@15700000 { 2063 compatible = "qcom,sdm660-adsp-pas"; 2064 reg = <0x15700000 0x4040>; 2065 2066 interrupts-extended = 2067 <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 2068 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2069 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2070 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2071 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2072 interrupt-names = "wdog", "fatal", "ready", 2073 "handover", "stop-ack"; 2074 2075 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 2076 clock-names = "xo"; 2077 2078 memory-region = <&adsp_region>; 2079 power-domains = <&rpmpd SDM660_VDDCX>; 2080 power-domain-names = "cx"; 2081 2082 qcom,smem-states = <&adsp_smp2p_out 0>; 2083 qcom,smem-state-names = "stop"; 2084 2085 glink-edge { 2086 interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>; 2087 2088 label = "lpass"; 2089 mboxes = <&apcs_glb 9>; 2090 qcom,remote-pid = <2>; 2091 #address-cells = <1>; 2092 #size-cells = <0>; 2093 2094 apr { 2095 compatible = "qcom,apr-v2"; 2096 qcom,glink-channels = "apr_audio_svc"; 2097 qcom,apr-domain = <APR_DOMAIN_ADSP>; 2098 #address-cells = <1>; 2099 #size-cells = <0>; 2100 2101 q6core { 2102 reg = <APR_SVC_ADSP_CORE>; 2103 compatible = "qcom,q6core"; 2104 }; 2105 2106 q6afe: apr-service@4 { 2107 compatible = "qcom,q6afe"; 2108 reg = <APR_SVC_AFE>; 2109 q6afedai: dais { 2110 compatible = "qcom,q6afe-dais"; 2111 #address-cells = <1>; 2112 #size-cells = <0>; 2113 #sound-dai-cells = <1>; 2114 }; 2115 }; 2116 2117 q6asm: apr-service@7 { 2118 compatible = "qcom,q6asm"; 2119 reg = <APR_SVC_ASM>; 2120 q6asmdai: dais { 2121 compatible = "qcom,q6asm-dais"; 2122 #address-cells = <1>; 2123 #size-cells = <0>; 2124 #sound-dai-cells = <1>; 2125 iommus = <&lpass_smmu 1>; 2126 }; 2127 }; 2128 2129 q6adm: apr-service@8 { 2130 compatible = "qcom,q6adm"; 2131 reg = <APR_SVC_ADM>; 2132 q6routing: routing { 2133 compatible = "qcom,q6adm-routing"; 2134 #sound-dai-cells = <0>; 2135 }; 2136 }; 2137 }; 2138 }; 2139 }; 2140 2141 gnoc: interconnect@17900000 { 2142 compatible = "qcom,sdm660-gnoc"; 2143 reg = <0x17900000 0xe000>; 2144 #interconnect-cells = <1>; 2145 /* 2146 * This one apparently features no clocks, 2147 * so let's not mess with the driver needlessly 2148 */ 2149 clock-names = "bus", "bus_a"; 2150 clocks = <&xo_board>, <&xo_board>; 2151 }; 2152 2153 apcs_glb: mailbox@17911000 { 2154 compatible = "qcom,sdm660-apcs-hmss-global"; 2155 reg = <0x17911000 0x1000>; 2156 2157 #mbox-cells = <1>; 2158 }; 2159 2160 timer@17920000 { 2161 #address-cells = <1>; 2162 #size-cells = <1>; 2163 ranges; 2164 compatible = "arm,armv7-timer-mem"; 2165 reg = <0x17920000 0x1000>; 2166 clock-frequency = <19200000>; 2167 2168 frame@17921000 { 2169 frame-number = <0>; 2170 interrupts = <0 8 0x4>, 2171 <0 7 0x4>; 2172 reg = <0x17921000 0x1000>, 2173 <0x17922000 0x1000>; 2174 }; 2175 2176 frame@17923000 { 2177 frame-number = <1>; 2178 interrupts = <0 9 0x4>; 2179 reg = <0x17923000 0x1000>; 2180 status = "disabled"; 2181 }; 2182 2183 frame@17924000 { 2184 frame-number = <2>; 2185 interrupts = <0 10 0x4>; 2186 reg = <0x17924000 0x1000>; 2187 status = "disabled"; 2188 }; 2189 2190 frame@17925000 { 2191 frame-number = <3>; 2192 interrupts = <0 11 0x4>; 2193 reg = <0x17925000 0x1000>; 2194 status = "disabled"; 2195 }; 2196 2197 frame@17926000 { 2198 frame-number = <4>; 2199 interrupts = <0 12 0x4>; 2200 reg = <0x17926000 0x1000>; 2201 status = "disabled"; 2202 }; 2203 2204 frame@17927000 { 2205 frame-number = <5>; 2206 interrupts = <0 13 0x4>; 2207 reg = <0x17927000 0x1000>; 2208 status = "disabled"; 2209 }; 2210 2211 frame@17928000 { 2212 frame-number = <6>; 2213 interrupts = <0 14 0x4>; 2214 reg = <0x17928000 0x1000>; 2215 status = "disabled"; 2216 }; 2217 }; 2218 2219 intc: interrupt-controller@17a00000 { 2220 compatible = "arm,gic-v3"; 2221 reg = <0x17a00000 0x10000>, /* GICD */ 2222 <0x17b00000 0x100000>; /* GICR * 8 */ 2223 #interrupt-cells = <3>; 2224 #address-cells = <1>; 2225 #size-cells = <1>; 2226 ranges; 2227 interrupt-controller; 2228 #redistributor-regions = <1>; 2229 redistributor-stride = <0x0 0x20000>; 2230 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 2231 }; 2232 }; 2233 2234 tcsr_mutex: hwlock { 2235 compatible = "qcom,tcsr-mutex"; 2236 syscon = <&tcsr_mutex_regs 0 0x1000>; 2237 #hwlock-cells = <1>; 2238 }; 2239 2240 sound: sound { 2241 }; 2242 2243 thermal-zones { 2244 aoss-thermal { 2245 polling-delay-passive = <250>; 2246 polling-delay = <1000>; 2247 2248 thermal-sensors = <&tsens 0>; 2249 2250 trips { 2251 aoss_alert0: trip-point0 { 2252 temperature = <105000>; 2253 hysteresis = <1000>; 2254 type = "hot"; 2255 }; 2256 }; 2257 }; 2258 2259 cpuss0-thermal { 2260 polling-delay-passive = <250>; 2261 polling-delay = <1000>; 2262 2263 thermal-sensors = <&tsens 1>; 2264 2265 trips { 2266 cpuss0_alert0: trip-point0 { 2267 temperature = <125000>; 2268 hysteresis = <1000>; 2269 type = "hot"; 2270 }; 2271 }; 2272 }; 2273 2274 cpuss1-thermal { 2275 polling-delay-passive = <250>; 2276 polling-delay = <1000>; 2277 2278 thermal-sensors = <&tsens 2>; 2279 2280 trips { 2281 cpuss1_alert0: trip-point0 { 2282 temperature = <125000>; 2283 hysteresis = <1000>; 2284 type = "hot"; 2285 }; 2286 }; 2287 }; 2288 2289 cpu0-thermal { 2290 polling-delay-passive = <250>; 2291 polling-delay = <1000>; 2292 2293 thermal-sensors = <&tsens 3>; 2294 2295 trips { 2296 cpu0_alert0: trip-point0 { 2297 temperature = <70000>; 2298 hysteresis = <1000>; 2299 type = "passive"; 2300 }; 2301 2302 cpu0_crit: cpu_crit { 2303 temperature = <110000>; 2304 hysteresis = <1000>; 2305 type = "critical"; 2306 }; 2307 }; 2308 }; 2309 2310 cpu1-thermal { 2311 polling-delay-passive = <250>; 2312 polling-delay = <1000>; 2313 2314 thermal-sensors = <&tsens 4>; 2315 2316 trips { 2317 cpu1_alert0: trip-point0 { 2318 temperature = <70000>; 2319 hysteresis = <1000>; 2320 type = "passive"; 2321 }; 2322 2323 cpu1_crit: cpu_crit { 2324 temperature = <110000>; 2325 hysteresis = <1000>; 2326 type = "critical"; 2327 }; 2328 }; 2329 }; 2330 2331 cpu2-thermal { 2332 polling-delay-passive = <250>; 2333 polling-delay = <1000>; 2334 2335 thermal-sensors = <&tsens 5>; 2336 2337 trips { 2338 cpu2_alert0: trip-point0 { 2339 temperature = <70000>; 2340 hysteresis = <1000>; 2341 type = "passive"; 2342 }; 2343 2344 cpu2_crit: cpu_crit { 2345 temperature = <110000>; 2346 hysteresis = <1000>; 2347 type = "critical"; 2348 }; 2349 }; 2350 }; 2351 2352 cpu3-thermal { 2353 polling-delay-passive = <250>; 2354 polling-delay = <1000>; 2355 2356 thermal-sensors = <&tsens 6>; 2357 2358 trips { 2359 cpu3_alert0: trip-point0 { 2360 temperature = <70000>; 2361 hysteresis = <1000>; 2362 type = "passive"; 2363 }; 2364 2365 cpu3_crit: cpu_crit { 2366 temperature = <110000>; 2367 hysteresis = <1000>; 2368 type = "critical"; 2369 }; 2370 }; 2371 }; 2372 2373 /* 2374 * According to what downstream DTS says, 2375 * the entire power efficient cluster has 2376 * only a single thermal sensor. 2377 */ 2378 2379 pwr-cluster-thermal { 2380 polling-delay-passive = <250>; 2381 polling-delay = <1000>; 2382 2383 thermal-sensors = <&tsens 7>; 2384 2385 trips { 2386 pwr_cluster_alert0: trip-point0 { 2387 temperature = <70000>; 2388 hysteresis = <1000>; 2389 type = "passive"; 2390 }; 2391 2392 pwr_cluster_crit: cpu_crit { 2393 temperature = <110000>; 2394 hysteresis = <1000>; 2395 type = "critical"; 2396 }; 2397 }; 2398 }; 2399 2400 gpu-thermal { 2401 polling-delay-passive = <250>; 2402 polling-delay = <1000>; 2403 2404 thermal-sensors = <&tsens 8>; 2405 2406 trips { 2407 gpu_alert0: trip-point0 { 2408 temperature = <90000>; 2409 hysteresis = <1000>; 2410 type = "hot"; 2411 }; 2412 }; 2413 }; 2414 }; 2415 2416 timer { 2417 compatible = "arm,armv8-timer"; 2418 interrupts = <GIC_PPI 1 0xf08>, 2419 <GIC_PPI 2 0xf08>, 2420 <GIC_PPI 3 0xf08>, 2421 <GIC_PPI 0 0xf08>; 2422 }; 2423}; 2424 2425