1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2020, Konrad Dybcio <konradybcio@gmail.com> 4 * Copyright (c) 2020, AngeloGioacchino Del Regno <kholk11@gmail.com> 5 */ 6 7#include <dt-bindings/clock/qcom,gcc-sdm660.h> 8#include <dt-bindings/clock/qcom,gpucc-sdm660.h> 9#include <dt-bindings/clock/qcom,mmcc-sdm660.h> 10#include <dt-bindings/clock/qcom,rpmcc.h> 11#include <dt-bindings/interconnect/qcom,sdm660.h> 12#include <dt-bindings/power/qcom-rpmpd.h> 13#include <dt-bindings/gpio/gpio.h> 14#include <dt-bindings/interrupt-controller/arm-gic.h> 15#include <dt-bindings/soc/qcom,apr.h> 16 17/ { 18 interrupt-parent = <&intc>; 19 20 #address-cells = <2>; 21 #size-cells = <2>; 22 23 aliases { 24 mmc1 = &sdhc_1; 25 mmc2 = &sdhc_2; 26 }; 27 28 chosen { }; 29 30 clocks { 31 xo_board: xo-board { 32 compatible = "fixed-clock"; 33 #clock-cells = <0>; 34 clock-frequency = <19200000>; 35 clock-output-names = "xo_board"; 36 }; 37 38 sleep_clk: sleep-clk { 39 compatible = "fixed-clock"; 40 #clock-cells = <0>; 41 clock-frequency = <32764>; 42 clock-output-names = "sleep_clk"; 43 }; 44 }; 45 46 cpus { 47 #address-cells = <2>; 48 #size-cells = <0>; 49 50 CPU0: cpu@100 { 51 device_type = "cpu"; 52 compatible = "arm,cortex-a53"; 53 reg = <0x0 0x100>; 54 enable-method = "psci"; 55 cpu-idle-states = <&PERF_CPU_SLEEP_0 56 &PERF_CPU_SLEEP_1 57 &PERF_CLUSTER_SLEEP_0 58 &PERF_CLUSTER_SLEEP_1 59 &PERF_CLUSTER_SLEEP_2>; 60 capacity-dmips-mhz = <1126>; 61 #cooling-cells = <2>; 62 next-level-cache = <&L2_1>; 63 L2_1: l2-cache { 64 compatible = "cache"; 65 cache-level = <2>; 66 }; 67 }; 68 69 CPU1: cpu@101 { 70 device_type = "cpu"; 71 compatible = "arm,cortex-a53"; 72 reg = <0x0 0x101>; 73 enable-method = "psci"; 74 cpu-idle-states = <&PERF_CPU_SLEEP_0 75 &PERF_CPU_SLEEP_1 76 &PERF_CLUSTER_SLEEP_0 77 &PERF_CLUSTER_SLEEP_1 78 &PERF_CLUSTER_SLEEP_2>; 79 capacity-dmips-mhz = <1126>; 80 #cooling-cells = <2>; 81 next-level-cache = <&L2_1>; 82 }; 83 84 CPU2: cpu@102 { 85 device_type = "cpu"; 86 compatible = "arm,cortex-a53"; 87 reg = <0x0 0x102>; 88 enable-method = "psci"; 89 cpu-idle-states = <&PERF_CPU_SLEEP_0 90 &PERF_CPU_SLEEP_1 91 &PERF_CLUSTER_SLEEP_0 92 &PERF_CLUSTER_SLEEP_1 93 &PERF_CLUSTER_SLEEP_2>; 94 capacity-dmips-mhz = <1126>; 95 #cooling-cells = <2>; 96 next-level-cache = <&L2_1>; 97 }; 98 99 CPU3: cpu@103 { 100 device_type = "cpu"; 101 compatible = "arm,cortex-a53"; 102 reg = <0x0 0x103>; 103 enable-method = "psci"; 104 cpu-idle-states = <&PERF_CPU_SLEEP_0 105 &PERF_CPU_SLEEP_1 106 &PERF_CLUSTER_SLEEP_0 107 &PERF_CLUSTER_SLEEP_1 108 &PERF_CLUSTER_SLEEP_2>; 109 capacity-dmips-mhz = <1126>; 110 #cooling-cells = <2>; 111 next-level-cache = <&L2_1>; 112 }; 113 114 CPU4: cpu@0 { 115 device_type = "cpu"; 116 compatible = "arm,cortex-a53"; 117 reg = <0x0 0x0>; 118 enable-method = "psci"; 119 cpu-idle-states = <&PWR_CPU_SLEEP_0 120 &PWR_CPU_SLEEP_1 121 &PWR_CLUSTER_SLEEP_0 122 &PWR_CLUSTER_SLEEP_1 123 &PWR_CLUSTER_SLEEP_2>; 124 capacity-dmips-mhz = <1024>; 125 #cooling-cells = <2>; 126 next-level-cache = <&L2_0>; 127 L2_0: l2-cache { 128 compatible = "cache"; 129 cache-level = <2>; 130 }; 131 }; 132 133 CPU5: cpu@1 { 134 device_type = "cpu"; 135 compatible = "arm,cortex-a53"; 136 reg = <0x0 0x1>; 137 enable-method = "psci"; 138 cpu-idle-states = <&PWR_CPU_SLEEP_0 139 &PWR_CPU_SLEEP_1 140 &PWR_CLUSTER_SLEEP_0 141 &PWR_CLUSTER_SLEEP_1 142 &PWR_CLUSTER_SLEEP_2>; 143 capacity-dmips-mhz = <1024>; 144 #cooling-cells = <2>; 145 next-level-cache = <&L2_0>; 146 }; 147 148 CPU6: cpu@2 { 149 device_type = "cpu"; 150 compatible = "arm,cortex-a53"; 151 reg = <0x0 0x2>; 152 enable-method = "psci"; 153 cpu-idle-states = <&PWR_CPU_SLEEP_0 154 &PWR_CPU_SLEEP_1 155 &PWR_CLUSTER_SLEEP_0 156 &PWR_CLUSTER_SLEEP_1 157 &PWR_CLUSTER_SLEEP_2>; 158 capacity-dmips-mhz = <1024>; 159 #cooling-cells = <2>; 160 next-level-cache = <&L2_0>; 161 }; 162 163 CPU7: cpu@3 { 164 device_type = "cpu"; 165 compatible = "arm,cortex-a53"; 166 reg = <0x0 0x3>; 167 enable-method = "psci"; 168 cpu-idle-states = <&PWR_CPU_SLEEP_0 169 &PWR_CPU_SLEEP_1 170 &PWR_CLUSTER_SLEEP_0 171 &PWR_CLUSTER_SLEEP_1 172 &PWR_CLUSTER_SLEEP_2>; 173 capacity-dmips-mhz = <1024>; 174 #cooling-cells = <2>; 175 next-level-cache = <&L2_0>; 176 }; 177 178 cpu-map { 179 cluster0 { 180 core0 { 181 cpu = <&CPU4>; 182 }; 183 184 core1 { 185 cpu = <&CPU5>; 186 }; 187 188 core2 { 189 cpu = <&CPU6>; 190 }; 191 192 core3 { 193 cpu = <&CPU7>; 194 }; 195 }; 196 197 cluster1 { 198 core0 { 199 cpu = <&CPU0>; 200 }; 201 202 core1 { 203 cpu = <&CPU1>; 204 }; 205 206 core2 { 207 cpu = <&CPU2>; 208 }; 209 210 core3 { 211 cpu = <&CPU3>; 212 }; 213 }; 214 }; 215 216 idle-states { 217 entry-method = "psci"; 218 219 PWR_CPU_SLEEP_0: cpu-sleep-0-0 { 220 compatible = "arm,idle-state"; 221 idle-state-name = "pwr-retention"; 222 arm,psci-suspend-param = <0x40000002>; 223 entry-latency-us = <338>; 224 exit-latency-us = <423>; 225 min-residency-us = <200>; 226 }; 227 228 PWR_CPU_SLEEP_1: cpu-sleep-0-1 { 229 compatible = "arm,idle-state"; 230 idle-state-name = "pwr-power-collapse"; 231 arm,psci-suspend-param = <0x40000003>; 232 entry-latency-us = <515>; 233 exit-latency-us = <1821>; 234 min-residency-us = <1000>; 235 local-timer-stop; 236 }; 237 238 PERF_CPU_SLEEP_0: cpu-sleep-1-0 { 239 compatible = "arm,idle-state"; 240 idle-state-name = "perf-retention"; 241 arm,psci-suspend-param = <0x40000002>; 242 entry-latency-us = <154>; 243 exit-latency-us = <87>; 244 min-residency-us = <200>; 245 }; 246 247 PERF_CPU_SLEEP_1: cpu-sleep-1-1 { 248 compatible = "arm,idle-state"; 249 idle-state-name = "perf-power-collapse"; 250 arm,psci-suspend-param = <0x40000003>; 251 entry-latency-us = <262>; 252 exit-latency-us = <301>; 253 min-residency-us = <1000>; 254 local-timer-stop; 255 }; 256 257 PWR_CLUSTER_SLEEP_0: cluster-sleep-0-0 { 258 compatible = "arm,idle-state"; 259 idle-state-name = "pwr-cluster-dynamic-retention"; 260 arm,psci-suspend-param = <0x400000F2>; 261 entry-latency-us = <284>; 262 exit-latency-us = <384>; 263 min-residency-us = <9987>; 264 local-timer-stop; 265 }; 266 267 PWR_CLUSTER_SLEEP_1: cluster-sleep-0-1 { 268 compatible = "arm,idle-state"; 269 idle-state-name = "pwr-cluster-retention"; 270 arm,psci-suspend-param = <0x400000F3>; 271 entry-latency-us = <338>; 272 exit-latency-us = <423>; 273 min-residency-us = <9987>; 274 local-timer-stop; 275 }; 276 277 PWR_CLUSTER_SLEEP_2: cluster-sleep-0-2 { 278 compatible = "arm,idle-state"; 279 idle-state-name = "pwr-cluster-retention"; 280 arm,psci-suspend-param = <0x400000F4>; 281 entry-latency-us = <515>; 282 exit-latency-us = <1821>; 283 min-residency-us = <9987>; 284 local-timer-stop; 285 }; 286 287 PERF_CLUSTER_SLEEP_0: cluster-sleep-1-0 { 288 compatible = "arm,idle-state"; 289 idle-state-name = "perf-cluster-dynamic-retention"; 290 arm,psci-suspend-param = <0x400000F2>; 291 entry-latency-us = <272>; 292 exit-latency-us = <329>; 293 min-residency-us = <9987>; 294 local-timer-stop; 295 }; 296 297 PERF_CLUSTER_SLEEP_1: cluster-sleep-1-1 { 298 compatible = "arm,idle-state"; 299 idle-state-name = "perf-cluster-retention"; 300 arm,psci-suspend-param = <0x400000F3>; 301 entry-latency-us = <332>; 302 exit-latency-us = <368>; 303 min-residency-us = <9987>; 304 local-timer-stop; 305 }; 306 307 PERF_CLUSTER_SLEEP_2: cluster-sleep-1-2 { 308 compatible = "arm,idle-state"; 309 idle-state-name = "perf-cluster-retention"; 310 arm,psci-suspend-param = <0x400000F4>; 311 entry-latency-us = <545>; 312 exit-latency-us = <1609>; 313 min-residency-us = <9987>; 314 local-timer-stop; 315 }; 316 }; 317 }; 318 319 firmware { 320 scm { 321 compatible = "qcom,scm-msm8998", "qcom,scm"; 322 }; 323 }; 324 325 memory@80000000 { 326 device_type = "memory"; 327 /* We expect the bootloader to fill in the reg */ 328 reg = <0x0 0x80000000 0x0 0x0>; 329 }; 330 331 dsi_opp_table: opp-table-dsi { 332 compatible = "operating-points-v2"; 333 334 opp-131250000 { 335 opp-hz = /bits/ 64 <131250000>; 336 required-opps = <&rpmpd_opp_svs>; 337 }; 338 339 opp-210000000 { 340 opp-hz = /bits/ 64 <210000000>; 341 required-opps = <&rpmpd_opp_svs_plus>; 342 }; 343 344 opp-262500000 { 345 opp-hz = /bits/ 64 <262500000>; 346 required-opps = <&rpmpd_opp_nom>; 347 }; 348 }; 349 350 pmu { 351 compatible = "arm,armv8-pmuv3"; 352 interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>; 353 }; 354 355 psci { 356 compatible = "arm,psci-1.0"; 357 method = "smc"; 358 }; 359 360 reserved-memory { 361 #address-cells = <2>; 362 #size-cells = <2>; 363 ranges; 364 365 wlan_msa_guard: wlan-msa-guard@85600000 { 366 reg = <0x0 0x85600000 0x0 0x100000>; 367 no-map; 368 }; 369 370 wlan_msa_mem: wlan-msa-mem@85700000 { 371 reg = <0x0 0x85700000 0x0 0x100000>; 372 no-map; 373 }; 374 375 qhee_code: qhee-code@85800000 { 376 reg = <0x0 0x85800000 0x0 0x600000>; 377 no-map; 378 }; 379 380 rmtfs_mem: memory@85e00000 { 381 compatible = "qcom,rmtfs-mem"; 382 reg = <0x0 0x85e00000 0x0 0x200000>; 383 no-map; 384 385 qcom,client-id = <1>; 386 qcom,vmid = <15>; 387 }; 388 389 smem_region: smem-mem@86000000 { 390 reg = <0 0x86000000 0 0x200000>; 391 no-map; 392 }; 393 394 tz_mem: memory@86200000 { 395 reg = <0x0 0x86200000 0x0 0x3300000>; 396 no-map; 397 }; 398 399 mpss_region: mpss@8ac00000 { 400 reg = <0x0 0x8ac00000 0x0 0x7e00000>; 401 no-map; 402 }; 403 404 adsp_region: adsp@92a00000 { 405 reg = <0x0 0x92a00000 0x0 0x1e00000>; 406 no-map; 407 }; 408 409 mba_region: mba@94800000 { 410 reg = <0x0 0x94800000 0x0 0x200000>; 411 no-map; 412 }; 413 414 buffer_mem: tzbuffer@94a00000 { 415 reg = <0x0 0x94a00000 0x0 0x100000>; 416 no-map; 417 }; 418 419 venus_region: venus@9f800000 { 420 reg = <0x0 0x9f800000 0x0 0x800000>; 421 no-map; 422 }; 423 424 adsp_mem: adsp-region@f6000000 { 425 reg = <0x0 0xf6000000 0x0 0x800000>; 426 no-map; 427 }; 428 429 qseecom_mem: qseecom-region@f6800000 { 430 reg = <0x0 0xf6800000 0x0 0x1400000>; 431 no-map; 432 }; 433 434 zap_shader_region: gpu@fed00000 { 435 compatible = "shared-dma-pool"; 436 reg = <0x0 0xfed00000 0x0 0xa00000>; 437 no-map; 438 }; 439 }; 440 441 rpm-glink { 442 compatible = "qcom,glink-rpm"; 443 444 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 445 qcom,rpm-msg-ram = <&rpm_msg_ram>; 446 mboxes = <&apcs_glb 0>; 447 448 rpm_requests: rpm-requests { 449 compatible = "qcom,rpm-sdm660"; 450 qcom,glink-channels = "rpm_requests"; 451 452 rpmcc: clock-controller { 453 compatible = "qcom,rpmcc-sdm660", "qcom,rpmcc"; 454 #clock-cells = <1>; 455 }; 456 457 rpmpd: power-controller { 458 compatible = "qcom,sdm660-rpmpd"; 459 #power-domain-cells = <1>; 460 operating-points-v2 = <&rpmpd_opp_table>; 461 462 rpmpd_opp_table: opp-table { 463 compatible = "operating-points-v2"; 464 465 rpmpd_opp_ret: opp1 { 466 opp-level = <RPM_SMD_LEVEL_RETENTION>; 467 }; 468 469 rpmpd_opp_ret_plus: opp2 { 470 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>; 471 }; 472 473 rpmpd_opp_min_svs: opp3 { 474 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 475 }; 476 477 rpmpd_opp_low_svs: opp4 { 478 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 479 }; 480 481 rpmpd_opp_svs: opp5 { 482 opp-level = <RPM_SMD_LEVEL_SVS>; 483 }; 484 485 rpmpd_opp_svs_plus: opp6 { 486 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 487 }; 488 489 rpmpd_opp_nom: opp7 { 490 opp-level = <RPM_SMD_LEVEL_NOM>; 491 }; 492 493 rpmpd_opp_nom_plus: opp8 { 494 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 495 }; 496 497 rpmpd_opp_turbo: opp9 { 498 opp-level = <RPM_SMD_LEVEL_TURBO>; 499 }; 500 }; 501 }; 502 }; 503 }; 504 505 smem: smem { 506 compatible = "qcom,smem"; 507 memory-region = <&smem_region>; 508 hwlocks = <&tcsr_mutex 3>; 509 }; 510 511 smp2p-adsp { 512 compatible = "qcom,smp2p"; 513 qcom,smem = <443>, <429>; 514 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 515 mboxes = <&apcs_glb 10>; 516 qcom,local-pid = <0>; 517 qcom,remote-pid = <2>; 518 519 adsp_smp2p_out: master-kernel { 520 qcom,entry-name = "master-kernel"; 521 #qcom,smem-state-cells = <1>; 522 }; 523 524 adsp_smp2p_in: slave-kernel { 525 qcom,entry-name = "slave-kernel"; 526 interrupt-controller; 527 #interrupt-cells = <2>; 528 }; 529 }; 530 531 smp2p-mpss { 532 compatible = "qcom,smp2p"; 533 qcom,smem = <435>, <428>; 534 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 535 mboxes = <&apcs_glb 14>; 536 qcom,local-pid = <0>; 537 qcom,remote-pid = <1>; 538 539 modem_smp2p_out: master-kernel { 540 qcom,entry-name = "master-kernel"; 541 #qcom,smem-state-cells = <1>; 542 }; 543 544 modem_smp2p_in: slave-kernel { 545 qcom,entry-name = "slave-kernel"; 546 interrupt-controller; 547 #interrupt-cells = <2>; 548 }; 549 }; 550 551 soc { 552 #address-cells = <1>; 553 #size-cells = <1>; 554 ranges = <0 0 0 0xffffffff>; 555 compatible = "simple-bus"; 556 557 gcc: clock-controller@100000 { 558 compatible = "qcom,gcc-sdm630"; 559 #clock-cells = <1>; 560 #reset-cells = <1>; 561 #power-domain-cells = <1>; 562 reg = <0x00100000 0x94000>; 563 564 clock-names = "xo", "sleep_clk"; 565 clocks = <&xo_board>, 566 <&sleep_clk>; 567 }; 568 569 rpm_msg_ram: sram@778000 { 570 compatible = "qcom,rpm-msg-ram"; 571 reg = <0x00778000 0x7000>; 572 }; 573 574 qfprom: qfprom@780000 { 575 compatible = "qcom,sdm630-qfprom", "qcom,qfprom"; 576 reg = <0x00780000 0x621c>; 577 #address-cells = <1>; 578 #size-cells = <1>; 579 580 qusb2_hstx_trim: hstx-trim@240 { 581 reg = <0x243 0x1>; 582 bits = <1 3>; 583 }; 584 585 gpu_speed_bin: gpu-speed-bin@41a0 { 586 reg = <0x41a2 0x1>; 587 bits = <5 7>; 588 }; 589 }; 590 591 rng: rng@793000 { 592 compatible = "qcom,prng-ee"; 593 reg = <0x00793000 0x1000>; 594 clocks = <&gcc GCC_PRNG_AHB_CLK>; 595 clock-names = "core"; 596 }; 597 598 bimc: interconnect@1008000 { 599 compatible = "qcom,sdm660-bimc"; 600 reg = <0x01008000 0x78000>; 601 #interconnect-cells = <1>; 602 clock-names = "bus", "bus_a"; 603 clocks = <&rpmcc RPM_SMD_BIMC_CLK>, 604 <&rpmcc RPM_SMD_BIMC_A_CLK>; 605 }; 606 607 restart@10ac000 { 608 compatible = "qcom,pshold"; 609 reg = <0x010ac000 0x4>; 610 }; 611 612 cnoc: interconnect@1500000 { 613 compatible = "qcom,sdm660-cnoc"; 614 reg = <0x01500000 0x10000>; 615 #interconnect-cells = <1>; 616 clock-names = "bus", "bus_a"; 617 clocks = <&rpmcc RPM_SMD_CNOC_CLK>, 618 <&rpmcc RPM_SMD_CNOC_A_CLK>; 619 }; 620 621 snoc: interconnect@1626000 { 622 compatible = "qcom,sdm660-snoc"; 623 reg = <0x01626000 0x7090>; 624 #interconnect-cells = <1>; 625 clock-names = "bus", "bus_a"; 626 clocks = <&rpmcc RPM_SMD_SNOC_CLK>, 627 <&rpmcc RPM_SMD_SNOC_A_CLK>; 628 }; 629 630 anoc2_smmu: iommu@16c0000 { 631 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2"; 632 reg = <0x016c0000 0x40000>; 633 634 assigned-clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>; 635 assigned-clock-rates = <1000>; 636 clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>; 637 clock-names = "bus"; 638 #global-interrupts = <2>; 639 #iommu-cells = <1>; 640 641 interrupts = 642 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 643 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 644 645 <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>, 646 <GIC_SPI 374 IRQ_TYPE_LEVEL_LOW>, 647 <GIC_SPI 375 IRQ_TYPE_LEVEL_LOW>, 648 <GIC_SPI 376 IRQ_TYPE_LEVEL_LOW>, 649 <GIC_SPI 377 IRQ_TYPE_LEVEL_LOW>, 650 <GIC_SPI 378 IRQ_TYPE_LEVEL_LOW>, 651 <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>, 652 <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>, 653 <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>, 654 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>, 655 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>, 656 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>, 657 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>, 658 <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, 659 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>, 660 <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>, 661 <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>, 662 <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, 663 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, 664 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, 665 <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>, 666 <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>, 667 <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, 668 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>, 669 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>, 670 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>, 671 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, 672 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, 673 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>; 674 675 status = "disabled"; 676 }; 677 678 a2noc: interconnect@1704000 { 679 compatible = "qcom,sdm660-a2noc"; 680 reg = <0x01704000 0xc100>; 681 #interconnect-cells = <1>; 682 clock-names = "bus", 683 "bus_a", 684 "ipa", 685 "ufs_axi", 686 "aggre2_ufs_axi", 687 "aggre2_usb3_axi", 688 "cfg_noc_usb2_axi"; 689 clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>, 690 <&rpmcc RPM_SMD_AGGR2_NOC_A_CLK>, 691 <&rpmcc RPM_SMD_IPA_CLK>, 692 <&gcc GCC_UFS_AXI_CLK>, 693 <&gcc GCC_AGGRE2_UFS_AXI_CLK>, 694 <&gcc GCC_AGGRE2_USB3_AXI_CLK>, 695 <&gcc GCC_CFG_NOC_USB2_AXI_CLK>; 696 }; 697 698 mnoc: interconnect@1745000 { 699 compatible = "qcom,sdm660-mnoc"; 700 reg = <0x01745000 0xa010>; 701 #interconnect-cells = <1>; 702 clock-names = "bus", "bus_a", "iface"; 703 clocks = <&rpmcc RPM_SMD_MMSSNOC_AXI_CLK>, 704 <&rpmcc RPM_SMD_MMSSNOC_AXI_CLK_A>, 705 <&mmcc AHB_CLK_SRC>; 706 }; 707 708 tsens: thermal-sensor@10ae000 { 709 compatible = "qcom,sdm630-tsens", "qcom,tsens-v2"; 710 reg = <0x010ae000 0x1000>, /* TM */ 711 <0x010ad000 0x1000>; /* SROT */ 712 #qcom,sensors = <12>; 713 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 714 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>; 715 interrupt-names = "uplow", "critical"; 716 #thermal-sensor-cells = <1>; 717 }; 718 719 tcsr_mutex: hwlock@1f40000 { 720 compatible = "qcom,tcsr-mutex"; 721 reg = <0x01f40000 0x20000>; 722 #hwlock-cells = <1>; 723 }; 724 725 tcsr_regs_1: syscon@1f60000 { 726 compatible = "qcom,sdm630-tcsr", "syscon"; 727 reg = <0x01f60000 0x20000>; 728 }; 729 730 tlmm: pinctrl@3100000 { 731 compatible = "qcom,sdm630-pinctrl"; 732 reg = <0x03100000 0x400000>, 733 <0x03500000 0x400000>, 734 <0x03900000 0x400000>; 735 reg-names = "south", "center", "north"; 736 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 737 gpio-controller; 738 gpio-ranges = <&tlmm 0 0 114>; 739 #gpio-cells = <2>; 740 interrupt-controller; 741 #interrupt-cells = <2>; 742 743 blsp1_uart1_default: blsp1-uart1-default-state { 744 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 745 function = "blsp_uart1"; 746 drive-strength = <2>; 747 bias-disable; 748 }; 749 750 blsp1_uart1_sleep: blsp1-uart1-sleep-state { 751 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 752 function = "gpio"; 753 drive-strength = <2>; 754 bias-disable; 755 }; 756 757 blsp1_uart2_default: blsp1-uart2-default-state { 758 pins = "gpio4", "gpio5"; 759 function = "blsp_uart2"; 760 drive-strength = <2>; 761 bias-disable; 762 }; 763 764 blsp2_uart1_default: blsp2-uart1-active-state { 765 tx-rts-pins { 766 pins = "gpio16", "gpio19"; 767 function = "blsp_uart5"; 768 drive-strength = <2>; 769 bias-disable; 770 }; 771 772 rx-pins { 773 /* 774 * Avoid garbage data while BT module 775 * is powered off or not driving signal 776 */ 777 pins = "gpio17"; 778 function = "blsp_uart5"; 779 drive-strength = <2>; 780 bias-pull-up; 781 }; 782 783 cts-pins { 784 /* Match the pull of the BT module */ 785 pins = "gpio18"; 786 function = "blsp_uart5"; 787 drive-strength = <2>; 788 bias-pull-down; 789 }; 790 }; 791 792 blsp2_uart1_sleep: blsp2-uart1-sleep-state { 793 tx-pins { 794 pins = "gpio16"; 795 function = "gpio"; 796 drive-strength = <2>; 797 bias-pull-up; 798 }; 799 800 rx-cts-rts-pins { 801 pins = "gpio17", "gpio18", "gpio19"; 802 function = "gpio"; 803 drive-strength = <2>; 804 bias-disable; 805 }; 806 }; 807 808 i2c1_default: i2c1-default-state { 809 pins = "gpio2", "gpio3"; 810 function = "blsp_i2c1"; 811 drive-strength = <2>; 812 bias-disable; 813 }; 814 815 i2c1_sleep: i2c1-sleep-state { 816 pins = "gpio2", "gpio3"; 817 function = "blsp_i2c1"; 818 drive-strength = <2>; 819 bias-pull-up; 820 }; 821 822 i2c2_default: i2c2-default-state { 823 pins = "gpio6", "gpio7"; 824 function = "blsp_i2c2"; 825 drive-strength = <2>; 826 bias-disable; 827 }; 828 829 i2c2_sleep: i2c2-sleep-state { 830 pins = "gpio6", "gpio7"; 831 function = "blsp_i2c2"; 832 drive-strength = <2>; 833 bias-pull-up; 834 }; 835 836 i2c3_default: i2c3-default-state { 837 pins = "gpio10", "gpio11"; 838 function = "blsp_i2c3"; 839 drive-strength = <2>; 840 bias-disable; 841 }; 842 843 i2c3_sleep: i2c3-sleep-state { 844 pins = "gpio10", "gpio11"; 845 function = "blsp_i2c3"; 846 drive-strength = <2>; 847 bias-pull-up; 848 }; 849 850 i2c4_default: i2c4-default-state { 851 pins = "gpio14", "gpio15"; 852 function = "blsp_i2c4"; 853 drive-strength = <2>; 854 bias-disable; 855 }; 856 857 i2c4_sleep: i2c4-sleep-state { 858 pins = "gpio14", "gpio15"; 859 function = "blsp_i2c4"; 860 drive-strength = <2>; 861 bias-pull-up; 862 }; 863 864 i2c5_default: i2c5-default-state { 865 pins = "gpio18", "gpio19"; 866 function = "blsp_i2c5"; 867 drive-strength = <2>; 868 bias-disable; 869 }; 870 871 i2c5_sleep: i2c5-sleep-state { 872 pins = "gpio18", "gpio19"; 873 function = "blsp_i2c5"; 874 drive-strength = <2>; 875 bias-pull-up; 876 }; 877 878 i2c6_default: i2c6-default-state { 879 pins = "gpio22", "gpio23"; 880 function = "blsp_i2c6"; 881 drive-strength = <2>; 882 bias-disable; 883 }; 884 885 i2c6_sleep: i2c6-sleep-state { 886 pins = "gpio22", "gpio23"; 887 function = "blsp_i2c6"; 888 drive-strength = <2>; 889 bias-pull-up; 890 }; 891 892 i2c7_default: i2c7-default-state { 893 pins = "gpio26", "gpio27"; 894 function = "blsp_i2c7"; 895 drive-strength = <2>; 896 bias-disable; 897 }; 898 899 i2c7_sleep: i2c7-sleep-state { 900 pins = "gpio26", "gpio27"; 901 function = "blsp_i2c7"; 902 drive-strength = <2>; 903 bias-pull-up; 904 }; 905 906 i2c8_default: i2c8-default-state { 907 pins = "gpio30", "gpio31"; 908 function = "blsp_i2c8_a"; 909 drive-strength = <2>; 910 bias-disable; 911 }; 912 913 i2c8_sleep: i2c8-sleep-state { 914 pins = "gpio30", "gpio31"; 915 function = "blsp_i2c8_a"; 916 drive-strength = <2>; 917 bias-pull-up; 918 }; 919 920 cci0_default: cci0-default-state { 921 pins = "gpio36","gpio37"; 922 function = "cci_i2c"; 923 bias-pull-up; 924 drive-strength = <2>; 925 }; 926 927 cci1_default: cci1-default-state { 928 pins = "gpio38","gpio39"; 929 function = "cci_i2c"; 930 bias-pull-up; 931 drive-strength = <2>; 932 }; 933 934 sdc1_state_on: sdc1-on-state { 935 clk-pins { 936 pins = "sdc1_clk"; 937 bias-disable; 938 drive-strength = <16>; 939 }; 940 941 cmd-pins { 942 pins = "sdc1_cmd"; 943 bias-pull-up; 944 drive-strength = <10>; 945 }; 946 947 data-pins { 948 pins = "sdc1_data"; 949 bias-pull-up; 950 drive-strength = <10>; 951 }; 952 953 rclk-pins { 954 pins = "sdc1_rclk"; 955 bias-pull-down; 956 }; 957 }; 958 959 sdc1_state_off: sdc1-off-state { 960 clk-pins { 961 pins = "sdc1_clk"; 962 bias-disable; 963 drive-strength = <2>; 964 }; 965 966 cmd-pins { 967 pins = "sdc1_cmd"; 968 bias-pull-up; 969 drive-strength = <2>; 970 }; 971 972 data-pins { 973 pins = "sdc1_data"; 974 bias-pull-up; 975 drive-strength = <2>; 976 }; 977 978 rclk-pins { 979 pins = "sdc1_rclk"; 980 bias-pull-down; 981 }; 982 }; 983 984 sdc2_state_on: sdc2-on-state { 985 clk-pins { 986 pins = "sdc2_clk"; 987 bias-disable; 988 drive-strength = <16>; 989 }; 990 991 cmd-pins { 992 pins = "sdc2_cmd"; 993 bias-pull-up; 994 drive-strength = <10>; 995 }; 996 997 data-pins { 998 pins = "sdc2_data"; 999 bias-pull-up; 1000 drive-strength = <10>; 1001 }; 1002 }; 1003 1004 sdc2_state_off: sdc2-off-state { 1005 clk-pins { 1006 pins = "sdc2_clk"; 1007 bias-disable; 1008 drive-strength = <2>; 1009 }; 1010 1011 cmd-pins { 1012 pins = "sdc2_cmd"; 1013 bias-pull-up; 1014 drive-strength = <2>; 1015 }; 1016 1017 data-pins { 1018 pins = "sdc2_data"; 1019 bias-pull-up; 1020 drive-strength = <2>; 1021 }; 1022 }; 1023 }; 1024 1025 adreno_gpu: gpu@5000000 { 1026 compatible = "qcom,adreno-508.0", "qcom,adreno"; 1027 1028 reg = <0x05000000 0x40000>; 1029 reg-names = "kgsl_3d0_reg_memory"; 1030 1031 interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>; 1032 1033 clocks = <&gcc GCC_GPU_CFG_AHB_CLK>, 1034 <&gpucc GPUCC_RBBMTIMER_CLK>, 1035 <&gcc GCC_BIMC_GFX_CLK>, 1036 <&gcc GCC_GPU_BIMC_GFX_CLK>, 1037 <&gpucc GPUCC_RBCPR_CLK>, 1038 <&gpucc GPUCC_GFX3D_CLK>; 1039 1040 clock-names = "iface", 1041 "rbbmtimer", 1042 "mem", 1043 "mem_iface", 1044 "rbcpr", 1045 "core"; 1046 1047 power-domains = <&rpmpd SDM660_VDDMX>; 1048 iommus = <&kgsl_smmu 0>; 1049 1050 nvmem-cells = <&gpu_speed_bin>; 1051 nvmem-cell-names = "speed_bin"; 1052 1053 interconnects = <&bimc MASTER_OXILI &bimc SLAVE_EBI>; 1054 interconnect-names = "gfx-mem"; 1055 1056 operating-points-v2 = <&gpu_sdm630_opp_table>; 1057 1058 status = "disabled"; 1059 1060 gpu_sdm630_opp_table: opp-table { 1061 compatible = "operating-points-v2"; 1062 opp-775000000 { 1063 opp-hz = /bits/ 64 <775000000>; 1064 opp-level = <RPM_SMD_LEVEL_TURBO>; 1065 opp-peak-kBps = <5412000>; 1066 opp-supported-hw = <0xa2>; 1067 }; 1068 opp-647000000 { 1069 opp-hz = /bits/ 64 <647000000>; 1070 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 1071 opp-peak-kBps = <4068000>; 1072 opp-supported-hw = <0xff>; 1073 }; 1074 opp-588000000 { 1075 opp-hz = /bits/ 64 <588000000>; 1076 opp-level = <RPM_SMD_LEVEL_NOM>; 1077 opp-peak-kBps = <3072000>; 1078 opp-supported-hw = <0xff>; 1079 }; 1080 opp-465000000 { 1081 opp-hz = /bits/ 64 <465000000>; 1082 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 1083 opp-peak-kBps = <2724000>; 1084 opp-supported-hw = <0xff>; 1085 }; 1086 opp-370000000 { 1087 opp-hz = /bits/ 64 <370000000>; 1088 opp-level = <RPM_SMD_LEVEL_SVS>; 1089 opp-peak-kBps = <2188000>; 1090 opp-supported-hw = <0xff>; 1091 }; 1092 opp-240000000 { 1093 opp-hz = /bits/ 64 <240000000>; 1094 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 1095 opp-peak-kBps = <1648000>; 1096 opp-supported-hw = <0xff>; 1097 }; 1098 opp-160000000 { 1099 opp-hz = /bits/ 64 <160000000>; 1100 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 1101 opp-peak-kBps = <1200000>; 1102 opp-supported-hw = <0xff>; 1103 }; 1104 }; 1105 }; 1106 1107 kgsl_smmu: iommu@5040000 { 1108 compatible = "qcom,sdm630-smmu-v2", 1109 "qcom,adreno-smmu", "qcom,smmu-v2"; 1110 reg = <0x05040000 0x10000>; 1111 1112 /* 1113 * GX GDSC parent is CX. We need to bring up CX for SMMU 1114 * but we need both up for Adreno. On the other hand, we 1115 * need to manage the GX rpmpd domain in the adreno driver. 1116 * Enable CX/GX GDSCs here so that we can manage just the GX 1117 * RPM Power Domain in the Adreno driver. 1118 */ 1119 power-domains = <&gpucc GPU_GX_GDSC>; 1120 clocks = <&gcc GCC_GPU_CFG_AHB_CLK>, 1121 <&gcc GCC_BIMC_GFX_CLK>, 1122 <&gcc GCC_GPU_BIMC_GFX_CLK>; 1123 clock-names = "iface", "mem", "mem_iface"; 1124 #global-interrupts = <2>; 1125 #iommu-cells = <1>; 1126 1127 interrupts = 1128 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 1129 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 1130 1131 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 1132 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 1133 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 1134 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 1135 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1136 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1137 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>, 1138 <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>; 1139 1140 status = "disabled"; 1141 }; 1142 1143 gpucc: clock-controller@5065000 { 1144 compatible = "qcom,gpucc-sdm630"; 1145 #clock-cells = <1>; 1146 #reset-cells = <1>; 1147 #power-domain-cells = <1>; 1148 reg = <0x05065000 0x9038>; 1149 1150 clocks = <&xo_board>, 1151 <&gcc GCC_GPU_GPLL0_CLK>, 1152 <&gcc GCC_GPU_GPLL0_DIV_CLK>; 1153 clock-names = "xo", 1154 "gcc_gpu_gpll0_clk", 1155 "gcc_gpu_gpll0_div_clk"; 1156 status = "disabled"; 1157 }; 1158 1159 lpass_smmu: iommu@5100000 { 1160 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2"; 1161 reg = <0x05100000 0x40000>; 1162 #iommu-cells = <1>; 1163 1164 #global-interrupts = <2>; 1165 interrupts = 1166 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 1167 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 1168 1169 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, 1170 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>, 1171 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>, 1172 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 1173 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 1174 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 1175 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 1176 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 1177 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 1178 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 1179 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 1180 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 1181 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 1182 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, 1183 <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>, 1184 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 1185 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>; 1186 1187 status = "disabled"; 1188 }; 1189 1190 sram@290000 { 1191 compatible = "qcom,rpm-stats"; 1192 reg = <0x00290000 0x10000>; 1193 }; 1194 1195 spmi_bus: spmi@800f000 { 1196 compatible = "qcom,spmi-pmic-arb"; 1197 reg = <0x0800f000 0x1000>, 1198 <0x08400000 0x1000000>, 1199 <0x09400000 0x1000000>, 1200 <0x0a400000 0x220000>, 1201 <0x0800a000 0x3000>; 1202 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1203 interrupt-names = "periph_irq"; 1204 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>; 1205 qcom,ee = <0>; 1206 qcom,channel = <0>; 1207 #address-cells = <2>; 1208 #size-cells = <0>; 1209 interrupt-controller; 1210 #interrupt-cells = <4>; 1211 }; 1212 1213 usb3: usb@a8f8800 { 1214 compatible = "qcom,sdm660-dwc3", "qcom,dwc3"; 1215 reg = <0x0a8f8800 0x400>; 1216 status = "disabled"; 1217 #address-cells = <1>; 1218 #size-cells = <1>; 1219 ranges; 1220 1221 clocks = <&gcc GCC_CFG_NOC_USB3_AXI_CLK>, 1222 <&gcc GCC_USB30_MASTER_CLK>, 1223 <&gcc GCC_AGGRE2_USB3_AXI_CLK>, 1224 <&gcc GCC_USB30_SLEEP_CLK>, 1225 <&gcc GCC_USB30_MOCK_UTMI_CLK>, 1226 <&rpmcc RPM_SMD_AGGR2_NOC_CLK>; 1227 clock-names = "cfg_noc", 1228 "core", 1229 "iface", 1230 "sleep", 1231 "mock_utmi", 1232 "bus"; 1233 1234 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, 1235 <&gcc GCC_USB30_MASTER_CLK>, 1236 <&rpmcc RPM_SMD_AGGR2_NOC_CLK>; 1237 assigned-clock-rates = <19200000>, <120000000>, 1238 <19200000>; 1239 1240 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, 1241 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 1242 interrupt-names = "hs_phy_irq", "ss_phy_irq"; 1243 1244 power-domains = <&gcc USB_30_GDSC>; 1245 qcom,select-utmi-as-pipe-clk; 1246 1247 resets = <&gcc GCC_USB_30_BCR>; 1248 1249 usb3_dwc3: usb@a800000 { 1250 compatible = "snps,dwc3"; 1251 reg = <0x0a800000 0xc8d0>; 1252 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 1253 snps,dis_u2_susphy_quirk; 1254 snps,dis_enblslpm_quirk; 1255 1256 /* 1257 * SDM630 technically supports USB3 but I 1258 * haven't seen any devices making use of it. 1259 */ 1260 maximum-speed = "high-speed"; 1261 phys = <&qusb2phy0>; 1262 phy-names = "usb2-phy"; 1263 snps,hird-threshold = /bits/ 8 <0>; 1264 }; 1265 }; 1266 1267 qusb2phy0: phy@c012000 { 1268 compatible = "qcom,sdm660-qusb2-phy"; 1269 reg = <0x0c012000 0x180>; 1270 #phy-cells = <0>; 1271 1272 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 1273 <&gcc GCC_RX0_USB2_CLKREF_CLK>; 1274 clock-names = "cfg_ahb", "ref"; 1275 1276 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 1277 nvmem-cells = <&qusb2_hstx_trim>; 1278 status = "disabled"; 1279 }; 1280 1281 qusb2phy1: phy@c014000 { 1282 compatible = "qcom,sdm660-qusb2-phy"; 1283 reg = <0x0c014000 0x180>; 1284 #phy-cells = <0>; 1285 1286 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 1287 <&gcc GCC_RX1_USB2_CLKREF_CLK>; 1288 clock-names = "cfg_ahb", "ref"; 1289 1290 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 1291 nvmem-cells = <&qusb2_hstx_trim>; 1292 status = "disabled"; 1293 }; 1294 1295 sdhc_2: mmc@c084000 { 1296 compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5"; 1297 reg = <0x0c084000 0x1000>; 1298 reg-names = "hc"; 1299 1300 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1301 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 1302 interrupt-names = "hc_irq", "pwr_irq"; 1303 1304 bus-width = <4>; 1305 1306 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 1307 <&gcc GCC_SDCC2_APPS_CLK>, 1308 <&xo_board>; 1309 clock-names = "iface", "core", "xo"; 1310 1311 1312 interconnects = <&a2noc 3 &a2noc 10>, 1313 <&gnoc 0 &cnoc 28>; 1314 interconnect-names = "sdhc-ddr","cpu-sdhc"; 1315 operating-points-v2 = <&sdhc2_opp_table>; 1316 1317 pinctrl-names = "default", "sleep"; 1318 pinctrl-0 = <&sdc2_state_on>; 1319 pinctrl-1 = <&sdc2_state_off>; 1320 power-domains = <&rpmpd SDM660_VDDCX>; 1321 1322 status = "disabled"; 1323 1324 sdhc2_opp_table: opp-table { 1325 compatible = "operating-points-v2"; 1326 1327 opp-50000000 { 1328 opp-hz = /bits/ 64 <50000000>; 1329 required-opps = <&rpmpd_opp_low_svs>; 1330 opp-peak-kBps = <200000 140000>; 1331 opp-avg-kBps = <130718 133320>; 1332 }; 1333 opp-100000000 { 1334 opp-hz = /bits/ 64 <100000000>; 1335 required-opps = <&rpmpd_opp_svs>; 1336 opp-peak-kBps = <250000 160000>; 1337 opp-avg-kBps = <196078 150000>; 1338 }; 1339 opp-200000000 { 1340 opp-hz = /bits/ 64 <200000000>; 1341 required-opps = <&rpmpd_opp_nom>; 1342 opp-peak-kBps = <4096000 4096000>; 1343 opp-avg-kBps = <1338562 1338562>; 1344 }; 1345 }; 1346 }; 1347 1348 sdhc_1: mmc@c0c4000 { 1349 compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5"; 1350 reg = <0x0c0c4000 0x1000>, 1351 <0x0c0c5000 0x1000>, 1352 <0x0c0c8000 0x8000>; 1353 reg-names = "hc", "cqhci", "ice"; 1354 1355 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1356 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1357 interrupt-names = "hc_irq", "pwr_irq"; 1358 1359 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 1360 <&gcc GCC_SDCC1_APPS_CLK>, 1361 <&xo_board>, 1362 <&gcc GCC_SDCC1_ICE_CORE_CLK>; 1363 clock-names = "iface", "core", "xo", "ice"; 1364 1365 interconnects = <&a2noc 2 &a2noc 10>, 1366 <&gnoc 0 &cnoc 27>; 1367 interconnect-names = "sdhc-ddr", "cpu-sdhc"; 1368 operating-points-v2 = <&sdhc1_opp_table>; 1369 pinctrl-names = "default", "sleep"; 1370 pinctrl-0 = <&sdc1_state_on>; 1371 pinctrl-1 = <&sdc1_state_off>; 1372 power-domains = <&rpmpd SDM660_VDDCX>; 1373 1374 bus-width = <8>; 1375 non-removable; 1376 1377 status = "disabled"; 1378 1379 sdhc1_opp_table: opp-table { 1380 compatible = "operating-points-v2"; 1381 1382 opp-50000000 { 1383 opp-hz = /bits/ 64 <50000000>; 1384 required-opps = <&rpmpd_opp_low_svs>; 1385 opp-peak-kBps = <200000 140000>; 1386 opp-avg-kBps = <130718 133320>; 1387 }; 1388 opp-100000000 { 1389 opp-hz = /bits/ 64 <100000000>; 1390 required-opps = <&rpmpd_opp_svs>; 1391 opp-peak-kBps = <250000 160000>; 1392 opp-avg-kBps = <196078 150000>; 1393 }; 1394 opp-384000000 { 1395 opp-hz = /bits/ 64 <384000000>; 1396 required-opps = <&rpmpd_opp_nom>; 1397 opp-peak-kBps = <4096000 4096000>; 1398 opp-avg-kBps = <1338562 1338562>; 1399 }; 1400 }; 1401 }; 1402 1403 usb2: usb@c2f8800 { 1404 compatible = "qcom,sdm660-dwc3", "qcom,dwc3"; 1405 reg = <0x0c2f8800 0x400>; 1406 status = "disabled"; 1407 #address-cells = <1>; 1408 #size-cells = <1>; 1409 ranges; 1410 1411 clocks = <&gcc GCC_CFG_NOC_USB2_AXI_CLK>, 1412 <&gcc GCC_USB20_MASTER_CLK>, 1413 <&gcc GCC_USB20_MOCK_UTMI_CLK>, 1414 <&gcc GCC_USB20_SLEEP_CLK>; 1415 clock-names = "cfg_noc", "core", 1416 "mock_utmi", "sleep"; 1417 1418 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, 1419 <&gcc GCC_USB20_MASTER_CLK>; 1420 assigned-clock-rates = <19200000>, <60000000>; 1421 1422 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>; 1423 interrupt-names = "hs_phy_irq"; 1424 1425 qcom,select-utmi-as-pipe-clk; 1426 1427 resets = <&gcc GCC_USB_20_BCR>; 1428 1429 usb2_dwc3: usb@c200000 { 1430 compatible = "snps,dwc3"; 1431 reg = <0x0c200000 0xc8d0>; 1432 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 1433 snps,dis_u2_susphy_quirk; 1434 snps,dis_enblslpm_quirk; 1435 1436 /* This is the HS-only host */ 1437 maximum-speed = "high-speed"; 1438 phys = <&qusb2phy1>; 1439 phy-names = "usb2-phy"; 1440 snps,hird-threshold = /bits/ 8 <0>; 1441 }; 1442 }; 1443 1444 mmcc: clock-controller@c8c0000 { 1445 compatible = "qcom,mmcc-sdm630"; 1446 reg = <0x0c8c0000 0x40000>; 1447 #clock-cells = <1>; 1448 #reset-cells = <1>; 1449 #power-domain-cells = <1>; 1450 clock-names = "xo", 1451 "sleep_clk", 1452 "gpll0", 1453 "gpll0_div", 1454 "dsi0pll", 1455 "dsi0pllbyte", 1456 "dsi1pll", 1457 "dsi1pllbyte", 1458 "dp_link_2x_clk_divsel_five", 1459 "dp_vco_divided_clk_src_mux"; 1460 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 1461 <&sleep_clk>, 1462 <&gcc GCC_MMSS_GPLL0_CLK>, 1463 <&gcc GCC_MMSS_GPLL0_DIV_CLK>, 1464 <&dsi0_phy 1>, 1465 <&dsi0_phy 0>, 1466 <0>, 1467 <0>, 1468 <0>, 1469 <0>; 1470 }; 1471 1472 mdss: display-subsystem@c900000 { 1473 compatible = "qcom,mdss"; 1474 reg = <0x0c900000 0x1000>, 1475 <0x0c9b0000 0x1040>; 1476 reg-names = "mdss_phys", "vbif_phys"; 1477 1478 power-domains = <&mmcc MDSS_GDSC>; 1479 1480 clocks = <&mmcc MDSS_AHB_CLK>, 1481 <&mmcc MDSS_AXI_CLK>, 1482 <&mmcc MDSS_VSYNC_CLK>, 1483 <&mmcc MDSS_MDP_CLK>; 1484 clock-names = "iface", 1485 "bus", 1486 "vsync", 1487 "core"; 1488 1489 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 1490 1491 interrupt-controller; 1492 #interrupt-cells = <1>; 1493 1494 #address-cells = <1>; 1495 #size-cells = <1>; 1496 ranges; 1497 status = "disabled"; 1498 1499 mdp: display-controller@c901000 { 1500 compatible = "qcom,sdm630-mdp5", "qcom,mdp5"; 1501 reg = <0x0c901000 0x89000>; 1502 reg-names = "mdp_phys"; 1503 1504 interrupt-parent = <&mdss>; 1505 interrupts = <0>; 1506 1507 assigned-clocks = <&mmcc MDSS_MDP_CLK>, 1508 <&mmcc MDSS_VSYNC_CLK>; 1509 assigned-clock-rates = <300000000>, 1510 <19200000>; 1511 clocks = <&mmcc MDSS_AHB_CLK>, 1512 <&mmcc MDSS_AXI_CLK>, 1513 <&mmcc MDSS_MDP_CLK>, 1514 <&mmcc MDSS_VSYNC_CLK>; 1515 clock-names = "iface", 1516 "bus", 1517 "core", 1518 "vsync"; 1519 1520 interconnects = <&mnoc 2 &bimc 5>, 1521 <&mnoc 3 &bimc 5>, 1522 <&gnoc 0 &mnoc 17>; 1523 interconnect-names = "mdp0-mem", 1524 "mdp1-mem", 1525 "rotator-mem"; 1526 iommus = <&mmss_smmu 0>; 1527 operating-points-v2 = <&mdp_opp_table>; 1528 power-domains = <&rpmpd SDM660_VDDCX>; 1529 1530 ports { 1531 #address-cells = <1>; 1532 #size-cells = <0>; 1533 1534 port@0 { 1535 reg = <0>; 1536 mdp5_intf1_out: endpoint { 1537 remote-endpoint = <&dsi0_in>; 1538 }; 1539 }; 1540 }; 1541 1542 mdp_opp_table: opp-table { 1543 compatible = "operating-points-v2"; 1544 1545 opp-150000000 { 1546 opp-hz = /bits/ 64 <150000000>; 1547 opp-peak-kBps = <320000 320000 76800>; 1548 required-opps = <&rpmpd_opp_low_svs>; 1549 }; 1550 opp-275000000 { 1551 opp-hz = /bits/ 64 <275000000>; 1552 opp-peak-kBps = <6400000 6400000 160000>; 1553 required-opps = <&rpmpd_opp_svs>; 1554 }; 1555 opp-300000000 { 1556 opp-hz = /bits/ 64 <300000000>; 1557 opp-peak-kBps = <6400000 6400000 190000>; 1558 required-opps = <&rpmpd_opp_svs_plus>; 1559 }; 1560 opp-330000000 { 1561 opp-hz = /bits/ 64 <330000000>; 1562 opp-peak-kBps = <6400000 6400000 240000>; 1563 required-opps = <&rpmpd_opp_nom>; 1564 }; 1565 opp-412500000 { 1566 opp-hz = /bits/ 64 <412500000>; 1567 opp-peak-kBps = <6400000 6400000 320000>; 1568 required-opps = <&rpmpd_opp_turbo>; 1569 }; 1570 }; 1571 }; 1572 1573 dsi0: dsi@c994000 { 1574 compatible = "qcom,sdm660-dsi-ctrl", 1575 "qcom,mdss-dsi-ctrl"; 1576 reg = <0x0c994000 0x400>; 1577 reg-names = "dsi_ctrl"; 1578 1579 operating-points-v2 = <&dsi_opp_table>; 1580 power-domains = <&rpmpd SDM660_VDDCX>; 1581 1582 interrupt-parent = <&mdss>; 1583 interrupts = <4>; 1584 1585 assigned-clocks = <&mmcc BYTE0_CLK_SRC>, 1586 <&mmcc PCLK0_CLK_SRC>; 1587 assigned-clock-parents = <&dsi0_phy 0>, 1588 <&dsi0_phy 1>; 1589 1590 clocks = <&mmcc MDSS_MDP_CLK>, 1591 <&mmcc MDSS_BYTE0_CLK>, 1592 <&mmcc MDSS_BYTE0_INTF_CLK>, 1593 <&mmcc MNOC_AHB_CLK>, 1594 <&mmcc MDSS_AHB_CLK>, 1595 <&mmcc MDSS_AXI_CLK>, 1596 <&mmcc MISC_AHB_CLK>, 1597 <&mmcc MDSS_PCLK0_CLK>, 1598 <&mmcc MDSS_ESC0_CLK>; 1599 clock-names = "mdp_core", 1600 "byte", 1601 "byte_intf", 1602 "mnoc", 1603 "iface", 1604 "bus", 1605 "core_mmss", 1606 "pixel", 1607 "core"; 1608 1609 phys = <&dsi0_phy>; 1610 1611 status = "disabled"; 1612 1613 ports { 1614 #address-cells = <1>; 1615 #size-cells = <0>; 1616 1617 port@0 { 1618 reg = <0>; 1619 dsi0_in: endpoint { 1620 remote-endpoint = <&mdp5_intf1_out>; 1621 }; 1622 }; 1623 1624 port@1 { 1625 reg = <1>; 1626 dsi0_out: endpoint { 1627 }; 1628 }; 1629 }; 1630 }; 1631 1632 dsi0_phy: phy@c994400 { 1633 compatible = "qcom,dsi-phy-14nm-660"; 1634 reg = <0x0c994400 0x100>, 1635 <0x0c994500 0x300>, 1636 <0x0c994800 0x188>; 1637 reg-names = "dsi_phy", 1638 "dsi_phy_lane", 1639 "dsi_pll"; 1640 1641 #clock-cells = <1>; 1642 #phy-cells = <0>; 1643 1644 clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>; 1645 clock-names = "iface", "ref"; 1646 status = "disabled"; 1647 }; 1648 }; 1649 1650 blsp1_dma: dma-controller@c144000 { 1651 compatible = "qcom,bam-v1.7.0"; 1652 reg = <0x0c144000 0x1f000>; 1653 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 1654 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 1655 clock-names = "bam_clk"; 1656 #dma-cells = <1>; 1657 qcom,ee = <0>; 1658 qcom,controlled-remotely; 1659 num-channels = <18>; 1660 qcom,num-ees = <4>; 1661 }; 1662 1663 blsp1_uart1: serial@c16f000 { 1664 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1665 reg = <0x0c16f000 0x200>; 1666 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1667 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, 1668 <&gcc GCC_BLSP1_AHB_CLK>; 1669 clock-names = "core", "iface"; 1670 dmas = <&blsp1_dma 0>, <&blsp1_dma 1>; 1671 dma-names = "tx", "rx"; 1672 pinctrl-names = "default", "sleep"; 1673 pinctrl-0 = <&blsp1_uart1_default>; 1674 pinctrl-1 = <&blsp1_uart1_sleep>; 1675 status = "disabled"; 1676 }; 1677 1678 blsp1_uart2: serial@c170000 { 1679 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1680 reg = <0x0c170000 0x1000>; 1681 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1682 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, 1683 <&gcc GCC_BLSP1_AHB_CLK>; 1684 clock-names = "core", "iface"; 1685 dmas = <&blsp1_dma 2>, <&blsp1_dma 3>; 1686 dma-names = "tx", "rx"; 1687 pinctrl-names = "default"; 1688 pinctrl-0 = <&blsp1_uart2_default>; 1689 status = "disabled"; 1690 }; 1691 1692 blsp_i2c1: i2c@c175000 { 1693 compatible = "qcom,i2c-qup-v2.2.1"; 1694 reg = <0x0c175000 0x600>; 1695 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1696 1697 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, 1698 <&gcc GCC_BLSP1_AHB_CLK>; 1699 clock-names = "core", "iface"; 1700 clock-frequency = <400000>; 1701 dmas = <&blsp1_dma 4>, <&blsp1_dma 5>; 1702 dma-names = "tx", "rx"; 1703 1704 pinctrl-names = "default", "sleep"; 1705 pinctrl-0 = <&i2c1_default>; 1706 pinctrl-1 = <&i2c1_sleep>; 1707 #address-cells = <1>; 1708 #size-cells = <0>; 1709 status = "disabled"; 1710 }; 1711 1712 blsp_i2c2: i2c@c176000 { 1713 compatible = "qcom,i2c-qup-v2.2.1"; 1714 reg = <0x0c176000 0x600>; 1715 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1716 1717 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 1718 <&gcc GCC_BLSP1_AHB_CLK>; 1719 clock-names = "core", "iface"; 1720 clock-frequency = <400000>; 1721 dmas = <&blsp1_dma 6>, <&blsp1_dma 7>; 1722 dma-names = "tx", "rx"; 1723 1724 pinctrl-names = "default", "sleep"; 1725 pinctrl-0 = <&i2c2_default>; 1726 pinctrl-1 = <&i2c2_sleep>; 1727 #address-cells = <1>; 1728 #size-cells = <0>; 1729 status = "disabled"; 1730 }; 1731 1732 blsp_i2c3: i2c@c177000 { 1733 compatible = "qcom,i2c-qup-v2.2.1"; 1734 reg = <0x0c177000 0x600>; 1735 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1736 1737 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 1738 <&gcc GCC_BLSP1_AHB_CLK>; 1739 clock-names = "core", "iface"; 1740 clock-frequency = <400000>; 1741 dmas = <&blsp1_dma 8>, <&blsp1_dma 9>; 1742 dma-names = "tx", "rx"; 1743 1744 pinctrl-names = "default", "sleep"; 1745 pinctrl-0 = <&i2c3_default>; 1746 pinctrl-1 = <&i2c3_sleep>; 1747 #address-cells = <1>; 1748 #size-cells = <0>; 1749 status = "disabled"; 1750 }; 1751 1752 blsp_i2c4: i2c@c178000 { 1753 compatible = "qcom,i2c-qup-v2.2.1"; 1754 reg = <0x0c178000 0x600>; 1755 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1756 1757 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, 1758 <&gcc GCC_BLSP1_AHB_CLK>; 1759 clock-names = "core", "iface"; 1760 clock-frequency = <400000>; 1761 dmas = <&blsp1_dma 10>, <&blsp1_dma 11>; 1762 dma-names = "tx", "rx"; 1763 1764 pinctrl-names = "default", "sleep"; 1765 pinctrl-0 = <&i2c4_default>; 1766 pinctrl-1 = <&i2c4_sleep>; 1767 #address-cells = <1>; 1768 #size-cells = <0>; 1769 status = "disabled"; 1770 }; 1771 1772 blsp2_dma: dma-controller@c184000 { 1773 compatible = "qcom,bam-v1.7.0"; 1774 reg = <0x0c184000 0x1f000>; 1775 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 1776 clocks = <&gcc GCC_BLSP2_AHB_CLK>; 1777 clock-names = "bam_clk"; 1778 #dma-cells = <1>; 1779 qcom,ee = <0>; 1780 qcom,controlled-remotely; 1781 num-channels = <18>; 1782 qcom,num-ees = <4>; 1783 }; 1784 1785 blsp2_uart1: serial@c1af000 { 1786 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1787 reg = <0x0c1af000 0x200>; 1788 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 1789 clocks = <&gcc GCC_BLSP2_UART1_APPS_CLK>, 1790 <&gcc GCC_BLSP2_AHB_CLK>; 1791 clock-names = "core", "iface"; 1792 dmas = <&blsp2_dma 0>, <&blsp2_dma 1>; 1793 dma-names = "tx", "rx"; 1794 pinctrl-names = "default", "sleep"; 1795 pinctrl-0 = <&blsp2_uart1_default>; 1796 pinctrl-1 = <&blsp2_uart1_sleep>; 1797 status = "disabled"; 1798 }; 1799 1800 blsp_i2c5: i2c@c1b5000 { 1801 compatible = "qcom,i2c-qup-v2.2.1"; 1802 reg = <0x0c1b5000 0x600>; 1803 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 1804 1805 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, 1806 <&gcc GCC_BLSP2_AHB_CLK>; 1807 clock-names = "core", "iface"; 1808 clock-frequency = <400000>; 1809 dmas = <&blsp2_dma 4>, <&blsp2_dma 5>; 1810 dma-names = "tx", "rx"; 1811 1812 pinctrl-names = "default", "sleep"; 1813 pinctrl-0 = <&i2c5_default>; 1814 pinctrl-1 = <&i2c5_sleep>; 1815 #address-cells = <1>; 1816 #size-cells = <0>; 1817 status = "disabled"; 1818 }; 1819 1820 blsp_i2c6: i2c@c1b6000 { 1821 compatible = "qcom,i2c-qup-v2.2.1"; 1822 reg = <0x0c1b6000 0x600>; 1823 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 1824 1825 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, 1826 <&gcc GCC_BLSP2_AHB_CLK>; 1827 clock-names = "core", "iface"; 1828 clock-frequency = <400000>; 1829 dmas = <&blsp2_dma 6>, <&blsp2_dma 7>; 1830 dma-names = "tx", "rx"; 1831 1832 pinctrl-names = "default", "sleep"; 1833 pinctrl-0 = <&i2c6_default>; 1834 pinctrl-1 = <&i2c6_sleep>; 1835 #address-cells = <1>; 1836 #size-cells = <0>; 1837 status = "disabled"; 1838 }; 1839 1840 blsp_i2c7: i2c@c1b7000 { 1841 compatible = "qcom,i2c-qup-v2.2.1"; 1842 reg = <0x0c1b7000 0x600>; 1843 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 1844 1845 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>, 1846 <&gcc GCC_BLSP2_AHB_CLK>; 1847 clock-names = "core", "iface"; 1848 clock-frequency = <400000>; 1849 dmas = <&blsp2_dma 8>, <&blsp2_dma 9>; 1850 dma-names = "tx", "rx"; 1851 1852 pinctrl-names = "default", "sleep"; 1853 pinctrl-0 = <&i2c7_default>; 1854 pinctrl-1 = <&i2c7_sleep>; 1855 #address-cells = <1>; 1856 #size-cells = <0>; 1857 status = "disabled"; 1858 }; 1859 1860 blsp_i2c8: i2c@c1b8000 { 1861 compatible = "qcom,i2c-qup-v2.2.1"; 1862 reg = <0x0c1b8000 0x600>; 1863 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 1864 1865 clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>, 1866 <&gcc GCC_BLSP2_AHB_CLK>; 1867 clock-names = "core", "iface"; 1868 clock-frequency = <400000>; 1869 dmas = <&blsp2_dma 10>, <&blsp2_dma 11>; 1870 dma-names = "tx", "rx"; 1871 1872 pinctrl-names = "default", "sleep"; 1873 pinctrl-0 = <&i2c8_default>; 1874 pinctrl-1 = <&i2c8_sleep>; 1875 #address-cells = <1>; 1876 #size-cells = <0>; 1877 status = "disabled"; 1878 }; 1879 1880 sram@146bf000 { 1881 compatible = "qcom,sdm630-imem", "syscon", "simple-mfd"; 1882 reg = <0x146bf000 0x1000>; 1883 1884 #address-cells = <1>; 1885 #size-cells = <1>; 1886 1887 ranges = <0 0x146bf000 0x1000>; 1888 1889 pil-reloc@94c { 1890 compatible = "qcom,pil-reloc-info"; 1891 reg = <0x94c 0xc8>; 1892 }; 1893 }; 1894 1895 camss: camss@ca00000 { 1896 compatible = "qcom,sdm660-camss"; 1897 reg = <0x0ca00020 0x10>, 1898 <0x0ca30000 0x100>, 1899 <0x0ca30400 0x100>, 1900 <0x0ca30800 0x100>, 1901 <0x0ca30c00 0x100>, 1902 <0x0c824000 0x1000>, 1903 <0x0ca00120 0x4>, 1904 <0x0c825000 0x1000>, 1905 <0x0ca00124 0x4>, 1906 <0x0c826000 0x1000>, 1907 <0x0ca00128 0x4>, 1908 <0x0ca31000 0x500>, 1909 <0x0ca10000 0x1000>, 1910 <0x0ca14000 0x1000>; 1911 reg-names = "csi_clk_mux", 1912 "csid0", 1913 "csid1", 1914 "csid2", 1915 "csid3", 1916 "csiphy0", 1917 "csiphy0_clk_mux", 1918 "csiphy1", 1919 "csiphy1_clk_mux", 1920 "csiphy2", 1921 "csiphy2_clk_mux", 1922 "ispif", 1923 "vfe0", 1924 "vfe1"; 1925 interrupts = <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>, 1926 <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>, 1927 <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>, 1928 <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>, 1929 <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>, 1930 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>, 1931 <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>, 1932 <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>, 1933 <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>, 1934 <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>; 1935 interrupt-names = "csid0", 1936 "csid1", 1937 "csid2", 1938 "csid3", 1939 "csiphy0", 1940 "csiphy1", 1941 "csiphy2", 1942 "ispif", 1943 "vfe0", 1944 "vfe1"; 1945 clocks = <&mmcc CAMSS_AHB_CLK>, 1946 <&mmcc CAMSS_CPHY_CSID0_CLK>, 1947 <&mmcc CAMSS_CPHY_CSID1_CLK>, 1948 <&mmcc CAMSS_CPHY_CSID2_CLK>, 1949 <&mmcc CAMSS_CPHY_CSID3_CLK>, 1950 <&mmcc CAMSS_CSI0_AHB_CLK>, 1951 <&mmcc CAMSS_CSI0_CLK>, 1952 <&mmcc CAMSS_CPHY_CSID0_CLK>, 1953 <&mmcc CAMSS_CSI0PIX_CLK>, 1954 <&mmcc CAMSS_CSI0RDI_CLK>, 1955 <&mmcc CAMSS_CSI1_AHB_CLK>, 1956 <&mmcc CAMSS_CSI1_CLK>, 1957 <&mmcc CAMSS_CPHY_CSID1_CLK>, 1958 <&mmcc CAMSS_CSI1PIX_CLK>, 1959 <&mmcc CAMSS_CSI1RDI_CLK>, 1960 <&mmcc CAMSS_CSI2_AHB_CLK>, 1961 <&mmcc CAMSS_CSI2_CLK>, 1962 <&mmcc CAMSS_CPHY_CSID2_CLK>, 1963 <&mmcc CAMSS_CSI2PIX_CLK>, 1964 <&mmcc CAMSS_CSI2RDI_CLK>, 1965 <&mmcc CAMSS_CSI3_AHB_CLK>, 1966 <&mmcc CAMSS_CSI3_CLK>, 1967 <&mmcc CAMSS_CPHY_CSID3_CLK>, 1968 <&mmcc CAMSS_CSI3PIX_CLK>, 1969 <&mmcc CAMSS_CSI3RDI_CLK>, 1970 <&mmcc CAMSS_CSI0PHYTIMER_CLK>, 1971 <&mmcc CAMSS_CSI1PHYTIMER_CLK>, 1972 <&mmcc CAMSS_CSI2PHYTIMER_CLK>, 1973 <&mmcc CSIPHY_AHB2CRIF_CLK>, 1974 <&mmcc CAMSS_CSI_VFE0_CLK>, 1975 <&mmcc CAMSS_CSI_VFE1_CLK>, 1976 <&mmcc CAMSS_ISPIF_AHB_CLK>, 1977 <&mmcc THROTTLE_CAMSS_AXI_CLK>, 1978 <&mmcc CAMSS_TOP_AHB_CLK>, 1979 <&mmcc CAMSS_VFE0_AHB_CLK>, 1980 <&mmcc CAMSS_VFE0_CLK>, 1981 <&mmcc CAMSS_VFE0_STREAM_CLK>, 1982 <&mmcc CAMSS_VFE1_AHB_CLK>, 1983 <&mmcc CAMSS_VFE1_CLK>, 1984 <&mmcc CAMSS_VFE1_STREAM_CLK>, 1985 <&mmcc CAMSS_VFE_VBIF_AHB_CLK>, 1986 <&mmcc CAMSS_VFE_VBIF_AXI_CLK>; 1987 clock-names = "ahb", 1988 "cphy_csid0", 1989 "cphy_csid1", 1990 "cphy_csid2", 1991 "cphy_csid3", 1992 "csi0_ahb", 1993 "csi0", 1994 "csi0_phy", 1995 "csi0_pix", 1996 "csi0_rdi", 1997 "csi1_ahb", 1998 "csi1", 1999 "csi1_phy", 2000 "csi1_pix", 2001 "csi1_rdi", 2002 "csi2_ahb", 2003 "csi2", 2004 "csi2_phy", 2005 "csi2_pix", 2006 "csi2_rdi", 2007 "csi3_ahb", 2008 "csi3", 2009 "csi3_phy", 2010 "csi3_pix", 2011 "csi3_rdi", 2012 "csiphy0_timer", 2013 "csiphy1_timer", 2014 "csiphy2_timer", 2015 "csiphy_ahb2crif", 2016 "csi_vfe0", 2017 "csi_vfe1", 2018 "ispif_ahb", 2019 "throttle_axi", 2020 "top_ahb", 2021 "vfe0_ahb", 2022 "vfe0", 2023 "vfe0_stream", 2024 "vfe1_ahb", 2025 "vfe1", 2026 "vfe1_stream", 2027 "vfe_ahb", 2028 "vfe_axi"; 2029 interconnects = <&mnoc 5 &bimc 5>; 2030 interconnect-names = "vfe-mem"; 2031 iommus = <&mmss_smmu 0xc00>, 2032 <&mmss_smmu 0xc01>, 2033 <&mmss_smmu 0xc02>, 2034 <&mmss_smmu 0xc03>; 2035 power-domains = <&mmcc CAMSS_VFE0_GDSC>, 2036 <&mmcc CAMSS_VFE1_GDSC>; 2037 status = "disabled"; 2038 2039 ports { 2040 #address-cells = <1>; 2041 #size-cells = <0>; 2042 }; 2043 }; 2044 2045 cci: cci@ca0c000 { 2046 compatible = "qcom,msm8996-cci"; 2047 #address-cells = <1>; 2048 #size-cells = <0>; 2049 reg = <0x0ca0c000 0x1000>; 2050 interrupts = <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>; 2051 2052 assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>, 2053 <&mmcc CAMSS_CCI_CLK>; 2054 assigned-clock-rates = <80800000>, <37500000>; 2055 clocks = <&mmcc CAMSS_TOP_AHB_CLK>, 2056 <&mmcc CAMSS_CCI_AHB_CLK>, 2057 <&mmcc CAMSS_CCI_CLK>, 2058 <&mmcc CAMSS_AHB_CLK>; 2059 clock-names = "camss_top_ahb", 2060 "cci_ahb", 2061 "cci", 2062 "camss_ahb"; 2063 2064 pinctrl-names = "default"; 2065 pinctrl-0 = <&cci0_default &cci1_default>; 2066 power-domains = <&mmcc CAMSS_TOP_GDSC>; 2067 status = "disabled"; 2068 2069 cci_i2c0: i2c-bus@0 { 2070 reg = <0>; 2071 clock-frequency = <400000>; 2072 #address-cells = <1>; 2073 #size-cells = <0>; 2074 }; 2075 2076 cci_i2c1: i2c-bus@1 { 2077 reg = <1>; 2078 clock-frequency = <400000>; 2079 #address-cells = <1>; 2080 #size-cells = <0>; 2081 }; 2082 }; 2083 2084 venus: video-codec@cc00000 { 2085 compatible = "qcom,sdm660-venus"; 2086 reg = <0x0cc00000 0xff000>; 2087 clocks = <&mmcc VIDEO_CORE_CLK>, 2088 <&mmcc VIDEO_AHB_CLK>, 2089 <&mmcc VIDEO_AXI_CLK>, 2090 <&mmcc THROTTLE_VIDEO_AXI_CLK>; 2091 clock-names = "core", "iface", "bus", "bus_throttle"; 2092 interconnects = <&gnoc 0 &mnoc 13>, 2093 <&mnoc 4 &bimc 5>; 2094 interconnect-names = "cpu-cfg", "video-mem"; 2095 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 2096 iommus = <&mmss_smmu 0x400>, 2097 <&mmss_smmu 0x401>, 2098 <&mmss_smmu 0x40a>, 2099 <&mmss_smmu 0x407>, 2100 <&mmss_smmu 0x40e>, 2101 <&mmss_smmu 0x40f>, 2102 <&mmss_smmu 0x408>, 2103 <&mmss_smmu 0x409>, 2104 <&mmss_smmu 0x40b>, 2105 <&mmss_smmu 0x40c>, 2106 <&mmss_smmu 0x40d>, 2107 <&mmss_smmu 0x410>, 2108 <&mmss_smmu 0x421>, 2109 <&mmss_smmu 0x428>, 2110 <&mmss_smmu 0x429>, 2111 <&mmss_smmu 0x42b>, 2112 <&mmss_smmu 0x42c>, 2113 <&mmss_smmu 0x42d>, 2114 <&mmss_smmu 0x411>, 2115 <&mmss_smmu 0x431>; 2116 memory-region = <&venus_region>; 2117 power-domains = <&mmcc VENUS_GDSC>; 2118 status = "disabled"; 2119 2120 video-decoder { 2121 compatible = "venus-decoder"; 2122 clocks = <&mmcc VIDEO_SUBCORE0_CLK>; 2123 clock-names = "vcodec0_core"; 2124 power-domains = <&mmcc VENUS_CORE0_GDSC>; 2125 }; 2126 2127 video-encoder { 2128 compatible = "venus-encoder"; 2129 clocks = <&mmcc VIDEO_SUBCORE0_CLK>; 2130 clock-names = "vcodec0_core"; 2131 power-domains = <&mmcc VENUS_CORE0_GDSC>; 2132 }; 2133 }; 2134 2135 mmss_smmu: iommu@cd00000 { 2136 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2"; 2137 reg = <0x0cd00000 0x40000>; 2138 2139 clocks = <&mmcc MNOC_AHB_CLK>, 2140 <&mmcc BIMC_SMMU_AHB_CLK>, 2141 <&rpmcc RPM_SMD_MMSSNOC_AXI_CLK>, 2142 <&mmcc BIMC_SMMU_AXI_CLK>; 2143 clock-names = "iface-mm", "iface-smmu", 2144 "bus-mm", "bus-smmu"; 2145 #global-interrupts = <2>; 2146 #iommu-cells = <1>; 2147 2148 interrupts = 2149 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 2150 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 2151 2152 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 2153 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 2154 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, 2155 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 2156 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 2157 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 2158 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 2159 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 2160 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 2161 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 2162 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 2163 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 2164 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 2165 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 2166 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 2167 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 2168 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 2169 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 2170 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 2171 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, 2172 <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, 2173 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 2174 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 2175 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>; 2176 2177 status = "disabled"; 2178 }; 2179 2180 adsp_pil: remoteproc@15700000 { 2181 compatible = "qcom,sdm660-adsp-pas"; 2182 reg = <0x15700000 0x4040>; 2183 2184 interrupts-extended = 2185 <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 2186 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2187 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2188 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2189 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2190 interrupt-names = "wdog", "fatal", "ready", 2191 "handover", "stop-ack"; 2192 2193 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 2194 clock-names = "xo"; 2195 2196 memory-region = <&adsp_region>; 2197 power-domains = <&rpmpd SDM660_VDDCX>; 2198 power-domain-names = "cx"; 2199 2200 qcom,smem-states = <&adsp_smp2p_out 0>; 2201 qcom,smem-state-names = "stop"; 2202 2203 glink-edge { 2204 interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>; 2205 2206 label = "lpass"; 2207 mboxes = <&apcs_glb 9>; 2208 qcom,remote-pid = <2>; 2209 2210 apr { 2211 compatible = "qcom,apr-v2"; 2212 qcom,glink-channels = "apr_audio_svc"; 2213 qcom,domain = <APR_DOMAIN_ADSP>; 2214 #address-cells = <1>; 2215 #size-cells = <0>; 2216 2217 service@3 { 2218 reg = <APR_SVC_ADSP_CORE>; 2219 compatible = "qcom,q6core"; 2220 }; 2221 2222 q6afe: service@4 { 2223 compatible = "qcom,q6afe"; 2224 reg = <APR_SVC_AFE>; 2225 q6afedai: dais { 2226 compatible = "qcom,q6afe-dais"; 2227 #address-cells = <1>; 2228 #size-cells = <0>; 2229 #sound-dai-cells = <1>; 2230 }; 2231 }; 2232 2233 q6asm: service@7 { 2234 compatible = "qcom,q6asm"; 2235 reg = <APR_SVC_ASM>; 2236 q6asmdai: dais { 2237 compatible = "qcom,q6asm-dais"; 2238 #address-cells = <1>; 2239 #size-cells = <0>; 2240 #sound-dai-cells = <1>; 2241 iommus = <&lpass_smmu 1>; 2242 }; 2243 }; 2244 2245 q6adm: service@8 { 2246 compatible = "qcom,q6adm"; 2247 reg = <APR_SVC_ADM>; 2248 q6routing: routing { 2249 compatible = "qcom,q6adm-routing"; 2250 #sound-dai-cells = <0>; 2251 }; 2252 }; 2253 }; 2254 }; 2255 }; 2256 2257 gnoc: interconnect@17900000 { 2258 compatible = "qcom,sdm660-gnoc"; 2259 reg = <0x17900000 0xe000>; 2260 #interconnect-cells = <1>; 2261 /* 2262 * This one apparently features no clocks, 2263 * so let's not mess with the driver needlessly 2264 */ 2265 clock-names = "bus", "bus_a"; 2266 clocks = <&xo_board>, <&xo_board>; 2267 }; 2268 2269 apcs_glb: mailbox@17911000 { 2270 compatible = "qcom,sdm660-apcs-hmss-global", 2271 "qcom,msm8994-apcs-kpss-global"; 2272 reg = <0x17911000 0x1000>; 2273 2274 #mbox-cells = <1>; 2275 }; 2276 2277 timer@17920000 { 2278 #address-cells = <1>; 2279 #size-cells = <1>; 2280 ranges; 2281 compatible = "arm,armv7-timer-mem"; 2282 reg = <0x17920000 0x1000>; 2283 clock-frequency = <19200000>; 2284 2285 frame@17921000 { 2286 frame-number = <0>; 2287 interrupts = <0 8 0x4>, 2288 <0 7 0x4>; 2289 reg = <0x17921000 0x1000>, 2290 <0x17922000 0x1000>; 2291 }; 2292 2293 frame@17923000 { 2294 frame-number = <1>; 2295 interrupts = <0 9 0x4>; 2296 reg = <0x17923000 0x1000>; 2297 status = "disabled"; 2298 }; 2299 2300 frame@17924000 { 2301 frame-number = <2>; 2302 interrupts = <0 10 0x4>; 2303 reg = <0x17924000 0x1000>; 2304 status = "disabled"; 2305 }; 2306 2307 frame@17925000 { 2308 frame-number = <3>; 2309 interrupts = <0 11 0x4>; 2310 reg = <0x17925000 0x1000>; 2311 status = "disabled"; 2312 }; 2313 2314 frame@17926000 { 2315 frame-number = <4>; 2316 interrupts = <0 12 0x4>; 2317 reg = <0x17926000 0x1000>; 2318 status = "disabled"; 2319 }; 2320 2321 frame@17927000 { 2322 frame-number = <5>; 2323 interrupts = <0 13 0x4>; 2324 reg = <0x17927000 0x1000>; 2325 status = "disabled"; 2326 }; 2327 2328 frame@17928000 { 2329 frame-number = <6>; 2330 interrupts = <0 14 0x4>; 2331 reg = <0x17928000 0x1000>; 2332 status = "disabled"; 2333 }; 2334 }; 2335 2336 intc: interrupt-controller@17a00000 { 2337 compatible = "arm,gic-v3"; 2338 reg = <0x17a00000 0x10000>, /* GICD */ 2339 <0x17b00000 0x100000>; /* GICR * 8 */ 2340 #interrupt-cells = <3>; 2341 #address-cells = <1>; 2342 #size-cells = <1>; 2343 ranges; 2344 interrupt-controller; 2345 #redistributor-regions = <1>; 2346 redistributor-stride = <0x0 0x20000>; 2347 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 2348 }; 2349 }; 2350 2351 sound: sound { 2352 }; 2353 2354 thermal-zones { 2355 aoss-thermal { 2356 polling-delay-passive = <250>; 2357 polling-delay = <1000>; 2358 2359 thermal-sensors = <&tsens 0>; 2360 2361 trips { 2362 aoss_alert0: trip-point0 { 2363 temperature = <105000>; 2364 hysteresis = <1000>; 2365 type = "hot"; 2366 }; 2367 }; 2368 }; 2369 2370 cpuss0-thermal { 2371 polling-delay-passive = <250>; 2372 polling-delay = <1000>; 2373 2374 thermal-sensors = <&tsens 1>; 2375 2376 trips { 2377 cpuss0_alert0: trip-point0 { 2378 temperature = <125000>; 2379 hysteresis = <1000>; 2380 type = "hot"; 2381 }; 2382 }; 2383 }; 2384 2385 cpuss1-thermal { 2386 polling-delay-passive = <250>; 2387 polling-delay = <1000>; 2388 2389 thermal-sensors = <&tsens 2>; 2390 2391 trips { 2392 cpuss1_alert0: trip-point0 { 2393 temperature = <125000>; 2394 hysteresis = <1000>; 2395 type = "hot"; 2396 }; 2397 }; 2398 }; 2399 2400 cpu0-thermal { 2401 polling-delay-passive = <250>; 2402 polling-delay = <1000>; 2403 2404 thermal-sensors = <&tsens 3>; 2405 2406 trips { 2407 cpu0_alert0: trip-point0 { 2408 temperature = <70000>; 2409 hysteresis = <1000>; 2410 type = "passive"; 2411 }; 2412 2413 cpu0_crit: cpu-crit { 2414 temperature = <110000>; 2415 hysteresis = <1000>; 2416 type = "critical"; 2417 }; 2418 }; 2419 }; 2420 2421 cpu1-thermal { 2422 polling-delay-passive = <250>; 2423 polling-delay = <1000>; 2424 2425 thermal-sensors = <&tsens 4>; 2426 2427 trips { 2428 cpu1_alert0: trip-point0 { 2429 temperature = <70000>; 2430 hysteresis = <1000>; 2431 type = "passive"; 2432 }; 2433 2434 cpu1_crit: cpu-crit { 2435 temperature = <110000>; 2436 hysteresis = <1000>; 2437 type = "critical"; 2438 }; 2439 }; 2440 }; 2441 2442 cpu2-thermal { 2443 polling-delay-passive = <250>; 2444 polling-delay = <1000>; 2445 2446 thermal-sensors = <&tsens 5>; 2447 2448 trips { 2449 cpu2_alert0: trip-point0 { 2450 temperature = <70000>; 2451 hysteresis = <1000>; 2452 type = "passive"; 2453 }; 2454 2455 cpu2_crit: cpu-crit { 2456 temperature = <110000>; 2457 hysteresis = <1000>; 2458 type = "critical"; 2459 }; 2460 }; 2461 }; 2462 2463 cpu3-thermal { 2464 polling-delay-passive = <250>; 2465 polling-delay = <1000>; 2466 2467 thermal-sensors = <&tsens 6>; 2468 2469 trips { 2470 cpu3_alert0: trip-point0 { 2471 temperature = <70000>; 2472 hysteresis = <1000>; 2473 type = "passive"; 2474 }; 2475 2476 cpu3_crit: cpu-crit { 2477 temperature = <110000>; 2478 hysteresis = <1000>; 2479 type = "critical"; 2480 }; 2481 }; 2482 }; 2483 2484 /* 2485 * According to what downstream DTS says, 2486 * the entire power efficient cluster has 2487 * only a single thermal sensor. 2488 */ 2489 2490 pwr-cluster-thermal { 2491 polling-delay-passive = <250>; 2492 polling-delay = <1000>; 2493 2494 thermal-sensors = <&tsens 7>; 2495 2496 trips { 2497 pwr_cluster_alert0: trip-point0 { 2498 temperature = <70000>; 2499 hysteresis = <1000>; 2500 type = "passive"; 2501 }; 2502 2503 pwr_cluster_crit: cpu-crit { 2504 temperature = <110000>; 2505 hysteresis = <1000>; 2506 type = "critical"; 2507 }; 2508 }; 2509 }; 2510 2511 gpu-thermal { 2512 polling-delay-passive = <250>; 2513 polling-delay = <1000>; 2514 2515 thermal-sensors = <&tsens 8>; 2516 2517 trips { 2518 gpu_alert0: trip-point0 { 2519 temperature = <90000>; 2520 hysteresis = <1000>; 2521 type = "hot"; 2522 }; 2523 }; 2524 }; 2525 }; 2526 2527 timer { 2528 compatible = "arm,armv8-timer"; 2529 interrupts = <GIC_PPI 1 0xf08>, 2530 <GIC_PPI 2 0xf08>, 2531 <GIC_PPI 3 0xf08>, 2532 <GIC_PPI 0 0xf08>; 2533 }; 2534}; 2535 2536