1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2020, Konrad Dybcio <konradybcio@gmail.com> 4 * Copyright (c) 2020, AngeloGioacchino Del Regno <kholk11@gmail.com> 5 */ 6 7#include <dt-bindings/clock/qcom,gcc-sdm660.h> 8#include <dt-bindings/clock/qcom,gpucc-sdm660.h> 9#include <dt-bindings/clock/qcom,mmcc-sdm660.h> 10#include <dt-bindings/clock/qcom,rpmcc.h> 11#include <dt-bindings/power/qcom-rpmpd.h> 12#include <dt-bindings/gpio/gpio.h> 13#include <dt-bindings/interrupt-controller/arm-gic.h> 14#include <dt-bindings/soc/qcom,apr.h> 15 16/ { 17 interrupt-parent = <&intc>; 18 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 chosen { }; 23 24 clocks { 25 xo_board: xo-board { 26 compatible = "fixed-clock"; 27 #clock-cells = <0>; 28 clock-frequency = <19200000>; 29 clock-output-names = "xo_board"; 30 }; 31 32 sleep_clk: sleep-clk { 33 compatible = "fixed-clock"; 34 #clock-cells = <0>; 35 clock-frequency = <32764>; 36 clock-output-names = "sleep_clk"; 37 }; 38 }; 39 40 cpus { 41 #address-cells = <2>; 42 #size-cells = <0>; 43 44 CPU0: cpu@100 { 45 device_type = "cpu"; 46 compatible = "arm,cortex-a53"; 47 reg = <0x0 0x100>; 48 enable-method = "psci"; 49 cpu-idle-states = <&PERF_CPU_SLEEP_0 50 &PERF_CPU_SLEEP_1 51 &PERF_CLUSTER_SLEEP_0 52 &PERF_CLUSTER_SLEEP_1 53 &PERF_CLUSTER_SLEEP_2>; 54 capacity-dmips-mhz = <1126>; 55 #cooling-cells = <2>; 56 next-level-cache = <&L2_1>; 57 L2_1: l2-cache { 58 compatible = "cache"; 59 cache-level = <2>; 60 }; 61 }; 62 63 CPU1: cpu@101 { 64 device_type = "cpu"; 65 compatible = "arm,cortex-a53"; 66 reg = <0x0 0x101>; 67 enable-method = "psci"; 68 cpu-idle-states = <&PERF_CPU_SLEEP_0 69 &PERF_CPU_SLEEP_1 70 &PERF_CLUSTER_SLEEP_0 71 &PERF_CLUSTER_SLEEP_1 72 &PERF_CLUSTER_SLEEP_2>; 73 capacity-dmips-mhz = <1126>; 74 #cooling-cells = <2>; 75 next-level-cache = <&L2_1>; 76 }; 77 78 CPU2: cpu@102 { 79 device_type = "cpu"; 80 compatible = "arm,cortex-a53"; 81 reg = <0x0 0x102>; 82 enable-method = "psci"; 83 cpu-idle-states = <&PERF_CPU_SLEEP_0 84 &PERF_CPU_SLEEP_1 85 &PERF_CLUSTER_SLEEP_0 86 &PERF_CLUSTER_SLEEP_1 87 &PERF_CLUSTER_SLEEP_2>; 88 capacity-dmips-mhz = <1126>; 89 #cooling-cells = <2>; 90 next-level-cache = <&L2_1>; 91 }; 92 93 CPU3: cpu@103 { 94 device_type = "cpu"; 95 compatible = "arm,cortex-a53"; 96 reg = <0x0 0x103>; 97 enable-method = "psci"; 98 cpu-idle-states = <&PERF_CPU_SLEEP_0 99 &PERF_CPU_SLEEP_1 100 &PERF_CLUSTER_SLEEP_0 101 &PERF_CLUSTER_SLEEP_1 102 &PERF_CLUSTER_SLEEP_2>; 103 capacity-dmips-mhz = <1126>; 104 #cooling-cells = <2>; 105 next-level-cache = <&L2_1>; 106 }; 107 108 CPU4: cpu@0 { 109 device_type = "cpu"; 110 compatible = "arm,cortex-a53"; 111 reg = <0x0 0x0>; 112 enable-method = "psci"; 113 cpu-idle-states = <&PWR_CPU_SLEEP_0 114 &PWR_CPU_SLEEP_1 115 &PWR_CLUSTER_SLEEP_0 116 &PWR_CLUSTER_SLEEP_1 117 &PWR_CLUSTER_SLEEP_2>; 118 capacity-dmips-mhz = <1024>; 119 #cooling-cells = <2>; 120 next-level-cache = <&L2_0>; 121 L2_0: l2-cache { 122 compatible = "cache"; 123 cache-level = <2>; 124 }; 125 }; 126 127 CPU5: cpu@1 { 128 device_type = "cpu"; 129 compatible = "arm,cortex-a53"; 130 reg = <0x0 0x1>; 131 enable-method = "psci"; 132 cpu-idle-states = <&PWR_CPU_SLEEP_0 133 &PWR_CPU_SLEEP_1 134 &PWR_CLUSTER_SLEEP_0 135 &PWR_CLUSTER_SLEEP_1 136 &PWR_CLUSTER_SLEEP_2>; 137 capacity-dmips-mhz = <1024>; 138 #cooling-cells = <2>; 139 next-level-cache = <&L2_0>; 140 }; 141 142 CPU6: cpu@2 { 143 device_type = "cpu"; 144 compatible = "arm,cortex-a53"; 145 reg = <0x0 0x2>; 146 enable-method = "psci"; 147 cpu-idle-states = <&PWR_CPU_SLEEP_0 148 &PWR_CPU_SLEEP_1 149 &PWR_CLUSTER_SLEEP_0 150 &PWR_CLUSTER_SLEEP_1 151 &PWR_CLUSTER_SLEEP_2>; 152 capacity-dmips-mhz = <1024>; 153 #cooling-cells = <2>; 154 next-level-cache = <&L2_0>; 155 }; 156 157 CPU7: cpu@3 { 158 device_type = "cpu"; 159 compatible = "arm,cortex-a53"; 160 reg = <0x0 0x3>; 161 enable-method = "psci"; 162 cpu-idle-states = <&PWR_CPU_SLEEP_0 163 &PWR_CPU_SLEEP_1 164 &PWR_CLUSTER_SLEEP_0 165 &PWR_CLUSTER_SLEEP_1 166 &PWR_CLUSTER_SLEEP_2>; 167 capacity-dmips-mhz = <1024>; 168 #cooling-cells = <2>; 169 next-level-cache = <&L2_0>; 170 }; 171 172 cpu-map { 173 cluster0 { 174 core0 { 175 cpu = <&CPU4>; 176 }; 177 178 core1 { 179 cpu = <&CPU5>; 180 }; 181 182 core2 { 183 cpu = <&CPU6>; 184 }; 185 186 core3 { 187 cpu = <&CPU7>; 188 }; 189 }; 190 191 cluster1 { 192 core0 { 193 cpu = <&CPU0>; 194 }; 195 196 core1 { 197 cpu = <&CPU1>; 198 }; 199 200 core2 { 201 cpu = <&CPU2>; 202 }; 203 204 core3 { 205 cpu = <&CPU3>; 206 }; 207 }; 208 }; 209 210 idle-states { 211 entry-method = "psci"; 212 213 PWR_CPU_SLEEP_0: cpu-sleep-0-0 { 214 compatible = "arm,idle-state"; 215 idle-state-name = "pwr-retention"; 216 arm,psci-suspend-param = <0x40000002>; 217 entry-latency-us = <338>; 218 exit-latency-us = <423>; 219 min-residency-us = <200>; 220 }; 221 222 PWR_CPU_SLEEP_1: cpu-sleep-0-1 { 223 compatible = "arm,idle-state"; 224 idle-state-name = "pwr-power-collapse"; 225 arm,psci-suspend-param = <0x40000003>; 226 entry-latency-us = <515>; 227 exit-latency-us = <1821>; 228 min-residency-us = <1000>; 229 local-timer-stop; 230 }; 231 232 PERF_CPU_SLEEP_0: cpu-sleep-1-0 { 233 compatible = "arm,idle-state"; 234 idle-state-name = "perf-retention"; 235 arm,psci-suspend-param = <0x40000002>; 236 entry-latency-us = <154>; 237 exit-latency-us = <87>; 238 min-residency-us = <200>; 239 }; 240 241 PERF_CPU_SLEEP_1: cpu-sleep-1-1 { 242 compatible = "arm,idle-state"; 243 idle-state-name = "perf-power-collapse"; 244 arm,psci-suspend-param = <0x40000003>; 245 entry-latency-us = <262>; 246 exit-latency-us = <301>; 247 min-residency-us = <1000>; 248 local-timer-stop; 249 }; 250 251 PWR_CLUSTER_SLEEP_0: cluster-sleep-0-0 { 252 compatible = "arm,idle-state"; 253 idle-state-name = "pwr-cluster-dynamic-retention"; 254 arm,psci-suspend-param = <0x400000F2>; 255 entry-latency-us = <284>; 256 exit-latency-us = <384>; 257 min-residency-us = <9987>; 258 local-timer-stop; 259 }; 260 261 PWR_CLUSTER_SLEEP_1: cluster-sleep-0-1 { 262 compatible = "arm,idle-state"; 263 idle-state-name = "pwr-cluster-retention"; 264 arm,psci-suspend-param = <0x400000F3>; 265 entry-latency-us = <338>; 266 exit-latency-us = <423>; 267 min-residency-us = <9987>; 268 local-timer-stop; 269 }; 270 271 PWR_CLUSTER_SLEEP_2: cluster-sleep-0-2 { 272 compatible = "arm,idle-state"; 273 idle-state-name = "pwr-cluster-retention"; 274 arm,psci-suspend-param = <0x400000F4>; 275 entry-latency-us = <515>; 276 exit-latency-us = <1821>; 277 min-residency-us = <9987>; 278 local-timer-stop; 279 }; 280 281 PERF_CLUSTER_SLEEP_0: cluster-sleep-1-0 { 282 compatible = "arm,idle-state"; 283 idle-state-name = "perf-cluster-dynamic-retention"; 284 arm,psci-suspend-param = <0x400000F2>; 285 entry-latency-us = <272>; 286 exit-latency-us = <329>; 287 min-residency-us = <9987>; 288 local-timer-stop; 289 }; 290 291 PERF_CLUSTER_SLEEP_1: cluster-sleep-1-1 { 292 compatible = "arm,idle-state"; 293 idle-state-name = "perf-cluster-retention"; 294 arm,psci-suspend-param = <0x400000F3>; 295 entry-latency-us = <332>; 296 exit-latency-us = <368>; 297 min-residency-us = <9987>; 298 local-timer-stop; 299 }; 300 301 PERF_CLUSTER_SLEEP_2: cluster-sleep-1-2 { 302 compatible = "arm,idle-state"; 303 idle-state-name = "perf-cluster-retention"; 304 arm,psci-suspend-param = <0x400000F4>; 305 entry-latency-us = <545>; 306 exit-latency-us = <1609>; 307 min-residency-us = <9987>; 308 local-timer-stop; 309 }; 310 }; 311 }; 312 313 firmware { 314 scm { 315 compatible = "qcom,scm-msm8998", "qcom,scm"; 316 }; 317 }; 318 319 memory@80000000 { 320 device_type = "memory"; 321 /* We expect the bootloader to fill in the reg */ 322 reg = <0x0 0x80000000 0x0 0x0>; 323 }; 324 325 pmu { 326 compatible = "arm,armv8-pmuv3"; 327 interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>; 328 }; 329 330 psci { 331 compatible = "arm,psci-1.0"; 332 method = "smc"; 333 }; 334 335 reserved-memory { 336 #address-cells = <2>; 337 #size-cells = <2>; 338 ranges; 339 340 wlan_msa_guard: wlan-msa-guard@85600000 { 341 reg = <0x0 0x85600000 0x0 0x100000>; 342 no-map; 343 }; 344 345 wlan_msa_mem: wlan-msa-mem@85700000 { 346 reg = <0x0 0x85700000 0x0 0x100000>; 347 no-map; 348 }; 349 350 qhee_code: qhee-code@85800000 { 351 reg = <0x0 0x85800000 0x0 0x600000>; 352 no-map; 353 }; 354 355 rmtfs_mem: memory@85e00000 { 356 compatible = "qcom,rmtfs-mem"; 357 reg = <0x0 0x85e00000 0x0 0x200000>; 358 no-map; 359 360 qcom,client-id = <1>; 361 qcom,vmid = <15>; 362 }; 363 364 smem_region: smem-mem@86000000 { 365 reg = <0 0x86000000 0 0x200000>; 366 no-map; 367 }; 368 369 tz_mem: memory@86200000 { 370 reg = <0x0 0x86200000 0x0 0x3300000>; 371 no-map; 372 }; 373 374 mpss_region: mpss@8ac00000 { 375 reg = <0x0 0x8ac00000 0x0 0x7e00000>; 376 no-map; 377 }; 378 379 adsp_region: adsp@92a00000 { 380 reg = <0x0 0x92a00000 0x0 0x1e00000>; 381 no-map; 382 }; 383 384 mba_region: mba@94800000 { 385 reg = <0x0 0x94800000 0x0 0x200000>; 386 no-map; 387 }; 388 389 buffer_mem: tzbuffer@94a00000 { 390 reg = <0x0 0x94a00000 0x0 0x100000>; 391 no-map; 392 }; 393 394 venus_region: venus@9f800000 { 395 reg = <0x0 0x9f800000 0x0 0x800000>; 396 no-map; 397 }; 398 399 adsp_mem: adsp-region@f6000000 { 400 reg = <0x0 0xf6000000 0x0 0x800000>; 401 no-map; 402 }; 403 404 qseecom_mem: qseecom-region@f6800000 { 405 reg = <0x0 0xf6800000 0x0 0x1400000>; 406 no-map; 407 }; 408 409 zap_shader_region: gpu@fed00000 { 410 compatible = "shared-dma-pool"; 411 reg = <0x0 0xfed00000 0x0 0xa00000>; 412 no-map; 413 }; 414 }; 415 416 rpm-glink { 417 compatible = "qcom,glink-rpm"; 418 419 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 420 qcom,rpm-msg-ram = <&rpm_msg_ram>; 421 mboxes = <&apcs_glb 0>; 422 423 rpm_requests: rpm-requests { 424 compatible = "qcom,rpm-sdm660"; 425 qcom,glink-channels = "rpm_requests"; 426 427 rpmcc: clock-controller { 428 compatible = "qcom,rpmcc-sdm660", "qcom,rpmcc"; 429 #clock-cells = <1>; 430 }; 431 432 rpmpd: power-controller { 433 compatible = "qcom,sdm660-rpmpd"; 434 #power-domain-cells = <1>; 435 operating-points-v2 = <&rpmpd_opp_table>; 436 437 rpmpd_opp_table: opp-table { 438 compatible = "operating-points-v2"; 439 440 rpmpd_opp_ret: opp1 { 441 opp-level = <RPM_SMD_LEVEL_RETENTION>; 442 }; 443 444 rpmpd_opp_ret_plus: opp2 { 445 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>; 446 }; 447 448 rpmpd_opp_min_svs: opp3 { 449 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 450 }; 451 452 rpmpd_opp_low_svs: opp4 { 453 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 454 }; 455 456 rpmpd_opp_svs: opp5 { 457 opp-level = <RPM_SMD_LEVEL_SVS>; 458 }; 459 460 rpmpd_opp_svs_plus: opp6 { 461 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 462 }; 463 464 rpmpd_opp_nom: opp7 { 465 opp-level = <RPM_SMD_LEVEL_NOM>; 466 }; 467 468 rpmpd_opp_nom_plus: opp8 { 469 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 470 }; 471 472 rpmpd_opp_turbo: opp9 { 473 opp-level = <RPM_SMD_LEVEL_TURBO>; 474 }; 475 }; 476 }; 477 }; 478 }; 479 480 smem: smem { 481 compatible = "qcom,smem"; 482 memory-region = <&smem_region>; 483 hwlocks = <&tcsr_mutex 3>; 484 }; 485 486 smp2p-adsp { 487 compatible = "qcom,smp2p"; 488 qcom,smem = <443>, <429>; 489 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 490 mboxes = <&apcs_glb 10>; 491 qcom,local-pid = <0>; 492 qcom,remote-pid = <2>; 493 494 adsp_smp2p_out: master-kernel { 495 qcom,entry-name = "master-kernel"; 496 #qcom,smem-state-cells = <1>; 497 }; 498 499 adsp_smp2p_in: slave-kernel { 500 qcom,entry-name = "slave-kernel"; 501 interrupt-controller; 502 #interrupt-cells = <2>; 503 }; 504 }; 505 506 smp2p-mpss { 507 compatible = "qcom,smp2p"; 508 qcom,smem = <435>, <428>; 509 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 510 mboxes = <&apcs_glb 14>; 511 qcom,local-pid = <0>; 512 qcom,remote-pid = <1>; 513 514 modem_smp2p_out: master-kernel { 515 qcom,entry-name = "master-kernel"; 516 #qcom,smem-state-cells = <1>; 517 }; 518 519 modem_smp2p_in: slave-kernel { 520 qcom,entry-name = "slave-kernel"; 521 interrupt-controller; 522 #interrupt-cells = <2>; 523 }; 524 }; 525 526 soc { 527 #address-cells = <1>; 528 #size-cells = <1>; 529 ranges = <0 0 0 0xffffffff>; 530 compatible = "simple-bus"; 531 532 gcc: clock-controller@100000 { 533 compatible = "qcom,gcc-sdm630"; 534 #clock-cells = <1>; 535 #reset-cells = <1>; 536 #power-domain-cells = <1>; 537 reg = <0x00100000 0x94000>; 538 539 clock-names = "xo", "sleep_clk"; 540 clocks = <&xo_board>, 541 <&sleep_clk>; 542 }; 543 544 rpm_msg_ram: memory@778000 { 545 compatible = "qcom,rpm-msg-ram"; 546 reg = <0x00778000 0x7000>; 547 }; 548 549 qfprom: qfprom@780000 { 550 compatible = "qcom,qfprom"; 551 reg = <0x00780000 0x621c>; 552 #address-cells = <1>; 553 #size-cells = <1>; 554 555 qusb2_hstx_trim: hstx-trim@240 { 556 reg = <0x240 0x1>; 557 bits = <25 3>; 558 }; 559 560 gpu_speed_bin: gpu-speed-bin@41a0 { 561 reg = <0x41a0 0x1>; 562 bits = <21 7>; 563 }; 564 }; 565 566 rng: rng@793000 { 567 compatible = "qcom,prng-ee"; 568 reg = <0x00793000 0x1000>; 569 clocks = <&gcc GCC_PRNG_AHB_CLK>; 570 clock-names = "core"; 571 }; 572 573 bimc: interconnect@1008000 { 574 compatible = "qcom,sdm660-bimc"; 575 reg = <0x01008000 0x78000>; 576 #interconnect-cells = <1>; 577 clock-names = "bus", "bus_a"; 578 clocks = <&rpmcc RPM_SMD_BIMC_CLK>, 579 <&rpmcc RPM_SMD_BIMC_A_CLK>; 580 }; 581 582 restart@10ac000 { 583 compatible = "qcom,pshold"; 584 reg = <0x010ac000 0x4>; 585 }; 586 587 cnoc: interconnect@1500000 { 588 compatible = "qcom,sdm660-cnoc"; 589 reg = <0x01500000 0x10000>; 590 #interconnect-cells = <1>; 591 clock-names = "bus", "bus_a"; 592 clocks = <&rpmcc RPM_SMD_CNOC_CLK>, 593 <&rpmcc RPM_SMD_CNOC_A_CLK>; 594 }; 595 596 snoc: interconnect@1626000 { 597 compatible = "qcom,sdm660-snoc"; 598 reg = <0x01626000 0x7090>; 599 #interconnect-cells = <1>; 600 clock-names = "bus", "bus_a"; 601 clocks = <&rpmcc RPM_SMD_SNOC_CLK>, 602 <&rpmcc RPM_SMD_SNOC_A_CLK>; 603 }; 604 605 anoc2_smmu: iommu@16c0000 { 606 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2"; 607 reg = <0x016c0000 0x40000>; 608 609 assigned-clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>; 610 assigned-clock-rates = <1000>; 611 clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>; 612 clock-names = "bus"; 613 #global-interrupts = <2>; 614 #iommu-cells = <1>; 615 616 interrupts = 617 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 618 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 619 620 <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>, 621 <GIC_SPI 374 IRQ_TYPE_LEVEL_LOW>, 622 <GIC_SPI 375 IRQ_TYPE_LEVEL_LOW>, 623 <GIC_SPI 376 IRQ_TYPE_LEVEL_LOW>, 624 <GIC_SPI 377 IRQ_TYPE_LEVEL_LOW>, 625 <GIC_SPI 378 IRQ_TYPE_LEVEL_LOW>, 626 <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>, 627 <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>, 628 <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>, 629 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>, 630 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>, 631 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>, 632 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>, 633 <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, 634 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>, 635 <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>, 636 <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>, 637 <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, 638 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, 639 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, 640 <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>, 641 <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>, 642 <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, 643 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>, 644 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>, 645 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>, 646 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, 647 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, 648 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>; 649 650 status = "disabled"; 651 }; 652 653 a2noc: interconnect@1704000 { 654 compatible = "qcom,sdm660-a2noc"; 655 reg = <0x01704000 0xc100>; 656 #interconnect-cells = <1>; 657 clock-names = "bus", 658 "bus_a", 659 "ipa", 660 "ufs_axi", 661 "aggre2_ufs_axi", 662 "aggre2_usb3_axi", 663 "cfg_noc_usb2_axi"; 664 clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>, 665 <&rpmcc RPM_SMD_AGGR2_NOC_A_CLK>, 666 <&rpmcc RPM_SMD_IPA_CLK>, 667 <&gcc GCC_UFS_AXI_CLK>, 668 <&gcc GCC_AGGRE2_UFS_AXI_CLK>, 669 <&gcc GCC_AGGRE2_USB3_AXI_CLK>, 670 <&gcc GCC_CFG_NOC_USB2_AXI_CLK>; 671 }; 672 673 mnoc: interconnect@1745000 { 674 compatible = "qcom,sdm660-mnoc"; 675 reg = <0x01745000 0xA010>; 676 #interconnect-cells = <1>; 677 clock-names = "bus", "bus_a", "iface"; 678 clocks = <&rpmcc RPM_SMD_MMSSNOC_AXI_CLK>, 679 <&rpmcc RPM_SMD_MMSSNOC_AXI_CLK_A>, 680 <&mmcc AHB_CLK_SRC>; 681 }; 682 683 tsens: thermal-sensor@10ae000 { 684 compatible = "qcom,sdm630-tsens", "qcom,tsens-v2"; 685 reg = <0x010ae000 0x1000>, /* TM */ 686 <0x010ad000 0x1000>; /* SROT */ 687 #qcom,sensors = <12>; 688 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 689 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>; 690 interrupt-names = "uplow", "critical"; 691 #thermal-sensor-cells = <1>; 692 }; 693 694 tcsr_mutex_regs: syscon@1f40000 { 695 compatible = "syscon"; 696 reg = <0x01f40000 0x40000>; 697 }; 698 699 tlmm: pinctrl@3100000 { 700 compatible = "qcom,sdm630-pinctrl"; 701 reg = <0x03100000 0x400000>, 702 <0x03500000 0x400000>, 703 <0x03900000 0x400000>; 704 reg-names = "south", "center", "north"; 705 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 706 gpio-controller; 707 gpio-ranges = <&tlmm 0 0 114>; 708 #gpio-cells = <2>; 709 interrupt-controller; 710 #interrupt-cells = <2>; 711 712 blsp1_uart1_default: blsp1-uart1-default { 713 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 714 drive-strength = <2>; 715 bias-disable; 716 }; 717 718 blsp1_uart1_sleep: blsp1-uart1-sleep { 719 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 720 drive-strength = <2>; 721 bias-disable; 722 }; 723 724 blsp1_uart2_default: blsp1-uart2-default { 725 pins = "gpio4", "gpio5"; 726 drive-strength = <2>; 727 bias-disable; 728 }; 729 730 blsp2_uart1_default: blsp2-uart1-active { 731 tx-rts { 732 pins = "gpio16", "gpio19"; 733 function = "blsp_uart5"; 734 drive-strength = <2>; 735 bias-disable; 736 }; 737 738 rx { 739 /* 740 * Avoid garbage data while BT module 741 * is powered off or not driving signal 742 */ 743 pins = "gpio17"; 744 function = "blsp_uart5"; 745 drive-strength = <2>; 746 bias-pull-up; 747 }; 748 749 cts { 750 /* Match the pull of the BT module */ 751 pins = "gpio18"; 752 function = "blsp_uart5"; 753 drive-strength = <2>; 754 bias-pull-down; 755 }; 756 }; 757 758 blsp2_uart1_sleep: blsp2-uart1-sleep { 759 tx { 760 pins = "gpio16"; 761 function = "gpio"; 762 drive-strength = <2>; 763 bias-pull-up; 764 }; 765 766 rx-cts-rts { 767 pins = "gpio17", "gpio18", "gpio19"; 768 function = "gpio"; 769 drive-strength = <2>; 770 bias-no-pull; 771 }; 772 }; 773 774 i2c1_default: i2c1-default { 775 pins = "gpio2", "gpio3"; 776 function = "blsp_i2c1"; 777 drive-strength = <2>; 778 bias-disable; 779 }; 780 781 i2c1_sleep: i2c1-sleep { 782 pins = "gpio2", "gpio3"; 783 function = "blsp_i2c1"; 784 drive-strength = <2>; 785 bias-pull-up; 786 }; 787 788 i2c2_default: i2c2-default { 789 pins = "gpio6", "gpio7"; 790 function = "blsp_i2c2"; 791 drive-strength = <2>; 792 bias-disable; 793 }; 794 795 i2c2_sleep: i2c2-sleep { 796 pins = "gpio6", "gpio7"; 797 function = "blsp_i2c2"; 798 drive-strength = <2>; 799 bias-pull-up; 800 }; 801 802 i2c3_default: i2c3-default { 803 pins = "gpio10", "gpio11"; 804 function = "blsp_i2c3"; 805 drive-strength = <2>; 806 bias-disable; 807 }; 808 809 i2c3_sleep: i2c3-sleep { 810 pins = "gpio10", "gpio11"; 811 function = "blsp_i2c3"; 812 drive-strength = <2>; 813 bias-pull-up; 814 }; 815 816 i2c4_default: i2c4-default { 817 pins = "gpio14", "gpio15"; 818 function = "blsp_i2c4"; 819 drive-strength = <2>; 820 bias-disable; 821 }; 822 823 i2c4_sleep: i2c4-sleep { 824 pins = "gpio14", "gpio15"; 825 function = "blsp_i2c4"; 826 drive-strength = <2>; 827 bias-pull-up; 828 }; 829 830 i2c5_default: i2c5-default { 831 pins = "gpio18", "gpio19"; 832 function = "blsp_i2c5"; 833 drive-strength = <2>; 834 bias-disable; 835 }; 836 837 i2c5_sleep: i2c5-sleep { 838 pins = "gpio18", "gpio19"; 839 function = "blsp_i2c5"; 840 drive-strength = <2>; 841 bias-pull-up; 842 }; 843 844 i2c6_default: i2c6-default { 845 pins = "gpio22", "gpio23"; 846 function = "blsp_i2c6"; 847 drive-strength = <2>; 848 bias-disable; 849 }; 850 851 i2c6_sleep: i2c6-sleep { 852 pins = "gpio22", "gpio23"; 853 function = "blsp_i2c6"; 854 drive-strength = <2>; 855 bias-pull-up; 856 }; 857 858 i2c7_default: i2c7-default { 859 pins = "gpio26", "gpio27"; 860 function = "blsp_i2c7"; 861 drive-strength = <2>; 862 bias-disable; 863 }; 864 865 i2c7_sleep: i2c7-sleep { 866 pins = "gpio26", "gpio27"; 867 function = "blsp_i2c7"; 868 drive-strength = <2>; 869 bias-pull-up; 870 }; 871 872 i2c8_default: i2c8-default { 873 pins = "gpio30", "gpio31"; 874 function = "blsp_i2c8"; 875 drive-strength = <2>; 876 bias-disable; 877 }; 878 879 i2c8_sleep: i2c8-sleep { 880 pins = "gpio30", "gpio31"; 881 function = "blsp_i2c8"; 882 drive-strength = <2>; 883 bias-pull-up; 884 }; 885 886 cci0_default: cci0_default { 887 pinmux { 888 pins = "gpio36","gpio37"; 889 function = "cci_i2c"; 890 }; 891 892 pinconf { 893 pins = "gpio36","gpio37"; 894 bias-pull-up; 895 drive-strength = <2>; 896 }; 897 }; 898 899 cci1_default: cci1_default { 900 pinmux { 901 pins = "gpio38","gpio39"; 902 function = "cci_i2c"; 903 }; 904 905 pinconf { 906 pins = "gpio38","gpio39"; 907 bias-pull-up; 908 drive-strength = <2>; 909 }; 910 }; 911 912 sdc1_state_on: sdc1-on { 913 clk { 914 pins = "sdc1_clk"; 915 bias-disable; 916 drive-strength = <16>; 917 }; 918 919 cmd { 920 pins = "sdc1_cmd"; 921 bias-pull-up; 922 drive-strength = <10>; 923 }; 924 925 data { 926 pins = "sdc1_data"; 927 bias-pull-up; 928 drive-strength = <10>; 929 }; 930 931 rclk { 932 pins = "sdc1_rclk"; 933 bias-pull-down; 934 }; 935 }; 936 937 sdc1_state_off: sdc1-off { 938 clk { 939 pins = "sdc1_clk"; 940 bias-disable; 941 drive-strength = <2>; 942 }; 943 944 cmd { 945 pins = "sdc1_cmd"; 946 bias-pull-up; 947 drive-strength = <2>; 948 }; 949 950 data { 951 pins = "sdc1_data"; 952 bias-pull-up; 953 drive-strength = <2>; 954 }; 955 956 rclk { 957 pins = "sdc1_rclk"; 958 bias-pull-down; 959 }; 960 }; 961 962 sdc2_state_on: sdc2-on { 963 clk { 964 pins = "sdc2_clk"; 965 bias-disable; 966 drive-strength = <16>; 967 }; 968 969 cmd { 970 pins = "sdc2_cmd"; 971 bias-pull-up; 972 drive-strength = <10>; 973 }; 974 975 data { 976 pins = "sdc2_data"; 977 bias-pull-up; 978 drive-strength = <10>; 979 }; 980 981 sd-cd { 982 pins = "gpio54"; 983 bias-pull-up; 984 drive-strength = <2>; 985 }; 986 }; 987 988 sdc2_state_off: sdc2-off { 989 clk { 990 pins = "sdc2_clk"; 991 bias-disable; 992 drive-strength = <2>; 993 }; 994 995 cmd { 996 pins = "sdc2_cmd"; 997 bias-pull-up; 998 drive-strength = <2>; 999 }; 1000 1001 data { 1002 pins = "sdc2_data"; 1003 bias-pull-up; 1004 drive-strength = <2>; 1005 }; 1006 1007 sd-cd { 1008 pins = "gpio54"; 1009 bias-disable; 1010 drive-strength = <2>; 1011 }; 1012 }; 1013 }; 1014 1015 adreno_gpu: gpu@5000000 { 1016 compatible = "qcom,adreno-508.0", "qcom,adreno"; 1017 #stream-id-cells = <16>; 1018 1019 reg = <0x05000000 0x40000>; 1020 reg-names = "kgsl_3d0_reg_memory"; 1021 1022 interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>; 1023 1024 clocks = <&gcc GCC_GPU_CFG_AHB_CLK>, 1025 <&gpucc GPUCC_RBBMTIMER_CLK>, 1026 <&gcc GCC_BIMC_GFX_CLK>, 1027 <&gcc GCC_GPU_BIMC_GFX_CLK>, 1028 <&gpucc GPUCC_RBCPR_CLK>, 1029 <&gpucc GPUCC_GFX3D_CLK>; 1030 1031 clock-names = "iface", 1032 "rbbmtimer", 1033 "mem", 1034 "mem_iface", 1035 "rbcpr", 1036 "core"; 1037 1038 power-domains = <&rpmpd SDM660_VDDMX>; 1039 iommus = <&kgsl_smmu 0>; 1040 1041 nvmem-cells = <&gpu_speed_bin>; 1042 nvmem-cell-names = "speed_bin"; 1043 1044 interconnects = <&gnoc 1 &bimc 5>; 1045 interconnect-names = "gfx-mem"; 1046 1047 operating-points-v2 = <&gpu_sdm630_opp_table>; 1048 1049 gpu_sdm630_opp_table: opp-table { 1050 compatible = "operating-points-v2"; 1051 opp-775000000 { 1052 opp-hz = /bits/ 64 <775000000>; 1053 opp-level = <RPM_SMD_LEVEL_TURBO>; 1054 opp-peak-kBps = <5412000>; 1055 opp-supported-hw = <0xA2>; 1056 }; 1057 opp-647000000 { 1058 opp-hz = /bits/ 64 <647000000>; 1059 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 1060 opp-peak-kBps = <4068000>; 1061 opp-supported-hw = <0xFF>; 1062 }; 1063 opp-588000000 { 1064 opp-hz = /bits/ 64 <588000000>; 1065 opp-level = <RPM_SMD_LEVEL_NOM>; 1066 opp-peak-kBps = <3072000>; 1067 opp-supported-hw = <0xFF>; 1068 }; 1069 opp-465000000 { 1070 opp-hz = /bits/ 64 <465000000>; 1071 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 1072 opp-peak-kBps = <2724000>; 1073 opp-supported-hw = <0xFF>; 1074 }; 1075 opp-370000000 { 1076 opp-hz = /bits/ 64 <370000000>; 1077 opp-level = <RPM_SMD_LEVEL_SVS>; 1078 opp-peak-kBps = <2188000>; 1079 opp-supported-hw = <0xFF>; 1080 }; 1081 opp-240000000 { 1082 opp-hz = /bits/ 64 <240000000>; 1083 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 1084 opp-peak-kBps = <1648000>; 1085 opp-supported-hw = <0xFF>; 1086 }; 1087 opp-160000000 { 1088 opp-hz = /bits/ 64 <160000000>; 1089 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 1090 opp-peak-kBps = <1200000>; 1091 opp-supported-hw = <0xFF>; 1092 }; 1093 }; 1094 }; 1095 1096 kgsl_smmu: iommu@5040000 { 1097 compatible = "qcom,sdm630-smmu-v2", 1098 "qcom,adreno-smmu", "qcom,smmu-v2"; 1099 reg = <0x05040000 0x10000>; 1100 1101 /* 1102 * GX GDSC parent is CX. We need to bring up CX for SMMU 1103 * but we need both up for Adreno. On the other hand, we 1104 * need to manage the GX rpmpd domain in the adreno driver. 1105 * Enable CX/GX GDSCs here so that we can manage just the GX 1106 * RPM Power Domain in the Adreno driver. 1107 */ 1108 power-domains = <&gpucc GPU_GX_GDSC>; 1109 clocks = <&gcc GCC_GPU_CFG_AHB_CLK>, 1110 <&gcc GCC_BIMC_GFX_CLK>, 1111 <&gcc GCC_GPU_BIMC_GFX_CLK>; 1112 clock-names = "iface", "mem", "mem_iface"; 1113 #global-interrupts = <2>; 1114 #iommu-cells = <1>; 1115 1116 interrupts = 1117 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 1118 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 1119 1120 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 1121 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 1122 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 1123 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 1124 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1125 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1126 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>, 1127 <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>; 1128 1129 status = "disabled"; 1130 }; 1131 1132 gpucc: clock-controller@5065000 { 1133 compatible = "qcom,gpucc-sdm630"; 1134 #clock-cells = <1>; 1135 #reset-cells = <1>; 1136 #power-domain-cells = <1>; 1137 reg = <0x05065000 0x9038>; 1138 1139 clocks = <&xo_board>, 1140 <&gcc GCC_GPU_GPLL0_CLK>, 1141 <&gcc GCC_GPU_GPLL0_DIV_CLK>; 1142 clock-names = "xo", 1143 "gcc_gpu_gpll0_clk", 1144 "gcc_gpu_gpll0_div_clk"; 1145 status = "disabled"; 1146 }; 1147 1148 lpass_smmu: iommu@5100000 { 1149 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2"; 1150 reg = <0x05100000 0x40000>; 1151 #iommu-cells = <1>; 1152 1153 #global-interrupts = <2>; 1154 interrupts = 1155 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 1156 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 1157 1158 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, 1159 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>, 1160 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>, 1161 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 1162 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 1163 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 1164 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 1165 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 1166 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 1167 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 1168 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 1169 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 1170 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 1171 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, 1172 <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>, 1173 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 1174 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>; 1175 1176 status = "disabled"; 1177 }; 1178 1179 spmi_bus: spmi@800f000 { 1180 compatible = "qcom,spmi-pmic-arb"; 1181 reg = <0x0800f000 0x1000>, 1182 <0x08400000 0x1000000>, 1183 <0x09400000 0x1000000>, 1184 <0x0a400000 0x220000>, 1185 <0x0800a000 0x3000>; 1186 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1187 interrupt-names = "periph_irq"; 1188 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>; 1189 qcom,ee = <0>; 1190 qcom,channel = <0>; 1191 #address-cells = <2>; 1192 #size-cells = <0>; 1193 interrupt-controller; 1194 #interrupt-cells = <4>; 1195 cell-index = <0>; 1196 }; 1197 1198 usb3: usb@a8f8800 { 1199 compatible = "qcom,sdm660-dwc3", "qcom,dwc3"; 1200 reg = <0x0a8f8800 0x400>; 1201 status = "disabled"; 1202 #address-cells = <1>; 1203 #size-cells = <1>; 1204 ranges; 1205 1206 clocks = <&gcc GCC_CFG_NOC_USB3_AXI_CLK>, 1207 <&gcc GCC_USB30_MASTER_CLK>, 1208 <&gcc GCC_AGGRE2_USB3_AXI_CLK>, 1209 <&rpmcc RPM_SMD_AGGR2_NOC_CLK>, 1210 <&gcc GCC_USB30_MOCK_UTMI_CLK>, 1211 <&gcc GCC_USB30_SLEEP_CLK>; 1212 clock-names = "cfg_noc", "core", "iface", "bus", 1213 "mock_utmi", "sleep"; 1214 1215 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, 1216 <&gcc GCC_USB30_MASTER_CLK>, 1217 <&rpmcc RPM_SMD_AGGR2_NOC_CLK>; 1218 assigned-clock-rates = <19200000>, <120000000>, 1219 <19200000>; 1220 1221 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, 1222 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 1223 interrupt-names = "hs_phy_irq", "ss_phy_irq"; 1224 1225 power-domains = <&gcc USB_30_GDSC>; 1226 qcom,select-utmi-as-pipe-clk; 1227 1228 resets = <&gcc GCC_USB_30_BCR>; 1229 1230 usb3_dwc3: usb@a800000 { 1231 compatible = "snps,dwc3"; 1232 reg = <0x0a800000 0xc8d0>; 1233 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 1234 snps,dis_u2_susphy_quirk; 1235 snps,dis_enblslpm_quirk; 1236 1237 /* 1238 * SDM630 technically supports USB3 but I 1239 * haven't seen any devices making use of it. 1240 */ 1241 maximum-speed = "high-speed"; 1242 phys = <&qusb2phy>; 1243 phy-names = "usb2-phy"; 1244 snps,hird-threshold = /bits/ 8 <0>; 1245 }; 1246 }; 1247 1248 qusb2phy: phy@c012000 { 1249 compatible = "qcom,sdm660-qusb2-phy"; 1250 reg = <0x0c012000 0x180>; 1251 #phy-cells = <0>; 1252 1253 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 1254 <&gcc GCC_RX1_USB2_CLKREF_CLK>; 1255 clock-names = "cfg_ahb", "ref"; 1256 1257 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 1258 nvmem-cells = <&qusb2_hstx_trim>; 1259 status = "disabled"; 1260 }; 1261 1262 sdhc_2: sdhci@c084000 { 1263 compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5"; 1264 reg = <0x0c084000 0x1000>; 1265 reg-names = "hc"; 1266 1267 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1268 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 1269 interrupt-names = "hc_irq", "pwr_irq"; 1270 1271 bus-width = <4>; 1272 clocks = <&gcc GCC_SDCC2_APPS_CLK>, 1273 <&gcc GCC_SDCC2_AHB_CLK>, 1274 <&xo_board>; 1275 clock-names = "core", "iface", "xo"; 1276 1277 interconnects = <&a2noc 3 &a2noc 10>, 1278 <&gnoc 0 &cnoc 28>; 1279 operating-points-v2 = <&sdhc2_opp_table>; 1280 1281 pinctrl-names = "default", "sleep"; 1282 pinctrl-0 = <&sdc2_state_on>; 1283 pinctrl-1 = <&sdc2_state_off>; 1284 power-domains = <&rpmpd SDM660_VDDCX>; 1285 1286 status = "disabled"; 1287 1288 sdhc2_opp_table: opp-table { 1289 compatible = "operating-points-v2"; 1290 1291 opp-50000000 { 1292 opp-hz = /bits/ 64 <50000000>; 1293 required-opps = <&rpmpd_opp_low_svs>; 1294 opp-peak-kBps = <200000 140000>; 1295 opp-avg-kBps = <130718 133320>; 1296 }; 1297 opp-100000000 { 1298 opp-hz = /bits/ 64 <100000000>; 1299 required-opps = <&rpmpd_opp_svs>; 1300 opp-peak-kBps = <250000 160000>; 1301 opp-avg-kBps = <196078 150000>; 1302 }; 1303 opp-200000000 { 1304 opp-hz = /bits/ 64 <200000000>; 1305 required-opps = <&rpmpd_opp_nom>; 1306 opp-peak-kBps = <4096000 4096000>; 1307 opp-avg-kBps = <1338562 1338562>; 1308 }; 1309 }; 1310 }; 1311 1312 sdhc_1: sdhci@c0c4000 { 1313 compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5"; 1314 reg = <0x0c0c4000 0x1000>, 1315 <0x0c0c5000 0x1000>, 1316 <0x0c0c8000 0x8000>; 1317 reg-names = "hc", "cqhci", "ice"; 1318 1319 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1320 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1321 interrupt-names = "hc_irq", "pwr_irq"; 1322 1323 clocks = <&gcc GCC_SDCC1_APPS_CLK>, 1324 <&gcc GCC_SDCC1_AHB_CLK>, 1325 <&xo_board>, 1326 <&gcc GCC_SDCC1_ICE_CORE_CLK>; 1327 clock-names = "core", "iface", "xo", "ice"; 1328 1329 interconnects = <&a2noc 2 &a2noc 10>, 1330 <&gnoc 0 &cnoc 27>; 1331 interconnect-names = "sdhc1-ddr", "cpu-sdhc1"; 1332 operating-points-v2 = <&sdhc1_opp_table>; 1333 pinctrl-names = "default", "sleep"; 1334 pinctrl-0 = <&sdc1_state_on>; 1335 pinctrl-1 = <&sdc1_state_off>; 1336 power-domains = <&rpmpd SDM660_VDDCX>; 1337 1338 bus-width = <8>; 1339 non-removable; 1340 1341 status = "disabled"; 1342 1343 sdhc1_opp_table: opp-table { 1344 compatible = "operating-points-v2"; 1345 1346 opp-50000000 { 1347 opp-hz = /bits/ 64 <50000000>; 1348 required-opps = <&rpmpd_opp_low_svs>; 1349 opp-peak-kBps = <200000 140000>; 1350 opp-avg-kBps = <130718 133320>; 1351 }; 1352 opp-100000000 { 1353 opp-hz = /bits/ 64 <100000000>; 1354 required-opps = <&rpmpd_opp_svs>; 1355 opp-peak-kBps = <250000 160000>; 1356 opp-avg-kBps = <196078 150000>; 1357 }; 1358 opp-384000000 { 1359 opp-hz = /bits/ 64 <384000000>; 1360 required-opps = <&rpmpd_opp_nom>; 1361 opp-peak-kBps = <4096000 4096000>; 1362 opp-avg-kBps = <1338562 1338562>; 1363 }; 1364 }; 1365 }; 1366 1367 mmcc: clock-controller@c8c0000 { 1368 compatible = "qcom,mmcc-sdm630"; 1369 reg = <0x0c8c0000 0x40000>; 1370 #clock-cells = <1>; 1371 #reset-cells = <1>; 1372 #power-domain-cells = <1>; 1373 clock-names = "xo", 1374 "sleep_clk", 1375 "gpll0", 1376 "gpll0_div", 1377 "dsi0pll", 1378 "dsi0pllbyte", 1379 "dsi1pll", 1380 "dsi1pllbyte", 1381 "dp_link_2x_clk_divsel_five", 1382 "dp_vco_divided_clk_src_mux"; 1383 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 1384 <&sleep_clk>, 1385 <&gcc GCC_MMSS_GPLL0_CLK>, 1386 <&gcc GCC_MMSS_GPLL0_DIV_CLK>, 1387 <&dsi0_phy 1>, 1388 <&dsi0_phy 0>, 1389 <0>, 1390 <0>, 1391 <0>, 1392 <0>; 1393 }; 1394 1395 dsi_opp_table: dsi-opp-table { 1396 compatible = "operating-points-v2"; 1397 1398 opp-131250000 { 1399 opp-hz = /bits/ 64 <131250000>; 1400 required-opps = <&rpmpd_opp_svs>; 1401 }; 1402 1403 opp-210000000 { 1404 opp-hz = /bits/ 64 <210000000>; 1405 required-opps = <&rpmpd_opp_svs_plus>; 1406 }; 1407 1408 opp-262500000 { 1409 opp-hz = /bits/ 64 <262500000>; 1410 required-opps = <&rpmpd_opp_nom>; 1411 }; 1412 }; 1413 1414 mdss: mdss@c900000 { 1415 compatible = "qcom,mdss"; 1416 reg = <0x0c900000 0x1000>, 1417 <0x0c9b0000 0x1040>; 1418 reg-names = "mdss_phys", "vbif_phys"; 1419 1420 power-domains = <&mmcc MDSS_GDSC>; 1421 1422 clocks = <&mmcc MDSS_AHB_CLK>, 1423 <&mmcc MDSS_AXI_CLK>, 1424 <&mmcc MDSS_VSYNC_CLK>, 1425 <&mmcc MDSS_MDP_CLK>; 1426 clock-names = "iface", 1427 "bus", 1428 "vsync", 1429 "core"; 1430 1431 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 1432 1433 interrupt-controller; 1434 #interrupt-cells = <1>; 1435 1436 #address-cells = <1>; 1437 #size-cells = <1>; 1438 ranges; 1439 status = "disabled"; 1440 1441 mdp: mdp@c901000 { 1442 compatible = "qcom,mdp5"; 1443 reg = <0x0c901000 0x89000>; 1444 reg-names = "mdp_phys"; 1445 1446 interrupt-parent = <&mdss>; 1447 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; 1448 1449 assigned-clocks = <&mmcc MDSS_MDP_CLK>, 1450 <&mmcc MDSS_VSYNC_CLK>; 1451 assigned-clock-rates = <300000000>, 1452 <19200000>; 1453 clocks = <&mmcc MDSS_AHB_CLK>, 1454 <&mmcc MDSS_AXI_CLK>, 1455 <&mmcc MDSS_MDP_CLK>, 1456 <&mmcc MDSS_VSYNC_CLK>; 1457 clock-names = "iface", 1458 "bus", 1459 "core", 1460 "vsync"; 1461 1462 interconnects = <&mnoc 2 &bimc 5>, 1463 <&mnoc 3 &bimc 5>, 1464 <&gnoc 0 &mnoc 17>; 1465 interconnect-names = "mdp0-mem", 1466 "mdp1-mem", 1467 "rotator-mem"; 1468 iommus = <&mmss_smmu 0>; 1469 operating-points-v2 = <&mdp_opp_table>; 1470 power-domains = <&rpmpd SDM660_VDDCX>; 1471 1472 ports { 1473 #address-cells = <1>; 1474 #size-cells = <0>; 1475 1476 port@0 { 1477 reg = <0>; 1478 mdp5_intf1_out: endpoint { 1479 remote-endpoint = <&dsi0_in>; 1480 }; 1481 }; 1482 }; 1483 1484 mdp_opp_table: mdp-opp { 1485 compatible = "operating-points-v2"; 1486 1487 opp-150000000 { 1488 opp-hz = /bits/ 64 <150000000>; 1489 opp-peak-kBps = <320000 320000 76800>; 1490 required-opps = <&rpmpd_opp_low_svs>; 1491 }; 1492 opp-275000000 { 1493 opp-hz = /bits/ 64 <275000000>; 1494 opp-peak-kBps = <6400000 6400000 160000>; 1495 required-opps = <&rpmpd_opp_svs>; 1496 }; 1497 opp-300000000 { 1498 opp-hz = /bits/ 64 <300000000>; 1499 opp-peak-kBps = <6400000 6400000 190000>; 1500 required-opps = <&rpmpd_opp_svs_plus>; 1501 }; 1502 opp-330000000 { 1503 opp-hz = /bits/ 64 <330000000>; 1504 opp-peak-kBps = <6400000 6400000 240000>; 1505 required-opps = <&rpmpd_opp_nom>; 1506 }; 1507 opp-412500000 { 1508 opp-hz = /bits/ 64 <412500000>; 1509 opp-peak-kBps = <6400000 6400000 320000>; 1510 required-opps = <&rpmpd_opp_turbo>; 1511 }; 1512 }; 1513 }; 1514 1515 dsi0: dsi@c994000 { 1516 compatible = "qcom,mdss-dsi-ctrl"; 1517 reg = <0x0c994000 0x400>; 1518 reg-names = "dsi_ctrl"; 1519 1520 operating-points-v2 = <&dsi_opp_table>; 1521 power-domains = <&rpmpd SDM660_VDDCX>; 1522 1523 interrupt-parent = <&mdss>; 1524 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; 1525 1526 assigned-clocks = <&mmcc BYTE0_CLK_SRC>, 1527 <&mmcc PCLK0_CLK_SRC>; 1528 assigned-clock-parents = <&dsi0_phy 0>, 1529 <&dsi0_phy 1>; 1530 1531 clocks = <&mmcc MDSS_MDP_CLK>, 1532 <&mmcc MDSS_BYTE0_CLK>, 1533 <&mmcc MDSS_BYTE0_INTF_CLK>, 1534 <&mmcc MNOC_AHB_CLK>, 1535 <&mmcc MDSS_AHB_CLK>, 1536 <&mmcc MDSS_AXI_CLK>, 1537 <&mmcc MISC_AHB_CLK>, 1538 <&mmcc MDSS_PCLK0_CLK>, 1539 <&mmcc MDSS_ESC0_CLK>; 1540 clock-names = "mdp_core", 1541 "byte", 1542 "byte_intf", 1543 "mnoc", 1544 "iface", 1545 "bus", 1546 "core_mmss", 1547 "pixel", 1548 "core"; 1549 1550 phys = <&dsi0_phy>; 1551 phy-names = "dsi"; 1552 1553 ports { 1554 #address-cells = <1>; 1555 #size-cells = <0>; 1556 1557 port@0 { 1558 reg = <0>; 1559 dsi0_in: endpoint { 1560 remote-endpoint = <&mdp5_intf1_out>; 1561 }; 1562 }; 1563 1564 port@1 { 1565 reg = <1>; 1566 dsi0_out: endpoint { 1567 }; 1568 }; 1569 }; 1570 }; 1571 1572 dsi0_phy: dsi-phy@c994400 { 1573 compatible = "qcom,dsi-phy-14nm-660"; 1574 reg = <0x0c994400 0x100>, 1575 <0x0c994500 0x300>, 1576 <0x0c994800 0x188>; 1577 reg-names = "dsi_phy", 1578 "dsi_phy_lane", 1579 "dsi_pll"; 1580 1581 #clock-cells = <1>; 1582 #phy-cells = <0>; 1583 1584 clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>; 1585 clock-names = "iface", "ref"; 1586 }; 1587 }; 1588 1589 blsp1_dma: dma-controller@c144000 { 1590 compatible = "qcom,bam-v1.7.0"; 1591 reg = <0x0c144000 0x1f000>; 1592 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 1593 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 1594 clock-names = "bam_clk"; 1595 #dma-cells = <1>; 1596 qcom,ee = <0>; 1597 qcom,controlled-remotely; 1598 num-channels = <18>; 1599 qcom,num-ees = <4>; 1600 }; 1601 1602 blsp1_uart1: serial@c16f000 { 1603 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1604 reg = <0x0c16f000 0x200>; 1605 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1606 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, 1607 <&gcc GCC_BLSP1_AHB_CLK>; 1608 clock-names = "core", "iface"; 1609 dmas = <&blsp1_dma 0>, <&blsp1_dma 1>; 1610 dma-names = "tx", "rx"; 1611 pinctrl-names = "default", "sleep"; 1612 pinctrl-0 = <&blsp1_uart1_default>; 1613 pinctrl-1 = <&blsp1_uart1_sleep>; 1614 status = "disabled"; 1615 }; 1616 1617 blsp1_uart2: serial@c170000 { 1618 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1619 reg = <0x0c170000 0x1000>; 1620 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1621 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, 1622 <&gcc GCC_BLSP1_AHB_CLK>; 1623 clock-names = "core", "iface"; 1624 dmas = <&blsp1_dma 2>, <&blsp1_dma 3>; 1625 dma-names = "tx", "rx"; 1626 pinctrl-names = "default"; 1627 pinctrl-0 = <&blsp1_uart2_default>; 1628 status = "disabled"; 1629 }; 1630 1631 blsp_i2c1: i2c@c175000 { 1632 compatible = "qcom,i2c-qup-v2.2.1"; 1633 reg = <0x0c175000 0x600>; 1634 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1635 1636 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, 1637 <&gcc GCC_BLSP1_AHB_CLK>; 1638 clock-names = "core", "iface"; 1639 clock-frequency = <400000>; 1640 dmas = <&blsp1_dma 4>, <&blsp1_dma 5>; 1641 dma-names = "tx", "rx"; 1642 1643 pinctrl-names = "default", "sleep"; 1644 pinctrl-0 = <&i2c1_default>; 1645 pinctrl-1 = <&i2c1_sleep>; 1646 #address-cells = <1>; 1647 #size-cells = <0>; 1648 status = "disabled"; 1649 }; 1650 1651 blsp_i2c2: i2c@c176000 { 1652 compatible = "qcom,i2c-qup-v2.2.1"; 1653 reg = <0x0c176000 0x600>; 1654 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1655 1656 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 1657 <&gcc GCC_BLSP1_AHB_CLK>; 1658 clock-names = "core", "iface"; 1659 clock-frequency = <400000>; 1660 dmas = <&blsp1_dma 6>, <&blsp1_dma 7>; 1661 dma-names = "tx", "rx"; 1662 1663 pinctrl-names = "default", "sleep"; 1664 pinctrl-0 = <&i2c2_default>; 1665 pinctrl-1 = <&i2c2_sleep>; 1666 #address-cells = <1>; 1667 #size-cells = <0>; 1668 status = "disabled"; 1669 }; 1670 1671 blsp_i2c3: i2c@c177000 { 1672 compatible = "qcom,i2c-qup-v2.2.1"; 1673 reg = <0x0c177000 0x600>; 1674 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1675 1676 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 1677 <&gcc GCC_BLSP1_AHB_CLK>; 1678 clock-names = "core", "iface"; 1679 clock-frequency = <400000>; 1680 dmas = <&blsp1_dma 8>, <&blsp1_dma 9>; 1681 dma-names = "tx", "rx"; 1682 1683 pinctrl-names = "default", "sleep"; 1684 pinctrl-0 = <&i2c3_default>; 1685 pinctrl-1 = <&i2c3_sleep>; 1686 #address-cells = <1>; 1687 #size-cells = <0>; 1688 status = "disabled"; 1689 }; 1690 1691 blsp_i2c4: i2c@c178000 { 1692 compatible = "qcom,i2c-qup-v2.2.1"; 1693 reg = <0x0c178000 0x600>; 1694 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1695 1696 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, 1697 <&gcc GCC_BLSP1_AHB_CLK>; 1698 clock-names = "core", "iface"; 1699 clock-frequency = <400000>; 1700 dmas = <&blsp1_dma 10>, <&blsp1_dma 11>; 1701 dma-names = "tx", "rx"; 1702 1703 pinctrl-names = "default", "sleep"; 1704 pinctrl-0 = <&i2c4_default>; 1705 pinctrl-1 = <&i2c4_sleep>; 1706 #address-cells = <1>; 1707 #size-cells = <0>; 1708 status = "disabled"; 1709 }; 1710 1711 blsp2_dma: dma-controller@c184000 { 1712 compatible = "qcom,bam-v1.7.0"; 1713 reg = <0x0c184000 0x1f000>; 1714 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 1715 clocks = <&gcc GCC_BLSP2_AHB_CLK>; 1716 clock-names = "bam_clk"; 1717 #dma-cells = <1>; 1718 qcom,ee = <0>; 1719 qcom,controlled-remotely; 1720 num-channels = <18>; 1721 qcom,num-ees = <4>; 1722 }; 1723 1724 blsp2_uart1: serial@c1af000 { 1725 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1726 reg = <0x0c1af000 0x200>; 1727 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 1728 clocks = <&gcc GCC_BLSP2_UART1_APPS_CLK>, 1729 <&gcc GCC_BLSP2_AHB_CLK>; 1730 clock-names = "core", "iface"; 1731 dmas = <&blsp2_dma 0>, <&blsp2_dma 1>; 1732 dma-names = "tx", "rx"; 1733 pinctrl-names = "default", "sleep"; 1734 pinctrl-0 = <&blsp2_uart1_default>; 1735 pinctrl-1 = <&blsp2_uart1_sleep>; 1736 status = "disabled"; 1737 }; 1738 1739 blsp_i2c5: i2c@c1b5000 { 1740 compatible = "qcom,i2c-qup-v2.2.1"; 1741 reg = <0x0c1b5000 0x600>; 1742 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 1743 1744 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, 1745 <&gcc GCC_BLSP2_AHB_CLK>; 1746 clock-names = "core", "iface"; 1747 clock-frequency = <400000>; 1748 dmas = <&blsp2_dma 4>, <&blsp2_dma 5>; 1749 dma-names = "tx", "rx"; 1750 1751 pinctrl-names = "default", "sleep"; 1752 pinctrl-0 = <&i2c5_default>; 1753 pinctrl-1 = <&i2c5_sleep>; 1754 #address-cells = <1>; 1755 #size-cells = <0>; 1756 status = "disabled"; 1757 }; 1758 1759 blsp_i2c6: i2c@c1b6000 { 1760 compatible = "qcom,i2c-qup-v2.2.1"; 1761 reg = <0x0c1b6000 0x600>; 1762 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 1763 1764 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, 1765 <&gcc GCC_BLSP2_AHB_CLK>; 1766 clock-names = "core", "iface"; 1767 clock-frequency = <400000>; 1768 dmas = <&blsp2_dma 6>, <&blsp2_dma 7>; 1769 dma-names = "tx", "rx"; 1770 1771 pinctrl-names = "default", "sleep"; 1772 pinctrl-0 = <&i2c6_default>; 1773 pinctrl-1 = <&i2c6_sleep>; 1774 #address-cells = <1>; 1775 #size-cells = <0>; 1776 status = "disabled"; 1777 }; 1778 1779 blsp_i2c7: i2c@c1b7000 { 1780 compatible = "qcom,i2c-qup-v2.2.1"; 1781 reg = <0x0c1b7000 0x600>; 1782 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 1783 1784 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>, 1785 <&gcc GCC_BLSP2_AHB_CLK>; 1786 clock-names = "core", "iface"; 1787 clock-frequency = <400000>; 1788 dmas = <&blsp2_dma 8>, <&blsp2_dma 9>; 1789 dma-names = "tx", "rx"; 1790 1791 pinctrl-names = "default", "sleep"; 1792 pinctrl-0 = <&i2c7_default>; 1793 pinctrl-1 = <&i2c7_sleep>; 1794 #address-cells = <1>; 1795 #size-cells = <0>; 1796 status = "disabled"; 1797 }; 1798 1799 blsp_i2c8: i2c@c1b8000 { 1800 compatible = "qcom,i2c-qup-v2.2.1"; 1801 reg = <0x0c1b8000 0x600>; 1802 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 1803 1804 clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>, 1805 <&gcc GCC_BLSP2_AHB_CLK>; 1806 clock-names = "core", "iface"; 1807 clock-frequency = <400000>; 1808 dmas = <&blsp2_dma 10>, <&blsp2_dma 11>; 1809 dma-names = "tx", "rx"; 1810 1811 pinctrl-names = "default", "sleep"; 1812 pinctrl-0 = <&i2c8_default>; 1813 pinctrl-1 = <&i2c8_sleep>; 1814 #address-cells = <1>; 1815 #size-cells = <0>; 1816 status = "disabled"; 1817 }; 1818 1819 imem@146bf000 { 1820 compatible = "simple-mfd"; 1821 reg = <0x146bf000 0x1000>; 1822 1823 #address-cells = <1>; 1824 #size-cells = <1>; 1825 1826 ranges = <0 0x146bf000 0x1000>; 1827 1828 pil-reloc@94c { 1829 compatible = "qcom,pil-reloc-info"; 1830 reg = <0x94c 0xc8>; 1831 }; 1832 }; 1833 1834 camss: camss@ca00000 { 1835 compatible = "qcom,sdm660-camss"; 1836 reg = <0x0c824000 0x1000>, 1837 <0x0ca00120 0x4>, 1838 <0x0c825000 0x1000>, 1839 <0x0ca00124 0x4>, 1840 <0x0c826000 0x1000>, 1841 <0x0ca00128 0x4>, 1842 <0x0ca30000 0x100>, 1843 <0x0ca30400 0x100>, 1844 <0x0ca30800 0x100>, 1845 <0x0ca30c00 0x100>, 1846 <0x0ca31000 0x500>, 1847 <0x0ca00020 0x10>, 1848 <0x0ca10000 0x1000>, 1849 <0x0ca14000 0x1000>; 1850 reg-names = "csiphy0", 1851 "csiphy0_clk_mux", 1852 "csiphy1", 1853 "csiphy1_clk_mux", 1854 "csiphy2", 1855 "csiphy2_clk_mux", 1856 "csid0", 1857 "csid1", 1858 "csid2", 1859 "csid3", 1860 "ispif", 1861 "csi_clk_mux", 1862 "vfe0", 1863 "vfe1"; 1864 interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>, 1865 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>, 1866 <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>, 1867 <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>, 1868 <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>, 1869 <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>, 1870 <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>, 1871 <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>, 1872 <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>, 1873 <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>; 1874 interrupt-names = "csiphy0", 1875 "csiphy1", 1876 "csiphy2", 1877 "csid0", 1878 "csid1", 1879 "csid2", 1880 "csid3", 1881 "ispif", 1882 "vfe0", 1883 "vfe1"; 1884 clocks = <&mmcc CAMSS_TOP_AHB_CLK>, 1885 <&mmcc THROTTLE_CAMSS_AXI_CLK>, 1886 <&mmcc CAMSS_ISPIF_AHB_CLK>, 1887 <&mmcc CAMSS_CSI0PHYTIMER_CLK>, 1888 <&mmcc CAMSS_CSI1PHYTIMER_CLK>, 1889 <&mmcc CAMSS_CSI2PHYTIMER_CLK>, 1890 <&mmcc CAMSS_CSI0_AHB_CLK>, 1891 <&mmcc CAMSS_CSI0_CLK>, 1892 <&mmcc CAMSS_CPHY_CSID0_CLK>, 1893 <&mmcc CAMSS_CSI0PIX_CLK>, 1894 <&mmcc CAMSS_CSI0RDI_CLK>, 1895 <&mmcc CAMSS_CSI1_AHB_CLK>, 1896 <&mmcc CAMSS_CSI1_CLK>, 1897 <&mmcc CAMSS_CPHY_CSID1_CLK>, 1898 <&mmcc CAMSS_CSI1PIX_CLK>, 1899 <&mmcc CAMSS_CSI1RDI_CLK>, 1900 <&mmcc CAMSS_CSI2_AHB_CLK>, 1901 <&mmcc CAMSS_CSI2_CLK>, 1902 <&mmcc CAMSS_CPHY_CSID2_CLK>, 1903 <&mmcc CAMSS_CSI2PIX_CLK>, 1904 <&mmcc CAMSS_CSI2RDI_CLK>, 1905 <&mmcc CAMSS_CSI3_AHB_CLK>, 1906 <&mmcc CAMSS_CSI3_CLK>, 1907 <&mmcc CAMSS_CPHY_CSID3_CLK>, 1908 <&mmcc CAMSS_CSI3PIX_CLK>, 1909 <&mmcc CAMSS_CSI3RDI_CLK>, 1910 <&mmcc CAMSS_AHB_CLK>, 1911 <&mmcc CAMSS_VFE0_CLK>, 1912 <&mmcc CAMSS_CSI_VFE0_CLK>, 1913 <&mmcc CAMSS_VFE0_AHB_CLK>, 1914 <&mmcc CAMSS_VFE0_STREAM_CLK>, 1915 <&mmcc CAMSS_VFE1_CLK>, 1916 <&mmcc CAMSS_CSI_VFE1_CLK>, 1917 <&mmcc CAMSS_VFE1_AHB_CLK>, 1918 <&mmcc CAMSS_VFE1_STREAM_CLK>, 1919 <&mmcc CAMSS_VFE_VBIF_AHB_CLK>, 1920 <&mmcc CAMSS_VFE_VBIF_AXI_CLK>, 1921 <&mmcc CSIPHY_AHB2CRIF_CLK>, 1922 <&mmcc CAMSS_CPHY_CSID0_CLK>, 1923 <&mmcc CAMSS_CPHY_CSID1_CLK>, 1924 <&mmcc CAMSS_CPHY_CSID2_CLK>, 1925 <&mmcc CAMSS_CPHY_CSID3_CLK>; 1926 clock-names = "top_ahb", 1927 "throttle_axi", 1928 "ispif_ahb", 1929 "csiphy0_timer", 1930 "csiphy1_timer", 1931 "csiphy2_timer", 1932 "csi0_ahb", 1933 "csi0", 1934 "csi0_phy", 1935 "csi0_pix", 1936 "csi0_rdi", 1937 "csi1_ahb", 1938 "csi1", 1939 "csi1_phy", 1940 "csi1_pix", 1941 "csi1_rdi", 1942 "csi2_ahb", 1943 "csi2", 1944 "csi2_phy", 1945 "csi2_pix", 1946 "csi2_rdi", 1947 "csi3_ahb", 1948 "csi3", 1949 "csi3_phy", 1950 "csi3_pix", 1951 "csi3_rdi", 1952 "ahb", 1953 "vfe0", 1954 "csi_vfe0", 1955 "vfe0_ahb", 1956 "vfe0_stream", 1957 "vfe1", 1958 "csi_vfe1", 1959 "vfe1_ahb", 1960 "vfe1_stream", 1961 "vfe_ahb", 1962 "vfe_axi", 1963 "csiphy_ahb2crif", 1964 "cphy_csid0", 1965 "cphy_csid1", 1966 "cphy_csid2", 1967 "cphy_csid3"; 1968 interconnects = <&mnoc 5 &bimc 5>; 1969 interconnect-names = "vfe-mem"; 1970 iommus = <&mmss_smmu 0xc00>, 1971 <&mmss_smmu 0xc01>, 1972 <&mmss_smmu 0xc02>, 1973 <&mmss_smmu 0xc03>; 1974 power-domains = <&mmcc CAMSS_VFE0_GDSC>, 1975 <&mmcc CAMSS_VFE1_GDSC>; 1976 status = "disabled"; 1977 1978 ports { 1979 #address-cells = <1>; 1980 #size-cells = <0>; 1981 }; 1982 }; 1983 1984 cci: cci@ca0c000 { 1985 compatible = "qcom,msm8996-cci"; 1986 #address-cells = <1>; 1987 #size-cells = <0>; 1988 reg = <0x0ca0c000 0x1000>; 1989 interrupts = <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>; 1990 1991 assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>, 1992 <&mmcc CAMSS_CCI_CLK>; 1993 assigned-clock-rates = <80800000>, <37500000>; 1994 clocks = <&mmcc CAMSS_TOP_AHB_CLK>, 1995 <&mmcc CAMSS_CCI_AHB_CLK>, 1996 <&mmcc CAMSS_CCI_CLK>, 1997 <&mmcc CAMSS_AHB_CLK>; 1998 clock-names = "camss_top_ahb", 1999 "cci_ahb", 2000 "cci", 2001 "camss_ahb"; 2002 2003 pinctrl-names = "default"; 2004 pinctrl-0 = <&cci0_default &cci1_default>; 2005 power-domains = <&mmcc CAMSS_TOP_GDSC>; 2006 status = "disabled"; 2007 2008 cci_i2c0: i2c-bus@0 { 2009 reg = <0>; 2010 clock-frequency = <400000>; 2011 #address-cells = <1>; 2012 #size-cells = <0>; 2013 }; 2014 2015 cci_i2c1: i2c-bus@1 { 2016 reg = <1>; 2017 clock-frequency = <400000>; 2018 #address-cells = <1>; 2019 #size-cells = <0>; 2020 }; 2021 }; 2022 2023 mmss_smmu: iommu@cd00000 { 2024 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2"; 2025 reg = <0x0cd00000 0x40000>; 2026 2027 clocks = <&mmcc MNOC_AHB_CLK>, 2028 <&mmcc BIMC_SMMU_AHB_CLK>, 2029 <&rpmcc RPM_SMD_MMSSNOC_AXI_CLK>, 2030 <&mmcc BIMC_SMMU_AXI_CLK>; 2031 clock-names = "iface-mm", "iface-smmu", 2032 "bus-mm", "bus-smmu"; 2033 #global-interrupts = <2>; 2034 #iommu-cells = <1>; 2035 2036 interrupts = 2037 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 2038 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 2039 2040 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 2041 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 2042 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, 2043 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 2044 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 2045 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 2046 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 2047 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 2048 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 2049 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 2050 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 2051 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 2052 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 2053 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 2054 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 2055 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 2056 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 2057 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 2058 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 2059 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, 2060 <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, 2061 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 2062 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 2063 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>; 2064 2065 status = "disabled"; 2066 }; 2067 2068 adsp_pil: remoteproc@15700000 { 2069 compatible = "qcom,sdm660-adsp-pas"; 2070 reg = <0x15700000 0x4040>; 2071 2072 interrupts-extended = 2073 <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 2074 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2075 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2076 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2077 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2078 interrupt-names = "wdog", "fatal", "ready", 2079 "handover", "stop-ack"; 2080 2081 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 2082 clock-names = "xo"; 2083 2084 memory-region = <&adsp_region>; 2085 power-domains = <&rpmpd SDM660_VDDCX>; 2086 power-domain-names = "cx"; 2087 2088 qcom,smem-states = <&adsp_smp2p_out 0>; 2089 qcom,smem-state-names = "stop"; 2090 2091 glink-edge { 2092 interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>; 2093 2094 label = "lpass"; 2095 mboxes = <&apcs_glb 9>; 2096 qcom,remote-pid = <2>; 2097 #address-cells = <1>; 2098 #size-cells = <0>; 2099 2100 apr { 2101 compatible = "qcom,apr-v2"; 2102 qcom,glink-channels = "apr_audio_svc"; 2103 qcom,apr-domain = <APR_DOMAIN_ADSP>; 2104 #address-cells = <1>; 2105 #size-cells = <0>; 2106 2107 q6core { 2108 reg = <APR_SVC_ADSP_CORE>; 2109 compatible = "qcom,q6core"; 2110 }; 2111 2112 q6afe: apr-service@4 { 2113 compatible = "qcom,q6afe"; 2114 reg = <APR_SVC_AFE>; 2115 q6afedai: dais { 2116 compatible = "qcom,q6afe-dais"; 2117 #address-cells = <1>; 2118 #size-cells = <0>; 2119 #sound-dai-cells = <1>; 2120 }; 2121 }; 2122 2123 q6asm: apr-service@7 { 2124 compatible = "qcom,q6asm"; 2125 reg = <APR_SVC_ASM>; 2126 q6asmdai: dais { 2127 compatible = "qcom,q6asm-dais"; 2128 #address-cells = <1>; 2129 #size-cells = <0>; 2130 #sound-dai-cells = <1>; 2131 iommus = <&lpass_smmu 1>; 2132 }; 2133 }; 2134 2135 q6adm: apr-service@8 { 2136 compatible = "qcom,q6adm"; 2137 reg = <APR_SVC_ADM>; 2138 q6routing: routing { 2139 compatible = "qcom,q6adm-routing"; 2140 #sound-dai-cells = <0>; 2141 }; 2142 }; 2143 }; 2144 }; 2145 }; 2146 2147 gnoc: interconnect@17900000 { 2148 compatible = "qcom,sdm660-gnoc"; 2149 reg = <0x17900000 0xe000>; 2150 #interconnect-cells = <1>; 2151 /* 2152 * This one apparently features no clocks, 2153 * so let's not mess with the driver needlessly 2154 */ 2155 clock-names = "bus", "bus_a"; 2156 clocks = <&xo_board>, <&xo_board>; 2157 }; 2158 2159 apcs_glb: mailbox@17911000 { 2160 compatible = "qcom,sdm660-apcs-hmss-global"; 2161 reg = <0x17911000 0x1000>; 2162 2163 #mbox-cells = <1>; 2164 }; 2165 2166 timer@17920000 { 2167 #address-cells = <1>; 2168 #size-cells = <1>; 2169 ranges; 2170 compatible = "arm,armv7-timer-mem"; 2171 reg = <0x17920000 0x1000>; 2172 clock-frequency = <19200000>; 2173 2174 frame@17921000 { 2175 frame-number = <0>; 2176 interrupts = <0 8 0x4>, 2177 <0 7 0x4>; 2178 reg = <0x17921000 0x1000>, 2179 <0x17922000 0x1000>; 2180 }; 2181 2182 frame@17923000 { 2183 frame-number = <1>; 2184 interrupts = <0 9 0x4>; 2185 reg = <0x17923000 0x1000>; 2186 status = "disabled"; 2187 }; 2188 2189 frame@17924000 { 2190 frame-number = <2>; 2191 interrupts = <0 10 0x4>; 2192 reg = <0x17924000 0x1000>; 2193 status = "disabled"; 2194 }; 2195 2196 frame@17925000 { 2197 frame-number = <3>; 2198 interrupts = <0 11 0x4>; 2199 reg = <0x17925000 0x1000>; 2200 status = "disabled"; 2201 }; 2202 2203 frame@17926000 { 2204 frame-number = <4>; 2205 interrupts = <0 12 0x4>; 2206 reg = <0x17926000 0x1000>; 2207 status = "disabled"; 2208 }; 2209 2210 frame@17927000 { 2211 frame-number = <5>; 2212 interrupts = <0 13 0x4>; 2213 reg = <0x17927000 0x1000>; 2214 status = "disabled"; 2215 }; 2216 2217 frame@17928000 { 2218 frame-number = <6>; 2219 interrupts = <0 14 0x4>; 2220 reg = <0x17928000 0x1000>; 2221 status = "disabled"; 2222 }; 2223 }; 2224 2225 intc: interrupt-controller@17a00000 { 2226 compatible = "arm,gic-v3"; 2227 reg = <0x17a00000 0x10000>, /* GICD */ 2228 <0x17b00000 0x100000>; /* GICR * 8 */ 2229 #interrupt-cells = <3>; 2230 #address-cells = <1>; 2231 #size-cells = <1>; 2232 ranges; 2233 interrupt-controller; 2234 #redistributor-regions = <1>; 2235 redistributor-stride = <0x0 0x20000>; 2236 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 2237 }; 2238 }; 2239 2240 tcsr_mutex: hwlock { 2241 compatible = "qcom,tcsr-mutex"; 2242 syscon = <&tcsr_mutex_regs 0 0x1000>; 2243 #hwlock-cells = <1>; 2244 }; 2245 2246 sound: sound { 2247 }; 2248 2249 thermal-zones { 2250 aoss-thermal { 2251 polling-delay-passive = <250>; 2252 polling-delay = <1000>; 2253 2254 thermal-sensors = <&tsens 0>; 2255 2256 trips { 2257 aoss_alert0: trip-point0 { 2258 temperature = <105000>; 2259 hysteresis = <1000>; 2260 type = "hot"; 2261 }; 2262 }; 2263 }; 2264 2265 cpuss0-thermal { 2266 polling-delay-passive = <250>; 2267 polling-delay = <1000>; 2268 2269 thermal-sensors = <&tsens 1>; 2270 2271 trips { 2272 cpuss0_alert0: trip-point0 { 2273 temperature = <125000>; 2274 hysteresis = <1000>; 2275 type = "hot"; 2276 }; 2277 }; 2278 }; 2279 2280 cpuss1-thermal { 2281 polling-delay-passive = <250>; 2282 polling-delay = <1000>; 2283 2284 thermal-sensors = <&tsens 2>; 2285 2286 trips { 2287 cpuss1_alert0: trip-point0 { 2288 temperature = <125000>; 2289 hysteresis = <1000>; 2290 type = "hot"; 2291 }; 2292 }; 2293 }; 2294 2295 cpu0-thermal { 2296 polling-delay-passive = <250>; 2297 polling-delay = <1000>; 2298 2299 thermal-sensors = <&tsens 3>; 2300 2301 trips { 2302 cpu0_alert0: trip-point0 { 2303 temperature = <70000>; 2304 hysteresis = <1000>; 2305 type = "passive"; 2306 }; 2307 2308 cpu0_crit: cpu_crit { 2309 temperature = <110000>; 2310 hysteresis = <1000>; 2311 type = "critical"; 2312 }; 2313 }; 2314 }; 2315 2316 cpu1-thermal { 2317 polling-delay-passive = <250>; 2318 polling-delay = <1000>; 2319 2320 thermal-sensors = <&tsens 4>; 2321 2322 trips { 2323 cpu1_alert0: trip-point0 { 2324 temperature = <70000>; 2325 hysteresis = <1000>; 2326 type = "passive"; 2327 }; 2328 2329 cpu1_crit: cpu_crit { 2330 temperature = <110000>; 2331 hysteresis = <1000>; 2332 type = "critical"; 2333 }; 2334 }; 2335 }; 2336 2337 cpu2-thermal { 2338 polling-delay-passive = <250>; 2339 polling-delay = <1000>; 2340 2341 thermal-sensors = <&tsens 5>; 2342 2343 trips { 2344 cpu2_alert0: trip-point0 { 2345 temperature = <70000>; 2346 hysteresis = <1000>; 2347 type = "passive"; 2348 }; 2349 2350 cpu2_crit: cpu_crit { 2351 temperature = <110000>; 2352 hysteresis = <1000>; 2353 type = "critical"; 2354 }; 2355 }; 2356 }; 2357 2358 cpu3-thermal { 2359 polling-delay-passive = <250>; 2360 polling-delay = <1000>; 2361 2362 thermal-sensors = <&tsens 6>; 2363 2364 trips { 2365 cpu3_alert0: trip-point0 { 2366 temperature = <70000>; 2367 hysteresis = <1000>; 2368 type = "passive"; 2369 }; 2370 2371 cpu3_crit: cpu_crit { 2372 temperature = <110000>; 2373 hysteresis = <1000>; 2374 type = "critical"; 2375 }; 2376 }; 2377 }; 2378 2379 /* 2380 * According to what downstream DTS says, 2381 * the entire power efficient cluster has 2382 * only a single thermal sensor. 2383 */ 2384 2385 pwr-cluster-thermal { 2386 polling-delay-passive = <250>; 2387 polling-delay = <1000>; 2388 2389 thermal-sensors = <&tsens 7>; 2390 2391 trips { 2392 pwr_cluster_alert0: trip-point0 { 2393 temperature = <70000>; 2394 hysteresis = <1000>; 2395 type = "passive"; 2396 }; 2397 2398 pwr_cluster_crit: cpu_crit { 2399 temperature = <110000>; 2400 hysteresis = <1000>; 2401 type = "critical"; 2402 }; 2403 }; 2404 }; 2405 2406 gpu-thermal { 2407 polling-delay-passive = <250>; 2408 polling-delay = <1000>; 2409 2410 thermal-sensors = <&tsens 8>; 2411 2412 trips { 2413 gpu_alert0: trip-point0 { 2414 temperature = <90000>; 2415 hysteresis = <1000>; 2416 type = "hot"; 2417 }; 2418 }; 2419 }; 2420 }; 2421 2422 timer { 2423 compatible = "arm,armv8-timer"; 2424 interrupts = <GIC_PPI 1 0xf08>, 2425 <GIC_PPI 2 0xf08>, 2426 <GIC_PPI 3 0xf08>, 2427 <GIC_PPI 0 0xf08>; 2428 }; 2429}; 2430 2431