1b190fb01SKonrad Dybcio// SPDX-License-Identifier: BSD-3-Clause 2b190fb01SKonrad Dybcio/* 35cf69dcbSAngeloGioacchino Del Regno * Copyright (c) 2020, Konrad Dybcio <konradybcio@gmail.com> 45cf69dcbSAngeloGioacchino Del Regno * Copyright (c) 2020, AngeloGioacchino Del Regno <kholk11@gmail.com> 5b190fb01SKonrad Dybcio */ 6b190fb01SKonrad Dybcio 7b190fb01SKonrad Dybcio#include <dt-bindings/clock/qcom,gcc-sdm660.h> 8a64fa0e2SAngeloGioacchino Del Regno#include <dt-bindings/clock/qcom,gpucc-sdm660.h> 9045547a0SKonrad Dybcio#include <dt-bindings/clock/qcom,mmcc-sdm660.h> 10b190fb01SKonrad Dybcio#include <dt-bindings/clock/qcom,rpmcc.h> 111ce921aeSKonrad Dybcio#include <dt-bindings/power/qcom-rpmpd.h> 12b190fb01SKonrad Dybcio#include <dt-bindings/gpio/gpio.h> 13b190fb01SKonrad Dybcio#include <dt-bindings/interrupt-controller/arm-gic.h> 147ca2ebc9SKonrad Dybcio#include <dt-bindings/soc/qcom,apr.h> 15b190fb01SKonrad Dybcio 16b190fb01SKonrad Dybcio/ { 17b190fb01SKonrad Dybcio interrupt-parent = <&intc>; 18b190fb01SKonrad Dybcio 19b190fb01SKonrad Dybcio #address-cells = <2>; 20b190fb01SKonrad Dybcio #size-cells = <2>; 21b190fb01SKonrad Dybcio 22b1394251SDang Huynh aliases { 23b1394251SDang Huynh mmc1 = &sdhc_1; 24b1394251SDang Huynh mmc2 = &sdhc_2; 25b1394251SDang Huynh }; 26b1394251SDang Huynh 27b190fb01SKonrad Dybcio chosen { }; 28b190fb01SKonrad Dybcio 29b190fb01SKonrad Dybcio clocks { 30639dfdbeSVinod Koul xo_board: xo-board { 31b190fb01SKonrad Dybcio compatible = "fixed-clock"; 32b190fb01SKonrad Dybcio #clock-cells = <0>; 33b190fb01SKonrad Dybcio clock-frequency = <19200000>; 34b190fb01SKonrad Dybcio clock-output-names = "xo_board"; 35b190fb01SKonrad Dybcio }; 36b190fb01SKonrad Dybcio 37639dfdbeSVinod Koul sleep_clk: sleep-clk { 38b190fb01SKonrad Dybcio compatible = "fixed-clock"; 39b190fb01SKonrad Dybcio #clock-cells = <0>; 40b190fb01SKonrad Dybcio clock-frequency = <32764>; 41b190fb01SKonrad Dybcio clock-output-names = "sleep_clk"; 42b190fb01SKonrad Dybcio }; 43b190fb01SKonrad Dybcio }; 44b190fb01SKonrad Dybcio 45b190fb01SKonrad Dybcio cpus { 46b190fb01SKonrad Dybcio #address-cells = <2>; 47b190fb01SKonrad Dybcio #size-cells = <0>; 48b190fb01SKonrad Dybcio 49b190fb01SKonrad Dybcio CPU0: cpu@100 { 50b190fb01SKonrad Dybcio device_type = "cpu"; 51b190fb01SKonrad Dybcio compatible = "arm,cortex-a53"; 52b190fb01SKonrad Dybcio reg = <0x0 0x100>; 53b190fb01SKonrad Dybcio enable-method = "psci"; 54b190fb01SKonrad Dybcio cpu-idle-states = <&PERF_CPU_SLEEP_0 55b190fb01SKonrad Dybcio &PERF_CPU_SLEEP_1 56b190fb01SKonrad Dybcio &PERF_CLUSTER_SLEEP_0 57b190fb01SKonrad Dybcio &PERF_CLUSTER_SLEEP_1 58b190fb01SKonrad Dybcio &PERF_CLUSTER_SLEEP_2>; 59b190fb01SKonrad Dybcio capacity-dmips-mhz = <1126>; 60b190fb01SKonrad Dybcio #cooling-cells = <2>; 61b190fb01SKonrad Dybcio next-level-cache = <&L2_1>; 62b190fb01SKonrad Dybcio L2_1: l2-cache { 63b190fb01SKonrad Dybcio compatible = "cache"; 64b190fb01SKonrad Dybcio cache-level = <2>; 65b190fb01SKonrad Dybcio }; 66b190fb01SKonrad Dybcio }; 67b190fb01SKonrad Dybcio 68b190fb01SKonrad Dybcio CPU1: cpu@101 { 69b190fb01SKonrad Dybcio device_type = "cpu"; 70b190fb01SKonrad Dybcio compatible = "arm,cortex-a53"; 71b190fb01SKonrad Dybcio reg = <0x0 0x101>; 72b190fb01SKonrad Dybcio enable-method = "psci"; 73b190fb01SKonrad Dybcio cpu-idle-states = <&PERF_CPU_SLEEP_0 74b190fb01SKonrad Dybcio &PERF_CPU_SLEEP_1 75b190fb01SKonrad Dybcio &PERF_CLUSTER_SLEEP_0 76b190fb01SKonrad Dybcio &PERF_CLUSTER_SLEEP_1 77b190fb01SKonrad Dybcio &PERF_CLUSTER_SLEEP_2>; 78b190fb01SKonrad Dybcio capacity-dmips-mhz = <1126>; 79b190fb01SKonrad Dybcio #cooling-cells = <2>; 80b190fb01SKonrad Dybcio next-level-cache = <&L2_1>; 81b190fb01SKonrad Dybcio }; 82b190fb01SKonrad Dybcio 83b190fb01SKonrad Dybcio CPU2: cpu@102 { 84b190fb01SKonrad Dybcio device_type = "cpu"; 85b190fb01SKonrad Dybcio compatible = "arm,cortex-a53"; 86b190fb01SKonrad Dybcio reg = <0x0 0x102>; 87b190fb01SKonrad Dybcio enable-method = "psci"; 88b190fb01SKonrad Dybcio cpu-idle-states = <&PERF_CPU_SLEEP_0 89b190fb01SKonrad Dybcio &PERF_CPU_SLEEP_1 90b190fb01SKonrad Dybcio &PERF_CLUSTER_SLEEP_0 91b190fb01SKonrad Dybcio &PERF_CLUSTER_SLEEP_1 92b190fb01SKonrad Dybcio &PERF_CLUSTER_SLEEP_2>; 93b190fb01SKonrad Dybcio capacity-dmips-mhz = <1126>; 94b190fb01SKonrad Dybcio #cooling-cells = <2>; 95b190fb01SKonrad Dybcio next-level-cache = <&L2_1>; 96b190fb01SKonrad Dybcio }; 97b190fb01SKonrad Dybcio 98b190fb01SKonrad Dybcio CPU3: cpu@103 { 99b190fb01SKonrad Dybcio device_type = "cpu"; 100b190fb01SKonrad Dybcio compatible = "arm,cortex-a53"; 101b190fb01SKonrad Dybcio reg = <0x0 0x103>; 102b190fb01SKonrad Dybcio enable-method = "psci"; 103b190fb01SKonrad Dybcio cpu-idle-states = <&PERF_CPU_SLEEP_0 104b190fb01SKonrad Dybcio &PERF_CPU_SLEEP_1 105b190fb01SKonrad Dybcio &PERF_CLUSTER_SLEEP_0 106b190fb01SKonrad Dybcio &PERF_CLUSTER_SLEEP_1 107b190fb01SKonrad Dybcio &PERF_CLUSTER_SLEEP_2>; 108b190fb01SKonrad Dybcio capacity-dmips-mhz = <1126>; 109b190fb01SKonrad Dybcio #cooling-cells = <2>; 110b190fb01SKonrad Dybcio next-level-cache = <&L2_1>; 111b190fb01SKonrad Dybcio }; 112b190fb01SKonrad Dybcio 113b190fb01SKonrad Dybcio CPU4: cpu@0 { 114b190fb01SKonrad Dybcio device_type = "cpu"; 115b190fb01SKonrad Dybcio compatible = "arm,cortex-a53"; 116b190fb01SKonrad Dybcio reg = <0x0 0x0>; 117b190fb01SKonrad Dybcio enable-method = "psci"; 118b190fb01SKonrad Dybcio cpu-idle-states = <&PWR_CPU_SLEEP_0 119b190fb01SKonrad Dybcio &PWR_CPU_SLEEP_1 120b190fb01SKonrad Dybcio &PWR_CLUSTER_SLEEP_0 121b190fb01SKonrad Dybcio &PWR_CLUSTER_SLEEP_1 122b190fb01SKonrad Dybcio &PWR_CLUSTER_SLEEP_2>; 123b190fb01SKonrad Dybcio capacity-dmips-mhz = <1024>; 124b190fb01SKonrad Dybcio #cooling-cells = <2>; 125b190fb01SKonrad Dybcio next-level-cache = <&L2_0>; 126b190fb01SKonrad Dybcio L2_0: l2-cache { 127b190fb01SKonrad Dybcio compatible = "cache"; 128b190fb01SKonrad Dybcio cache-level = <2>; 129b190fb01SKonrad Dybcio }; 130b190fb01SKonrad Dybcio }; 131b190fb01SKonrad Dybcio 132b190fb01SKonrad Dybcio CPU5: cpu@1 { 133b190fb01SKonrad Dybcio device_type = "cpu"; 134b190fb01SKonrad Dybcio compatible = "arm,cortex-a53"; 135b190fb01SKonrad Dybcio reg = <0x0 0x1>; 136b190fb01SKonrad Dybcio enable-method = "psci"; 137b190fb01SKonrad Dybcio cpu-idle-states = <&PWR_CPU_SLEEP_0 138b190fb01SKonrad Dybcio &PWR_CPU_SLEEP_1 139b190fb01SKonrad Dybcio &PWR_CLUSTER_SLEEP_0 140b190fb01SKonrad Dybcio &PWR_CLUSTER_SLEEP_1 141b190fb01SKonrad Dybcio &PWR_CLUSTER_SLEEP_2>; 142b190fb01SKonrad Dybcio capacity-dmips-mhz = <1024>; 143b190fb01SKonrad Dybcio #cooling-cells = <2>; 144b190fb01SKonrad Dybcio next-level-cache = <&L2_0>; 145b190fb01SKonrad Dybcio }; 146b190fb01SKonrad Dybcio 147b190fb01SKonrad Dybcio CPU6: cpu@2 { 148b190fb01SKonrad Dybcio device_type = "cpu"; 149b190fb01SKonrad Dybcio compatible = "arm,cortex-a53"; 150b190fb01SKonrad Dybcio reg = <0x0 0x2>; 151b190fb01SKonrad Dybcio enable-method = "psci"; 152b190fb01SKonrad Dybcio cpu-idle-states = <&PWR_CPU_SLEEP_0 153b190fb01SKonrad Dybcio &PWR_CPU_SLEEP_1 154b190fb01SKonrad Dybcio &PWR_CLUSTER_SLEEP_0 155b190fb01SKonrad Dybcio &PWR_CLUSTER_SLEEP_1 156b190fb01SKonrad Dybcio &PWR_CLUSTER_SLEEP_2>; 157b190fb01SKonrad Dybcio capacity-dmips-mhz = <1024>; 158b190fb01SKonrad Dybcio #cooling-cells = <2>; 159b190fb01SKonrad Dybcio next-level-cache = <&L2_0>; 160b190fb01SKonrad Dybcio }; 161b190fb01SKonrad Dybcio 162b190fb01SKonrad Dybcio CPU7: cpu@3 { 163b190fb01SKonrad Dybcio device_type = "cpu"; 164b190fb01SKonrad Dybcio compatible = "arm,cortex-a53"; 165b190fb01SKonrad Dybcio reg = <0x0 0x3>; 166b190fb01SKonrad Dybcio enable-method = "psci"; 167b190fb01SKonrad Dybcio cpu-idle-states = <&PWR_CPU_SLEEP_0 168b190fb01SKonrad Dybcio &PWR_CPU_SLEEP_1 169b190fb01SKonrad Dybcio &PWR_CLUSTER_SLEEP_0 170b190fb01SKonrad Dybcio &PWR_CLUSTER_SLEEP_1 171b190fb01SKonrad Dybcio &PWR_CLUSTER_SLEEP_2>; 172b190fb01SKonrad Dybcio capacity-dmips-mhz = <1024>; 173b190fb01SKonrad Dybcio #cooling-cells = <2>; 174b190fb01SKonrad Dybcio next-level-cache = <&L2_0>; 175b190fb01SKonrad Dybcio }; 176b190fb01SKonrad Dybcio 177b190fb01SKonrad Dybcio cpu-map { 178b190fb01SKonrad Dybcio cluster0 { 179b190fb01SKonrad Dybcio core0 { 180b190fb01SKonrad Dybcio cpu = <&CPU4>; 181b190fb01SKonrad Dybcio }; 182b190fb01SKonrad Dybcio 183b190fb01SKonrad Dybcio core1 { 184b190fb01SKonrad Dybcio cpu = <&CPU5>; 185b190fb01SKonrad Dybcio }; 186b190fb01SKonrad Dybcio 187b190fb01SKonrad Dybcio core2 { 188b190fb01SKonrad Dybcio cpu = <&CPU6>; 189b190fb01SKonrad Dybcio }; 190b190fb01SKonrad Dybcio 191b190fb01SKonrad Dybcio core3 { 192b190fb01SKonrad Dybcio cpu = <&CPU7>; 193b190fb01SKonrad Dybcio }; 194b190fb01SKonrad Dybcio }; 195b190fb01SKonrad Dybcio 196b190fb01SKonrad Dybcio cluster1 { 197b190fb01SKonrad Dybcio core0 { 198b190fb01SKonrad Dybcio cpu = <&CPU0>; 199b190fb01SKonrad Dybcio }; 200b190fb01SKonrad Dybcio 201b190fb01SKonrad Dybcio core1 { 202b190fb01SKonrad Dybcio cpu = <&CPU1>; 203b190fb01SKonrad Dybcio }; 204b190fb01SKonrad Dybcio 205b190fb01SKonrad Dybcio core2 { 206b190fb01SKonrad Dybcio cpu = <&CPU2>; 207b190fb01SKonrad Dybcio }; 208b190fb01SKonrad Dybcio 209b190fb01SKonrad Dybcio core3 { 210b190fb01SKonrad Dybcio cpu = <&CPU3>; 211b190fb01SKonrad Dybcio }; 212b190fb01SKonrad Dybcio }; 213b190fb01SKonrad Dybcio }; 214b190fb01SKonrad Dybcio 215b190fb01SKonrad Dybcio idle-states { 216b190fb01SKonrad Dybcio entry-method = "psci"; 217b190fb01SKonrad Dybcio 218b190fb01SKonrad Dybcio PWR_CPU_SLEEP_0: cpu-sleep-0-0 { 219b190fb01SKonrad Dybcio compatible = "arm,idle-state"; 220b190fb01SKonrad Dybcio idle-state-name = "pwr-retention"; 221b190fb01SKonrad Dybcio arm,psci-suspend-param = <0x40000002>; 222b190fb01SKonrad Dybcio entry-latency-us = <338>; 223b190fb01SKonrad Dybcio exit-latency-us = <423>; 224b190fb01SKonrad Dybcio min-residency-us = <200>; 225b190fb01SKonrad Dybcio }; 226b190fb01SKonrad Dybcio 227b190fb01SKonrad Dybcio PWR_CPU_SLEEP_1: cpu-sleep-0-1 { 228b190fb01SKonrad Dybcio compatible = "arm,idle-state"; 229b190fb01SKonrad Dybcio idle-state-name = "pwr-power-collapse"; 230b190fb01SKonrad Dybcio arm,psci-suspend-param = <0x40000003>; 231b190fb01SKonrad Dybcio entry-latency-us = <515>; 232b190fb01SKonrad Dybcio exit-latency-us = <1821>; 233b190fb01SKonrad Dybcio min-residency-us = <1000>; 234b190fb01SKonrad Dybcio local-timer-stop; 235b190fb01SKonrad Dybcio }; 236b190fb01SKonrad Dybcio 237b190fb01SKonrad Dybcio PERF_CPU_SLEEP_0: cpu-sleep-1-0 { 238b190fb01SKonrad Dybcio compatible = "arm,idle-state"; 239b190fb01SKonrad Dybcio idle-state-name = "perf-retention"; 240b190fb01SKonrad Dybcio arm,psci-suspend-param = <0x40000002>; 241b190fb01SKonrad Dybcio entry-latency-us = <154>; 242b190fb01SKonrad Dybcio exit-latency-us = <87>; 243b190fb01SKonrad Dybcio min-residency-us = <200>; 244b190fb01SKonrad Dybcio }; 245b190fb01SKonrad Dybcio 246b190fb01SKonrad Dybcio PERF_CPU_SLEEP_1: cpu-sleep-1-1 { 247b190fb01SKonrad Dybcio compatible = "arm,idle-state"; 248b190fb01SKonrad Dybcio idle-state-name = "perf-power-collapse"; 249b190fb01SKonrad Dybcio arm,psci-suspend-param = <0x40000003>; 250b190fb01SKonrad Dybcio entry-latency-us = <262>; 251b190fb01SKonrad Dybcio exit-latency-us = <301>; 252b190fb01SKonrad Dybcio min-residency-us = <1000>; 253b190fb01SKonrad Dybcio local-timer-stop; 254b190fb01SKonrad Dybcio }; 255b190fb01SKonrad Dybcio 256b190fb01SKonrad Dybcio PWR_CLUSTER_SLEEP_0: cluster-sleep-0-0 { 257b190fb01SKonrad Dybcio compatible = "arm,idle-state"; 258b190fb01SKonrad Dybcio idle-state-name = "pwr-cluster-dynamic-retention"; 259b190fb01SKonrad Dybcio arm,psci-suspend-param = <0x400000F2>; 260b190fb01SKonrad Dybcio entry-latency-us = <284>; 261b190fb01SKonrad Dybcio exit-latency-us = <384>; 262b190fb01SKonrad Dybcio min-residency-us = <9987>; 263b190fb01SKonrad Dybcio local-timer-stop; 264b190fb01SKonrad Dybcio }; 265b190fb01SKonrad Dybcio 266b190fb01SKonrad Dybcio PWR_CLUSTER_SLEEP_1: cluster-sleep-0-1 { 267b190fb01SKonrad Dybcio compatible = "arm,idle-state"; 268b190fb01SKonrad Dybcio idle-state-name = "pwr-cluster-retention"; 269b190fb01SKonrad Dybcio arm,psci-suspend-param = <0x400000F3>; 270b190fb01SKonrad Dybcio entry-latency-us = <338>; 271b190fb01SKonrad Dybcio exit-latency-us = <423>; 272b190fb01SKonrad Dybcio min-residency-us = <9987>; 273b190fb01SKonrad Dybcio local-timer-stop; 274b190fb01SKonrad Dybcio }; 275b190fb01SKonrad Dybcio 276b190fb01SKonrad Dybcio PWR_CLUSTER_SLEEP_2: cluster-sleep-0-2 { 277b190fb01SKonrad Dybcio compatible = "arm,idle-state"; 278b190fb01SKonrad Dybcio idle-state-name = "pwr-cluster-retention"; 279b190fb01SKonrad Dybcio arm,psci-suspend-param = <0x400000F4>; 280b190fb01SKonrad Dybcio entry-latency-us = <515>; 281b190fb01SKonrad Dybcio exit-latency-us = <1821>; 282b190fb01SKonrad Dybcio min-residency-us = <9987>; 283b190fb01SKonrad Dybcio local-timer-stop; 284b190fb01SKonrad Dybcio }; 285b190fb01SKonrad Dybcio 286b190fb01SKonrad Dybcio PERF_CLUSTER_SLEEP_0: cluster-sleep-1-0 { 287b190fb01SKonrad Dybcio compatible = "arm,idle-state"; 288b190fb01SKonrad Dybcio idle-state-name = "perf-cluster-dynamic-retention"; 289b190fb01SKonrad Dybcio arm,psci-suspend-param = <0x400000F2>; 290b190fb01SKonrad Dybcio entry-latency-us = <272>; 291b190fb01SKonrad Dybcio exit-latency-us = <329>; 292b190fb01SKonrad Dybcio min-residency-us = <9987>; 293b190fb01SKonrad Dybcio local-timer-stop; 294b190fb01SKonrad Dybcio }; 295b190fb01SKonrad Dybcio 296b190fb01SKonrad Dybcio PERF_CLUSTER_SLEEP_1: cluster-sleep-1-1 { 297b190fb01SKonrad Dybcio compatible = "arm,idle-state"; 298b190fb01SKonrad Dybcio idle-state-name = "perf-cluster-retention"; 299b190fb01SKonrad Dybcio arm,psci-suspend-param = <0x400000F3>; 300b190fb01SKonrad Dybcio entry-latency-us = <332>; 301b190fb01SKonrad Dybcio exit-latency-us = <368>; 302b190fb01SKonrad Dybcio min-residency-us = <9987>; 303b190fb01SKonrad Dybcio local-timer-stop; 304b190fb01SKonrad Dybcio }; 305b190fb01SKonrad Dybcio 306b190fb01SKonrad Dybcio PERF_CLUSTER_SLEEP_2: cluster-sleep-1-2 { 307b190fb01SKonrad Dybcio compatible = "arm,idle-state"; 308b190fb01SKonrad Dybcio idle-state-name = "perf-cluster-retention"; 309b190fb01SKonrad Dybcio arm,psci-suspend-param = <0x400000F4>; 310b190fb01SKonrad Dybcio entry-latency-us = <545>; 311b190fb01SKonrad Dybcio exit-latency-us = <1609>; 312b190fb01SKonrad Dybcio min-residency-us = <9987>; 313b190fb01SKonrad Dybcio local-timer-stop; 314b190fb01SKonrad Dybcio }; 315b190fb01SKonrad Dybcio }; 316b190fb01SKonrad Dybcio }; 317b190fb01SKonrad Dybcio 318b190fb01SKonrad Dybcio firmware { 319b190fb01SKonrad Dybcio scm { 320b190fb01SKonrad Dybcio compatible = "qcom,scm-msm8998", "qcom,scm"; 321b190fb01SKonrad Dybcio }; 322b190fb01SKonrad Dybcio }; 323b190fb01SKonrad Dybcio 324cfdf0c27SVinod Koul memory@80000000 { 325b190fb01SKonrad Dybcio device_type = "memory"; 326b190fb01SKonrad Dybcio /* We expect the bootloader to fill in the reg */ 327cfdf0c27SVinod Koul reg = <0x0 0x80000000 0x0 0x0>; 328b190fb01SKonrad Dybcio }; 329b190fb01SKonrad Dybcio 330b190fb01SKonrad Dybcio pmu { 331b190fb01SKonrad Dybcio compatible = "arm,armv8-pmuv3"; 332b190fb01SKonrad Dybcio interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>; 333b190fb01SKonrad Dybcio }; 334b190fb01SKonrad Dybcio 335b190fb01SKonrad Dybcio psci { 336b190fb01SKonrad Dybcio compatible = "arm,psci-1.0"; 337b190fb01SKonrad Dybcio method = "smc"; 338b190fb01SKonrad Dybcio }; 339b190fb01SKonrad Dybcio 340b190fb01SKonrad Dybcio reserved-memory { 341b190fb01SKonrad Dybcio #address-cells = <2>; 342b190fb01SKonrad Dybcio #size-cells = <2>; 343b190fb01SKonrad Dybcio ranges; 344b190fb01SKonrad Dybcio 345b190fb01SKonrad Dybcio wlan_msa_guard: wlan-msa-guard@85600000 { 346b190fb01SKonrad Dybcio reg = <0x0 0x85600000 0x0 0x100000>; 347b190fb01SKonrad Dybcio no-map; 348b190fb01SKonrad Dybcio }; 349b190fb01SKonrad Dybcio 350b190fb01SKonrad Dybcio wlan_msa_mem: wlan-msa-mem@85700000 { 351b190fb01SKonrad Dybcio reg = <0x0 0x85700000 0x0 0x100000>; 352b190fb01SKonrad Dybcio no-map; 353b190fb01SKonrad Dybcio }; 354b190fb01SKonrad Dybcio 355b190fb01SKonrad Dybcio qhee_code: qhee-code@85800000 { 35626e02c98SAngeloGioacchino Del Regno reg = <0x0 0x85800000 0x0 0x600000>; 357b190fb01SKonrad Dybcio no-map; 358b190fb01SKonrad Dybcio }; 359b190fb01SKonrad Dybcio 36026e02c98SAngeloGioacchino Del Regno rmtfs_mem: memory@85e00000 { 36126e02c98SAngeloGioacchino Del Regno compatible = "qcom,rmtfs-mem"; 36226e02c98SAngeloGioacchino Del Regno reg = <0x0 0x85e00000 0x0 0x200000>; 36326e02c98SAngeloGioacchino Del Regno no-map; 36426e02c98SAngeloGioacchino Del Regno 36526e02c98SAngeloGioacchino Del Regno qcom,client-id = <1>; 36626e02c98SAngeloGioacchino Del Regno qcom,vmid = <15>; 36726e02c98SAngeloGioacchino Del Regno }; 36826e02c98SAngeloGioacchino Del Regno 369b190fb01SKonrad Dybcio smem_region: smem-mem@86000000 { 370b190fb01SKonrad Dybcio reg = <0 0x86000000 0 0x200000>; 371b190fb01SKonrad Dybcio no-map; 372b190fb01SKonrad Dybcio }; 373b190fb01SKonrad Dybcio 374b190fb01SKonrad Dybcio tz_mem: memory@86200000 { 375b190fb01SKonrad Dybcio reg = <0x0 0x86200000 0x0 0x3300000>; 376b190fb01SKonrad Dybcio no-map; 377b190fb01SKonrad Dybcio }; 378b190fb01SKonrad Dybcio 37926e02c98SAngeloGioacchino Del Regno mpss_region: mpss@8ac00000 { 380b190fb01SKonrad Dybcio reg = <0x0 0x8ac00000 0x0 0x7e00000>; 381b190fb01SKonrad Dybcio no-map; 382b190fb01SKonrad Dybcio }; 383b190fb01SKonrad Dybcio 38426e02c98SAngeloGioacchino Del Regno adsp_region: adsp@92a00000 { 385b190fb01SKonrad Dybcio reg = <0x0 0x92a00000 0x0 0x1e00000>; 386b190fb01SKonrad Dybcio no-map; 387b190fb01SKonrad Dybcio }; 388b190fb01SKonrad Dybcio 38926e02c98SAngeloGioacchino Del Regno mba_region: mba@94800000 { 390b190fb01SKonrad Dybcio reg = <0x0 0x94800000 0x0 0x200000>; 391b190fb01SKonrad Dybcio no-map; 392b190fb01SKonrad Dybcio }; 393b190fb01SKonrad Dybcio 39426e02c98SAngeloGioacchino Del Regno buffer_mem: tzbuffer@94a00000 { 395b190fb01SKonrad Dybcio reg = <0x0 0x94a00000 0x0 0x100000>; 396b190fb01SKonrad Dybcio no-map; 397b190fb01SKonrad Dybcio }; 398b190fb01SKonrad Dybcio 39926e02c98SAngeloGioacchino Del Regno venus_region: venus@9f800000 { 400b190fb01SKonrad Dybcio reg = <0x0 0x9f800000 0x0 0x800000>; 401b190fb01SKonrad Dybcio no-map; 402b190fb01SKonrad Dybcio }; 403b190fb01SKonrad Dybcio 404b190fb01SKonrad Dybcio adsp_mem: adsp-region@f6000000 { 405b190fb01SKonrad Dybcio reg = <0x0 0xf6000000 0x0 0x800000>; 406b190fb01SKonrad Dybcio no-map; 407b190fb01SKonrad Dybcio }; 408b190fb01SKonrad Dybcio 409b190fb01SKonrad Dybcio qseecom_mem: qseecom-region@f6800000 { 410b190fb01SKonrad Dybcio reg = <0x0 0xf6800000 0x0 0x1400000>; 411b190fb01SKonrad Dybcio no-map; 412b190fb01SKonrad Dybcio }; 413b190fb01SKonrad Dybcio 41426e02c98SAngeloGioacchino Del Regno zap_shader_region: gpu@fed00000 { 41526e02c98SAngeloGioacchino Del Regno compatible = "shared-dma-pool"; 41626e02c98SAngeloGioacchino Del Regno reg = <0x0 0xfed00000 0x0 0xa00000>; 417b190fb01SKonrad Dybcio no-map; 418b190fb01SKonrad Dybcio }; 419b190fb01SKonrad Dybcio }; 420b190fb01SKonrad Dybcio 421b190fb01SKonrad Dybcio rpm-glink { 422b190fb01SKonrad Dybcio compatible = "qcom,glink-rpm"; 423b190fb01SKonrad Dybcio 424b190fb01SKonrad Dybcio interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 425b190fb01SKonrad Dybcio qcom,rpm-msg-ram = <&rpm_msg_ram>; 426b190fb01SKonrad Dybcio mboxes = <&apcs_glb 0>; 427b190fb01SKonrad Dybcio 428b190fb01SKonrad Dybcio rpm_requests: rpm-requests { 429b190fb01SKonrad Dybcio compatible = "qcom,rpm-sdm660"; 430b190fb01SKonrad Dybcio qcom,glink-channels = "rpm_requests"; 431b190fb01SKonrad Dybcio 432b190fb01SKonrad Dybcio rpmcc: clock-controller { 433b190fb01SKonrad Dybcio compatible = "qcom,rpmcc-sdm660", "qcom,rpmcc"; 434b190fb01SKonrad Dybcio #clock-cells = <1>; 435b190fb01SKonrad Dybcio }; 4361ce921aeSKonrad Dybcio 4371ce921aeSKonrad Dybcio rpmpd: power-controller { 4381ce921aeSKonrad Dybcio compatible = "qcom,sdm660-rpmpd"; 4391ce921aeSKonrad Dybcio #power-domain-cells = <1>; 4401ce921aeSKonrad Dybcio operating-points-v2 = <&rpmpd_opp_table>; 4411ce921aeSKonrad Dybcio 4421ce921aeSKonrad Dybcio rpmpd_opp_table: opp-table { 4431ce921aeSKonrad Dybcio compatible = "operating-points-v2"; 4441ce921aeSKonrad Dybcio 4451ce921aeSKonrad Dybcio rpmpd_opp_ret: opp1 { 4461ce921aeSKonrad Dybcio opp-level = <RPM_SMD_LEVEL_RETENTION>; 4471ce921aeSKonrad Dybcio }; 4481ce921aeSKonrad Dybcio 4491ce921aeSKonrad Dybcio rpmpd_opp_ret_plus: opp2 { 4501ce921aeSKonrad Dybcio opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>; 4511ce921aeSKonrad Dybcio }; 4521ce921aeSKonrad Dybcio 4531ce921aeSKonrad Dybcio rpmpd_opp_min_svs: opp3 { 4541ce921aeSKonrad Dybcio opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 4551ce921aeSKonrad Dybcio }; 4561ce921aeSKonrad Dybcio 4571ce921aeSKonrad Dybcio rpmpd_opp_low_svs: opp4 { 4581ce921aeSKonrad Dybcio opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 4591ce921aeSKonrad Dybcio }; 4601ce921aeSKonrad Dybcio 4611ce921aeSKonrad Dybcio rpmpd_opp_svs: opp5 { 4621ce921aeSKonrad Dybcio opp-level = <RPM_SMD_LEVEL_SVS>; 4631ce921aeSKonrad Dybcio }; 4641ce921aeSKonrad Dybcio 4651ce921aeSKonrad Dybcio rpmpd_opp_svs_plus: opp6 { 4661ce921aeSKonrad Dybcio opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 4671ce921aeSKonrad Dybcio }; 4681ce921aeSKonrad Dybcio 4691ce921aeSKonrad Dybcio rpmpd_opp_nom: opp7 { 4701ce921aeSKonrad Dybcio opp-level = <RPM_SMD_LEVEL_NOM>; 4711ce921aeSKonrad Dybcio }; 4721ce921aeSKonrad Dybcio 4731ce921aeSKonrad Dybcio rpmpd_opp_nom_plus: opp8 { 4741ce921aeSKonrad Dybcio opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 4751ce921aeSKonrad Dybcio }; 4761ce921aeSKonrad Dybcio 4771ce921aeSKonrad Dybcio rpmpd_opp_turbo: opp9 { 4781ce921aeSKonrad Dybcio opp-level = <RPM_SMD_LEVEL_TURBO>; 4791ce921aeSKonrad Dybcio }; 4801ce921aeSKonrad Dybcio }; 4811ce921aeSKonrad Dybcio }; 482b190fb01SKonrad Dybcio }; 483b190fb01SKonrad Dybcio }; 484b190fb01SKonrad Dybcio 485b190fb01SKonrad Dybcio smem: smem { 486b190fb01SKonrad Dybcio compatible = "qcom,smem"; 487b190fb01SKonrad Dybcio memory-region = <&smem_region>; 488b190fb01SKonrad Dybcio hwlocks = <&tcsr_mutex 3>; 489b190fb01SKonrad Dybcio }; 490b190fb01SKonrad Dybcio 491c8236767SKonrad Dybcio smp2p-adsp { 492c8236767SKonrad Dybcio compatible = "qcom,smp2p"; 493c8236767SKonrad Dybcio qcom,smem = <443>, <429>; 494c8236767SKonrad Dybcio interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 495c8236767SKonrad Dybcio mboxes = <&apcs_glb 10>; 496c8236767SKonrad Dybcio qcom,local-pid = <0>; 497c8236767SKonrad Dybcio qcom,remote-pid = <2>; 498c8236767SKonrad Dybcio 499c8236767SKonrad Dybcio adsp_smp2p_out: master-kernel { 500c8236767SKonrad Dybcio qcom,entry-name = "master-kernel"; 501c8236767SKonrad Dybcio #qcom,smem-state-cells = <1>; 502c8236767SKonrad Dybcio }; 503c8236767SKonrad Dybcio 504c8236767SKonrad Dybcio adsp_smp2p_in: slave-kernel { 505c8236767SKonrad Dybcio qcom,entry-name = "slave-kernel"; 506c8236767SKonrad Dybcio interrupt-controller; 507c8236767SKonrad Dybcio #interrupt-cells = <2>; 508c8236767SKonrad Dybcio }; 509c8236767SKonrad Dybcio }; 510c8236767SKonrad Dybcio 511c8236767SKonrad Dybcio smp2p-mpss { 512c8236767SKonrad Dybcio compatible = "qcom,smp2p"; 513c8236767SKonrad Dybcio qcom,smem = <435>, <428>; 514c8236767SKonrad Dybcio interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 515c8236767SKonrad Dybcio mboxes = <&apcs_glb 14>; 516c8236767SKonrad Dybcio qcom,local-pid = <0>; 517c8236767SKonrad Dybcio qcom,remote-pid = <1>; 518c8236767SKonrad Dybcio 519c8236767SKonrad Dybcio modem_smp2p_out: master-kernel { 520c8236767SKonrad Dybcio qcom,entry-name = "master-kernel"; 521c8236767SKonrad Dybcio #qcom,smem-state-cells = <1>; 522c8236767SKonrad Dybcio }; 523c8236767SKonrad Dybcio 524c8236767SKonrad Dybcio modem_smp2p_in: slave-kernel { 525c8236767SKonrad Dybcio qcom,entry-name = "slave-kernel"; 526c8236767SKonrad Dybcio interrupt-controller; 527c8236767SKonrad Dybcio #interrupt-cells = <2>; 528c8236767SKonrad Dybcio }; 529c8236767SKonrad Dybcio }; 530c8236767SKonrad Dybcio 531b190fb01SKonrad Dybcio soc { 532b190fb01SKonrad Dybcio #address-cells = <1>; 533b190fb01SKonrad Dybcio #size-cells = <1>; 534b190fb01SKonrad Dybcio ranges = <0 0 0 0xffffffff>; 535b190fb01SKonrad Dybcio compatible = "simple-bus"; 536b190fb01SKonrad Dybcio 537b190fb01SKonrad Dybcio gcc: clock-controller@100000 { 538b190fb01SKonrad Dybcio compatible = "qcom,gcc-sdm630"; 539b190fb01SKonrad Dybcio #clock-cells = <1>; 540b190fb01SKonrad Dybcio #reset-cells = <1>; 541b190fb01SKonrad Dybcio #power-domain-cells = <1>; 542b190fb01SKonrad Dybcio reg = <0x00100000 0x94000>; 543b190fb01SKonrad Dybcio 544b190fb01SKonrad Dybcio clock-names = "xo", "sleep_clk"; 545b190fb01SKonrad Dybcio clocks = <&xo_board>, 546b190fb01SKonrad Dybcio <&sleep_clk>; 547b190fb01SKonrad Dybcio }; 548b190fb01SKonrad Dybcio 549179811beSStephan Gerhold rpm_msg_ram: sram@778000 { 550b190fb01SKonrad Dybcio compatible = "qcom,rpm-msg-ram"; 551b190fb01SKonrad Dybcio reg = <0x00778000 0x7000>; 552b190fb01SKonrad Dybcio }; 553b190fb01SKonrad Dybcio 554b190fb01SKonrad Dybcio qfprom: qfprom@780000 { 555b190fb01SKonrad Dybcio compatible = "qcom,qfprom"; 556b190fb01SKonrad Dybcio reg = <0x00780000 0x621c>; 557b190fb01SKonrad Dybcio #address-cells = <1>; 558b190fb01SKonrad Dybcio #size-cells = <1>; 559142662f8SAngeloGioacchino Del Regno 560142662f8SAngeloGioacchino Del Regno qusb2_hstx_trim: hstx-trim@240 { 561142662f8SAngeloGioacchino Del Regno reg = <0x240 0x1>; 562142662f8SAngeloGioacchino Del Regno bits = <25 3>; 563142662f8SAngeloGioacchino Del Regno }; 564142662f8SAngeloGioacchino Del Regno 565142662f8SAngeloGioacchino Del Regno gpu_speed_bin: gpu-speed-bin@41a0 { 566142662f8SAngeloGioacchino Del Regno reg = <0x41a0 0x1>; 567142662f8SAngeloGioacchino Del Regno bits = <21 7>; 568142662f8SAngeloGioacchino Del Regno }; 569b190fb01SKonrad Dybcio }; 570b190fb01SKonrad Dybcio 571b190fb01SKonrad Dybcio rng: rng@793000 { 572b190fb01SKonrad Dybcio compatible = "qcom,prng-ee"; 573b190fb01SKonrad Dybcio reg = <0x00793000 0x1000>; 574b190fb01SKonrad Dybcio clocks = <&gcc GCC_PRNG_AHB_CLK>; 575b190fb01SKonrad Dybcio clock-names = "core"; 576b190fb01SKonrad Dybcio }; 577b190fb01SKonrad Dybcio 578045547a0SKonrad Dybcio bimc: interconnect@1008000 { 579045547a0SKonrad Dybcio compatible = "qcom,sdm660-bimc"; 580045547a0SKonrad Dybcio reg = <0x01008000 0x78000>; 581045547a0SKonrad Dybcio #interconnect-cells = <1>; 582045547a0SKonrad Dybcio clock-names = "bus", "bus_a"; 583045547a0SKonrad Dybcio clocks = <&rpmcc RPM_SMD_BIMC_CLK>, 584045547a0SKonrad Dybcio <&rpmcc RPM_SMD_BIMC_A_CLK>; 585045547a0SKonrad Dybcio }; 586045547a0SKonrad Dybcio 587b190fb01SKonrad Dybcio restart@10ac000 { 588b190fb01SKonrad Dybcio compatible = "qcom,pshold"; 589b190fb01SKonrad Dybcio reg = <0x010ac000 0x4>; 590b190fb01SKonrad Dybcio }; 591b190fb01SKonrad Dybcio 592045547a0SKonrad Dybcio cnoc: interconnect@1500000 { 593045547a0SKonrad Dybcio compatible = "qcom,sdm660-cnoc"; 594045547a0SKonrad Dybcio reg = <0x01500000 0x10000>; 595045547a0SKonrad Dybcio #interconnect-cells = <1>; 596045547a0SKonrad Dybcio clock-names = "bus", "bus_a"; 597045547a0SKonrad Dybcio clocks = <&rpmcc RPM_SMD_CNOC_CLK>, 598045547a0SKonrad Dybcio <&rpmcc RPM_SMD_CNOC_A_CLK>; 599045547a0SKonrad Dybcio }; 600045547a0SKonrad Dybcio 601045547a0SKonrad Dybcio snoc: interconnect@1626000 { 602045547a0SKonrad Dybcio compatible = "qcom,sdm660-snoc"; 603045547a0SKonrad Dybcio reg = <0x01626000 0x7090>; 604045547a0SKonrad Dybcio #interconnect-cells = <1>; 605045547a0SKonrad Dybcio clock-names = "bus", "bus_a"; 606045547a0SKonrad Dybcio clocks = <&rpmcc RPM_SMD_SNOC_CLK>, 607045547a0SKonrad Dybcio <&rpmcc RPM_SMD_SNOC_A_CLK>; 608045547a0SKonrad Dybcio }; 609045547a0SKonrad Dybcio 610b190fb01SKonrad Dybcio anoc2_smmu: iommu@16c0000 { 611b190fb01SKonrad Dybcio compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2"; 612b190fb01SKonrad Dybcio reg = <0x016c0000 0x40000>; 6136bb717feSAngeloGioacchino Del Regno 6146bb717feSAngeloGioacchino Del Regno assigned-clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>; 6156bb717feSAngeloGioacchino Del Regno assigned-clock-rates = <1000>; 6166bb717feSAngeloGioacchino Del Regno clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>; 6176bb717feSAngeloGioacchino Del Regno clock-names = "bus"; 6186bb717feSAngeloGioacchino Del Regno #global-interrupts = <2>; 619b190fb01SKonrad Dybcio #iommu-cells = <1>; 620b190fb01SKonrad Dybcio 621b190fb01SKonrad Dybcio interrupts = 622b190fb01SKonrad Dybcio <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 623b190fb01SKonrad Dybcio <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 624b190fb01SKonrad Dybcio 625b190fb01SKonrad Dybcio <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>, 626b190fb01SKonrad Dybcio <GIC_SPI 374 IRQ_TYPE_LEVEL_LOW>, 627b190fb01SKonrad Dybcio <GIC_SPI 375 IRQ_TYPE_LEVEL_LOW>, 628b190fb01SKonrad Dybcio <GIC_SPI 376 IRQ_TYPE_LEVEL_LOW>, 629b190fb01SKonrad Dybcio <GIC_SPI 377 IRQ_TYPE_LEVEL_LOW>, 630b190fb01SKonrad Dybcio <GIC_SPI 378 IRQ_TYPE_LEVEL_LOW>, 631b190fb01SKonrad Dybcio <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>, 632b190fb01SKonrad Dybcio <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>, 633b190fb01SKonrad Dybcio <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>, 634b190fb01SKonrad Dybcio <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>, 635b190fb01SKonrad Dybcio <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>, 636b190fb01SKonrad Dybcio <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>, 637b190fb01SKonrad Dybcio <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>, 638b190fb01SKonrad Dybcio <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, 639b190fb01SKonrad Dybcio <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>, 640b190fb01SKonrad Dybcio <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>, 641b190fb01SKonrad Dybcio <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>, 642b190fb01SKonrad Dybcio <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, 643b190fb01SKonrad Dybcio <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, 644b190fb01SKonrad Dybcio <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, 645b190fb01SKonrad Dybcio <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>, 646b190fb01SKonrad Dybcio <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>, 647b190fb01SKonrad Dybcio <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, 648b190fb01SKonrad Dybcio <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>, 649b190fb01SKonrad Dybcio <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>, 650b190fb01SKonrad Dybcio <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>, 651b190fb01SKonrad Dybcio <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, 652b190fb01SKonrad Dybcio <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, 653b190fb01SKonrad Dybcio <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>; 654326407d2SKonrad Dybcio 655326407d2SKonrad Dybcio status = "disabled"; 656b190fb01SKonrad Dybcio }; 657b190fb01SKonrad Dybcio 658045547a0SKonrad Dybcio a2noc: interconnect@1704000 { 659045547a0SKonrad Dybcio compatible = "qcom,sdm660-a2noc"; 660045547a0SKonrad Dybcio reg = <0x01704000 0xc100>; 661045547a0SKonrad Dybcio #interconnect-cells = <1>; 6621878f4b7SShawn Guo clock-names = "bus", 6631878f4b7SShawn Guo "bus_a", 6641878f4b7SShawn Guo "ipa", 6651878f4b7SShawn Guo "ufs_axi", 6661878f4b7SShawn Guo "aggre2_ufs_axi", 6671878f4b7SShawn Guo "aggre2_usb3_axi", 6681878f4b7SShawn Guo "cfg_noc_usb2_axi"; 669045547a0SKonrad Dybcio clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>, 6701878f4b7SShawn Guo <&rpmcc RPM_SMD_AGGR2_NOC_A_CLK>, 6711878f4b7SShawn Guo <&rpmcc RPM_SMD_IPA_CLK>, 6721878f4b7SShawn Guo <&gcc GCC_UFS_AXI_CLK>, 6731878f4b7SShawn Guo <&gcc GCC_AGGRE2_UFS_AXI_CLK>, 6741878f4b7SShawn Guo <&gcc GCC_AGGRE2_USB3_AXI_CLK>, 6751878f4b7SShawn Guo <&gcc GCC_CFG_NOC_USB2_AXI_CLK>; 676045547a0SKonrad Dybcio }; 677045547a0SKonrad Dybcio 678045547a0SKonrad Dybcio mnoc: interconnect@1745000 { 679045547a0SKonrad Dybcio compatible = "qcom,sdm660-mnoc"; 680045547a0SKonrad Dybcio reg = <0x01745000 0xA010>; 681045547a0SKonrad Dybcio #interconnect-cells = <1>; 682045547a0SKonrad Dybcio clock-names = "bus", "bus_a", "iface"; 683045547a0SKonrad Dybcio clocks = <&rpmcc RPM_SMD_MMSSNOC_AXI_CLK>, 684045547a0SKonrad Dybcio <&rpmcc RPM_SMD_MMSSNOC_AXI_CLK_A>, 685045547a0SKonrad Dybcio <&mmcc AHB_CLK_SRC>; 686045547a0SKonrad Dybcio }; 687045547a0SKonrad Dybcio 6887c54b82bSKonrad Dybcio tsens: thermal-sensor@10ae000 { 6897c54b82bSKonrad Dybcio compatible = "qcom,sdm630-tsens", "qcom,tsens-v2"; 6907c54b82bSKonrad Dybcio reg = <0x010ae000 0x1000>, /* TM */ 6917c54b82bSKonrad Dybcio <0x010ad000 0x1000>; /* SROT */ 6927c54b82bSKonrad Dybcio #qcom,sensors = <12>; 6937c54b82bSKonrad Dybcio interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 6947c54b82bSKonrad Dybcio <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>; 6957c54b82bSKonrad Dybcio interrupt-names = "uplow", "critical"; 6967c54b82bSKonrad Dybcio #thermal-sensor-cells = <1>; 6977c54b82bSKonrad Dybcio }; 6987c54b82bSKonrad Dybcio 699b190fb01SKonrad Dybcio tcsr_mutex_regs: syscon@1f40000 { 700b190fb01SKonrad Dybcio compatible = "syscon"; 701adc57d4aSKonrad Dybcio reg = <0x01f40000 0x40000>; 702b190fb01SKonrad Dybcio }; 703b190fb01SKonrad Dybcio 70436a0d47aSAngeloGioacchino Del Regno tlmm: pinctrl@3100000 { 705b190fb01SKonrad Dybcio compatible = "qcom,sdm630-pinctrl"; 70636a0d47aSAngeloGioacchino Del Regno reg = <0x03100000 0x400000>, 70736a0d47aSAngeloGioacchino Del Regno <0x03500000 0x400000>, 70836a0d47aSAngeloGioacchino Del Regno <0x03900000 0x400000>; 70936a0d47aSAngeloGioacchino Del Regno reg-names = "south", "center", "north"; 710b190fb01SKonrad Dybcio interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 711b190fb01SKonrad Dybcio gpio-controller; 71236a0d47aSAngeloGioacchino Del Regno gpio-ranges = <&tlmm 0 0 114>; 71336a0d47aSAngeloGioacchino Del Regno #gpio-cells = <2>; 714b190fb01SKonrad Dybcio interrupt-controller; 71536a0d47aSAngeloGioacchino Del Regno #interrupt-cells = <2>; 716b190fb01SKonrad Dybcio 717b190fb01SKonrad Dybcio blsp1_uart1_default: blsp1-uart1-default { 718b190fb01SKonrad Dybcio pins = "gpio0", "gpio1", "gpio2", "gpio3"; 719b190fb01SKonrad Dybcio drive-strength = <2>; 720b190fb01SKonrad Dybcio bias-disable; 721b190fb01SKonrad Dybcio }; 722b190fb01SKonrad Dybcio 723b190fb01SKonrad Dybcio blsp1_uart1_sleep: blsp1-uart1-sleep { 724b190fb01SKonrad Dybcio pins = "gpio0", "gpio1", "gpio2", "gpio3"; 725b190fb01SKonrad Dybcio drive-strength = <2>; 726b190fb01SKonrad Dybcio bias-disable; 727b190fb01SKonrad Dybcio }; 728b190fb01SKonrad Dybcio 729b190fb01SKonrad Dybcio blsp1_uart2_default: blsp1-uart2-default { 730b190fb01SKonrad Dybcio pins = "gpio4", "gpio5"; 731b190fb01SKonrad Dybcio drive-strength = <2>; 732b190fb01SKonrad Dybcio bias-disable; 733b190fb01SKonrad Dybcio }; 734b190fb01SKonrad Dybcio 73536a0d47aSAngeloGioacchino Del Regno blsp2_uart1_default: blsp2-uart1-active { 73636a0d47aSAngeloGioacchino Del Regno tx-rts { 73736a0d47aSAngeloGioacchino Del Regno pins = "gpio16", "gpio19"; 73836a0d47aSAngeloGioacchino Del Regno function = "blsp_uart5"; 739b190fb01SKonrad Dybcio drive-strength = <2>; 740b190fb01SKonrad Dybcio bias-disable; 741b190fb01SKonrad Dybcio }; 742b190fb01SKonrad Dybcio 74336a0d47aSAngeloGioacchino Del Regno rx { 74436a0d47aSAngeloGioacchino Del Regno /* 74536a0d47aSAngeloGioacchino Del Regno * Avoid garbage data while BT module 74636a0d47aSAngeloGioacchino Del Regno * is powered off or not driving signal 74736a0d47aSAngeloGioacchino Del Regno */ 74836a0d47aSAngeloGioacchino Del Regno pins = "gpio17"; 74936a0d47aSAngeloGioacchino Del Regno function = "blsp_uart5"; 750b190fb01SKonrad Dybcio drive-strength = <2>; 751b190fb01SKonrad Dybcio bias-pull-up; 752b190fb01SKonrad Dybcio }; 753b190fb01SKonrad Dybcio 75436a0d47aSAngeloGioacchino Del Regno cts { 75536a0d47aSAngeloGioacchino Del Regno /* Match the pull of the BT module */ 75636a0d47aSAngeloGioacchino Del Regno pins = "gpio18"; 75736a0d47aSAngeloGioacchino Del Regno function = "blsp_uart5"; 758b190fb01SKonrad Dybcio drive-strength = <2>; 75936a0d47aSAngeloGioacchino Del Regno bias-pull-down; 76036a0d47aSAngeloGioacchino Del Regno }; 761b190fb01SKonrad Dybcio }; 762b190fb01SKonrad Dybcio 76336a0d47aSAngeloGioacchino Del Regno blsp2_uart1_sleep: blsp2-uart1-sleep { 76436a0d47aSAngeloGioacchino Del Regno tx { 76536a0d47aSAngeloGioacchino Del Regno pins = "gpio16"; 76636a0d47aSAngeloGioacchino Del Regno function = "gpio"; 76736a0d47aSAngeloGioacchino Del Regno drive-strength = <2>; 76836a0d47aSAngeloGioacchino Del Regno bias-pull-up; 76936a0d47aSAngeloGioacchino Del Regno }; 77036a0d47aSAngeloGioacchino Del Regno 77136a0d47aSAngeloGioacchino Del Regno rx-cts-rts { 77236a0d47aSAngeloGioacchino Del Regno pins = "gpio17", "gpio18", "gpio19"; 77336a0d47aSAngeloGioacchino Del Regno function = "gpio"; 774b190fb01SKonrad Dybcio drive-strength = <2>; 775b190fb01SKonrad Dybcio bias-no-pull; 776b190fb01SKonrad Dybcio }; 777b190fb01SKonrad Dybcio }; 778b190fb01SKonrad Dybcio 779b190fb01SKonrad Dybcio i2c1_default: i2c1-default { 780b190fb01SKonrad Dybcio pins = "gpio2", "gpio3"; 781536f4428SKonrad Dybcio function = "blsp_i2c1"; 782b190fb01SKonrad Dybcio drive-strength = <2>; 783b190fb01SKonrad Dybcio bias-disable; 784b190fb01SKonrad Dybcio }; 785b190fb01SKonrad Dybcio 786b190fb01SKonrad Dybcio i2c1_sleep: i2c1-sleep { 787b190fb01SKonrad Dybcio pins = "gpio2", "gpio3"; 788536f4428SKonrad Dybcio function = "blsp_i2c1"; 789b190fb01SKonrad Dybcio drive-strength = <2>; 790b190fb01SKonrad Dybcio bias-pull-up; 791b190fb01SKonrad Dybcio }; 792b190fb01SKonrad Dybcio 793b190fb01SKonrad Dybcio i2c2_default: i2c2-default { 794b190fb01SKonrad Dybcio pins = "gpio6", "gpio7"; 795536f4428SKonrad Dybcio function = "blsp_i2c2"; 796b190fb01SKonrad Dybcio drive-strength = <2>; 797b190fb01SKonrad Dybcio bias-disable; 798b190fb01SKonrad Dybcio }; 799b190fb01SKonrad Dybcio 800b190fb01SKonrad Dybcio i2c2_sleep: i2c2-sleep { 801b190fb01SKonrad Dybcio pins = "gpio6", "gpio7"; 802536f4428SKonrad Dybcio function = "blsp_i2c2"; 803b190fb01SKonrad Dybcio drive-strength = <2>; 804b190fb01SKonrad Dybcio bias-pull-up; 805b190fb01SKonrad Dybcio }; 806b190fb01SKonrad Dybcio 807b190fb01SKonrad Dybcio i2c3_default: i2c3-default { 808b190fb01SKonrad Dybcio pins = "gpio10", "gpio11"; 809536f4428SKonrad Dybcio function = "blsp_i2c3"; 810b190fb01SKonrad Dybcio drive-strength = <2>; 811b190fb01SKonrad Dybcio bias-disable; 812b190fb01SKonrad Dybcio }; 813b190fb01SKonrad Dybcio 814b190fb01SKonrad Dybcio i2c3_sleep: i2c3-sleep { 815b190fb01SKonrad Dybcio pins = "gpio10", "gpio11"; 816536f4428SKonrad Dybcio function = "blsp_i2c3"; 817b190fb01SKonrad Dybcio drive-strength = <2>; 818b190fb01SKonrad Dybcio bias-pull-up; 819b190fb01SKonrad Dybcio }; 820b190fb01SKonrad Dybcio 821b190fb01SKonrad Dybcio i2c4_default: i2c4-default { 822b190fb01SKonrad Dybcio pins = "gpio14", "gpio15"; 823536f4428SKonrad Dybcio function = "blsp_i2c4"; 824b190fb01SKonrad Dybcio drive-strength = <2>; 825b190fb01SKonrad Dybcio bias-disable; 826b190fb01SKonrad Dybcio }; 827b190fb01SKonrad Dybcio 828b190fb01SKonrad Dybcio i2c4_sleep: i2c4-sleep { 829b190fb01SKonrad Dybcio pins = "gpio14", "gpio15"; 830536f4428SKonrad Dybcio function = "blsp_i2c4"; 831b190fb01SKonrad Dybcio drive-strength = <2>; 832b190fb01SKonrad Dybcio bias-pull-up; 833b190fb01SKonrad Dybcio }; 834b190fb01SKonrad Dybcio 835b190fb01SKonrad Dybcio i2c5_default: i2c5-default { 836b190fb01SKonrad Dybcio pins = "gpio18", "gpio19"; 837536f4428SKonrad Dybcio function = "blsp_i2c5"; 838b190fb01SKonrad Dybcio drive-strength = <2>; 839b190fb01SKonrad Dybcio bias-disable; 840b190fb01SKonrad Dybcio }; 841b190fb01SKonrad Dybcio 842b190fb01SKonrad Dybcio i2c5_sleep: i2c5-sleep { 843b190fb01SKonrad Dybcio pins = "gpio18", "gpio19"; 844536f4428SKonrad Dybcio function = "blsp_i2c5"; 845b190fb01SKonrad Dybcio drive-strength = <2>; 846b190fb01SKonrad Dybcio bias-pull-up; 847b190fb01SKonrad Dybcio }; 848b190fb01SKonrad Dybcio 849b190fb01SKonrad Dybcio i2c6_default: i2c6-default { 850b190fb01SKonrad Dybcio pins = "gpio22", "gpio23"; 851536f4428SKonrad Dybcio function = "blsp_i2c6"; 852b190fb01SKonrad Dybcio drive-strength = <2>; 853b190fb01SKonrad Dybcio bias-disable; 854b190fb01SKonrad Dybcio }; 855b190fb01SKonrad Dybcio 856b190fb01SKonrad Dybcio i2c6_sleep: i2c6-sleep { 857b190fb01SKonrad Dybcio pins = "gpio22", "gpio23"; 858536f4428SKonrad Dybcio function = "blsp_i2c6"; 859b190fb01SKonrad Dybcio drive-strength = <2>; 860b190fb01SKonrad Dybcio bias-pull-up; 861b190fb01SKonrad Dybcio }; 862b190fb01SKonrad Dybcio 863b190fb01SKonrad Dybcio i2c7_default: i2c7-default { 864b190fb01SKonrad Dybcio pins = "gpio26", "gpio27"; 865536f4428SKonrad Dybcio function = "blsp_i2c7"; 866b190fb01SKonrad Dybcio drive-strength = <2>; 867b190fb01SKonrad Dybcio bias-disable; 868b190fb01SKonrad Dybcio }; 869b190fb01SKonrad Dybcio 870b190fb01SKonrad Dybcio i2c7_sleep: i2c7-sleep { 871b190fb01SKonrad Dybcio pins = "gpio26", "gpio27"; 872536f4428SKonrad Dybcio function = "blsp_i2c7"; 873b190fb01SKonrad Dybcio drive-strength = <2>; 874b190fb01SKonrad Dybcio bias-pull-up; 875b190fb01SKonrad Dybcio }; 876b190fb01SKonrad Dybcio 877b190fb01SKonrad Dybcio i2c8_default: i2c8-default { 878b190fb01SKonrad Dybcio pins = "gpio30", "gpio31"; 879536f4428SKonrad Dybcio function = "blsp_i2c8"; 880b190fb01SKonrad Dybcio drive-strength = <2>; 881b190fb01SKonrad Dybcio bias-disable; 882b190fb01SKonrad Dybcio }; 883b190fb01SKonrad Dybcio 884b190fb01SKonrad Dybcio i2c8_sleep: i2c8-sleep { 885b190fb01SKonrad Dybcio pins = "gpio30", "gpio31"; 886536f4428SKonrad Dybcio function = "blsp_i2c8"; 887b190fb01SKonrad Dybcio drive-strength = <2>; 888b190fb01SKonrad Dybcio bias-pull-up; 889b190fb01SKonrad Dybcio }; 890b190fb01SKonrad Dybcio 891f3d5d3ccSAngeloGioacchino Del Regno cci0_default: cci0_default { 892f3d5d3ccSAngeloGioacchino Del Regno pinmux { 893f3d5d3ccSAngeloGioacchino Del Regno pins = "gpio36","gpio37"; 894f3d5d3ccSAngeloGioacchino Del Regno function = "cci_i2c"; 895f3d5d3ccSAngeloGioacchino Del Regno }; 896f3d5d3ccSAngeloGioacchino Del Regno 897f3d5d3ccSAngeloGioacchino Del Regno pinconf { 898f3d5d3ccSAngeloGioacchino Del Regno pins = "gpio36","gpio37"; 899f3d5d3ccSAngeloGioacchino Del Regno bias-pull-up; 900f3d5d3ccSAngeloGioacchino Del Regno drive-strength = <2>; 901f3d5d3ccSAngeloGioacchino Del Regno }; 902f3d5d3ccSAngeloGioacchino Del Regno }; 903f3d5d3ccSAngeloGioacchino Del Regno 904f3d5d3ccSAngeloGioacchino Del Regno cci1_default: cci1_default { 905f3d5d3ccSAngeloGioacchino Del Regno pinmux { 906f3d5d3ccSAngeloGioacchino Del Regno pins = "gpio38","gpio39"; 907f3d5d3ccSAngeloGioacchino Del Regno function = "cci_i2c"; 908f3d5d3ccSAngeloGioacchino Del Regno }; 909f3d5d3ccSAngeloGioacchino Del Regno 910f3d5d3ccSAngeloGioacchino Del Regno pinconf { 911f3d5d3ccSAngeloGioacchino Del Regno pins = "gpio38","gpio39"; 912f3d5d3ccSAngeloGioacchino Del Regno bias-pull-up; 913f3d5d3ccSAngeloGioacchino Del Regno drive-strength = <2>; 914f3d5d3ccSAngeloGioacchino Del Regno }; 915f3d5d3ccSAngeloGioacchino Del Regno }; 916f3d5d3ccSAngeloGioacchino Del Regno 91736a0d47aSAngeloGioacchino Del Regno sdc1_state_on: sdc1-on { 91836a0d47aSAngeloGioacchino Del Regno clk { 919b190fb01SKonrad Dybcio pins = "sdc1_clk"; 920b190fb01SKonrad Dybcio bias-disable; 921b190fb01SKonrad Dybcio drive-strength = <16>; 922b190fb01SKonrad Dybcio }; 923b190fb01SKonrad Dybcio 92436a0d47aSAngeloGioacchino Del Regno cmd { 925b190fb01SKonrad Dybcio pins = "sdc1_cmd"; 926b190fb01SKonrad Dybcio bias-pull-up; 927b190fb01SKonrad Dybcio drive-strength = <10>; 928b190fb01SKonrad Dybcio }; 929b190fb01SKonrad Dybcio 93036a0d47aSAngeloGioacchino Del Regno data { 93136a0d47aSAngeloGioacchino Del Regno pins = "sdc1_data"; 93236a0d47aSAngeloGioacchino Del Regno bias-pull-up; 93336a0d47aSAngeloGioacchino Del Regno drive-strength = <10>; 93436a0d47aSAngeloGioacchino Del Regno }; 93536a0d47aSAngeloGioacchino Del Regno 93636a0d47aSAngeloGioacchino Del Regno rclk { 93736a0d47aSAngeloGioacchino Del Regno pins = "sdc1_rclk"; 93836a0d47aSAngeloGioacchino Del Regno bias-pull-down; 93936a0d47aSAngeloGioacchino Del Regno }; 94036a0d47aSAngeloGioacchino Del Regno }; 94136a0d47aSAngeloGioacchino Del Regno 94236a0d47aSAngeloGioacchino Del Regno sdc1_state_off: sdc1-off { 94336a0d47aSAngeloGioacchino Del Regno clk { 94436a0d47aSAngeloGioacchino Del Regno pins = "sdc1_clk"; 94536a0d47aSAngeloGioacchino Del Regno bias-disable; 94636a0d47aSAngeloGioacchino Del Regno drive-strength = <2>; 94736a0d47aSAngeloGioacchino Del Regno }; 94836a0d47aSAngeloGioacchino Del Regno 94936a0d47aSAngeloGioacchino Del Regno cmd { 950b190fb01SKonrad Dybcio pins = "sdc1_cmd"; 951b190fb01SKonrad Dybcio bias-pull-up; 952b190fb01SKonrad Dybcio drive-strength = <2>; 953b190fb01SKonrad Dybcio }; 954b190fb01SKonrad Dybcio 95536a0d47aSAngeloGioacchino Del Regno data { 956b190fb01SKonrad Dybcio pins = "sdc1_data"; 957b190fb01SKonrad Dybcio bias-pull-up; 958b190fb01SKonrad Dybcio drive-strength = <2>; 959b190fb01SKonrad Dybcio }; 960b190fb01SKonrad Dybcio 96136a0d47aSAngeloGioacchino Del Regno rclk { 962b190fb01SKonrad Dybcio pins = "sdc1_rclk"; 963b190fb01SKonrad Dybcio bias-pull-down; 964b190fb01SKonrad Dybcio }; 96536a0d47aSAngeloGioacchino Del Regno }; 966b190fb01SKonrad Dybcio 96736a0d47aSAngeloGioacchino Del Regno sdc2_state_on: sdc2-on { 96836a0d47aSAngeloGioacchino Del Regno clk { 96936a0d47aSAngeloGioacchino Del Regno pins = "sdc2_clk"; 97036a0d47aSAngeloGioacchino Del Regno bias-disable; 97136a0d47aSAngeloGioacchino Del Regno drive-strength = <16>; 97236a0d47aSAngeloGioacchino Del Regno }; 97336a0d47aSAngeloGioacchino Del Regno 97436a0d47aSAngeloGioacchino Del Regno cmd { 97536a0d47aSAngeloGioacchino Del Regno pins = "sdc2_cmd"; 97636a0d47aSAngeloGioacchino Del Regno bias-pull-up; 97736a0d47aSAngeloGioacchino Del Regno drive-strength = <10>; 97836a0d47aSAngeloGioacchino Del Regno }; 97936a0d47aSAngeloGioacchino Del Regno 98036a0d47aSAngeloGioacchino Del Regno data { 98136a0d47aSAngeloGioacchino Del Regno pins = "sdc2_data"; 98236a0d47aSAngeloGioacchino Del Regno bias-pull-up; 98336a0d47aSAngeloGioacchino Del Regno drive-strength = <10>; 98436a0d47aSAngeloGioacchino Del Regno }; 98536a0d47aSAngeloGioacchino Del Regno 98636a0d47aSAngeloGioacchino Del Regno sd-cd { 98736a0d47aSAngeloGioacchino Del Regno pins = "gpio54"; 98836a0d47aSAngeloGioacchino Del Regno bias-pull-up; 98936a0d47aSAngeloGioacchino Del Regno drive-strength = <2>; 99036a0d47aSAngeloGioacchino Del Regno }; 99136a0d47aSAngeloGioacchino Del Regno }; 99236a0d47aSAngeloGioacchino Del Regno 99336a0d47aSAngeloGioacchino Del Regno sdc2_state_off: sdc2-off { 99436a0d47aSAngeloGioacchino Del Regno clk { 99536a0d47aSAngeloGioacchino Del Regno pins = "sdc2_clk"; 99636a0d47aSAngeloGioacchino Del Regno bias-disable; 99736a0d47aSAngeloGioacchino Del Regno drive-strength = <2>; 99836a0d47aSAngeloGioacchino Del Regno }; 99936a0d47aSAngeloGioacchino Del Regno 100036a0d47aSAngeloGioacchino Del Regno cmd { 100136a0d47aSAngeloGioacchino Del Regno pins = "sdc2_cmd"; 100236a0d47aSAngeloGioacchino Del Regno bias-pull-up; 100336a0d47aSAngeloGioacchino Del Regno drive-strength = <2>; 100436a0d47aSAngeloGioacchino Del Regno }; 100536a0d47aSAngeloGioacchino Del Regno 100636a0d47aSAngeloGioacchino Del Regno data { 100736a0d47aSAngeloGioacchino Del Regno pins = "sdc2_data"; 100836a0d47aSAngeloGioacchino Del Regno bias-pull-up; 100936a0d47aSAngeloGioacchino Del Regno drive-strength = <2>; 101036a0d47aSAngeloGioacchino Del Regno }; 101136a0d47aSAngeloGioacchino Del Regno 101236a0d47aSAngeloGioacchino Del Regno sd-cd { 101336a0d47aSAngeloGioacchino Del Regno pins = "gpio54"; 101436a0d47aSAngeloGioacchino Del Regno bias-disable; 101536a0d47aSAngeloGioacchino Del Regno drive-strength = <2>; 101636a0d47aSAngeloGioacchino Del Regno }; 1017b190fb01SKonrad Dybcio }; 1018b190fb01SKonrad Dybcio }; 1019b190fb01SKonrad Dybcio 10205cf69dcbSAngeloGioacchino Del Regno adreno_gpu: gpu@5000000 { 10215cf69dcbSAngeloGioacchino Del Regno compatible = "qcom,adreno-508.0", "qcom,adreno"; 10225cf69dcbSAngeloGioacchino Del Regno 10235cf69dcbSAngeloGioacchino Del Regno reg = <0x05000000 0x40000>; 10245cf69dcbSAngeloGioacchino Del Regno reg-names = "kgsl_3d0_reg_memory"; 10255cf69dcbSAngeloGioacchino Del Regno 10265cf69dcbSAngeloGioacchino Del Regno interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>; 10275cf69dcbSAngeloGioacchino Del Regno 10285cf69dcbSAngeloGioacchino Del Regno clocks = <&gcc GCC_GPU_CFG_AHB_CLK>, 10295cf69dcbSAngeloGioacchino Del Regno <&gpucc GPUCC_RBBMTIMER_CLK>, 10305cf69dcbSAngeloGioacchino Del Regno <&gcc GCC_BIMC_GFX_CLK>, 10315cf69dcbSAngeloGioacchino Del Regno <&gcc GCC_GPU_BIMC_GFX_CLK>, 10325cf69dcbSAngeloGioacchino Del Regno <&gpucc GPUCC_RBCPR_CLK>, 10335cf69dcbSAngeloGioacchino Del Regno <&gpucc GPUCC_GFX3D_CLK>; 10345cf69dcbSAngeloGioacchino Del Regno 10355cf69dcbSAngeloGioacchino Del Regno clock-names = "iface", 10365cf69dcbSAngeloGioacchino Del Regno "rbbmtimer", 10375cf69dcbSAngeloGioacchino Del Regno "mem", 10385cf69dcbSAngeloGioacchino Del Regno "mem_iface", 10395cf69dcbSAngeloGioacchino Del Regno "rbcpr", 10405cf69dcbSAngeloGioacchino Del Regno "core"; 10415cf69dcbSAngeloGioacchino Del Regno 10425cf69dcbSAngeloGioacchino Del Regno power-domains = <&rpmpd SDM660_VDDMX>; 10435cf69dcbSAngeloGioacchino Del Regno iommus = <&kgsl_smmu 0>; 10445cf69dcbSAngeloGioacchino Del Regno 10455cf69dcbSAngeloGioacchino Del Regno nvmem-cells = <&gpu_speed_bin>; 10465cf69dcbSAngeloGioacchino Del Regno nvmem-cell-names = "speed_bin"; 10475cf69dcbSAngeloGioacchino Del Regno 10485cf69dcbSAngeloGioacchino Del Regno interconnects = <&gnoc 1 &bimc 5>; 10495cf69dcbSAngeloGioacchino Del Regno interconnect-names = "gfx-mem"; 10505cf69dcbSAngeloGioacchino Del Regno 10515cf69dcbSAngeloGioacchino Del Regno operating-points-v2 = <&gpu_sdm630_opp_table>; 10525cf69dcbSAngeloGioacchino Del Regno 10531c047919SDmitry Baryshkov status = "disabled"; 10541c047919SDmitry Baryshkov 10555cf69dcbSAngeloGioacchino Del Regno gpu_sdm630_opp_table: opp-table { 10565cf69dcbSAngeloGioacchino Del Regno compatible = "operating-points-v2"; 10575cf69dcbSAngeloGioacchino Del Regno opp-775000000 { 10585cf69dcbSAngeloGioacchino Del Regno opp-hz = /bits/ 64 <775000000>; 10595cf69dcbSAngeloGioacchino Del Regno opp-level = <RPM_SMD_LEVEL_TURBO>; 10605cf69dcbSAngeloGioacchino Del Regno opp-peak-kBps = <5412000>; 10615cf69dcbSAngeloGioacchino Del Regno opp-supported-hw = <0xA2>; 10625cf69dcbSAngeloGioacchino Del Regno }; 10635cf69dcbSAngeloGioacchino Del Regno opp-647000000 { 10645cf69dcbSAngeloGioacchino Del Regno opp-hz = /bits/ 64 <647000000>; 10655cf69dcbSAngeloGioacchino Del Regno opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 10665cf69dcbSAngeloGioacchino Del Regno opp-peak-kBps = <4068000>; 10675cf69dcbSAngeloGioacchino Del Regno opp-supported-hw = <0xFF>; 10685cf69dcbSAngeloGioacchino Del Regno }; 10695cf69dcbSAngeloGioacchino Del Regno opp-588000000 { 10705cf69dcbSAngeloGioacchino Del Regno opp-hz = /bits/ 64 <588000000>; 10715cf69dcbSAngeloGioacchino Del Regno opp-level = <RPM_SMD_LEVEL_NOM>; 10725cf69dcbSAngeloGioacchino Del Regno opp-peak-kBps = <3072000>; 10735cf69dcbSAngeloGioacchino Del Regno opp-supported-hw = <0xFF>; 10745cf69dcbSAngeloGioacchino Del Regno }; 10755cf69dcbSAngeloGioacchino Del Regno opp-465000000 { 10765cf69dcbSAngeloGioacchino Del Regno opp-hz = /bits/ 64 <465000000>; 10775cf69dcbSAngeloGioacchino Del Regno opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 10785cf69dcbSAngeloGioacchino Del Regno opp-peak-kBps = <2724000>; 10795cf69dcbSAngeloGioacchino Del Regno opp-supported-hw = <0xFF>; 10805cf69dcbSAngeloGioacchino Del Regno }; 10815cf69dcbSAngeloGioacchino Del Regno opp-370000000 { 10825cf69dcbSAngeloGioacchino Del Regno opp-hz = /bits/ 64 <370000000>; 10835cf69dcbSAngeloGioacchino Del Regno opp-level = <RPM_SMD_LEVEL_SVS>; 10845cf69dcbSAngeloGioacchino Del Regno opp-peak-kBps = <2188000>; 10855cf69dcbSAngeloGioacchino Del Regno opp-supported-hw = <0xFF>; 10865cf69dcbSAngeloGioacchino Del Regno }; 10875cf69dcbSAngeloGioacchino Del Regno opp-240000000 { 10885cf69dcbSAngeloGioacchino Del Regno opp-hz = /bits/ 64 <240000000>; 10895cf69dcbSAngeloGioacchino Del Regno opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 10905cf69dcbSAngeloGioacchino Del Regno opp-peak-kBps = <1648000>; 10915cf69dcbSAngeloGioacchino Del Regno opp-supported-hw = <0xFF>; 10925cf69dcbSAngeloGioacchino Del Regno }; 10935cf69dcbSAngeloGioacchino Del Regno opp-160000000 { 10945cf69dcbSAngeloGioacchino Del Regno opp-hz = /bits/ 64 <160000000>; 10955cf69dcbSAngeloGioacchino Del Regno opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 10965cf69dcbSAngeloGioacchino Del Regno opp-peak-kBps = <1200000>; 10975cf69dcbSAngeloGioacchino Del Regno opp-supported-hw = <0xFF>; 10985cf69dcbSAngeloGioacchino Del Regno }; 10995cf69dcbSAngeloGioacchino Del Regno }; 11005cf69dcbSAngeloGioacchino Del Regno }; 11015cf69dcbSAngeloGioacchino Del Regno 1102b190fb01SKonrad Dybcio kgsl_smmu: iommu@5040000 { 1103056d4ff8SAngeloGioacchino Del Regno compatible = "qcom,sdm630-smmu-v2", 1104056d4ff8SAngeloGioacchino Del Regno "qcom,adreno-smmu", "qcom,smmu-v2"; 1105b190fb01SKonrad Dybcio reg = <0x05040000 0x10000>; 11066bb717feSAngeloGioacchino Del Regno 11076bb717feSAngeloGioacchino Del Regno /* 11086bb717feSAngeloGioacchino Del Regno * GX GDSC parent is CX. We need to bring up CX for SMMU 11096bb717feSAngeloGioacchino Del Regno * but we need both up for Adreno. On the other hand, we 11106bb717feSAngeloGioacchino Del Regno * need to manage the GX rpmpd domain in the adreno driver. 11116bb717feSAngeloGioacchino Del Regno * Enable CX/GX GDSCs here so that we can manage just the GX 11126bb717feSAngeloGioacchino Del Regno * RPM Power Domain in the Adreno driver. 11136bb717feSAngeloGioacchino Del Regno */ 11146bb717feSAngeloGioacchino Del Regno power-domains = <&gpucc GPU_GX_GDSC>; 11156bb717feSAngeloGioacchino Del Regno clocks = <&gcc GCC_GPU_CFG_AHB_CLK>, 11166bb717feSAngeloGioacchino Del Regno <&gcc GCC_BIMC_GFX_CLK>, 11176bb717feSAngeloGioacchino Del Regno <&gcc GCC_GPU_BIMC_GFX_CLK>; 11186bb717feSAngeloGioacchino Del Regno clock-names = "iface", "mem", "mem_iface"; 11196bb717feSAngeloGioacchino Del Regno #global-interrupts = <2>; 1120b190fb01SKonrad Dybcio #iommu-cells = <1>; 1121b190fb01SKonrad Dybcio 1122b190fb01SKonrad Dybcio interrupts = 1123b190fb01SKonrad Dybcio <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 1124b190fb01SKonrad Dybcio <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 1125b190fb01SKonrad Dybcio 1126b190fb01SKonrad Dybcio <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 1127b190fb01SKonrad Dybcio <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 1128b190fb01SKonrad Dybcio <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 1129b190fb01SKonrad Dybcio <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 1130b190fb01SKonrad Dybcio <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1131b190fb01SKonrad Dybcio <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1132b190fb01SKonrad Dybcio <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>, 1133b190fb01SKonrad Dybcio <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>; 1134326407d2SKonrad Dybcio 1135326407d2SKonrad Dybcio status = "disabled"; 1136b190fb01SKonrad Dybcio }; 1137b190fb01SKonrad Dybcio 1138a64fa0e2SAngeloGioacchino Del Regno gpucc: clock-controller@5065000 { 1139a64fa0e2SAngeloGioacchino Del Regno compatible = "qcom,gpucc-sdm630"; 1140a64fa0e2SAngeloGioacchino Del Regno #clock-cells = <1>; 1141a64fa0e2SAngeloGioacchino Del Regno #reset-cells = <1>; 1142a64fa0e2SAngeloGioacchino Del Regno #power-domain-cells = <1>; 1143a64fa0e2SAngeloGioacchino Del Regno reg = <0x05065000 0x9038>; 1144a64fa0e2SAngeloGioacchino Del Regno 1145a64fa0e2SAngeloGioacchino Del Regno clocks = <&xo_board>, 1146a64fa0e2SAngeloGioacchino Del Regno <&gcc GCC_GPU_GPLL0_CLK>, 1147a64fa0e2SAngeloGioacchino Del Regno <&gcc GCC_GPU_GPLL0_DIV_CLK>; 1148a64fa0e2SAngeloGioacchino Del Regno clock-names = "xo", 1149a64fa0e2SAngeloGioacchino Del Regno "gcc_gpu_gpll0_clk", 1150a64fa0e2SAngeloGioacchino Del Regno "gcc_gpu_gpll0_div_clk"; 1151a64fa0e2SAngeloGioacchino Del Regno status = "disabled"; 1152a64fa0e2SAngeloGioacchino Del Regno }; 1153a64fa0e2SAngeloGioacchino Del Regno 1154b190fb01SKonrad Dybcio lpass_smmu: iommu@5100000 { 1155b190fb01SKonrad Dybcio compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2"; 1156b190fb01SKonrad Dybcio reg = <0x05100000 0x40000>; 1157b190fb01SKonrad Dybcio #iommu-cells = <1>; 1158b190fb01SKonrad Dybcio 1159b190fb01SKonrad Dybcio #global-interrupts = <2>; 1160b190fb01SKonrad Dybcio interrupts = 1161b190fb01SKonrad Dybcio <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 1162b190fb01SKonrad Dybcio <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 1163b190fb01SKonrad Dybcio 1164b190fb01SKonrad Dybcio <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, 1165b190fb01SKonrad Dybcio <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>, 1166b190fb01SKonrad Dybcio <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>, 1167b190fb01SKonrad Dybcio <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 1168b190fb01SKonrad Dybcio <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 1169b190fb01SKonrad Dybcio <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 1170b190fb01SKonrad Dybcio <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 1171b190fb01SKonrad Dybcio <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 1172b190fb01SKonrad Dybcio <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 1173b190fb01SKonrad Dybcio <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 1174b190fb01SKonrad Dybcio <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 1175b190fb01SKonrad Dybcio <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 1176b190fb01SKonrad Dybcio <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 1177b190fb01SKonrad Dybcio <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, 1178b190fb01SKonrad Dybcio <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>, 1179b190fb01SKonrad Dybcio <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 1180b190fb01SKonrad Dybcio <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>; 1181326407d2SKonrad Dybcio 1182326407d2SKonrad Dybcio status = "disabled"; 1183b190fb01SKonrad Dybcio }; 1184b190fb01SKonrad Dybcio 1185290bc684SMaulik Shah sram@290000 { 1186290bc684SMaulik Shah compatible = "qcom,rpm-stats"; 1187290bc684SMaulik Shah reg = <0x00290000 0x10000>; 1188290bc684SMaulik Shah }; 1189290bc684SMaulik Shah 1190b190fb01SKonrad Dybcio spmi_bus: spmi@800f000 { 1191b190fb01SKonrad Dybcio compatible = "qcom,spmi-pmic-arb"; 1192b190fb01SKonrad Dybcio reg = <0x0800f000 0x1000>, 1193b190fb01SKonrad Dybcio <0x08400000 0x1000000>, 1194b190fb01SKonrad Dybcio <0x09400000 0x1000000>, 1195b190fb01SKonrad Dybcio <0x0a400000 0x220000>, 1196b190fb01SKonrad Dybcio <0x0800a000 0x3000>; 1197b190fb01SKonrad Dybcio reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1198b190fb01SKonrad Dybcio interrupt-names = "periph_irq"; 1199b190fb01SKonrad Dybcio interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>; 1200b190fb01SKonrad Dybcio qcom,ee = <0>; 1201b190fb01SKonrad Dybcio qcom,channel = <0>; 1202b190fb01SKonrad Dybcio #address-cells = <2>; 1203b190fb01SKonrad Dybcio #size-cells = <0>; 1204b190fb01SKonrad Dybcio interrupt-controller; 1205b190fb01SKonrad Dybcio #interrupt-cells = <4>; 1206b190fb01SKonrad Dybcio cell-index = <0>; 1207b190fb01SKonrad Dybcio }; 1208b190fb01SKonrad Dybcio 1209c65a4ed2SKonrad Dybcio usb3: usb@a8f8800 { 1210c65a4ed2SKonrad Dybcio compatible = "qcom,sdm660-dwc3", "qcom,dwc3"; 1211c65a4ed2SKonrad Dybcio reg = <0x0a8f8800 0x400>; 1212c65a4ed2SKonrad Dybcio status = "disabled"; 1213c65a4ed2SKonrad Dybcio #address-cells = <1>; 1214c65a4ed2SKonrad Dybcio #size-cells = <1>; 1215c65a4ed2SKonrad Dybcio ranges; 1216c65a4ed2SKonrad Dybcio 1217c65a4ed2SKonrad Dybcio clocks = <&gcc GCC_CFG_NOC_USB3_AXI_CLK>, 1218c65a4ed2SKonrad Dybcio <&gcc GCC_USB30_MASTER_CLK>, 1219c65a4ed2SKonrad Dybcio <&gcc GCC_AGGRE2_USB3_AXI_CLK>, 12208d5fd4e4SKrzysztof Kozlowski <&gcc GCC_USB30_SLEEP_CLK>, 1221c65a4ed2SKonrad Dybcio <&gcc GCC_USB30_MOCK_UTMI_CLK>, 12228d5fd4e4SKrzysztof Kozlowski <&rpmcc RPM_SMD_AGGR2_NOC_CLK>; 12238d5fd4e4SKrzysztof Kozlowski clock-names = "cfg_noc", 12248d5fd4e4SKrzysztof Kozlowski "core", 12258d5fd4e4SKrzysztof Kozlowski "iface", 12268d5fd4e4SKrzysztof Kozlowski "sleep", 12278d5fd4e4SKrzysztof Kozlowski "mock_utmi", 12288d5fd4e4SKrzysztof Kozlowski "bus"; 1229c65a4ed2SKonrad Dybcio 1230c65a4ed2SKonrad Dybcio assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, 1231c65a4ed2SKonrad Dybcio <&gcc GCC_USB30_MASTER_CLK>, 1232c65a4ed2SKonrad Dybcio <&rpmcc RPM_SMD_AGGR2_NOC_CLK>; 1233c65a4ed2SKonrad Dybcio assigned-clock-rates = <19200000>, <120000000>, 1234c65a4ed2SKonrad Dybcio <19200000>; 1235c65a4ed2SKonrad Dybcio 1236c65a4ed2SKonrad Dybcio interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, 1237c65a4ed2SKonrad Dybcio <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 1238c65a4ed2SKonrad Dybcio interrupt-names = "hs_phy_irq", "ss_phy_irq"; 1239c65a4ed2SKonrad Dybcio 1240c65a4ed2SKonrad Dybcio power-domains = <&gcc USB_30_GDSC>; 1241c65a4ed2SKonrad Dybcio qcom,select-utmi-as-pipe-clk; 1242c65a4ed2SKonrad Dybcio 1243c65a4ed2SKonrad Dybcio resets = <&gcc GCC_USB_30_BCR>; 1244c65a4ed2SKonrad Dybcio 1245c65a4ed2SKonrad Dybcio usb3_dwc3: usb@a800000 { 1246c65a4ed2SKonrad Dybcio compatible = "snps,dwc3"; 1247c65a4ed2SKonrad Dybcio reg = <0x0a800000 0xc8d0>; 1248c65a4ed2SKonrad Dybcio interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 1249c65a4ed2SKonrad Dybcio snps,dis_u2_susphy_quirk; 1250c65a4ed2SKonrad Dybcio snps,dis_enblslpm_quirk; 1251c65a4ed2SKonrad Dybcio 1252c65a4ed2SKonrad Dybcio /* 1253c65a4ed2SKonrad Dybcio * SDM630 technically supports USB3 but I 1254c65a4ed2SKonrad Dybcio * haven't seen any devices making use of it. 1255c65a4ed2SKonrad Dybcio */ 1256c65a4ed2SKonrad Dybcio maximum-speed = "high-speed"; 1257*696dea7eSDmitry Baryshkov phys = <&qusb2phy0>; 1258c65a4ed2SKonrad Dybcio phy-names = "usb2-phy"; 1259c65a4ed2SKonrad Dybcio snps,hird-threshold = /bits/ 8 <0>; 1260c65a4ed2SKonrad Dybcio }; 1261c65a4ed2SKonrad Dybcio }; 1262c65a4ed2SKonrad Dybcio 1263*696dea7eSDmitry Baryshkov qusb2phy0: phy@c012000 { 1264c65a4ed2SKonrad Dybcio compatible = "qcom,sdm660-qusb2-phy"; 1265c65a4ed2SKonrad Dybcio reg = <0x0c012000 0x180>; 1266c65a4ed2SKonrad Dybcio #phy-cells = <0>; 1267c65a4ed2SKonrad Dybcio 1268c65a4ed2SKonrad Dybcio clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 1269924bbd8dSDmitry Baryshkov <&gcc GCC_RX0_USB2_CLKREF_CLK>; 1270c65a4ed2SKonrad Dybcio clock-names = "cfg_ahb", "ref"; 1271c65a4ed2SKonrad Dybcio 1272c65a4ed2SKonrad Dybcio resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 1273c65a4ed2SKonrad Dybcio nvmem-cells = <&qusb2_hstx_trim>; 1274c65a4ed2SKonrad Dybcio status = "disabled"; 1275c65a4ed2SKonrad Dybcio }; 1276c65a4ed2SKonrad Dybcio 12770b700aa1SAngeloGioacchino Del Regno sdhc_2: sdhci@c084000 { 12780b700aa1SAngeloGioacchino Del Regno compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5"; 12790b700aa1SAngeloGioacchino Del Regno reg = <0x0c084000 0x1000>; 12800b700aa1SAngeloGioacchino Del Regno reg-names = "hc"; 12810b700aa1SAngeloGioacchino Del Regno 12820b700aa1SAngeloGioacchino Del Regno interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 12830b700aa1SAngeloGioacchino Del Regno <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 12840b700aa1SAngeloGioacchino Del Regno interrupt-names = "hc_irq", "pwr_irq"; 12850b700aa1SAngeloGioacchino Del Regno 12860b700aa1SAngeloGioacchino Del Regno bus-width = <4>; 12870b700aa1SAngeloGioacchino Del Regno clocks = <&gcc GCC_SDCC2_APPS_CLK>, 12880b700aa1SAngeloGioacchino Del Regno <&gcc GCC_SDCC2_AHB_CLK>, 12890b700aa1SAngeloGioacchino Del Regno <&xo_board>; 12900b700aa1SAngeloGioacchino Del Regno clock-names = "core", "iface", "xo"; 12910b700aa1SAngeloGioacchino Del Regno 12920b700aa1SAngeloGioacchino Del Regno interconnects = <&a2noc 3 &a2noc 10>, 12930b700aa1SAngeloGioacchino Del Regno <&gnoc 0 &cnoc 28>; 12940b700aa1SAngeloGioacchino Del Regno operating-points-v2 = <&sdhc2_opp_table>; 12950b700aa1SAngeloGioacchino Del Regno 12960b700aa1SAngeloGioacchino Del Regno pinctrl-names = "default", "sleep"; 12970b700aa1SAngeloGioacchino Del Regno pinctrl-0 = <&sdc2_state_on>; 12980b700aa1SAngeloGioacchino Del Regno pinctrl-1 = <&sdc2_state_off>; 12990b700aa1SAngeloGioacchino Del Regno power-domains = <&rpmpd SDM660_VDDCX>; 13000b700aa1SAngeloGioacchino Del Regno 13010b700aa1SAngeloGioacchino Del Regno status = "disabled"; 13020b700aa1SAngeloGioacchino Del Regno 13030b700aa1SAngeloGioacchino Del Regno sdhc2_opp_table: opp-table { 13040b700aa1SAngeloGioacchino Del Regno compatible = "operating-points-v2"; 13050b700aa1SAngeloGioacchino Del Regno 13060b700aa1SAngeloGioacchino Del Regno opp-50000000 { 13070b700aa1SAngeloGioacchino Del Regno opp-hz = /bits/ 64 <50000000>; 13080b700aa1SAngeloGioacchino Del Regno required-opps = <&rpmpd_opp_low_svs>; 13090b700aa1SAngeloGioacchino Del Regno opp-peak-kBps = <200000 140000>; 13100b700aa1SAngeloGioacchino Del Regno opp-avg-kBps = <130718 133320>; 13110b700aa1SAngeloGioacchino Del Regno }; 13120b700aa1SAngeloGioacchino Del Regno opp-100000000 { 13130b700aa1SAngeloGioacchino Del Regno opp-hz = /bits/ 64 <100000000>; 13140b700aa1SAngeloGioacchino Del Regno required-opps = <&rpmpd_opp_svs>; 13150b700aa1SAngeloGioacchino Del Regno opp-peak-kBps = <250000 160000>; 13160b700aa1SAngeloGioacchino Del Regno opp-avg-kBps = <196078 150000>; 13170b700aa1SAngeloGioacchino Del Regno }; 13180b700aa1SAngeloGioacchino Del Regno opp-200000000 { 13190b700aa1SAngeloGioacchino Del Regno opp-hz = /bits/ 64 <200000000>; 13200b700aa1SAngeloGioacchino Del Regno required-opps = <&rpmpd_opp_nom>; 13210b700aa1SAngeloGioacchino Del Regno opp-peak-kBps = <4096000 4096000>; 13220b700aa1SAngeloGioacchino Del Regno opp-avg-kBps = <1338562 1338562>; 13230b700aa1SAngeloGioacchino Del Regno }; 13240b700aa1SAngeloGioacchino Del Regno }; 13250b700aa1SAngeloGioacchino Del Regno }; 13260b700aa1SAngeloGioacchino Del Regno 1327b190fb01SKonrad Dybcio sdhc_1: sdhci@c0c4000 { 1328b190fb01SKonrad Dybcio compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5"; 1329b190fb01SKonrad Dybcio reg = <0x0c0c4000 0x1000>, 1330e49c2912SEric Biggers <0x0c0c5000 0x1000>, 1331e49c2912SEric Biggers <0x0c0c8000 0x8000>; 1332e49c2912SEric Biggers reg-names = "hc", "cqhci", "ice"; 1333b190fb01SKonrad Dybcio 1334b190fb01SKonrad Dybcio interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1335b190fb01SKonrad Dybcio <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1336b190fb01SKonrad Dybcio interrupt-names = "hc_irq", "pwr_irq"; 1337b190fb01SKonrad Dybcio 1338b190fb01SKonrad Dybcio clocks = <&gcc GCC_SDCC1_APPS_CLK>, 1339b190fb01SKonrad Dybcio <&gcc GCC_SDCC1_AHB_CLK>, 1340e49c2912SEric Biggers <&xo_board>, 1341e49c2912SEric Biggers <&gcc GCC_SDCC1_ICE_CORE_CLK>; 1342e49c2912SEric Biggers clock-names = "core", "iface", "xo", "ice"; 1343b190fb01SKonrad Dybcio 1344738777abSAngeloGioacchino Del Regno interconnects = <&a2noc 2 &a2noc 10>, 1345738777abSAngeloGioacchino Del Regno <&gnoc 0 &cnoc 27>; 1346738777abSAngeloGioacchino Del Regno interconnect-names = "sdhc1-ddr", "cpu-sdhc1"; 1347738777abSAngeloGioacchino Del Regno operating-points-v2 = <&sdhc1_opp_table>; 1348b190fb01SKonrad Dybcio pinctrl-names = "default", "sleep"; 134936a0d47aSAngeloGioacchino Del Regno pinctrl-0 = <&sdc1_state_on>; 135036a0d47aSAngeloGioacchino Del Regno pinctrl-1 = <&sdc1_state_off>; 1351738777abSAngeloGioacchino Del Regno power-domains = <&rpmpd SDM660_VDDCX>; 1352b190fb01SKonrad Dybcio 1353b190fb01SKonrad Dybcio bus-width = <8>; 1354b190fb01SKonrad Dybcio non-removable; 1355b190fb01SKonrad Dybcio 1356b190fb01SKonrad Dybcio status = "disabled"; 1357738777abSAngeloGioacchino Del Regno 1358738777abSAngeloGioacchino Del Regno sdhc1_opp_table: opp-table { 1359738777abSAngeloGioacchino Del Regno compatible = "operating-points-v2"; 1360738777abSAngeloGioacchino Del Regno 1361738777abSAngeloGioacchino Del Regno opp-50000000 { 1362738777abSAngeloGioacchino Del Regno opp-hz = /bits/ 64 <50000000>; 1363738777abSAngeloGioacchino Del Regno required-opps = <&rpmpd_opp_low_svs>; 1364738777abSAngeloGioacchino Del Regno opp-peak-kBps = <200000 140000>; 1365738777abSAngeloGioacchino Del Regno opp-avg-kBps = <130718 133320>; 1366738777abSAngeloGioacchino Del Regno }; 1367738777abSAngeloGioacchino Del Regno opp-100000000 { 1368738777abSAngeloGioacchino Del Regno opp-hz = /bits/ 64 <100000000>; 1369738777abSAngeloGioacchino Del Regno required-opps = <&rpmpd_opp_svs>; 1370738777abSAngeloGioacchino Del Regno opp-peak-kBps = <250000 160000>; 1371738777abSAngeloGioacchino Del Regno opp-avg-kBps = <196078 150000>; 1372738777abSAngeloGioacchino Del Regno }; 1373738777abSAngeloGioacchino Del Regno opp-384000000 { 1374738777abSAngeloGioacchino Del Regno opp-hz = /bits/ 64 <384000000>; 1375738777abSAngeloGioacchino Del Regno required-opps = <&rpmpd_opp_nom>; 1376738777abSAngeloGioacchino Del Regno opp-peak-kBps = <4096000 4096000>; 1377738777abSAngeloGioacchino Del Regno opp-avg-kBps = <1338562 1338562>; 1378738777abSAngeloGioacchino Del Regno }; 1379738777abSAngeloGioacchino Del Regno }; 1380b190fb01SKonrad Dybcio }; 1381b190fb01SKonrad Dybcio 138201b182d9SKonrad Dybcio mmcc: clock-controller@c8c0000 { 138301b182d9SKonrad Dybcio compatible = "qcom,mmcc-sdm630"; 138401b182d9SKonrad Dybcio reg = <0x0c8c0000 0x40000>; 138501b182d9SKonrad Dybcio #clock-cells = <1>; 138601b182d9SKonrad Dybcio #reset-cells = <1>; 138701b182d9SKonrad Dybcio #power-domain-cells = <1>; 138801b182d9SKonrad Dybcio clock-names = "xo", 138901b182d9SKonrad Dybcio "sleep_clk", 139001b182d9SKonrad Dybcio "gpll0", 139101b182d9SKonrad Dybcio "gpll0_div", 139201b182d9SKonrad Dybcio "dsi0pll", 139301b182d9SKonrad Dybcio "dsi0pllbyte", 139401b182d9SKonrad Dybcio "dsi1pll", 139501b182d9SKonrad Dybcio "dsi1pllbyte", 139601b182d9SKonrad Dybcio "dp_link_2x_clk_divsel_five", 139701b182d9SKonrad Dybcio "dp_vco_divided_clk_src_mux"; 139801b182d9SKonrad Dybcio clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 139901b182d9SKonrad Dybcio <&sleep_clk>, 140001b182d9SKonrad Dybcio <&gcc GCC_MMSS_GPLL0_CLK>, 140101b182d9SKonrad Dybcio <&gcc GCC_MMSS_GPLL0_DIV_CLK>, 1402b52555d5SKonrad Dybcio <&dsi0_phy 1>, 1403b52555d5SKonrad Dybcio <&dsi0_phy 0>, 140401b182d9SKonrad Dybcio <0>, 140501b182d9SKonrad Dybcio <0>, 140601b182d9SKonrad Dybcio <0>, 140701b182d9SKonrad Dybcio <0>; 140801b182d9SKonrad Dybcio }; 140901b182d9SKonrad Dybcio 14100e3e6546SKrzysztof Kozlowski dsi_opp_table: opp-table-dsi { 1411b52555d5SKonrad Dybcio compatible = "operating-points-v2"; 1412b52555d5SKonrad Dybcio 1413b52555d5SKonrad Dybcio opp-131250000 { 1414b52555d5SKonrad Dybcio opp-hz = /bits/ 64 <131250000>; 1415b52555d5SKonrad Dybcio required-opps = <&rpmpd_opp_svs>; 1416b52555d5SKonrad Dybcio }; 1417b52555d5SKonrad Dybcio 1418b52555d5SKonrad Dybcio opp-210000000 { 1419b52555d5SKonrad Dybcio opp-hz = /bits/ 64 <210000000>; 1420b52555d5SKonrad Dybcio required-opps = <&rpmpd_opp_svs_plus>; 1421b52555d5SKonrad Dybcio }; 1422b52555d5SKonrad Dybcio 1423b52555d5SKonrad Dybcio opp-262500000 { 1424b52555d5SKonrad Dybcio opp-hz = /bits/ 64 <262500000>; 1425b52555d5SKonrad Dybcio required-opps = <&rpmpd_opp_nom>; 1426b52555d5SKonrad Dybcio }; 1427b52555d5SKonrad Dybcio }; 1428b52555d5SKonrad Dybcio 1429b52555d5SKonrad Dybcio mdss: mdss@c900000 { 1430b52555d5SKonrad Dybcio compatible = "qcom,mdss"; 1431b52555d5SKonrad Dybcio reg = <0x0c900000 0x1000>, 1432b52555d5SKonrad Dybcio <0x0c9b0000 0x1040>; 1433b52555d5SKonrad Dybcio reg-names = "mdss_phys", "vbif_phys"; 1434b52555d5SKonrad Dybcio 1435b52555d5SKonrad Dybcio power-domains = <&mmcc MDSS_GDSC>; 1436b52555d5SKonrad Dybcio 1437b52555d5SKonrad Dybcio clocks = <&mmcc MDSS_AHB_CLK>, 1438b52555d5SKonrad Dybcio <&mmcc MDSS_AXI_CLK>, 1439b52555d5SKonrad Dybcio <&mmcc MDSS_VSYNC_CLK>, 1440b52555d5SKonrad Dybcio <&mmcc MDSS_MDP_CLK>; 1441b52555d5SKonrad Dybcio clock-names = "iface", 1442b52555d5SKonrad Dybcio "bus", 1443b52555d5SKonrad Dybcio "vsync", 1444b52555d5SKonrad Dybcio "core"; 1445b52555d5SKonrad Dybcio 1446b52555d5SKonrad Dybcio interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 1447b52555d5SKonrad Dybcio 1448b52555d5SKonrad Dybcio interrupt-controller; 1449b52555d5SKonrad Dybcio #interrupt-cells = <1>; 1450b52555d5SKonrad Dybcio 1451b52555d5SKonrad Dybcio #address-cells = <1>; 1452b52555d5SKonrad Dybcio #size-cells = <1>; 1453b52555d5SKonrad Dybcio ranges; 1454b52555d5SKonrad Dybcio status = "disabled"; 1455b52555d5SKonrad Dybcio 1456b52555d5SKonrad Dybcio mdp: mdp@c901000 { 1457b52555d5SKonrad Dybcio compatible = "qcom,mdp5"; 1458b52555d5SKonrad Dybcio reg = <0x0c901000 0x89000>; 1459b52555d5SKonrad Dybcio reg-names = "mdp_phys"; 1460b52555d5SKonrad Dybcio 1461b52555d5SKonrad Dybcio interrupt-parent = <&mdss>; 14622a11b3bfSDmitry Baryshkov interrupts = <0>; 1463b52555d5SKonrad Dybcio 1464b52555d5SKonrad Dybcio assigned-clocks = <&mmcc MDSS_MDP_CLK>, 1465b52555d5SKonrad Dybcio <&mmcc MDSS_VSYNC_CLK>; 1466b52555d5SKonrad Dybcio assigned-clock-rates = <300000000>, 1467b52555d5SKonrad Dybcio <19200000>; 1468b52555d5SKonrad Dybcio clocks = <&mmcc MDSS_AHB_CLK>, 1469b52555d5SKonrad Dybcio <&mmcc MDSS_AXI_CLK>, 1470b52555d5SKonrad Dybcio <&mmcc MDSS_MDP_CLK>, 1471b52555d5SKonrad Dybcio <&mmcc MDSS_VSYNC_CLK>; 1472b52555d5SKonrad Dybcio clock-names = "iface", 1473b52555d5SKonrad Dybcio "bus", 1474b52555d5SKonrad Dybcio "core", 1475b52555d5SKonrad Dybcio "vsync"; 1476b52555d5SKonrad Dybcio 1477b52555d5SKonrad Dybcio interconnects = <&mnoc 2 &bimc 5>, 1478b52555d5SKonrad Dybcio <&mnoc 3 &bimc 5>, 1479b52555d5SKonrad Dybcio <&gnoc 0 &mnoc 17>; 1480b52555d5SKonrad Dybcio interconnect-names = "mdp0-mem", 1481b52555d5SKonrad Dybcio "mdp1-mem", 1482b52555d5SKonrad Dybcio "rotator-mem"; 1483b52555d5SKonrad Dybcio iommus = <&mmss_smmu 0>; 1484b52555d5SKonrad Dybcio operating-points-v2 = <&mdp_opp_table>; 1485b52555d5SKonrad Dybcio power-domains = <&rpmpd SDM660_VDDCX>; 1486b52555d5SKonrad Dybcio 1487b52555d5SKonrad Dybcio ports { 1488b52555d5SKonrad Dybcio #address-cells = <1>; 1489b52555d5SKonrad Dybcio #size-cells = <0>; 1490b52555d5SKonrad Dybcio 1491b52555d5SKonrad Dybcio port@0 { 1492b52555d5SKonrad Dybcio reg = <0>; 1493b52555d5SKonrad Dybcio mdp5_intf1_out: endpoint { 1494b52555d5SKonrad Dybcio remote-endpoint = <&dsi0_in>; 1495b52555d5SKonrad Dybcio }; 1496b52555d5SKonrad Dybcio }; 1497b52555d5SKonrad Dybcio }; 1498b52555d5SKonrad Dybcio 14990e3e6546SKrzysztof Kozlowski mdp_opp_table: opp-table { 1500b52555d5SKonrad Dybcio compatible = "operating-points-v2"; 1501b52555d5SKonrad Dybcio 1502b52555d5SKonrad Dybcio opp-150000000 { 1503b52555d5SKonrad Dybcio opp-hz = /bits/ 64 <150000000>; 1504b52555d5SKonrad Dybcio opp-peak-kBps = <320000 320000 76800>; 1505b52555d5SKonrad Dybcio required-opps = <&rpmpd_opp_low_svs>; 1506b52555d5SKonrad Dybcio }; 1507b52555d5SKonrad Dybcio opp-275000000 { 1508b52555d5SKonrad Dybcio opp-hz = /bits/ 64 <275000000>; 1509b52555d5SKonrad Dybcio opp-peak-kBps = <6400000 6400000 160000>; 1510b52555d5SKonrad Dybcio required-opps = <&rpmpd_opp_svs>; 1511b52555d5SKonrad Dybcio }; 1512b52555d5SKonrad Dybcio opp-300000000 { 1513b52555d5SKonrad Dybcio opp-hz = /bits/ 64 <300000000>; 1514b52555d5SKonrad Dybcio opp-peak-kBps = <6400000 6400000 190000>; 1515b52555d5SKonrad Dybcio required-opps = <&rpmpd_opp_svs_plus>; 1516b52555d5SKonrad Dybcio }; 1517b52555d5SKonrad Dybcio opp-330000000 { 1518b52555d5SKonrad Dybcio opp-hz = /bits/ 64 <330000000>; 1519b52555d5SKonrad Dybcio opp-peak-kBps = <6400000 6400000 240000>; 1520b52555d5SKonrad Dybcio required-opps = <&rpmpd_opp_nom>; 1521b52555d5SKonrad Dybcio }; 1522b52555d5SKonrad Dybcio opp-412500000 { 1523b52555d5SKonrad Dybcio opp-hz = /bits/ 64 <412500000>; 1524b52555d5SKonrad Dybcio opp-peak-kBps = <6400000 6400000 320000>; 1525b52555d5SKonrad Dybcio required-opps = <&rpmpd_opp_turbo>; 1526b52555d5SKonrad Dybcio }; 1527b52555d5SKonrad Dybcio }; 1528b52555d5SKonrad Dybcio }; 1529b52555d5SKonrad Dybcio 1530b52555d5SKonrad Dybcio dsi0: dsi@c994000 { 1531b52555d5SKonrad Dybcio compatible = "qcom,mdss-dsi-ctrl"; 1532b52555d5SKonrad Dybcio reg = <0x0c994000 0x400>; 1533b52555d5SKonrad Dybcio reg-names = "dsi_ctrl"; 1534b52555d5SKonrad Dybcio 1535b52555d5SKonrad Dybcio operating-points-v2 = <&dsi_opp_table>; 1536b52555d5SKonrad Dybcio power-domains = <&rpmpd SDM660_VDDCX>; 1537b52555d5SKonrad Dybcio 1538b52555d5SKonrad Dybcio interrupt-parent = <&mdss>; 15392a11b3bfSDmitry Baryshkov interrupts = <4>; 1540b52555d5SKonrad Dybcio 1541b52555d5SKonrad Dybcio assigned-clocks = <&mmcc BYTE0_CLK_SRC>, 1542b52555d5SKonrad Dybcio <&mmcc PCLK0_CLK_SRC>; 1543b52555d5SKonrad Dybcio assigned-clock-parents = <&dsi0_phy 0>, 1544b52555d5SKonrad Dybcio <&dsi0_phy 1>; 1545b52555d5SKonrad Dybcio 1546b52555d5SKonrad Dybcio clocks = <&mmcc MDSS_MDP_CLK>, 1547b52555d5SKonrad Dybcio <&mmcc MDSS_BYTE0_CLK>, 1548b52555d5SKonrad Dybcio <&mmcc MDSS_BYTE0_INTF_CLK>, 1549b52555d5SKonrad Dybcio <&mmcc MNOC_AHB_CLK>, 1550b52555d5SKonrad Dybcio <&mmcc MDSS_AHB_CLK>, 1551b52555d5SKonrad Dybcio <&mmcc MDSS_AXI_CLK>, 1552b52555d5SKonrad Dybcio <&mmcc MISC_AHB_CLK>, 1553b52555d5SKonrad Dybcio <&mmcc MDSS_PCLK0_CLK>, 1554b52555d5SKonrad Dybcio <&mmcc MDSS_ESC0_CLK>; 1555b52555d5SKonrad Dybcio clock-names = "mdp_core", 1556b52555d5SKonrad Dybcio "byte", 1557b52555d5SKonrad Dybcio "byte_intf", 1558b52555d5SKonrad Dybcio "mnoc", 1559b52555d5SKonrad Dybcio "iface", 1560b52555d5SKonrad Dybcio "bus", 1561b52555d5SKonrad Dybcio "core_mmss", 1562b52555d5SKonrad Dybcio "pixel", 1563b52555d5SKonrad Dybcio "core"; 1564b52555d5SKonrad Dybcio 1565b52555d5SKonrad Dybcio phys = <&dsi0_phy>; 1566b52555d5SKonrad Dybcio phy-names = "dsi"; 1567b52555d5SKonrad Dybcio 156879d8e016SDmitry Baryshkov status = "disabled"; 156979d8e016SDmitry Baryshkov 1570b52555d5SKonrad Dybcio ports { 1571b52555d5SKonrad Dybcio #address-cells = <1>; 1572b52555d5SKonrad Dybcio #size-cells = <0>; 1573b52555d5SKonrad Dybcio 1574b52555d5SKonrad Dybcio port@0 { 1575b52555d5SKonrad Dybcio reg = <0>; 1576b52555d5SKonrad Dybcio dsi0_in: endpoint { 1577b52555d5SKonrad Dybcio remote-endpoint = <&mdp5_intf1_out>; 1578b52555d5SKonrad Dybcio }; 1579b52555d5SKonrad Dybcio }; 1580b52555d5SKonrad Dybcio 1581b52555d5SKonrad Dybcio port@1 { 1582b52555d5SKonrad Dybcio reg = <1>; 1583b52555d5SKonrad Dybcio dsi0_out: endpoint { 1584b52555d5SKonrad Dybcio }; 1585b52555d5SKonrad Dybcio }; 1586b52555d5SKonrad Dybcio }; 1587b52555d5SKonrad Dybcio }; 1588b52555d5SKonrad Dybcio 1589b52555d5SKonrad Dybcio dsi0_phy: dsi-phy@c994400 { 1590b52555d5SKonrad Dybcio compatible = "qcom,dsi-phy-14nm-660"; 1591b52555d5SKonrad Dybcio reg = <0x0c994400 0x100>, 1592b52555d5SKonrad Dybcio <0x0c994500 0x300>, 1593b52555d5SKonrad Dybcio <0x0c994800 0x188>; 1594b52555d5SKonrad Dybcio reg-names = "dsi_phy", 1595b52555d5SKonrad Dybcio "dsi_phy_lane", 1596b52555d5SKonrad Dybcio "dsi_pll"; 1597b52555d5SKonrad Dybcio 1598b52555d5SKonrad Dybcio #clock-cells = <1>; 1599b52555d5SKonrad Dybcio #phy-cells = <0>; 1600b52555d5SKonrad Dybcio 1601b52555d5SKonrad Dybcio clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>; 1602b52555d5SKonrad Dybcio clock-names = "iface", "ref"; 160379d8e016SDmitry Baryshkov status = "disabled"; 1604b52555d5SKonrad Dybcio }; 1605b52555d5SKonrad Dybcio }; 1606b52555d5SKonrad Dybcio 1607b831fba3SVinod Koul blsp1_dma: dma-controller@c144000 { 1608b190fb01SKonrad Dybcio compatible = "qcom,bam-v1.7.0"; 1609b190fb01SKonrad Dybcio reg = <0x0c144000 0x1f000>; 1610b190fb01SKonrad Dybcio interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 1611b190fb01SKonrad Dybcio clocks = <&gcc GCC_BLSP1_AHB_CLK>; 1612b190fb01SKonrad Dybcio clock-names = "bam_clk"; 1613b190fb01SKonrad Dybcio #dma-cells = <1>; 1614b190fb01SKonrad Dybcio qcom,ee = <0>; 1615b190fb01SKonrad Dybcio qcom,controlled-remotely; 1616b190fb01SKonrad Dybcio num-channels = <18>; 1617b190fb01SKonrad Dybcio qcom,num-ees = <4>; 1618b190fb01SKonrad Dybcio }; 1619b190fb01SKonrad Dybcio 1620b190fb01SKonrad Dybcio blsp1_uart1: serial@c16f000 { 1621b190fb01SKonrad Dybcio compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1622b190fb01SKonrad Dybcio reg = <0x0c16f000 0x200>; 1623b190fb01SKonrad Dybcio interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1624b190fb01SKonrad Dybcio clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, 1625b190fb01SKonrad Dybcio <&gcc GCC_BLSP1_AHB_CLK>; 1626b190fb01SKonrad Dybcio clock-names = "core", "iface"; 1627b190fb01SKonrad Dybcio dmas = <&blsp1_dma 0>, <&blsp1_dma 1>; 1628b190fb01SKonrad Dybcio dma-names = "tx", "rx"; 1629b190fb01SKonrad Dybcio pinctrl-names = "default", "sleep"; 1630b190fb01SKonrad Dybcio pinctrl-0 = <&blsp1_uart1_default>; 1631b190fb01SKonrad Dybcio pinctrl-1 = <&blsp1_uart1_sleep>; 1632b190fb01SKonrad Dybcio status = "disabled"; 1633b190fb01SKonrad Dybcio }; 1634b190fb01SKonrad Dybcio 1635b190fb01SKonrad Dybcio blsp1_uart2: serial@c170000 { 1636b190fb01SKonrad Dybcio compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1637b190fb01SKonrad Dybcio reg = <0x0c170000 0x1000>; 1638b190fb01SKonrad Dybcio interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1639b190fb01SKonrad Dybcio clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, 1640b190fb01SKonrad Dybcio <&gcc GCC_BLSP1_AHB_CLK>; 1641b190fb01SKonrad Dybcio clock-names = "core", "iface"; 1642b190fb01SKonrad Dybcio dmas = <&blsp1_dma 2>, <&blsp1_dma 3>; 1643b190fb01SKonrad Dybcio dma-names = "tx", "rx"; 1644b190fb01SKonrad Dybcio pinctrl-names = "default"; 1645b190fb01SKonrad Dybcio pinctrl-0 = <&blsp1_uart2_default>; 1646b190fb01SKonrad Dybcio status = "disabled"; 1647b190fb01SKonrad Dybcio }; 1648b190fb01SKonrad Dybcio 1649b190fb01SKonrad Dybcio blsp_i2c1: i2c@c175000 { 1650b190fb01SKonrad Dybcio compatible = "qcom,i2c-qup-v2.2.1"; 1651b190fb01SKonrad Dybcio reg = <0x0c175000 0x600>; 1652b190fb01SKonrad Dybcio interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1653b190fb01SKonrad Dybcio 1654b190fb01SKonrad Dybcio clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, 1655b190fb01SKonrad Dybcio <&gcc GCC_BLSP1_AHB_CLK>; 1656b190fb01SKonrad Dybcio clock-names = "core", "iface"; 1657b190fb01SKonrad Dybcio clock-frequency = <400000>; 1658712e245fSKonrad Dybcio dmas = <&blsp1_dma 4>, <&blsp1_dma 5>; 1659712e245fSKonrad Dybcio dma-names = "tx", "rx"; 1660b190fb01SKonrad Dybcio 1661b190fb01SKonrad Dybcio pinctrl-names = "default", "sleep"; 1662b190fb01SKonrad Dybcio pinctrl-0 = <&i2c1_default>; 1663b190fb01SKonrad Dybcio pinctrl-1 = <&i2c1_sleep>; 1664b190fb01SKonrad Dybcio #address-cells = <1>; 1665b190fb01SKonrad Dybcio #size-cells = <0>; 1666b190fb01SKonrad Dybcio status = "disabled"; 1667b190fb01SKonrad Dybcio }; 1668b190fb01SKonrad Dybcio 1669b190fb01SKonrad Dybcio blsp_i2c2: i2c@c176000 { 1670b190fb01SKonrad Dybcio compatible = "qcom,i2c-qup-v2.2.1"; 1671b190fb01SKonrad Dybcio reg = <0x0c176000 0x600>; 1672b190fb01SKonrad Dybcio interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1673b190fb01SKonrad Dybcio 1674b190fb01SKonrad Dybcio clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 1675b190fb01SKonrad Dybcio <&gcc GCC_BLSP1_AHB_CLK>; 1676b190fb01SKonrad Dybcio clock-names = "core", "iface"; 1677b190fb01SKonrad Dybcio clock-frequency = <400000>; 1678712e245fSKonrad Dybcio dmas = <&blsp1_dma 6>, <&blsp1_dma 7>; 1679712e245fSKonrad Dybcio dma-names = "tx", "rx"; 1680b190fb01SKonrad Dybcio 1681b190fb01SKonrad Dybcio pinctrl-names = "default", "sleep"; 1682b190fb01SKonrad Dybcio pinctrl-0 = <&i2c2_default>; 1683b190fb01SKonrad Dybcio pinctrl-1 = <&i2c2_sleep>; 1684b190fb01SKonrad Dybcio #address-cells = <1>; 1685b190fb01SKonrad Dybcio #size-cells = <0>; 1686b190fb01SKonrad Dybcio status = "disabled"; 1687b190fb01SKonrad Dybcio }; 1688b190fb01SKonrad Dybcio 1689b190fb01SKonrad Dybcio blsp_i2c3: i2c@c177000 { 1690b190fb01SKonrad Dybcio compatible = "qcom,i2c-qup-v2.2.1"; 1691b190fb01SKonrad Dybcio reg = <0x0c177000 0x600>; 1692b190fb01SKonrad Dybcio interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1693b190fb01SKonrad Dybcio 1694b190fb01SKonrad Dybcio clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 1695b190fb01SKonrad Dybcio <&gcc GCC_BLSP1_AHB_CLK>; 1696b190fb01SKonrad Dybcio clock-names = "core", "iface"; 1697b190fb01SKonrad Dybcio clock-frequency = <400000>; 1698712e245fSKonrad Dybcio dmas = <&blsp1_dma 8>, <&blsp1_dma 9>; 1699712e245fSKonrad Dybcio dma-names = "tx", "rx"; 1700b190fb01SKonrad Dybcio 1701b190fb01SKonrad Dybcio pinctrl-names = "default", "sleep"; 1702b190fb01SKonrad Dybcio pinctrl-0 = <&i2c3_default>; 1703b190fb01SKonrad Dybcio pinctrl-1 = <&i2c3_sleep>; 1704b190fb01SKonrad Dybcio #address-cells = <1>; 1705b190fb01SKonrad Dybcio #size-cells = <0>; 1706b190fb01SKonrad Dybcio status = "disabled"; 1707b190fb01SKonrad Dybcio }; 1708b190fb01SKonrad Dybcio 1709b190fb01SKonrad Dybcio blsp_i2c4: i2c@c178000 { 1710b190fb01SKonrad Dybcio compatible = "qcom,i2c-qup-v2.2.1"; 1711b190fb01SKonrad Dybcio reg = <0x0c178000 0x600>; 1712b190fb01SKonrad Dybcio interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1713b190fb01SKonrad Dybcio 1714b190fb01SKonrad Dybcio clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, 1715b190fb01SKonrad Dybcio <&gcc GCC_BLSP1_AHB_CLK>; 1716b190fb01SKonrad Dybcio clock-names = "core", "iface"; 1717b190fb01SKonrad Dybcio clock-frequency = <400000>; 1718712e245fSKonrad Dybcio dmas = <&blsp1_dma 10>, <&blsp1_dma 11>; 1719712e245fSKonrad Dybcio dma-names = "tx", "rx"; 1720b190fb01SKonrad Dybcio 1721b190fb01SKonrad Dybcio pinctrl-names = "default", "sleep"; 1722b190fb01SKonrad Dybcio pinctrl-0 = <&i2c4_default>; 1723b190fb01SKonrad Dybcio pinctrl-1 = <&i2c4_sleep>; 1724b190fb01SKonrad Dybcio #address-cells = <1>; 1725b190fb01SKonrad Dybcio #size-cells = <0>; 1726b190fb01SKonrad Dybcio status = "disabled"; 1727b190fb01SKonrad Dybcio }; 1728b190fb01SKonrad Dybcio 1729b831fba3SVinod Koul blsp2_dma: dma-controller@c184000 { 1730b190fb01SKonrad Dybcio compatible = "qcom,bam-v1.7.0"; 1731b190fb01SKonrad Dybcio reg = <0x0c184000 0x1f000>; 1732b190fb01SKonrad Dybcio interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 1733b190fb01SKonrad Dybcio clocks = <&gcc GCC_BLSP2_AHB_CLK>; 1734b190fb01SKonrad Dybcio clock-names = "bam_clk"; 1735b190fb01SKonrad Dybcio #dma-cells = <1>; 1736b190fb01SKonrad Dybcio qcom,ee = <0>; 1737b190fb01SKonrad Dybcio qcom,controlled-remotely; 1738b190fb01SKonrad Dybcio num-channels = <18>; 1739b190fb01SKonrad Dybcio qcom,num-ees = <4>; 1740b190fb01SKonrad Dybcio }; 1741b190fb01SKonrad Dybcio 1742b190fb01SKonrad Dybcio blsp2_uart1: serial@c1af000 { 1743b190fb01SKonrad Dybcio compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1744b190fb01SKonrad Dybcio reg = <0x0c1af000 0x200>; 1745b190fb01SKonrad Dybcio interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 1746b190fb01SKonrad Dybcio clocks = <&gcc GCC_BLSP2_UART1_APPS_CLK>, 1747b190fb01SKonrad Dybcio <&gcc GCC_BLSP2_AHB_CLK>; 1748b190fb01SKonrad Dybcio clock-names = "core", "iface"; 1749b190fb01SKonrad Dybcio dmas = <&blsp2_dma 0>, <&blsp2_dma 1>; 1750b190fb01SKonrad Dybcio dma-names = "tx", "rx"; 1751b190fb01SKonrad Dybcio pinctrl-names = "default", "sleep"; 175236a0d47aSAngeloGioacchino Del Regno pinctrl-0 = <&blsp2_uart1_default>; 175336a0d47aSAngeloGioacchino Del Regno pinctrl-1 = <&blsp2_uart1_sleep>; 1754b190fb01SKonrad Dybcio status = "disabled"; 1755b190fb01SKonrad Dybcio }; 1756b190fb01SKonrad Dybcio 1757b190fb01SKonrad Dybcio blsp_i2c5: i2c@c1b5000 { 1758b190fb01SKonrad Dybcio compatible = "qcom,i2c-qup-v2.2.1"; 1759b190fb01SKonrad Dybcio reg = <0x0c1b5000 0x600>; 1760b190fb01SKonrad Dybcio interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 1761b190fb01SKonrad Dybcio 1762b190fb01SKonrad Dybcio clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, 1763b190fb01SKonrad Dybcio <&gcc GCC_BLSP2_AHB_CLK>; 1764b190fb01SKonrad Dybcio clock-names = "core", "iface"; 1765b190fb01SKonrad Dybcio clock-frequency = <400000>; 1766712e245fSKonrad Dybcio dmas = <&blsp2_dma 4>, <&blsp2_dma 5>; 1767712e245fSKonrad Dybcio dma-names = "tx", "rx"; 1768b190fb01SKonrad Dybcio 1769b190fb01SKonrad Dybcio pinctrl-names = "default", "sleep"; 1770b190fb01SKonrad Dybcio pinctrl-0 = <&i2c5_default>; 1771b190fb01SKonrad Dybcio pinctrl-1 = <&i2c5_sleep>; 1772b190fb01SKonrad Dybcio #address-cells = <1>; 1773b190fb01SKonrad Dybcio #size-cells = <0>; 1774b190fb01SKonrad Dybcio status = "disabled"; 1775b190fb01SKonrad Dybcio }; 1776b190fb01SKonrad Dybcio 1777b190fb01SKonrad Dybcio blsp_i2c6: i2c@c1b6000 { 1778b190fb01SKonrad Dybcio compatible = "qcom,i2c-qup-v2.2.1"; 1779b190fb01SKonrad Dybcio reg = <0x0c1b6000 0x600>; 1780b190fb01SKonrad Dybcio interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 1781b190fb01SKonrad Dybcio 1782b190fb01SKonrad Dybcio clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, 1783b190fb01SKonrad Dybcio <&gcc GCC_BLSP2_AHB_CLK>; 1784b190fb01SKonrad Dybcio clock-names = "core", "iface"; 1785b190fb01SKonrad Dybcio clock-frequency = <400000>; 1786712e245fSKonrad Dybcio dmas = <&blsp2_dma 6>, <&blsp2_dma 7>; 1787712e245fSKonrad Dybcio dma-names = "tx", "rx"; 1788b190fb01SKonrad Dybcio 1789b190fb01SKonrad Dybcio pinctrl-names = "default", "sleep"; 1790b190fb01SKonrad Dybcio pinctrl-0 = <&i2c6_default>; 1791b190fb01SKonrad Dybcio pinctrl-1 = <&i2c6_sleep>; 1792b190fb01SKonrad Dybcio #address-cells = <1>; 1793b190fb01SKonrad Dybcio #size-cells = <0>; 1794b190fb01SKonrad Dybcio status = "disabled"; 1795b190fb01SKonrad Dybcio }; 1796b190fb01SKonrad Dybcio 1797b190fb01SKonrad Dybcio blsp_i2c7: i2c@c1b7000 { 1798b190fb01SKonrad Dybcio compatible = "qcom,i2c-qup-v2.2.1"; 1799b190fb01SKonrad Dybcio reg = <0x0c1b7000 0x600>; 1800b190fb01SKonrad Dybcio interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 1801b190fb01SKonrad Dybcio 1802b190fb01SKonrad Dybcio clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>, 1803b190fb01SKonrad Dybcio <&gcc GCC_BLSP2_AHB_CLK>; 1804b190fb01SKonrad Dybcio clock-names = "core", "iface"; 1805b190fb01SKonrad Dybcio clock-frequency = <400000>; 1806712e245fSKonrad Dybcio dmas = <&blsp2_dma 8>, <&blsp2_dma 9>; 1807712e245fSKonrad Dybcio dma-names = "tx", "rx"; 1808b190fb01SKonrad Dybcio 1809b190fb01SKonrad Dybcio pinctrl-names = "default", "sleep"; 1810b190fb01SKonrad Dybcio pinctrl-0 = <&i2c7_default>; 1811b190fb01SKonrad Dybcio pinctrl-1 = <&i2c7_sleep>; 1812b190fb01SKonrad Dybcio #address-cells = <1>; 1813b190fb01SKonrad Dybcio #size-cells = <0>; 1814b190fb01SKonrad Dybcio status = "disabled"; 1815b190fb01SKonrad Dybcio }; 1816b190fb01SKonrad Dybcio 1817b190fb01SKonrad Dybcio blsp_i2c8: i2c@c1b8000 { 1818b190fb01SKonrad Dybcio compatible = "qcom,i2c-qup-v2.2.1"; 1819b190fb01SKonrad Dybcio reg = <0x0c1b8000 0x600>; 1820b190fb01SKonrad Dybcio interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 1821b190fb01SKonrad Dybcio 1822b190fb01SKonrad Dybcio clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>, 1823b190fb01SKonrad Dybcio <&gcc GCC_BLSP2_AHB_CLK>; 1824b190fb01SKonrad Dybcio clock-names = "core", "iface"; 1825b190fb01SKonrad Dybcio clock-frequency = <400000>; 1826712e245fSKonrad Dybcio dmas = <&blsp2_dma 10>, <&blsp2_dma 11>; 1827712e245fSKonrad Dybcio dma-names = "tx", "rx"; 1828b190fb01SKonrad Dybcio 1829b190fb01SKonrad Dybcio pinctrl-names = "default", "sleep"; 1830b190fb01SKonrad Dybcio pinctrl-0 = <&i2c8_default>; 1831b190fb01SKonrad Dybcio pinctrl-1 = <&i2c8_sleep>; 1832b190fb01SKonrad Dybcio #address-cells = <1>; 1833b190fb01SKonrad Dybcio #size-cells = <0>; 1834b190fb01SKonrad Dybcio status = "disabled"; 1835b190fb01SKonrad Dybcio }; 1836b190fb01SKonrad Dybcio 1837c21512cbSKonrad Dybcio imem@146bf000 { 1838c21512cbSKonrad Dybcio compatible = "simple-mfd"; 1839c21512cbSKonrad Dybcio reg = <0x146bf000 0x1000>; 1840c21512cbSKonrad Dybcio 1841c21512cbSKonrad Dybcio #address-cells = <1>; 1842c21512cbSKonrad Dybcio #size-cells = <1>; 1843c21512cbSKonrad Dybcio 1844c21512cbSKonrad Dybcio ranges = <0 0x146bf000 0x1000>; 1845c21512cbSKonrad Dybcio 1846c21512cbSKonrad Dybcio pil-reloc@94c { 1847c21512cbSKonrad Dybcio compatible = "qcom,pil-reloc-info"; 1848c21512cbSKonrad Dybcio reg = <0x94c 0xc8>; 1849c21512cbSKonrad Dybcio }; 1850c21512cbSKonrad Dybcio }; 1851c21512cbSKonrad Dybcio 1852f3d5d3ccSAngeloGioacchino Del Regno camss: camss@ca00000 { 1853f3d5d3ccSAngeloGioacchino Del Regno compatible = "qcom,sdm660-camss"; 18547908dcc8SKrzysztof Kozlowski reg = <0x0ca00020 0x10>, 18557908dcc8SKrzysztof Kozlowski <0x0ca30000 0x100>, 18567908dcc8SKrzysztof Kozlowski <0x0ca30400 0x100>, 18577908dcc8SKrzysztof Kozlowski <0x0ca30800 0x100>, 18587908dcc8SKrzysztof Kozlowski <0x0ca30c00 0x100>, 18597908dcc8SKrzysztof Kozlowski <0x0c824000 0x1000>, 1860f3d5d3ccSAngeloGioacchino Del Regno <0x0ca00120 0x4>, 1861f3d5d3ccSAngeloGioacchino Del Regno <0x0c825000 0x1000>, 1862f3d5d3ccSAngeloGioacchino Del Regno <0x0ca00124 0x4>, 1863f3d5d3ccSAngeloGioacchino Del Regno <0x0c826000 0x1000>, 1864f3d5d3ccSAngeloGioacchino Del Regno <0x0ca00128 0x4>, 1865f3d5d3ccSAngeloGioacchino Del Regno <0x0ca31000 0x500>, 1866f3d5d3ccSAngeloGioacchino Del Regno <0x0ca10000 0x1000>, 1867f3d5d3ccSAngeloGioacchino Del Regno <0x0ca14000 0x1000>; 18687908dcc8SKrzysztof Kozlowski reg-names = "csi_clk_mux", 18697908dcc8SKrzysztof Kozlowski "csid0", 18707908dcc8SKrzysztof Kozlowski "csid1", 18717908dcc8SKrzysztof Kozlowski "csid2", 18727908dcc8SKrzysztof Kozlowski "csid3", 18737908dcc8SKrzysztof Kozlowski "csiphy0", 1874f3d5d3ccSAngeloGioacchino Del Regno "csiphy0_clk_mux", 1875f3d5d3ccSAngeloGioacchino Del Regno "csiphy1", 1876f3d5d3ccSAngeloGioacchino Del Regno "csiphy1_clk_mux", 1877f3d5d3ccSAngeloGioacchino Del Regno "csiphy2", 1878f3d5d3ccSAngeloGioacchino Del Regno "csiphy2_clk_mux", 1879f3d5d3ccSAngeloGioacchino Del Regno "ispif", 1880f3d5d3ccSAngeloGioacchino Del Regno "vfe0", 1881f3d5d3ccSAngeloGioacchino Del Regno "vfe1"; 1882cb0b6853SKrzysztof Kozlowski interrupts = <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>, 1883f3d5d3ccSAngeloGioacchino Del Regno <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>, 1884f3d5d3ccSAngeloGioacchino Del Regno <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>, 1885f3d5d3ccSAngeloGioacchino Del Regno <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>, 1886cb0b6853SKrzysztof Kozlowski <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>, 1887cb0b6853SKrzysztof Kozlowski <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>, 1888cb0b6853SKrzysztof Kozlowski <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>, 1889f3d5d3ccSAngeloGioacchino Del Regno <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>, 1890f3d5d3ccSAngeloGioacchino Del Regno <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>, 1891f3d5d3ccSAngeloGioacchino Del Regno <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>; 1892cb0b6853SKrzysztof Kozlowski interrupt-names = "csid0", 1893f3d5d3ccSAngeloGioacchino Del Regno "csid1", 1894f3d5d3ccSAngeloGioacchino Del Regno "csid2", 1895f3d5d3ccSAngeloGioacchino Del Regno "csid3", 1896cb0b6853SKrzysztof Kozlowski "csiphy0", 1897cb0b6853SKrzysztof Kozlowski "csiphy1", 1898cb0b6853SKrzysztof Kozlowski "csiphy2", 1899f3d5d3ccSAngeloGioacchino Del Regno "ispif", 1900f3d5d3ccSAngeloGioacchino Del Regno "vfe0", 1901f3d5d3ccSAngeloGioacchino Del Regno "vfe1"; 1902e8881372SKrzysztof Kozlowski clocks = <&mmcc CAMSS_AHB_CLK>, 1903e8881372SKrzysztof Kozlowski <&mmcc CAMSS_CPHY_CSID0_CLK>, 1904e8881372SKrzysztof Kozlowski <&mmcc CAMSS_CPHY_CSID1_CLK>, 1905e8881372SKrzysztof Kozlowski <&mmcc CAMSS_CPHY_CSID2_CLK>, 1906e8881372SKrzysztof Kozlowski <&mmcc CAMSS_CPHY_CSID3_CLK>, 1907f3d5d3ccSAngeloGioacchino Del Regno <&mmcc CAMSS_CSI0_AHB_CLK>, 1908f3d5d3ccSAngeloGioacchino Del Regno <&mmcc CAMSS_CSI0_CLK>, 1909f3d5d3ccSAngeloGioacchino Del Regno <&mmcc CAMSS_CPHY_CSID0_CLK>, 1910f3d5d3ccSAngeloGioacchino Del Regno <&mmcc CAMSS_CSI0PIX_CLK>, 1911f3d5d3ccSAngeloGioacchino Del Regno <&mmcc CAMSS_CSI0RDI_CLK>, 1912f3d5d3ccSAngeloGioacchino Del Regno <&mmcc CAMSS_CSI1_AHB_CLK>, 1913f3d5d3ccSAngeloGioacchino Del Regno <&mmcc CAMSS_CSI1_CLK>, 1914f3d5d3ccSAngeloGioacchino Del Regno <&mmcc CAMSS_CPHY_CSID1_CLK>, 1915f3d5d3ccSAngeloGioacchino Del Regno <&mmcc CAMSS_CSI1PIX_CLK>, 1916f3d5d3ccSAngeloGioacchino Del Regno <&mmcc CAMSS_CSI1RDI_CLK>, 1917f3d5d3ccSAngeloGioacchino Del Regno <&mmcc CAMSS_CSI2_AHB_CLK>, 1918f3d5d3ccSAngeloGioacchino Del Regno <&mmcc CAMSS_CSI2_CLK>, 1919f3d5d3ccSAngeloGioacchino Del Regno <&mmcc CAMSS_CPHY_CSID2_CLK>, 1920f3d5d3ccSAngeloGioacchino Del Regno <&mmcc CAMSS_CSI2PIX_CLK>, 1921f3d5d3ccSAngeloGioacchino Del Regno <&mmcc CAMSS_CSI2RDI_CLK>, 1922f3d5d3ccSAngeloGioacchino Del Regno <&mmcc CAMSS_CSI3_AHB_CLK>, 1923f3d5d3ccSAngeloGioacchino Del Regno <&mmcc CAMSS_CSI3_CLK>, 1924f3d5d3ccSAngeloGioacchino Del Regno <&mmcc CAMSS_CPHY_CSID3_CLK>, 1925f3d5d3ccSAngeloGioacchino Del Regno <&mmcc CAMSS_CSI3PIX_CLK>, 1926f3d5d3ccSAngeloGioacchino Del Regno <&mmcc CAMSS_CSI3RDI_CLK>, 1927e8881372SKrzysztof Kozlowski <&mmcc CAMSS_CSI0PHYTIMER_CLK>, 1928e8881372SKrzysztof Kozlowski <&mmcc CAMSS_CSI1PHYTIMER_CLK>, 1929e8881372SKrzysztof Kozlowski <&mmcc CAMSS_CSI2PHYTIMER_CLK>, 1930e8881372SKrzysztof Kozlowski <&mmcc CSIPHY_AHB2CRIF_CLK>, 1931f3d5d3ccSAngeloGioacchino Del Regno <&mmcc CAMSS_CSI_VFE0_CLK>, 1932f3d5d3ccSAngeloGioacchino Del Regno <&mmcc CAMSS_CSI_VFE1_CLK>, 1933e8881372SKrzysztof Kozlowski <&mmcc CAMSS_ISPIF_AHB_CLK>, 1934e8881372SKrzysztof Kozlowski <&mmcc THROTTLE_CAMSS_AXI_CLK>, 1935e8881372SKrzysztof Kozlowski <&mmcc CAMSS_TOP_AHB_CLK>, 1936e8881372SKrzysztof Kozlowski <&mmcc CAMSS_VFE0_AHB_CLK>, 1937e8881372SKrzysztof Kozlowski <&mmcc CAMSS_VFE0_CLK>, 1938e8881372SKrzysztof Kozlowski <&mmcc CAMSS_VFE0_STREAM_CLK>, 1939f3d5d3ccSAngeloGioacchino Del Regno <&mmcc CAMSS_VFE1_AHB_CLK>, 1940e8881372SKrzysztof Kozlowski <&mmcc CAMSS_VFE1_CLK>, 1941f3d5d3ccSAngeloGioacchino Del Regno <&mmcc CAMSS_VFE1_STREAM_CLK>, 1942f3d5d3ccSAngeloGioacchino Del Regno <&mmcc CAMSS_VFE_VBIF_AHB_CLK>, 1943e8881372SKrzysztof Kozlowski <&mmcc CAMSS_VFE_VBIF_AXI_CLK>; 1944e8881372SKrzysztof Kozlowski clock-names = "ahb", 1945e8881372SKrzysztof Kozlowski "cphy_csid0", 1946e8881372SKrzysztof Kozlowski "cphy_csid1", 1947e8881372SKrzysztof Kozlowski "cphy_csid2", 1948e8881372SKrzysztof Kozlowski "cphy_csid3", 1949f3d5d3ccSAngeloGioacchino Del Regno "csi0_ahb", 1950f3d5d3ccSAngeloGioacchino Del Regno "csi0", 1951f3d5d3ccSAngeloGioacchino Del Regno "csi0_phy", 1952f3d5d3ccSAngeloGioacchino Del Regno "csi0_pix", 1953f3d5d3ccSAngeloGioacchino Del Regno "csi0_rdi", 1954f3d5d3ccSAngeloGioacchino Del Regno "csi1_ahb", 1955f3d5d3ccSAngeloGioacchino Del Regno "csi1", 1956f3d5d3ccSAngeloGioacchino Del Regno "csi1_phy", 1957f3d5d3ccSAngeloGioacchino Del Regno "csi1_pix", 1958f3d5d3ccSAngeloGioacchino Del Regno "csi1_rdi", 1959f3d5d3ccSAngeloGioacchino Del Regno "csi2_ahb", 1960f3d5d3ccSAngeloGioacchino Del Regno "csi2", 1961f3d5d3ccSAngeloGioacchino Del Regno "csi2_phy", 1962f3d5d3ccSAngeloGioacchino Del Regno "csi2_pix", 1963f3d5d3ccSAngeloGioacchino Del Regno "csi2_rdi", 1964f3d5d3ccSAngeloGioacchino Del Regno "csi3_ahb", 1965f3d5d3ccSAngeloGioacchino Del Regno "csi3", 1966f3d5d3ccSAngeloGioacchino Del Regno "csi3_phy", 1967f3d5d3ccSAngeloGioacchino Del Regno "csi3_pix", 1968f3d5d3ccSAngeloGioacchino Del Regno "csi3_rdi", 1969e8881372SKrzysztof Kozlowski "csiphy0_timer", 1970e8881372SKrzysztof Kozlowski "csiphy1_timer", 1971e8881372SKrzysztof Kozlowski "csiphy2_timer", 1972e8881372SKrzysztof Kozlowski "csiphy_ahb2crif", 1973f3d5d3ccSAngeloGioacchino Del Regno "csi_vfe0", 1974f3d5d3ccSAngeloGioacchino Del Regno "csi_vfe1", 1975e8881372SKrzysztof Kozlowski "ispif_ahb", 1976e8881372SKrzysztof Kozlowski "throttle_axi", 1977e8881372SKrzysztof Kozlowski "top_ahb", 1978e8881372SKrzysztof Kozlowski "vfe0_ahb", 1979e8881372SKrzysztof Kozlowski "vfe0", 1980e8881372SKrzysztof Kozlowski "vfe0_stream", 1981f3d5d3ccSAngeloGioacchino Del Regno "vfe1_ahb", 1982e8881372SKrzysztof Kozlowski "vfe1", 1983f3d5d3ccSAngeloGioacchino Del Regno "vfe1_stream", 1984f3d5d3ccSAngeloGioacchino Del Regno "vfe_ahb", 1985e8881372SKrzysztof Kozlowski "vfe_axi"; 1986f3d5d3ccSAngeloGioacchino Del Regno interconnects = <&mnoc 5 &bimc 5>; 1987f3d5d3ccSAngeloGioacchino Del Regno interconnect-names = "vfe-mem"; 1988f3d5d3ccSAngeloGioacchino Del Regno iommus = <&mmss_smmu 0xc00>, 1989f3d5d3ccSAngeloGioacchino Del Regno <&mmss_smmu 0xc01>, 1990f3d5d3ccSAngeloGioacchino Del Regno <&mmss_smmu 0xc02>, 1991f3d5d3ccSAngeloGioacchino Del Regno <&mmss_smmu 0xc03>; 1992f3d5d3ccSAngeloGioacchino Del Regno power-domains = <&mmcc CAMSS_VFE0_GDSC>, 1993f3d5d3ccSAngeloGioacchino Del Regno <&mmcc CAMSS_VFE1_GDSC>; 1994f3d5d3ccSAngeloGioacchino Del Regno status = "disabled"; 1995f3d5d3ccSAngeloGioacchino Del Regno 1996f3d5d3ccSAngeloGioacchino Del Regno ports { 1997f3d5d3ccSAngeloGioacchino Del Regno #address-cells = <1>; 1998f3d5d3ccSAngeloGioacchino Del Regno #size-cells = <0>; 1999f3d5d3ccSAngeloGioacchino Del Regno }; 2000f3d5d3ccSAngeloGioacchino Del Regno }; 2001f3d5d3ccSAngeloGioacchino Del Regno 2002f3d5d3ccSAngeloGioacchino Del Regno cci: cci@ca0c000 { 2003f3d5d3ccSAngeloGioacchino Del Regno compatible = "qcom,msm8996-cci"; 2004f3d5d3ccSAngeloGioacchino Del Regno #address-cells = <1>; 2005f3d5d3ccSAngeloGioacchino Del Regno #size-cells = <0>; 2006f3d5d3ccSAngeloGioacchino Del Regno reg = <0x0ca0c000 0x1000>; 2007f3d5d3ccSAngeloGioacchino Del Regno interrupts = <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>; 2008f3d5d3ccSAngeloGioacchino Del Regno 2009f3d5d3ccSAngeloGioacchino Del Regno assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>, 2010f3d5d3ccSAngeloGioacchino Del Regno <&mmcc CAMSS_CCI_CLK>; 2011f3d5d3ccSAngeloGioacchino Del Regno assigned-clock-rates = <80800000>, <37500000>; 2012f3d5d3ccSAngeloGioacchino Del Regno clocks = <&mmcc CAMSS_TOP_AHB_CLK>, 2013f3d5d3ccSAngeloGioacchino Del Regno <&mmcc CAMSS_CCI_AHB_CLK>, 2014f3d5d3ccSAngeloGioacchino Del Regno <&mmcc CAMSS_CCI_CLK>, 2015f3d5d3ccSAngeloGioacchino Del Regno <&mmcc CAMSS_AHB_CLK>; 2016f3d5d3ccSAngeloGioacchino Del Regno clock-names = "camss_top_ahb", 2017f3d5d3ccSAngeloGioacchino Del Regno "cci_ahb", 2018f3d5d3ccSAngeloGioacchino Del Regno "cci", 2019f3d5d3ccSAngeloGioacchino Del Regno "camss_ahb"; 2020f3d5d3ccSAngeloGioacchino Del Regno 2021f3d5d3ccSAngeloGioacchino Del Regno pinctrl-names = "default"; 2022f3d5d3ccSAngeloGioacchino Del Regno pinctrl-0 = <&cci0_default &cci1_default>; 2023f3d5d3ccSAngeloGioacchino Del Regno power-domains = <&mmcc CAMSS_TOP_GDSC>; 2024f3d5d3ccSAngeloGioacchino Del Regno status = "disabled"; 2025f3d5d3ccSAngeloGioacchino Del Regno 2026f3d5d3ccSAngeloGioacchino Del Regno cci_i2c0: i2c-bus@0 { 2027f3d5d3ccSAngeloGioacchino Del Regno reg = <0>; 2028f3d5d3ccSAngeloGioacchino Del Regno clock-frequency = <400000>; 2029f3d5d3ccSAngeloGioacchino Del Regno #address-cells = <1>; 2030f3d5d3ccSAngeloGioacchino Del Regno #size-cells = <0>; 2031f3d5d3ccSAngeloGioacchino Del Regno }; 2032f3d5d3ccSAngeloGioacchino Del Regno 2033f3d5d3ccSAngeloGioacchino Del Regno cci_i2c1: i2c-bus@1 { 2034f3d5d3ccSAngeloGioacchino Del Regno reg = <1>; 2035f3d5d3ccSAngeloGioacchino Del Regno clock-frequency = <400000>; 2036f3d5d3ccSAngeloGioacchino Del Regno #address-cells = <1>; 2037f3d5d3ccSAngeloGioacchino Del Regno #size-cells = <0>; 2038f3d5d3ccSAngeloGioacchino Del Regno }; 2039f3d5d3ccSAngeloGioacchino Del Regno }; 2040f3d5d3ccSAngeloGioacchino Del Regno 2041f468ecf1SAngeloGioacchino Del Regno venus: video-codec@cc00000 { 2042f468ecf1SAngeloGioacchino Del Regno compatible = "qcom,sdm660-venus"; 2043f468ecf1SAngeloGioacchino Del Regno reg = <0x0cc00000 0xff000>; 2044f468ecf1SAngeloGioacchino Del Regno clocks = <&mmcc VIDEO_CORE_CLK>, 2045f468ecf1SAngeloGioacchino Del Regno <&mmcc VIDEO_AHB_CLK>, 2046f468ecf1SAngeloGioacchino Del Regno <&mmcc VIDEO_AXI_CLK>, 2047f468ecf1SAngeloGioacchino Del Regno <&mmcc THROTTLE_VIDEO_AXI_CLK>; 2048f468ecf1SAngeloGioacchino Del Regno clock-names = "core", "iface", "bus", "bus_throttle"; 2049f468ecf1SAngeloGioacchino Del Regno interconnects = <&gnoc 0 &mnoc 13>, 2050f468ecf1SAngeloGioacchino Del Regno <&mnoc 4 &bimc 5>; 2051f468ecf1SAngeloGioacchino Del Regno interconnect-names = "cpu-cfg", "video-mem"; 2052f468ecf1SAngeloGioacchino Del Regno interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 2053f468ecf1SAngeloGioacchino Del Regno iommus = <&mmss_smmu 0x400>, 2054f468ecf1SAngeloGioacchino Del Regno <&mmss_smmu 0x401>, 2055f468ecf1SAngeloGioacchino Del Regno <&mmss_smmu 0x40a>, 2056f468ecf1SAngeloGioacchino Del Regno <&mmss_smmu 0x407>, 2057f468ecf1SAngeloGioacchino Del Regno <&mmss_smmu 0x40e>, 2058f468ecf1SAngeloGioacchino Del Regno <&mmss_smmu 0x40f>, 2059f468ecf1SAngeloGioacchino Del Regno <&mmss_smmu 0x408>, 2060f468ecf1SAngeloGioacchino Del Regno <&mmss_smmu 0x409>, 2061f468ecf1SAngeloGioacchino Del Regno <&mmss_smmu 0x40b>, 2062f468ecf1SAngeloGioacchino Del Regno <&mmss_smmu 0x40c>, 2063f468ecf1SAngeloGioacchino Del Regno <&mmss_smmu 0x40d>, 2064f468ecf1SAngeloGioacchino Del Regno <&mmss_smmu 0x410>, 2065f468ecf1SAngeloGioacchino Del Regno <&mmss_smmu 0x421>, 2066f468ecf1SAngeloGioacchino Del Regno <&mmss_smmu 0x428>, 2067f468ecf1SAngeloGioacchino Del Regno <&mmss_smmu 0x429>, 2068f468ecf1SAngeloGioacchino Del Regno <&mmss_smmu 0x42b>, 2069f468ecf1SAngeloGioacchino Del Regno <&mmss_smmu 0x42c>, 2070f468ecf1SAngeloGioacchino Del Regno <&mmss_smmu 0x42d>, 2071f468ecf1SAngeloGioacchino Del Regno <&mmss_smmu 0x411>, 2072f468ecf1SAngeloGioacchino Del Regno <&mmss_smmu 0x431>; 2073f468ecf1SAngeloGioacchino Del Regno memory-region = <&venus_region>; 2074f468ecf1SAngeloGioacchino Del Regno power-domains = <&mmcc VENUS_GDSC>; 2075f468ecf1SAngeloGioacchino Del Regno status = "disabled"; 2076f468ecf1SAngeloGioacchino Del Regno 2077f468ecf1SAngeloGioacchino Del Regno video-decoder { 2078f468ecf1SAngeloGioacchino Del Regno compatible = "venus-decoder"; 2079f468ecf1SAngeloGioacchino Del Regno clocks = <&mmcc VIDEO_SUBCORE0_CLK>; 2080f468ecf1SAngeloGioacchino Del Regno clock-names = "vcodec0_core"; 2081f468ecf1SAngeloGioacchino Del Regno power-domains = <&mmcc VENUS_CORE0_GDSC>; 2082f468ecf1SAngeloGioacchino Del Regno }; 2083f468ecf1SAngeloGioacchino Del Regno 2084f468ecf1SAngeloGioacchino Del Regno video-encoder { 2085f468ecf1SAngeloGioacchino Del Regno compatible = "venus-encoder"; 2086f468ecf1SAngeloGioacchino Del Regno clocks = <&mmcc VIDEO_SUBCORE0_CLK>; 2087f468ecf1SAngeloGioacchino Del Regno clock-names = "vcodec0_core"; 2088f468ecf1SAngeloGioacchino Del Regno power-domains = <&mmcc VENUS_CORE0_GDSC>; 2089f468ecf1SAngeloGioacchino Del Regno }; 2090f468ecf1SAngeloGioacchino Del Regno }; 2091f468ecf1SAngeloGioacchino Del Regno 2092b190fb01SKonrad Dybcio mmss_smmu: iommu@cd00000 { 2093b190fb01SKonrad Dybcio compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2"; 2094b190fb01SKonrad Dybcio reg = <0x0cd00000 0x40000>; 20956bb717feSAngeloGioacchino Del Regno 20966bb717feSAngeloGioacchino Del Regno clocks = <&mmcc MNOC_AHB_CLK>, 20976bb717feSAngeloGioacchino Del Regno <&mmcc BIMC_SMMU_AHB_CLK>, 20986bb717feSAngeloGioacchino Del Regno <&rpmcc RPM_SMD_MMSSNOC_AXI_CLK>, 20996bb717feSAngeloGioacchino Del Regno <&mmcc BIMC_SMMU_AXI_CLK>; 21006bb717feSAngeloGioacchino Del Regno clock-names = "iface-mm", "iface-smmu", 21016bb717feSAngeloGioacchino Del Regno "bus-mm", "bus-smmu"; 21026bb717feSAngeloGioacchino Del Regno #global-interrupts = <2>; 2103b190fb01SKonrad Dybcio #iommu-cells = <1>; 2104b190fb01SKonrad Dybcio 2105b190fb01SKonrad Dybcio interrupts = 2106b190fb01SKonrad Dybcio <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 2107b190fb01SKonrad Dybcio <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 2108b190fb01SKonrad Dybcio 2109b190fb01SKonrad Dybcio <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 2110b190fb01SKonrad Dybcio <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 2111b190fb01SKonrad Dybcio <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, 2112b190fb01SKonrad Dybcio <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 2113b190fb01SKonrad Dybcio <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 2114b190fb01SKonrad Dybcio <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 2115b190fb01SKonrad Dybcio <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 2116b190fb01SKonrad Dybcio <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 2117b190fb01SKonrad Dybcio <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 2118b190fb01SKonrad Dybcio <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 2119b190fb01SKonrad Dybcio <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 2120b190fb01SKonrad Dybcio <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 2121b190fb01SKonrad Dybcio <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 2122b190fb01SKonrad Dybcio <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 2123b190fb01SKonrad Dybcio <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 2124b190fb01SKonrad Dybcio <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 2125b190fb01SKonrad Dybcio <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 2126b190fb01SKonrad Dybcio <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 2127b190fb01SKonrad Dybcio <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 2128b190fb01SKonrad Dybcio <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, 2129b190fb01SKonrad Dybcio <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, 2130b190fb01SKonrad Dybcio <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 2131b190fb01SKonrad Dybcio <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 2132b190fb01SKonrad Dybcio <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>; 2133326407d2SKonrad Dybcio 2134326407d2SKonrad Dybcio status = "disabled"; 2135b190fb01SKonrad Dybcio }; 2136b190fb01SKonrad Dybcio 21377ca2ebc9SKonrad Dybcio adsp_pil: remoteproc@15700000 { 21387ca2ebc9SKonrad Dybcio compatible = "qcom,sdm660-adsp-pas"; 21397ca2ebc9SKonrad Dybcio reg = <0x15700000 0x4040>; 21407ca2ebc9SKonrad Dybcio 21417ca2ebc9SKonrad Dybcio interrupts-extended = 21427ca2ebc9SKonrad Dybcio <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 21437ca2ebc9SKonrad Dybcio <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 21447ca2ebc9SKonrad Dybcio <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 21457ca2ebc9SKonrad Dybcio <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 21467ca2ebc9SKonrad Dybcio <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 21477ca2ebc9SKonrad Dybcio interrupt-names = "wdog", "fatal", "ready", 21487ca2ebc9SKonrad Dybcio "handover", "stop-ack"; 21497ca2ebc9SKonrad Dybcio 21507ca2ebc9SKonrad Dybcio clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 21517ca2ebc9SKonrad Dybcio clock-names = "xo"; 21527ca2ebc9SKonrad Dybcio 21537ca2ebc9SKonrad Dybcio memory-region = <&adsp_region>; 21547ca2ebc9SKonrad Dybcio power-domains = <&rpmpd SDM660_VDDCX>; 21557ca2ebc9SKonrad Dybcio power-domain-names = "cx"; 21567ca2ebc9SKonrad Dybcio 21577ca2ebc9SKonrad Dybcio qcom,smem-states = <&adsp_smp2p_out 0>; 21587ca2ebc9SKonrad Dybcio qcom,smem-state-names = "stop"; 21597ca2ebc9SKonrad Dybcio 21607ca2ebc9SKonrad Dybcio glink-edge { 21617ca2ebc9SKonrad Dybcio interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>; 21627ca2ebc9SKonrad Dybcio 21637ca2ebc9SKonrad Dybcio label = "lpass"; 21647ca2ebc9SKonrad Dybcio mboxes = <&apcs_glb 9>; 21657ca2ebc9SKonrad Dybcio qcom,remote-pid = <2>; 21667ca2ebc9SKonrad Dybcio #address-cells = <1>; 21677ca2ebc9SKonrad Dybcio #size-cells = <0>; 21687ca2ebc9SKonrad Dybcio 21697ca2ebc9SKonrad Dybcio apr { 21707ca2ebc9SKonrad Dybcio compatible = "qcom,apr-v2"; 21717ca2ebc9SKonrad Dybcio qcom,glink-channels = "apr_audio_svc"; 21722f114511SDavid Heidelberg qcom,domain = <APR_DOMAIN_ADSP>; 21737ca2ebc9SKonrad Dybcio #address-cells = <1>; 21747ca2ebc9SKonrad Dybcio #size-cells = <0>; 21757ca2ebc9SKonrad Dybcio 21767ca2ebc9SKonrad Dybcio q6core { 21777ca2ebc9SKonrad Dybcio reg = <APR_SVC_ADSP_CORE>; 21787ca2ebc9SKonrad Dybcio compatible = "qcom,q6core"; 21797ca2ebc9SKonrad Dybcio }; 21807ca2ebc9SKonrad Dybcio 21817ca2ebc9SKonrad Dybcio q6afe: apr-service@4 { 21827ca2ebc9SKonrad Dybcio compatible = "qcom,q6afe"; 21837ca2ebc9SKonrad Dybcio reg = <APR_SVC_AFE>; 21847ca2ebc9SKonrad Dybcio q6afedai: dais { 21857ca2ebc9SKonrad Dybcio compatible = "qcom,q6afe-dais"; 21867ca2ebc9SKonrad Dybcio #address-cells = <1>; 21877ca2ebc9SKonrad Dybcio #size-cells = <0>; 21887ca2ebc9SKonrad Dybcio #sound-dai-cells = <1>; 21897ca2ebc9SKonrad Dybcio }; 21907ca2ebc9SKonrad Dybcio }; 21917ca2ebc9SKonrad Dybcio 21927ca2ebc9SKonrad Dybcio q6asm: apr-service@7 { 21937ca2ebc9SKonrad Dybcio compatible = "qcom,q6asm"; 21947ca2ebc9SKonrad Dybcio reg = <APR_SVC_ASM>; 21957ca2ebc9SKonrad Dybcio q6asmdai: dais { 21967ca2ebc9SKonrad Dybcio compatible = "qcom,q6asm-dais"; 21977ca2ebc9SKonrad Dybcio #address-cells = <1>; 21987ca2ebc9SKonrad Dybcio #size-cells = <0>; 21997ca2ebc9SKonrad Dybcio #sound-dai-cells = <1>; 22007ca2ebc9SKonrad Dybcio iommus = <&lpass_smmu 1>; 22017ca2ebc9SKonrad Dybcio }; 22027ca2ebc9SKonrad Dybcio }; 22037ca2ebc9SKonrad Dybcio 22047ca2ebc9SKonrad Dybcio q6adm: apr-service@8 { 22057ca2ebc9SKonrad Dybcio compatible = "qcom,q6adm"; 22067ca2ebc9SKonrad Dybcio reg = <APR_SVC_ADM>; 22077ca2ebc9SKonrad Dybcio q6routing: routing { 22087ca2ebc9SKonrad Dybcio compatible = "qcom,q6adm-routing"; 22097ca2ebc9SKonrad Dybcio #sound-dai-cells = <0>; 22107ca2ebc9SKonrad Dybcio }; 22117ca2ebc9SKonrad Dybcio }; 22127ca2ebc9SKonrad Dybcio }; 22137ca2ebc9SKonrad Dybcio }; 22147ca2ebc9SKonrad Dybcio }; 22157ca2ebc9SKonrad Dybcio 2216045547a0SKonrad Dybcio gnoc: interconnect@17900000 { 2217045547a0SKonrad Dybcio compatible = "qcom,sdm660-gnoc"; 2218045547a0SKonrad Dybcio reg = <0x17900000 0xe000>; 2219045547a0SKonrad Dybcio #interconnect-cells = <1>; 2220045547a0SKonrad Dybcio /* 2221045547a0SKonrad Dybcio * This one apparently features no clocks, 2222045547a0SKonrad Dybcio * so let's not mess with the driver needlessly 2223045547a0SKonrad Dybcio */ 2224045547a0SKonrad Dybcio clock-names = "bus", "bus_a"; 2225045547a0SKonrad Dybcio clocks = <&xo_board>, <&xo_board>; 2226045547a0SKonrad Dybcio }; 2227045547a0SKonrad Dybcio 2228b190fb01SKonrad Dybcio apcs_glb: mailbox@17911000 { 2229b190fb01SKonrad Dybcio compatible = "qcom,sdm660-apcs-hmss-global"; 2230b190fb01SKonrad Dybcio reg = <0x17911000 0x1000>; 2231b190fb01SKonrad Dybcio 2232b190fb01SKonrad Dybcio #mbox-cells = <1>; 2233b190fb01SKonrad Dybcio }; 2234b190fb01SKonrad Dybcio 2235b190fb01SKonrad Dybcio timer@17920000 { 2236b190fb01SKonrad Dybcio #address-cells = <1>; 2237b190fb01SKonrad Dybcio #size-cells = <1>; 2238b190fb01SKonrad Dybcio ranges; 2239b190fb01SKonrad Dybcio compatible = "arm,armv7-timer-mem"; 2240b190fb01SKonrad Dybcio reg = <0x17920000 0x1000>; 2241b190fb01SKonrad Dybcio clock-frequency = <19200000>; 2242b190fb01SKonrad Dybcio 2243b190fb01SKonrad Dybcio frame@17921000 { 2244b190fb01SKonrad Dybcio frame-number = <0>; 2245b190fb01SKonrad Dybcio interrupts = <0 8 0x4>, 2246b190fb01SKonrad Dybcio <0 7 0x4>; 2247b190fb01SKonrad Dybcio reg = <0x17921000 0x1000>, 2248b190fb01SKonrad Dybcio <0x17922000 0x1000>; 2249b190fb01SKonrad Dybcio }; 2250b190fb01SKonrad Dybcio 2251b190fb01SKonrad Dybcio frame@17923000 { 2252b190fb01SKonrad Dybcio frame-number = <1>; 2253b190fb01SKonrad Dybcio interrupts = <0 9 0x4>; 2254b190fb01SKonrad Dybcio reg = <0x17923000 0x1000>; 2255b190fb01SKonrad Dybcio status = "disabled"; 2256b190fb01SKonrad Dybcio }; 2257b190fb01SKonrad Dybcio 2258b190fb01SKonrad Dybcio frame@17924000 { 2259b190fb01SKonrad Dybcio frame-number = <2>; 2260b190fb01SKonrad Dybcio interrupts = <0 10 0x4>; 2261b190fb01SKonrad Dybcio reg = <0x17924000 0x1000>; 2262b190fb01SKonrad Dybcio status = "disabled"; 2263b190fb01SKonrad Dybcio }; 2264b190fb01SKonrad Dybcio 2265b190fb01SKonrad Dybcio frame@17925000 { 2266b190fb01SKonrad Dybcio frame-number = <3>; 2267b190fb01SKonrad Dybcio interrupts = <0 11 0x4>; 2268b190fb01SKonrad Dybcio reg = <0x17925000 0x1000>; 2269b190fb01SKonrad Dybcio status = "disabled"; 2270b190fb01SKonrad Dybcio }; 2271b190fb01SKonrad Dybcio 2272b190fb01SKonrad Dybcio frame@17926000 { 2273b190fb01SKonrad Dybcio frame-number = <4>; 2274b190fb01SKonrad Dybcio interrupts = <0 12 0x4>; 2275b190fb01SKonrad Dybcio reg = <0x17926000 0x1000>; 2276b190fb01SKonrad Dybcio status = "disabled"; 2277b190fb01SKonrad Dybcio }; 2278b190fb01SKonrad Dybcio 2279b190fb01SKonrad Dybcio frame@17927000 { 2280b190fb01SKonrad Dybcio frame-number = <5>; 2281b190fb01SKonrad Dybcio interrupts = <0 13 0x4>; 2282b190fb01SKonrad Dybcio reg = <0x17927000 0x1000>; 2283b190fb01SKonrad Dybcio status = "disabled"; 2284b190fb01SKonrad Dybcio }; 2285b190fb01SKonrad Dybcio 2286b190fb01SKonrad Dybcio frame@17928000 { 2287b190fb01SKonrad Dybcio frame-number = <6>; 2288b190fb01SKonrad Dybcio interrupts = <0 14 0x4>; 2289b190fb01SKonrad Dybcio reg = <0x17928000 0x1000>; 2290b190fb01SKonrad Dybcio status = "disabled"; 2291b190fb01SKonrad Dybcio }; 2292b190fb01SKonrad Dybcio }; 2293b190fb01SKonrad Dybcio 2294b190fb01SKonrad Dybcio intc: interrupt-controller@17a00000 { 2295b190fb01SKonrad Dybcio compatible = "arm,gic-v3"; 2296b190fb01SKonrad Dybcio reg = <0x17a00000 0x10000>, /* GICD */ 2297b190fb01SKonrad Dybcio <0x17b00000 0x100000>; /* GICR * 8 */ 2298b190fb01SKonrad Dybcio #interrupt-cells = <3>; 2299b190fb01SKonrad Dybcio #address-cells = <1>; 2300b190fb01SKonrad Dybcio #size-cells = <1>; 2301b190fb01SKonrad Dybcio ranges; 2302b190fb01SKonrad Dybcio interrupt-controller; 2303b190fb01SKonrad Dybcio #redistributor-regions = <1>; 2304b190fb01SKonrad Dybcio redistributor-stride = <0x0 0x20000>; 2305b190fb01SKonrad Dybcio interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 2306b190fb01SKonrad Dybcio }; 2307b190fb01SKonrad Dybcio }; 2308b190fb01SKonrad Dybcio 2309b190fb01SKonrad Dybcio tcsr_mutex: hwlock { 2310b190fb01SKonrad Dybcio compatible = "qcom,tcsr-mutex"; 2311b190fb01SKonrad Dybcio syscon = <&tcsr_mutex_regs 0 0x1000>; 2312b190fb01SKonrad Dybcio #hwlock-cells = <1>; 2313b190fb01SKonrad Dybcio }; 2314b190fb01SKonrad Dybcio 23157ca2ebc9SKonrad Dybcio sound: sound { 23167ca2ebc9SKonrad Dybcio }; 23177ca2ebc9SKonrad Dybcio 23183332c596SKonrad Dybcio thermal-zones { 23193332c596SKonrad Dybcio aoss-thermal { 23203332c596SKonrad Dybcio polling-delay-passive = <250>; 23213332c596SKonrad Dybcio polling-delay = <1000>; 23223332c596SKonrad Dybcio 23233332c596SKonrad Dybcio thermal-sensors = <&tsens 0>; 23243332c596SKonrad Dybcio 23253332c596SKonrad Dybcio trips { 23263332c596SKonrad Dybcio aoss_alert0: trip-point0 { 23273332c596SKonrad Dybcio temperature = <105000>; 23283332c596SKonrad Dybcio hysteresis = <1000>; 23293332c596SKonrad Dybcio type = "hot"; 23303332c596SKonrad Dybcio }; 23313332c596SKonrad Dybcio }; 23323332c596SKonrad Dybcio }; 23333332c596SKonrad Dybcio 23343332c596SKonrad Dybcio cpuss0-thermal { 23353332c596SKonrad Dybcio polling-delay-passive = <250>; 23363332c596SKonrad Dybcio polling-delay = <1000>; 23373332c596SKonrad Dybcio 23383332c596SKonrad Dybcio thermal-sensors = <&tsens 1>; 23393332c596SKonrad Dybcio 23403332c596SKonrad Dybcio trips { 23413332c596SKonrad Dybcio cpuss0_alert0: trip-point0 { 23423332c596SKonrad Dybcio temperature = <125000>; 23433332c596SKonrad Dybcio hysteresis = <1000>; 23443332c596SKonrad Dybcio type = "hot"; 23453332c596SKonrad Dybcio }; 23463332c596SKonrad Dybcio }; 23473332c596SKonrad Dybcio }; 23483332c596SKonrad Dybcio 23493332c596SKonrad Dybcio cpuss1-thermal { 23503332c596SKonrad Dybcio polling-delay-passive = <250>; 23513332c596SKonrad Dybcio polling-delay = <1000>; 23523332c596SKonrad Dybcio 23533332c596SKonrad Dybcio thermal-sensors = <&tsens 2>; 23543332c596SKonrad Dybcio 23553332c596SKonrad Dybcio trips { 23563332c596SKonrad Dybcio cpuss1_alert0: trip-point0 { 23573332c596SKonrad Dybcio temperature = <125000>; 23583332c596SKonrad Dybcio hysteresis = <1000>; 23593332c596SKonrad Dybcio type = "hot"; 23603332c596SKonrad Dybcio }; 23613332c596SKonrad Dybcio }; 23623332c596SKonrad Dybcio }; 23633332c596SKonrad Dybcio 23643332c596SKonrad Dybcio cpu0-thermal { 23653332c596SKonrad Dybcio polling-delay-passive = <250>; 23663332c596SKonrad Dybcio polling-delay = <1000>; 23673332c596SKonrad Dybcio 23683332c596SKonrad Dybcio thermal-sensors = <&tsens 3>; 23693332c596SKonrad Dybcio 23703332c596SKonrad Dybcio trips { 23713332c596SKonrad Dybcio cpu0_alert0: trip-point0 { 23723332c596SKonrad Dybcio temperature = <70000>; 23733332c596SKonrad Dybcio hysteresis = <1000>; 23743332c596SKonrad Dybcio type = "passive"; 23753332c596SKonrad Dybcio }; 23763332c596SKonrad Dybcio 23773332c596SKonrad Dybcio cpu0_crit: cpu_crit { 23783332c596SKonrad Dybcio temperature = <110000>; 23793332c596SKonrad Dybcio hysteresis = <1000>; 23803332c596SKonrad Dybcio type = "critical"; 23813332c596SKonrad Dybcio }; 23823332c596SKonrad Dybcio }; 23833332c596SKonrad Dybcio }; 23843332c596SKonrad Dybcio 23853332c596SKonrad Dybcio cpu1-thermal { 23863332c596SKonrad Dybcio polling-delay-passive = <250>; 23873332c596SKonrad Dybcio polling-delay = <1000>; 23883332c596SKonrad Dybcio 23893332c596SKonrad Dybcio thermal-sensors = <&tsens 4>; 23903332c596SKonrad Dybcio 23913332c596SKonrad Dybcio trips { 23923332c596SKonrad Dybcio cpu1_alert0: trip-point0 { 23933332c596SKonrad Dybcio temperature = <70000>; 23943332c596SKonrad Dybcio hysteresis = <1000>; 23953332c596SKonrad Dybcio type = "passive"; 23963332c596SKonrad Dybcio }; 23973332c596SKonrad Dybcio 23983332c596SKonrad Dybcio cpu1_crit: cpu_crit { 23993332c596SKonrad Dybcio temperature = <110000>; 24003332c596SKonrad Dybcio hysteresis = <1000>; 24013332c596SKonrad Dybcio type = "critical"; 24023332c596SKonrad Dybcio }; 24033332c596SKonrad Dybcio }; 24043332c596SKonrad Dybcio }; 24053332c596SKonrad Dybcio 24063332c596SKonrad Dybcio cpu2-thermal { 24073332c596SKonrad Dybcio polling-delay-passive = <250>; 24083332c596SKonrad Dybcio polling-delay = <1000>; 24093332c596SKonrad Dybcio 24103332c596SKonrad Dybcio thermal-sensors = <&tsens 5>; 24113332c596SKonrad Dybcio 24123332c596SKonrad Dybcio trips { 24133332c596SKonrad Dybcio cpu2_alert0: trip-point0 { 24143332c596SKonrad Dybcio temperature = <70000>; 24153332c596SKonrad Dybcio hysteresis = <1000>; 24163332c596SKonrad Dybcio type = "passive"; 24173332c596SKonrad Dybcio }; 24183332c596SKonrad Dybcio 24193332c596SKonrad Dybcio cpu2_crit: cpu_crit { 24203332c596SKonrad Dybcio temperature = <110000>; 24213332c596SKonrad Dybcio hysteresis = <1000>; 24223332c596SKonrad Dybcio type = "critical"; 24233332c596SKonrad Dybcio }; 24243332c596SKonrad Dybcio }; 24253332c596SKonrad Dybcio }; 24263332c596SKonrad Dybcio 24273332c596SKonrad Dybcio cpu3-thermal { 24283332c596SKonrad Dybcio polling-delay-passive = <250>; 24293332c596SKonrad Dybcio polling-delay = <1000>; 24303332c596SKonrad Dybcio 24313332c596SKonrad Dybcio thermal-sensors = <&tsens 6>; 24323332c596SKonrad Dybcio 24333332c596SKonrad Dybcio trips { 24343332c596SKonrad Dybcio cpu3_alert0: trip-point0 { 24353332c596SKonrad Dybcio temperature = <70000>; 24363332c596SKonrad Dybcio hysteresis = <1000>; 24373332c596SKonrad Dybcio type = "passive"; 24383332c596SKonrad Dybcio }; 24393332c596SKonrad Dybcio 24403332c596SKonrad Dybcio cpu3_crit: cpu_crit { 24413332c596SKonrad Dybcio temperature = <110000>; 24423332c596SKonrad Dybcio hysteresis = <1000>; 24433332c596SKonrad Dybcio type = "critical"; 24443332c596SKonrad Dybcio }; 24453332c596SKonrad Dybcio }; 24463332c596SKonrad Dybcio }; 24473332c596SKonrad Dybcio 24483332c596SKonrad Dybcio /* 24493332c596SKonrad Dybcio * According to what downstream DTS says, 24503332c596SKonrad Dybcio * the entire power efficient cluster has 24513332c596SKonrad Dybcio * only a single thermal sensor. 24523332c596SKonrad Dybcio */ 24533332c596SKonrad Dybcio 24543332c596SKonrad Dybcio pwr-cluster-thermal { 24553332c596SKonrad Dybcio polling-delay-passive = <250>; 24563332c596SKonrad Dybcio polling-delay = <1000>; 24573332c596SKonrad Dybcio 24583332c596SKonrad Dybcio thermal-sensors = <&tsens 7>; 24593332c596SKonrad Dybcio 24603332c596SKonrad Dybcio trips { 24613332c596SKonrad Dybcio pwr_cluster_alert0: trip-point0 { 24623332c596SKonrad Dybcio temperature = <70000>; 24633332c596SKonrad Dybcio hysteresis = <1000>; 24643332c596SKonrad Dybcio type = "passive"; 24653332c596SKonrad Dybcio }; 24663332c596SKonrad Dybcio 24673332c596SKonrad Dybcio pwr_cluster_crit: cpu_crit { 24683332c596SKonrad Dybcio temperature = <110000>; 24693332c596SKonrad Dybcio hysteresis = <1000>; 24703332c596SKonrad Dybcio type = "critical"; 24713332c596SKonrad Dybcio }; 24723332c596SKonrad Dybcio }; 24733332c596SKonrad Dybcio }; 24743332c596SKonrad Dybcio 24753332c596SKonrad Dybcio gpu-thermal { 24763332c596SKonrad Dybcio polling-delay-passive = <250>; 24773332c596SKonrad Dybcio polling-delay = <1000>; 24783332c596SKonrad Dybcio 24793332c596SKonrad Dybcio thermal-sensors = <&tsens 8>; 24803332c596SKonrad Dybcio 24813332c596SKonrad Dybcio trips { 24823332c596SKonrad Dybcio gpu_alert0: trip-point0 { 24833332c596SKonrad Dybcio temperature = <90000>; 24843332c596SKonrad Dybcio hysteresis = <1000>; 24853332c596SKonrad Dybcio type = "hot"; 24863332c596SKonrad Dybcio }; 24873332c596SKonrad Dybcio }; 24883332c596SKonrad Dybcio }; 24893332c596SKonrad Dybcio }; 24903332c596SKonrad Dybcio 2491b190fb01SKonrad Dybcio timer { 2492b190fb01SKonrad Dybcio compatible = "arm,armv8-timer"; 2493b190fb01SKonrad Dybcio interrupts = <GIC_PPI 1 0xf08>, 2494b190fb01SKonrad Dybcio <GIC_PPI 2 0xf08>, 2495b190fb01SKonrad Dybcio <GIC_PPI 3 0xf08>, 2496b190fb01SKonrad Dybcio <GIC_PPI 0 0xf08>; 2497b190fb01SKonrad Dybcio }; 2498b190fb01SKonrad Dybcio}; 2499b190fb01SKonrad Dybcio 2500