1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2021, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2022, Linaro Limited 5 */ 6 7#include <dt-bindings/clock/qcom,dispcc-sc8280xp.h> 8#include <dt-bindings/clock/qcom,gcc-sc8280xp.h> 9#include <dt-bindings/clock/qcom,gpucc-sc8280xp.h> 10#include <dt-bindings/clock/qcom,rpmh.h> 11#include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h> 12#include <dt-bindings/interconnect/qcom,osm-l3.h> 13#include <dt-bindings/interconnect/qcom,sc8280xp.h> 14#include <dt-bindings/interrupt-controller/arm-gic.h> 15#include <dt-bindings/mailbox/qcom-ipcc.h> 16#include <dt-bindings/phy/phy-qcom-qmp.h> 17#include <dt-bindings/power/qcom-rpmpd.h> 18#include <dt-bindings/soc/qcom,gpr.h> 19#include <dt-bindings/soc/qcom,rpmh-rsc.h> 20#include <dt-bindings/sound/qcom,q6afe.h> 21#include <dt-bindings/thermal/thermal.h> 22 23/ { 24 interrupt-parent = <&intc>; 25 26 #address-cells = <2>; 27 #size-cells = <2>; 28 29 clocks { 30 xo_board_clk: xo-board-clk { 31 compatible = "fixed-clock"; 32 #clock-cells = <0>; 33 }; 34 35 sleep_clk: sleep-clk { 36 compatible = "fixed-clock"; 37 #clock-cells = <0>; 38 clock-frequency = <32764>; 39 }; 40 }; 41 42 cpus { 43 #address-cells = <2>; 44 #size-cells = <0>; 45 46 CPU0: cpu@0 { 47 device_type = "cpu"; 48 compatible = "arm,cortex-a78c"; 49 reg = <0x0 0x0>; 50 clocks = <&cpufreq_hw 0>; 51 enable-method = "psci"; 52 capacity-dmips-mhz = <602>; 53 next-level-cache = <&L2_0>; 54 power-domains = <&CPU_PD0>; 55 power-domain-names = "psci"; 56 qcom,freq-domain = <&cpufreq_hw 0>; 57 operating-points-v2 = <&cpu0_opp_table>; 58 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 59 #cooling-cells = <2>; 60 L2_0: l2-cache { 61 compatible = "cache"; 62 cache-level = <2>; 63 cache-unified; 64 next-level-cache = <&L3_0>; 65 L3_0: l3-cache { 66 compatible = "cache"; 67 cache-level = <3>; 68 cache-unified; 69 }; 70 }; 71 }; 72 73 CPU1: cpu@100 { 74 device_type = "cpu"; 75 compatible = "arm,cortex-a78c"; 76 reg = <0x0 0x100>; 77 clocks = <&cpufreq_hw 0>; 78 enable-method = "psci"; 79 capacity-dmips-mhz = <602>; 80 next-level-cache = <&L2_100>; 81 power-domains = <&CPU_PD1>; 82 power-domain-names = "psci"; 83 qcom,freq-domain = <&cpufreq_hw 0>; 84 operating-points-v2 = <&cpu0_opp_table>; 85 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 86 #cooling-cells = <2>; 87 L2_100: l2-cache { 88 compatible = "cache"; 89 cache-level = <2>; 90 cache-unified; 91 next-level-cache = <&L3_0>; 92 }; 93 }; 94 95 CPU2: cpu@200 { 96 device_type = "cpu"; 97 compatible = "arm,cortex-a78c"; 98 reg = <0x0 0x200>; 99 clocks = <&cpufreq_hw 0>; 100 enable-method = "psci"; 101 capacity-dmips-mhz = <602>; 102 next-level-cache = <&L2_200>; 103 power-domains = <&CPU_PD2>; 104 power-domain-names = "psci"; 105 qcom,freq-domain = <&cpufreq_hw 0>; 106 operating-points-v2 = <&cpu0_opp_table>; 107 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 108 #cooling-cells = <2>; 109 L2_200: l2-cache { 110 compatible = "cache"; 111 cache-level = <2>; 112 cache-unified; 113 next-level-cache = <&L3_0>; 114 }; 115 }; 116 117 CPU3: cpu@300 { 118 device_type = "cpu"; 119 compatible = "arm,cortex-a78c"; 120 reg = <0x0 0x300>; 121 clocks = <&cpufreq_hw 0>; 122 enable-method = "psci"; 123 capacity-dmips-mhz = <602>; 124 next-level-cache = <&L2_300>; 125 power-domains = <&CPU_PD3>; 126 power-domain-names = "psci"; 127 qcom,freq-domain = <&cpufreq_hw 0>; 128 operating-points-v2 = <&cpu0_opp_table>; 129 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 130 #cooling-cells = <2>; 131 L2_300: l2-cache { 132 compatible = "cache"; 133 cache-level = <2>; 134 cache-unified; 135 next-level-cache = <&L3_0>; 136 }; 137 }; 138 139 CPU4: cpu@400 { 140 device_type = "cpu"; 141 compatible = "arm,cortex-x1c"; 142 reg = <0x0 0x400>; 143 clocks = <&cpufreq_hw 1>; 144 enable-method = "psci"; 145 capacity-dmips-mhz = <1024>; 146 next-level-cache = <&L2_400>; 147 power-domains = <&CPU_PD4>; 148 power-domain-names = "psci"; 149 qcom,freq-domain = <&cpufreq_hw 1>; 150 operating-points-v2 = <&cpu4_opp_table>; 151 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 152 #cooling-cells = <2>; 153 L2_400: l2-cache { 154 compatible = "cache"; 155 cache-level = <2>; 156 cache-unified; 157 next-level-cache = <&L3_0>; 158 }; 159 }; 160 161 CPU5: cpu@500 { 162 device_type = "cpu"; 163 compatible = "arm,cortex-x1c"; 164 reg = <0x0 0x500>; 165 clocks = <&cpufreq_hw 1>; 166 enable-method = "psci"; 167 capacity-dmips-mhz = <1024>; 168 next-level-cache = <&L2_500>; 169 power-domains = <&CPU_PD5>; 170 power-domain-names = "psci"; 171 qcom,freq-domain = <&cpufreq_hw 1>; 172 operating-points-v2 = <&cpu4_opp_table>; 173 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 174 #cooling-cells = <2>; 175 L2_500: l2-cache { 176 compatible = "cache"; 177 cache-level = <2>; 178 cache-unified; 179 next-level-cache = <&L3_0>; 180 }; 181 }; 182 183 CPU6: cpu@600 { 184 device_type = "cpu"; 185 compatible = "arm,cortex-x1c"; 186 reg = <0x0 0x600>; 187 clocks = <&cpufreq_hw 1>; 188 enable-method = "psci"; 189 capacity-dmips-mhz = <1024>; 190 next-level-cache = <&L2_600>; 191 power-domains = <&CPU_PD6>; 192 power-domain-names = "psci"; 193 qcom,freq-domain = <&cpufreq_hw 1>; 194 operating-points-v2 = <&cpu4_opp_table>; 195 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 196 #cooling-cells = <2>; 197 L2_600: l2-cache { 198 compatible = "cache"; 199 cache-level = <2>; 200 cache-unified; 201 next-level-cache = <&L3_0>; 202 }; 203 }; 204 205 CPU7: cpu@700 { 206 device_type = "cpu"; 207 compatible = "arm,cortex-x1c"; 208 reg = <0x0 0x700>; 209 clocks = <&cpufreq_hw 1>; 210 enable-method = "psci"; 211 capacity-dmips-mhz = <1024>; 212 next-level-cache = <&L2_700>; 213 power-domains = <&CPU_PD7>; 214 power-domain-names = "psci"; 215 qcom,freq-domain = <&cpufreq_hw 1>; 216 operating-points-v2 = <&cpu4_opp_table>; 217 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 218 #cooling-cells = <2>; 219 L2_700: l2-cache { 220 compatible = "cache"; 221 cache-level = <2>; 222 cache-unified; 223 next-level-cache = <&L3_0>; 224 }; 225 }; 226 227 cpu-map { 228 cluster0 { 229 core0 { 230 cpu = <&CPU0>; 231 }; 232 233 core1 { 234 cpu = <&CPU1>; 235 }; 236 237 core2 { 238 cpu = <&CPU2>; 239 }; 240 241 core3 { 242 cpu = <&CPU3>; 243 }; 244 245 core4 { 246 cpu = <&CPU4>; 247 }; 248 249 core5 { 250 cpu = <&CPU5>; 251 }; 252 253 core6 { 254 cpu = <&CPU6>; 255 }; 256 257 core7 { 258 cpu = <&CPU7>; 259 }; 260 }; 261 }; 262 263 idle-states { 264 entry-method = "psci"; 265 266 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 267 compatible = "arm,idle-state"; 268 idle-state-name = "little-rail-power-collapse"; 269 arm,psci-suspend-param = <0x40000004>; 270 entry-latency-us = <355>; 271 exit-latency-us = <909>; 272 min-residency-us = <3934>; 273 local-timer-stop; 274 }; 275 276 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 277 compatible = "arm,idle-state"; 278 idle-state-name = "big-rail-power-collapse"; 279 arm,psci-suspend-param = <0x40000004>; 280 entry-latency-us = <241>; 281 exit-latency-us = <1461>; 282 min-residency-us = <4488>; 283 local-timer-stop; 284 }; 285 }; 286 287 domain-idle-states { 288 CLUSTER_SLEEP_0: cluster-sleep-0 { 289 compatible = "domain-idle-state"; 290 arm,psci-suspend-param = <0x4100c344>; 291 entry-latency-us = <3263>; 292 exit-latency-us = <6562>; 293 min-residency-us = <9987>; 294 }; 295 }; 296 }; 297 298 firmware { 299 scm: scm { 300 compatible = "qcom,scm-sc8280xp", "qcom,scm"; 301 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; 302 }; 303 }; 304 305 aggre1_noc: interconnect-aggre1-noc { 306 compatible = "qcom,sc8280xp-aggre1-noc"; 307 #interconnect-cells = <2>; 308 qcom,bcm-voters = <&apps_bcm_voter>; 309 }; 310 311 aggre2_noc: interconnect-aggre2-noc { 312 compatible = "qcom,sc8280xp-aggre2-noc"; 313 #interconnect-cells = <2>; 314 qcom,bcm-voters = <&apps_bcm_voter>; 315 }; 316 317 clk_virt: interconnect-clk-virt { 318 compatible = "qcom,sc8280xp-clk-virt"; 319 #interconnect-cells = <2>; 320 qcom,bcm-voters = <&apps_bcm_voter>; 321 }; 322 323 config_noc: interconnect-config-noc { 324 compatible = "qcom,sc8280xp-config-noc"; 325 #interconnect-cells = <2>; 326 qcom,bcm-voters = <&apps_bcm_voter>; 327 }; 328 329 dc_noc: interconnect-dc-noc { 330 compatible = "qcom,sc8280xp-dc-noc"; 331 #interconnect-cells = <2>; 332 qcom,bcm-voters = <&apps_bcm_voter>; 333 }; 334 335 gem_noc: interconnect-gem-noc { 336 compatible = "qcom,sc8280xp-gem-noc"; 337 #interconnect-cells = <2>; 338 qcom,bcm-voters = <&apps_bcm_voter>; 339 }; 340 341 lpass_noc: interconnect-lpass-ag-noc { 342 compatible = "qcom,sc8280xp-lpass-ag-noc"; 343 #interconnect-cells = <2>; 344 qcom,bcm-voters = <&apps_bcm_voter>; 345 }; 346 347 mc_virt: interconnect-mc-virt { 348 compatible = "qcom,sc8280xp-mc-virt"; 349 #interconnect-cells = <2>; 350 qcom,bcm-voters = <&apps_bcm_voter>; 351 }; 352 353 mmss_noc: interconnect-mmss-noc { 354 compatible = "qcom,sc8280xp-mmss-noc"; 355 #interconnect-cells = <2>; 356 qcom,bcm-voters = <&apps_bcm_voter>; 357 }; 358 359 nspa_noc: interconnect-nspa-noc { 360 compatible = "qcom,sc8280xp-nspa-noc"; 361 #interconnect-cells = <2>; 362 qcom,bcm-voters = <&apps_bcm_voter>; 363 }; 364 365 nspb_noc: interconnect-nspb-noc { 366 compatible = "qcom,sc8280xp-nspb-noc"; 367 #interconnect-cells = <2>; 368 qcom,bcm-voters = <&apps_bcm_voter>; 369 }; 370 371 system_noc: interconnect-system-noc { 372 compatible = "qcom,sc8280xp-system-noc"; 373 #interconnect-cells = <2>; 374 qcom,bcm-voters = <&apps_bcm_voter>; 375 }; 376 377 memory@80000000 { 378 device_type = "memory"; 379 /* We expect the bootloader to fill in the size */ 380 reg = <0x0 0x80000000 0x0 0x0>; 381 }; 382 383 cpu0_opp_table: opp-table-cpu0 { 384 compatible = "operating-points-v2"; 385 opp-shared; 386 387 opp-300000000 { 388 opp-hz = /bits/ 64 <300000000>; 389 opp-peak-kBps = <(300000 * 32)>; 390 }; 391 opp-403200000 { 392 opp-hz = /bits/ 64 <403200000>; 393 opp-peak-kBps = <(384000 * 32)>; 394 }; 395 opp-499200000 { 396 opp-hz = /bits/ 64 <499200000>; 397 opp-peak-kBps = <(480000 * 32)>; 398 }; 399 opp-595200000 { 400 opp-hz = /bits/ 64 <595200000>; 401 opp-peak-kBps = <(576000 * 32)>; 402 }; 403 opp-691200000 { 404 opp-hz = /bits/ 64 <691200000>; 405 opp-peak-kBps = <(672000 * 32)>; 406 }; 407 opp-806400000 { 408 opp-hz = /bits/ 64 <806400000>; 409 opp-peak-kBps = <(768000 * 32)>; 410 }; 411 opp-902400000 { 412 opp-hz = /bits/ 64 <902400000>; 413 opp-peak-kBps = <(864000 * 32)>; 414 }; 415 opp-1017600000 { 416 opp-hz = /bits/ 64 <1017600000>; 417 opp-peak-kBps = <(960000 * 32)>; 418 }; 419 opp-1113600000 { 420 opp-hz = /bits/ 64 <1113600000>; 421 opp-peak-kBps = <(1075200 * 32)>; 422 }; 423 opp-1209600000 { 424 opp-hz = /bits/ 64 <1209600000>; 425 opp-peak-kBps = <(1171200 * 32)>; 426 }; 427 opp-1324800000 { 428 opp-hz = /bits/ 64 <1324800000>; 429 opp-peak-kBps = <(1267200 * 32)>; 430 }; 431 opp-1440000000 { 432 opp-hz = /bits/ 64 <1440000000>; 433 opp-peak-kBps = <(1363200 * 32)>; 434 }; 435 opp-1555200000 { 436 opp-hz = /bits/ 64 <1555200000>; 437 opp-peak-kBps = <(1536000 * 32)>; 438 }; 439 opp-1670400000 { 440 opp-hz = /bits/ 64 <1670400000>; 441 opp-peak-kBps = <(1612800 * 32)>; 442 }; 443 opp-1785600000 { 444 opp-hz = /bits/ 64 <1785600000>; 445 opp-peak-kBps = <(1689600 * 32)>; 446 }; 447 opp-1881600000 { 448 opp-hz = /bits/ 64 <1881600000>; 449 opp-peak-kBps = <(1689600 * 32)>; 450 }; 451 opp-1996800000 { 452 opp-hz = /bits/ 64 <1996800000>; 453 opp-peak-kBps = <(1689600 * 32)>; 454 }; 455 opp-2112000000 { 456 opp-hz = /bits/ 64 <2112000000>; 457 opp-peak-kBps = <(1689600 * 32)>; 458 }; 459 opp-2227200000 { 460 opp-hz = /bits/ 64 <2227200000>; 461 opp-peak-kBps = <(1689600 * 32)>; 462 }; 463 opp-2342400000 { 464 opp-hz = /bits/ 64 <2342400000>; 465 opp-peak-kBps = <(1689600 * 32)>; 466 }; 467 opp-2438400000 { 468 opp-hz = /bits/ 64 <2438400000>; 469 opp-peak-kBps = <(1689600 * 32)>; 470 }; 471 }; 472 473 cpu4_opp_table: opp-table-cpu4 { 474 compatible = "operating-points-v2"; 475 opp-shared; 476 477 opp-825600000 { 478 opp-hz = /bits/ 64 <825600000>; 479 opp-peak-kBps = <(768000 * 32)>; 480 }; 481 opp-940800000 { 482 opp-hz = /bits/ 64 <940800000>; 483 opp-peak-kBps = <(864000 * 32)>; 484 }; 485 opp-1056000000 { 486 opp-hz = /bits/ 64 <1056000000>; 487 opp-peak-kBps = <(960000 * 32)>; 488 }; 489 opp-1171200000 { 490 opp-hz = /bits/ 64 <1171200000>; 491 opp-peak-kBps = <(1171200 * 32)>; 492 }; 493 opp-1286400000 { 494 opp-hz = /bits/ 64 <1286400000>; 495 opp-peak-kBps = <(1267200 * 32)>; 496 }; 497 opp-1401600000 { 498 opp-hz = /bits/ 64 <1401600000>; 499 opp-peak-kBps = <(1363200 * 32)>; 500 }; 501 opp-1516800000 { 502 opp-hz = /bits/ 64 <1516800000>; 503 opp-peak-kBps = <(1459200 * 32)>; 504 }; 505 opp-1632000000 { 506 opp-hz = /bits/ 64 <1632000000>; 507 opp-peak-kBps = <(1612800 * 32)>; 508 }; 509 opp-1747200000 { 510 opp-hz = /bits/ 64 <1747200000>; 511 opp-peak-kBps = <(1689600 * 32)>; 512 }; 513 opp-1862400000 { 514 opp-hz = /bits/ 64 <1862400000>; 515 opp-peak-kBps = <(1689600 * 32)>; 516 }; 517 opp-1977600000 { 518 opp-hz = /bits/ 64 <1977600000>; 519 opp-peak-kBps = <(1689600 * 32)>; 520 }; 521 opp-2073600000 { 522 opp-hz = /bits/ 64 <2073600000>; 523 opp-peak-kBps = <(1689600 * 32)>; 524 }; 525 opp-2169600000 { 526 opp-hz = /bits/ 64 <2169600000>; 527 opp-peak-kBps = <(1689600 * 32)>; 528 }; 529 opp-2284800000 { 530 opp-hz = /bits/ 64 <2284800000>; 531 opp-peak-kBps = <(1689600 * 32)>; 532 }; 533 opp-2400000000 { 534 opp-hz = /bits/ 64 <2400000000>; 535 opp-peak-kBps = <(1689600 * 32)>; 536 }; 537 opp-2496000000 { 538 opp-hz = /bits/ 64 <2496000000>; 539 opp-peak-kBps = <(1689600 * 32)>; 540 }; 541 opp-2592000000 { 542 opp-hz = /bits/ 64 <2592000000>; 543 opp-peak-kBps = <(1689600 * 32)>; 544 }; 545 opp-2688000000 { 546 opp-hz = /bits/ 64 <2688000000>; 547 opp-peak-kBps = <(1689600 * 32)>; 548 }; 549 opp-2803200000 { 550 opp-hz = /bits/ 64 <2803200000>; 551 opp-peak-kBps = <(1689600 * 32)>; 552 }; 553 opp-2899200000 { 554 opp-hz = /bits/ 64 <2899200000>; 555 opp-peak-kBps = <(1689600 * 32)>; 556 }; 557 opp-2995200000 { 558 opp-hz = /bits/ 64 <2995200000>; 559 opp-peak-kBps = <(1689600 * 32)>; 560 }; 561 }; 562 563 qup_opp_table_100mhz: opp-table-qup100mhz { 564 compatible = "operating-points-v2"; 565 566 opp-75000000 { 567 opp-hz = /bits/ 64 <75000000>; 568 required-opps = <&rpmhpd_opp_low_svs>; 569 }; 570 571 opp-100000000 { 572 opp-hz = /bits/ 64 <100000000>; 573 required-opps = <&rpmhpd_opp_svs>; 574 }; 575 }; 576 577 pmu { 578 compatible = "arm,armv8-pmuv3"; 579 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 580 }; 581 582 psci { 583 compatible = "arm,psci-1.0"; 584 method = "smc"; 585 586 CPU_PD0: power-domain-cpu0 { 587 #power-domain-cells = <0>; 588 power-domains = <&CLUSTER_PD>; 589 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 590 }; 591 592 CPU_PD1: power-domain-cpu1 { 593 #power-domain-cells = <0>; 594 power-domains = <&CLUSTER_PD>; 595 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 596 }; 597 598 CPU_PD2: power-domain-cpu2 { 599 #power-domain-cells = <0>; 600 power-domains = <&CLUSTER_PD>; 601 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 602 }; 603 604 CPU_PD3: power-domain-cpu3 { 605 #power-domain-cells = <0>; 606 power-domains = <&CLUSTER_PD>; 607 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 608 }; 609 610 CPU_PD4: power-domain-cpu4 { 611 #power-domain-cells = <0>; 612 power-domains = <&CLUSTER_PD>; 613 domain-idle-states = <&BIG_CPU_SLEEP_0>; 614 }; 615 616 CPU_PD5: power-domain-cpu5 { 617 #power-domain-cells = <0>; 618 power-domains = <&CLUSTER_PD>; 619 domain-idle-states = <&BIG_CPU_SLEEP_0>; 620 }; 621 622 CPU_PD6: power-domain-cpu6 { 623 #power-domain-cells = <0>; 624 power-domains = <&CLUSTER_PD>; 625 domain-idle-states = <&BIG_CPU_SLEEP_0>; 626 }; 627 628 CPU_PD7: power-domain-cpu7 { 629 #power-domain-cells = <0>; 630 power-domains = <&CLUSTER_PD>; 631 domain-idle-states = <&BIG_CPU_SLEEP_0>; 632 }; 633 634 CLUSTER_PD: power-domain-cpu-cluster0 { 635 #power-domain-cells = <0>; 636 domain-idle-states = <&CLUSTER_SLEEP_0>; 637 }; 638 }; 639 640 reserved-memory { 641 #address-cells = <2>; 642 #size-cells = <2>; 643 ranges; 644 645 reserved-region@80000000 { 646 reg = <0 0x80000000 0 0x860000>; 647 no-map; 648 }; 649 650 cmd_db: cmd-db-region@80860000 { 651 compatible = "qcom,cmd-db"; 652 reg = <0 0x80860000 0 0x20000>; 653 no-map; 654 }; 655 656 reserved-region@80880000 { 657 reg = <0 0x80880000 0 0x80000>; 658 no-map; 659 }; 660 661 smem_mem: smem-region@80900000 { 662 compatible = "qcom,smem"; 663 reg = <0 0x80900000 0 0x200000>; 664 no-map; 665 hwlocks = <&tcsr_mutex 3>; 666 }; 667 668 reserved-region@80b00000 { 669 reg = <0 0x80b00000 0 0x100000>; 670 no-map; 671 }; 672 673 reserved-region@83b00000 { 674 reg = <0 0x83b00000 0 0x1700000>; 675 no-map; 676 }; 677 678 reserved-region@85b00000 { 679 reg = <0 0x85b00000 0 0xc00000>; 680 no-map; 681 }; 682 683 pil_adsp_mem: adsp-region@86c00000 { 684 reg = <0 0x86c00000 0 0x2000000>; 685 no-map; 686 }; 687 688 pil_nsp0_mem: cdsp0-region@8a100000 { 689 reg = <0 0x8a100000 0 0x1e00000>; 690 no-map; 691 }; 692 693 pil_nsp1_mem: cdsp1-region@8c600000 { 694 reg = <0 0x8c600000 0 0x1e00000>; 695 no-map; 696 }; 697 698 reserved-region@aeb00000 { 699 reg = <0 0xaeb00000 0 0x16600000>; 700 no-map; 701 }; 702 }; 703 704 smp2p-adsp { 705 compatible = "qcom,smp2p"; 706 qcom,smem = <443>, <429>; 707 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 708 IPCC_MPROC_SIGNAL_SMP2P 709 IRQ_TYPE_EDGE_RISING>; 710 mboxes = <&ipcc IPCC_CLIENT_LPASS 711 IPCC_MPROC_SIGNAL_SMP2P>; 712 713 qcom,local-pid = <0>; 714 qcom,remote-pid = <2>; 715 716 smp2p_adsp_out: master-kernel { 717 qcom,entry-name = "master-kernel"; 718 #qcom,smem-state-cells = <1>; 719 }; 720 721 smp2p_adsp_in: slave-kernel { 722 qcom,entry-name = "slave-kernel"; 723 interrupt-controller; 724 #interrupt-cells = <2>; 725 }; 726 }; 727 728 smp2p-nsp0 { 729 compatible = "qcom,smp2p"; 730 qcom,smem = <94>, <432>; 731 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 732 IPCC_MPROC_SIGNAL_SMP2P 733 IRQ_TYPE_EDGE_RISING>; 734 mboxes = <&ipcc IPCC_CLIENT_CDSP 735 IPCC_MPROC_SIGNAL_SMP2P>; 736 737 qcom,local-pid = <0>; 738 qcom,remote-pid = <5>; 739 740 smp2p_nsp0_out: master-kernel { 741 qcom,entry-name = "master-kernel"; 742 #qcom,smem-state-cells = <1>; 743 }; 744 745 smp2p_nsp0_in: slave-kernel { 746 qcom,entry-name = "slave-kernel"; 747 interrupt-controller; 748 #interrupt-cells = <2>; 749 }; 750 }; 751 752 smp2p-nsp1 { 753 compatible = "qcom,smp2p"; 754 qcom,smem = <617>, <616>; 755 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1 756 IPCC_MPROC_SIGNAL_SMP2P 757 IRQ_TYPE_EDGE_RISING>; 758 mboxes = <&ipcc IPCC_CLIENT_NSP1 759 IPCC_MPROC_SIGNAL_SMP2P>; 760 761 qcom,local-pid = <0>; 762 qcom,remote-pid = <12>; 763 764 smp2p_nsp1_out: master-kernel { 765 qcom,entry-name = "master-kernel"; 766 #qcom,smem-state-cells = <1>; 767 }; 768 769 smp2p_nsp1_in: slave-kernel { 770 qcom,entry-name = "slave-kernel"; 771 interrupt-controller; 772 #interrupt-cells = <2>; 773 }; 774 }; 775 776 soc: soc@0 { 777 compatible = "simple-bus"; 778 #address-cells = <2>; 779 #size-cells = <2>; 780 ranges = <0 0 0 0 0x10 0>; 781 dma-ranges = <0 0 0 0 0x10 0>; 782 783 ethernet0: ethernet@20000 { 784 compatible = "qcom,sc8280xp-ethqos"; 785 reg = <0x0 0x00020000 0x0 0x10000>, 786 <0x0 0x00036000 0x0 0x100>; 787 reg-names = "stmmaceth", "rgmii"; 788 789 clocks = <&gcc GCC_EMAC0_AXI_CLK>, 790 <&gcc GCC_EMAC0_SLV_AHB_CLK>, 791 <&gcc GCC_EMAC0_PTP_CLK>, 792 <&gcc GCC_EMAC0_RGMII_CLK>; 793 clock-names = "stmmaceth", 794 "pclk", 795 "ptp_ref", 796 "rgmii"; 797 798 interrupts = <GIC_SPI 946 IRQ_TYPE_LEVEL_HIGH>, 799 <GIC_SPI 936 IRQ_TYPE_LEVEL_HIGH>; 800 interrupt-names = "macirq", "eth_lpi"; 801 802 iommus = <&apps_smmu 0x4c0 0xf>; 803 power-domains = <&gcc EMAC_0_GDSC>; 804 805 snps,tso; 806 snps,pbl = <32>; 807 rx-fifo-depth = <4096>; 808 tx-fifo-depth = <4096>; 809 810 status = "disabled"; 811 }; 812 813 gcc: clock-controller@100000 { 814 compatible = "qcom,gcc-sc8280xp"; 815 reg = <0x0 0x00100000 0x0 0x1f0000>; 816 #clock-cells = <1>; 817 #reset-cells = <1>; 818 #power-domain-cells = <1>; 819 clocks = <&rpmhcc RPMH_CXO_CLK>, 820 <&sleep_clk>, 821 <0>, 822 <0>, 823 <0>, 824 <0>, 825 <0>, 826 <0>, 827 <&usb_0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 828 <0>, 829 <0>, 830 <0>, 831 <0>, 832 <0>, 833 <0>, 834 <0>, 835 <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 836 <0>, 837 <0>, 838 <0>, 839 <0>, 840 <0>, 841 <0>, 842 <0>, 843 <0>, 844 <0>, 845 <&pcie2a_phy>, 846 <&pcie2b_phy>, 847 <&pcie3a_phy>, 848 <&pcie3b_phy>, 849 <&pcie4_phy>, 850 <0>, 851 <0>; 852 power-domains = <&rpmhpd SC8280XP_CX>; 853 }; 854 855 ipcc: mailbox@408000 { 856 compatible = "qcom,sc8280xp-ipcc", "qcom,ipcc"; 857 reg = <0 0x00408000 0 0x1000>; 858 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 859 interrupt-controller; 860 #interrupt-cells = <3>; 861 #mbox-cells = <2>; 862 }; 863 864 qup2: geniqup@8c0000 { 865 compatible = "qcom,geni-se-qup"; 866 reg = <0 0x008c0000 0 0x2000>; 867 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 868 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 869 clock-names = "m-ahb", "s-ahb"; 870 iommus = <&apps_smmu 0xa3 0>; 871 872 #address-cells = <2>; 873 #size-cells = <2>; 874 ranges; 875 876 status = "disabled"; 877 878 i2c16: i2c@880000 { 879 compatible = "qcom,geni-i2c"; 880 reg = <0 0x00880000 0 0x4000>; 881 #address-cells = <1>; 882 #size-cells = <0>; 883 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 884 clock-names = "se"; 885 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 886 power-domains = <&rpmhpd SC8280XP_CX>; 887 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 888 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 889 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 890 interconnect-names = "qup-core", "qup-config", "qup-memory"; 891 status = "disabled"; 892 }; 893 894 spi16: spi@880000 { 895 compatible = "qcom,geni-spi"; 896 reg = <0 0x00880000 0 0x4000>; 897 #address-cells = <1>; 898 #size-cells = <0>; 899 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 900 clock-names = "se"; 901 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 902 power-domains = <&rpmhpd SC8280XP_CX>; 903 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 904 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 905 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 906 interconnect-names = "qup-core", "qup-config", "qup-memory"; 907 status = "disabled"; 908 }; 909 910 i2c17: i2c@884000 { 911 compatible = "qcom,geni-i2c"; 912 reg = <0 0x00884000 0 0x4000>; 913 #address-cells = <1>; 914 #size-cells = <0>; 915 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 916 clock-names = "se"; 917 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 918 power-domains = <&rpmhpd SC8280XP_CX>; 919 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 920 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 921 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 922 interconnect-names = "qup-core", "qup-config", "qup-memory"; 923 status = "disabled"; 924 }; 925 926 spi17: spi@884000 { 927 compatible = "qcom,geni-spi"; 928 reg = <0 0x00884000 0 0x4000>; 929 #address-cells = <1>; 930 #size-cells = <0>; 931 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 932 clock-names = "se"; 933 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 934 power-domains = <&rpmhpd SC8280XP_CX>; 935 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 936 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 937 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 938 interconnect-names = "qup-core", "qup-config", "qup-memory"; 939 status = "disabled"; 940 }; 941 942 uart17: serial@884000 { 943 compatible = "qcom,geni-uart"; 944 reg = <0 0x00884000 0 0x4000>; 945 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 946 clock-names = "se"; 947 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 948 operating-points-v2 = <&qup_opp_table_100mhz>; 949 power-domains = <&rpmhpd SC8280XP_CX>; 950 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 951 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>; 952 interconnect-names = "qup-core", "qup-config"; 953 status = "disabled"; 954 }; 955 956 i2c18: i2c@888000 { 957 compatible = "qcom,geni-i2c"; 958 reg = <0 0x00888000 0 0x4000>; 959 #address-cells = <1>; 960 #size-cells = <0>; 961 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 962 clock-names = "se"; 963 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 964 power-domains = <&rpmhpd SC8280XP_CX>; 965 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 966 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 967 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 968 interconnect-names = "qup-core", "qup-config", "qup-memory"; 969 status = "disabled"; 970 }; 971 972 spi18: spi@888000 { 973 compatible = "qcom,geni-spi"; 974 reg = <0 0x00888000 0 0x4000>; 975 #address-cells = <1>; 976 #size-cells = <0>; 977 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 978 clock-names = "se"; 979 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 980 power-domains = <&rpmhpd SC8280XP_CX>; 981 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 982 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 983 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 984 interconnect-names = "qup-core", "qup-config", "qup-memory"; 985 status = "disabled"; 986 }; 987 988 i2c19: i2c@88c000 { 989 compatible = "qcom,geni-i2c"; 990 reg = <0 0x0088c000 0 0x4000>; 991 #address-cells = <1>; 992 #size-cells = <0>; 993 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 994 clock-names = "se"; 995 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 996 power-domains = <&rpmhpd SC8280XP_CX>; 997 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 998 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 999 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1000 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1001 status = "disabled"; 1002 }; 1003 1004 spi19: spi@88c000 { 1005 compatible = "qcom,geni-spi"; 1006 reg = <0 0x0088c000 0 0x4000>; 1007 #address-cells = <1>; 1008 #size-cells = <0>; 1009 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1010 clock-names = "se"; 1011 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1012 power-domains = <&rpmhpd SC8280XP_CX>; 1013 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1014 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1015 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1016 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1017 status = "disabled"; 1018 }; 1019 1020 i2c20: i2c@890000 { 1021 compatible = "qcom,geni-i2c"; 1022 reg = <0 0x00890000 0 0x4000>; 1023 #address-cells = <1>; 1024 #size-cells = <0>; 1025 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1026 clock-names = "se"; 1027 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1028 power-domains = <&rpmhpd SC8280XP_CX>; 1029 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1030 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1031 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1032 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1033 status = "disabled"; 1034 }; 1035 1036 spi20: spi@890000 { 1037 compatible = "qcom,geni-spi"; 1038 reg = <0 0x00890000 0 0x4000>; 1039 #address-cells = <1>; 1040 #size-cells = <0>; 1041 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1042 clock-names = "se"; 1043 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1044 power-domains = <&rpmhpd SC8280XP_CX>; 1045 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1046 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1047 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1048 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1049 status = "disabled"; 1050 }; 1051 1052 i2c21: i2c@894000 { 1053 compatible = "qcom,geni-i2c"; 1054 reg = <0 0x00894000 0 0x4000>; 1055 clock-names = "se"; 1056 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1057 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1058 #address-cells = <1>; 1059 #size-cells = <0>; 1060 power-domains = <&rpmhpd SC8280XP_CX>; 1061 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1062 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1063 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1064 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1065 status = "disabled"; 1066 }; 1067 1068 spi21: spi@894000 { 1069 compatible = "qcom,geni-spi"; 1070 reg = <0 0x00894000 0 0x4000>; 1071 #address-cells = <1>; 1072 #size-cells = <0>; 1073 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1074 clock-names = "se"; 1075 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1076 power-domains = <&rpmhpd SC8280XP_CX>; 1077 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1078 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1079 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1080 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1081 status = "disabled"; 1082 }; 1083 1084 i2c22: i2c@898000 { 1085 compatible = "qcom,geni-i2c"; 1086 reg = <0 0x00898000 0 0x4000>; 1087 #address-cells = <1>; 1088 #size-cells = <0>; 1089 clock-names = "se"; 1090 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1091 interrupts = <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>; 1092 power-domains = <&rpmhpd SC8280XP_CX>; 1093 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1094 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1095 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1096 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1097 status = "disabled"; 1098 }; 1099 1100 spi22: spi@898000 { 1101 compatible = "qcom,geni-spi"; 1102 reg = <0 0x00898000 0 0x4000>; 1103 #address-cells = <1>; 1104 #size-cells = <0>; 1105 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1106 clock-names = "se"; 1107 interrupts = <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>; 1108 power-domains = <&rpmhpd SC8280XP_CX>; 1109 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1110 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1111 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1112 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1113 status = "disabled"; 1114 }; 1115 1116 i2c23: i2c@89c000 { 1117 compatible = "qcom,geni-i2c"; 1118 reg = <0 0x0089c000 0 0x4000>; 1119 #address-cells = <1>; 1120 #size-cells = <0>; 1121 clock-names = "se"; 1122 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1123 interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>; 1124 power-domains = <&rpmhpd SC8280XP_CX>; 1125 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1126 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1127 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1128 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1129 status = "disabled"; 1130 }; 1131 1132 spi23: spi@89c000 { 1133 compatible = "qcom,geni-spi"; 1134 reg = <0 0x0089c000 0 0x4000>; 1135 #address-cells = <1>; 1136 #size-cells = <0>; 1137 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1138 clock-names = "se"; 1139 interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>; 1140 power-domains = <&rpmhpd SC8280XP_CX>; 1141 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1142 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1143 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1144 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1145 status = "disabled"; 1146 }; 1147 }; 1148 1149 qup0: geniqup@9c0000 { 1150 compatible = "qcom,geni-se-qup"; 1151 reg = <0 0x009c0000 0 0x6000>; 1152 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1153 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1154 clock-names = "m-ahb", "s-ahb"; 1155 iommus = <&apps_smmu 0x563 0>; 1156 1157 #address-cells = <2>; 1158 #size-cells = <2>; 1159 ranges; 1160 1161 status = "disabled"; 1162 1163 i2c0: i2c@980000 { 1164 compatible = "qcom,geni-i2c"; 1165 reg = <0 0x00980000 0 0x4000>; 1166 #address-cells = <1>; 1167 #size-cells = <0>; 1168 clock-names = "se"; 1169 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1170 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1171 power-domains = <&rpmhpd SC8280XP_CX>; 1172 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1173 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1174 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1175 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1176 status = "disabled"; 1177 }; 1178 1179 spi0: spi@980000 { 1180 compatible = "qcom,geni-spi"; 1181 reg = <0 0x00980000 0 0x4000>; 1182 #address-cells = <1>; 1183 #size-cells = <0>; 1184 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1185 clock-names = "se"; 1186 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1187 power-domains = <&rpmhpd SC8280XP_CX>; 1188 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1189 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1190 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1191 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1192 status = "disabled"; 1193 }; 1194 1195 i2c1: i2c@984000 { 1196 compatible = "qcom,geni-i2c"; 1197 reg = <0 0x00984000 0 0x4000>; 1198 #address-cells = <1>; 1199 #size-cells = <0>; 1200 clock-names = "se"; 1201 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1202 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1203 power-domains = <&rpmhpd SC8280XP_CX>; 1204 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1205 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1206 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1207 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1208 status = "disabled"; 1209 }; 1210 1211 spi1: spi@984000 { 1212 compatible = "qcom,geni-spi"; 1213 reg = <0 0x00984000 0 0x4000>; 1214 #address-cells = <1>; 1215 #size-cells = <0>; 1216 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1217 clock-names = "se"; 1218 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1219 power-domains = <&rpmhpd SC8280XP_CX>; 1220 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1221 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1222 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1223 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1224 status = "disabled"; 1225 }; 1226 1227 i2c2: i2c@988000 { 1228 compatible = "qcom,geni-i2c"; 1229 reg = <0 0x00988000 0 0x4000>; 1230 #address-cells = <1>; 1231 #size-cells = <0>; 1232 clock-names = "se"; 1233 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1234 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1235 power-domains = <&rpmhpd SC8280XP_CX>; 1236 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1237 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1238 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1239 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1240 status = "disabled"; 1241 }; 1242 1243 spi2: spi@988000 { 1244 compatible = "qcom,geni-spi"; 1245 reg = <0 0x00988000 0 0x4000>; 1246 #address-cells = <1>; 1247 #size-cells = <0>; 1248 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1249 clock-names = "se"; 1250 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1251 power-domains = <&rpmhpd SC8280XP_CX>; 1252 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1253 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1254 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1255 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1256 status = "disabled"; 1257 }; 1258 1259 uart2: serial@988000 { 1260 compatible = "qcom,geni-uart"; 1261 reg = <0 0x00988000 0 0x4000>; 1262 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1263 clock-names = "se"; 1264 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1265 operating-points-v2 = <&qup_opp_table_100mhz>; 1266 power-domains = <&rpmhpd SC8280XP_CX>; 1267 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1268 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 1269 interconnect-names = "qup-core", "qup-config"; 1270 status = "disabled"; 1271 }; 1272 1273 i2c3: i2c@98c000 { 1274 compatible = "qcom,geni-i2c"; 1275 reg = <0 0x0098c000 0 0x4000>; 1276 #address-cells = <1>; 1277 #size-cells = <0>; 1278 clock-names = "se"; 1279 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1280 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1281 power-domains = <&rpmhpd SC8280XP_CX>; 1282 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1283 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1284 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1285 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1286 status = "disabled"; 1287 }; 1288 1289 spi3: spi@98c000 { 1290 compatible = "qcom,geni-spi"; 1291 reg = <0 0x0098c000 0 0x4000>; 1292 #address-cells = <1>; 1293 #size-cells = <0>; 1294 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1295 clock-names = "se"; 1296 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1297 power-domains = <&rpmhpd SC8280XP_CX>; 1298 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1299 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1300 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1301 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1302 status = "disabled"; 1303 }; 1304 1305 i2c4: i2c@990000 { 1306 compatible = "qcom,geni-i2c"; 1307 reg = <0 0x00990000 0 0x4000>; 1308 clock-names = "se"; 1309 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1310 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1311 #address-cells = <1>; 1312 #size-cells = <0>; 1313 power-domains = <&rpmhpd SC8280XP_CX>; 1314 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1315 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1316 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1317 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1318 status = "disabled"; 1319 }; 1320 1321 spi4: spi@990000 { 1322 compatible = "qcom,geni-spi"; 1323 reg = <0 0x00990000 0 0x4000>; 1324 #address-cells = <1>; 1325 #size-cells = <0>; 1326 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1327 clock-names = "se"; 1328 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1329 power-domains = <&rpmhpd SC8280XP_CX>; 1330 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1331 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1332 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1333 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1334 status = "disabled"; 1335 }; 1336 1337 i2c5: i2c@994000 { 1338 compatible = "qcom,geni-i2c"; 1339 reg = <0 0x00994000 0 0x4000>; 1340 #address-cells = <1>; 1341 #size-cells = <0>; 1342 clock-names = "se"; 1343 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1344 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1345 power-domains = <&rpmhpd SC8280XP_CX>; 1346 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1347 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1348 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1349 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1350 status = "disabled"; 1351 }; 1352 1353 spi5: spi@994000 { 1354 compatible = "qcom,geni-spi"; 1355 reg = <0 0x00994000 0 0x4000>; 1356 #address-cells = <1>; 1357 #size-cells = <0>; 1358 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1359 clock-names = "se"; 1360 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1361 power-domains = <&rpmhpd SC8280XP_CX>; 1362 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1363 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1364 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1365 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1366 status = "disabled"; 1367 }; 1368 1369 i2c6: i2c@998000 { 1370 compatible = "qcom,geni-i2c"; 1371 reg = <0 0x00998000 0 0x4000>; 1372 #address-cells = <1>; 1373 #size-cells = <0>; 1374 clock-names = "se"; 1375 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1376 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1377 power-domains = <&rpmhpd SC8280XP_CX>; 1378 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1379 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1380 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1381 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1382 status = "disabled"; 1383 }; 1384 1385 spi6: spi@998000 { 1386 compatible = "qcom,geni-spi"; 1387 reg = <0 0x00998000 0 0x4000>; 1388 #address-cells = <1>; 1389 #size-cells = <0>; 1390 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1391 clock-names = "se"; 1392 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1393 power-domains = <&rpmhpd SC8280XP_CX>; 1394 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1395 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1396 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1397 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1398 status = "disabled"; 1399 }; 1400 1401 i2c7: i2c@99c000 { 1402 compatible = "qcom,geni-i2c"; 1403 reg = <0 0x0099c000 0 0x4000>; 1404 #address-cells = <1>; 1405 #size-cells = <0>; 1406 clock-names = "se"; 1407 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1408 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1409 power-domains = <&rpmhpd SC8280XP_CX>; 1410 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1411 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1412 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1413 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1414 status = "disabled"; 1415 }; 1416 1417 spi7: spi@99c000 { 1418 compatible = "qcom,geni-spi"; 1419 reg = <0 0x0099c000 0 0x4000>; 1420 #address-cells = <1>; 1421 #size-cells = <0>; 1422 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1423 clock-names = "se"; 1424 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1425 power-domains = <&rpmhpd SC8280XP_CX>; 1426 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1427 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1428 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1429 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1430 status = "disabled"; 1431 }; 1432 }; 1433 1434 qup1: geniqup@ac0000 { 1435 compatible = "qcom,geni-se-qup"; 1436 reg = <0 0x00ac0000 0 0x6000>; 1437 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1438 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1439 clock-names = "m-ahb", "s-ahb"; 1440 iommus = <&apps_smmu 0x83 0>; 1441 1442 #address-cells = <2>; 1443 #size-cells = <2>; 1444 ranges; 1445 1446 status = "disabled"; 1447 1448 i2c8: i2c@a80000 { 1449 compatible = "qcom,geni-i2c"; 1450 reg = <0 0x00a80000 0 0x4000>; 1451 #address-cells = <1>; 1452 #size-cells = <0>; 1453 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1454 clock-names = "se"; 1455 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1456 power-domains = <&rpmhpd SC8280XP_CX>; 1457 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1458 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1459 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1460 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1461 status = "disabled"; 1462 }; 1463 1464 spi8: spi@a80000 { 1465 compatible = "qcom,geni-spi"; 1466 reg = <0 0x00a80000 0 0x4000>; 1467 #address-cells = <1>; 1468 #size-cells = <0>; 1469 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1470 clock-names = "se"; 1471 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1472 power-domains = <&rpmhpd SC8280XP_CX>; 1473 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1474 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1475 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1476 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1477 status = "disabled"; 1478 }; 1479 1480 i2c9: i2c@a84000 { 1481 compatible = "qcom,geni-i2c"; 1482 reg = <0 0x00a84000 0 0x4000>; 1483 #address-cells = <1>; 1484 #size-cells = <0>; 1485 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1486 clock-names = "se"; 1487 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1488 power-domains = <&rpmhpd SC8280XP_CX>; 1489 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1490 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1491 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1492 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1493 status = "disabled"; 1494 }; 1495 1496 spi9: spi@a84000 { 1497 compatible = "qcom,geni-spi"; 1498 reg = <0 0x00a84000 0 0x4000>; 1499 #address-cells = <1>; 1500 #size-cells = <0>; 1501 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1502 clock-names = "se"; 1503 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1504 power-domains = <&rpmhpd SC8280XP_CX>; 1505 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1506 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1507 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1508 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1509 status = "disabled"; 1510 }; 1511 1512 i2c10: i2c@a88000 { 1513 compatible = "qcom,geni-i2c"; 1514 reg = <0 0x00a88000 0 0x4000>; 1515 #address-cells = <1>; 1516 #size-cells = <0>; 1517 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1518 clock-names = "se"; 1519 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1520 power-domains = <&rpmhpd SC8280XP_CX>; 1521 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1522 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1523 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1524 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1525 status = "disabled"; 1526 }; 1527 1528 spi10: spi@a88000 { 1529 compatible = "qcom,geni-spi"; 1530 reg = <0 0x00a88000 0 0x4000>; 1531 #address-cells = <1>; 1532 #size-cells = <0>; 1533 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1534 clock-names = "se"; 1535 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1536 power-domains = <&rpmhpd SC8280XP_CX>; 1537 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1538 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1539 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1540 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1541 status = "disabled"; 1542 }; 1543 1544 i2c11: i2c@a8c000 { 1545 compatible = "qcom,geni-i2c"; 1546 reg = <0 0x00a8c000 0 0x4000>; 1547 #address-cells = <1>; 1548 #size-cells = <0>; 1549 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1550 clock-names = "se"; 1551 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1552 power-domains = <&rpmhpd SC8280XP_CX>; 1553 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1554 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1555 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1556 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1557 status = "disabled"; 1558 }; 1559 1560 spi11: spi@a8c000 { 1561 compatible = "qcom,geni-spi"; 1562 reg = <0 0x00a8c000 0 0x4000>; 1563 #address-cells = <1>; 1564 #size-cells = <0>; 1565 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1566 clock-names = "se"; 1567 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1568 power-domains = <&rpmhpd SC8280XP_CX>; 1569 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1570 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1571 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1572 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1573 status = "disabled"; 1574 }; 1575 1576 i2c12: i2c@a90000 { 1577 compatible = "qcom,geni-i2c"; 1578 reg = <0 0x00a90000 0 0x4000>; 1579 #address-cells = <1>; 1580 #size-cells = <0>; 1581 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1582 clock-names = "se"; 1583 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1584 power-domains = <&rpmhpd SC8280XP_CX>; 1585 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1586 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1587 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1588 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1589 status = "disabled"; 1590 }; 1591 1592 spi12: spi@a90000 { 1593 compatible = "qcom,geni-spi"; 1594 reg = <0 0x00a90000 0 0x4000>; 1595 #address-cells = <1>; 1596 #size-cells = <0>; 1597 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1598 clock-names = "se"; 1599 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1600 power-domains = <&rpmhpd SC8280XP_CX>; 1601 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1602 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1603 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1604 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1605 status = "disabled"; 1606 }; 1607 1608 i2c13: i2c@a94000 { 1609 compatible = "qcom,geni-i2c"; 1610 reg = <0 0x00a94000 0 0x4000>; 1611 #address-cells = <1>; 1612 #size-cells = <0>; 1613 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1614 clock-names = "se"; 1615 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1616 power-domains = <&rpmhpd SC8280XP_CX>; 1617 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1618 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1619 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1620 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1621 status = "disabled"; 1622 }; 1623 1624 spi13: spi@a94000 { 1625 compatible = "qcom,geni-spi"; 1626 reg = <0 0x00a94000 0 0x4000>; 1627 #address-cells = <1>; 1628 #size-cells = <0>; 1629 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1630 clock-names = "se"; 1631 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1632 power-domains = <&rpmhpd SC8280XP_CX>; 1633 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1634 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1635 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1636 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1637 status = "disabled"; 1638 }; 1639 1640 i2c14: i2c@a98000 { 1641 compatible = "qcom,geni-i2c"; 1642 reg = <0 0x00a98000 0 0x4000>; 1643 #address-cells = <1>; 1644 #size-cells = <0>; 1645 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1646 clock-names = "se"; 1647 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>; 1648 power-domains = <&rpmhpd SC8280XP_CX>; 1649 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1650 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1651 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1652 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1653 status = "disabled"; 1654 }; 1655 1656 spi14: spi@a98000 { 1657 compatible = "qcom,geni-spi"; 1658 reg = <0 0x00a98000 0 0x4000>; 1659 #address-cells = <1>; 1660 #size-cells = <0>; 1661 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1662 clock-names = "se"; 1663 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>; 1664 power-domains = <&rpmhpd SC8280XP_CX>; 1665 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1666 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1667 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1668 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1669 status = "disabled"; 1670 }; 1671 1672 i2c15: i2c@a9c000 { 1673 compatible = "qcom,geni-i2c"; 1674 reg = <0 0x00a9c000 0 0x4000>; 1675 #address-cells = <1>; 1676 #size-cells = <0>; 1677 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1678 clock-names = "se"; 1679 interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>; 1680 power-domains = <&rpmhpd SC8280XP_CX>; 1681 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1682 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1683 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1684 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1685 status = "disabled"; 1686 }; 1687 1688 spi15: spi@a9c000 { 1689 compatible = "qcom,geni-spi"; 1690 reg = <0 0x00a9c000 0 0x4000>; 1691 #address-cells = <1>; 1692 #size-cells = <0>; 1693 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1694 clock-names = "se"; 1695 interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>; 1696 power-domains = <&rpmhpd SC8280XP_CX>; 1697 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1698 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1699 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1700 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1701 status = "disabled"; 1702 }; 1703 }; 1704 1705 rng: rng@10d3000 { 1706 compatible = "qcom,prng-ee"; 1707 reg = <0 0x010d3000 0 0x1000>; 1708 clocks = <&rpmhcc RPMH_HWKM_CLK>; 1709 clock-names = "core"; 1710 }; 1711 1712 pcie4: pcie@1c00000 { 1713 device_type = "pci"; 1714 compatible = "qcom,pcie-sc8280xp"; 1715 reg = <0x0 0x01c00000 0x0 0x3000>, 1716 <0x0 0x30000000 0x0 0xf1d>, 1717 <0x0 0x30000f20 0x0 0xa8>, 1718 <0x0 0x30001000 0x0 0x1000>, 1719 <0x0 0x30100000 0x0 0x100000>, 1720 <0x0 0x01c03000 0x0 0x1000>; 1721 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 1722 #address-cells = <3>; 1723 #size-cells = <2>; 1724 ranges = <0x01000000 0x0 0x00000000 0x0 0x30200000 0x0 0x100000>, 1725 <0x02000000 0x0 0x30300000 0x0 0x30300000 0x0 0x1d00000>; 1726 bus-range = <0x00 0xff>; 1727 1728 dma-coherent; 1729 1730 linux,pci-domain = <6>; 1731 num-lanes = <1>; 1732 1733 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 1734 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1735 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 1736 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 1737 interrupt-names = "msi0", "msi1", "msi2", "msi3"; 1738 1739 #interrupt-cells = <1>; 1740 interrupt-map-mask = <0 0 0 0x7>; 1741 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 1742 <0 0 0 2 &intc 0 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 1743 <0 0 0 3 &intc 0 0 GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 1744 <0 0 0 4 &intc 0 0 GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 1745 1746 clocks = <&gcc GCC_PCIE_4_AUX_CLK>, 1747 <&gcc GCC_PCIE_4_CFG_AHB_CLK>, 1748 <&gcc GCC_PCIE_4_MSTR_AXI_CLK>, 1749 <&gcc GCC_PCIE_4_SLV_AXI_CLK>, 1750 <&gcc GCC_PCIE_4_SLV_Q2A_AXI_CLK>, 1751 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 1752 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, 1753 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>, 1754 <&gcc GCC_CNOC_PCIE4_QX_CLK>; 1755 clock-names = "aux", 1756 "cfg", 1757 "bus_master", 1758 "bus_slave", 1759 "slave_q2a", 1760 "ddrss_sf_tbu", 1761 "noc_aggr_4", 1762 "noc_aggr_south_sf", 1763 "cnoc_qx"; 1764 1765 assigned-clocks = <&gcc GCC_PCIE_4_AUX_CLK>; 1766 assigned-clock-rates = <19200000>; 1767 1768 interconnects = <&aggre2_noc MASTER_PCIE_4 0 &mc_virt SLAVE_EBI1 0>, 1769 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_4 0>; 1770 interconnect-names = "pcie-mem", "cpu-pcie"; 1771 1772 resets = <&gcc GCC_PCIE_4_BCR>; 1773 reset-names = "pci"; 1774 1775 power-domains = <&gcc PCIE_4_GDSC>; 1776 required-opps = <&rpmhpd_opp_nom>; 1777 1778 phys = <&pcie4_phy>; 1779 phy-names = "pciephy"; 1780 1781 status = "disabled"; 1782 }; 1783 1784 pcie4_phy: phy@1c06000 { 1785 compatible = "qcom,sc8280xp-qmp-gen3x1-pcie-phy"; 1786 reg = <0x0 0x01c06000 0x0 0x2000>; 1787 1788 clocks = <&gcc GCC_PCIE_4_AUX_CLK>, 1789 <&gcc GCC_PCIE_4_CFG_AHB_CLK>, 1790 <&gcc GCC_PCIE_4_CLKREF_CLK>, 1791 <&gcc GCC_PCIE4_PHY_RCHNG_CLK>, 1792 <&gcc GCC_PCIE_4_PIPE_CLK>, 1793 <&gcc GCC_PCIE_4_PIPEDIV2_CLK>; 1794 clock-names = "aux", "cfg_ahb", "ref", "rchng", 1795 "pipe", "pipediv2"; 1796 1797 assigned-clocks = <&gcc GCC_PCIE4_PHY_RCHNG_CLK>; 1798 assigned-clock-rates = <100000000>; 1799 1800 power-domains = <&gcc PCIE_4_GDSC>; 1801 1802 resets = <&gcc GCC_PCIE_4_PHY_BCR>; 1803 reset-names = "phy"; 1804 1805 #clock-cells = <0>; 1806 clock-output-names = "pcie_4_pipe_clk"; 1807 1808 #phy-cells = <0>; 1809 1810 status = "disabled"; 1811 }; 1812 1813 pcie3b: pcie@1c08000 { 1814 device_type = "pci"; 1815 compatible = "qcom,pcie-sc8280xp"; 1816 reg = <0x0 0x01c08000 0x0 0x3000>, 1817 <0x0 0x32000000 0x0 0xf1d>, 1818 <0x0 0x32000f20 0x0 0xa8>, 1819 <0x0 0x32001000 0x0 0x1000>, 1820 <0x0 0x32100000 0x0 0x100000>, 1821 <0x0 0x01c0b000 0x0 0x1000>; 1822 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 1823 #address-cells = <3>; 1824 #size-cells = <2>; 1825 ranges = <0x01000000 0x0 0x00000000 0x0 0x32200000 0x0 0x100000>, 1826 <0x02000000 0x0 0x32300000 0x0 0x32300000 0x0 0x1d00000>; 1827 bus-range = <0x00 0xff>; 1828 1829 dma-coherent; 1830 1831 linux,pci-domain = <5>; 1832 num-lanes = <2>; 1833 1834 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1835 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1836 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1837 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 1838 interrupt-names = "msi0", "msi1", "msi2", "msi3"; 1839 1840 #interrupt-cells = <1>; 1841 interrupt-map-mask = <0 0 0 0x7>; 1842 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 526 IRQ_TYPE_LEVEL_HIGH>, 1843 <0 0 0 2 &intc 0 0 GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>, 1844 <0 0 0 3 &intc 0 0 GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH>, 1845 <0 0 0 4 &intc 0 0 GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>; 1846 1847 clocks = <&gcc GCC_PCIE_3B_AUX_CLK>, 1848 <&gcc GCC_PCIE_3B_CFG_AHB_CLK>, 1849 <&gcc GCC_PCIE_3B_MSTR_AXI_CLK>, 1850 <&gcc GCC_PCIE_3B_SLV_AXI_CLK>, 1851 <&gcc GCC_PCIE_3B_SLV_Q2A_AXI_CLK>, 1852 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 1853 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, 1854 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>; 1855 clock-names = "aux", 1856 "cfg", 1857 "bus_master", 1858 "bus_slave", 1859 "slave_q2a", 1860 "ddrss_sf_tbu", 1861 "noc_aggr_4", 1862 "noc_aggr_south_sf"; 1863 1864 assigned-clocks = <&gcc GCC_PCIE_3B_AUX_CLK>; 1865 assigned-clock-rates = <19200000>; 1866 1867 interconnects = <&aggre2_noc MASTER_PCIE_3B 0 &mc_virt SLAVE_EBI1 0>, 1868 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_3B 0>; 1869 interconnect-names = "pcie-mem", "cpu-pcie"; 1870 1871 resets = <&gcc GCC_PCIE_3B_BCR>; 1872 reset-names = "pci"; 1873 1874 power-domains = <&gcc PCIE_3B_GDSC>; 1875 required-opps = <&rpmhpd_opp_nom>; 1876 1877 phys = <&pcie3b_phy>; 1878 phy-names = "pciephy"; 1879 1880 status = "disabled"; 1881 }; 1882 1883 pcie3b_phy: phy@1c0e000 { 1884 compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy"; 1885 reg = <0x0 0x01c0e000 0x0 0x2000>; 1886 1887 clocks = <&gcc GCC_PCIE_3B_AUX_CLK>, 1888 <&gcc GCC_PCIE_3B_CFG_AHB_CLK>, 1889 <&gcc GCC_PCIE_3A3B_CLKREF_CLK>, 1890 <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>, 1891 <&gcc GCC_PCIE_3B_PIPE_CLK>, 1892 <&gcc GCC_PCIE_3B_PIPEDIV2_CLK>; 1893 clock-names = "aux", "cfg_ahb", "ref", "rchng", 1894 "pipe", "pipediv2"; 1895 1896 assigned-clocks = <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>; 1897 assigned-clock-rates = <100000000>; 1898 1899 power-domains = <&gcc PCIE_3B_GDSC>; 1900 1901 resets = <&gcc GCC_PCIE_3B_PHY_BCR>; 1902 reset-names = "phy"; 1903 1904 #clock-cells = <0>; 1905 clock-output-names = "pcie_3b_pipe_clk"; 1906 1907 #phy-cells = <0>; 1908 1909 status = "disabled"; 1910 }; 1911 1912 pcie3a: pcie@1c10000 { 1913 device_type = "pci"; 1914 compatible = "qcom,pcie-sc8280xp"; 1915 reg = <0x0 0x01c10000 0x0 0x3000>, 1916 <0x0 0x34000000 0x0 0xf1d>, 1917 <0x0 0x34000f20 0x0 0xa8>, 1918 <0x0 0x34001000 0x0 0x1000>, 1919 <0x0 0x34100000 0x0 0x100000>, 1920 <0x0 0x01c13000 0x0 0x1000>; 1921 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 1922 #address-cells = <3>; 1923 #size-cells = <2>; 1924 ranges = <0x01000000 0x0 0x00000000 0x0 0x34200000 0x0 0x100000>, 1925 <0x02000000 0x0 0x34300000 0x0 0x34300000 0x0 0x1d00000>; 1926 bus-range = <0x00 0xff>; 1927 1928 dma-coherent; 1929 1930 linux,pci-domain = <4>; 1931 num-lanes = <4>; 1932 1933 interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 1934 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 1935 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 1936 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; 1937 interrupt-names = "msi0", "msi1", "msi2", "msi3"; 1938 1939 #interrupt-cells = <1>; 1940 interrupt-map-mask = <0 0 0 0x7>; 1941 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>, 1942 <0 0 0 2 &intc 0 0 GIC_SPI 542 IRQ_TYPE_LEVEL_HIGH>, 1943 <0 0 0 3 &intc 0 0 GIC_SPI 543 IRQ_TYPE_LEVEL_HIGH>, 1944 <0 0 0 4 &intc 0 0 GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>; 1945 1946 clocks = <&gcc GCC_PCIE_3A_AUX_CLK>, 1947 <&gcc GCC_PCIE_3A_CFG_AHB_CLK>, 1948 <&gcc GCC_PCIE_3A_MSTR_AXI_CLK>, 1949 <&gcc GCC_PCIE_3A_SLV_AXI_CLK>, 1950 <&gcc GCC_PCIE_3A_SLV_Q2A_AXI_CLK>, 1951 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 1952 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, 1953 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>; 1954 clock-names = "aux", 1955 "cfg", 1956 "bus_master", 1957 "bus_slave", 1958 "slave_q2a", 1959 "ddrss_sf_tbu", 1960 "noc_aggr_4", 1961 "noc_aggr_south_sf"; 1962 1963 assigned-clocks = <&gcc GCC_PCIE_3A_AUX_CLK>; 1964 assigned-clock-rates = <19200000>; 1965 1966 interconnects = <&aggre2_noc MASTER_PCIE_3A 0 &mc_virt SLAVE_EBI1 0>, 1967 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_3A 0>; 1968 interconnect-names = "pcie-mem", "cpu-pcie"; 1969 1970 resets = <&gcc GCC_PCIE_3A_BCR>; 1971 reset-names = "pci"; 1972 1973 power-domains = <&gcc PCIE_3A_GDSC>; 1974 required-opps = <&rpmhpd_opp_nom>; 1975 1976 phys = <&pcie3a_phy>; 1977 phy-names = "pciephy"; 1978 1979 status = "disabled"; 1980 }; 1981 1982 pcie3a_phy: phy@1c14000 { 1983 compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy"; 1984 reg = <0x0 0x01c14000 0x0 0x2000>, 1985 <0x0 0x01c16000 0x0 0x2000>; 1986 1987 clocks = <&gcc GCC_PCIE_3A_AUX_CLK>, 1988 <&gcc GCC_PCIE_3A_CFG_AHB_CLK>, 1989 <&gcc GCC_PCIE_3A3B_CLKREF_CLK>, 1990 <&gcc GCC_PCIE3A_PHY_RCHNG_CLK>, 1991 <&gcc GCC_PCIE_3A_PIPE_CLK>, 1992 <&gcc GCC_PCIE_3A_PIPEDIV2_CLK>; 1993 clock-names = "aux", "cfg_ahb", "ref", "rchng", 1994 "pipe", "pipediv2"; 1995 1996 assigned-clocks = <&gcc GCC_PCIE3A_PHY_RCHNG_CLK>; 1997 assigned-clock-rates = <100000000>; 1998 1999 power-domains = <&gcc PCIE_3A_GDSC>; 2000 2001 resets = <&gcc GCC_PCIE_3A_PHY_BCR>; 2002 reset-names = "phy"; 2003 2004 qcom,4ln-config-sel = <&tcsr 0xa044 1>; 2005 2006 #clock-cells = <0>; 2007 clock-output-names = "pcie_3a_pipe_clk"; 2008 2009 #phy-cells = <0>; 2010 2011 status = "disabled"; 2012 }; 2013 2014 pcie2b: pcie@1c18000 { 2015 device_type = "pci"; 2016 compatible = "qcom,pcie-sc8280xp"; 2017 reg = <0x0 0x01c18000 0x0 0x3000>, 2018 <0x0 0x38000000 0x0 0xf1d>, 2019 <0x0 0x38000f20 0x0 0xa8>, 2020 <0x0 0x38001000 0x0 0x1000>, 2021 <0x0 0x38100000 0x0 0x100000>, 2022 <0x0 0x01c1b000 0x0 0x1000>; 2023 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 2024 #address-cells = <3>; 2025 #size-cells = <2>; 2026 ranges = <0x01000000 0x0 0x00000000 0x0 0x38200000 0x0 0x100000>, 2027 <0x02000000 0x0 0x38300000 0x0 0x38300000 0x0 0x1d00000>; 2028 bus-range = <0x00 0xff>; 2029 2030 dma-coherent; 2031 2032 linux,pci-domain = <3>; 2033 num-lanes = <2>; 2034 2035 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 2036 <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 2037 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 2038 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>; 2039 interrupt-names = "msi0", "msi1", "msi2", "msi3"; 2040 2041 #interrupt-cells = <1>; 2042 interrupt-map-mask = <0 0 0 0x7>; 2043 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, 2044 <0 0 0 2 &intc 0 0 GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, 2045 <0 0 0 3 &intc 0 0 GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, 2046 <0 0 0 4 &intc 0 0 GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>; 2047 2048 clocks = <&gcc GCC_PCIE_2B_AUX_CLK>, 2049 <&gcc GCC_PCIE_2B_CFG_AHB_CLK>, 2050 <&gcc GCC_PCIE_2B_MSTR_AXI_CLK>, 2051 <&gcc GCC_PCIE_2B_SLV_AXI_CLK>, 2052 <&gcc GCC_PCIE_2B_SLV_Q2A_AXI_CLK>, 2053 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 2054 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, 2055 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>; 2056 clock-names = "aux", 2057 "cfg", 2058 "bus_master", 2059 "bus_slave", 2060 "slave_q2a", 2061 "ddrss_sf_tbu", 2062 "noc_aggr_4", 2063 "noc_aggr_south_sf"; 2064 2065 assigned-clocks = <&gcc GCC_PCIE_2B_AUX_CLK>; 2066 assigned-clock-rates = <19200000>; 2067 2068 interconnects = <&aggre2_noc MASTER_PCIE_2B 0 &mc_virt SLAVE_EBI1 0>, 2069 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_2B 0>; 2070 interconnect-names = "pcie-mem", "cpu-pcie"; 2071 2072 resets = <&gcc GCC_PCIE_2B_BCR>; 2073 reset-names = "pci"; 2074 2075 power-domains = <&gcc PCIE_2B_GDSC>; 2076 required-opps = <&rpmhpd_opp_nom>; 2077 2078 phys = <&pcie2b_phy>; 2079 phy-names = "pciephy"; 2080 2081 status = "disabled"; 2082 }; 2083 2084 pcie2b_phy: phy@1c1e000 { 2085 compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy"; 2086 reg = <0x0 0x01c1e000 0x0 0x2000>; 2087 2088 clocks = <&gcc GCC_PCIE_2B_AUX_CLK>, 2089 <&gcc GCC_PCIE_2B_CFG_AHB_CLK>, 2090 <&gcc GCC_PCIE_2A2B_CLKREF_CLK>, 2091 <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>, 2092 <&gcc GCC_PCIE_2B_PIPE_CLK>, 2093 <&gcc GCC_PCIE_2B_PIPEDIV2_CLK>; 2094 clock-names = "aux", "cfg_ahb", "ref", "rchng", 2095 "pipe", "pipediv2"; 2096 2097 assigned-clocks = <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>; 2098 assigned-clock-rates = <100000000>; 2099 2100 power-domains = <&gcc PCIE_2B_GDSC>; 2101 2102 resets = <&gcc GCC_PCIE_2B_PHY_BCR>; 2103 reset-names = "phy"; 2104 2105 #clock-cells = <0>; 2106 clock-output-names = "pcie_2b_pipe_clk"; 2107 2108 #phy-cells = <0>; 2109 2110 status = "disabled"; 2111 }; 2112 2113 pcie2a: pcie@1c20000 { 2114 device_type = "pci"; 2115 compatible = "qcom,pcie-sc8280xp"; 2116 reg = <0x0 0x01c20000 0x0 0x3000>, 2117 <0x0 0x3c000000 0x0 0xf1d>, 2118 <0x0 0x3c000f20 0x0 0xa8>, 2119 <0x0 0x3c001000 0x0 0x1000>, 2120 <0x0 0x3c100000 0x0 0x100000>, 2121 <0x0 0x01c23000 0x0 0x1000>; 2122 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 2123 #address-cells = <3>; 2124 #size-cells = <2>; 2125 ranges = <0x01000000 0x0 0x00000000 0x0 0x3c200000 0x0 0x100000>, 2126 <0x02000000 0x0 0x3c300000 0x0 0x3c300000 0x0 0x1d00000>; 2127 bus-range = <0x00 0xff>; 2128 2129 dma-coherent; 2130 2131 linux,pci-domain = <2>; 2132 num-lanes = <4>; 2133 2134 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 2135 <GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH>, 2136 <GIC_SPI 524 IRQ_TYPE_LEVEL_HIGH>, 2137 <GIC_SPI 525 IRQ_TYPE_LEVEL_HIGH>; 2138 interrupt-names = "msi0", "msi1", "msi2", "msi3"; 2139 2140 #interrupt-cells = <1>; 2141 interrupt-map-mask = <0 0 0 0x7>; 2142 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>, 2143 <0 0 0 2 &intc 0 0 GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>, 2144 <0 0 0 3 &intc 0 0 GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>, 2145 <0 0 0 4 &intc 0 0 GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>; 2146 2147 clocks = <&gcc GCC_PCIE_2A_AUX_CLK>, 2148 <&gcc GCC_PCIE_2A_CFG_AHB_CLK>, 2149 <&gcc GCC_PCIE_2A_MSTR_AXI_CLK>, 2150 <&gcc GCC_PCIE_2A_SLV_AXI_CLK>, 2151 <&gcc GCC_PCIE_2A_SLV_Q2A_AXI_CLK>, 2152 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 2153 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, 2154 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>; 2155 clock-names = "aux", 2156 "cfg", 2157 "bus_master", 2158 "bus_slave", 2159 "slave_q2a", 2160 "ddrss_sf_tbu", 2161 "noc_aggr_4", 2162 "noc_aggr_south_sf"; 2163 2164 assigned-clocks = <&gcc GCC_PCIE_2A_AUX_CLK>; 2165 assigned-clock-rates = <19200000>; 2166 2167 interconnects = <&aggre2_noc MASTER_PCIE_2A 0 &mc_virt SLAVE_EBI1 0>, 2168 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_2A 0>; 2169 interconnect-names = "pcie-mem", "cpu-pcie"; 2170 2171 resets = <&gcc GCC_PCIE_2A_BCR>; 2172 reset-names = "pci"; 2173 2174 power-domains = <&gcc PCIE_2A_GDSC>; 2175 required-opps = <&rpmhpd_opp_nom>; 2176 2177 phys = <&pcie2a_phy>; 2178 phy-names = "pciephy"; 2179 2180 status = "disabled"; 2181 }; 2182 2183 pcie2a_phy: phy@1c24000 { 2184 compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy"; 2185 reg = <0x0 0x01c24000 0x0 0x2000>, 2186 <0x0 0x01c26000 0x0 0x2000>; 2187 2188 clocks = <&gcc GCC_PCIE_2A_AUX_CLK>, 2189 <&gcc GCC_PCIE_2A_CFG_AHB_CLK>, 2190 <&gcc GCC_PCIE_2A2B_CLKREF_CLK>, 2191 <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>, 2192 <&gcc GCC_PCIE_2A_PIPE_CLK>, 2193 <&gcc GCC_PCIE_2A_PIPEDIV2_CLK>; 2194 clock-names = "aux", "cfg_ahb", "ref", "rchng", 2195 "pipe", "pipediv2"; 2196 2197 assigned-clocks = <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>; 2198 assigned-clock-rates = <100000000>; 2199 2200 power-domains = <&gcc PCIE_2A_GDSC>; 2201 2202 resets = <&gcc GCC_PCIE_2A_PHY_BCR>; 2203 reset-names = "phy"; 2204 2205 qcom,4ln-config-sel = <&tcsr 0xa044 0>; 2206 2207 #clock-cells = <0>; 2208 clock-output-names = "pcie_2a_pipe_clk"; 2209 2210 #phy-cells = <0>; 2211 2212 status = "disabled"; 2213 }; 2214 2215 ufs_mem_hc: ufs@1d84000 { 2216 compatible = "qcom,sc8280xp-ufshc", "qcom,ufshc", 2217 "jedec,ufs-2.0"; 2218 reg = <0 0x01d84000 0 0x3000>; 2219 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2220 phys = <&ufs_mem_phy>; 2221 phy-names = "ufsphy"; 2222 lanes-per-direction = <2>; 2223 #reset-cells = <1>; 2224 resets = <&gcc GCC_UFS_PHY_BCR>; 2225 reset-names = "rst"; 2226 2227 power-domains = <&gcc UFS_PHY_GDSC>; 2228 required-opps = <&rpmhpd_opp_nom>; 2229 2230 iommus = <&apps_smmu 0xe0 0x0>; 2231 dma-coherent; 2232 2233 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 2234 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2235 <&gcc GCC_UFS_PHY_AHB_CLK>, 2236 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2237 <&gcc GCC_UFS_REF_CLKREF_CLK>, 2238 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2239 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2240 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 2241 clock-names = "core_clk", 2242 "bus_aggr_clk", 2243 "iface_clk", 2244 "core_clk_unipro", 2245 "ref_clk", 2246 "tx_lane0_sync_clk", 2247 "rx_lane0_sync_clk", 2248 "rx_lane1_sync_clk"; 2249 freq-table-hz = <75000000 300000000>, 2250 <0 0>, 2251 <0 0>, 2252 <75000000 300000000>, 2253 <0 0>, 2254 <0 0>, 2255 <0 0>, 2256 <0 0>; 2257 status = "disabled"; 2258 }; 2259 2260 ufs_mem_phy: phy@1d87000 { 2261 compatible = "qcom,sc8280xp-qmp-ufs-phy"; 2262 reg = <0 0x01d87000 0 0x1000>; 2263 2264 clocks = <&gcc GCC_UFS_CARD_CLKREF_CLK>, 2265 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 2266 clock-names = "ref", "ref_aux"; 2267 2268 power-domains = <&gcc UFS_PHY_GDSC>; 2269 2270 resets = <&ufs_mem_hc 0>; 2271 reset-names = "ufsphy"; 2272 2273 #phy-cells = <0>; 2274 2275 status = "disabled"; 2276 }; 2277 2278 ufs_card_hc: ufs@1da4000 { 2279 compatible = "qcom,sc8280xp-ufshc", "qcom,ufshc", 2280 "jedec,ufs-2.0"; 2281 reg = <0 0x01da4000 0 0x3000>; 2282 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 2283 phys = <&ufs_card_phy>; 2284 phy-names = "ufsphy"; 2285 lanes-per-direction = <2>; 2286 #reset-cells = <1>; 2287 resets = <&gcc GCC_UFS_CARD_BCR>; 2288 reset-names = "rst"; 2289 2290 power-domains = <&gcc UFS_CARD_GDSC>; 2291 2292 iommus = <&apps_smmu 0x4a0 0x0>; 2293 dma-coherent; 2294 2295 clocks = <&gcc GCC_UFS_CARD_AXI_CLK>, 2296 <&gcc GCC_AGGRE_UFS_CARD_AXI_CLK>, 2297 <&gcc GCC_UFS_CARD_AHB_CLK>, 2298 <&gcc GCC_UFS_CARD_UNIPRO_CORE_CLK>, 2299 <&gcc GCC_UFS_REF_CLKREF_CLK>, 2300 <&gcc GCC_UFS_CARD_TX_SYMBOL_0_CLK>, 2301 <&gcc GCC_UFS_CARD_RX_SYMBOL_0_CLK>, 2302 <&gcc GCC_UFS_CARD_RX_SYMBOL_1_CLK>; 2303 clock-names = "core_clk", 2304 "bus_aggr_clk", 2305 "iface_clk", 2306 "core_clk_unipro", 2307 "ref_clk", 2308 "tx_lane0_sync_clk", 2309 "rx_lane0_sync_clk", 2310 "rx_lane1_sync_clk"; 2311 freq-table-hz = <75000000 300000000>, 2312 <0 0>, 2313 <0 0>, 2314 <75000000 300000000>, 2315 <0 0>, 2316 <0 0>, 2317 <0 0>, 2318 <0 0>; 2319 status = "disabled"; 2320 }; 2321 2322 ufs_card_phy: phy@1da7000 { 2323 compatible = "qcom,sc8280xp-qmp-ufs-phy"; 2324 reg = <0 0x01da7000 0 0x1000>; 2325 2326 clocks = <&gcc GCC_UFS_1_CARD_CLKREF_CLK>, 2327 <&gcc GCC_UFS_CARD_PHY_AUX_CLK>; 2328 clock-names = "ref", "ref_aux"; 2329 2330 power-domains = <&gcc UFS_CARD_GDSC>; 2331 2332 resets = <&ufs_card_hc 0>; 2333 reset-names = "ufsphy"; 2334 2335 #phy-cells = <0>; 2336 2337 status = "disabled"; 2338 }; 2339 2340 tcsr_mutex: hwlock@1f40000 { 2341 compatible = "qcom,tcsr-mutex"; 2342 reg = <0x0 0x01f40000 0x0 0x20000>; 2343 #hwlock-cells = <1>; 2344 }; 2345 2346 tcsr: syscon@1fc0000 { 2347 compatible = "qcom,sc8280xp-tcsr", "syscon"; 2348 reg = <0x0 0x01fc0000 0x0 0x30000>; 2349 }; 2350 2351 gpu: gpu@3d00000 { 2352 compatible = "qcom,adreno-690.0", "qcom,adreno"; 2353 2354 reg = <0 0x03d00000 0 0x40000>, 2355 <0 0x03d9e000 0 0x1000>, 2356 <0 0x03d61000 0 0x800>; 2357 reg-names = "kgsl_3d0_reg_memory", 2358 "cx_mem", 2359 "cx_dbgc"; 2360 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2361 iommus = <&gpu_smmu 0 0xc00>, <&gpu_smmu 1 0xc00>; 2362 operating-points-v2 = <&gpu_opp_table>; 2363 2364 qcom,gmu = <&gmu>; 2365 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 2366 interconnect-names = "gfx-mem"; 2367 #cooling-cells = <2>; 2368 2369 status = "disabled"; 2370 2371 gpu_opp_table: opp-table { 2372 compatible = "operating-points-v2"; 2373 2374 opp-270000000 { 2375 opp-hz = /bits/ 64 <270000000>; 2376 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2377 opp-peak-kBps = <451000>; 2378 }; 2379 2380 opp-410000000 { 2381 opp-hz = /bits/ 64 <410000000>; 2382 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2383 opp-peak-kBps = <1555000>; 2384 }; 2385 2386 opp-500000000 { 2387 opp-hz = /bits/ 64 <500000000>; 2388 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2389 opp-peak-kBps = <1555000>; 2390 }; 2391 2392 opp-547000000 { 2393 opp-hz = /bits/ 64 <547000000>; 2394 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 2395 opp-peak-kBps = <1555000>; 2396 }; 2397 2398 opp-606000000 { 2399 opp-hz = /bits/ 64 <606000000>; 2400 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2401 opp-peak-kBps = <2736000>; 2402 }; 2403 2404 opp-640000000 { 2405 opp-hz = /bits/ 64 <640000000>; 2406 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2407 opp-peak-kBps = <2736000>; 2408 }; 2409 2410 opp-655000000 { 2411 opp-hz = /bits/ 64 <655000000>; 2412 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2413 opp-peak-kBps = <2736000>; 2414 }; 2415 2416 opp-690000000 { 2417 opp-hz = /bits/ 64 <690000000>; 2418 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 2419 opp-peak-kBps = <2736000>; 2420 }; 2421 }; 2422 }; 2423 2424 gmu: gmu@3d6a000 { 2425 compatible = "qcom,adreno-gmu-690.0", "qcom,adreno-gmu"; 2426 reg = <0 0x03d6a000 0 0x34000>, 2427 <0 0x03de0000 0 0x10000>, 2428 <0 0x0b290000 0 0x10000>; 2429 reg-names = "gmu", "rscc", "gmu_pdc"; 2430 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2431 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2432 interrupt-names = "hfi", "gmu"; 2433 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 2434 <&gpucc GPU_CC_CXO_CLK>, 2435 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2436 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2437 <&gpucc GPU_CC_AHB_CLK>, 2438 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2439 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; 2440 clock-names = "gmu", 2441 "cxo", 2442 "axi", 2443 "memnoc", 2444 "ahb", 2445 "hub", 2446 "smmu_vote"; 2447 power-domains = <&gpucc GPU_CC_CX_GDSC>, 2448 <&gpucc GPU_CC_GX_GDSC>; 2449 power-domain-names = "cx", 2450 "gx"; 2451 iommus = <&gpu_smmu 5 0xc00>; 2452 operating-points-v2 = <&gmu_opp_table>; 2453 2454 gmu_opp_table: opp-table { 2455 compatible = "operating-points-v2"; 2456 2457 opp-200000000 { 2458 opp-hz = /bits/ 64 <200000000>; 2459 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2460 }; 2461 2462 opp-500000000 { 2463 opp-hz = /bits/ 64 <500000000>; 2464 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2465 }; 2466 }; 2467 }; 2468 2469 gpucc: clock-controller@3d90000 { 2470 compatible = "qcom,sc8280xp-gpucc"; 2471 reg = <0 0x03d90000 0 0x9000>; 2472 clocks = <&rpmhcc RPMH_CXO_CLK>, 2473 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2474 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2475 clock-names = "bi_tcxo", 2476 "gcc_gpu_gpll0_clk_src", 2477 "gcc_gpu_gpll0_div_clk_src"; 2478 2479 power-domains = <&rpmhpd SC8280XP_GFX>; 2480 #clock-cells = <1>; 2481 #reset-cells = <1>; 2482 #power-domain-cells = <1>; 2483 }; 2484 2485 gpu_smmu: iommu@3da0000 { 2486 compatible = "qcom,sc8280xp-smmu-500", "qcom,adreno-smmu", 2487 "qcom,smmu-500", "arm,mmu-500"; 2488 reg = <0 0x03da0000 0 0x20000>; 2489 #iommu-cells = <2>; 2490 #global-interrupts = <2>; 2491 interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>, 2492 <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 2493 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 2494 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 2495 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 2496 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2497 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2498 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2499 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2500 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 2501 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 2502 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>, 2503 <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>, 2504 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>; 2505 2506 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2507 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 2508 <&gpucc GPU_CC_AHB_CLK>, 2509 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 2510 <&gpucc GPU_CC_CX_GMU_CLK>, 2511 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2512 <&gpucc GPU_CC_HUB_AON_CLK>; 2513 clock-names = "gcc_gpu_memnoc_gfx_clk", 2514 "gcc_gpu_snoc_dvm_gfx_clk", 2515 "gpu_cc_ahb_clk", 2516 "gpu_cc_hlos1_vote_gpu_smmu_clk", 2517 "gpu_cc_cx_gmu_clk", 2518 "gpu_cc_hub_cx_int_clk", 2519 "gpu_cc_hub_aon_clk"; 2520 2521 power-domains = <&gpucc GPU_CC_CX_GDSC>; 2522 dma-coherent; 2523 }; 2524 2525 usb_0_hsphy: phy@88e5000 { 2526 compatible = "qcom,sc8280xp-usb-hs-phy", 2527 "qcom,usb-snps-hs-5nm-phy"; 2528 reg = <0 0x088e5000 0 0x400>; 2529 clocks = <&rpmhcc RPMH_CXO_CLK>; 2530 clock-names = "ref"; 2531 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2532 2533 #phy-cells = <0>; 2534 2535 status = "disabled"; 2536 }; 2537 2538 usb_2_hsphy0: phy@88e7000 { 2539 compatible = "qcom,sc8280xp-usb-hs-phy", 2540 "qcom,usb-snps-hs-5nm-phy"; 2541 reg = <0 0x088e7000 0 0x400>; 2542 clocks = <&gcc GCC_USB2_HS0_CLKREF_CLK>; 2543 clock-names = "ref"; 2544 resets = <&gcc GCC_QUSB2PHY_HS0_MP_BCR>; 2545 2546 #phy-cells = <0>; 2547 2548 status = "disabled"; 2549 }; 2550 2551 usb_2_hsphy1: phy@88e8000 { 2552 compatible = "qcom,sc8280xp-usb-hs-phy", 2553 "qcom,usb-snps-hs-5nm-phy"; 2554 reg = <0 0x088e8000 0 0x400>; 2555 clocks = <&gcc GCC_USB2_HS1_CLKREF_CLK>; 2556 clock-names = "ref"; 2557 resets = <&gcc GCC_QUSB2PHY_HS1_MP_BCR>; 2558 2559 #phy-cells = <0>; 2560 2561 status = "disabled"; 2562 }; 2563 2564 usb_2_hsphy2: phy@88e9000 { 2565 compatible = "qcom,sc8280xp-usb-hs-phy", 2566 "qcom,usb-snps-hs-5nm-phy"; 2567 reg = <0 0x088e9000 0 0x400>; 2568 clocks = <&gcc GCC_USB2_HS2_CLKREF_CLK>; 2569 clock-names = "ref"; 2570 resets = <&gcc GCC_QUSB2PHY_HS2_MP_BCR>; 2571 2572 #phy-cells = <0>; 2573 2574 status = "disabled"; 2575 }; 2576 2577 usb_2_hsphy3: phy@88ea000 { 2578 compatible = "qcom,sc8280xp-usb-hs-phy", 2579 "qcom,usb-snps-hs-5nm-phy"; 2580 reg = <0 0x088ea000 0 0x400>; 2581 clocks = <&gcc GCC_USB2_HS3_CLKREF_CLK>; 2582 clock-names = "ref"; 2583 resets = <&gcc GCC_QUSB2PHY_HS3_MP_BCR>; 2584 2585 #phy-cells = <0>; 2586 2587 status = "disabled"; 2588 }; 2589 2590 usb_2_qmpphy0: phy@88ef000 { 2591 compatible = "qcom,sc8280xp-qmp-usb3-uni-phy"; 2592 reg = <0 0x088ef000 0 0x2000>; 2593 2594 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, 2595 <&gcc GCC_USB3_MP0_CLKREF_CLK>, 2596 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, 2597 <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>; 2598 clock-names = "aux", "ref", "com_aux", "pipe"; 2599 2600 resets = <&gcc GCC_USB3_UNIPHY_MP0_BCR>, 2601 <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>; 2602 reset-names = "phy", "phy_phy"; 2603 2604 power-domains = <&gcc USB30_MP_GDSC>; 2605 2606 #clock-cells = <0>; 2607 clock-output-names = "usb2_phy0_pipe_clk"; 2608 2609 #phy-cells = <0>; 2610 2611 status = "disabled"; 2612 }; 2613 2614 usb_2_qmpphy1: phy@88f1000 { 2615 compatible = "qcom,sc8280xp-qmp-usb3-uni-phy"; 2616 reg = <0 0x088f1000 0 0x2000>; 2617 2618 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, 2619 <&gcc GCC_USB3_MP1_CLKREF_CLK>, 2620 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, 2621 <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>; 2622 clock-names = "aux", "ref", "com_aux", "pipe"; 2623 2624 resets = <&gcc GCC_USB3_UNIPHY_MP1_BCR>, 2625 <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>; 2626 reset-names = "phy", "phy_phy"; 2627 2628 power-domains = <&gcc USB30_MP_GDSC>; 2629 2630 #clock-cells = <0>; 2631 clock-output-names = "usb2_phy1_pipe_clk"; 2632 2633 #phy-cells = <0>; 2634 2635 status = "disabled"; 2636 }; 2637 2638 remoteproc_adsp: remoteproc@3000000 { 2639 compatible = "qcom,sc8280xp-adsp-pas"; 2640 reg = <0 0x03000000 0 0x100>; 2641 2642 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, 2643 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 2644 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 2645 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 2646 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>, 2647 <&smp2p_adsp_in 7 IRQ_TYPE_EDGE_RISING>; 2648 interrupt-names = "wdog", "fatal", "ready", 2649 "handover", "stop-ack", "shutdown-ack"; 2650 2651 clocks = <&rpmhcc RPMH_CXO_CLK>; 2652 clock-names = "xo"; 2653 2654 power-domains = <&rpmhpd SC8280XP_LCX>, 2655 <&rpmhpd SC8280XP_LMX>; 2656 power-domain-names = "lcx", "lmx"; 2657 2658 memory-region = <&pil_adsp_mem>; 2659 2660 qcom,qmp = <&aoss_qmp>; 2661 2662 qcom,smem-states = <&smp2p_adsp_out 0>; 2663 qcom,smem-state-names = "stop"; 2664 2665 status = "disabled"; 2666 2667 remoteproc_adsp_glink: glink-edge { 2668 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 2669 IPCC_MPROC_SIGNAL_GLINK_QMP 2670 IRQ_TYPE_EDGE_RISING>; 2671 mboxes = <&ipcc IPCC_CLIENT_LPASS 2672 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2673 2674 label = "lpass"; 2675 qcom,remote-pid = <2>; 2676 2677 gpr { 2678 compatible = "qcom,gpr"; 2679 qcom,glink-channels = "adsp_apps"; 2680 qcom,domain = <GPR_DOMAIN_ID_ADSP>; 2681 qcom,intents = <512 20>; 2682 #address-cells = <1>; 2683 #size-cells = <0>; 2684 2685 q6apm: service@1 { 2686 compatible = "qcom,q6apm"; 2687 reg = <GPR_APM_MODULE_IID>; 2688 #sound-dai-cells = <0>; 2689 qcom,protection-domain = "avs/audio", 2690 "msm/adsp/audio_pd"; 2691 q6apmdai: dais { 2692 compatible = "qcom,q6apm-dais"; 2693 iommus = <&apps_smmu 0x0c01 0x0>; 2694 }; 2695 2696 q6apmbedai: bedais { 2697 compatible = "qcom,q6apm-lpass-dais"; 2698 #sound-dai-cells = <1>; 2699 }; 2700 }; 2701 2702 q6prm: service@2 { 2703 compatible = "qcom,q6prm"; 2704 reg = <GPR_PRM_MODULE_IID>; 2705 qcom,protection-domain = "avs/audio", 2706 "msm/adsp/audio_pd"; 2707 q6prmcc: clock-controller { 2708 compatible = "qcom,q6prm-lpass-clocks"; 2709 #clock-cells = <2>; 2710 }; 2711 }; 2712 }; 2713 }; 2714 }; 2715 2716 rxmacro: rxmacro@3200000 { 2717 compatible = "qcom,sc8280xp-lpass-rx-macro"; 2718 reg = <0 0x03200000 0 0x1000>; 2719 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2720 <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2721 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2722 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2723 <&vamacro>; 2724 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2725 assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2726 <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2727 assigned-clock-rates = <19200000>, <19200000>; 2728 2729 clock-output-names = "mclk"; 2730 #clock-cells = <0>; 2731 #sound-dai-cells = <1>; 2732 2733 pinctrl-names = "default"; 2734 pinctrl-0 = <&rx_swr_default>; 2735 2736 status = "disabled"; 2737 }; 2738 2739 swr1: soundwire-controller@3210000 { 2740 compatible = "qcom,soundwire-v1.6.0"; 2741 reg = <0 0x03210000 0 0x2000>; 2742 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 2743 clocks = <&rxmacro>; 2744 clock-names = "iface"; 2745 resets = <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>; 2746 reset-names = "swr_audio_cgcr"; 2747 label = "RX"; 2748 2749 qcom,din-ports = <0>; 2750 qcom,dout-ports = <5>; 2751 2752 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>; 2753 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0B 0x01 0x00>; 2754 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0B 0x00 0x00>; 2755 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0x00 0xff 0xff>; 2756 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0x0f 0xff 0xff>; 2757 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>; 2758 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff>; 2759 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; 2760 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 2761 2762 #sound-dai-cells = <1>; 2763 #address-cells = <2>; 2764 #size-cells = <0>; 2765 2766 status = "disabled"; 2767 }; 2768 2769 txmacro: txmacro@3220000 { 2770 compatible = "qcom,sc8280xp-lpass-tx-macro"; 2771 reg = <0 0x03220000 0 0x1000>; 2772 pinctrl-names = "default"; 2773 pinctrl-0 = <&tx_swr_default>; 2774 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2775 <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2776 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2777 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2778 <&vamacro>; 2779 2780 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2781 assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2782 <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2783 assigned-clock-rates = <19200000>, <19200000>; 2784 clock-output-names = "mclk"; 2785 2786 #clock-cells = <0>; 2787 #sound-dai-cells = <1>; 2788 2789 status = "disabled"; 2790 }; 2791 2792 wsamacro: codec@3240000 { 2793 compatible = "qcom,sc8280xp-lpass-wsa-macro"; 2794 reg = <0 0x03240000 0 0x1000>; 2795 clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2796 <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2797 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2798 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2799 <&vamacro>; 2800 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2801 assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2802 <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2803 assigned-clock-rates = <19200000>, <19200000>; 2804 2805 #clock-cells = <0>; 2806 clock-output-names = "mclk"; 2807 #sound-dai-cells = <1>; 2808 2809 pinctrl-names = "default"; 2810 pinctrl-0 = <&wsa_swr_default>; 2811 2812 status = "disabled"; 2813 }; 2814 2815 swr0: soundwire-controller@3250000 { 2816 reg = <0 0x03250000 0 0x2000>; 2817 compatible = "qcom,soundwire-v1.6.0"; 2818 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 2819 clocks = <&wsamacro>; 2820 clock-names = "iface"; 2821 resets = <&lpass_audiocc LPASS_AUDIO_SWR_WSA_CGCR>; 2822 reset-names = "swr_audio_cgcr"; 2823 label = "WSA"; 2824 2825 qcom,din-ports = <2>; 2826 qcom,dout-ports = <6>; 2827 2828 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>; 2829 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>; 2830 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>; 2831 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2832 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2833 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2834 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>; 2835 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2836 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2837 2838 #sound-dai-cells = <1>; 2839 #address-cells = <2>; 2840 #size-cells = <0>; 2841 2842 status = "disabled"; 2843 }; 2844 2845 lpass_audiocc: clock-controller@32a9000 { 2846 compatible = "qcom,sc8280xp-lpassaudiocc"; 2847 reg = <0 0x032a9000 0 0x1000>; 2848 #clock-cells = <1>; 2849 #reset-cells = <1>; 2850 }; 2851 2852 swr2: soundwire-controller@3330000 { 2853 compatible = "qcom,soundwire-v1.6.0"; 2854 reg = <0 0x03330000 0 0x2000>; 2855 interrupts = <GIC_SPI 959 IRQ_TYPE_LEVEL_HIGH>, 2856 <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>; 2857 interrupt-names = "core", "wakeup"; 2858 2859 clocks = <&txmacro>; 2860 clock-names = "iface"; 2861 resets = <&lpasscc LPASS_AUDIO_SWR_TX_CGCR>; 2862 reset-names = "swr_audio_cgcr"; 2863 label = "TX"; 2864 #sound-dai-cells = <1>; 2865 #address-cells = <2>; 2866 #size-cells = <0>; 2867 2868 qcom,din-ports = <4>; 2869 qcom,dout-ports = <0>; 2870 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>; 2871 qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02 0x00>; 2872 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>; 2873 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>; 2874 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>; 2875 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>; 2876 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>; 2877 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>; 2878 qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00 0x01>; 2879 2880 status = "disabled"; 2881 }; 2882 2883 vamacro: codec@3370000 { 2884 compatible = "qcom,sc8280xp-lpass-va-macro"; 2885 reg = <0 0x03370000 0 0x1000>; 2886 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2887 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2888 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2889 <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2890 clock-names = "mclk", "macro", "dcodec", "npl"; 2891 assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2892 assigned-clock-rates = <19200000>; 2893 2894 #clock-cells = <0>; 2895 clock-output-names = "fsgen"; 2896 #sound-dai-cells = <1>; 2897 2898 status = "disabled"; 2899 }; 2900 2901 lpass_tlmm: pinctrl@33c0000 { 2902 compatible = "qcom,sc8280xp-lpass-lpi-pinctrl"; 2903 reg = <0 0x33c0000 0x0 0x20000>, 2904 <0 0x3550000 0x0 0x10000>; 2905 gpio-controller; 2906 #gpio-cells = <2>; 2907 gpio-ranges = <&lpass_tlmm 0 0 19>; 2908 2909 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2910 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2911 clock-names = "core", "audio"; 2912 2913 status = "disabled"; 2914 2915 tx_swr_default: tx-swr-default-state { 2916 clk-pins { 2917 pins = "gpio0"; 2918 function = "swr_tx_clk"; 2919 drive-strength = <2>; 2920 slew-rate = <1>; 2921 bias-disable; 2922 }; 2923 2924 data-pins { 2925 pins = "gpio1", "gpio2"; 2926 function = "swr_tx_data"; 2927 drive-strength = <2>; 2928 slew-rate = <1>; 2929 bias-bus-hold; 2930 }; 2931 }; 2932 2933 rx_swr_default: rx-swr-default-state { 2934 clk-pins { 2935 pins = "gpio3"; 2936 function = "swr_rx_clk"; 2937 drive-strength = <2>; 2938 slew-rate = <1>; 2939 bias-disable; 2940 }; 2941 2942 data-pins { 2943 pins = "gpio4", "gpio5"; 2944 function = "swr_rx_data"; 2945 drive-strength = <2>; 2946 slew-rate = <1>; 2947 bias-bus-hold; 2948 }; 2949 }; 2950 2951 dmic01_default: dmic01-default-state { 2952 clk-pins { 2953 pins = "gpio6"; 2954 function = "dmic1_clk"; 2955 drive-strength = <8>; 2956 output-high; 2957 }; 2958 2959 data-pins { 2960 pins = "gpio7"; 2961 function = "dmic1_data"; 2962 drive-strength = <8>; 2963 input-enable; 2964 }; 2965 }; 2966 2967 dmic01_sleep: dmic01-sleep-state { 2968 clk-pins { 2969 pins = "gpio6"; 2970 function = "dmic1_clk"; 2971 drive-strength = <2>; 2972 bias-disable; 2973 output-low; 2974 }; 2975 2976 data-pins { 2977 pins = "gpio7"; 2978 function = "dmic1_data"; 2979 drive-strength = <2>; 2980 bias-pull-down; 2981 input-enable; 2982 }; 2983 }; 2984 2985 dmic02_default: dmic02-default-state { 2986 clk-pins { 2987 pins = "gpio8"; 2988 function = "dmic2_clk"; 2989 drive-strength = <8>; 2990 output-high; 2991 }; 2992 2993 data-pins { 2994 pins = "gpio9"; 2995 function = "dmic2_data"; 2996 drive-strength = <8>; 2997 input-enable; 2998 }; 2999 }; 3000 3001 dmic02_sleep: dmic02-sleep-state { 3002 clk-pins { 3003 pins = "gpio8"; 3004 function = "dmic2_clk"; 3005 drive-strength = <2>; 3006 bias-disable; 3007 output-low; 3008 }; 3009 3010 data-pins { 3011 pins = "gpio9"; 3012 function = "dmic2_data"; 3013 drive-strength = <2>; 3014 bias-pull-down; 3015 input-enable; 3016 }; 3017 }; 3018 3019 wsa_swr_default: wsa-swr-default-state { 3020 clk-pins { 3021 pins = "gpio10"; 3022 function = "wsa_swr_clk"; 3023 drive-strength = <2>; 3024 slew-rate = <1>; 3025 bias-disable; 3026 }; 3027 3028 data-pins { 3029 pins = "gpio11"; 3030 function = "wsa_swr_data"; 3031 drive-strength = <2>; 3032 slew-rate = <1>; 3033 bias-bus-hold; 3034 }; 3035 }; 3036 3037 wsa2_swr_default: wsa2-swr-default-state { 3038 clk-pins { 3039 pins = "gpio15"; 3040 function = "wsa2_swr_clk"; 3041 drive-strength = <2>; 3042 slew-rate = <1>; 3043 bias-disable; 3044 }; 3045 3046 data-pins { 3047 pins = "gpio16"; 3048 function = "wsa2_swr_data"; 3049 drive-strength = <2>; 3050 slew-rate = <1>; 3051 bias-bus-hold; 3052 }; 3053 }; 3054 }; 3055 3056 lpasscc: clock-controller@33e0000 { 3057 compatible = "qcom,sc8280xp-lpasscc"; 3058 reg = <0 0x033e0000 0 0x12000>; 3059 #clock-cells = <1>; 3060 #reset-cells = <1>; 3061 }; 3062 3063 sdc2: mmc@8804000 { 3064 compatible = "qcom,sc8280xp-sdhci", "qcom,sdhci-msm-v5"; 3065 reg = <0 0x08804000 0 0x1000>; 3066 3067 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 3068 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 3069 interrupt-names = "hc_irq", "pwr_irq"; 3070 3071 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3072 <&gcc GCC_SDCC2_APPS_CLK>, 3073 <&rpmhcc RPMH_CXO_CLK>; 3074 clock-names = "iface", "core", "xo"; 3075 resets = <&gcc GCC_SDCC2_BCR>; 3076 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 3077 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; 3078 interconnect-names = "sdhc-ddr","cpu-sdhc"; 3079 iommus = <&apps_smmu 0x4e0 0x0>; 3080 power-domains = <&rpmhpd SC8280XP_CX>; 3081 operating-points-v2 = <&sdc2_opp_table>; 3082 bus-width = <4>; 3083 dma-coherent; 3084 3085 status = "disabled"; 3086 3087 sdc2_opp_table: opp-table { 3088 compatible = "operating-points-v2"; 3089 3090 opp-100000000 { 3091 opp-hz = /bits/ 64 <100000000>; 3092 required-opps = <&rpmhpd_opp_low_svs>; 3093 opp-peak-kBps = <1800000 400000>; 3094 opp-avg-kBps = <100000 0>; 3095 }; 3096 3097 opp-202000000 { 3098 opp-hz = /bits/ 64 <202000000>; 3099 required-opps = <&rpmhpd_opp_svs_l1>; 3100 opp-peak-kBps = <5400000 1600000>; 3101 opp-avg-kBps = <200000 0>; 3102 }; 3103 }; 3104 }; 3105 3106 usb_0_qmpphy: phy@88eb000 { 3107 compatible = "qcom,sc8280xp-qmp-usb43dp-phy"; 3108 reg = <0 0x088eb000 0 0x4000>; 3109 3110 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3111 <&gcc GCC_USB4_EUD_CLKREF_CLK>, 3112 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 3113 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3114 clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 3115 3116 power-domains = <&gcc USB30_PRIM_GDSC>; 3117 3118 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 3119 <&gcc GCC_USB4_DP_PHY_PRIM_BCR>; 3120 reset-names = "phy", "common"; 3121 3122 #clock-cells = <1>; 3123 #phy-cells = <1>; 3124 3125 status = "disabled"; 3126 3127 ports { 3128 #address-cells = <1>; 3129 #size-cells = <0>; 3130 3131 port@0 { 3132 reg = <0>; 3133 3134 usb_0_qmpphy_out: endpoint {}; 3135 }; 3136 3137 port@2 { 3138 reg = <2>; 3139 3140 usb_0_qmpphy_dp_in: endpoint {}; 3141 }; 3142 }; 3143 }; 3144 3145 usb_1_hsphy: phy@8902000 { 3146 compatible = "qcom,sc8280xp-usb-hs-phy", 3147 "qcom,usb-snps-hs-5nm-phy"; 3148 reg = <0 0x08902000 0 0x400>; 3149 #phy-cells = <0>; 3150 3151 clocks = <&rpmhcc RPMH_CXO_CLK>; 3152 clock-names = "ref"; 3153 3154 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3155 3156 status = "disabled"; 3157 }; 3158 3159 usb_1_qmpphy: phy@8903000 { 3160 compatible = "qcom,sc8280xp-qmp-usb43dp-phy"; 3161 reg = <0 0x08903000 0 0x4000>; 3162 3163 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 3164 <&gcc GCC_USB4_CLKREF_CLK>, 3165 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, 3166 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 3167 clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 3168 3169 power-domains = <&gcc USB30_SEC_GDSC>; 3170 3171 resets = <&gcc GCC_USB3_PHY_SEC_BCR>, 3172 <&gcc GCC_USB4_1_DP_PHY_PRIM_BCR>; 3173 reset-names = "phy", "common"; 3174 3175 #clock-cells = <1>; 3176 #phy-cells = <1>; 3177 3178 status = "disabled"; 3179 3180 ports { 3181 #address-cells = <1>; 3182 #size-cells = <0>; 3183 3184 port@0 { 3185 reg = <0>; 3186 3187 usb_1_qmpphy_out: endpoint {}; 3188 }; 3189 3190 port@2 { 3191 reg = <2>; 3192 3193 usb_1_qmpphy_dp_in: endpoint {}; 3194 }; 3195 }; 3196 }; 3197 3198 mdss1_dp0_phy: phy@8909a00 { 3199 compatible = "qcom,sc8280xp-dp-phy"; 3200 reg = <0 0x08909a00 0 0x19c>, 3201 <0 0x08909200 0 0xec>, 3202 <0 0x08909600 0 0xec>, 3203 <0 0x08909000 0 0x1c8>; 3204 3205 clocks = <&dispcc1 DISP_CC_MDSS_DPTX0_AUX_CLK>, 3206 <&dispcc1 DISP_CC_MDSS_AHB_CLK>; 3207 clock-names = "aux", "cfg_ahb"; 3208 power-domains = <&rpmhpd SC8280XP_MX>; 3209 3210 #clock-cells = <1>; 3211 #phy-cells = <0>; 3212 3213 status = "disabled"; 3214 }; 3215 3216 mdss1_dp1_phy: phy@890ca00 { 3217 compatible = "qcom,sc8280xp-dp-phy"; 3218 reg = <0 0x0890ca00 0 0x19c>, 3219 <0 0x0890c200 0 0xec>, 3220 <0 0x0890c600 0 0xec>, 3221 <0 0x0890c000 0 0x1c8>; 3222 3223 clocks = <&dispcc1 DISP_CC_MDSS_DPTX1_AUX_CLK>, 3224 <&dispcc1 DISP_CC_MDSS_AHB_CLK>; 3225 clock-names = "aux", "cfg_ahb"; 3226 power-domains = <&rpmhpd SC8280XP_MX>; 3227 3228 #clock-cells = <1>; 3229 #phy-cells = <0>; 3230 3231 status = "disabled"; 3232 }; 3233 3234 pmu@9091000 { 3235 compatible = "qcom,sc8280xp-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; 3236 reg = <0 0x09091000 0 0x1000>; 3237 3238 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 3239 3240 interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>; 3241 3242 operating-points-v2 = <&llcc_bwmon_opp_table>; 3243 3244 llcc_bwmon_opp_table: opp-table { 3245 compatible = "operating-points-v2"; 3246 3247 opp-0 { 3248 opp-peak-kBps = <762000>; 3249 }; 3250 opp-1 { 3251 opp-peak-kBps = <1720000>; 3252 }; 3253 opp-2 { 3254 opp-peak-kBps = <2086000>; 3255 }; 3256 opp-3 { 3257 opp-peak-kBps = <2597000>; 3258 }; 3259 opp-4 { 3260 opp-peak-kBps = <2929000>; 3261 }; 3262 opp-5 { 3263 opp-peak-kBps = <3879000>; 3264 }; 3265 opp-6 { 3266 opp-peak-kBps = <5161000>; 3267 }; 3268 opp-7 { 3269 opp-peak-kBps = <5931000>; 3270 }; 3271 opp-8 { 3272 opp-peak-kBps = <6515000>; 3273 }; 3274 opp-9 { 3275 opp-peak-kBps = <7980000>; 3276 }; 3277 opp-10 { 3278 opp-peak-kBps = <8136000>; 3279 }; 3280 opp-11 { 3281 opp-peak-kBps = <10437000>; 3282 }; 3283 opp-12 { 3284 opp-peak-kBps = <12191000>; 3285 }; 3286 }; 3287 }; 3288 3289 pmu@90b6400 { 3290 compatible = "qcom,sc8280xp-cpu-bwmon", "qcom,sdm845-bwmon"; 3291 reg = <0 0x090b6400 0 0x600>; 3292 3293 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 3294 3295 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>; 3296 operating-points-v2 = <&cpu_bwmon_opp_table>; 3297 3298 cpu_bwmon_opp_table: opp-table { 3299 compatible = "operating-points-v2"; 3300 3301 opp-0 { 3302 opp-peak-kBps = <2288000>; 3303 }; 3304 opp-1 { 3305 opp-peak-kBps = <4577000>; 3306 }; 3307 opp-2 { 3308 opp-peak-kBps = <7110000>; 3309 }; 3310 opp-3 { 3311 opp-peak-kBps = <9155000>; 3312 }; 3313 opp-4 { 3314 opp-peak-kBps = <12298000>; 3315 }; 3316 opp-5 { 3317 opp-peak-kBps = <14236000>; 3318 }; 3319 opp-6 { 3320 opp-peak-kBps = <15258001>; 3321 }; 3322 }; 3323 }; 3324 3325 system-cache-controller@9200000 { 3326 compatible = "qcom,sc8280xp-llcc"; 3327 reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, 3328 <0 0x09300000 0 0x58000>, <0 0x09380000 0 0x58000>, 3329 <0 0x09400000 0 0x58000>, <0 0x09480000 0 0x58000>, 3330 <0 0x09500000 0 0x58000>, <0 0x09580000 0 0x58000>, 3331 <0 0x09600000 0 0x58000>; 3332 reg-names = "llcc0_base", "llcc1_base", "llcc2_base", 3333 "llcc3_base", "llcc4_base", "llcc5_base", 3334 "llcc6_base", "llcc7_base", "llcc_broadcast_base"; 3335 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 3336 }; 3337 3338 usb_0: usb@a6f8800 { 3339 compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3"; 3340 reg = <0 0x0a6f8800 0 0x400>; 3341 #address-cells = <2>; 3342 #size-cells = <2>; 3343 ranges; 3344 3345 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3346 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3347 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3348 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 3349 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3350 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 3351 <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>, 3352 <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>, 3353 <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 3354 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", 3355 "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys"; 3356 3357 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3358 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3359 assigned-clock-rates = <19200000>, <200000000>; 3360 3361 interrupts-extended = <&intc GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>, 3362 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 3363 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 3364 <&pdc 138 IRQ_TYPE_LEVEL_HIGH>; 3365 interrupt-names = "pwr_event", 3366 "dp_hs_phy_irq", 3367 "dm_hs_phy_irq", 3368 "ss_phy_irq"; 3369 3370 power-domains = <&gcc USB30_PRIM_GDSC>; 3371 required-opps = <&rpmhpd_opp_nom>; 3372 3373 resets = <&gcc GCC_USB30_PRIM_BCR>; 3374 3375 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 3376 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; 3377 interconnect-names = "usb-ddr", "apps-usb"; 3378 3379 wakeup-source; 3380 3381 status = "disabled"; 3382 3383 usb_0_dwc3: usb@a600000 { 3384 compatible = "snps,dwc3"; 3385 reg = <0 0x0a600000 0 0xcd00>; 3386 interrupts = <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>; 3387 iommus = <&apps_smmu 0x820 0x0>; 3388 phys = <&usb_0_hsphy>, <&usb_0_qmpphy QMP_USB43DP_USB3_PHY>; 3389 phy-names = "usb2-phy", "usb3-phy"; 3390 3391 port { 3392 usb_0_role_switch: endpoint { 3393 }; 3394 }; 3395 }; 3396 }; 3397 3398 usb_1: usb@a8f8800 { 3399 compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3"; 3400 reg = <0 0x0a8f8800 0 0x400>; 3401 #address-cells = <2>; 3402 #size-cells = <2>; 3403 ranges; 3404 3405 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 3406 <&gcc GCC_USB30_SEC_MASTER_CLK>, 3407 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 3408 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 3409 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3410 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 3411 <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>, 3412 <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>, 3413 <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 3414 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", 3415 "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys"; 3416 3417 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3418 <&gcc GCC_USB30_SEC_MASTER_CLK>; 3419 assigned-clock-rates = <19200000>, <200000000>; 3420 3421 interrupts-extended = <&intc GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>, 3422 <&pdc 12 IRQ_TYPE_EDGE_BOTH>, 3423 <&pdc 13 IRQ_TYPE_EDGE_BOTH>, 3424 <&pdc 136 IRQ_TYPE_LEVEL_HIGH>; 3425 interrupt-names = "pwr_event", 3426 "dp_hs_phy_irq", 3427 "dm_hs_phy_irq", 3428 "ss_phy_irq"; 3429 3430 power-domains = <&gcc USB30_SEC_GDSC>; 3431 required-opps = <&rpmhpd_opp_nom>; 3432 3433 resets = <&gcc GCC_USB30_SEC_BCR>; 3434 3435 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>, 3436 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>; 3437 interconnect-names = "usb-ddr", "apps-usb"; 3438 3439 wakeup-source; 3440 3441 status = "disabled"; 3442 3443 usb_1_dwc3: usb@a800000 { 3444 compatible = "snps,dwc3"; 3445 reg = <0 0x0a800000 0 0xcd00>; 3446 interrupts = <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>; 3447 iommus = <&apps_smmu 0x860 0x0>; 3448 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 3449 phy-names = "usb2-phy", "usb3-phy"; 3450 3451 port { 3452 usb_1_role_switch: endpoint { 3453 }; 3454 }; 3455 }; 3456 }; 3457 3458 mdss0: display-subsystem@ae00000 { 3459 compatible = "qcom,sc8280xp-mdss"; 3460 reg = <0 0x0ae00000 0 0x1000>; 3461 reg-names = "mdss"; 3462 3463 clocks = <&gcc GCC_DISP_AHB_CLK>, 3464 <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 3465 <&dispcc0 DISP_CC_MDSS_MDP_CLK>; 3466 clock-names = "iface", 3467 "ahb", 3468 "core"; 3469 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 3470 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>, 3471 <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>; 3472 interconnect-names = "mdp0-mem", "mdp1-mem"; 3473 iommus = <&apps_smmu 0x1000 0x402>; 3474 power-domains = <&dispcc0 MDSS_GDSC>; 3475 resets = <&dispcc0 DISP_CC_MDSS_CORE_BCR>; 3476 3477 interrupt-controller; 3478 #interrupt-cells = <1>; 3479 #address-cells = <2>; 3480 #size-cells = <2>; 3481 ranges; 3482 3483 status = "disabled"; 3484 3485 mdss0_mdp: display-controller@ae01000 { 3486 compatible = "qcom,sc8280xp-dpu"; 3487 reg = <0 0x0ae01000 0 0x8f000>, 3488 <0 0x0aeb0000 0 0x2008>; 3489 reg-names = "mdp", "vbif"; 3490 3491 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 3492 <&gcc GCC_DISP_SF_AXI_CLK>, 3493 <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 3494 <&dispcc0 DISP_CC_MDSS_MDP_LUT_CLK>, 3495 <&dispcc0 DISP_CC_MDSS_MDP_CLK>, 3496 <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>; 3497 clock-names = "bus", 3498 "nrt_bus", 3499 "iface", 3500 "lut", 3501 "core", 3502 "vsync"; 3503 interrupt-parent = <&mdss0>; 3504 interrupts = <0>; 3505 power-domains = <&rpmhpd SC8280XP_MMCX>; 3506 3507 assigned-clocks = <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>; 3508 assigned-clock-rates = <19200000>; 3509 operating-points-v2 = <&mdss0_mdp_opp_table>; 3510 3511 ports { 3512 #address-cells = <1>; 3513 #size-cells = <0>; 3514 3515 port@0 { 3516 reg = <0>; 3517 mdss0_intf0_out: endpoint { 3518 remote-endpoint = <&mdss0_dp0_in>; 3519 }; 3520 }; 3521 3522 port@4 { 3523 reg = <4>; 3524 mdss0_intf4_out: endpoint { 3525 remote-endpoint = <&mdss0_dp1_in>; 3526 }; 3527 }; 3528 3529 port@5 { 3530 reg = <5>; 3531 mdss0_intf5_out: endpoint { 3532 remote-endpoint = <&mdss0_dp3_in>; 3533 }; 3534 }; 3535 3536 port@6 { 3537 reg = <6>; 3538 mdss0_intf6_out: endpoint { 3539 remote-endpoint = <&mdss0_dp2_in>; 3540 }; 3541 }; 3542 }; 3543 3544 mdss0_mdp_opp_table: opp-table { 3545 compatible = "operating-points-v2"; 3546 3547 opp-200000000 { 3548 opp-hz = /bits/ 64 <200000000>; 3549 required-opps = <&rpmhpd_opp_low_svs>; 3550 }; 3551 3552 opp-300000000 { 3553 opp-hz = /bits/ 64 <300000000>; 3554 required-opps = <&rpmhpd_opp_svs>; 3555 }; 3556 3557 opp-375000000 { 3558 opp-hz = /bits/ 64 <375000000>; 3559 required-opps = <&rpmhpd_opp_svs_l1>; 3560 }; 3561 3562 opp-500000000 { 3563 opp-hz = /bits/ 64 <500000000>; 3564 required-opps = <&rpmhpd_opp_nom>; 3565 }; 3566 opp-600000000 { 3567 opp-hz = /bits/ 64 <600000000>; 3568 required-opps = <&rpmhpd_opp_turbo_l1>; 3569 }; 3570 }; 3571 }; 3572 3573 mdss0_dp0: displayport-controller@ae90000 { 3574 compatible = "qcom,sc8280xp-dp"; 3575 reg = <0 0xae90000 0 0x200>, 3576 <0 0xae90200 0 0x200>, 3577 <0 0xae90400 0 0x600>, 3578 <0 0xae91000 0 0x400>, 3579 <0 0xae91400 0 0x400>; 3580 interrupt-parent = <&mdss0>; 3581 interrupts = <12>; 3582 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 3583 <&dispcc0 DISP_CC_MDSS_DPTX0_AUX_CLK>, 3584 <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_CLK>, 3585 <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 3586 <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; 3587 clock-names = "core_iface", "core_aux", 3588 "ctrl_link", 3589 "ctrl_link_iface", 3590 "stream_pixel"; 3591 3592 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 3593 <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; 3594 assigned-clock-parents = <&usb_0_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3595 <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 3596 3597 phys = <&usb_0_qmpphy QMP_USB43DP_DP_PHY>; 3598 phy-names = "dp"; 3599 3600 #sound-dai-cells = <0>; 3601 3602 operating-points-v2 = <&mdss0_dp0_opp_table>; 3603 power-domains = <&rpmhpd SC8280XP_MMCX>; 3604 3605 status = "disabled"; 3606 3607 ports { 3608 #address-cells = <1>; 3609 #size-cells = <0>; 3610 3611 port@0 { 3612 reg = <0>; 3613 3614 mdss0_dp0_in: endpoint { 3615 remote-endpoint = <&mdss0_intf0_out>; 3616 }; 3617 }; 3618 3619 port@1 { 3620 reg = <1>; 3621 3622 mdss0_dp0_out: endpoint { 3623 }; 3624 }; 3625 }; 3626 3627 mdss0_dp0_opp_table: opp-table { 3628 compatible = "operating-points-v2"; 3629 3630 opp-160000000 { 3631 opp-hz = /bits/ 64 <160000000>; 3632 required-opps = <&rpmhpd_opp_low_svs>; 3633 }; 3634 3635 opp-270000000 { 3636 opp-hz = /bits/ 64 <270000000>; 3637 required-opps = <&rpmhpd_opp_svs>; 3638 }; 3639 3640 opp-540000000 { 3641 opp-hz = /bits/ 64 <540000000>; 3642 required-opps = <&rpmhpd_opp_svs_l1>; 3643 }; 3644 3645 opp-810000000 { 3646 opp-hz = /bits/ 64 <810000000>; 3647 required-opps = <&rpmhpd_opp_nom>; 3648 }; 3649 }; 3650 }; 3651 3652 mdss0_dp1: displayport-controller@ae98000 { 3653 compatible = "qcom,sc8280xp-dp"; 3654 reg = <0 0xae98000 0 0x200>, 3655 <0 0xae98200 0 0x200>, 3656 <0 0xae98400 0 0x600>, 3657 <0 0xae99000 0 0x400>, 3658 <0 0xae99400 0 0x400>; 3659 interrupt-parent = <&mdss0>; 3660 interrupts = <13>; 3661 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 3662 <&dispcc0 DISP_CC_MDSS_DPTX1_AUX_CLK>, 3663 <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_CLK>, 3664 <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, 3665 <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>; 3666 clock-names = "core_iface", "core_aux", 3667 "ctrl_link", 3668 "ctrl_link_iface", "stream_pixel"; 3669 3670 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, 3671 <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>; 3672 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3673 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 3674 3675 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; 3676 phy-names = "dp"; 3677 3678 #sound-dai-cells = <0>; 3679 3680 operating-points-v2 = <&mdss0_dp1_opp_table>; 3681 power-domains = <&rpmhpd SC8280XP_MMCX>; 3682 3683 status = "disabled"; 3684 3685 ports { 3686 #address-cells = <1>; 3687 #size-cells = <0>; 3688 3689 port@0 { 3690 reg = <0>; 3691 3692 mdss0_dp1_in: endpoint { 3693 remote-endpoint = <&mdss0_intf4_out>; 3694 }; 3695 }; 3696 3697 port@1 { 3698 reg = <1>; 3699 3700 mdss0_dp1_out: endpoint { 3701 }; 3702 }; 3703 }; 3704 3705 mdss0_dp1_opp_table: opp-table { 3706 compatible = "operating-points-v2"; 3707 3708 opp-160000000 { 3709 opp-hz = /bits/ 64 <160000000>; 3710 required-opps = <&rpmhpd_opp_low_svs>; 3711 }; 3712 3713 opp-270000000 { 3714 opp-hz = /bits/ 64 <270000000>; 3715 required-opps = <&rpmhpd_opp_svs>; 3716 }; 3717 3718 opp-540000000 { 3719 opp-hz = /bits/ 64 <540000000>; 3720 required-opps = <&rpmhpd_opp_svs_l1>; 3721 }; 3722 3723 opp-810000000 { 3724 opp-hz = /bits/ 64 <810000000>; 3725 required-opps = <&rpmhpd_opp_nom>; 3726 }; 3727 }; 3728 }; 3729 3730 mdss0_dp2: displayport-controller@ae9a000 { 3731 compatible = "qcom,sc8280xp-dp"; 3732 reg = <0 0xae9a000 0 0x200>, 3733 <0 0xae9a200 0 0x200>, 3734 <0 0xae9a400 0 0x600>, 3735 <0 0xae9b000 0 0x400>, 3736 <0 0xae9b400 0 0x400>; 3737 3738 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 3739 <&dispcc0 DISP_CC_MDSS_DPTX2_AUX_CLK>, 3740 <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_CLK>, 3741 <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>, 3742 <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>; 3743 clock-names = "core_iface", "core_aux", 3744 "ctrl_link", 3745 "ctrl_link_iface", "stream_pixel"; 3746 interrupt-parent = <&mdss0>; 3747 interrupts = <14>; 3748 phys = <&mdss0_dp2_phy>; 3749 phy-names = "dp"; 3750 power-domains = <&rpmhpd SC8280XP_MMCX>; 3751 3752 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>, 3753 <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>; 3754 assigned-clock-parents = <&mdss0_dp2_phy 0>, <&mdss0_dp2_phy 1>; 3755 operating-points-v2 = <&mdss0_dp2_opp_table>; 3756 3757 #sound-dai-cells = <0>; 3758 3759 status = "disabled"; 3760 3761 ports { 3762 #address-cells = <1>; 3763 #size-cells = <0>; 3764 3765 port@0 { 3766 reg = <0>; 3767 mdss0_dp2_in: endpoint { 3768 remote-endpoint = <&mdss0_intf6_out>; 3769 }; 3770 }; 3771 3772 port@1 { 3773 reg = <1>; 3774 }; 3775 }; 3776 3777 mdss0_dp2_opp_table: opp-table { 3778 compatible = "operating-points-v2"; 3779 3780 opp-160000000 { 3781 opp-hz = /bits/ 64 <160000000>; 3782 required-opps = <&rpmhpd_opp_low_svs>; 3783 }; 3784 3785 opp-270000000 { 3786 opp-hz = /bits/ 64 <270000000>; 3787 required-opps = <&rpmhpd_opp_svs>; 3788 }; 3789 3790 opp-540000000 { 3791 opp-hz = /bits/ 64 <540000000>; 3792 required-opps = <&rpmhpd_opp_svs_l1>; 3793 }; 3794 3795 opp-810000000 { 3796 opp-hz = /bits/ 64 <810000000>; 3797 required-opps = <&rpmhpd_opp_nom>; 3798 }; 3799 }; 3800 }; 3801 3802 mdss0_dp3: displayport-controller@aea0000 { 3803 compatible = "qcom,sc8280xp-dp"; 3804 reg = <0 0xaea0000 0 0x200>, 3805 <0 0xaea0200 0 0x200>, 3806 <0 0xaea0400 0 0x600>, 3807 <0 0xaea1000 0 0x400>, 3808 <0 0xaea1400 0 0x400>; 3809 3810 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 3811 <&dispcc0 DISP_CC_MDSS_DPTX3_AUX_CLK>, 3812 <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_CLK>, 3813 <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>, 3814 <&dispcc0 DISP_CC_MDSS_DPTX3_PIXEL0_CLK>; 3815 clock-names = "core_iface", "core_aux", 3816 "ctrl_link", 3817 "ctrl_link_iface", "stream_pixel"; 3818 interrupt-parent = <&mdss0>; 3819 interrupts = <15>; 3820 phys = <&mdss0_dp3_phy>; 3821 phy-names = "dp"; 3822 power-domains = <&rpmhpd SC8280XP_MMCX>; 3823 3824 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>, 3825 <&dispcc0 DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>; 3826 assigned-clock-parents = <&mdss0_dp3_phy 0>, <&mdss0_dp3_phy 1>; 3827 operating-points-v2 = <&mdss0_dp3_opp_table>; 3828 3829 #sound-dai-cells = <0>; 3830 3831 status = "disabled"; 3832 3833 ports { 3834 #address-cells = <1>; 3835 #size-cells = <0>; 3836 3837 port@0 { 3838 reg = <0>; 3839 mdss0_dp3_in: endpoint { 3840 remote-endpoint = <&mdss0_intf5_out>; 3841 }; 3842 }; 3843 3844 port@1 { 3845 reg = <1>; 3846 }; 3847 }; 3848 3849 mdss0_dp3_opp_table: opp-table { 3850 compatible = "operating-points-v2"; 3851 3852 opp-160000000 { 3853 opp-hz = /bits/ 64 <160000000>; 3854 required-opps = <&rpmhpd_opp_low_svs>; 3855 }; 3856 3857 opp-270000000 { 3858 opp-hz = /bits/ 64 <270000000>; 3859 required-opps = <&rpmhpd_opp_svs>; 3860 }; 3861 3862 opp-540000000 { 3863 opp-hz = /bits/ 64 <540000000>; 3864 required-opps = <&rpmhpd_opp_svs_l1>; 3865 }; 3866 3867 opp-810000000 { 3868 opp-hz = /bits/ 64 <810000000>; 3869 required-opps = <&rpmhpd_opp_nom>; 3870 }; 3871 }; 3872 }; 3873 }; 3874 3875 mdss0_dp2_phy: phy@aec2a00 { 3876 compatible = "qcom,sc8280xp-dp-phy"; 3877 reg = <0 0x0aec2a00 0 0x19c>, 3878 <0 0x0aec2200 0 0xec>, 3879 <0 0x0aec2600 0 0xec>, 3880 <0 0x0aec2000 0 0x1c8>; 3881 3882 clocks = <&dispcc0 DISP_CC_MDSS_DPTX2_AUX_CLK>, 3883 <&dispcc0 DISP_CC_MDSS_AHB_CLK>; 3884 clock-names = "aux", "cfg_ahb"; 3885 power-domains = <&rpmhpd SC8280XP_MX>; 3886 3887 #clock-cells = <1>; 3888 #phy-cells = <0>; 3889 3890 status = "disabled"; 3891 }; 3892 3893 mdss0_dp3_phy: phy@aec5a00 { 3894 compatible = "qcom,sc8280xp-dp-phy"; 3895 reg = <0 0x0aec5a00 0 0x19c>, 3896 <0 0x0aec5200 0 0xec>, 3897 <0 0x0aec5600 0 0xec>, 3898 <0 0x0aec5000 0 0x1c8>; 3899 3900 clocks = <&dispcc0 DISP_CC_MDSS_DPTX3_AUX_CLK>, 3901 <&dispcc0 DISP_CC_MDSS_AHB_CLK>; 3902 clock-names = "aux", "cfg_ahb"; 3903 power-domains = <&rpmhpd SC8280XP_MX>; 3904 3905 #clock-cells = <1>; 3906 #phy-cells = <0>; 3907 3908 status = "disabled"; 3909 }; 3910 3911 dispcc0: clock-controller@af00000 { 3912 compatible = "qcom,sc8280xp-dispcc0"; 3913 reg = <0 0x0af00000 0 0x20000>; 3914 3915 clocks = <&gcc GCC_DISP_AHB_CLK>, 3916 <&rpmhcc RPMH_CXO_CLK>, 3917 <&sleep_clk>, 3918 <&usb_0_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3919 <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 3920 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3921 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 3922 <&mdss0_dp2_phy 0>, 3923 <&mdss0_dp2_phy 1>, 3924 <&mdss0_dp3_phy 0>, 3925 <&mdss0_dp3_phy 1>, 3926 <0>, 3927 <0>, 3928 <0>, 3929 <0>; 3930 power-domains = <&rpmhpd SC8280XP_MMCX>; 3931 3932 #clock-cells = <1>; 3933 #power-domain-cells = <1>; 3934 #reset-cells = <1>; 3935 3936 status = "disabled"; 3937 }; 3938 3939 pdc: interrupt-controller@b220000 { 3940 compatible = "qcom,sc8280xp-pdc", "qcom,pdc"; 3941 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; 3942 qcom,pdc-ranges = <0 480 40>, 3943 <40 140 14>, 3944 <54 263 1>, 3945 <55 306 4>, 3946 <59 312 3>, 3947 <62 374 2>, 3948 <64 434 2>, 3949 <66 438 3>, 3950 <69 86 1>, 3951 <70 520 54>, 3952 <124 609 28>, 3953 <159 638 1>, 3954 <160 720 8>, 3955 <168 801 1>, 3956 <169 728 30>, 3957 <199 416 2>, 3958 <201 449 1>, 3959 <202 89 1>, 3960 <203 451 1>, 3961 <204 462 1>, 3962 <205 264 1>, 3963 <206 579 1>, 3964 <207 653 1>, 3965 <208 656 1>, 3966 <209 659 1>, 3967 <210 122 1>, 3968 <211 699 1>, 3969 <212 705 1>, 3970 <213 450 1>, 3971 <214 643 1>, 3972 <216 646 5>, 3973 <221 390 5>, 3974 <226 700 3>, 3975 <229 240 3>, 3976 <232 269 1>, 3977 <233 377 1>, 3978 <234 372 1>, 3979 <235 138 1>, 3980 <236 857 1>, 3981 <237 860 1>, 3982 <238 137 1>, 3983 <239 668 1>, 3984 <240 366 1>, 3985 <241 949 1>, 3986 <242 815 5>, 3987 <247 769 1>, 3988 <248 768 1>, 3989 <249 663 1>, 3990 <250 799 2>, 3991 <252 798 1>, 3992 <253 765 1>, 3993 <254 763 1>, 3994 <255 454 1>, 3995 <258 139 1>, 3996 <259 786 2>, 3997 <261 370 2>, 3998 <263 158 2>; 3999 #interrupt-cells = <2>; 4000 interrupt-parent = <&intc>; 4001 interrupt-controller; 4002 }; 4003 4004 tsens0: thermal-sensor@c263000 { 4005 compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2"; 4006 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 4007 <0 0x0c222000 0 0x8>; /* SROT */ 4008 #qcom,sensors = <14>; 4009 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, 4010 <&pdc 28 IRQ_TYPE_LEVEL_HIGH>; 4011 interrupt-names = "uplow", "critical"; 4012 #thermal-sensor-cells = <1>; 4013 }; 4014 4015 tsens1: thermal-sensor@c265000 { 4016 compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2"; 4017 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 4018 <0 0x0c223000 0 0x8>; /* SROT */ 4019 #qcom,sensors = <16>; 4020 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, 4021 <&pdc 29 IRQ_TYPE_LEVEL_HIGH>; 4022 interrupt-names = "uplow", "critical"; 4023 #thermal-sensor-cells = <1>; 4024 }; 4025 4026 aoss_qmp: power-management@c300000 { 4027 compatible = "qcom,sc8280xp-aoss-qmp", "qcom,aoss-qmp"; 4028 reg = <0 0x0c300000 0 0x400>; 4029 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>; 4030 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 4031 4032 #clock-cells = <0>; 4033 }; 4034 4035 sram@c3f0000 { 4036 compatible = "qcom,rpmh-stats"; 4037 reg = <0 0x0c3f0000 0 0x400>; 4038 }; 4039 4040 spmi_bus: spmi@c440000 { 4041 compatible = "qcom,spmi-pmic-arb"; 4042 reg = <0 0x0c440000 0 0x1100>, 4043 <0 0x0c600000 0 0x2000000>, 4044 <0 0x0e600000 0 0x100000>, 4045 <0 0x0e700000 0 0xa0000>, 4046 <0 0x0c40a000 0 0x26000>; 4047 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 4048 interrupt-names = "periph_irq"; 4049 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 4050 qcom,ee = <0>; 4051 qcom,channel = <0>; 4052 #address-cells = <2>; 4053 #size-cells = <0>; 4054 interrupt-controller; 4055 #interrupt-cells = <4>; 4056 }; 4057 4058 tlmm: pinctrl@f100000 { 4059 compatible = "qcom,sc8280xp-tlmm"; 4060 reg = <0 0x0f100000 0 0x300000>; 4061 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 4062 gpio-controller; 4063 #gpio-cells = <2>; 4064 interrupt-controller; 4065 #interrupt-cells = <2>; 4066 gpio-ranges = <&tlmm 0 0 230>; 4067 wakeup-parent = <&pdc>; 4068 }; 4069 4070 apps_smmu: iommu@15000000 { 4071 compatible = "qcom,sc8280xp-smmu-500", "arm,mmu-500"; 4072 reg = <0 0x15000000 0 0x100000>; 4073 #iommu-cells = <2>; 4074 #global-interrupts = <2>; 4075 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 4076 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 4077 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 4078 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 4079 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 4080 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 4081 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 4082 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 4083 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 4084 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 4085 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 4086 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 4087 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 4088 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 4089 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 4090 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 4091 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 4092 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 4093 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 4094 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 4095 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 4096 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 4097 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 4098 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 4099 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 4100 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 4101 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 4102 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 4103 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 4104 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 4105 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 4106 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 4107 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 4108 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 4109 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 4110 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 4111 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 4112 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 4113 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 4114 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 4115 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 4116 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 4117 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 4118 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 4119 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 4120 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 4121 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 4122 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 4123 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 4124 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 4125 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 4126 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 4127 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 4128 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 4129 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 4130 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 4131 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 4132 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 4133 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 4134 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 4135 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 4136 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 4137 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 4138 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 4139 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 4140 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 4141 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 4142 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 4143 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 4144 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 4145 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 4146 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 4147 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 4148 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 4149 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 4150 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 4151 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 4152 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 4153 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 4154 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 4155 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, 4156 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 4157 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 4158 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 4159 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, 4160 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 4161 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 4162 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 4163 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 4164 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 4165 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 4166 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 4167 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 4168 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 4169 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 4170 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>, 4171 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 4172 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 4173 <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>, 4174 <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>, 4175 <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>, 4176 <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>, 4177 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 4178 <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>, 4179 <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>, 4180 <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>, 4181 <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>, 4182 <GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH>, 4183 <GIC_SPI 911 IRQ_TYPE_LEVEL_HIGH>, 4184 <GIC_SPI 910 IRQ_TYPE_LEVEL_HIGH>, 4185 <GIC_SPI 909 IRQ_TYPE_LEVEL_HIGH>, 4186 <GIC_SPI 908 IRQ_TYPE_LEVEL_HIGH>, 4187 <GIC_SPI 907 IRQ_TYPE_LEVEL_HIGH>, 4188 <GIC_SPI 906 IRQ_TYPE_LEVEL_HIGH>, 4189 <GIC_SPI 905 IRQ_TYPE_LEVEL_HIGH>, 4190 <GIC_SPI 904 IRQ_TYPE_LEVEL_HIGH>, 4191 <GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>, 4192 <GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>, 4193 <GIC_SPI 901 IRQ_TYPE_LEVEL_HIGH>, 4194 <GIC_SPI 900 IRQ_TYPE_LEVEL_HIGH>, 4195 <GIC_SPI 899 IRQ_TYPE_LEVEL_HIGH>, 4196 <GIC_SPI 898 IRQ_TYPE_LEVEL_HIGH>, 4197 <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>, 4198 <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>, 4199 <GIC_SPI 895 IRQ_TYPE_LEVEL_HIGH>, 4200 <GIC_SPI 894 IRQ_TYPE_LEVEL_HIGH>, 4201 <GIC_SPI 893 IRQ_TYPE_LEVEL_HIGH>, 4202 <GIC_SPI 892 IRQ_TYPE_LEVEL_HIGH>, 4203 <GIC_SPI 891 IRQ_TYPE_LEVEL_HIGH>, 4204 <GIC_SPI 890 IRQ_TYPE_LEVEL_HIGH>; 4205 }; 4206 4207 intc: interrupt-controller@17a00000 { 4208 compatible = "arm,gic-v3"; 4209 interrupt-controller; 4210 #interrupt-cells = <3>; 4211 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 4212 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 4213 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 4214 #redistributor-regions = <1>; 4215 redistributor-stride = <0 0x20000>; 4216 4217 #address-cells = <2>; 4218 #size-cells = <2>; 4219 ranges; 4220 4221 msi-controller@17a40000 { 4222 compatible = "arm,gic-v3-its"; 4223 reg = <0 0x17a40000 0 0x20000>; 4224 msi-controller; 4225 #msi-cells = <1>; 4226 }; 4227 }; 4228 4229 watchdog@17c10000 { 4230 compatible = "qcom,apss-wdt-sc8280xp", "qcom,kpss-wdt"; 4231 reg = <0 0x17c10000 0 0x1000>; 4232 clocks = <&sleep_clk>; 4233 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 4234 }; 4235 4236 timer@17c20000 { 4237 compatible = "arm,armv7-timer-mem"; 4238 reg = <0x0 0x17c20000 0x0 0x1000>; 4239 #address-cells = <1>; 4240 #size-cells = <1>; 4241 ranges = <0x0 0x0 0x0 0x20000000>; 4242 4243 frame@17c21000 { 4244 frame-number = <0>; 4245 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 4246 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 4247 reg = <0x17c21000 0x1000>, 4248 <0x17c22000 0x1000>; 4249 }; 4250 4251 frame@17c23000 { 4252 frame-number = <1>; 4253 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 4254 reg = <0x17c23000 0x1000>; 4255 status = "disabled"; 4256 }; 4257 4258 frame@17c25000 { 4259 frame-number = <2>; 4260 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 4261 reg = <0x17c25000 0x1000>; 4262 status = "disabled"; 4263 }; 4264 4265 frame@17c27000 { 4266 frame-number = <3>; 4267 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 4268 reg = <0x17c26000 0x1000>; 4269 status = "disabled"; 4270 }; 4271 4272 frame@17c29000 { 4273 frame-number = <4>; 4274 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 4275 reg = <0x17c29000 0x1000>; 4276 status = "disabled"; 4277 }; 4278 4279 frame@17c2b000 { 4280 frame-number = <5>; 4281 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 4282 reg = <0x17c2b000 0x1000>; 4283 status = "disabled"; 4284 }; 4285 4286 frame@17c2d000 { 4287 frame-number = <6>; 4288 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 4289 reg = <0x17c2d000 0x1000>; 4290 status = "disabled"; 4291 }; 4292 }; 4293 4294 apps_rsc: rsc@18200000 { 4295 compatible = "qcom,rpmh-rsc"; 4296 reg = <0x0 0x18200000 0x0 0x10000>, 4297 <0x0 0x18210000 0x0 0x10000>, 4298 <0x0 0x18220000 0x0 0x10000>; 4299 reg-names = "drv-0", "drv-1", "drv-2"; 4300 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 4301 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 4302 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 4303 qcom,tcs-offset = <0xd00>; 4304 qcom,drv-id = <2>; 4305 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 4306 <WAKE_TCS 3>, <CONTROL_TCS 1>; 4307 label = "apps_rsc"; 4308 power-domains = <&CLUSTER_PD>; 4309 4310 apps_bcm_voter: bcm-voter { 4311 compatible = "qcom,bcm-voter"; 4312 }; 4313 4314 rpmhcc: clock-controller { 4315 compatible = "qcom,sc8280xp-rpmh-clk"; 4316 #clock-cells = <1>; 4317 clock-names = "xo"; 4318 clocks = <&xo_board_clk>; 4319 }; 4320 4321 rpmhpd: power-controller { 4322 compatible = "qcom,sc8280xp-rpmhpd"; 4323 #power-domain-cells = <1>; 4324 operating-points-v2 = <&rpmhpd_opp_table>; 4325 4326 rpmhpd_opp_table: opp-table { 4327 compatible = "operating-points-v2"; 4328 4329 rpmhpd_opp_ret: opp1 { 4330 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 4331 }; 4332 4333 rpmhpd_opp_min_svs: opp2 { 4334 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 4335 }; 4336 4337 rpmhpd_opp_low_svs: opp3 { 4338 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4339 }; 4340 4341 rpmhpd_opp_svs: opp4 { 4342 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4343 }; 4344 4345 rpmhpd_opp_svs_l1: opp5 { 4346 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4347 }; 4348 4349 rpmhpd_opp_nom: opp6 { 4350 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4351 }; 4352 4353 rpmhpd_opp_nom_l1: opp7 { 4354 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4355 }; 4356 4357 rpmhpd_opp_nom_l2: opp8 { 4358 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 4359 }; 4360 4361 rpmhpd_opp_turbo: opp9 { 4362 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4363 }; 4364 4365 rpmhpd_opp_turbo_l1: opp10 { 4366 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4367 }; 4368 }; 4369 }; 4370 }; 4371 4372 epss_l3: interconnect@18590000 { 4373 compatible = "qcom,sc8280xp-epss-l3", "qcom,epss-l3"; 4374 reg = <0 0x18590000 0 0x1000>; 4375 4376 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 4377 clock-names = "xo", "alternate"; 4378 4379 #interconnect-cells = <1>; 4380 }; 4381 4382 cpufreq_hw: cpufreq@18591000 { 4383 compatible = "qcom,sc8280xp-cpufreq-epss", "qcom,cpufreq-epss"; 4384 reg = <0 0x18591000 0 0x1000>, 4385 <0 0x18592000 0 0x1000>; 4386 reg-names = "freq-domain0", "freq-domain1"; 4387 4388 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 4389 clock-names = "xo", "alternate"; 4390 4391 #freq-domain-cells = <1>; 4392 #clock-cells = <1>; 4393 }; 4394 4395 remoteproc_nsp0: remoteproc@1b300000 { 4396 compatible = "qcom,sc8280xp-nsp0-pas"; 4397 reg = <0 0x1b300000 0 0x100>; 4398 4399 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, 4400 <&smp2p_nsp0_in 0 IRQ_TYPE_EDGE_RISING>, 4401 <&smp2p_nsp0_in 1 IRQ_TYPE_EDGE_RISING>, 4402 <&smp2p_nsp0_in 2 IRQ_TYPE_EDGE_RISING>, 4403 <&smp2p_nsp0_in 3 IRQ_TYPE_EDGE_RISING>; 4404 interrupt-names = "wdog", "fatal", "ready", 4405 "handover", "stop-ack"; 4406 4407 clocks = <&rpmhcc RPMH_CXO_CLK>; 4408 clock-names = "xo"; 4409 4410 power-domains = <&rpmhpd SC8280XP_NSP>; 4411 power-domain-names = "nsp"; 4412 4413 memory-region = <&pil_nsp0_mem>; 4414 4415 qcom,smem-states = <&smp2p_nsp0_out 0>; 4416 qcom,smem-state-names = "stop"; 4417 4418 interconnects = <&nspa_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>; 4419 4420 status = "disabled"; 4421 4422 glink-edge { 4423 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 4424 IPCC_MPROC_SIGNAL_GLINK_QMP 4425 IRQ_TYPE_EDGE_RISING>; 4426 mboxes = <&ipcc IPCC_CLIENT_CDSP 4427 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4428 4429 label = "nsp0"; 4430 qcom,remote-pid = <5>; 4431 4432 fastrpc { 4433 compatible = "qcom,fastrpc"; 4434 qcom,glink-channels = "fastrpcglink-apps-dsp"; 4435 label = "cdsp"; 4436 #address-cells = <1>; 4437 #size-cells = <0>; 4438 4439 compute-cb@1 { 4440 compatible = "qcom,fastrpc-compute-cb"; 4441 reg = <1>; 4442 iommus = <&apps_smmu 0x3181 0x0420>; 4443 }; 4444 4445 compute-cb@2 { 4446 compatible = "qcom,fastrpc-compute-cb"; 4447 reg = <2>; 4448 iommus = <&apps_smmu 0x3182 0x0420>; 4449 }; 4450 4451 compute-cb@3 { 4452 compatible = "qcom,fastrpc-compute-cb"; 4453 reg = <3>; 4454 iommus = <&apps_smmu 0x3183 0x0420>; 4455 }; 4456 4457 compute-cb@4 { 4458 compatible = "qcom,fastrpc-compute-cb"; 4459 reg = <4>; 4460 iommus = <&apps_smmu 0x3184 0x0420>; 4461 }; 4462 4463 compute-cb@5 { 4464 compatible = "qcom,fastrpc-compute-cb"; 4465 reg = <5>; 4466 iommus = <&apps_smmu 0x3185 0x0420>; 4467 }; 4468 4469 compute-cb@6 { 4470 compatible = "qcom,fastrpc-compute-cb"; 4471 reg = <6>; 4472 iommus = <&apps_smmu 0x3186 0x0420>; 4473 }; 4474 4475 compute-cb@7 { 4476 compatible = "qcom,fastrpc-compute-cb"; 4477 reg = <7>; 4478 iommus = <&apps_smmu 0x3187 0x0420>; 4479 }; 4480 4481 compute-cb@8 { 4482 compatible = "qcom,fastrpc-compute-cb"; 4483 reg = <8>; 4484 iommus = <&apps_smmu 0x3188 0x0420>; 4485 }; 4486 4487 compute-cb@9 { 4488 compatible = "qcom,fastrpc-compute-cb"; 4489 reg = <9>; 4490 iommus = <&apps_smmu 0x318b 0x0420>; 4491 }; 4492 4493 compute-cb@10 { 4494 compatible = "qcom,fastrpc-compute-cb"; 4495 reg = <10>; 4496 iommus = <&apps_smmu 0x318b 0x0420>; 4497 }; 4498 4499 compute-cb@11 { 4500 compatible = "qcom,fastrpc-compute-cb"; 4501 reg = <11>; 4502 iommus = <&apps_smmu 0x318c 0x0420>; 4503 }; 4504 4505 compute-cb@12 { 4506 compatible = "qcom,fastrpc-compute-cb"; 4507 reg = <12>; 4508 iommus = <&apps_smmu 0x318d 0x0420>; 4509 }; 4510 4511 compute-cb@13 { 4512 compatible = "qcom,fastrpc-compute-cb"; 4513 reg = <13>; 4514 iommus = <&apps_smmu 0x318e 0x0420>; 4515 }; 4516 4517 compute-cb@14 { 4518 compatible = "qcom,fastrpc-compute-cb"; 4519 reg = <14>; 4520 iommus = <&apps_smmu 0x318f 0x0420>; 4521 }; 4522 }; 4523 }; 4524 }; 4525 4526 remoteproc_nsp1: remoteproc@21300000 { 4527 compatible = "qcom,sc8280xp-nsp1-pas"; 4528 reg = <0 0x21300000 0 0x100>; 4529 4530 interrupts-extended = <&intc GIC_SPI 887 IRQ_TYPE_LEVEL_HIGH>, 4531 <&smp2p_nsp1_in 0 IRQ_TYPE_EDGE_RISING>, 4532 <&smp2p_nsp1_in 1 IRQ_TYPE_EDGE_RISING>, 4533 <&smp2p_nsp1_in 2 IRQ_TYPE_EDGE_RISING>, 4534 <&smp2p_nsp1_in 3 IRQ_TYPE_EDGE_RISING>; 4535 interrupt-names = "wdog", "fatal", "ready", 4536 "handover", "stop-ack"; 4537 4538 clocks = <&rpmhcc RPMH_CXO_CLK>; 4539 clock-names = "xo"; 4540 4541 power-domains = <&rpmhpd SC8280XP_NSP>; 4542 power-domain-names = "nsp"; 4543 4544 memory-region = <&pil_nsp1_mem>; 4545 4546 qcom,smem-states = <&smp2p_nsp1_out 0>; 4547 qcom,smem-state-names = "stop"; 4548 4549 interconnects = <&nspb_noc MASTER_CDSP_PROC_B 0 &mc_virt SLAVE_EBI1 0>; 4550 4551 status = "disabled"; 4552 4553 glink-edge { 4554 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1 4555 IPCC_MPROC_SIGNAL_GLINK_QMP 4556 IRQ_TYPE_EDGE_RISING>; 4557 mboxes = <&ipcc IPCC_CLIENT_NSP1 4558 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4559 4560 label = "nsp1"; 4561 qcom,remote-pid = <12>; 4562 }; 4563 }; 4564 4565 mdss1: display-subsystem@22000000 { 4566 compatible = "qcom,sc8280xp-mdss"; 4567 reg = <0 0x22000000 0 0x1000>; 4568 reg-names = "mdss"; 4569 4570 clocks = <&gcc GCC_DISP_AHB_CLK>, 4571 <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 4572 <&dispcc1 DISP_CC_MDSS_MDP_CLK>; 4573 clock-names = "iface", 4574 "ahb", 4575 "core"; 4576 interconnects = <&mmss_noc MASTER_MDP_CORE1_0 0 &mc_virt SLAVE_EBI1 0>, 4577 <&mmss_noc MASTER_MDP_CORE1_1 0 &mc_virt SLAVE_EBI1 0>; 4578 interconnect-names = "mdp0-mem", "mdp1-mem"; 4579 interrupts = <GIC_SPI 865 IRQ_TYPE_LEVEL_HIGH>; 4580 4581 iommus = <&apps_smmu 0x1800 0x402>; 4582 power-domains = <&dispcc1 MDSS_GDSC>; 4583 resets = <&dispcc1 DISP_CC_MDSS_CORE_BCR>; 4584 4585 interrupt-controller; 4586 #interrupt-cells = <1>; 4587 #address-cells = <2>; 4588 #size-cells = <2>; 4589 ranges; 4590 4591 status = "disabled"; 4592 4593 mdss1_mdp: display-controller@22001000 { 4594 compatible = "qcom,sc8280xp-dpu"; 4595 reg = <0 0x22001000 0 0x8f000>, 4596 <0 0x220b0000 0 0x2008>; 4597 reg-names = "mdp", "vbif"; 4598 4599 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 4600 <&gcc GCC_DISP_SF_AXI_CLK>, 4601 <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 4602 <&dispcc1 DISP_CC_MDSS_MDP_LUT_CLK>, 4603 <&dispcc1 DISP_CC_MDSS_MDP_CLK>, 4604 <&dispcc1 DISP_CC_MDSS_VSYNC_CLK>; 4605 clock-names = "bus", 4606 "nrt_bus", 4607 "iface", 4608 "lut", 4609 "core", 4610 "vsync"; 4611 interrupt-parent = <&mdss1>; 4612 interrupts = <0>; 4613 power-domains = <&rpmhpd SC8280XP_MMCX>; 4614 4615 assigned-clocks = <&dispcc1 DISP_CC_MDSS_VSYNC_CLK>; 4616 assigned-clock-rates = <19200000>; 4617 operating-points-v2 = <&mdss1_mdp_opp_table>; 4618 4619 ports { 4620 #address-cells = <1>; 4621 #size-cells = <0>; 4622 4623 port@0 { 4624 reg = <0>; 4625 mdss1_intf0_out: endpoint { 4626 remote-endpoint = <&mdss1_dp0_in>; 4627 }; 4628 }; 4629 4630 port@4 { 4631 reg = <4>; 4632 mdss1_intf4_out: endpoint { 4633 remote-endpoint = <&mdss1_dp1_in>; 4634 }; 4635 }; 4636 4637 port@5 { 4638 reg = <5>; 4639 mdss1_intf5_out: endpoint { 4640 remote-endpoint = <&mdss1_dp3_in>; 4641 }; 4642 }; 4643 4644 port@6 { 4645 reg = <6>; 4646 mdss1_intf6_out: endpoint { 4647 remote-endpoint = <&mdss1_dp2_in>; 4648 }; 4649 }; 4650 }; 4651 4652 mdss1_mdp_opp_table: opp-table { 4653 compatible = "operating-points-v2"; 4654 4655 opp-200000000 { 4656 opp-hz = /bits/ 64 <200000000>; 4657 required-opps = <&rpmhpd_opp_low_svs>; 4658 }; 4659 4660 opp-300000000 { 4661 opp-hz = /bits/ 64 <300000000>; 4662 required-opps = <&rpmhpd_opp_svs>; 4663 }; 4664 4665 opp-375000000 { 4666 opp-hz = /bits/ 64 <375000000>; 4667 required-opps = <&rpmhpd_opp_svs_l1>; 4668 }; 4669 4670 opp-500000000 { 4671 opp-hz = /bits/ 64 <500000000>; 4672 required-opps = <&rpmhpd_opp_nom>; 4673 }; 4674 opp-600000000 { 4675 opp-hz = /bits/ 64 <600000000>; 4676 required-opps = <&rpmhpd_opp_turbo_l1>; 4677 }; 4678 }; 4679 }; 4680 4681 mdss1_dp0: displayport-controller@22090000 { 4682 compatible = "qcom,sc8280xp-dp"; 4683 reg = <0 0x22090000 0 0x200>, 4684 <0 0x22090200 0 0x200>, 4685 <0 0x22090400 0 0x600>, 4686 <0 0x22091000 0 0x400>, 4687 <0 0x22091400 0 0x400>; 4688 4689 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 4690 <&dispcc1 DISP_CC_MDSS_DPTX0_AUX_CLK>, 4691 <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_CLK>, 4692 <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 4693 <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; 4694 clock-names = "core_iface", "core_aux", 4695 "ctrl_link", 4696 "ctrl_link_iface", "stream_pixel"; 4697 interrupt-parent = <&mdss1>; 4698 interrupts = <12>; 4699 phys = <&mdss1_dp0_phy>; 4700 phy-names = "dp"; 4701 power-domains = <&rpmhpd SC8280XP_MMCX>; 4702 4703 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 4704 <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; 4705 assigned-clock-parents = <&mdss1_dp0_phy 0>, <&mdss1_dp0_phy 1>; 4706 operating-points-v2 = <&mdss1_dp0_opp_table>; 4707 4708 #sound-dai-cells = <0>; 4709 4710 status = "disabled"; 4711 4712 ports { 4713 #address-cells = <1>; 4714 #size-cells = <0>; 4715 4716 port@0 { 4717 reg = <0>; 4718 mdss1_dp0_in: endpoint { 4719 remote-endpoint = <&mdss1_intf0_out>; 4720 }; 4721 }; 4722 4723 port@1 { 4724 reg = <1>; 4725 }; 4726 }; 4727 4728 mdss1_dp0_opp_table: opp-table { 4729 compatible = "operating-points-v2"; 4730 4731 opp-160000000 { 4732 opp-hz = /bits/ 64 <160000000>; 4733 required-opps = <&rpmhpd_opp_low_svs>; 4734 }; 4735 4736 opp-270000000 { 4737 opp-hz = /bits/ 64 <270000000>; 4738 required-opps = <&rpmhpd_opp_svs>; 4739 }; 4740 4741 opp-540000000 { 4742 opp-hz = /bits/ 64 <540000000>; 4743 required-opps = <&rpmhpd_opp_svs_l1>; 4744 }; 4745 4746 opp-810000000 { 4747 opp-hz = /bits/ 64 <810000000>; 4748 required-opps = <&rpmhpd_opp_nom>; 4749 }; 4750 }; 4751 }; 4752 4753 mdss1_dp1: displayport-controller@22098000 { 4754 compatible = "qcom,sc8280xp-dp"; 4755 reg = <0 0x22098000 0 0x200>, 4756 <0 0x22098200 0 0x200>, 4757 <0 0x22098400 0 0x600>, 4758 <0 0x22099000 0 0x400>, 4759 <0 0x22099400 0 0x400>; 4760 4761 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 4762 <&dispcc1 DISP_CC_MDSS_DPTX1_AUX_CLK>, 4763 <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_CLK>, 4764 <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, 4765 <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>; 4766 clock-names = "core_iface", "core_aux", 4767 "ctrl_link", 4768 "ctrl_link_iface", "stream_pixel"; 4769 interrupt-parent = <&mdss1>; 4770 interrupts = <13>; 4771 phys = <&mdss1_dp1_phy>; 4772 phy-names = "dp"; 4773 power-domains = <&rpmhpd SC8280XP_MMCX>; 4774 4775 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, 4776 <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>; 4777 assigned-clock-parents = <&mdss1_dp1_phy 0>, <&mdss1_dp1_phy 1>; 4778 operating-points-v2 = <&mdss1_dp1_opp_table>; 4779 4780 #sound-dai-cells = <0>; 4781 4782 status = "disabled"; 4783 4784 ports { 4785 #address-cells = <1>; 4786 #size-cells = <0>; 4787 4788 port@0 { 4789 reg = <0>; 4790 mdss1_dp1_in: endpoint { 4791 remote-endpoint = <&mdss1_intf4_out>; 4792 }; 4793 }; 4794 4795 port@1 { 4796 reg = <1>; 4797 }; 4798 }; 4799 4800 mdss1_dp1_opp_table: opp-table { 4801 compatible = "operating-points-v2"; 4802 4803 opp-160000000 { 4804 opp-hz = /bits/ 64 <160000000>; 4805 required-opps = <&rpmhpd_opp_low_svs>; 4806 }; 4807 4808 opp-270000000 { 4809 opp-hz = /bits/ 64 <270000000>; 4810 required-opps = <&rpmhpd_opp_svs>; 4811 }; 4812 4813 opp-540000000 { 4814 opp-hz = /bits/ 64 <540000000>; 4815 required-opps = <&rpmhpd_opp_svs_l1>; 4816 }; 4817 4818 opp-810000000 { 4819 opp-hz = /bits/ 64 <810000000>; 4820 required-opps = <&rpmhpd_opp_nom>; 4821 }; 4822 }; 4823 }; 4824 4825 mdss1_dp2: displayport-controller@2209a000 { 4826 compatible = "qcom,sc8280xp-dp"; 4827 reg = <0 0x2209a000 0 0x200>, 4828 <0 0x2209a200 0 0x200>, 4829 <0 0x2209a400 0 0x600>, 4830 <0 0x2209b000 0 0x400>, 4831 <0 0x2209b400 0 0x400>; 4832 4833 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 4834 <&dispcc1 DISP_CC_MDSS_DPTX2_AUX_CLK>, 4835 <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_CLK>, 4836 <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>, 4837 <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>; 4838 clock-names = "core_iface", "core_aux", 4839 "ctrl_link", 4840 "ctrl_link_iface", "stream_pixel"; 4841 interrupt-parent = <&mdss1>; 4842 interrupts = <14>; 4843 phys = <&mdss1_dp2_phy>; 4844 phy-names = "dp"; 4845 power-domains = <&rpmhpd SC8280XP_MMCX>; 4846 4847 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>, 4848 <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>; 4849 assigned-clock-parents = <&mdss1_dp2_phy 0>, <&mdss1_dp2_phy 1>; 4850 operating-points-v2 = <&mdss1_dp2_opp_table>; 4851 4852 #sound-dai-cells = <0>; 4853 4854 status = "disabled"; 4855 4856 ports { 4857 #address-cells = <1>; 4858 #size-cells = <0>; 4859 4860 port@0 { 4861 reg = <0>; 4862 mdss1_dp2_in: endpoint { 4863 remote-endpoint = <&mdss1_intf6_out>; 4864 }; 4865 }; 4866 4867 port@1 { 4868 reg = <1>; 4869 }; 4870 }; 4871 4872 mdss1_dp2_opp_table: opp-table { 4873 compatible = "operating-points-v2"; 4874 4875 opp-160000000 { 4876 opp-hz = /bits/ 64 <160000000>; 4877 required-opps = <&rpmhpd_opp_low_svs>; 4878 }; 4879 4880 opp-270000000 { 4881 opp-hz = /bits/ 64 <270000000>; 4882 required-opps = <&rpmhpd_opp_svs>; 4883 }; 4884 4885 opp-540000000 { 4886 opp-hz = /bits/ 64 <540000000>; 4887 required-opps = <&rpmhpd_opp_svs_l1>; 4888 }; 4889 4890 opp-810000000 { 4891 opp-hz = /bits/ 64 <810000000>; 4892 required-opps = <&rpmhpd_opp_nom>; 4893 }; 4894 }; 4895 }; 4896 4897 mdss1_dp3: displayport-controller@220a0000 { 4898 compatible = "qcom,sc8280xp-dp"; 4899 reg = <0 0x220a0000 0 0x200>, 4900 <0 0x220a0200 0 0x200>, 4901 <0 0x220a0400 0 0x600>, 4902 <0 0x220a1000 0 0x400>, 4903 <0 0x220a1400 0 0x400>; 4904 4905 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 4906 <&dispcc1 DISP_CC_MDSS_DPTX3_AUX_CLK>, 4907 <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_CLK>, 4908 <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>, 4909 <&dispcc1 DISP_CC_MDSS_DPTX3_PIXEL0_CLK>; 4910 clock-names = "core_iface", "core_aux", 4911 "ctrl_link", 4912 "ctrl_link_iface", "stream_pixel"; 4913 interrupt-parent = <&mdss1>; 4914 interrupts = <15>; 4915 phys = <&mdss1_dp3_phy>; 4916 phy-names = "dp"; 4917 power-domains = <&rpmhpd SC8280XP_MMCX>; 4918 4919 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>, 4920 <&dispcc1 DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>; 4921 assigned-clock-parents = <&mdss1_dp3_phy 0>, <&mdss1_dp3_phy 1>; 4922 operating-points-v2 = <&mdss1_dp3_opp_table>; 4923 4924 #sound-dai-cells = <0>; 4925 4926 status = "disabled"; 4927 4928 ports { 4929 #address-cells = <1>; 4930 #size-cells = <0>; 4931 4932 port@0 { 4933 reg = <0>; 4934 mdss1_dp3_in: endpoint { 4935 remote-endpoint = <&mdss1_intf5_out>; 4936 }; 4937 }; 4938 4939 port@1 { 4940 reg = <1>; 4941 }; 4942 }; 4943 4944 mdss1_dp3_opp_table: opp-table { 4945 compatible = "operating-points-v2"; 4946 4947 opp-160000000 { 4948 opp-hz = /bits/ 64 <160000000>; 4949 required-opps = <&rpmhpd_opp_low_svs>; 4950 }; 4951 4952 opp-270000000 { 4953 opp-hz = /bits/ 64 <270000000>; 4954 required-opps = <&rpmhpd_opp_svs>; 4955 }; 4956 4957 opp-540000000 { 4958 opp-hz = /bits/ 64 <540000000>; 4959 required-opps = <&rpmhpd_opp_svs_l1>; 4960 }; 4961 4962 opp-810000000 { 4963 opp-hz = /bits/ 64 <810000000>; 4964 required-opps = <&rpmhpd_opp_nom>; 4965 }; 4966 }; 4967 }; 4968 }; 4969 4970 mdss1_dp2_phy: phy@220c2a00 { 4971 compatible = "qcom,sc8280xp-dp-phy"; 4972 reg = <0 0x220c2a00 0 0x19c>, 4973 <0 0x220c2200 0 0xec>, 4974 <0 0x220c2600 0 0xec>, 4975 <0 0x220c2000 0 0x1c8>; 4976 4977 clocks = <&dispcc1 DISP_CC_MDSS_DPTX2_AUX_CLK>, 4978 <&dispcc1 DISP_CC_MDSS_AHB_CLK>; 4979 clock-names = "aux", "cfg_ahb"; 4980 power-domains = <&rpmhpd SC8280XP_MX>; 4981 4982 #clock-cells = <1>; 4983 #phy-cells = <0>; 4984 4985 status = "disabled"; 4986 }; 4987 4988 mdss1_dp3_phy: phy@220c5a00 { 4989 compatible = "qcom,sc8280xp-dp-phy"; 4990 reg = <0 0x220c5a00 0 0x19c>, 4991 <0 0x220c5200 0 0xec>, 4992 <0 0x220c5600 0 0xec>, 4993 <0 0x220c5000 0 0x1c8>; 4994 4995 clocks = <&dispcc1 DISP_CC_MDSS_DPTX3_AUX_CLK>, 4996 <&dispcc1 DISP_CC_MDSS_AHB_CLK>; 4997 clock-names = "aux", "cfg_ahb"; 4998 power-domains = <&rpmhpd SC8280XP_MX>; 4999 5000 #clock-cells = <1>; 5001 #phy-cells = <0>; 5002 5003 status = "disabled"; 5004 }; 5005 5006 dispcc1: clock-controller@22100000 { 5007 compatible = "qcom,sc8280xp-dispcc1"; 5008 reg = <0 0x22100000 0 0x20000>; 5009 5010 clocks = <&gcc GCC_DISP_AHB_CLK>, 5011 <&rpmhcc RPMH_CXO_CLK>, 5012 <0>, 5013 <&mdss1_dp0_phy 0>, 5014 <&mdss1_dp0_phy 1>, 5015 <&mdss1_dp1_phy 0>, 5016 <&mdss1_dp1_phy 1>, 5017 <&mdss1_dp2_phy 0>, 5018 <&mdss1_dp2_phy 1>, 5019 <&mdss1_dp3_phy 0>, 5020 <&mdss1_dp3_phy 1>, 5021 <0>, 5022 <0>, 5023 <0>, 5024 <0>; 5025 power-domains = <&rpmhpd SC8280XP_MMCX>; 5026 5027 #clock-cells = <1>; 5028 #power-domain-cells = <1>; 5029 #reset-cells = <1>; 5030 5031 status = "disabled"; 5032 }; 5033 5034 ethernet1: ethernet@23000000 { 5035 compatible = "qcom,sc8280xp-ethqos"; 5036 reg = <0x0 0x23000000 0x0 0x10000>, 5037 <0x0 0x23016000 0x0 0x100>; 5038 reg-names = "stmmaceth", "rgmii"; 5039 5040 clocks = <&gcc GCC_EMAC1_AXI_CLK>, 5041 <&gcc GCC_EMAC1_SLV_AHB_CLK>, 5042 <&gcc GCC_EMAC1_PTP_CLK>, 5043 <&gcc GCC_EMAC1_RGMII_CLK>; 5044 clock-names = "stmmaceth", 5045 "pclk", 5046 "ptp_ref", 5047 "rgmii"; 5048 5049 interrupts = <GIC_SPI 929 IRQ_TYPE_LEVEL_HIGH>, 5050 <GIC_SPI 919 IRQ_TYPE_LEVEL_HIGH>; 5051 interrupt-names = "macirq", "eth_lpi"; 5052 5053 iommus = <&apps_smmu 0x40 0xf>; 5054 power-domains = <&gcc EMAC_1_GDSC>; 5055 5056 snps,tso; 5057 snps,pbl = <32>; 5058 rx-fifo-depth = <4096>; 5059 tx-fifo-depth = <4096>; 5060 5061 status = "disabled"; 5062 }; 5063 }; 5064 5065 sound: sound { 5066 }; 5067 5068 thermal-zones { 5069 cpu0-thermal { 5070 polling-delay-passive = <250>; 5071 polling-delay = <1000>; 5072 5073 thermal-sensors = <&tsens0 1>; 5074 5075 trips { 5076 cpu-crit { 5077 temperature = <110000>; 5078 hysteresis = <1000>; 5079 type = "critical"; 5080 }; 5081 }; 5082 }; 5083 5084 cpu1-thermal { 5085 polling-delay-passive = <250>; 5086 polling-delay = <1000>; 5087 5088 thermal-sensors = <&tsens0 2>; 5089 5090 trips { 5091 cpu-crit { 5092 temperature = <110000>; 5093 hysteresis = <1000>; 5094 type = "critical"; 5095 }; 5096 }; 5097 }; 5098 5099 cpu2-thermal { 5100 polling-delay-passive = <250>; 5101 polling-delay = <1000>; 5102 5103 thermal-sensors = <&tsens0 3>; 5104 5105 trips { 5106 cpu-crit { 5107 temperature = <110000>; 5108 hysteresis = <1000>; 5109 type = "critical"; 5110 }; 5111 }; 5112 }; 5113 5114 cpu3-thermal { 5115 polling-delay-passive = <250>; 5116 polling-delay = <1000>; 5117 5118 thermal-sensors = <&tsens0 4>; 5119 5120 trips { 5121 cpu-crit { 5122 temperature = <110000>; 5123 hysteresis = <1000>; 5124 type = "critical"; 5125 }; 5126 }; 5127 }; 5128 5129 cpu4-thermal { 5130 polling-delay-passive = <250>; 5131 polling-delay = <1000>; 5132 5133 thermal-sensors = <&tsens0 5>; 5134 5135 trips { 5136 cpu-crit { 5137 temperature = <110000>; 5138 hysteresis = <1000>; 5139 type = "critical"; 5140 }; 5141 }; 5142 }; 5143 5144 cpu5-thermal { 5145 polling-delay-passive = <250>; 5146 polling-delay = <1000>; 5147 5148 thermal-sensors = <&tsens0 6>; 5149 5150 trips { 5151 cpu-crit { 5152 temperature = <110000>; 5153 hysteresis = <1000>; 5154 type = "critical"; 5155 }; 5156 }; 5157 }; 5158 5159 cpu6-thermal { 5160 polling-delay-passive = <250>; 5161 polling-delay = <1000>; 5162 5163 thermal-sensors = <&tsens0 7>; 5164 5165 trips { 5166 cpu-crit { 5167 temperature = <110000>; 5168 hysteresis = <1000>; 5169 type = "critical"; 5170 }; 5171 }; 5172 }; 5173 5174 cpu7-thermal { 5175 polling-delay-passive = <250>; 5176 polling-delay = <1000>; 5177 5178 thermal-sensors = <&tsens0 8>; 5179 5180 trips { 5181 cpu-crit { 5182 temperature = <110000>; 5183 hysteresis = <1000>; 5184 type = "critical"; 5185 }; 5186 }; 5187 }; 5188 5189 cluster0-thermal { 5190 polling-delay-passive = <250>; 5191 polling-delay = <1000>; 5192 5193 thermal-sensors = <&tsens0 9>; 5194 5195 trips { 5196 cpu-crit { 5197 temperature = <110000>; 5198 hysteresis = <1000>; 5199 type = "critical"; 5200 }; 5201 }; 5202 }; 5203 5204 mem-thermal { 5205 polling-delay-passive = <250>; 5206 polling-delay = <1000>; 5207 5208 thermal-sensors = <&tsens1 15>; 5209 5210 trips { 5211 trip-point0 { 5212 temperature = <90000>; 5213 hysteresis = <2000>; 5214 type = "hot"; 5215 }; 5216 }; 5217 }; 5218 }; 5219 5220 timer { 5221 compatible = "arm,armv8-timer"; 5222 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5223 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5224 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5225 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 5226 }; 5227}; 5228