1// SPDX-License-Identifier: BSD-3-Clause
2/*
3 * Copyright (c) 2021, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2022, Linaro Limited
5 */
6
7#include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
8#include <dt-bindings/clock/qcom,rpmh.h>
9#include <dt-bindings/interconnect/qcom,osm-l3.h>
10#include <dt-bindings/interconnect/qcom,sc8280xp.h>
11#include <dt-bindings/interrupt-controller/arm-gic.h>
12#include <dt-bindings/mailbox/qcom-ipcc.h>
13#include <dt-bindings/power/qcom-rpmpd.h>
14#include <dt-bindings/soc/qcom,rpmh-rsc.h>
15#include <dt-bindings/thermal/thermal.h>
16
17/ {
18	interrupt-parent = <&intc>;
19
20	#address-cells = <2>;
21	#size-cells = <2>;
22
23	clocks {
24		xo_board_clk: xo-board-clk {
25			compatible = "fixed-clock";
26			#clock-cells = <0>;
27		};
28
29		sleep_clk: sleep-clk {
30			compatible = "fixed-clock";
31			#clock-cells = <0>;
32			clock-frequency = <32764>;
33		};
34	};
35
36	cpu0_opp_table: cpu0-opp-table {
37		compatible = "operating-points-v2";
38		opp-shared;
39
40		opp-300000000 {
41			opp-hz = /bits/ 64 <300000000>;
42			opp-peak-kBps = <(300000 * 32)>;
43		};
44		opp-403200000 {
45			opp-hz = /bits/ 64 <403200000>;
46			opp-peak-kBps = <(384000 * 32)>;
47		};
48		opp-499200000 {
49			opp-hz = /bits/ 64 <499200000>;
50			opp-peak-kBps = <(480000 * 32)>;
51		};
52		opp-595200000 {
53			opp-hz = /bits/ 64 <595200000>;
54			opp-peak-kBps = <(576000 * 32)>;
55		};
56		opp-691200000 {
57			opp-hz = /bits/ 64 <691200000>;
58			opp-peak-kBps = <(672000 * 32)>;
59		};
60		opp-806400000 {
61			opp-hz = /bits/ 64 <806400000>;
62			opp-peak-kBps = <(768000 * 32)>;
63		};
64		opp-902400000 {
65			opp-hz = /bits/ 64 <902400000>;
66			opp-peak-kBps = <(864000 * 32)>;
67		};
68		opp-1017600000 {
69			opp-hz = /bits/ 64 <1017600000>;
70			opp-peak-kBps = <(960000 * 32)>;
71		};
72		opp-1113600000 {
73			opp-hz = /bits/ 64 <1113600000>;
74			opp-peak-kBps = <(1075200 * 32)>;
75		};
76		opp-1209600000 {
77			opp-hz = /bits/ 64 <1209600000>;
78			opp-peak-kBps = <(1171200 * 32)>;
79		};
80		opp-1324800000 {
81			opp-hz = /bits/ 64 <1324800000>;
82			opp-peak-kBps = <(1267200 * 32)>;
83		};
84		opp-1440000000 {
85			opp-hz = /bits/ 64 <1440000000>;
86			opp-peak-kBps = <(1363200 * 32)>;
87		};
88		opp-1555200000 {
89			opp-hz = /bits/ 64 <1555200000>;
90			opp-peak-kBps = <(1536000 * 32)>;
91		};
92		opp-1670400000 {
93			opp-hz = /bits/ 64 <1670400000>;
94			opp-peak-kBps = <(1612800 * 32)>;
95		};
96		opp-1785600000 {
97			opp-hz = /bits/ 64 <1785600000>;
98			opp-peak-kBps = <(1689600 * 32)>;
99		};
100		opp-1881600000 {
101			opp-hz = /bits/ 64 <1881600000>;
102			opp-peak-kBps = <(1689600 * 32)>;
103		};
104		opp-1996800000 {
105			opp-hz = /bits/ 64 <1996800000>;
106			opp-peak-kBps = <(1689600 * 32)>;
107		};
108		opp-2112000000 {
109			opp-hz = /bits/ 64 <2112000000>;
110			opp-peak-kBps = <(1689600 * 32)>;
111		};
112		opp-2227200000 {
113			opp-hz = /bits/ 64 <2227200000>;
114			opp-peak-kBps = <(1689600 * 32)>;
115		};
116		opp-2342400000 {
117			opp-hz = /bits/ 64 <2342400000>;
118			opp-peak-kBps = <(1689600 * 32)>;
119		};
120		opp-2438400000 {
121			opp-hz = /bits/ 64 <2438400000>;
122			opp-peak-kBps = <(1689600 * 32)>;
123		};
124	};
125
126	cpu4_opp_table: cpu4-opp-table {
127		compatible = "operating-points-v2";
128		opp-shared;
129
130		opp-825600000 {
131			opp-hz = /bits/ 64 <825600000>;
132			opp-peak-kBps = <(768000 * 32)>;
133		};
134		opp-940800000 {
135			opp-hz = /bits/ 64 <940800000>;
136			opp-peak-kBps = <(864000 * 32)>;
137		};
138		opp-1056000000 {
139			opp-hz = /bits/ 64 <1056000000>;
140			opp-peak-kBps = <(960000 * 32)>;
141		};
142		opp-1171200000 {
143			opp-hz = /bits/ 64 <1171200000>;
144			opp-peak-kBps = <(1171200 * 32)>;
145		};
146		opp-1286400000 {
147			opp-hz = /bits/ 64 <1286400000>;
148			opp-peak-kBps = <(1267200 * 32)>;
149		};
150		opp-1401600000 {
151			opp-hz = /bits/ 64 <1401600000>;
152			opp-peak-kBps = <(1363200 * 32)>;
153		};
154		opp-1516800000 {
155			opp-hz = /bits/ 64 <1516800000>;
156			opp-peak-kBps = <(1459200 * 32)>;
157		};
158		opp-1632000000 {
159			opp-hz = /bits/ 64 <1632000000>;
160			opp-peak-kBps = <(1612800 * 32)>;
161		};
162		opp-1747200000 {
163			opp-hz = /bits/ 64 <1747200000>;
164			opp-peak-kBps = <(1689600 * 32)>;
165		};
166		opp-1862400000 {
167			opp-hz = /bits/ 64 <1862400000>;
168			opp-peak-kBps = <(1689600 * 32)>;
169		};
170		opp-1977600000 {
171			opp-hz = /bits/ 64 <1977600000>;
172			opp-peak-kBps = <(1689600 * 32)>;
173		};
174		opp-2073600000 {
175			opp-hz = /bits/ 64 <2073600000>;
176			opp-peak-kBps = <(1689600 * 32)>;
177		};
178		opp-2169600000 {
179			opp-hz = /bits/ 64 <2169600000>;
180			opp-peak-kBps = <(1689600 * 32)>;
181		};
182		opp-2284800000 {
183			opp-hz = /bits/ 64 <2284800000>;
184			opp-peak-kBps = <(1689600 * 32)>;
185		};
186		opp-2400000000 {
187			opp-hz = /bits/ 64 <2400000000>;
188			opp-peak-kBps = <(1689600 * 32)>;
189		};
190		opp-2496000000 {
191			opp-hz = /bits/ 64 <2496000000>;
192			opp-peak-kBps = <(1689600 * 32)>;
193		};
194		opp-2592000000 {
195			opp-hz = /bits/ 64 <2592000000>;
196			opp-peak-kBps = <(1689600 * 32)>;
197		};
198		opp-2688000000 {
199			opp-hz = /bits/ 64 <2688000000>;
200			opp-peak-kBps = <(1689600 * 32)>;
201		};
202		opp-2803200000 {
203			opp-hz = /bits/ 64 <2803200000>;
204			opp-peak-kBps = <(1689600 * 32)>;
205		};
206		opp-2899200000 {
207			opp-hz = /bits/ 64 <2899200000>;
208			opp-peak-kBps = <(1689600 * 32)>;
209		};
210		opp-2995200000 {
211			opp-hz = /bits/ 64 <2995200000>;
212			opp-peak-kBps = <(1689600 * 32)>;
213		};
214	};
215
216	cpus {
217		#address-cells = <2>;
218		#size-cells = <0>;
219
220		CPU0: cpu@0 {
221			device_type = "cpu";
222			compatible = "qcom,kryo";
223			reg = <0x0 0x0>;
224			enable-method = "psci";
225			capacity-dmips-mhz = <602>;
226			next-level-cache = <&L2_0>;
227			power-domains = <&CPU_PD0>;
228			power-domain-names = "psci";
229			qcom,freq-domain = <&cpufreq_hw 0>;
230			operating-points-v2 = <&cpu0_opp_table>;
231			interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
232			#cooling-cells = <2>;
233			L2_0: l2-cache {
234				compatible = "cache";
235				next-level-cache = <&L3_0>;
236				L3_0: l3-cache {
237				      compatible = "cache";
238				};
239			};
240		};
241
242		CPU1: cpu@100 {
243			device_type = "cpu";
244			compatible = "qcom,kryo";
245			reg = <0x0 0x100>;
246			enable-method = "psci";
247			capacity-dmips-mhz = <602>;
248			next-level-cache = <&L2_100>;
249			power-domains = <&CPU_PD1>;
250			power-domain-names = "psci";
251			qcom,freq-domain = <&cpufreq_hw 0>;
252			operating-points-v2 = <&cpu0_opp_table>;
253			interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
254			#cooling-cells = <2>;
255			L2_100: l2-cache {
256				compatible = "cache";
257				next-level-cache = <&L3_0>;
258			};
259		};
260
261		CPU2: cpu@200 {
262			device_type = "cpu";
263			compatible = "qcom,kryo";
264			reg = <0x0 0x200>;
265			enable-method = "psci";
266			capacity-dmips-mhz = <602>;
267			next-level-cache = <&L2_200>;
268			power-domains = <&CPU_PD2>;
269			power-domain-names = "psci";
270			qcom,freq-domain = <&cpufreq_hw 0>;
271			operating-points-v2 = <&cpu0_opp_table>;
272			interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
273			#cooling-cells = <2>;
274			L2_200: l2-cache {
275				compatible = "cache";
276				next-level-cache = <&L3_0>;
277			};
278		};
279
280		CPU3: cpu@300 {
281			device_type = "cpu";
282			compatible = "qcom,kryo";
283			reg = <0x0 0x300>;
284			enable-method = "psci";
285			capacity-dmips-mhz = <602>;
286			next-level-cache = <&L2_300>;
287			power-domains = <&CPU_PD3>;
288			power-domain-names = "psci";
289			qcom,freq-domain = <&cpufreq_hw 0>;
290			operating-points-v2 = <&cpu0_opp_table>;
291			interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
292			#cooling-cells = <2>;
293			L2_300: l2-cache {
294				compatible = "cache";
295				next-level-cache = <&L3_0>;
296			};
297		};
298
299		CPU4: cpu@400 {
300			device_type = "cpu";
301			compatible = "qcom,kryo";
302			reg = <0x0 0x400>;
303			enable-method = "psci";
304			capacity-dmips-mhz = <1024>;
305			next-level-cache = <&L2_400>;
306			power-domains = <&CPU_PD4>;
307			power-domain-names = "psci";
308			qcom,freq-domain = <&cpufreq_hw 1>;
309			operating-points-v2 = <&cpu4_opp_table>;
310			interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
311			#cooling-cells = <2>;
312			L2_400: l2-cache {
313				compatible = "cache";
314				next-level-cache = <&L3_0>;
315			};
316		};
317
318		CPU5: cpu@500 {
319			device_type = "cpu";
320			compatible = "qcom,kryo";
321			reg = <0x0 0x500>;
322			enable-method = "psci";
323			capacity-dmips-mhz = <1024>;
324			next-level-cache = <&L2_500>;
325			power-domains = <&CPU_PD5>;
326			power-domain-names = "psci";
327			qcom,freq-domain = <&cpufreq_hw 1>;
328			operating-points-v2 = <&cpu4_opp_table>;
329			interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
330			#cooling-cells = <2>;
331			L2_500: l2-cache {
332				compatible = "cache";
333				next-level-cache = <&L3_0>;
334			};
335		};
336
337		CPU6: cpu@600 {
338			device_type = "cpu";
339			compatible = "qcom,kryo";
340			reg = <0x0 0x600>;
341			enable-method = "psci";
342			capacity-dmips-mhz = <1024>;
343			next-level-cache = <&L2_600>;
344			power-domains = <&CPU_PD6>;
345			power-domain-names = "psci";
346			qcom,freq-domain = <&cpufreq_hw 1>;
347			operating-points-v2 = <&cpu4_opp_table>;
348			interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
349			#cooling-cells = <2>;
350			L2_600: l2-cache {
351				compatible = "cache";
352				next-level-cache = <&L3_0>;
353			};
354		};
355
356		CPU7: cpu@700 {
357			device_type = "cpu";
358			compatible = "qcom,kryo";
359			reg = <0x0 0x700>;
360			enable-method = "psci";
361			capacity-dmips-mhz = <1024>;
362			next-level-cache = <&L2_700>;
363			power-domains = <&CPU_PD7>;
364			power-domain-names = "psci";
365			qcom,freq-domain = <&cpufreq_hw 1>;
366			operating-points-v2 = <&cpu4_opp_table>;
367			interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
368			#cooling-cells = <2>;
369			L2_700: l2-cache {
370				compatible = "cache";
371				next-level-cache = <&L3_0>;
372			};
373		};
374
375		cpu-map {
376			cluster0 {
377				core0 {
378					cpu = <&CPU0>;
379				};
380
381				core1 {
382					cpu = <&CPU1>;
383				};
384
385				core2 {
386					cpu = <&CPU2>;
387				};
388
389				core3 {
390					cpu = <&CPU3>;
391				};
392
393				core4 {
394					cpu = <&CPU4>;
395				};
396
397				core5 {
398					cpu = <&CPU5>;
399				};
400
401				core6 {
402					cpu = <&CPU6>;
403				};
404
405				core7 {
406					cpu = <&CPU7>;
407				};
408			};
409		};
410
411		idle-states {
412			entry-method = "psci";
413
414			LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
415				compatible = "arm,idle-state";
416				idle-state-name = "little-rail-power-collapse";
417				arm,psci-suspend-param = <0x40000004>;
418				entry-latency-us = <355>;
419				exit-latency-us = <909>;
420				min-residency-us = <3934>;
421				local-timer-stop;
422			};
423
424			BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
425				compatible = "arm,idle-state";
426				idle-state-name = "big-rail-power-collapse";
427				arm,psci-suspend-param = <0x40000004>;
428				entry-latency-us = <241>;
429				exit-latency-us = <1461>;
430				min-residency-us = <4488>;
431				local-timer-stop;
432			};
433		};
434
435		domain-idle-states {
436			CLUSTER_SLEEP_0: cluster-sleep-0 {
437				compatible = "domain-idle-state";
438				idle-state-name = "cluster-power-collapse";
439				arm,psci-suspend-param = <0x4100c344>;
440				entry-latency-us = <3263>;
441				exit-latency-us = <6562>;
442				min-residency-us = <9987>;
443			};
444		};
445	};
446
447	firmware {
448		scm: scm {
449			compatible = "qcom,scm-sc8280xp", "qcom,scm";
450		};
451	};
452
453	aggre1_noc: interconnect-aggre1-noc {
454		compatible = "qcom,sc8280xp-aggre1-noc";
455		#interconnect-cells = <2>;
456		qcom,bcm-voters = <&apps_bcm_voter>;
457	};
458
459	aggre2_noc: interconnect-aggre2-noc {
460		compatible = "qcom,sc8280xp-aggre2-noc";
461		#interconnect-cells = <2>;
462		qcom,bcm-voters = <&apps_bcm_voter>;
463	};
464
465	clk_virt: interconnect-clk-virt {
466		compatible = "qcom,sc8280xp-clk-virt";
467		#interconnect-cells = <2>;
468		qcom,bcm-voters = <&apps_bcm_voter>;
469	};
470
471	config_noc: interconnect-config-noc {
472		compatible = "qcom,sc8280xp-config-noc";
473		#interconnect-cells = <2>;
474		qcom,bcm-voters = <&apps_bcm_voter>;
475	};
476
477	dc_noc: interconnect-dc-noc {
478		compatible = "qcom,sc8280xp-dc-noc";
479		#interconnect-cells = <2>;
480		qcom,bcm-voters = <&apps_bcm_voter>;
481	};
482
483	gem_noc: interconnect-gem-noc {
484		compatible = "qcom,sc8280xp-gem-noc";
485		#interconnect-cells = <2>;
486		qcom,bcm-voters = <&apps_bcm_voter>;
487	};
488
489	lpass_noc: interconnect-lpass-ag-noc {
490		compatible = "qcom,sc8280xp-lpass-ag-noc";
491		#interconnect-cells = <2>;
492		qcom,bcm-voters = <&apps_bcm_voter>;
493	};
494
495	mc_virt: interconnect-mc-virt {
496		compatible = "qcom,sc8280xp-mc-virt";
497		#interconnect-cells = <2>;
498		qcom,bcm-voters = <&apps_bcm_voter>;
499	};
500
501	mmss_noc: interconnect-mmss-noc {
502		compatible = "qcom,sc8280xp-mmss-noc";
503		#interconnect-cells = <2>;
504		qcom,bcm-voters = <&apps_bcm_voter>;
505	};
506
507	nspa_noc: interconnect-nspa-noc {
508		compatible = "qcom,sc8280xp-nspa-noc";
509		#interconnect-cells = <2>;
510		qcom,bcm-voters = <&apps_bcm_voter>;
511	};
512
513	nspb_noc: interconnect-nspb-noc {
514		compatible = "qcom,sc8280xp-nspb-noc";
515		#interconnect-cells = <2>;
516		qcom,bcm-voters = <&apps_bcm_voter>;
517	};
518
519	system_noc: interconnect-system-noc {
520		compatible = "qcom,sc8280xp-system-noc";
521		#interconnect-cells = <2>;
522		qcom,bcm-voters = <&apps_bcm_voter>;
523	};
524
525	memory@80000000 {
526		device_type = "memory";
527		/* We expect the bootloader to fill in the size */
528		reg = <0x0 0x80000000 0x0 0x0>;
529	};
530
531	pmu {
532		compatible = "arm,armv8-pmuv3";
533		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
534	};
535
536	psci {
537		compatible = "arm,psci-1.0";
538		method = "smc";
539
540		CPU_PD0: cpu0 {
541			#power-domain-cells = <0>;
542			power-domains = <&CLUSTER_PD>;
543			domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
544		};
545
546		CPU_PD1: cpu1 {
547			#power-domain-cells = <0>;
548			power-domains = <&CLUSTER_PD>;
549			domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
550		};
551
552		CPU_PD2: cpu2 {
553			#power-domain-cells = <0>;
554			power-domains = <&CLUSTER_PD>;
555			domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
556		};
557
558		CPU_PD3: cpu3 {
559			#power-domain-cells = <0>;
560			power-domains = <&CLUSTER_PD>;
561			domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
562		};
563
564		CPU_PD4: cpu4 {
565			#power-domain-cells = <0>;
566			power-domains = <&CLUSTER_PD>;
567			domain-idle-states = <&BIG_CPU_SLEEP_0>;
568		};
569
570		CPU_PD5: cpu5 {
571			#power-domain-cells = <0>;
572			power-domains = <&CLUSTER_PD>;
573			domain-idle-states = <&BIG_CPU_SLEEP_0>;
574		};
575
576		CPU_PD6: cpu6 {
577			#power-domain-cells = <0>;
578			power-domains = <&CLUSTER_PD>;
579			domain-idle-states = <&BIG_CPU_SLEEP_0>;
580		};
581
582		CPU_PD7: cpu7 {
583			#power-domain-cells = <0>;
584			power-domains = <&CLUSTER_PD>;
585			domain-idle-states = <&BIG_CPU_SLEEP_0>;
586		};
587
588		CLUSTER_PD: cpu-cluster0 {
589			#power-domain-cells = <0>;
590			domain-idle-states = <&CLUSTER_SLEEP_0>;
591		};
592	};
593
594	qup_opp_table_100mhz: qup-100mhz-opp-table {
595		compatible = "operating-points-v2";
596
597		opp-75000000 {
598			opp-hz = /bits/ 64 <75000000>;
599			required-opps = <&rpmhpd_opp_low_svs>;
600		};
601
602		opp-100000000 {
603			opp-hz = /bits/ 64 <100000000>;
604			required-opps = <&rpmhpd_opp_svs>;
605		};
606	};
607
608	reserved-memory {
609		#address-cells = <2>;
610		#size-cells = <2>;
611		ranges;
612
613		reserved-region@80000000 {
614			reg = <0 0x80000000 0 0x860000>;
615			no-map;
616		};
617
618		cmd_db: cmd-db-region@80860000 {
619			compatible = "qcom,cmd-db";
620			reg = <0 0x80860000 0 0x20000>;
621			no-map;
622		};
623
624		reserved-region@80880000 {
625			reg = <0 0x80880000 0 0x80000>;
626			no-map;
627		};
628
629		smem_mem: smem-region@80900000 {
630			compatible = "qcom,smem";
631			reg = <0 0x80900000 0 0x200000>;
632			no-map;
633			hwlocks = <&tcsr_mutex 3>;
634		};
635
636		reserved-region@80b00000 {
637			reg = <0 0x80b00000 0 0x100000>;
638			no-map;
639		};
640
641		reserved-region@83b00000 {
642			reg = <0 0x83b00000 0 0x1700000>;
643			no-map;
644		};
645
646		reserved-region@85b00000 {
647			reg = <0 0x85b00000 0 0xc00000>;
648			no-map;
649		};
650
651		pil_adsp_mem: adsp-region@86c00000 {
652			reg = <0 0x86c00000 0 0x2000000>;
653			no-map;
654		};
655
656		pil_nsp0_mem: cdsp0-region@8a100000 {
657			reg = <0 0x8a100000 0 0x1e00000>;
658			no-map;
659		};
660
661		pil_nsp1_mem: cdsp1-region@8c600000 {
662			reg = <0 0x8c600000 0 0x1e00000>;
663			no-map;
664		};
665
666		reserved-region@aeb00000 {
667			reg = <0 0xaeb00000 0 0x16600000>;
668			no-map;
669		};
670	};
671
672	smp2p-adsp {
673		compatible = "qcom,smp2p";
674		qcom,smem = <443>, <429>;
675		interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
676					     IPCC_MPROC_SIGNAL_SMP2P
677					     IRQ_TYPE_EDGE_RISING>;
678		mboxes = <&ipcc IPCC_CLIENT_LPASS
679				IPCC_MPROC_SIGNAL_SMP2P>;
680
681		qcom,local-pid = <0>;
682		qcom,remote-pid = <2>;
683
684		smp2p_adsp_out: master-kernel {
685			qcom,entry-name = "master-kernel";
686			#qcom,smem-state-cells = <1>;
687		};
688
689		smp2p_adsp_in: slave-kernel {
690			qcom,entry-name = "slave-kernel";
691			interrupt-controller;
692			#interrupt-cells = <2>;
693		};
694	};
695
696	smp2p-nsp0 {
697		compatible = "qcom,smp2p";
698		qcom,smem = <94>, <432>;
699		interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
700					     IPCC_MPROC_SIGNAL_SMP2P
701					     IRQ_TYPE_EDGE_RISING>;
702		mboxes = <&ipcc IPCC_CLIENT_CDSP
703				IPCC_MPROC_SIGNAL_SMP2P>;
704
705		qcom,local-pid = <0>;
706		qcom,remote-pid = <5>;
707
708		smp2p_nsp0_out: master-kernel {
709			qcom,entry-name = "master-kernel";
710			#qcom,smem-state-cells = <1>;
711		};
712
713		smp2p_nsp0_in: slave-kernel {
714			qcom,entry-name = "slave-kernel";
715			interrupt-controller;
716			#interrupt-cells = <2>;
717		};
718	};
719
720	smp2p-nsp1 {
721		compatible = "qcom,smp2p";
722		qcom,smem = <617>, <616>;
723		interrupts-extended = <&ipcc IPCC_CLIENT_NSP1
724					     IPCC_MPROC_SIGNAL_SMP2P
725					     IRQ_TYPE_EDGE_RISING>;
726		mboxes = <&ipcc IPCC_CLIENT_NSP1
727				IPCC_MPROC_SIGNAL_SMP2P>;
728
729		qcom,local-pid = <0>;
730		qcom,remote-pid = <12>;
731
732		smp2p_nsp1_out: master-kernel {
733			qcom,entry-name = "master-kernel";
734			#qcom,smem-state-cells = <1>;
735		};
736
737		smp2p_nsp1_in: slave-kernel {
738			qcom,entry-name = "slave-kernel";
739			interrupt-controller;
740			#interrupt-cells = <2>;
741		};
742	};
743
744	soc: soc@0 {
745		compatible = "simple-bus";
746		#address-cells = <2>;
747		#size-cells = <2>;
748		ranges = <0 0 0 0 0x10 0>;
749		dma-ranges = <0 0 0 0 0x10 0>;
750
751		gcc: clock-controller@100000 {
752			compatible = "qcom,gcc-sc8280xp";
753			reg = <0x0 0x00100000 0x0 0x1f0000>;
754			#clock-cells = <1>;
755			#reset-cells = <1>;
756			#power-domain-cells = <1>;
757			clocks = <&rpmhcc RPMH_CXO_CLK>,
758				 <&sleep_clk>,
759				 <0>,
760				 <0>,
761				 <0>,
762				 <0>,
763				 <0>,
764				 <0>,
765				 <&usb_0_ssphy>,
766				 <0>,
767				 <0>,
768				 <0>,
769				 <0>,
770				 <0>,
771				 <0>,
772				 <0>,
773				 <&usb_1_ssphy>,
774				 <0>,
775				 <0>,
776				 <0>,
777				 <0>,
778				 <0>,
779				 <0>,
780				 <0>,
781				 <0>,
782				 <0>,
783				 <&pcie2a_phy>,
784				 <&pcie2b_phy>,
785				 <&pcie3a_phy>,
786				 <&pcie3b_phy>,
787				 <&pcie4_phy>,
788				 <0>,
789				 <0>;
790			power-domains = <&rpmhpd SC8280XP_CX>;
791		};
792
793		ipcc: mailbox@408000 {
794			compatible = "qcom,sc8280xp-ipcc", "qcom,ipcc";
795			reg = <0 0x00408000 0 0x1000>;
796			interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
797			interrupt-controller;
798			#interrupt-cells = <3>;
799			#mbox-cells = <2>;
800		};
801
802		qup2: geniqup@8c0000 {
803			compatible = "qcom,geni-se-qup";
804			reg = <0 0x008c0000 0 0x2000>;
805			clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
806				 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
807			clock-names = "m-ahb", "s-ahb";
808			iommus = <&apps_smmu 0xa3 0>;
809
810			#address-cells = <2>;
811			#size-cells = <2>;
812			ranges;
813
814			status = "disabled";
815
816			qup2_uart17: serial@884000 {
817				compatible = "qcom,geni-uart";
818				reg = <0 0x00884000 0 0x4000>;
819				clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
820				clock-names = "se";
821				interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
822				operating-points-v2 = <&qup_opp_table_100mhz>;
823				power-domains = <&rpmhpd SC8280XP_CX>;
824				interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
825						<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>;
826				interconnect-names = "qup-core", "qup-config";
827				status = "disabled";
828			};
829
830			qup2_i2c5: i2c@894000 {
831				compatible = "qcom,geni-i2c";
832				reg = <0 0x00894000 0 0x4000>;
833				clock-names = "se";
834				clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
835				interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
836				#address-cells = <1>;
837				#size-cells = <0>;
838				power-domains = <&rpmhpd SC8280XP_CX>;
839				interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
840						<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
841						<&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
842				interconnect-names = "qup-core", "qup-config", "qup-memory";
843				status = "disabled";
844			};
845		};
846
847		qup0: geniqup@9c0000 {
848			compatible = "qcom,geni-se-qup";
849			reg = <0 0x009c0000 0 0x6000>;
850			clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
851				 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
852			clock-names = "m-ahb", "s-ahb";
853			iommus = <&apps_smmu 0x563 0>;
854
855			#address-cells = <2>;
856			#size-cells = <2>;
857			ranges;
858
859			status = "disabled";
860
861			qup0_i2c4: i2c@990000 {
862				compatible = "qcom,geni-i2c";
863				reg = <0 0x00990000 0 0x4000>;
864				clock-names = "se";
865				clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
866				interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
867				#address-cells = <1>;
868				#size-cells = <0>;
869				power-domains = <&rpmhpd SC8280XP_CX>;
870				interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
871						<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
872						<&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
873				interconnect-names = "qup-core", "qup-config", "qup-memory";
874				status = "disabled";
875			};
876		};
877
878		qup1: geniqup@ac0000 {
879			compatible = "qcom,geni-se-qup";
880			reg = <0 0x00ac0000 0 0x6000>;
881			clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
882				 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
883			clock-names = "m-ahb", "s-ahb";
884			iommus = <&apps_smmu 0x83 0>;
885
886			#address-cells = <2>;
887			#size-cells = <2>;
888			ranges;
889
890			status = "disabled";
891		};
892
893		pcie4: pcie@1c00000 {
894			device_type = "pci";
895			compatible = "qcom,pcie-sc8280xp";
896			reg = <0x0 0x01c00000 0x0 0x3000>,
897			      <0x0 0x30000000 0x0 0xf1d>,
898			      <0x0 0x30000f20 0x0 0xa8>,
899			      <0x0 0x30001000 0x0 0x1000>,
900			      <0x0 0x30100000 0x0 0x100000>;
901			reg-names = "parf", "dbi", "elbi", "atu", "config";
902			#address-cells = <3>;
903			#size-cells = <2>;
904			ranges = <0x01000000 0x0 0x30200000 0x0 0x30200000 0x0 0x100000>,
905				 <0x02000000 0x0 0x30300000 0x0 0x30300000 0x0 0x1d00000>;
906			bus-range = <0x00 0xff>;
907
908			dma-coherent;
909
910			linux,pci-domain = <6>;
911			num-lanes = <1>;
912
913			interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
914				     <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
915				     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
916				     <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
917			interrupt-names = "msi0", "msi1", "msi2", "msi3";
918
919			#interrupt-cells = <1>;
920			interrupt-map-mask = <0 0 0 0x7>;
921			interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
922					<0 0 0 2 &intc 0 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
923					<0 0 0 3 &intc 0 0 GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
924					<0 0 0 4 &intc 0 0 GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
925
926			clocks = <&gcc GCC_PCIE_4_AUX_CLK>,
927				 <&gcc GCC_PCIE_4_CFG_AHB_CLK>,
928				 <&gcc GCC_PCIE_4_MSTR_AXI_CLK>,
929				 <&gcc GCC_PCIE_4_SLV_AXI_CLK>,
930				 <&gcc GCC_PCIE_4_SLV_Q2A_AXI_CLK>,
931				 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
932				 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
933				 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>,
934				 <&gcc GCC_CNOC_PCIE4_QX_CLK>;
935			clock-names = "aux",
936				      "cfg",
937				      "bus_master",
938				      "bus_slave",
939				      "slave_q2a",
940				      "ddrss_sf_tbu",
941				      "noc_aggr_4",
942				      "noc_aggr_south_sf",
943				      "cnoc_qx";
944
945			assigned-clocks = <&gcc GCC_PCIE_4_AUX_CLK>;
946			assigned-clock-rates = <19200000>;
947
948			interconnects = <&aggre2_noc MASTER_PCIE_4 0 &mc_virt SLAVE_EBI1 0>,
949					<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_4 0>;
950			interconnect-names = "pcie-mem", "cpu-pcie";
951
952			resets = <&gcc GCC_PCIE_4_BCR>;
953			reset-names = "pci";
954
955			power-domains = <&gcc PCIE_4_GDSC>;
956
957			phys = <&pcie4_phy>;
958			phy-names = "pciephy";
959
960			status = "disabled";
961		};
962
963		pcie4_phy: phy@1c06000 {
964			compatible = "qcom,sc8280xp-qmp-gen3x1-pcie-phy";
965			reg = <0x0 0x01c06000 0x0 0x2000>;
966
967			clocks = <&gcc GCC_PCIE_4_AUX_CLK>,
968				 <&gcc GCC_PCIE_4_CFG_AHB_CLK>,
969				 <&gcc GCC_PCIE_4_CLKREF_CLK>,
970				 <&gcc GCC_PCIE4_PHY_RCHNG_CLK>,
971				 <&gcc GCC_PCIE_4_PIPE_CLK>,
972				 <&gcc GCC_PCIE_4_PIPEDIV2_CLK>;
973			clock-names = "aux", "cfg_ahb", "ref", "rchng",
974				      "pipe", "pipediv2";
975
976			assigned-clocks = <&gcc GCC_PCIE4_PHY_RCHNG_CLK>;
977			assigned-clock-rates = <100000000>;
978
979			power-domains = <&gcc PCIE_4_GDSC>;
980
981			resets = <&gcc GCC_PCIE_4_PHY_BCR>;
982			reset-names = "phy";
983
984			#clock-cells = <0>;
985			clock-output-names = "pcie_4_pipe_clk";
986
987			#phy-cells = <0>;
988
989			status = "disabled";
990		};
991
992		pcie3b: pcie@1c08000 {
993			device_type = "pci";
994			compatible = "qcom,pcie-sc8280xp";
995			reg = <0x0 0x01c08000 0x0 0x3000>,
996			      <0x0 0x32000000 0x0 0xf1d>,
997			      <0x0 0x32000f20 0x0 0xa8>,
998			      <0x0 0x32001000 0x0 0x1000>,
999			      <0x0 0x32100000 0x0 0x100000>;
1000			reg-names = "parf", "dbi", "elbi", "atu", "config";
1001			#address-cells = <3>;
1002			#size-cells = <2>;
1003			ranges = <0x01000000 0x0 0x32200000 0x0 0x32200000 0x0 0x100000>,
1004				 <0x02000000 0x0 0x32300000 0x0 0x32300000 0x0 0x1d00000>;
1005			bus-range = <0x00 0xff>;
1006
1007			dma-coherent;
1008
1009			linux,pci-domain = <5>;
1010			num-lanes = <2>;
1011
1012			interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
1013				     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
1014				     <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
1015				     <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
1016			interrupt-names = "msi0", "msi1", "msi2", "msi3";
1017
1018			#interrupt-cells = <1>;
1019			interrupt-map-mask = <0 0 0 0x7>;
1020			interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 526 IRQ_TYPE_LEVEL_HIGH>,
1021					<0 0 0 2 &intc 0 0 GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>,
1022					<0 0 0 3 &intc 0 0 GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH>,
1023					<0 0 0 4 &intc 0 0 GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>;
1024
1025			clocks = <&gcc GCC_PCIE_3B_AUX_CLK>,
1026				 <&gcc GCC_PCIE_3B_CFG_AHB_CLK>,
1027				 <&gcc GCC_PCIE_3B_MSTR_AXI_CLK>,
1028				 <&gcc GCC_PCIE_3B_SLV_AXI_CLK>,
1029				 <&gcc GCC_PCIE_3B_SLV_Q2A_AXI_CLK>,
1030				 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
1031				 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
1032				 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>;
1033			clock-names = "aux",
1034				      "cfg",
1035				      "bus_master",
1036				      "bus_slave",
1037				      "slave_q2a",
1038				      "ddrss_sf_tbu",
1039				      "noc_aggr_4",
1040				      "noc_aggr_south_sf";
1041
1042			assigned-clocks = <&gcc GCC_PCIE_3B_AUX_CLK>;
1043			assigned-clock-rates = <19200000>;
1044
1045			interconnects = <&aggre2_noc MASTER_PCIE_3B 0 &mc_virt SLAVE_EBI1 0>,
1046					<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_3B 0>;
1047			interconnect-names = "pcie-mem", "cpu-pcie";
1048
1049			resets = <&gcc GCC_PCIE_3B_BCR>;
1050			reset-names = "pci";
1051
1052			power-domains = <&gcc PCIE_3B_GDSC>;
1053
1054			phys = <&pcie3b_phy>;
1055			phy-names = "pciephy";
1056
1057			status = "disabled";
1058		};
1059
1060		pcie3b_phy: phy@1c0e000 {
1061			compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy";
1062			reg = <0x0 0x01c0e000 0x0 0x2000>;
1063
1064			clocks = <&gcc GCC_PCIE_3B_AUX_CLK>,
1065				 <&gcc GCC_PCIE_3B_CFG_AHB_CLK>,
1066				 <&gcc GCC_PCIE_3A3B_CLKREF_CLK>,
1067				 <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>,
1068				 <&gcc GCC_PCIE_3B_PIPE_CLK>,
1069				 <&gcc GCC_PCIE_3B_PIPEDIV2_CLK>;
1070			clock-names = "aux", "cfg_ahb", "ref", "rchng",
1071				      "pipe", "pipediv2";
1072
1073			assigned-clocks = <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>;
1074			assigned-clock-rates = <100000000>;
1075
1076			power-domains = <&gcc PCIE_3B_GDSC>;
1077
1078			resets = <&gcc GCC_PCIE_3B_PHY_BCR>;
1079			reset-names = "phy";
1080
1081			#clock-cells = <0>;
1082			clock-output-names = "pcie_3b_pipe_clk";
1083
1084			#phy-cells = <0>;
1085
1086			status = "disabled";
1087		};
1088
1089		pcie3a: pcie@1c10000 {
1090			device_type = "pci";
1091			compatible = "qcom,pcie-sc8280xp";
1092			reg = <0x0 0x01c10000 0x0 0x3000>,
1093			      <0x0 0x34000000 0x0 0xf1d>,
1094			      <0x0 0x34000f20 0x0 0xa8>,
1095			      <0x0 0x34001000 0x0 0x1000>,
1096			      <0x0 0x34100000 0x0 0x100000>;
1097			reg-names = "parf", "dbi", "elbi", "atu", "config";
1098			#address-cells = <3>;
1099			#size-cells = <2>;
1100			ranges = <0x01000000 0x0 0x34200000 0x0 0x34200000 0x0 0x100000>,
1101				 <0x02000000 0x0 0x34300000 0x0 0x34300000 0x0 0x1d00000>;
1102			bus-range = <0x00 0xff>;
1103
1104			dma-coherent;
1105
1106			linux,pci-domain = <4>;
1107			num-lanes = <4>;
1108
1109			interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
1110				     <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
1111				     <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
1112				     <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
1113			interrupt-names = "msi0", "msi1", "msi2", "msi3";
1114
1115			#interrupt-cells = <1>;
1116			interrupt-map-mask = <0 0 0 0x7>;
1117			interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>,
1118					<0 0 0 2 &intc 0 0 GIC_SPI 542 IRQ_TYPE_LEVEL_HIGH>,
1119					<0 0 0 3 &intc 0 0 GIC_SPI 543 IRQ_TYPE_LEVEL_HIGH>,
1120					<0 0 0 4 &intc 0 0 GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>;
1121
1122			clocks = <&gcc GCC_PCIE_3A_AUX_CLK>,
1123				 <&gcc GCC_PCIE_3A_CFG_AHB_CLK>,
1124				 <&gcc GCC_PCIE_3A_MSTR_AXI_CLK>,
1125				 <&gcc GCC_PCIE_3A_SLV_AXI_CLK>,
1126				 <&gcc GCC_PCIE_3A_SLV_Q2A_AXI_CLK>,
1127				 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
1128				 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
1129				 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>;
1130			clock-names = "aux",
1131				      "cfg",
1132				      "bus_master",
1133				      "bus_slave",
1134				      "slave_q2a",
1135				      "ddrss_sf_tbu",
1136				      "noc_aggr_4",
1137				      "noc_aggr_south_sf";
1138
1139			assigned-clocks = <&gcc GCC_PCIE_3A_AUX_CLK>;
1140			assigned-clock-rates = <19200000>;
1141
1142			interconnects = <&aggre2_noc MASTER_PCIE_3A 0 &mc_virt SLAVE_EBI1 0>,
1143					<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_3A 0>;
1144			interconnect-names = "pcie-mem", "cpu-pcie";
1145
1146			resets = <&gcc GCC_PCIE_3A_BCR>;
1147			reset-names = "pci";
1148
1149			power-domains = <&gcc PCIE_3A_GDSC>;
1150
1151			phys = <&pcie3a_phy>;
1152			phy-names = "pciephy";
1153
1154			status = "disabled";
1155		};
1156
1157		pcie3a_phy: phy@1c14000 {
1158			compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy";
1159			reg = <0x0 0x01c14000 0x0 0x2000>,
1160			      <0x0 0x01c16000 0x0 0x2000>;
1161
1162			clocks = <&gcc GCC_PCIE_3A_AUX_CLK>,
1163				 <&gcc GCC_PCIE_3A_CFG_AHB_CLK>,
1164				 <&gcc GCC_PCIE_3A3B_CLKREF_CLK>,
1165				 <&gcc GCC_PCIE3A_PHY_RCHNG_CLK>,
1166				 <&gcc GCC_PCIE_3A_PIPE_CLK>,
1167				 <&gcc GCC_PCIE_3A_PIPEDIV2_CLK>;
1168			clock-names = "aux", "cfg_ahb", "ref", "rchng",
1169				      "pipe", "pipediv2";
1170
1171			assigned-clocks = <&gcc GCC_PCIE3A_PHY_RCHNG_CLK>;
1172			assigned-clock-rates = <100000000>;
1173
1174			power-domains = <&gcc PCIE_3A_GDSC>;
1175
1176			resets = <&gcc GCC_PCIE_3A_PHY_BCR>;
1177			reset-names = "phy";
1178
1179			qcom,4ln-config-sel = <&tcsr 0xa044 1>;
1180
1181			#clock-cells = <0>;
1182			clock-output-names = "pcie_3a_pipe_clk";
1183
1184			#phy-cells = <0>;
1185
1186			status = "disabled";
1187		};
1188
1189		pcie2b: pcie@1c18000 {
1190			device_type = "pci";
1191			compatible = "qcom,pcie-sc8280xp";
1192			reg = <0x0 0x01c18000 0x0 0x3000>,
1193			      <0x0 0x38000000 0x0 0xf1d>,
1194			      <0x0 0x38000f20 0x0 0xa8>,
1195			      <0x0 0x38001000 0x0 0x1000>,
1196			      <0x0 0x38100000 0x0 0x100000>;
1197			reg-names = "parf", "dbi", "elbi", "atu", "config";
1198			#address-cells = <3>;
1199			#size-cells = <2>;
1200			ranges = <0x01000000 0x0 0x38200000 0x0 0x38200000 0x0 0x100000>,
1201				 <0x02000000 0x0 0x38300000 0x0 0x38300000 0x0 0x1d00000>;
1202			bus-range = <0x00 0xff>;
1203
1204			dma-coherent;
1205
1206			linux,pci-domain = <3>;
1207			num-lanes = <2>;
1208
1209			interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
1210				     <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
1211				     <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
1212				     <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>;
1213			interrupt-names = "msi0", "msi1", "msi2", "msi3";
1214
1215			#interrupt-cells = <1>;
1216			interrupt-map-mask = <0 0 0 0x7>;
1217			interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
1218					<0 0 0 2 &intc 0 0 GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
1219					<0 0 0 3 &intc 0 0 GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
1220					<0 0 0 4 &intc 0 0 GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>;
1221
1222			clocks = <&gcc GCC_PCIE_2B_AUX_CLK>,
1223				 <&gcc GCC_PCIE_2B_CFG_AHB_CLK>,
1224				 <&gcc GCC_PCIE_2B_MSTR_AXI_CLK>,
1225				 <&gcc GCC_PCIE_2B_SLV_AXI_CLK>,
1226				 <&gcc GCC_PCIE_2B_SLV_Q2A_AXI_CLK>,
1227				 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
1228				 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
1229				 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>;
1230			clock-names = "aux",
1231				      "cfg",
1232				      "bus_master",
1233				      "bus_slave",
1234				      "slave_q2a",
1235				      "ddrss_sf_tbu",
1236				      "noc_aggr_4",
1237				      "noc_aggr_south_sf";
1238
1239			assigned-clocks = <&gcc GCC_PCIE_2B_AUX_CLK>;
1240			assigned-clock-rates = <19200000>;
1241
1242			interconnects = <&aggre2_noc MASTER_PCIE_2B 0 &mc_virt SLAVE_EBI1 0>,
1243					<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_2B 0>;
1244			interconnect-names = "pcie-mem", "cpu-pcie";
1245
1246			resets = <&gcc GCC_PCIE_2B_BCR>;
1247			reset-names = "pci";
1248
1249			power-domains = <&gcc PCIE_2B_GDSC>;
1250
1251			phys = <&pcie2b_phy>;
1252			phy-names = "pciephy";
1253
1254			status = "disabled";
1255		};
1256
1257		pcie2b_phy: phy@1c1e000 {
1258			compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy";
1259			reg = <0x0 0x01c1e000 0x0 0x2000>;
1260
1261			clocks = <&gcc GCC_PCIE_2B_AUX_CLK>,
1262				 <&gcc GCC_PCIE_2B_CFG_AHB_CLK>,
1263				 <&gcc GCC_PCIE_2A2B_CLKREF_CLK>,
1264				 <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>,
1265				 <&gcc GCC_PCIE_2B_PIPE_CLK>,
1266				 <&gcc GCC_PCIE_2B_PIPEDIV2_CLK>;
1267			clock-names = "aux", "cfg_ahb", "ref", "rchng",
1268				      "pipe", "pipediv2";
1269
1270			assigned-clocks = <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>;
1271			assigned-clock-rates = <100000000>;
1272
1273			power-domains = <&gcc PCIE_2B_GDSC>;
1274
1275			resets = <&gcc GCC_PCIE_2B_PHY_BCR>;
1276			reset-names = "phy";
1277
1278			#clock-cells = <0>;
1279			clock-output-names = "pcie_2b_pipe_clk";
1280
1281			#phy-cells = <0>;
1282
1283			status = "disabled";
1284		};
1285
1286		pcie2a: pcie@1c20000 {
1287			device_type = "pci";
1288			compatible = "qcom,pcie-sc8280xp";
1289			reg = <0x0 0x01c20000 0x0 0x3000>,
1290			      <0x0 0x3c000000 0x0 0xf1d>,
1291			      <0x0 0x3c000f20 0x0 0xa8>,
1292			      <0x0 0x3c001000 0x0 0x1000>,
1293			      <0x0 0x3c100000 0x0 0x100000>;
1294			reg-names = "parf", "dbi", "elbi", "atu", "config";
1295			#address-cells = <3>;
1296			#size-cells = <2>;
1297			ranges = <0x01000000 0x0 0x3c200000 0x0 0x3c200000 0x0 0x100000>,
1298				 <0x02000000 0x0 0x3c300000 0x0 0x3c300000 0x0 0x1d00000>;
1299			bus-range = <0x00 0xff>;
1300
1301			dma-coherent;
1302
1303			linux,pci-domain = <2>;
1304			num-lanes = <4>;
1305
1306			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
1307				     <GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH>,
1308				     <GIC_SPI 524 IRQ_TYPE_LEVEL_HIGH>,
1309				     <GIC_SPI 525 IRQ_TYPE_LEVEL_HIGH>;
1310			interrupt-names = "msi0", "msi1", "msi2", "msi3";
1311
1312			#interrupt-cells = <1>;
1313			interrupt-map-mask = <0 0 0 0x7>;
1314			interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>,
1315					<0 0 0 2 &intc 0 0 GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>,
1316					<0 0 0 3 &intc 0 0 GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>,
1317					<0 0 0 4 &intc 0 0 GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>;
1318
1319			clocks = <&gcc GCC_PCIE_2A_AUX_CLK>,
1320				 <&gcc GCC_PCIE_2A_CFG_AHB_CLK>,
1321				 <&gcc GCC_PCIE_2A_MSTR_AXI_CLK>,
1322				 <&gcc GCC_PCIE_2A_SLV_AXI_CLK>,
1323				 <&gcc GCC_PCIE_2A_SLV_Q2A_AXI_CLK>,
1324				 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
1325				 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
1326				 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>;
1327			clock-names = "aux",
1328				      "cfg",
1329				      "bus_master",
1330				      "bus_slave",
1331				      "slave_q2a",
1332				      "ddrss_sf_tbu",
1333				      "noc_aggr_4",
1334				      "noc_aggr_south_sf";
1335
1336			assigned-clocks = <&gcc GCC_PCIE_2A_AUX_CLK>;
1337			assigned-clock-rates = <19200000>;
1338
1339			interconnects = <&aggre2_noc MASTER_PCIE_2A 0 &mc_virt SLAVE_EBI1 0>,
1340					<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_2A 0>;
1341			interconnect-names = "pcie-mem", "cpu-pcie";
1342
1343			resets = <&gcc GCC_PCIE_2A_BCR>;
1344			reset-names = "pci";
1345
1346			power-domains = <&gcc PCIE_2A_GDSC>;
1347
1348			phys = <&pcie2a_phy>;
1349			phy-names = "pciephy";
1350
1351			status = "disabled";
1352		};
1353
1354		pcie2a_phy: phy@1c24000 {
1355			compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy";
1356			reg = <0x0 0x01c24000 0x0 0x2000>,
1357			      <0x0 0x01c26000 0x0 0x2000>;
1358
1359			clocks = <&gcc GCC_PCIE_2A_AUX_CLK>,
1360				 <&gcc GCC_PCIE_2A_CFG_AHB_CLK>,
1361				 <&gcc GCC_PCIE_2A2B_CLKREF_CLK>,
1362				 <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>,
1363				 <&gcc GCC_PCIE_2A_PIPE_CLK>,
1364				 <&gcc GCC_PCIE_2A_PIPEDIV2_CLK>;
1365			clock-names = "aux", "cfg_ahb", "ref", "rchng",
1366				      "pipe", "pipediv2";
1367
1368			assigned-clocks = <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>;
1369			assigned-clock-rates = <100000000>;
1370
1371			power-domains = <&gcc PCIE_2A_GDSC>;
1372
1373			resets = <&gcc GCC_PCIE_2A_PHY_BCR>;
1374			reset-names = "phy";
1375
1376			qcom,4ln-config-sel = <&tcsr 0xa044 0>;
1377
1378			#clock-cells = <0>;
1379			clock-output-names = "pcie_2a_pipe_clk";
1380
1381			#phy-cells = <0>;
1382
1383			status = "disabled";
1384		};
1385
1386		ufs_mem_hc: ufs@1d84000 {
1387			compatible = "qcom,sc8280xp-ufshc", "qcom,ufshc",
1388				     "jedec,ufs-2.0";
1389			reg = <0 0x01d84000 0 0x3000>;
1390			interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
1391			phys = <&ufs_mem_phy>;
1392			phy-names = "ufsphy";
1393			lanes-per-direction = <2>;
1394			#reset-cells = <1>;
1395			resets = <&gcc GCC_UFS_PHY_BCR>;
1396			reset-names = "rst";
1397
1398			power-domains = <&gcc UFS_PHY_GDSC>;
1399			required-opps = <&rpmhpd_opp_nom>;
1400
1401			iommus = <&apps_smmu 0xe0 0x0>;
1402			dma-coherent;
1403
1404			clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
1405				 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
1406				 <&gcc GCC_UFS_PHY_AHB_CLK>,
1407				 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
1408				 <&gcc GCC_UFS_REF_CLKREF_CLK>,
1409				 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
1410				 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
1411				 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
1412			clock-names = "core_clk",
1413				      "bus_aggr_clk",
1414				      "iface_clk",
1415				      "core_clk_unipro",
1416				      "ref_clk",
1417				      "tx_lane0_sync_clk",
1418				      "rx_lane0_sync_clk",
1419				      "rx_lane1_sync_clk";
1420			freq-table-hz = <75000000 300000000>,
1421					<0 0>,
1422					<0 0>,
1423					<75000000 300000000>,
1424					<0 0>,
1425					<0 0>,
1426					<0 0>,
1427					<0 0>;
1428			status = "disabled";
1429		};
1430
1431		ufs_mem_phy: phy@1d87000 {
1432			compatible = "qcom,sc8280xp-qmp-ufs-phy";
1433			reg = <0 0x01d87000 0 0x1000>;
1434
1435			clocks = <&gcc GCC_UFS_CARD_CLKREF_CLK>,
1436				 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
1437			clock-names = "ref", "ref_aux";
1438
1439			power-domains = <&gcc UFS_PHY_GDSC>;
1440
1441			resets = <&ufs_mem_hc 0>;
1442			reset-names = "ufsphy";
1443
1444			#phy-cells = <0>;
1445
1446			status = "disabled";
1447		};
1448
1449		ufs_card_hc: ufs@1da4000 {
1450			compatible = "qcom,sc8280xp-ufshc", "qcom,ufshc",
1451				     "jedec,ufs-2.0";
1452			reg = <0 0x01da4000 0 0x3000>;
1453			interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
1454			phys = <&ufs_card_phy>;
1455			phy-names = "ufsphy";
1456			lanes-per-direction = <2>;
1457			#reset-cells = <1>;
1458			resets = <&gcc GCC_UFS_CARD_BCR>;
1459			reset-names = "rst";
1460
1461			power-domains = <&gcc UFS_CARD_GDSC>;
1462
1463			iommus = <&apps_smmu 0x4a0 0x0>;
1464			dma-coherent;
1465
1466			clocks = <&gcc GCC_UFS_CARD_AXI_CLK>,
1467				 <&gcc GCC_AGGRE_UFS_CARD_AXI_CLK>,
1468				 <&gcc GCC_UFS_CARD_AHB_CLK>,
1469				 <&gcc GCC_UFS_CARD_UNIPRO_CORE_CLK>,
1470				 <&gcc GCC_UFS_REF_CLKREF_CLK>,
1471				 <&gcc GCC_UFS_CARD_TX_SYMBOL_0_CLK>,
1472				 <&gcc GCC_UFS_CARD_RX_SYMBOL_0_CLK>,
1473				 <&gcc GCC_UFS_CARD_RX_SYMBOL_1_CLK>;
1474			clock-names = "core_clk",
1475				      "bus_aggr_clk",
1476				      "iface_clk",
1477				      "core_clk_unipro",
1478				      "ref_clk",
1479				      "tx_lane0_sync_clk",
1480				      "rx_lane0_sync_clk",
1481				      "rx_lane1_sync_clk";
1482			freq-table-hz = <75000000 300000000>,
1483					<0 0>,
1484					<0 0>,
1485					<75000000 300000000>,
1486					<0 0>,
1487					<0 0>,
1488					<0 0>,
1489					<0 0>;
1490			status = "disabled";
1491		};
1492
1493		ufs_card_phy: phy@1da7000 {
1494			compatible = "qcom,sc8280xp-qmp-ufs-phy";
1495			reg = <0 0x01da7000 0 0x1000>;
1496
1497			clocks = <&gcc GCC_UFS_1_CARD_CLKREF_CLK>,
1498				 <&gcc GCC_UFS_CARD_PHY_AUX_CLK>;
1499			clock-names = "ref", "ref_aux";
1500
1501			power-domains = <&gcc UFS_CARD_GDSC>;
1502
1503			resets = <&ufs_card_hc 0>;
1504			reset-names = "ufsphy";
1505
1506			#phy-cells = <0>;
1507
1508			status = "disabled";
1509		};
1510
1511		tcsr_mutex: hwlock@1f40000 {
1512			compatible = "qcom,tcsr-mutex";
1513			reg = <0x0 0x01f40000 0x0 0x20000>;
1514			#hwlock-cells = <1>;
1515		};
1516
1517		tcsr: syscon@1fc0000 {
1518			compatible = "qcom,sc8280xp-tcsr", "syscon";
1519			reg = <0x0 0x01fc0000 0x0 0x30000>;
1520		};
1521
1522		usb_0_hsphy: phy@88e5000 {
1523			compatible = "qcom,sc8280xp-usb-hs-phy",
1524				     "qcom,usb-snps-hs-5nm-phy";
1525			reg = <0 0x088e5000 0 0x400>;
1526			clocks = <&rpmhcc RPMH_CXO_CLK>;
1527			clock-names = "ref";
1528			resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
1529
1530			#phy-cells = <0>;
1531
1532			status = "disabled";
1533		};
1534
1535		usb_2_hsphy0: phy@88e7000 {
1536			compatible = "qcom,sc8280xp-usb-hs-phy",
1537				     "qcom,usb-snps-hs-5nm-phy";
1538			reg = <0 0x088e7000 0 0x400>;
1539			clocks = <&gcc GCC_USB2_HS0_CLKREF_CLK>;
1540			clock-names = "ref";
1541			resets = <&gcc GCC_QUSB2PHY_HS0_MP_BCR>;
1542
1543			#phy-cells = <0>;
1544
1545			status = "disabled";
1546		};
1547
1548		usb_2_hsphy1: phy@88e8000 {
1549			compatible = "qcom,sc8280xp-usb-hs-phy",
1550				     "qcom,usb-snps-hs-5nm-phy";
1551			reg = <0 0x088e8000 0 0x400>;
1552			clocks = <&gcc GCC_USB2_HS1_CLKREF_CLK>;
1553			clock-names = "ref";
1554			resets = <&gcc GCC_QUSB2PHY_HS1_MP_BCR>;
1555
1556			#phy-cells = <0>;
1557
1558			status = "disabled";
1559		};
1560
1561		usb_2_hsphy2: phy@88e9000 {
1562			compatible = "qcom,sc8280xp-usb-hs-phy",
1563				     "qcom,usb-snps-hs-5nm-phy";
1564			reg = <0 0x088e9000 0 0x400>;
1565			clocks = <&gcc GCC_USB2_HS2_CLKREF_CLK>;
1566			clock-names = "ref";
1567			resets = <&gcc GCC_QUSB2PHY_HS2_MP_BCR>;
1568
1569			#phy-cells = <0>;
1570
1571			status = "disabled";
1572		};
1573
1574		usb_2_hsphy3: phy@88ea000 {
1575			compatible = "qcom,sc8280xp-usb-hs-phy",
1576				     "qcom,usb-snps-hs-5nm-phy";
1577			reg = <0 0x088ea000 0 0x400>;
1578			clocks = <&gcc GCC_USB2_HS3_CLKREF_CLK>;
1579			clock-names = "ref";
1580			resets = <&gcc GCC_QUSB2PHY_HS3_MP_BCR>;
1581
1582			#phy-cells = <0>;
1583
1584			status = "disabled";
1585		};
1586
1587		usb_2_qmpphy0: phy@88ef000 {
1588			compatible = "qcom,sc8280xp-qmp-usb3-uni-phy";
1589			reg = <0 0x088ef000 0 0x2000>;
1590
1591			clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>,
1592				 <&gcc GCC_USB3_MP0_CLKREF_CLK>,
1593				 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>,
1594				 <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>;
1595			clock-names = "aux", "ref", "com_aux", "pipe";
1596
1597			resets = <&gcc GCC_USB3_UNIPHY_MP0_BCR>,
1598				 <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>;
1599			reset-names = "phy", "phy_phy";
1600
1601			power-domains = <&gcc USB30_MP_GDSC>;
1602
1603			#clock-cells = <0>;
1604			clock-output-names = "usb2_phy0_pipe_clk";
1605
1606			#phy-cells = <0>;
1607
1608			status = "disabled";
1609		};
1610
1611		usb_2_qmpphy1: phy@88f1000 {
1612			compatible = "qcom,sc8280xp-qmp-usb3-uni-phy";
1613			reg = <0 0x088f1000 0 0x2000>;
1614
1615			clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>,
1616				 <&gcc GCC_USB3_MP1_CLKREF_CLK>,
1617				 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>,
1618				 <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>;
1619			clock-names = "aux", "ref", "com_aux", "pipe";
1620
1621			resets = <&gcc GCC_USB3_UNIPHY_MP1_BCR>,
1622				 <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>;
1623			reset-names = "phy", "phy_phy";
1624
1625			power-domains = <&gcc USB30_MP_GDSC>;
1626
1627			#clock-cells = <0>;
1628			clock-output-names = "usb2_phy1_pipe_clk";
1629
1630			#phy-cells = <0>;
1631
1632			status = "disabled";
1633		};
1634
1635		remoteproc_adsp: remoteproc@3000000 {
1636			compatible = "qcom,sc8280xp-adsp-pas";
1637			reg = <0 0x03000000 0 0x100>;
1638
1639			interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
1640					      <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
1641					      <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
1642					      <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
1643					      <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>,
1644					      <&smp2p_adsp_in 7 IRQ_TYPE_EDGE_RISING>;
1645			interrupt-names = "wdog", "fatal", "ready",
1646					  "handover", "stop-ack", "shutdown-ack";
1647
1648			clocks = <&rpmhcc RPMH_CXO_CLK>;
1649			clock-names = "xo";
1650
1651			power-domains = <&rpmhpd SC8280XP_LCX>,
1652					<&rpmhpd SC8280XP_LMX>;
1653			power-domain-names = "lcx", "lmx";
1654
1655			memory-region = <&pil_adsp_mem>;
1656
1657			qcom,qmp = <&aoss_qmp>;
1658
1659			qcom,smem-states = <&smp2p_adsp_out 0>;
1660			qcom,smem-state-names = "stop";
1661
1662			status = "disabled";
1663
1664			remoteproc_adsp_glink: glink-edge {
1665				interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
1666							     IPCC_MPROC_SIGNAL_GLINK_QMP
1667							     IRQ_TYPE_EDGE_RISING>;
1668				mboxes = <&ipcc IPCC_CLIENT_LPASS
1669						IPCC_MPROC_SIGNAL_GLINK_QMP>;
1670
1671				label = "lpass";
1672				qcom,remote-pid = <2>;
1673			};
1674		};
1675
1676		usb_0_qmpphy: phy-wrapper@88ec000 {
1677			compatible = "qcom,sc8280xp-qmp-usb43dp-phy";
1678			reg = <0 0x088ec000 0 0x1e4>,
1679			      <0 0x088eb000 0 0x40>,
1680			      <0 0x088ed000 0 0x1c8>;
1681			#address-cells = <2>;
1682			#size-cells = <2>;
1683			ranges;
1684
1685			clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
1686				 <&rpmhcc RPMH_CXO_CLK>,
1687				 <&gcc GCC_USB4_EUD_CLKREF_CLK>,
1688				 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
1689			clock-names = "aux", "ref_clk_src", "ref", "com_aux";
1690
1691			resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
1692				 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
1693			reset-names = "phy", "common";
1694
1695			power-domains = <&gcc USB30_PRIM_GDSC>;
1696
1697			status = "disabled";
1698
1699			usb_0_ssphy: usb3-phy@88eb400 {
1700				reg = <0 0x088eb400 0 0x100>,
1701				      <0 0x088eb600 0 0x3ec>,
1702				      <0 0x088ec400 0 0x364>,
1703				      <0 0x088eba00 0 0x100>,
1704				      <0 0x088ebc00 0 0x3ec>,
1705				      <0 0x088ec200 0 0x18>;
1706				#phy-cells = <0>;
1707				#clock-cells = <0>;
1708				clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
1709				clock-names = "pipe0";
1710				clock-output-names = "usb0_phy_pipe_clk_src";
1711			};
1712		};
1713
1714		usb_1_hsphy: phy@8902000 {
1715			compatible = "qcom,sc8280xp-usb-hs-phy",
1716				     "qcom,usb-snps-hs-5nm-phy";
1717			reg = <0 0x08902000 0 0x400>;
1718			#phy-cells = <0>;
1719
1720			clocks = <&rpmhcc RPMH_CXO_CLK>;
1721			clock-names = "ref";
1722
1723			resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
1724
1725			status = "disabled";
1726		};
1727
1728		usb_1_qmpphy: phy-wrapper@8904000 {
1729			compatible = "qcom,sc8280xp-qmp-usb43dp-phy";
1730			reg = <0 0x08904000 0 0x1e4>,
1731			      <0 0x08903000 0 0x40>,
1732			      <0 0x08905000 0 0x1c8>;
1733			#address-cells = <2>;
1734			#size-cells = <2>;
1735			ranges;
1736
1737			clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
1738				 <&rpmhcc RPMH_CXO_CLK>,
1739				 <&gcc GCC_USB4_CLKREF_CLK>,
1740				 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
1741			clock-names = "aux", "ref_clk_src", "ref", "com_aux";
1742
1743			resets = <&gcc GCC_USB3_PHY_SEC_BCR>,
1744				 <&gcc GCC_USB4_1_DP_PHY_PRIM_BCR>;
1745			reset-names = "phy", "common";
1746
1747			power-domains = <&gcc USB30_SEC_GDSC>;
1748
1749			status = "disabled";
1750
1751			usb_1_ssphy: usb3-phy@8903400 {
1752				reg = <0 0x08903400 0 0x100>,
1753				      <0 0x08903600 0 0x3ec>,
1754				      <0 0x08904400 0 0x364>,
1755				      <0 0x08903a00 0 0x100>,
1756				      <0 0x08903c00 0 0x3ec>,
1757				      <0 0x08904200 0 0x18>;
1758				#phy-cells = <0>;
1759				#clock-cells = <0>;
1760				clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
1761				clock-names = "pipe0";
1762				clock-output-names = "usb1_phy_pipe_clk_src";
1763			};
1764		};
1765
1766		pmu@9091000 {
1767			compatible = "qcom,sc8280xp-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
1768			reg = <0 0x9091000 0 0x1000>;
1769
1770			interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1771
1772			interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>;
1773
1774			operating-points-v2 = <&llcc_bwmon_opp_table>;
1775
1776			llcc_bwmon_opp_table: opp-table {
1777				compatible = "operating-points-v2";
1778
1779				opp-0 {
1780					opp-peak-kBps = <762000>;
1781				};
1782				opp-1 {
1783					opp-peak-kBps = <1720000>;
1784				};
1785				opp-2 {
1786					opp-peak-kBps = <2086000>;
1787				};
1788				opp-3 {
1789					opp-peak-kBps = <2597000>;
1790				};
1791				opp-4 {
1792					opp-peak-kBps = <2929000>;
1793				};
1794				opp-5 {
1795					opp-peak-kBps = <3879000>;
1796				};
1797				opp-6 {
1798					opp-peak-kBps = <5161000>;
1799				};
1800				opp-7 {
1801					opp-peak-kBps = <5931000>;
1802				};
1803				opp-8 {
1804					opp-peak-kBps = <6515000>;
1805				};
1806				opp-9 {
1807					opp-peak-kBps = <7980000>;
1808				};
1809				opp-10 {
1810					opp-peak-kBps = <8136000>;
1811				};
1812				opp-11 {
1813					opp-peak-kBps = <10437000>;
1814				};
1815				opp-12 {
1816					opp-peak-kBps = <12191000>;
1817				};
1818			};
1819		};
1820
1821		pmu@90b6400 {
1822			compatible = "qcom,sc8280xp-cpu-bwmon", "qcom,msm8998-bwmon";
1823			reg = <0 0x090b6400 0 0x600>;
1824
1825			interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
1826
1827			interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>;
1828			operating-points-v2 = <&cpu_bwmon_opp_table>;
1829
1830			cpu_bwmon_opp_table: opp-table {
1831				compatible = "operating-points-v2";
1832
1833				opp-0 {
1834					opp-peak-kBps = <2288000>;
1835				};
1836				opp-1 {
1837					opp-peak-kBps = <4577000>;
1838				};
1839				opp-2 {
1840					opp-peak-kBps = <7110000>;
1841				};
1842				opp-3 {
1843					opp-peak-kBps = <9155000>;
1844				};
1845				opp-4 {
1846					opp-peak-kBps = <12298000>;
1847				};
1848				opp-5 {
1849					opp-peak-kBps = <14236000>;
1850				};
1851				opp-6 {
1852					opp-peak-kBps = <15258001>;
1853				};
1854			};
1855		};
1856
1857		system-cache-controller@9200000 {
1858			compatible = "qcom,sc8280xp-llcc";
1859			reg = <0 0x09200000 0 0x58000>, <0 0x09600000 0 0x58000>;
1860			reg-names = "llcc_base", "llcc_broadcast_base";
1861			interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
1862		};
1863
1864		usb_0: usb@a6f8800 {
1865			compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3";
1866			reg = <0 0x0a6f8800 0 0x400>;
1867			#address-cells = <2>;
1868			#size-cells = <2>;
1869			ranges;
1870
1871			clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
1872				 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
1873				 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
1874				 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
1875				 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1876				 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
1877				 <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>,
1878				 <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>,
1879				 <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
1880			clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi",
1881				      "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys";
1882
1883			assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1884					  <&gcc GCC_USB30_PRIM_MASTER_CLK>;
1885			assigned-clock-rates = <19200000>, <200000000>;
1886
1887			interrupts-extended = <&intc GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>,
1888					      <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
1889					      <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
1890					      <&pdc 138 IRQ_TYPE_LEVEL_HIGH>;
1891			interrupt-names = "pwr_event",
1892					  "dp_hs_phy_irq",
1893					  "dm_hs_phy_irq",
1894					  "ss_phy_irq";
1895
1896			power-domains = <&gcc USB30_PRIM_GDSC>;
1897
1898			resets = <&gcc GCC_USB30_PRIM_BCR>;
1899
1900			interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
1901					<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
1902			interconnect-names = "usb-ddr", "apps-usb";
1903
1904			wakeup-source;
1905
1906			status = "disabled";
1907
1908			usb_0_dwc3: usb@a600000 {
1909				compatible = "snps,dwc3";
1910				reg = <0 0x0a600000 0 0xcd00>;
1911				interrupts = <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>;
1912				iommus = <&apps_smmu 0x820 0x0>;
1913				phys = <&usb_0_hsphy>, <&usb_0_ssphy>;
1914				phy-names = "usb2-phy", "usb3-phy";
1915			};
1916		};
1917
1918		usb_1: usb@a8f8800 {
1919			compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3";
1920			reg = <0 0x0a8f8800 0 0x400>;
1921			#address-cells = <2>;
1922			#size-cells = <2>;
1923			ranges;
1924
1925			clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
1926				 <&gcc GCC_USB30_SEC_MASTER_CLK>,
1927				 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
1928				 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
1929				 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
1930				 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
1931				 <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>,
1932				 <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>,
1933				 <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
1934			clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi",
1935				      "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys";
1936
1937			assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
1938					  <&gcc GCC_USB30_SEC_MASTER_CLK>;
1939			assigned-clock-rates = <19200000>, <200000000>;
1940
1941			interrupts-extended = <&intc GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>,
1942					      <&pdc 12 IRQ_TYPE_EDGE_BOTH>,
1943					      <&pdc 13 IRQ_TYPE_EDGE_BOTH>,
1944					      <&pdc 136 IRQ_TYPE_LEVEL_HIGH>;
1945			interrupt-names = "pwr_event",
1946					  "dp_hs_phy_irq",
1947					  "dm_hs_phy_irq",
1948					  "ss_phy_irq";
1949
1950			power-domains = <&gcc USB30_SEC_GDSC>;
1951
1952			resets = <&gcc GCC_USB30_SEC_BCR>;
1953
1954			interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>,
1955					<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>;
1956			interconnect-names = "usb-ddr", "apps-usb";
1957
1958			wakeup-source;
1959
1960			status = "disabled";
1961
1962			usb_1_dwc3: usb@a800000 {
1963				compatible = "snps,dwc3";
1964				reg = <0 0x0a800000 0 0xcd00>;
1965				interrupts = <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>;
1966				iommus = <&apps_smmu 0x860 0x0>;
1967				phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
1968				phy-names = "usb2-phy", "usb3-phy";
1969			};
1970		};
1971
1972		pdc: interrupt-controller@b220000 {
1973			compatible = "qcom,sc8280xp-pdc", "qcom,pdc";
1974			reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
1975			qcom,pdc-ranges = <0 480 40>,
1976					  <40 140 14>,
1977					  <54 263 1>,
1978					  <55 306 4>,
1979					  <59 312 3>,
1980					  <62 374 2>,
1981					  <64 434 2>,
1982					  <66 438 3>,
1983					  <69 86 1>,
1984					  <70 520 54>,
1985					  <124 609 28>,
1986					  <159 638 1>,
1987					  <160 720 8>,
1988					  <168 801 1>,
1989					  <169 728 30>,
1990					  <199 416 2>,
1991					  <201 449 1>,
1992					  <202 89 1>,
1993					  <203 451 1>,
1994					  <204 462 1>,
1995					  <205 264 1>,
1996					  <206 579 1>,
1997					  <207 653 1>,
1998					  <208 656 1>,
1999					  <209 659 1>,
2000					  <210 122 1>,
2001					  <211 699 1>,
2002					  <212 705 1>,
2003					  <213 450 1>,
2004					  <214 643 1>,
2005					  <216 646 5>,
2006					  <221 390 5>,
2007					  <226 700 3>,
2008					  <229 240 3>,
2009					  <232 269 1>,
2010					  <233 377 1>,
2011					  <234 372 1>,
2012					  <235 138 1>,
2013					  <236 857 1>,
2014					  <237 860 1>,
2015					  <238 137 1>,
2016					  <239 668 1>,
2017					  <240 366 1>,
2018					  <241 949 1>,
2019					  <242 815 5>,
2020					  <247 769 1>,
2021					  <248 768 1>,
2022					  <249 663 1>,
2023					  <250 799 2>,
2024					  <252 798 1>,
2025					  <253 765 1>,
2026					  <254 763 1>,
2027					  <255 454 1>,
2028					  <258 139 1>,
2029					  <259 786 2>,
2030					  <261 370 2>,
2031					  <263 158 2>;
2032			#interrupt-cells = <2>;
2033			interrupt-parent = <&intc>;
2034			interrupt-controller;
2035		};
2036
2037		tsens0: thermal-sensor@c263000 {
2038			compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2";
2039			reg = <0 0x0c263000 0 0x1ff>, /* TM */
2040			      <0 0x0c222000 0 0x8>; /* SROT */
2041			#qcom,sensors = <14>;
2042			interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>,
2043					      <&pdc 28 IRQ_TYPE_LEVEL_HIGH>;
2044			interrupt-names = "uplow", "critical";
2045			#thermal-sensor-cells = <1>;
2046		};
2047
2048		tsens1: thermal-sensor@c265000 {
2049			compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2";
2050			reg = <0 0x0c265000 0 0x1ff>, /* TM */
2051			      <0 0x0c223000 0 0x8>; /* SROT */
2052			#qcom,sensors = <16>;
2053			interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>,
2054					      <&pdc 29 IRQ_TYPE_LEVEL_HIGH>;
2055			interrupt-names = "uplow", "critical";
2056			#thermal-sensor-cells = <1>;
2057		};
2058
2059		aoss_qmp: power-controller@c300000 {
2060			compatible = "qcom,sc8280xp-aoss-qmp", "qcom,aoss-qmp";
2061			reg = <0 0x0c300000 0 0x400>;
2062			interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>;
2063			mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
2064
2065			#clock-cells = <0>;
2066		};
2067
2068		sram@c3f0000 {
2069			compatible = "qcom,rpmh-stats";
2070			reg = <0 0x0c3f0000 0 0x400>;
2071		};
2072
2073		spmi_bus: spmi@c440000 {
2074			compatible = "qcom,spmi-pmic-arb";
2075			reg = <0 0x0c440000 0 0x1100>,
2076			      <0 0x0c600000 0 0x2000000>,
2077			      <0 0x0e600000 0 0x100000>,
2078			      <0 0x0e700000 0 0xa0000>,
2079			      <0 0x0c40a000 0 0x26000>;
2080			reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
2081			interrupt-names = "periph_irq";
2082			interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
2083			qcom,ee = <0>;
2084			qcom,channel = <0>;
2085			#address-cells = <1>;
2086			#size-cells = <1>;
2087			interrupt-controller;
2088			#interrupt-cells = <4>;
2089		};
2090
2091		tlmm: pinctrl@f100000 {
2092			compatible = "qcom,sc8280xp-tlmm";
2093			reg = <0 0x0f100000 0 0x300000>;
2094			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
2095			gpio-controller;
2096			#gpio-cells = <2>;
2097			interrupt-controller;
2098			#interrupt-cells = <2>;
2099			gpio-ranges = <&tlmm 0 0 230>;
2100		};
2101
2102		apps_smmu: iommu@15000000 {
2103			compatible = "qcom,sc8280xp-smmu-500", "arm,mmu-500";
2104			reg = <0 0x15000000 0 0x100000>;
2105			#iommu-cells = <2>;
2106			#global-interrupts = <2>;
2107			interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
2108				     <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
2109				     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
2110				     <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
2111				     <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
2112				     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
2113				     <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
2114				     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
2115				     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
2116				     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
2117				     <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
2118				     <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
2119				     <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
2120				     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
2121				     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
2122				     <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
2123				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
2124				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
2125				     <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
2126				     <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
2127				     <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
2128				     <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
2129				     <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
2130				     <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
2131				     <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
2132				     <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
2133				     <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
2134				     <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
2135				     <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
2136				     <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
2137				     <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
2138				     <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
2139				     <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
2140				     <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
2141				     <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
2142				     <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
2143				     <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
2144				     <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
2145				     <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
2146				     <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
2147				     <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
2148				     <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
2149				     <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
2150				     <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
2151				     <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
2152				     <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
2153				     <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
2154				     <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
2155				     <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
2156				     <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
2157				     <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
2158				     <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
2159				     <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
2160				     <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
2161				     <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
2162				     <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
2163				     <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
2164				     <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
2165				     <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
2166				     <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
2167				     <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
2168				     <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
2169				     <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
2170				     <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
2171				     <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
2172				     <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
2173				     <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
2174				     <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
2175				     <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
2176				     <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
2177				     <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
2178				     <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
2179				     <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
2180				     <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
2181				     <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
2182				     <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
2183				     <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
2184				     <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
2185				     <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
2186				     <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
2187				     <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>,
2188				     <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
2189				     <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
2190				     <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
2191				     <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>,
2192				     <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
2193				     <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
2194				     <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
2195				     <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
2196				     <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
2197				     <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
2198				     <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
2199				     <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
2200				     <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
2201				     <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
2202				     <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
2203				     <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
2204				     <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
2205				     <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>,
2206				     <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>,
2207				     <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>,
2208				     <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>,
2209				     <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
2210				     <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>,
2211				     <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>,
2212				     <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>,
2213				     <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>,
2214				     <GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH>,
2215				     <GIC_SPI 911 IRQ_TYPE_LEVEL_HIGH>,
2216				     <GIC_SPI 910 IRQ_TYPE_LEVEL_HIGH>,
2217				     <GIC_SPI 909 IRQ_TYPE_LEVEL_HIGH>,
2218				     <GIC_SPI 908 IRQ_TYPE_LEVEL_HIGH>,
2219				     <GIC_SPI 907 IRQ_TYPE_LEVEL_HIGH>,
2220				     <GIC_SPI 906 IRQ_TYPE_LEVEL_HIGH>,
2221				     <GIC_SPI 905 IRQ_TYPE_LEVEL_HIGH>,
2222				     <GIC_SPI 904 IRQ_TYPE_LEVEL_HIGH>,
2223				     <GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>,
2224				     <GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>,
2225				     <GIC_SPI 901 IRQ_TYPE_LEVEL_HIGH>,
2226				     <GIC_SPI 900 IRQ_TYPE_LEVEL_HIGH>,
2227				     <GIC_SPI 899 IRQ_TYPE_LEVEL_HIGH>,
2228				     <GIC_SPI 898 IRQ_TYPE_LEVEL_HIGH>,
2229				     <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>,
2230				     <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>,
2231				     <GIC_SPI 895 IRQ_TYPE_LEVEL_HIGH>,
2232				     <GIC_SPI 894 IRQ_TYPE_LEVEL_HIGH>,
2233				     <GIC_SPI 893 IRQ_TYPE_LEVEL_HIGH>,
2234				     <GIC_SPI 892 IRQ_TYPE_LEVEL_HIGH>,
2235				     <GIC_SPI 891 IRQ_TYPE_LEVEL_HIGH>,
2236				     <GIC_SPI 890 IRQ_TYPE_LEVEL_HIGH>;
2237		};
2238
2239		intc: interrupt-controller@17a00000 {
2240			compatible = "arm,gic-v3";
2241			interrupt-controller;
2242			#interrupt-cells = <3>;
2243			reg = <0x0 0x17a00000 0x0 0x10000>,	/* GICD */
2244			      <0x0 0x17a60000 0x0 0x100000>;	/* GICR * 8 */
2245			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
2246			#redistributor-regions = <1>;
2247			redistributor-stride = <0 0x20000>;
2248
2249			#address-cells = <2>;
2250			#size-cells = <2>;
2251			ranges;
2252
2253			gic-its@17a40000 {
2254				compatible = "arm,gic-v3-its";
2255				reg = <0 0x17a40000 0 0x20000>;
2256				msi-controller;
2257				#msi-cells = <1>;
2258			};
2259		};
2260
2261		watchdog@17c10000 {
2262			compatible = "qcom,apss-wdt-sc8280xp", "qcom,kpss-wdt";
2263			reg = <0 0x17c10000 0 0x1000>;
2264			clocks = <&sleep_clk>;
2265			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
2266		};
2267
2268		timer@17c20000 {
2269			compatible = "arm,armv7-timer-mem";
2270			reg = <0x0 0x17c20000 0x0 0x1000>;
2271			#address-cells = <1>;
2272			#size-cells = <1>;
2273			ranges = <0x0 0x0 0x0 0x20000000>;
2274
2275			frame@17c21000 {
2276				frame-number = <0>;
2277				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
2278					     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
2279				reg = <0x17c21000 0x1000>,
2280				      <0x17c22000 0x1000>;
2281			};
2282
2283			frame@17c23000 {
2284				frame-number = <1>;
2285				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
2286				reg = <0x17c23000 0x1000>;
2287				status = "disabled";
2288			};
2289
2290			frame@17c25000 {
2291				frame-number = <2>;
2292				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
2293				reg = <0x17c25000 0x1000>;
2294				status = "disabled";
2295			};
2296
2297			frame@17c27000 {
2298				frame-number = <3>;
2299				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
2300				reg = <0x17c26000 0x1000>;
2301				status = "disabled";
2302			};
2303
2304			frame@17c29000 {
2305				frame-number = <4>;
2306				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
2307				reg = <0x17c29000 0x1000>;
2308				status = "disabled";
2309			};
2310
2311			frame@17c2b000 {
2312				frame-number = <5>;
2313				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
2314				reg = <0x17c2b000 0x1000>;
2315				status = "disabled";
2316			};
2317
2318			frame@17c2d000 {
2319				frame-number = <6>;
2320				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
2321				reg = <0x17c2d000 0x1000>;
2322				status = "disabled";
2323			};
2324		};
2325
2326		apps_rsc: rsc@18200000 {
2327			compatible = "qcom,rpmh-rsc";
2328			reg = <0x0 0x18200000 0x0 0x10000>,
2329				<0x0 0x18210000 0x0 0x10000>,
2330				<0x0 0x18220000 0x0 0x10000>;
2331			reg-names = "drv-0", "drv-1", "drv-2";
2332			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
2333				     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
2334				     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
2335			qcom,tcs-offset = <0xd00>;
2336			qcom,drv-id = <2>;
2337			qcom,tcs-config = <ACTIVE_TCS  2>, <SLEEP_TCS   3>,
2338					  <WAKE_TCS    3>, <CONTROL_TCS 1>;
2339			label = "apps_rsc";
2340
2341			apps_bcm_voter: bcm-voter {
2342				compatible = "qcom,bcm-voter";
2343			};
2344
2345			rpmhcc: clock-controller {
2346				compatible = "qcom,sc8280xp-rpmh-clk";
2347				#clock-cells = <1>;
2348				clock-names = "xo";
2349				clocks = <&xo_board_clk>;
2350			};
2351
2352			rpmhpd: power-controller {
2353				compatible = "qcom,sc8280xp-rpmhpd";
2354				#power-domain-cells = <1>;
2355				operating-points-v2 = <&rpmhpd_opp_table>;
2356
2357				rpmhpd_opp_table: opp-table {
2358					compatible = "operating-points-v2";
2359
2360					rpmhpd_opp_ret: opp1 {
2361						opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
2362					};
2363
2364					rpmhpd_opp_min_svs: opp2 {
2365						opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2366					};
2367
2368					rpmhpd_opp_low_svs: opp3 {
2369						opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2370					};
2371
2372					rpmhpd_opp_svs: opp4 {
2373						opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2374					};
2375
2376					rpmhpd_opp_svs_l1: opp5 {
2377						opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2378					};
2379
2380					rpmhpd_opp_nom: opp6 {
2381						opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2382					};
2383
2384					rpmhpd_opp_nom_l1: opp7 {
2385						opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2386					};
2387
2388					rpmhpd_opp_nom_l2: opp8 {
2389						opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
2390					};
2391
2392					rpmhpd_opp_turbo: opp9 {
2393						opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2394					};
2395
2396					rpmhpd_opp_turbo_l1: opp10 {
2397						opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
2398					};
2399				};
2400			};
2401		};
2402
2403		epss_l3: interconnect@18590000 {
2404			compatible = "qcom,sc8280xp-epss-l3", "qcom,epss-l3";
2405			reg = <0 0x18590000 0 0x1000>;
2406
2407			clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
2408			clock-names = "xo", "alternate";
2409
2410			#interconnect-cells = <1>;
2411		};
2412
2413		cpufreq_hw: cpufreq@18591000 {
2414			compatible = "qcom,sc8280xp-cpufreq-epss", "qcom,cpufreq-epss";
2415			reg = <0 0x18591000 0 0x1000>,
2416			      <0 0x18592000 0 0x1000>;
2417			reg-names = "freq-domain0", "freq-domain1";
2418
2419			clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
2420			clock-names = "xo", "alternate";
2421
2422			#freq-domain-cells = <1>;
2423		};
2424
2425		remoteproc_nsp0: remoteproc@1b300000 {
2426			compatible = "qcom,sc8280xp-nsp0-pas";
2427			reg = <0 0x1b300000 0 0x100>;
2428
2429			interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
2430					      <&smp2p_nsp0_in 0 IRQ_TYPE_EDGE_RISING>,
2431					      <&smp2p_nsp0_in 1 IRQ_TYPE_EDGE_RISING>,
2432					      <&smp2p_nsp0_in 2 IRQ_TYPE_EDGE_RISING>,
2433					      <&smp2p_nsp0_in 3 IRQ_TYPE_EDGE_RISING>;
2434			interrupt-names = "wdog", "fatal", "ready",
2435					  "handover", "stop-ack";
2436
2437			clocks = <&rpmhcc RPMH_CXO_CLK>;
2438			clock-names = "xo";
2439
2440			power-domains = <&rpmhpd SC8280XP_NSP>;
2441			power-domain-names = "nsp";
2442
2443			memory-region = <&pil_nsp0_mem>;
2444
2445			qcom,smem-states = <&smp2p_nsp0_out 0>;
2446			qcom,smem-state-names = "stop";
2447
2448			interconnects = <&nspa_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>;
2449
2450			status = "disabled";
2451
2452			glink-edge {
2453				interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
2454							     IPCC_MPROC_SIGNAL_GLINK_QMP
2455							     IRQ_TYPE_EDGE_RISING>;
2456				mboxes = <&ipcc IPCC_CLIENT_CDSP
2457						IPCC_MPROC_SIGNAL_GLINK_QMP>;
2458
2459				label = "nsp0";
2460				qcom,remote-pid = <5>;
2461
2462				fastrpc {
2463					compatible = "qcom,fastrpc";
2464					qcom,glink-channels = "fastrpcglink-apps-dsp";
2465					label = "cdsp";
2466					#address-cells = <1>;
2467					#size-cells = <0>;
2468
2469					compute-cb@1 {
2470						compatible = "qcom,fastrpc-compute-cb";
2471						reg = <1>;
2472						iommus = <&apps_smmu 0x3181 0x0420>;
2473					};
2474
2475					compute-cb@2 {
2476						compatible = "qcom,fastrpc-compute-cb";
2477						reg = <2>;
2478						iommus = <&apps_smmu 0x3182 0x0420>;
2479					};
2480
2481					compute-cb@3 {
2482						compatible = "qcom,fastrpc-compute-cb";
2483						reg = <3>;
2484						iommus = <&apps_smmu 0x3183 0x0420>;
2485					};
2486
2487					compute-cb@4 {
2488						compatible = "qcom,fastrpc-compute-cb";
2489						reg = <4>;
2490						iommus = <&apps_smmu 0x3184 0x0420>;
2491					};
2492
2493					compute-cb@5 {
2494						compatible = "qcom,fastrpc-compute-cb";
2495						reg = <5>;
2496						iommus = <&apps_smmu 0x3185 0x0420>;
2497					};
2498
2499					compute-cb@6 {
2500						compatible = "qcom,fastrpc-compute-cb";
2501						reg = <6>;
2502						iommus = <&apps_smmu 0x3186 0x0420>;
2503					};
2504
2505					compute-cb@7 {
2506						compatible = "qcom,fastrpc-compute-cb";
2507						reg = <7>;
2508						iommus = <&apps_smmu 0x3187 0x0420>;
2509					};
2510
2511					compute-cb@8 {
2512						compatible = "qcom,fastrpc-compute-cb";
2513						reg = <8>;
2514						iommus = <&apps_smmu 0x3188 0x0420>;
2515					};
2516
2517					compute-cb@9 {
2518						compatible = "qcom,fastrpc-compute-cb";
2519						reg = <9>;
2520						iommus = <&apps_smmu 0x318b 0x0420>;
2521					};
2522
2523					compute-cb@10 {
2524						compatible = "qcom,fastrpc-compute-cb";
2525						reg = <10>;
2526						iommus = <&apps_smmu 0x318b 0x0420>;
2527					};
2528
2529					compute-cb@11 {
2530						compatible = "qcom,fastrpc-compute-cb";
2531						reg = <11>;
2532						iommus = <&apps_smmu 0x318c 0x0420>;
2533					};
2534
2535					compute-cb@12 {
2536						compatible = "qcom,fastrpc-compute-cb";
2537						reg = <12>;
2538						iommus = <&apps_smmu 0x318d 0x0420>;
2539					};
2540
2541					compute-cb@13 {
2542						compatible = "qcom,fastrpc-compute-cb";
2543						reg = <13>;
2544						iommus = <&apps_smmu 0x318e 0x0420>;
2545					};
2546
2547					compute-cb@14 {
2548						compatible = "qcom,fastrpc-compute-cb";
2549						reg = <14>;
2550						iommus = <&apps_smmu 0x318f 0x0420>;
2551					};
2552				};
2553			};
2554		};
2555
2556		remoteproc_nsp1: remoteproc@21300000 {
2557			compatible = "qcom,sc8280xp-nsp1-pas";
2558			reg = <0 0x21300000 0 0x100>;
2559
2560			interrupts-extended = <&intc GIC_SPI 887 IRQ_TYPE_LEVEL_HIGH>,
2561					      <&smp2p_nsp1_in 0 IRQ_TYPE_EDGE_RISING>,
2562					      <&smp2p_nsp1_in 1 IRQ_TYPE_EDGE_RISING>,
2563					      <&smp2p_nsp1_in 2 IRQ_TYPE_EDGE_RISING>,
2564					      <&smp2p_nsp1_in 3 IRQ_TYPE_EDGE_RISING>;
2565			interrupt-names = "wdog", "fatal", "ready",
2566					  "handover", "stop-ack";
2567
2568			clocks = <&rpmhcc RPMH_CXO_CLK>;
2569			clock-names = "xo";
2570
2571			power-domains = <&rpmhpd SC8280XP_NSP>;
2572			power-domain-names = "nsp";
2573
2574			memory-region = <&pil_nsp1_mem>;
2575
2576			qcom,smem-states = <&smp2p_nsp1_out 0>;
2577			qcom,smem-state-names = "stop";
2578
2579			interconnects = <&nspb_noc MASTER_CDSP_PROC_B 0 &mc_virt SLAVE_EBI1 0>;
2580
2581			status = "disabled";
2582
2583			glink-edge {
2584				interrupts-extended = <&ipcc IPCC_CLIENT_NSP1
2585							     IPCC_MPROC_SIGNAL_GLINK_QMP
2586							     IRQ_TYPE_EDGE_RISING>;
2587				mboxes = <&ipcc IPCC_CLIENT_NSP1
2588						IPCC_MPROC_SIGNAL_GLINK_QMP>;
2589
2590				label = "nsp1";
2591				qcom,remote-pid = <12>;
2592			};
2593		};
2594	};
2595
2596	thermal-zones {
2597		cpu0-thermal {
2598			polling-delay-passive = <250>;
2599			polling-delay = <1000>;
2600
2601			thermal-sensors = <&tsens0 1>;
2602
2603			trips {
2604				cpu-crit {
2605					temperature = <110000>;
2606					hysteresis = <1000>;
2607					type = "critical";
2608				};
2609			};
2610		};
2611
2612		cpu1-thermal {
2613			polling-delay-passive = <250>;
2614			polling-delay = <1000>;
2615
2616			thermal-sensors = <&tsens0 2>;
2617
2618			trips {
2619				cpu-crit {
2620					temperature = <110000>;
2621					hysteresis = <1000>;
2622					type = "critical";
2623				};
2624			};
2625		};
2626
2627		cpu2-thermal {
2628			polling-delay-passive = <250>;
2629			polling-delay = <1000>;
2630
2631			thermal-sensors = <&tsens0 3>;
2632
2633			trips {
2634				cpu-crit {
2635					temperature = <110000>;
2636					hysteresis = <1000>;
2637					type = "critical";
2638				};
2639			};
2640		};
2641
2642		cpu3-thermal {
2643			polling-delay-passive = <250>;
2644			polling-delay = <1000>;
2645
2646			thermal-sensors = <&tsens0 4>;
2647
2648			trips {
2649				cpu-crit {
2650					temperature = <110000>;
2651					hysteresis = <1000>;
2652					type = "critical";
2653				};
2654			};
2655		};
2656
2657		cpu4-thermal {
2658			polling-delay-passive = <250>;
2659			polling-delay = <1000>;
2660
2661			thermal-sensors = <&tsens0 5>;
2662
2663			trips {
2664				cpu-crit {
2665					temperature = <110000>;
2666					hysteresis = <1000>;
2667					type = "critical";
2668				};
2669			};
2670		};
2671
2672		cpu5-thermal {
2673			polling-delay-passive = <250>;
2674			polling-delay = <1000>;
2675
2676			thermal-sensors = <&tsens0 6>;
2677
2678			trips {
2679				cpu-crit {
2680					temperature = <110000>;
2681					hysteresis = <1000>;
2682					type = "critical";
2683				};
2684			};
2685		};
2686
2687		cpu6-thermal {
2688			polling-delay-passive = <250>;
2689			polling-delay = <1000>;
2690
2691			thermal-sensors = <&tsens0 7>;
2692
2693			trips {
2694				cpu-crit {
2695					temperature = <110000>;
2696					hysteresis = <1000>;
2697					type = "critical";
2698				};
2699			};
2700		};
2701
2702		cpu7-thermal {
2703			polling-delay-passive = <250>;
2704			polling-delay = <1000>;
2705
2706			thermal-sensors = <&tsens0 8>;
2707
2708			trips {
2709				cpu-crit {
2710					temperature = <110000>;
2711					hysteresis = <1000>;
2712					type = "critical";
2713				};
2714			};
2715		};
2716
2717		cluster0-thermal {
2718			polling-delay-passive = <250>;
2719			polling-delay = <1000>;
2720
2721			thermal-sensors = <&tsens0 9>;
2722
2723			trips {
2724				cpu-crit {
2725					temperature = <110000>;
2726					hysteresis = <1000>;
2727					type = "critical";
2728				};
2729			};
2730		};
2731
2732		mem-thermal {
2733			polling-delay-passive = <250>;
2734			polling-delay = <1000>;
2735
2736			thermal-sensors = <&tsens1 15>;
2737
2738			trips {
2739				trip-point0 {
2740					temperature = <90000>;
2741					hysteresis = <2000>;
2742					type = "hot";
2743				};
2744			};
2745		};
2746	};
2747
2748	timer {
2749		compatible = "arm,armv8-timer";
2750		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
2751			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
2752			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
2753			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
2754	};
2755};
2756