1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2021, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2022, Linaro Limited 5 */ 6 7#include <dt-bindings/clock/qcom,dispcc-sc8280xp.h> 8#include <dt-bindings/clock/qcom,gcc-sc8280xp.h> 9#include <dt-bindings/clock/qcom,rpmh.h> 10#include <dt-bindings/interconnect/qcom,osm-l3.h> 11#include <dt-bindings/interconnect/qcom,sc8280xp.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/mailbox/qcom-ipcc.h> 14#include <dt-bindings/phy/phy-qcom-qmp.h> 15#include <dt-bindings/power/qcom-rpmpd.h> 16#include <dt-bindings/soc/qcom,gpr.h> 17#include <dt-bindings/soc/qcom,rpmh-rsc.h> 18#include <dt-bindings/sound/qcom,q6afe.h> 19#include <dt-bindings/thermal/thermal.h> 20 21/ { 22 interrupt-parent = <&intc>; 23 24 #address-cells = <2>; 25 #size-cells = <2>; 26 27 clocks { 28 xo_board_clk: xo-board-clk { 29 compatible = "fixed-clock"; 30 #clock-cells = <0>; 31 }; 32 33 sleep_clk: sleep-clk { 34 compatible = "fixed-clock"; 35 #clock-cells = <0>; 36 clock-frequency = <32764>; 37 }; 38 }; 39 40 cpus { 41 #address-cells = <2>; 42 #size-cells = <0>; 43 44 CPU0: cpu@0 { 45 device_type = "cpu"; 46 compatible = "qcom,kryo"; 47 reg = <0x0 0x0>; 48 enable-method = "psci"; 49 capacity-dmips-mhz = <602>; 50 next-level-cache = <&L2_0>; 51 power-domains = <&CPU_PD0>; 52 power-domain-names = "psci"; 53 qcom,freq-domain = <&cpufreq_hw 0>; 54 operating-points-v2 = <&cpu0_opp_table>; 55 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 56 #cooling-cells = <2>; 57 L2_0: l2-cache { 58 compatible = "cache"; 59 cache-level = <2>; 60 next-level-cache = <&L3_0>; 61 L3_0: l3-cache { 62 compatible = "cache"; 63 cache-level = <3>; 64 }; 65 }; 66 }; 67 68 CPU1: cpu@100 { 69 device_type = "cpu"; 70 compatible = "qcom,kryo"; 71 reg = <0x0 0x100>; 72 enable-method = "psci"; 73 capacity-dmips-mhz = <602>; 74 next-level-cache = <&L2_100>; 75 power-domains = <&CPU_PD1>; 76 power-domain-names = "psci"; 77 qcom,freq-domain = <&cpufreq_hw 0>; 78 operating-points-v2 = <&cpu0_opp_table>; 79 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 80 #cooling-cells = <2>; 81 L2_100: l2-cache { 82 compatible = "cache"; 83 cache-level = <2>; 84 next-level-cache = <&L3_0>; 85 }; 86 }; 87 88 CPU2: cpu@200 { 89 device_type = "cpu"; 90 compatible = "qcom,kryo"; 91 reg = <0x0 0x200>; 92 enable-method = "psci"; 93 capacity-dmips-mhz = <602>; 94 next-level-cache = <&L2_200>; 95 power-domains = <&CPU_PD2>; 96 power-domain-names = "psci"; 97 qcom,freq-domain = <&cpufreq_hw 0>; 98 operating-points-v2 = <&cpu0_opp_table>; 99 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 100 #cooling-cells = <2>; 101 L2_200: l2-cache { 102 compatible = "cache"; 103 cache-level = <2>; 104 next-level-cache = <&L3_0>; 105 }; 106 }; 107 108 CPU3: cpu@300 { 109 device_type = "cpu"; 110 compatible = "qcom,kryo"; 111 reg = <0x0 0x300>; 112 enable-method = "psci"; 113 capacity-dmips-mhz = <602>; 114 next-level-cache = <&L2_300>; 115 power-domains = <&CPU_PD3>; 116 power-domain-names = "psci"; 117 qcom,freq-domain = <&cpufreq_hw 0>; 118 operating-points-v2 = <&cpu0_opp_table>; 119 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 120 #cooling-cells = <2>; 121 L2_300: l2-cache { 122 compatible = "cache"; 123 cache-level = <2>; 124 next-level-cache = <&L3_0>; 125 }; 126 }; 127 128 CPU4: cpu@400 { 129 device_type = "cpu"; 130 compatible = "qcom,kryo"; 131 reg = <0x0 0x400>; 132 enable-method = "psci"; 133 capacity-dmips-mhz = <1024>; 134 next-level-cache = <&L2_400>; 135 power-domains = <&CPU_PD4>; 136 power-domain-names = "psci"; 137 qcom,freq-domain = <&cpufreq_hw 1>; 138 operating-points-v2 = <&cpu4_opp_table>; 139 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 140 #cooling-cells = <2>; 141 L2_400: l2-cache { 142 compatible = "cache"; 143 cache-level = <2>; 144 next-level-cache = <&L3_0>; 145 }; 146 }; 147 148 CPU5: cpu@500 { 149 device_type = "cpu"; 150 compatible = "qcom,kryo"; 151 reg = <0x0 0x500>; 152 enable-method = "psci"; 153 capacity-dmips-mhz = <1024>; 154 next-level-cache = <&L2_500>; 155 power-domains = <&CPU_PD5>; 156 power-domain-names = "psci"; 157 qcom,freq-domain = <&cpufreq_hw 1>; 158 operating-points-v2 = <&cpu4_opp_table>; 159 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 160 #cooling-cells = <2>; 161 L2_500: l2-cache { 162 compatible = "cache"; 163 cache-level = <2>; 164 next-level-cache = <&L3_0>; 165 }; 166 }; 167 168 CPU6: cpu@600 { 169 device_type = "cpu"; 170 compatible = "qcom,kryo"; 171 reg = <0x0 0x600>; 172 enable-method = "psci"; 173 capacity-dmips-mhz = <1024>; 174 next-level-cache = <&L2_600>; 175 power-domains = <&CPU_PD6>; 176 power-domain-names = "psci"; 177 qcom,freq-domain = <&cpufreq_hw 1>; 178 operating-points-v2 = <&cpu4_opp_table>; 179 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 180 #cooling-cells = <2>; 181 L2_600: l2-cache { 182 compatible = "cache"; 183 cache-level = <2>; 184 next-level-cache = <&L3_0>; 185 }; 186 }; 187 188 CPU7: cpu@700 { 189 device_type = "cpu"; 190 compatible = "qcom,kryo"; 191 reg = <0x0 0x700>; 192 enable-method = "psci"; 193 capacity-dmips-mhz = <1024>; 194 next-level-cache = <&L2_700>; 195 power-domains = <&CPU_PD7>; 196 power-domain-names = "psci"; 197 qcom,freq-domain = <&cpufreq_hw 1>; 198 operating-points-v2 = <&cpu4_opp_table>; 199 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 200 #cooling-cells = <2>; 201 L2_700: l2-cache { 202 compatible = "cache"; 203 cache-level = <2>; 204 next-level-cache = <&L3_0>; 205 }; 206 }; 207 208 cpu-map { 209 cluster0 { 210 core0 { 211 cpu = <&CPU0>; 212 }; 213 214 core1 { 215 cpu = <&CPU1>; 216 }; 217 218 core2 { 219 cpu = <&CPU2>; 220 }; 221 222 core3 { 223 cpu = <&CPU3>; 224 }; 225 226 core4 { 227 cpu = <&CPU4>; 228 }; 229 230 core5 { 231 cpu = <&CPU5>; 232 }; 233 234 core6 { 235 cpu = <&CPU6>; 236 }; 237 238 core7 { 239 cpu = <&CPU7>; 240 }; 241 }; 242 }; 243 244 idle-states { 245 entry-method = "psci"; 246 247 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 248 compatible = "arm,idle-state"; 249 idle-state-name = "little-rail-power-collapse"; 250 arm,psci-suspend-param = <0x40000004>; 251 entry-latency-us = <355>; 252 exit-latency-us = <909>; 253 min-residency-us = <3934>; 254 local-timer-stop; 255 }; 256 257 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 258 compatible = "arm,idle-state"; 259 idle-state-name = "big-rail-power-collapse"; 260 arm,psci-suspend-param = <0x40000004>; 261 entry-latency-us = <241>; 262 exit-latency-us = <1461>; 263 min-residency-us = <4488>; 264 local-timer-stop; 265 }; 266 }; 267 268 domain-idle-states { 269 CLUSTER_SLEEP_0: cluster-sleep-0 { 270 compatible = "domain-idle-state"; 271 idle-state-name = "cluster-power-collapse"; 272 arm,psci-suspend-param = <0x4100c344>; 273 entry-latency-us = <3263>; 274 exit-latency-us = <6562>; 275 min-residency-us = <9987>; 276 }; 277 }; 278 }; 279 280 firmware { 281 scm: scm { 282 compatible = "qcom,scm-sc8280xp", "qcom,scm"; 283 }; 284 }; 285 286 aggre1_noc: interconnect-aggre1-noc { 287 compatible = "qcom,sc8280xp-aggre1-noc"; 288 #interconnect-cells = <2>; 289 qcom,bcm-voters = <&apps_bcm_voter>; 290 }; 291 292 aggre2_noc: interconnect-aggre2-noc { 293 compatible = "qcom,sc8280xp-aggre2-noc"; 294 #interconnect-cells = <2>; 295 qcom,bcm-voters = <&apps_bcm_voter>; 296 }; 297 298 clk_virt: interconnect-clk-virt { 299 compatible = "qcom,sc8280xp-clk-virt"; 300 #interconnect-cells = <2>; 301 qcom,bcm-voters = <&apps_bcm_voter>; 302 }; 303 304 config_noc: interconnect-config-noc { 305 compatible = "qcom,sc8280xp-config-noc"; 306 #interconnect-cells = <2>; 307 qcom,bcm-voters = <&apps_bcm_voter>; 308 }; 309 310 dc_noc: interconnect-dc-noc { 311 compatible = "qcom,sc8280xp-dc-noc"; 312 #interconnect-cells = <2>; 313 qcom,bcm-voters = <&apps_bcm_voter>; 314 }; 315 316 gem_noc: interconnect-gem-noc { 317 compatible = "qcom,sc8280xp-gem-noc"; 318 #interconnect-cells = <2>; 319 qcom,bcm-voters = <&apps_bcm_voter>; 320 }; 321 322 lpass_noc: interconnect-lpass-ag-noc { 323 compatible = "qcom,sc8280xp-lpass-ag-noc"; 324 #interconnect-cells = <2>; 325 qcom,bcm-voters = <&apps_bcm_voter>; 326 }; 327 328 mc_virt: interconnect-mc-virt { 329 compatible = "qcom,sc8280xp-mc-virt"; 330 #interconnect-cells = <2>; 331 qcom,bcm-voters = <&apps_bcm_voter>; 332 }; 333 334 mmss_noc: interconnect-mmss-noc { 335 compatible = "qcom,sc8280xp-mmss-noc"; 336 #interconnect-cells = <2>; 337 qcom,bcm-voters = <&apps_bcm_voter>; 338 }; 339 340 nspa_noc: interconnect-nspa-noc { 341 compatible = "qcom,sc8280xp-nspa-noc"; 342 #interconnect-cells = <2>; 343 qcom,bcm-voters = <&apps_bcm_voter>; 344 }; 345 346 nspb_noc: interconnect-nspb-noc { 347 compatible = "qcom,sc8280xp-nspb-noc"; 348 #interconnect-cells = <2>; 349 qcom,bcm-voters = <&apps_bcm_voter>; 350 }; 351 352 system_noc: interconnect-system-noc { 353 compatible = "qcom,sc8280xp-system-noc"; 354 #interconnect-cells = <2>; 355 qcom,bcm-voters = <&apps_bcm_voter>; 356 }; 357 358 memory@80000000 { 359 device_type = "memory"; 360 /* We expect the bootloader to fill in the size */ 361 reg = <0x0 0x80000000 0x0 0x0>; 362 }; 363 364 cpu0_opp_table: opp-table-cpu0 { 365 compatible = "operating-points-v2"; 366 opp-shared; 367 368 opp-300000000 { 369 opp-hz = /bits/ 64 <300000000>; 370 opp-peak-kBps = <(300000 * 32)>; 371 }; 372 opp-403200000 { 373 opp-hz = /bits/ 64 <403200000>; 374 opp-peak-kBps = <(384000 * 32)>; 375 }; 376 opp-499200000 { 377 opp-hz = /bits/ 64 <499200000>; 378 opp-peak-kBps = <(480000 * 32)>; 379 }; 380 opp-595200000 { 381 opp-hz = /bits/ 64 <595200000>; 382 opp-peak-kBps = <(576000 * 32)>; 383 }; 384 opp-691200000 { 385 opp-hz = /bits/ 64 <691200000>; 386 opp-peak-kBps = <(672000 * 32)>; 387 }; 388 opp-806400000 { 389 opp-hz = /bits/ 64 <806400000>; 390 opp-peak-kBps = <(768000 * 32)>; 391 }; 392 opp-902400000 { 393 opp-hz = /bits/ 64 <902400000>; 394 opp-peak-kBps = <(864000 * 32)>; 395 }; 396 opp-1017600000 { 397 opp-hz = /bits/ 64 <1017600000>; 398 opp-peak-kBps = <(960000 * 32)>; 399 }; 400 opp-1113600000 { 401 opp-hz = /bits/ 64 <1113600000>; 402 opp-peak-kBps = <(1075200 * 32)>; 403 }; 404 opp-1209600000 { 405 opp-hz = /bits/ 64 <1209600000>; 406 opp-peak-kBps = <(1171200 * 32)>; 407 }; 408 opp-1324800000 { 409 opp-hz = /bits/ 64 <1324800000>; 410 opp-peak-kBps = <(1267200 * 32)>; 411 }; 412 opp-1440000000 { 413 opp-hz = /bits/ 64 <1440000000>; 414 opp-peak-kBps = <(1363200 * 32)>; 415 }; 416 opp-1555200000 { 417 opp-hz = /bits/ 64 <1555200000>; 418 opp-peak-kBps = <(1536000 * 32)>; 419 }; 420 opp-1670400000 { 421 opp-hz = /bits/ 64 <1670400000>; 422 opp-peak-kBps = <(1612800 * 32)>; 423 }; 424 opp-1785600000 { 425 opp-hz = /bits/ 64 <1785600000>; 426 opp-peak-kBps = <(1689600 * 32)>; 427 }; 428 opp-1881600000 { 429 opp-hz = /bits/ 64 <1881600000>; 430 opp-peak-kBps = <(1689600 * 32)>; 431 }; 432 opp-1996800000 { 433 opp-hz = /bits/ 64 <1996800000>; 434 opp-peak-kBps = <(1689600 * 32)>; 435 }; 436 opp-2112000000 { 437 opp-hz = /bits/ 64 <2112000000>; 438 opp-peak-kBps = <(1689600 * 32)>; 439 }; 440 opp-2227200000 { 441 opp-hz = /bits/ 64 <2227200000>; 442 opp-peak-kBps = <(1689600 * 32)>; 443 }; 444 opp-2342400000 { 445 opp-hz = /bits/ 64 <2342400000>; 446 opp-peak-kBps = <(1689600 * 32)>; 447 }; 448 opp-2438400000 { 449 opp-hz = /bits/ 64 <2438400000>; 450 opp-peak-kBps = <(1689600 * 32)>; 451 }; 452 }; 453 454 cpu4_opp_table: opp-table-cpu4 { 455 compatible = "operating-points-v2"; 456 opp-shared; 457 458 opp-825600000 { 459 opp-hz = /bits/ 64 <825600000>; 460 opp-peak-kBps = <(768000 * 32)>; 461 }; 462 opp-940800000 { 463 opp-hz = /bits/ 64 <940800000>; 464 opp-peak-kBps = <(864000 * 32)>; 465 }; 466 opp-1056000000 { 467 opp-hz = /bits/ 64 <1056000000>; 468 opp-peak-kBps = <(960000 * 32)>; 469 }; 470 opp-1171200000 { 471 opp-hz = /bits/ 64 <1171200000>; 472 opp-peak-kBps = <(1171200 * 32)>; 473 }; 474 opp-1286400000 { 475 opp-hz = /bits/ 64 <1286400000>; 476 opp-peak-kBps = <(1267200 * 32)>; 477 }; 478 opp-1401600000 { 479 opp-hz = /bits/ 64 <1401600000>; 480 opp-peak-kBps = <(1363200 * 32)>; 481 }; 482 opp-1516800000 { 483 opp-hz = /bits/ 64 <1516800000>; 484 opp-peak-kBps = <(1459200 * 32)>; 485 }; 486 opp-1632000000 { 487 opp-hz = /bits/ 64 <1632000000>; 488 opp-peak-kBps = <(1612800 * 32)>; 489 }; 490 opp-1747200000 { 491 opp-hz = /bits/ 64 <1747200000>; 492 opp-peak-kBps = <(1689600 * 32)>; 493 }; 494 opp-1862400000 { 495 opp-hz = /bits/ 64 <1862400000>; 496 opp-peak-kBps = <(1689600 * 32)>; 497 }; 498 opp-1977600000 { 499 opp-hz = /bits/ 64 <1977600000>; 500 opp-peak-kBps = <(1689600 * 32)>; 501 }; 502 opp-2073600000 { 503 opp-hz = /bits/ 64 <2073600000>; 504 opp-peak-kBps = <(1689600 * 32)>; 505 }; 506 opp-2169600000 { 507 opp-hz = /bits/ 64 <2169600000>; 508 opp-peak-kBps = <(1689600 * 32)>; 509 }; 510 opp-2284800000 { 511 opp-hz = /bits/ 64 <2284800000>; 512 opp-peak-kBps = <(1689600 * 32)>; 513 }; 514 opp-2400000000 { 515 opp-hz = /bits/ 64 <2400000000>; 516 opp-peak-kBps = <(1689600 * 32)>; 517 }; 518 opp-2496000000 { 519 opp-hz = /bits/ 64 <2496000000>; 520 opp-peak-kBps = <(1689600 * 32)>; 521 }; 522 opp-2592000000 { 523 opp-hz = /bits/ 64 <2592000000>; 524 opp-peak-kBps = <(1689600 * 32)>; 525 }; 526 opp-2688000000 { 527 opp-hz = /bits/ 64 <2688000000>; 528 opp-peak-kBps = <(1689600 * 32)>; 529 }; 530 opp-2803200000 { 531 opp-hz = /bits/ 64 <2803200000>; 532 opp-peak-kBps = <(1689600 * 32)>; 533 }; 534 opp-2899200000 { 535 opp-hz = /bits/ 64 <2899200000>; 536 opp-peak-kBps = <(1689600 * 32)>; 537 }; 538 opp-2995200000 { 539 opp-hz = /bits/ 64 <2995200000>; 540 opp-peak-kBps = <(1689600 * 32)>; 541 }; 542 }; 543 544 qup_opp_table_100mhz: opp-table-qup100mhz { 545 compatible = "operating-points-v2"; 546 547 opp-75000000 { 548 opp-hz = /bits/ 64 <75000000>; 549 required-opps = <&rpmhpd_opp_low_svs>; 550 }; 551 552 opp-100000000 { 553 opp-hz = /bits/ 64 <100000000>; 554 required-opps = <&rpmhpd_opp_svs>; 555 }; 556 }; 557 558 pmu { 559 compatible = "arm,armv8-pmuv3"; 560 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 561 }; 562 563 psci { 564 compatible = "arm,psci-1.0"; 565 method = "smc"; 566 567 CPU_PD0: power-domain-cpu0 { 568 #power-domain-cells = <0>; 569 power-domains = <&CLUSTER_PD>; 570 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 571 }; 572 573 CPU_PD1: power-domain-cpu1 { 574 #power-domain-cells = <0>; 575 power-domains = <&CLUSTER_PD>; 576 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 577 }; 578 579 CPU_PD2: power-domain-cpu2 { 580 #power-domain-cells = <0>; 581 power-domains = <&CLUSTER_PD>; 582 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 583 }; 584 585 CPU_PD3: power-domain-cpu3 { 586 #power-domain-cells = <0>; 587 power-domains = <&CLUSTER_PD>; 588 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 589 }; 590 591 CPU_PD4: power-domain-cpu4 { 592 #power-domain-cells = <0>; 593 power-domains = <&CLUSTER_PD>; 594 domain-idle-states = <&BIG_CPU_SLEEP_0>; 595 }; 596 597 CPU_PD5: power-domain-cpu5 { 598 #power-domain-cells = <0>; 599 power-domains = <&CLUSTER_PD>; 600 domain-idle-states = <&BIG_CPU_SLEEP_0>; 601 }; 602 603 CPU_PD6: power-domain-cpu6 { 604 #power-domain-cells = <0>; 605 power-domains = <&CLUSTER_PD>; 606 domain-idle-states = <&BIG_CPU_SLEEP_0>; 607 }; 608 609 CPU_PD7: power-domain-cpu7 { 610 #power-domain-cells = <0>; 611 power-domains = <&CLUSTER_PD>; 612 domain-idle-states = <&BIG_CPU_SLEEP_0>; 613 }; 614 615 CLUSTER_PD: power-domain-cpu-cluster0 { 616 #power-domain-cells = <0>; 617 domain-idle-states = <&CLUSTER_SLEEP_0>; 618 }; 619 }; 620 621 reserved-memory { 622 #address-cells = <2>; 623 #size-cells = <2>; 624 ranges; 625 626 reserved-region@80000000 { 627 reg = <0 0x80000000 0 0x860000>; 628 no-map; 629 }; 630 631 cmd_db: cmd-db-region@80860000 { 632 compatible = "qcom,cmd-db"; 633 reg = <0 0x80860000 0 0x20000>; 634 no-map; 635 }; 636 637 reserved-region@80880000 { 638 reg = <0 0x80880000 0 0x80000>; 639 no-map; 640 }; 641 642 smem_mem: smem-region@80900000 { 643 compatible = "qcom,smem"; 644 reg = <0 0x80900000 0 0x200000>; 645 no-map; 646 hwlocks = <&tcsr_mutex 3>; 647 }; 648 649 reserved-region@80b00000 { 650 reg = <0 0x80b00000 0 0x100000>; 651 no-map; 652 }; 653 654 reserved-region@83b00000 { 655 reg = <0 0x83b00000 0 0x1700000>; 656 no-map; 657 }; 658 659 reserved-region@85b00000 { 660 reg = <0 0x85b00000 0 0xc00000>; 661 no-map; 662 }; 663 664 pil_adsp_mem: adsp-region@86c00000 { 665 reg = <0 0x86c00000 0 0x2000000>; 666 no-map; 667 }; 668 669 pil_nsp0_mem: cdsp0-region@8a100000 { 670 reg = <0 0x8a100000 0 0x1e00000>; 671 no-map; 672 }; 673 674 pil_nsp1_mem: cdsp1-region@8c600000 { 675 reg = <0 0x8c600000 0 0x1e00000>; 676 no-map; 677 }; 678 679 reserved-region@aeb00000 { 680 reg = <0 0xaeb00000 0 0x16600000>; 681 no-map; 682 }; 683 }; 684 685 smp2p-adsp { 686 compatible = "qcom,smp2p"; 687 qcom,smem = <443>, <429>; 688 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 689 IPCC_MPROC_SIGNAL_SMP2P 690 IRQ_TYPE_EDGE_RISING>; 691 mboxes = <&ipcc IPCC_CLIENT_LPASS 692 IPCC_MPROC_SIGNAL_SMP2P>; 693 694 qcom,local-pid = <0>; 695 qcom,remote-pid = <2>; 696 697 smp2p_adsp_out: master-kernel { 698 qcom,entry-name = "master-kernel"; 699 #qcom,smem-state-cells = <1>; 700 }; 701 702 smp2p_adsp_in: slave-kernel { 703 qcom,entry-name = "slave-kernel"; 704 interrupt-controller; 705 #interrupt-cells = <2>; 706 }; 707 }; 708 709 smp2p-nsp0 { 710 compatible = "qcom,smp2p"; 711 qcom,smem = <94>, <432>; 712 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 713 IPCC_MPROC_SIGNAL_SMP2P 714 IRQ_TYPE_EDGE_RISING>; 715 mboxes = <&ipcc IPCC_CLIENT_CDSP 716 IPCC_MPROC_SIGNAL_SMP2P>; 717 718 qcom,local-pid = <0>; 719 qcom,remote-pid = <5>; 720 721 smp2p_nsp0_out: master-kernel { 722 qcom,entry-name = "master-kernel"; 723 #qcom,smem-state-cells = <1>; 724 }; 725 726 smp2p_nsp0_in: slave-kernel { 727 qcom,entry-name = "slave-kernel"; 728 interrupt-controller; 729 #interrupt-cells = <2>; 730 }; 731 }; 732 733 smp2p-nsp1 { 734 compatible = "qcom,smp2p"; 735 qcom,smem = <617>, <616>; 736 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1 737 IPCC_MPROC_SIGNAL_SMP2P 738 IRQ_TYPE_EDGE_RISING>; 739 mboxes = <&ipcc IPCC_CLIENT_NSP1 740 IPCC_MPROC_SIGNAL_SMP2P>; 741 742 qcom,local-pid = <0>; 743 qcom,remote-pid = <12>; 744 745 smp2p_nsp1_out: master-kernel { 746 qcom,entry-name = "master-kernel"; 747 #qcom,smem-state-cells = <1>; 748 }; 749 750 smp2p_nsp1_in: slave-kernel { 751 qcom,entry-name = "slave-kernel"; 752 interrupt-controller; 753 #interrupt-cells = <2>; 754 }; 755 }; 756 757 soc: soc@0 { 758 compatible = "simple-bus"; 759 #address-cells = <2>; 760 #size-cells = <2>; 761 ranges = <0 0 0 0 0x10 0>; 762 dma-ranges = <0 0 0 0 0x10 0>; 763 764 gcc: clock-controller@100000 { 765 compatible = "qcom,gcc-sc8280xp"; 766 reg = <0x0 0x00100000 0x0 0x1f0000>; 767 #clock-cells = <1>; 768 #reset-cells = <1>; 769 #power-domain-cells = <1>; 770 clocks = <&rpmhcc RPMH_CXO_CLK>, 771 <&sleep_clk>, 772 <0>, 773 <0>, 774 <0>, 775 <0>, 776 <0>, 777 <0>, 778 <&usb_0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 779 <0>, 780 <0>, 781 <0>, 782 <0>, 783 <0>, 784 <0>, 785 <0>, 786 <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 787 <0>, 788 <0>, 789 <0>, 790 <0>, 791 <0>, 792 <0>, 793 <0>, 794 <0>, 795 <0>, 796 <&pcie2a_phy>, 797 <&pcie2b_phy>, 798 <&pcie3a_phy>, 799 <&pcie3b_phy>, 800 <&pcie4_phy>, 801 <0>, 802 <0>; 803 power-domains = <&rpmhpd SC8280XP_CX>; 804 }; 805 806 ipcc: mailbox@408000 { 807 compatible = "qcom,sc8280xp-ipcc", "qcom,ipcc"; 808 reg = <0 0x00408000 0 0x1000>; 809 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 810 interrupt-controller; 811 #interrupt-cells = <3>; 812 #mbox-cells = <2>; 813 }; 814 815 qup2: geniqup@8c0000 { 816 compatible = "qcom,geni-se-qup"; 817 reg = <0 0x008c0000 0 0x2000>; 818 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 819 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 820 clock-names = "m-ahb", "s-ahb"; 821 iommus = <&apps_smmu 0xa3 0>; 822 823 #address-cells = <2>; 824 #size-cells = <2>; 825 ranges; 826 827 status = "disabled"; 828 829 i2c16: i2c@880000 { 830 compatible = "qcom,geni-i2c"; 831 reg = <0 0x00880000 0 0x4000>; 832 #address-cells = <1>; 833 #size-cells = <0>; 834 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 835 clock-names = "se"; 836 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 837 power-domains = <&rpmhpd SC8280XP_CX>; 838 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 839 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 840 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 841 interconnect-names = "qup-core", "qup-config", "qup-memory"; 842 status = "disabled"; 843 }; 844 845 spi16: spi@880000 { 846 compatible = "qcom,geni-spi"; 847 reg = <0 0x00880000 0 0x4000>; 848 #address-cells = <1>; 849 #size-cells = <0>; 850 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 851 clock-names = "se"; 852 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 853 power-domains = <&rpmhpd SC8280XP_CX>; 854 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 855 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 856 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 857 interconnect-names = "qup-core", "qup-config", "qup-memory"; 858 status = "disabled"; 859 }; 860 861 i2c17: i2c@884000 { 862 compatible = "qcom,geni-i2c"; 863 reg = <0 0x00884000 0 0x4000>; 864 #address-cells = <1>; 865 #size-cells = <0>; 866 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 867 clock-names = "se"; 868 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 869 power-domains = <&rpmhpd SC8280XP_CX>; 870 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 871 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 872 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 873 interconnect-names = "qup-core", "qup-config", "qup-memory"; 874 status = "disabled"; 875 }; 876 877 spi17: spi@884000 { 878 compatible = "qcom,geni-spi"; 879 reg = <0 0x00884000 0 0x4000>; 880 #address-cells = <1>; 881 #size-cells = <0>; 882 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 883 clock-names = "se"; 884 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 885 power-domains = <&rpmhpd SC8280XP_CX>; 886 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 887 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 888 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 889 interconnect-names = "qup-core", "qup-config", "qup-memory"; 890 status = "disabled"; 891 }; 892 893 uart17: serial@884000 { 894 compatible = "qcom,geni-uart"; 895 reg = <0 0x00884000 0 0x4000>; 896 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 897 clock-names = "se"; 898 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 899 operating-points-v2 = <&qup_opp_table_100mhz>; 900 power-domains = <&rpmhpd SC8280XP_CX>; 901 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 902 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>; 903 interconnect-names = "qup-core", "qup-config"; 904 status = "disabled"; 905 }; 906 907 i2c18: i2c@888000 { 908 compatible = "qcom,geni-i2c"; 909 reg = <0 0x00888000 0 0x4000>; 910 #address-cells = <1>; 911 #size-cells = <0>; 912 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 913 clock-names = "se"; 914 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 915 power-domains = <&rpmhpd SC8280XP_CX>; 916 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 917 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 918 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 919 interconnect-names = "qup-core", "qup-config", "qup-memory"; 920 status = "disabled"; 921 }; 922 923 spi18: spi@888000 { 924 compatible = "qcom,geni-spi"; 925 reg = <0 0x00888000 0 0x4000>; 926 #address-cells = <1>; 927 #size-cells = <0>; 928 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 929 clock-names = "se"; 930 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 931 power-domains = <&rpmhpd SC8280XP_CX>; 932 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 933 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 934 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 935 interconnect-names = "qup-core", "qup-config", "qup-memory"; 936 status = "disabled"; 937 }; 938 939 i2c19: i2c@88c000 { 940 compatible = "qcom,geni-i2c"; 941 reg = <0 0x0088c000 0 0x4000>; 942 #address-cells = <1>; 943 #size-cells = <0>; 944 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 945 clock-names = "se"; 946 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 947 power-domains = <&rpmhpd SC8280XP_CX>; 948 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 949 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 950 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 951 interconnect-names = "qup-core", "qup-config", "qup-memory"; 952 status = "disabled"; 953 }; 954 955 spi19: spi@88c000 { 956 compatible = "qcom,geni-spi"; 957 reg = <0 0x0088c000 0 0x4000>; 958 #address-cells = <1>; 959 #size-cells = <0>; 960 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 961 clock-names = "se"; 962 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 963 power-domains = <&rpmhpd SC8280XP_CX>; 964 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 965 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 966 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 967 interconnect-names = "qup-core", "qup-config", "qup-memory"; 968 status = "disabled"; 969 }; 970 971 i2c20: i2c@890000 { 972 compatible = "qcom,geni-i2c"; 973 reg = <0 0x00890000 0 0x4000>; 974 #address-cells = <1>; 975 #size-cells = <0>; 976 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 977 clock-names = "se"; 978 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 979 power-domains = <&rpmhpd SC8280XP_CX>; 980 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 981 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 982 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 983 interconnect-names = "qup-core", "qup-config", "qup-memory"; 984 status = "disabled"; 985 }; 986 987 spi20: spi@890000 { 988 compatible = "qcom,geni-spi"; 989 reg = <0 0x00890000 0 0x4000>; 990 #address-cells = <1>; 991 #size-cells = <0>; 992 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 993 clock-names = "se"; 994 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 995 power-domains = <&rpmhpd SC8280XP_CX>; 996 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 997 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 998 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 999 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1000 status = "disabled"; 1001 }; 1002 1003 i2c21: i2c@894000 { 1004 compatible = "qcom,geni-i2c"; 1005 reg = <0 0x00894000 0 0x4000>; 1006 clock-names = "se"; 1007 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1008 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1009 #address-cells = <1>; 1010 #size-cells = <0>; 1011 power-domains = <&rpmhpd SC8280XP_CX>; 1012 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1013 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1014 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1015 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1016 status = "disabled"; 1017 }; 1018 1019 spi21: spi@894000 { 1020 compatible = "qcom,geni-spi"; 1021 reg = <0 0x00894000 0 0x4000>; 1022 #address-cells = <1>; 1023 #size-cells = <0>; 1024 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1025 clock-names = "se"; 1026 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1027 power-domains = <&rpmhpd SC8280XP_CX>; 1028 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1029 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1030 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1031 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1032 status = "disabled"; 1033 }; 1034 1035 i2c22: i2c@898000 { 1036 compatible = "qcom,geni-i2c"; 1037 reg = <0 0x00898000 0 0x4000>; 1038 #address-cells = <1>; 1039 #size-cells = <0>; 1040 clock-names = "se"; 1041 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1042 interrupts = <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>; 1043 power-domains = <&rpmhpd SC8280XP_CX>; 1044 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1045 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1046 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1047 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1048 status = "disabled"; 1049 }; 1050 1051 spi22: spi@898000 { 1052 compatible = "qcom,geni-spi"; 1053 reg = <0 0x00898000 0 0x4000>; 1054 #address-cells = <1>; 1055 #size-cells = <0>; 1056 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1057 clock-names = "se"; 1058 interrupts = <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>; 1059 power-domains = <&rpmhpd SC8280XP_CX>; 1060 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1061 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1062 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1063 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1064 status = "disabled"; 1065 }; 1066 1067 i2c23: i2c@89c000 { 1068 compatible = "qcom,geni-i2c"; 1069 reg = <0 0x0089c000 0 0x4000>; 1070 #address-cells = <1>; 1071 #size-cells = <0>; 1072 clock-names = "se"; 1073 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1074 interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>; 1075 power-domains = <&rpmhpd SC8280XP_CX>; 1076 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1077 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1078 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1079 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1080 status = "disabled"; 1081 }; 1082 1083 spi23: spi@89c000 { 1084 compatible = "qcom,geni-spi"; 1085 reg = <0 0x0089c000 0 0x4000>; 1086 #address-cells = <1>; 1087 #size-cells = <0>; 1088 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1089 clock-names = "se"; 1090 interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>; 1091 power-domains = <&rpmhpd SC8280XP_CX>; 1092 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1093 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1094 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1095 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1096 status = "disabled"; 1097 }; 1098 }; 1099 1100 qup0: geniqup@9c0000 { 1101 compatible = "qcom,geni-se-qup"; 1102 reg = <0 0x009c0000 0 0x6000>; 1103 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1104 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1105 clock-names = "m-ahb", "s-ahb"; 1106 iommus = <&apps_smmu 0x563 0>; 1107 1108 #address-cells = <2>; 1109 #size-cells = <2>; 1110 ranges; 1111 1112 status = "disabled"; 1113 1114 i2c0: i2c@980000 { 1115 compatible = "qcom,geni-i2c"; 1116 reg = <0 0x00980000 0 0x4000>; 1117 #address-cells = <1>; 1118 #size-cells = <0>; 1119 clock-names = "se"; 1120 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1121 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1122 power-domains = <&rpmhpd SC8280XP_CX>; 1123 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1124 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1125 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1126 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1127 status = "disabled"; 1128 }; 1129 1130 spi0: spi@980000 { 1131 compatible = "qcom,geni-spi"; 1132 reg = <0 0x00980000 0 0x4000>; 1133 #address-cells = <1>; 1134 #size-cells = <0>; 1135 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1136 clock-names = "se"; 1137 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1138 power-domains = <&rpmhpd SC8280XP_CX>; 1139 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1140 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1141 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1142 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1143 status = "disabled"; 1144 }; 1145 1146 i2c1: i2c@984000 { 1147 compatible = "qcom,geni-i2c"; 1148 reg = <0 0x00984000 0 0x4000>; 1149 #address-cells = <1>; 1150 #size-cells = <0>; 1151 clock-names = "se"; 1152 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1153 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1154 power-domains = <&rpmhpd SC8280XP_CX>; 1155 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1156 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1157 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1158 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1159 status = "disabled"; 1160 }; 1161 1162 spi1: spi@984000 { 1163 compatible = "qcom,geni-spi"; 1164 reg = <0 0x00984000 0 0x4000>; 1165 #address-cells = <1>; 1166 #size-cells = <0>; 1167 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1168 clock-names = "se"; 1169 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1170 power-domains = <&rpmhpd SC8280XP_CX>; 1171 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1172 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1173 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1174 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1175 status = "disabled"; 1176 }; 1177 1178 i2c2: i2c@988000 { 1179 compatible = "qcom,geni-i2c"; 1180 reg = <0 0x00988000 0 0x4000>; 1181 #address-cells = <1>; 1182 #size-cells = <0>; 1183 clock-names = "se"; 1184 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1185 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1186 power-domains = <&rpmhpd SC8280XP_CX>; 1187 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1188 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1189 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1190 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1191 status = "disabled"; 1192 }; 1193 1194 spi2: spi@988000 { 1195 compatible = "qcom,geni-spi"; 1196 reg = <0 0x00988000 0 0x4000>; 1197 #address-cells = <1>; 1198 #size-cells = <0>; 1199 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1200 clock-names = "se"; 1201 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1202 power-domains = <&rpmhpd SC8280XP_CX>; 1203 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1204 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1205 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1206 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1207 status = "disabled"; 1208 }; 1209 1210 i2c3: i2c@98c000 { 1211 compatible = "qcom,geni-i2c"; 1212 reg = <0 0x0098c000 0 0x4000>; 1213 #address-cells = <1>; 1214 #size-cells = <0>; 1215 clock-names = "se"; 1216 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1217 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1218 power-domains = <&rpmhpd SC8280XP_CX>; 1219 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1220 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1221 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1222 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1223 status = "disabled"; 1224 }; 1225 1226 spi3: spi@98c000 { 1227 compatible = "qcom,geni-spi"; 1228 reg = <0 0x0098c000 0 0x4000>; 1229 #address-cells = <1>; 1230 #size-cells = <0>; 1231 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1232 clock-names = "se"; 1233 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1234 power-domains = <&rpmhpd SC8280XP_CX>; 1235 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1236 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1237 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1238 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1239 status = "disabled"; 1240 }; 1241 1242 i2c4: i2c@990000 { 1243 compatible = "qcom,geni-i2c"; 1244 reg = <0 0x00990000 0 0x4000>; 1245 clock-names = "se"; 1246 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1247 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1248 #address-cells = <1>; 1249 #size-cells = <0>; 1250 power-domains = <&rpmhpd SC8280XP_CX>; 1251 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1252 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1253 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1254 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1255 status = "disabled"; 1256 }; 1257 1258 spi4: spi@990000 { 1259 compatible = "qcom,geni-spi"; 1260 reg = <0 0x00990000 0 0x4000>; 1261 #address-cells = <1>; 1262 #size-cells = <0>; 1263 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1264 clock-names = "se"; 1265 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1266 power-domains = <&rpmhpd SC8280XP_CX>; 1267 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1268 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1269 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1270 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1271 status = "disabled"; 1272 }; 1273 1274 i2c5: i2c@994000 { 1275 compatible = "qcom,geni-i2c"; 1276 reg = <0 0x00994000 0 0x4000>; 1277 #address-cells = <1>; 1278 #size-cells = <0>; 1279 clock-names = "se"; 1280 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1281 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1282 power-domains = <&rpmhpd SC8280XP_CX>; 1283 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1284 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1285 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1286 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1287 status = "disabled"; 1288 }; 1289 1290 spi5: spi@994000 { 1291 compatible = "qcom,geni-spi"; 1292 reg = <0 0x00994000 0 0x4000>; 1293 #address-cells = <1>; 1294 #size-cells = <0>; 1295 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1296 clock-names = "se"; 1297 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1298 power-domains = <&rpmhpd SC8280XP_CX>; 1299 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1300 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1301 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1302 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1303 status = "disabled"; 1304 }; 1305 1306 i2c6: i2c@998000 { 1307 compatible = "qcom,geni-i2c"; 1308 reg = <0 0x00998000 0 0x4000>; 1309 #address-cells = <1>; 1310 #size-cells = <0>; 1311 clock-names = "se"; 1312 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1313 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1314 power-domains = <&rpmhpd SC8280XP_CX>; 1315 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1316 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1317 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1318 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1319 status = "disabled"; 1320 }; 1321 1322 spi6: spi@998000 { 1323 compatible = "qcom,geni-spi"; 1324 reg = <0 0x00998000 0 0x4000>; 1325 #address-cells = <1>; 1326 #size-cells = <0>; 1327 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1328 clock-names = "se"; 1329 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1330 power-domains = <&rpmhpd SC8280XP_CX>; 1331 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1332 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1333 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1334 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1335 status = "disabled"; 1336 }; 1337 1338 i2c7: i2c@99c000 { 1339 compatible = "qcom,geni-i2c"; 1340 reg = <0 0x0099c000 0 0x4000>; 1341 #address-cells = <1>; 1342 #size-cells = <0>; 1343 clock-names = "se"; 1344 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1345 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1346 power-domains = <&rpmhpd SC8280XP_CX>; 1347 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1348 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1349 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1350 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1351 status = "disabled"; 1352 }; 1353 1354 spi7: spi@99c000 { 1355 compatible = "qcom,geni-spi"; 1356 reg = <0 0x0099c000 0 0x4000>; 1357 #address-cells = <1>; 1358 #size-cells = <0>; 1359 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1360 clock-names = "se"; 1361 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1362 power-domains = <&rpmhpd SC8280XP_CX>; 1363 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1364 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1365 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1366 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1367 status = "disabled"; 1368 }; 1369 }; 1370 1371 qup1: geniqup@ac0000 { 1372 compatible = "qcom,geni-se-qup"; 1373 reg = <0 0x00ac0000 0 0x6000>; 1374 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1375 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1376 clock-names = "m-ahb", "s-ahb"; 1377 iommus = <&apps_smmu 0x83 0>; 1378 1379 #address-cells = <2>; 1380 #size-cells = <2>; 1381 ranges; 1382 1383 status = "disabled"; 1384 1385 i2c8: i2c@a80000 { 1386 compatible = "qcom,geni-i2c"; 1387 reg = <0 0x00a80000 0 0x4000>; 1388 #address-cells = <1>; 1389 #size-cells = <0>; 1390 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1391 clock-names = "se"; 1392 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1393 power-domains = <&rpmhpd SC8280XP_CX>; 1394 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1395 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1396 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1397 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1398 status = "disabled"; 1399 }; 1400 1401 spi8: spi@a80000 { 1402 compatible = "qcom,geni-spi"; 1403 reg = <0 0x00a80000 0 0x4000>; 1404 #address-cells = <1>; 1405 #size-cells = <0>; 1406 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1407 clock-names = "se"; 1408 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1409 power-domains = <&rpmhpd SC8280XP_CX>; 1410 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1411 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1412 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1413 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1414 status = "disabled"; 1415 }; 1416 1417 i2c9: i2c@a84000 { 1418 compatible = "qcom,geni-i2c"; 1419 reg = <0 0x00a84000 0 0x4000>; 1420 #address-cells = <1>; 1421 #size-cells = <0>; 1422 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1423 clock-names = "se"; 1424 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1425 power-domains = <&rpmhpd SC8280XP_CX>; 1426 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1427 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1428 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1429 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1430 status = "disabled"; 1431 }; 1432 1433 spi9: spi@a84000 { 1434 compatible = "qcom,geni-spi"; 1435 reg = <0 0x00a84000 0 0x4000>; 1436 #address-cells = <1>; 1437 #size-cells = <0>; 1438 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1439 clock-names = "se"; 1440 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1441 power-domains = <&rpmhpd SC8280XP_CX>; 1442 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1443 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1444 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1445 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1446 status = "disabled"; 1447 }; 1448 1449 i2c10: i2c@a88000 { 1450 compatible = "qcom,geni-i2c"; 1451 reg = <0 0x00a88000 0 0x4000>; 1452 #address-cells = <1>; 1453 #size-cells = <0>; 1454 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1455 clock-names = "se"; 1456 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1457 power-domains = <&rpmhpd SC8280XP_CX>; 1458 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1459 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1460 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1461 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1462 status = "disabled"; 1463 }; 1464 1465 spi10: spi@a88000 { 1466 compatible = "qcom,geni-spi"; 1467 reg = <0 0x00a88000 0 0x4000>; 1468 #address-cells = <1>; 1469 #size-cells = <0>; 1470 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1471 clock-names = "se"; 1472 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1473 power-domains = <&rpmhpd SC8280XP_CX>; 1474 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1475 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1476 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1477 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1478 status = "disabled"; 1479 }; 1480 1481 i2c11: i2c@a8c000 { 1482 compatible = "qcom,geni-i2c"; 1483 reg = <0 0x00a8c000 0 0x4000>; 1484 #address-cells = <1>; 1485 #size-cells = <0>; 1486 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1487 clock-names = "se"; 1488 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1489 power-domains = <&rpmhpd SC8280XP_CX>; 1490 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1491 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1492 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1493 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1494 status = "disabled"; 1495 }; 1496 1497 spi11: spi@a8c000 { 1498 compatible = "qcom,geni-spi"; 1499 reg = <0 0x00a8c000 0 0x4000>; 1500 #address-cells = <1>; 1501 #size-cells = <0>; 1502 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1503 clock-names = "se"; 1504 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1505 power-domains = <&rpmhpd SC8280XP_CX>; 1506 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1507 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1508 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1509 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1510 status = "disabled"; 1511 }; 1512 1513 i2c12: i2c@a90000 { 1514 compatible = "qcom,geni-i2c"; 1515 reg = <0 0x00a90000 0 0x4000>; 1516 #address-cells = <1>; 1517 #size-cells = <0>; 1518 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1519 clock-names = "se"; 1520 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1521 power-domains = <&rpmhpd SC8280XP_CX>; 1522 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1523 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1524 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1525 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1526 status = "disabled"; 1527 }; 1528 1529 spi12: spi@a90000 { 1530 compatible = "qcom,geni-spi"; 1531 reg = <0 0x00a90000 0 0x4000>; 1532 #address-cells = <1>; 1533 #size-cells = <0>; 1534 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1535 clock-names = "se"; 1536 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1537 power-domains = <&rpmhpd SC8280XP_CX>; 1538 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1539 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1540 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1541 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1542 status = "disabled"; 1543 }; 1544 1545 i2c13: i2c@a94000 { 1546 compatible = "qcom,geni-i2c"; 1547 reg = <0 0x00a94000 0 0x4000>; 1548 #address-cells = <1>; 1549 #size-cells = <0>; 1550 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1551 clock-names = "se"; 1552 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1553 power-domains = <&rpmhpd SC8280XP_CX>; 1554 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1555 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1556 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1557 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1558 status = "disabled"; 1559 }; 1560 1561 spi13: spi@a94000 { 1562 compatible = "qcom,geni-spi"; 1563 reg = <0 0x00a94000 0 0x4000>; 1564 #address-cells = <1>; 1565 #size-cells = <0>; 1566 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1567 clock-names = "se"; 1568 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1569 power-domains = <&rpmhpd SC8280XP_CX>; 1570 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1571 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1572 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1573 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1574 status = "disabled"; 1575 }; 1576 1577 i2c14: i2c@a98000 { 1578 compatible = "qcom,geni-i2c"; 1579 reg = <0 0x00a98000 0 0x4000>; 1580 #address-cells = <1>; 1581 #size-cells = <0>; 1582 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1583 clock-names = "se"; 1584 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>; 1585 power-domains = <&rpmhpd SC8280XP_CX>; 1586 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1587 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1588 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1589 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1590 status = "disabled"; 1591 }; 1592 1593 spi14: spi@a98000 { 1594 compatible = "qcom,geni-spi"; 1595 reg = <0 0x00a98000 0 0x4000>; 1596 #address-cells = <1>; 1597 #size-cells = <0>; 1598 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1599 clock-names = "se"; 1600 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>; 1601 power-domains = <&rpmhpd SC8280XP_CX>; 1602 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1603 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1604 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1605 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1606 status = "disabled"; 1607 }; 1608 1609 i2c15: i2c@a9c000 { 1610 compatible = "qcom,geni-i2c"; 1611 reg = <0 0x00a9c000 0 0x4000>; 1612 #address-cells = <1>; 1613 #size-cells = <0>; 1614 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1615 clock-names = "se"; 1616 interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>; 1617 power-domains = <&rpmhpd SC8280XP_CX>; 1618 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1619 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1620 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1621 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1622 status = "disabled"; 1623 }; 1624 1625 spi15: spi@a9c000 { 1626 compatible = "qcom,geni-spi"; 1627 reg = <0 0x00a9c000 0 0x4000>; 1628 #address-cells = <1>; 1629 #size-cells = <0>; 1630 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1631 clock-names = "se"; 1632 interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>; 1633 power-domains = <&rpmhpd SC8280XP_CX>; 1634 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1635 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1636 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1637 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1638 status = "disabled"; 1639 }; 1640 }; 1641 1642 rng: rng@10d3000 { 1643 compatible = "qcom,prng-ee"; 1644 reg = <0 0x010d3000 0 0x1000>; 1645 clocks = <&rpmhcc RPMH_HWKM_CLK>; 1646 clock-names = "core"; 1647 }; 1648 1649 pcie4: pcie@1c00000 { 1650 device_type = "pci"; 1651 compatible = "qcom,pcie-sc8280xp"; 1652 reg = <0x0 0x01c00000 0x0 0x3000>, 1653 <0x0 0x30000000 0x0 0xf1d>, 1654 <0x0 0x30000f20 0x0 0xa8>, 1655 <0x0 0x30001000 0x0 0x1000>, 1656 <0x0 0x30100000 0x0 0x100000>; 1657 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1658 #address-cells = <3>; 1659 #size-cells = <2>; 1660 ranges = <0x01000000 0x0 0x30200000 0x0 0x30200000 0x0 0x100000>, 1661 <0x02000000 0x0 0x30300000 0x0 0x30300000 0x0 0x1d00000>; 1662 bus-range = <0x00 0xff>; 1663 1664 dma-coherent; 1665 1666 linux,pci-domain = <6>; 1667 num-lanes = <1>; 1668 1669 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 1670 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1671 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 1672 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 1673 interrupt-names = "msi0", "msi1", "msi2", "msi3"; 1674 1675 #interrupt-cells = <1>; 1676 interrupt-map-mask = <0 0 0 0x7>; 1677 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 1678 <0 0 0 2 &intc 0 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 1679 <0 0 0 3 &intc 0 0 GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 1680 <0 0 0 4 &intc 0 0 GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 1681 1682 clocks = <&gcc GCC_PCIE_4_AUX_CLK>, 1683 <&gcc GCC_PCIE_4_CFG_AHB_CLK>, 1684 <&gcc GCC_PCIE_4_MSTR_AXI_CLK>, 1685 <&gcc GCC_PCIE_4_SLV_AXI_CLK>, 1686 <&gcc GCC_PCIE_4_SLV_Q2A_AXI_CLK>, 1687 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 1688 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, 1689 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>, 1690 <&gcc GCC_CNOC_PCIE4_QX_CLK>; 1691 clock-names = "aux", 1692 "cfg", 1693 "bus_master", 1694 "bus_slave", 1695 "slave_q2a", 1696 "ddrss_sf_tbu", 1697 "noc_aggr_4", 1698 "noc_aggr_south_sf", 1699 "cnoc_qx"; 1700 1701 assigned-clocks = <&gcc GCC_PCIE_4_AUX_CLK>; 1702 assigned-clock-rates = <19200000>; 1703 1704 interconnects = <&aggre2_noc MASTER_PCIE_4 0 &mc_virt SLAVE_EBI1 0>, 1705 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_4 0>; 1706 interconnect-names = "pcie-mem", "cpu-pcie"; 1707 1708 resets = <&gcc GCC_PCIE_4_BCR>; 1709 reset-names = "pci"; 1710 1711 power-domains = <&gcc PCIE_4_GDSC>; 1712 1713 phys = <&pcie4_phy>; 1714 phy-names = "pciephy"; 1715 1716 status = "disabled"; 1717 }; 1718 1719 pcie4_phy: phy@1c06000 { 1720 compatible = "qcom,sc8280xp-qmp-gen3x1-pcie-phy"; 1721 reg = <0x0 0x01c06000 0x0 0x2000>; 1722 1723 clocks = <&gcc GCC_PCIE_4_AUX_CLK>, 1724 <&gcc GCC_PCIE_4_CFG_AHB_CLK>, 1725 <&gcc GCC_PCIE_4_CLKREF_CLK>, 1726 <&gcc GCC_PCIE4_PHY_RCHNG_CLK>, 1727 <&gcc GCC_PCIE_4_PIPE_CLK>, 1728 <&gcc GCC_PCIE_4_PIPEDIV2_CLK>; 1729 clock-names = "aux", "cfg_ahb", "ref", "rchng", 1730 "pipe", "pipediv2"; 1731 1732 assigned-clocks = <&gcc GCC_PCIE4_PHY_RCHNG_CLK>; 1733 assigned-clock-rates = <100000000>; 1734 1735 power-domains = <&gcc PCIE_4_GDSC>; 1736 1737 resets = <&gcc GCC_PCIE_4_PHY_BCR>; 1738 reset-names = "phy"; 1739 1740 #clock-cells = <0>; 1741 clock-output-names = "pcie_4_pipe_clk"; 1742 1743 #phy-cells = <0>; 1744 1745 status = "disabled"; 1746 }; 1747 1748 pcie3b: pcie@1c08000 { 1749 device_type = "pci"; 1750 compatible = "qcom,pcie-sc8280xp"; 1751 reg = <0x0 0x01c08000 0x0 0x3000>, 1752 <0x0 0x32000000 0x0 0xf1d>, 1753 <0x0 0x32000f20 0x0 0xa8>, 1754 <0x0 0x32001000 0x0 0x1000>, 1755 <0x0 0x32100000 0x0 0x100000>; 1756 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1757 #address-cells = <3>; 1758 #size-cells = <2>; 1759 ranges = <0x01000000 0x0 0x32200000 0x0 0x32200000 0x0 0x100000>, 1760 <0x02000000 0x0 0x32300000 0x0 0x32300000 0x0 0x1d00000>; 1761 bus-range = <0x00 0xff>; 1762 1763 dma-coherent; 1764 1765 linux,pci-domain = <5>; 1766 num-lanes = <2>; 1767 1768 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1769 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1770 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1771 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 1772 interrupt-names = "msi0", "msi1", "msi2", "msi3"; 1773 1774 #interrupt-cells = <1>; 1775 interrupt-map-mask = <0 0 0 0x7>; 1776 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 526 IRQ_TYPE_LEVEL_HIGH>, 1777 <0 0 0 2 &intc 0 0 GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>, 1778 <0 0 0 3 &intc 0 0 GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH>, 1779 <0 0 0 4 &intc 0 0 GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>; 1780 1781 clocks = <&gcc GCC_PCIE_3B_AUX_CLK>, 1782 <&gcc GCC_PCIE_3B_CFG_AHB_CLK>, 1783 <&gcc GCC_PCIE_3B_MSTR_AXI_CLK>, 1784 <&gcc GCC_PCIE_3B_SLV_AXI_CLK>, 1785 <&gcc GCC_PCIE_3B_SLV_Q2A_AXI_CLK>, 1786 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 1787 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, 1788 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>; 1789 clock-names = "aux", 1790 "cfg", 1791 "bus_master", 1792 "bus_slave", 1793 "slave_q2a", 1794 "ddrss_sf_tbu", 1795 "noc_aggr_4", 1796 "noc_aggr_south_sf"; 1797 1798 assigned-clocks = <&gcc GCC_PCIE_3B_AUX_CLK>; 1799 assigned-clock-rates = <19200000>; 1800 1801 interconnects = <&aggre2_noc MASTER_PCIE_3B 0 &mc_virt SLAVE_EBI1 0>, 1802 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_3B 0>; 1803 interconnect-names = "pcie-mem", "cpu-pcie"; 1804 1805 resets = <&gcc GCC_PCIE_3B_BCR>; 1806 reset-names = "pci"; 1807 1808 power-domains = <&gcc PCIE_3B_GDSC>; 1809 1810 phys = <&pcie3b_phy>; 1811 phy-names = "pciephy"; 1812 1813 status = "disabled"; 1814 }; 1815 1816 pcie3b_phy: phy@1c0e000 { 1817 compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy"; 1818 reg = <0x0 0x01c0e000 0x0 0x2000>; 1819 1820 clocks = <&gcc GCC_PCIE_3B_AUX_CLK>, 1821 <&gcc GCC_PCIE_3B_CFG_AHB_CLK>, 1822 <&gcc GCC_PCIE_3A3B_CLKREF_CLK>, 1823 <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>, 1824 <&gcc GCC_PCIE_3B_PIPE_CLK>, 1825 <&gcc GCC_PCIE_3B_PIPEDIV2_CLK>; 1826 clock-names = "aux", "cfg_ahb", "ref", "rchng", 1827 "pipe", "pipediv2"; 1828 1829 assigned-clocks = <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>; 1830 assigned-clock-rates = <100000000>; 1831 1832 power-domains = <&gcc PCIE_3B_GDSC>; 1833 1834 resets = <&gcc GCC_PCIE_3B_PHY_BCR>; 1835 reset-names = "phy"; 1836 1837 #clock-cells = <0>; 1838 clock-output-names = "pcie_3b_pipe_clk"; 1839 1840 #phy-cells = <0>; 1841 1842 status = "disabled"; 1843 }; 1844 1845 pcie3a: pcie@1c10000 { 1846 device_type = "pci"; 1847 compatible = "qcom,pcie-sc8280xp"; 1848 reg = <0x0 0x01c10000 0x0 0x3000>, 1849 <0x0 0x34000000 0x0 0xf1d>, 1850 <0x0 0x34000f20 0x0 0xa8>, 1851 <0x0 0x34001000 0x0 0x1000>, 1852 <0x0 0x34100000 0x0 0x100000>; 1853 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1854 #address-cells = <3>; 1855 #size-cells = <2>; 1856 ranges = <0x01000000 0x0 0x34200000 0x0 0x34200000 0x0 0x100000>, 1857 <0x02000000 0x0 0x34300000 0x0 0x34300000 0x0 0x1d00000>; 1858 bus-range = <0x00 0xff>; 1859 1860 dma-coherent; 1861 1862 linux,pci-domain = <4>; 1863 num-lanes = <4>; 1864 1865 interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 1866 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 1867 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 1868 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; 1869 interrupt-names = "msi0", "msi1", "msi2", "msi3"; 1870 1871 #interrupt-cells = <1>; 1872 interrupt-map-mask = <0 0 0 0x7>; 1873 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>, 1874 <0 0 0 2 &intc 0 0 GIC_SPI 542 IRQ_TYPE_LEVEL_HIGH>, 1875 <0 0 0 3 &intc 0 0 GIC_SPI 543 IRQ_TYPE_LEVEL_HIGH>, 1876 <0 0 0 4 &intc 0 0 GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>; 1877 1878 clocks = <&gcc GCC_PCIE_3A_AUX_CLK>, 1879 <&gcc GCC_PCIE_3A_CFG_AHB_CLK>, 1880 <&gcc GCC_PCIE_3A_MSTR_AXI_CLK>, 1881 <&gcc GCC_PCIE_3A_SLV_AXI_CLK>, 1882 <&gcc GCC_PCIE_3A_SLV_Q2A_AXI_CLK>, 1883 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 1884 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, 1885 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>; 1886 clock-names = "aux", 1887 "cfg", 1888 "bus_master", 1889 "bus_slave", 1890 "slave_q2a", 1891 "ddrss_sf_tbu", 1892 "noc_aggr_4", 1893 "noc_aggr_south_sf"; 1894 1895 assigned-clocks = <&gcc GCC_PCIE_3A_AUX_CLK>; 1896 assigned-clock-rates = <19200000>; 1897 1898 interconnects = <&aggre2_noc MASTER_PCIE_3A 0 &mc_virt SLAVE_EBI1 0>, 1899 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_3A 0>; 1900 interconnect-names = "pcie-mem", "cpu-pcie"; 1901 1902 resets = <&gcc GCC_PCIE_3A_BCR>; 1903 reset-names = "pci"; 1904 1905 power-domains = <&gcc PCIE_3A_GDSC>; 1906 1907 phys = <&pcie3a_phy>; 1908 phy-names = "pciephy"; 1909 1910 status = "disabled"; 1911 }; 1912 1913 pcie3a_phy: phy@1c14000 { 1914 compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy"; 1915 reg = <0x0 0x01c14000 0x0 0x2000>, 1916 <0x0 0x01c16000 0x0 0x2000>; 1917 1918 clocks = <&gcc GCC_PCIE_3A_AUX_CLK>, 1919 <&gcc GCC_PCIE_3A_CFG_AHB_CLK>, 1920 <&gcc GCC_PCIE_3A3B_CLKREF_CLK>, 1921 <&gcc GCC_PCIE3A_PHY_RCHNG_CLK>, 1922 <&gcc GCC_PCIE_3A_PIPE_CLK>, 1923 <&gcc GCC_PCIE_3A_PIPEDIV2_CLK>; 1924 clock-names = "aux", "cfg_ahb", "ref", "rchng", 1925 "pipe", "pipediv2"; 1926 1927 assigned-clocks = <&gcc GCC_PCIE3A_PHY_RCHNG_CLK>; 1928 assigned-clock-rates = <100000000>; 1929 1930 power-domains = <&gcc PCIE_3A_GDSC>; 1931 1932 resets = <&gcc GCC_PCIE_3A_PHY_BCR>; 1933 reset-names = "phy"; 1934 1935 qcom,4ln-config-sel = <&tcsr 0xa044 1>; 1936 1937 #clock-cells = <0>; 1938 clock-output-names = "pcie_3a_pipe_clk"; 1939 1940 #phy-cells = <0>; 1941 1942 status = "disabled"; 1943 }; 1944 1945 pcie2b: pcie@1c18000 { 1946 device_type = "pci"; 1947 compatible = "qcom,pcie-sc8280xp"; 1948 reg = <0x0 0x01c18000 0x0 0x3000>, 1949 <0x0 0x38000000 0x0 0xf1d>, 1950 <0x0 0x38000f20 0x0 0xa8>, 1951 <0x0 0x38001000 0x0 0x1000>, 1952 <0x0 0x38100000 0x0 0x100000>; 1953 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1954 #address-cells = <3>; 1955 #size-cells = <2>; 1956 ranges = <0x01000000 0x0 0x38200000 0x0 0x38200000 0x0 0x100000>, 1957 <0x02000000 0x0 0x38300000 0x0 0x38300000 0x0 0x1d00000>; 1958 bus-range = <0x00 0xff>; 1959 1960 dma-coherent; 1961 1962 linux,pci-domain = <3>; 1963 num-lanes = <2>; 1964 1965 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 1966 <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 1967 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 1968 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>; 1969 interrupt-names = "msi0", "msi1", "msi2", "msi3"; 1970 1971 #interrupt-cells = <1>; 1972 interrupt-map-mask = <0 0 0 0x7>; 1973 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, 1974 <0 0 0 2 &intc 0 0 GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, 1975 <0 0 0 3 &intc 0 0 GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, 1976 <0 0 0 4 &intc 0 0 GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>; 1977 1978 clocks = <&gcc GCC_PCIE_2B_AUX_CLK>, 1979 <&gcc GCC_PCIE_2B_CFG_AHB_CLK>, 1980 <&gcc GCC_PCIE_2B_MSTR_AXI_CLK>, 1981 <&gcc GCC_PCIE_2B_SLV_AXI_CLK>, 1982 <&gcc GCC_PCIE_2B_SLV_Q2A_AXI_CLK>, 1983 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 1984 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, 1985 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>; 1986 clock-names = "aux", 1987 "cfg", 1988 "bus_master", 1989 "bus_slave", 1990 "slave_q2a", 1991 "ddrss_sf_tbu", 1992 "noc_aggr_4", 1993 "noc_aggr_south_sf"; 1994 1995 assigned-clocks = <&gcc GCC_PCIE_2B_AUX_CLK>; 1996 assigned-clock-rates = <19200000>; 1997 1998 interconnects = <&aggre2_noc MASTER_PCIE_2B 0 &mc_virt SLAVE_EBI1 0>, 1999 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_2B 0>; 2000 interconnect-names = "pcie-mem", "cpu-pcie"; 2001 2002 resets = <&gcc GCC_PCIE_2B_BCR>; 2003 reset-names = "pci"; 2004 2005 power-domains = <&gcc PCIE_2B_GDSC>; 2006 2007 phys = <&pcie2b_phy>; 2008 phy-names = "pciephy"; 2009 2010 status = "disabled"; 2011 }; 2012 2013 pcie2b_phy: phy@1c1e000 { 2014 compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy"; 2015 reg = <0x0 0x01c1e000 0x0 0x2000>; 2016 2017 clocks = <&gcc GCC_PCIE_2B_AUX_CLK>, 2018 <&gcc GCC_PCIE_2B_CFG_AHB_CLK>, 2019 <&gcc GCC_PCIE_2A2B_CLKREF_CLK>, 2020 <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>, 2021 <&gcc GCC_PCIE_2B_PIPE_CLK>, 2022 <&gcc GCC_PCIE_2B_PIPEDIV2_CLK>; 2023 clock-names = "aux", "cfg_ahb", "ref", "rchng", 2024 "pipe", "pipediv2"; 2025 2026 assigned-clocks = <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>; 2027 assigned-clock-rates = <100000000>; 2028 2029 power-domains = <&gcc PCIE_2B_GDSC>; 2030 2031 resets = <&gcc GCC_PCIE_2B_PHY_BCR>; 2032 reset-names = "phy"; 2033 2034 #clock-cells = <0>; 2035 clock-output-names = "pcie_2b_pipe_clk"; 2036 2037 #phy-cells = <0>; 2038 2039 status = "disabled"; 2040 }; 2041 2042 pcie2a: pcie@1c20000 { 2043 device_type = "pci"; 2044 compatible = "qcom,pcie-sc8280xp"; 2045 reg = <0x0 0x01c20000 0x0 0x3000>, 2046 <0x0 0x3c000000 0x0 0xf1d>, 2047 <0x0 0x3c000f20 0x0 0xa8>, 2048 <0x0 0x3c001000 0x0 0x1000>, 2049 <0x0 0x3c100000 0x0 0x100000>; 2050 reg-names = "parf", "dbi", "elbi", "atu", "config"; 2051 #address-cells = <3>; 2052 #size-cells = <2>; 2053 ranges = <0x01000000 0x0 0x3c200000 0x0 0x3c200000 0x0 0x100000>, 2054 <0x02000000 0x0 0x3c300000 0x0 0x3c300000 0x0 0x1d00000>; 2055 bus-range = <0x00 0xff>; 2056 2057 dma-coherent; 2058 2059 linux,pci-domain = <2>; 2060 num-lanes = <4>; 2061 2062 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 2063 <GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH>, 2064 <GIC_SPI 524 IRQ_TYPE_LEVEL_HIGH>, 2065 <GIC_SPI 525 IRQ_TYPE_LEVEL_HIGH>; 2066 interrupt-names = "msi0", "msi1", "msi2", "msi3"; 2067 2068 #interrupt-cells = <1>; 2069 interrupt-map-mask = <0 0 0 0x7>; 2070 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>, 2071 <0 0 0 2 &intc 0 0 GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>, 2072 <0 0 0 3 &intc 0 0 GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>, 2073 <0 0 0 4 &intc 0 0 GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>; 2074 2075 clocks = <&gcc GCC_PCIE_2A_AUX_CLK>, 2076 <&gcc GCC_PCIE_2A_CFG_AHB_CLK>, 2077 <&gcc GCC_PCIE_2A_MSTR_AXI_CLK>, 2078 <&gcc GCC_PCIE_2A_SLV_AXI_CLK>, 2079 <&gcc GCC_PCIE_2A_SLV_Q2A_AXI_CLK>, 2080 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 2081 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, 2082 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>; 2083 clock-names = "aux", 2084 "cfg", 2085 "bus_master", 2086 "bus_slave", 2087 "slave_q2a", 2088 "ddrss_sf_tbu", 2089 "noc_aggr_4", 2090 "noc_aggr_south_sf"; 2091 2092 assigned-clocks = <&gcc GCC_PCIE_2A_AUX_CLK>; 2093 assigned-clock-rates = <19200000>; 2094 2095 interconnects = <&aggre2_noc MASTER_PCIE_2A 0 &mc_virt SLAVE_EBI1 0>, 2096 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_2A 0>; 2097 interconnect-names = "pcie-mem", "cpu-pcie"; 2098 2099 resets = <&gcc GCC_PCIE_2A_BCR>; 2100 reset-names = "pci"; 2101 2102 power-domains = <&gcc PCIE_2A_GDSC>; 2103 2104 phys = <&pcie2a_phy>; 2105 phy-names = "pciephy"; 2106 2107 status = "disabled"; 2108 }; 2109 2110 pcie2a_phy: phy@1c24000 { 2111 compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy"; 2112 reg = <0x0 0x01c24000 0x0 0x2000>, 2113 <0x0 0x01c26000 0x0 0x2000>; 2114 2115 clocks = <&gcc GCC_PCIE_2A_AUX_CLK>, 2116 <&gcc GCC_PCIE_2A_CFG_AHB_CLK>, 2117 <&gcc GCC_PCIE_2A2B_CLKREF_CLK>, 2118 <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>, 2119 <&gcc GCC_PCIE_2A_PIPE_CLK>, 2120 <&gcc GCC_PCIE_2A_PIPEDIV2_CLK>; 2121 clock-names = "aux", "cfg_ahb", "ref", "rchng", 2122 "pipe", "pipediv2"; 2123 2124 assigned-clocks = <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>; 2125 assigned-clock-rates = <100000000>; 2126 2127 power-domains = <&gcc PCIE_2A_GDSC>; 2128 2129 resets = <&gcc GCC_PCIE_2A_PHY_BCR>; 2130 reset-names = "phy"; 2131 2132 qcom,4ln-config-sel = <&tcsr 0xa044 0>; 2133 2134 #clock-cells = <0>; 2135 clock-output-names = "pcie_2a_pipe_clk"; 2136 2137 #phy-cells = <0>; 2138 2139 status = "disabled"; 2140 }; 2141 2142 ufs_mem_hc: ufs@1d84000 { 2143 compatible = "qcom,sc8280xp-ufshc", "qcom,ufshc", 2144 "jedec,ufs-2.0"; 2145 reg = <0 0x01d84000 0 0x3000>; 2146 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2147 phys = <&ufs_mem_phy>; 2148 phy-names = "ufsphy"; 2149 lanes-per-direction = <2>; 2150 #reset-cells = <1>; 2151 resets = <&gcc GCC_UFS_PHY_BCR>; 2152 reset-names = "rst"; 2153 2154 power-domains = <&gcc UFS_PHY_GDSC>; 2155 required-opps = <&rpmhpd_opp_nom>; 2156 2157 iommus = <&apps_smmu 0xe0 0x0>; 2158 dma-coherent; 2159 2160 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 2161 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2162 <&gcc GCC_UFS_PHY_AHB_CLK>, 2163 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2164 <&gcc GCC_UFS_REF_CLKREF_CLK>, 2165 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2166 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2167 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 2168 clock-names = "core_clk", 2169 "bus_aggr_clk", 2170 "iface_clk", 2171 "core_clk_unipro", 2172 "ref_clk", 2173 "tx_lane0_sync_clk", 2174 "rx_lane0_sync_clk", 2175 "rx_lane1_sync_clk"; 2176 freq-table-hz = <75000000 300000000>, 2177 <0 0>, 2178 <0 0>, 2179 <75000000 300000000>, 2180 <0 0>, 2181 <0 0>, 2182 <0 0>, 2183 <0 0>; 2184 status = "disabled"; 2185 }; 2186 2187 ufs_mem_phy: phy@1d87000 { 2188 compatible = "qcom,sc8280xp-qmp-ufs-phy"; 2189 reg = <0 0x01d87000 0 0x1000>; 2190 2191 clocks = <&gcc GCC_UFS_CARD_CLKREF_CLK>, 2192 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 2193 clock-names = "ref", "ref_aux"; 2194 2195 power-domains = <&gcc UFS_PHY_GDSC>; 2196 2197 resets = <&ufs_mem_hc 0>; 2198 reset-names = "ufsphy"; 2199 2200 #phy-cells = <0>; 2201 2202 status = "disabled"; 2203 }; 2204 2205 ufs_card_hc: ufs@1da4000 { 2206 compatible = "qcom,sc8280xp-ufshc", "qcom,ufshc", 2207 "jedec,ufs-2.0"; 2208 reg = <0 0x01da4000 0 0x3000>; 2209 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 2210 phys = <&ufs_card_phy>; 2211 phy-names = "ufsphy"; 2212 lanes-per-direction = <2>; 2213 #reset-cells = <1>; 2214 resets = <&gcc GCC_UFS_CARD_BCR>; 2215 reset-names = "rst"; 2216 2217 power-domains = <&gcc UFS_CARD_GDSC>; 2218 2219 iommus = <&apps_smmu 0x4a0 0x0>; 2220 dma-coherent; 2221 2222 clocks = <&gcc GCC_UFS_CARD_AXI_CLK>, 2223 <&gcc GCC_AGGRE_UFS_CARD_AXI_CLK>, 2224 <&gcc GCC_UFS_CARD_AHB_CLK>, 2225 <&gcc GCC_UFS_CARD_UNIPRO_CORE_CLK>, 2226 <&gcc GCC_UFS_REF_CLKREF_CLK>, 2227 <&gcc GCC_UFS_CARD_TX_SYMBOL_0_CLK>, 2228 <&gcc GCC_UFS_CARD_RX_SYMBOL_0_CLK>, 2229 <&gcc GCC_UFS_CARD_RX_SYMBOL_1_CLK>; 2230 clock-names = "core_clk", 2231 "bus_aggr_clk", 2232 "iface_clk", 2233 "core_clk_unipro", 2234 "ref_clk", 2235 "tx_lane0_sync_clk", 2236 "rx_lane0_sync_clk", 2237 "rx_lane1_sync_clk"; 2238 freq-table-hz = <75000000 300000000>, 2239 <0 0>, 2240 <0 0>, 2241 <75000000 300000000>, 2242 <0 0>, 2243 <0 0>, 2244 <0 0>, 2245 <0 0>; 2246 status = "disabled"; 2247 }; 2248 2249 ufs_card_phy: phy@1da7000 { 2250 compatible = "qcom,sc8280xp-qmp-ufs-phy"; 2251 reg = <0 0x01da7000 0 0x1000>; 2252 2253 clocks = <&gcc GCC_UFS_1_CARD_CLKREF_CLK>, 2254 <&gcc GCC_UFS_CARD_PHY_AUX_CLK>; 2255 clock-names = "ref", "ref_aux"; 2256 2257 power-domains = <&gcc UFS_CARD_GDSC>; 2258 2259 resets = <&ufs_card_hc 0>; 2260 reset-names = "ufsphy"; 2261 2262 #phy-cells = <0>; 2263 2264 status = "disabled"; 2265 }; 2266 2267 tcsr_mutex: hwlock@1f40000 { 2268 compatible = "qcom,tcsr-mutex"; 2269 reg = <0x0 0x01f40000 0x0 0x20000>; 2270 #hwlock-cells = <1>; 2271 }; 2272 2273 tcsr: syscon@1fc0000 { 2274 compatible = "qcom,sc8280xp-tcsr", "syscon"; 2275 reg = <0x0 0x01fc0000 0x0 0x30000>; 2276 }; 2277 2278 usb_0_hsphy: phy@88e5000 { 2279 compatible = "qcom,sc8280xp-usb-hs-phy", 2280 "qcom,usb-snps-hs-5nm-phy"; 2281 reg = <0 0x088e5000 0 0x400>; 2282 clocks = <&rpmhcc RPMH_CXO_CLK>; 2283 clock-names = "ref"; 2284 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2285 2286 #phy-cells = <0>; 2287 2288 status = "disabled"; 2289 }; 2290 2291 usb_2_hsphy0: phy@88e7000 { 2292 compatible = "qcom,sc8280xp-usb-hs-phy", 2293 "qcom,usb-snps-hs-5nm-phy"; 2294 reg = <0 0x088e7000 0 0x400>; 2295 clocks = <&gcc GCC_USB2_HS0_CLKREF_CLK>; 2296 clock-names = "ref"; 2297 resets = <&gcc GCC_QUSB2PHY_HS0_MP_BCR>; 2298 2299 #phy-cells = <0>; 2300 2301 status = "disabled"; 2302 }; 2303 2304 usb_2_hsphy1: phy@88e8000 { 2305 compatible = "qcom,sc8280xp-usb-hs-phy", 2306 "qcom,usb-snps-hs-5nm-phy"; 2307 reg = <0 0x088e8000 0 0x400>; 2308 clocks = <&gcc GCC_USB2_HS1_CLKREF_CLK>; 2309 clock-names = "ref"; 2310 resets = <&gcc GCC_QUSB2PHY_HS1_MP_BCR>; 2311 2312 #phy-cells = <0>; 2313 2314 status = "disabled"; 2315 }; 2316 2317 usb_2_hsphy2: phy@88e9000 { 2318 compatible = "qcom,sc8280xp-usb-hs-phy", 2319 "qcom,usb-snps-hs-5nm-phy"; 2320 reg = <0 0x088e9000 0 0x400>; 2321 clocks = <&gcc GCC_USB2_HS2_CLKREF_CLK>; 2322 clock-names = "ref"; 2323 resets = <&gcc GCC_QUSB2PHY_HS2_MP_BCR>; 2324 2325 #phy-cells = <0>; 2326 2327 status = "disabled"; 2328 }; 2329 2330 usb_2_hsphy3: phy@88ea000 { 2331 compatible = "qcom,sc8280xp-usb-hs-phy", 2332 "qcom,usb-snps-hs-5nm-phy"; 2333 reg = <0 0x088ea000 0 0x400>; 2334 clocks = <&gcc GCC_USB2_HS3_CLKREF_CLK>; 2335 clock-names = "ref"; 2336 resets = <&gcc GCC_QUSB2PHY_HS3_MP_BCR>; 2337 2338 #phy-cells = <0>; 2339 2340 status = "disabled"; 2341 }; 2342 2343 usb_2_qmpphy0: phy@88ef000 { 2344 compatible = "qcom,sc8280xp-qmp-usb3-uni-phy"; 2345 reg = <0 0x088ef000 0 0x2000>; 2346 2347 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, 2348 <&gcc GCC_USB3_MP0_CLKREF_CLK>, 2349 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, 2350 <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>; 2351 clock-names = "aux", "ref", "com_aux", "pipe"; 2352 2353 resets = <&gcc GCC_USB3_UNIPHY_MP0_BCR>, 2354 <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>; 2355 reset-names = "phy", "phy_phy"; 2356 2357 power-domains = <&gcc USB30_MP_GDSC>; 2358 2359 #clock-cells = <0>; 2360 clock-output-names = "usb2_phy0_pipe_clk"; 2361 2362 #phy-cells = <0>; 2363 2364 status = "disabled"; 2365 }; 2366 2367 usb_2_qmpphy1: phy@88f1000 { 2368 compatible = "qcom,sc8280xp-qmp-usb3-uni-phy"; 2369 reg = <0 0x088f1000 0 0x2000>; 2370 2371 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, 2372 <&gcc GCC_USB3_MP1_CLKREF_CLK>, 2373 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, 2374 <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>; 2375 clock-names = "aux", "ref", "com_aux", "pipe"; 2376 2377 resets = <&gcc GCC_USB3_UNIPHY_MP1_BCR>, 2378 <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>; 2379 reset-names = "phy", "phy_phy"; 2380 2381 power-domains = <&gcc USB30_MP_GDSC>; 2382 2383 #clock-cells = <0>; 2384 clock-output-names = "usb2_phy1_pipe_clk"; 2385 2386 #phy-cells = <0>; 2387 2388 status = "disabled"; 2389 }; 2390 2391 remoteproc_adsp: remoteproc@3000000 { 2392 compatible = "qcom,sc8280xp-adsp-pas"; 2393 reg = <0 0x03000000 0 0x100>; 2394 2395 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, 2396 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 2397 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 2398 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 2399 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>, 2400 <&smp2p_adsp_in 7 IRQ_TYPE_EDGE_RISING>; 2401 interrupt-names = "wdog", "fatal", "ready", 2402 "handover", "stop-ack", "shutdown-ack"; 2403 2404 clocks = <&rpmhcc RPMH_CXO_CLK>; 2405 clock-names = "xo"; 2406 2407 power-domains = <&rpmhpd SC8280XP_LCX>, 2408 <&rpmhpd SC8280XP_LMX>; 2409 power-domain-names = "lcx", "lmx"; 2410 2411 memory-region = <&pil_adsp_mem>; 2412 2413 qcom,qmp = <&aoss_qmp>; 2414 2415 qcom,smem-states = <&smp2p_adsp_out 0>; 2416 qcom,smem-state-names = "stop"; 2417 2418 status = "disabled"; 2419 2420 remoteproc_adsp_glink: glink-edge { 2421 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 2422 IPCC_MPROC_SIGNAL_GLINK_QMP 2423 IRQ_TYPE_EDGE_RISING>; 2424 mboxes = <&ipcc IPCC_CLIENT_LPASS 2425 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2426 2427 label = "lpass"; 2428 qcom,remote-pid = <2>; 2429 2430 gpr { 2431 compatible = "qcom,gpr"; 2432 qcom,glink-channels = "adsp_apps"; 2433 qcom,domain = <GPR_DOMAIN_ID_ADSP>; 2434 qcom,intents = <512 20>; 2435 #address-cells = <1>; 2436 #size-cells = <0>; 2437 2438 q6apm: service@1 { 2439 compatible = "qcom,q6apm"; 2440 reg = <GPR_APM_MODULE_IID>; 2441 #sound-dai-cells = <0>; 2442 qcom,protection-domain = "avs/audio", 2443 "msm/adsp/audio_pd"; 2444 q6apmdai: dais { 2445 compatible = "qcom,q6apm-dais"; 2446 iommus = <&apps_smmu 0x0c01 0x0>; 2447 }; 2448 2449 q6apmbedai: bedais { 2450 compatible = "qcom,q6apm-lpass-dais"; 2451 #sound-dai-cells = <1>; 2452 }; 2453 }; 2454 2455 q6prm: service@2 { 2456 compatible = "qcom,q6prm"; 2457 reg = <GPR_PRM_MODULE_IID>; 2458 qcom,protection-domain = "avs/audio", 2459 "msm/adsp/audio_pd"; 2460 q6prmcc: clock-controller { 2461 compatible = "qcom,q6prm-lpass-clocks"; 2462 #clock-cells = <2>; 2463 }; 2464 }; 2465 }; 2466 }; 2467 }; 2468 2469 rxmacro: rxmacro@3200000 { 2470 compatible = "qcom,sc8280xp-lpass-rx-macro"; 2471 reg = <0 0x03200000 0 0x1000>; 2472 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2473 <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2474 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2475 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2476 <&vamacro>; 2477 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2478 assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2479 <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2480 assigned-clock-rates = <19200000>, <19200000>; 2481 2482 clock-output-names = "mclk"; 2483 #clock-cells = <0>; 2484 #sound-dai-cells = <1>; 2485 2486 pinctrl-names = "default"; 2487 pinctrl-0 = <&rx_swr_default>; 2488 2489 status = "disabled"; 2490 }; 2491 2492 /* RX */ 2493 swr1: soundwire-controller@3210000 { 2494 compatible = "qcom,soundwire-v1.6.0"; 2495 reg = <0 0x03210000 0 0x2000>; 2496 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 2497 clocks = <&rxmacro>; 2498 clock-names = "iface"; 2499 label = "RX"; 2500 2501 qcom,din-ports = <0>; 2502 qcom,dout-ports = <5>; 2503 2504 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>; 2505 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0B 0x01 0x00>; 2506 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0B 0x00 0x00>; 2507 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0x00 0xff 0xff>; 2508 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0x0f 0xff 0xff>; 2509 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>; 2510 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff>; 2511 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; 2512 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 2513 2514 #sound-dai-cells = <1>; 2515 #address-cells = <2>; 2516 #size-cells = <0>; 2517 2518 status = "disabled"; 2519 }; 2520 2521 txmacro: txmacro@3220000 { 2522 compatible = "qcom,sc8280xp-lpass-tx-macro"; 2523 reg = <0 0x03220000 0 0x1000>; 2524 pinctrl-names = "default"; 2525 pinctrl-0 = <&tx_swr_default>; 2526 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2527 <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2528 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2529 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2530 <&vamacro>; 2531 2532 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2533 assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2534 <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2535 assigned-clock-rates = <19200000>, <19200000>; 2536 clock-output-names = "mclk"; 2537 2538 #clock-cells = <0>; 2539 #sound-dai-cells = <1>; 2540 2541 status = "disabled"; 2542 }; 2543 2544 wsamacro: codec@3240000 { 2545 compatible = "qcom,sc8280xp-lpass-wsa-macro"; 2546 reg = <0 0x03240000 0 0x1000>; 2547 clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2548 <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2549 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2550 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2551 <&vamacro>; 2552 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2553 assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2554 <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2555 assigned-clock-rates = <19200000>, <19200000>; 2556 2557 #clock-cells = <0>; 2558 clock-output-names = "mclk"; 2559 #sound-dai-cells = <1>; 2560 2561 pinctrl-names = "default"; 2562 pinctrl-0 = <&wsa_swr_default>; 2563 2564 status = "disabled"; 2565 }; 2566 2567 /* WSA */ 2568 swr0: soundwire-controller@3250000 { 2569 reg = <0 0x03250000 0 0x2000>; 2570 compatible = "qcom,soundwire-v1.6.0"; 2571 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 2572 clocks = <&wsamacro>; 2573 clock-names = "iface"; 2574 2575 qcom,din-ports = <2>; 2576 qcom,dout-ports = <6>; 2577 2578 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>; 2579 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>; 2580 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>; 2581 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2582 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2583 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2584 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>; 2585 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2586 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2587 2588 #sound-dai-cells = <1>; 2589 #address-cells = <2>; 2590 #size-cells = <0>; 2591 2592 status = "disabled"; 2593 }; 2594 2595 /* TX */ 2596 swr2: soundwire-controller@3330000 { 2597 compatible = "qcom,soundwire-v1.6.0"; 2598 reg = <0 0x03330000 0 0x2000>; 2599 interrupts-extended = <&intc GIC_SPI 959 IRQ_TYPE_LEVEL_HIGH>, 2600 <&intc GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>; 2601 interrupt-names = "core", "wake"; 2602 2603 clocks = <&txmacro>; 2604 clock-names = "iface"; 2605 label = "TX"; 2606 #sound-dai-cells = <1>; 2607 #address-cells = <2>; 2608 #size-cells = <0>; 2609 2610 qcom,din-ports = <4>; 2611 qcom,dout-ports = <0>; 2612 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>; 2613 qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02 0x00>; 2614 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>; 2615 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>; 2616 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>; 2617 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>; 2618 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>; 2619 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>; 2620 qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00 0x01>; 2621 2622 status = "disabled"; 2623 }; 2624 2625 vamacro: codec@3370000 { 2626 compatible = "qcom,sc8280xp-lpass-va-macro"; 2627 reg = <0 0x03370000 0 0x1000>; 2628 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2629 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2630 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2631 <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2632 clock-names = "mclk", "macro", "dcodec", "npl"; 2633 assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2634 assigned-clock-rates = <19200000>; 2635 2636 #clock-cells = <0>; 2637 clock-output-names = "fsgen"; 2638 #sound-dai-cells = <1>; 2639 2640 status = "disabled"; 2641 }; 2642 2643 lpass_tlmm: pinctrl@33c0000 { 2644 compatible = "qcom,sc8280xp-lpass-lpi-pinctrl"; 2645 reg = <0 0x33c0000 0x0 0x20000>, 2646 <0 0x3550000 0x0 0x10000>; 2647 gpio-controller; 2648 #gpio-cells = <2>; 2649 gpio-ranges = <&lpass_tlmm 0 0 19>; 2650 2651 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2652 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2653 clock-names = "core", "audio"; 2654 2655 status = "disabled"; 2656 2657 tx_swr_default: tx-swr-default-state { 2658 clk-pins { 2659 pins = "gpio0"; 2660 function = "swr_tx_clk"; 2661 drive-strength = <2>; 2662 slew-rate = <1>; 2663 bias-disable; 2664 }; 2665 2666 data-pins { 2667 pins = "gpio1", "gpio2"; 2668 function = "swr_tx_data"; 2669 drive-strength = <2>; 2670 slew-rate = <1>; 2671 bias-bus-hold; 2672 }; 2673 }; 2674 2675 rx_swr_default: rx-swr-default-state { 2676 clk-pins { 2677 pins = "gpio3"; 2678 function = "swr_rx_clk"; 2679 drive-strength = <2>; 2680 slew-rate = <1>; 2681 bias-disable; 2682 }; 2683 2684 data-pins { 2685 pins = "gpio4", "gpio5"; 2686 function = "swr_rx_data"; 2687 drive-strength = <2>; 2688 slew-rate = <1>; 2689 bias-bus-hold; 2690 }; 2691 }; 2692 2693 dmic01_default: dmic01-default-state { 2694 clk-pins { 2695 pins = "gpio6"; 2696 function = "dmic1_clk"; 2697 drive-strength = <8>; 2698 output-high; 2699 }; 2700 2701 data-pins { 2702 pins = "gpio7"; 2703 function = "dmic1_data"; 2704 drive-strength = <8>; 2705 input-enable; 2706 }; 2707 }; 2708 2709 dmic01_sleep: dmic01-sleep-state { 2710 clk-pins { 2711 pins = "gpio6"; 2712 function = "dmic1_clk"; 2713 drive-strength = <2>; 2714 bias-disable; 2715 output-low; 2716 }; 2717 2718 data-pins { 2719 pins = "gpio7"; 2720 function = "dmic1_data"; 2721 drive-strength = <2>; 2722 bias-pull-down; 2723 input-enable; 2724 }; 2725 }; 2726 2727 dmic02_default: dmic02-default-state { 2728 clk-pins { 2729 pins = "gpio8"; 2730 function = "dmic2_clk"; 2731 drive-strength = <8>; 2732 output-high; 2733 }; 2734 2735 data-pins { 2736 pins = "gpio9"; 2737 function = "dmic2_data"; 2738 drive-strength = <8>; 2739 input-enable; 2740 }; 2741 }; 2742 2743 dmic02_sleep: dmic02-sleep-state { 2744 clk-pins { 2745 pins = "gpio8"; 2746 function = "dmic2_clk"; 2747 drive-strength = <2>; 2748 bias-disable; 2749 output-low; 2750 }; 2751 2752 data-pins { 2753 pins = "gpio9"; 2754 function = "dmic2_data"; 2755 drive-strength = <2>; 2756 bias-pull-down; 2757 input-enable; 2758 }; 2759 }; 2760 2761 wsa_swr_default: wsa-swr-default-state { 2762 clk-pins { 2763 pins = "gpio10"; 2764 function = "wsa_swr_clk"; 2765 drive-strength = <2>; 2766 slew-rate = <1>; 2767 bias-disable; 2768 }; 2769 2770 data-pins { 2771 pins = "gpio11"; 2772 function = "wsa_swr_data"; 2773 drive-strength = <2>; 2774 slew-rate = <1>; 2775 bias-bus-hold; 2776 2777 }; 2778 }; 2779 2780 wsa2_swr_default: wsa2-swr-default-state { 2781 clk-pins { 2782 pins = "gpio15"; 2783 function = "wsa2_swr_clk"; 2784 drive-strength = <2>; 2785 slew-rate = <1>; 2786 bias-disable; 2787 }; 2788 2789 data-pins { 2790 pins = "gpio16"; 2791 function = "wsa2_swr_data"; 2792 drive-strength = <2>; 2793 slew-rate = <1>; 2794 bias-bus-hold; 2795 }; 2796 }; 2797 }; 2798 2799 usb_0_qmpphy: phy@88eb000 { 2800 compatible = "qcom,sc8280xp-qmp-usb43dp-phy"; 2801 reg = <0 0x088eb000 0 0x4000>; 2802 2803 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2804 <&gcc GCC_USB4_EUD_CLKREF_CLK>, 2805 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 2806 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2807 clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 2808 2809 power-domains = <&gcc USB30_PRIM_GDSC>; 2810 2811 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 2812 <&gcc GCC_USB4_DP_PHY_PRIM_BCR>; 2813 reset-names = "phy", "common"; 2814 2815 #clock-cells = <1>; 2816 #phy-cells = <1>; 2817 2818 status = "disabled"; 2819 }; 2820 2821 usb_1_hsphy: phy@8902000 { 2822 compatible = "qcom,sc8280xp-usb-hs-phy", 2823 "qcom,usb-snps-hs-5nm-phy"; 2824 reg = <0 0x08902000 0 0x400>; 2825 #phy-cells = <0>; 2826 2827 clocks = <&rpmhcc RPMH_CXO_CLK>; 2828 clock-names = "ref"; 2829 2830 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 2831 2832 status = "disabled"; 2833 }; 2834 2835 usb_1_qmpphy: phy@8903000 { 2836 compatible = "qcom,sc8280xp-qmp-usb43dp-phy"; 2837 reg = <0 0x08903000 0 0x4000>; 2838 2839 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 2840 <&gcc GCC_USB4_CLKREF_CLK>, 2841 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, 2842 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 2843 clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 2844 2845 power-domains = <&gcc USB30_SEC_GDSC>; 2846 2847 resets = <&gcc GCC_USB3_PHY_SEC_BCR>, 2848 <&gcc GCC_USB4_1_DP_PHY_PRIM_BCR>; 2849 reset-names = "phy", "common"; 2850 2851 #clock-cells = <1>; 2852 #phy-cells = <1>; 2853 2854 status = "disabled"; 2855 }; 2856 2857 mdss1_dp0_phy: phy@8909a00 { 2858 compatible = "qcom,sc8280xp-dp-phy"; 2859 reg = <0 0x08909a00 0 0x19c>, 2860 <0 0x08909200 0 0xec>, 2861 <0 0x08909600 0 0xec>, 2862 <0 0x08909000 0 0x1c8>; 2863 2864 clocks = <&dispcc1 DISP_CC_MDSS_DPTX0_AUX_CLK>, 2865 <&dispcc1 DISP_CC_MDSS_AHB_CLK>; 2866 clock-names = "aux", "cfg_ahb"; 2867 power-domains = <&rpmhpd SC8280XP_MX>; 2868 2869 #clock-cells = <1>; 2870 #phy-cells = <0>; 2871 2872 status = "disabled"; 2873 }; 2874 2875 mdss1_dp1_phy: phy@890ca00 { 2876 compatible = "qcom,sc8280xp-dp-phy"; 2877 reg = <0 0x0890ca00 0 0x19c>, 2878 <0 0x0890c200 0 0xec>, 2879 <0 0x0890c600 0 0xec>, 2880 <0 0x0890c000 0 0x1c8>; 2881 2882 clocks = <&dispcc1 DISP_CC_MDSS_DPTX1_AUX_CLK>, 2883 <&dispcc1 DISP_CC_MDSS_AHB_CLK>; 2884 clock-names = "aux", "cfg_ahb"; 2885 power-domains = <&rpmhpd SC8280XP_MX>; 2886 2887 #clock-cells = <1>; 2888 #phy-cells = <0>; 2889 2890 status = "disabled"; 2891 }; 2892 2893 pmu@9091000 { 2894 compatible = "qcom,sc8280xp-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; 2895 reg = <0 0x09091000 0 0x1000>; 2896 2897 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 2898 2899 interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>; 2900 2901 operating-points-v2 = <&llcc_bwmon_opp_table>; 2902 2903 llcc_bwmon_opp_table: opp-table { 2904 compatible = "operating-points-v2"; 2905 2906 opp-0 { 2907 opp-peak-kBps = <762000>; 2908 }; 2909 opp-1 { 2910 opp-peak-kBps = <1720000>; 2911 }; 2912 opp-2 { 2913 opp-peak-kBps = <2086000>; 2914 }; 2915 opp-3 { 2916 opp-peak-kBps = <2597000>; 2917 }; 2918 opp-4 { 2919 opp-peak-kBps = <2929000>; 2920 }; 2921 opp-5 { 2922 opp-peak-kBps = <3879000>; 2923 }; 2924 opp-6 { 2925 opp-peak-kBps = <5161000>; 2926 }; 2927 opp-7 { 2928 opp-peak-kBps = <5931000>; 2929 }; 2930 opp-8 { 2931 opp-peak-kBps = <6515000>; 2932 }; 2933 opp-9 { 2934 opp-peak-kBps = <7980000>; 2935 }; 2936 opp-10 { 2937 opp-peak-kBps = <8136000>; 2938 }; 2939 opp-11 { 2940 opp-peak-kBps = <10437000>; 2941 }; 2942 opp-12 { 2943 opp-peak-kBps = <12191000>; 2944 }; 2945 }; 2946 }; 2947 2948 pmu@90b6400 { 2949 compatible = "qcom,sc8280xp-cpu-bwmon", "qcom,msm8998-bwmon"; 2950 reg = <0 0x090b6400 0 0x600>; 2951 2952 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 2953 2954 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>; 2955 operating-points-v2 = <&cpu_bwmon_opp_table>; 2956 2957 cpu_bwmon_opp_table: opp-table { 2958 compatible = "operating-points-v2"; 2959 2960 opp-0 { 2961 opp-peak-kBps = <2288000>; 2962 }; 2963 opp-1 { 2964 opp-peak-kBps = <4577000>; 2965 }; 2966 opp-2 { 2967 opp-peak-kBps = <7110000>; 2968 }; 2969 opp-3 { 2970 opp-peak-kBps = <9155000>; 2971 }; 2972 opp-4 { 2973 opp-peak-kBps = <12298000>; 2974 }; 2975 opp-5 { 2976 opp-peak-kBps = <14236000>; 2977 }; 2978 opp-6 { 2979 opp-peak-kBps = <15258001>; 2980 }; 2981 }; 2982 }; 2983 2984 system-cache-controller@9200000 { 2985 compatible = "qcom,sc8280xp-llcc"; 2986 reg = <0 0x09200000 0 0x58000>, <0 0x09600000 0 0x58000>; 2987 reg-names = "llcc_base", "llcc_broadcast_base"; 2988 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 2989 }; 2990 2991 usb_0: usb@a6f8800 { 2992 compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3"; 2993 reg = <0 0x0a6f8800 0 0x400>; 2994 #address-cells = <2>; 2995 #size-cells = <2>; 2996 ranges; 2997 2998 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 2999 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3000 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3001 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 3002 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3003 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 3004 <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>, 3005 <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>, 3006 <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 3007 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", 3008 "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys"; 3009 3010 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3011 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3012 assigned-clock-rates = <19200000>, <200000000>; 3013 3014 interrupts-extended = <&intc GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>, 3015 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 3016 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 3017 <&pdc 138 IRQ_TYPE_LEVEL_HIGH>; 3018 interrupt-names = "pwr_event", 3019 "dp_hs_phy_irq", 3020 "dm_hs_phy_irq", 3021 "ss_phy_irq"; 3022 3023 power-domains = <&gcc USB30_PRIM_GDSC>; 3024 required-opps = <&rpmhpd_opp_nom>; 3025 3026 resets = <&gcc GCC_USB30_PRIM_BCR>; 3027 3028 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 3029 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; 3030 interconnect-names = "usb-ddr", "apps-usb"; 3031 3032 wakeup-source; 3033 3034 status = "disabled"; 3035 3036 usb_0_dwc3: usb@a600000 { 3037 compatible = "snps,dwc3"; 3038 reg = <0 0x0a600000 0 0xcd00>; 3039 interrupts = <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>; 3040 iommus = <&apps_smmu 0x820 0x0>; 3041 phys = <&usb_0_hsphy>, <&usb_0_qmpphy QMP_USB43DP_USB3_PHY>; 3042 phy-names = "usb2-phy", "usb3-phy"; 3043 3044 port { 3045 usb_0_role_switch: endpoint { 3046 }; 3047 }; 3048 }; 3049 }; 3050 3051 usb_1: usb@a8f8800 { 3052 compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3"; 3053 reg = <0 0x0a8f8800 0 0x400>; 3054 #address-cells = <2>; 3055 #size-cells = <2>; 3056 ranges; 3057 3058 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 3059 <&gcc GCC_USB30_SEC_MASTER_CLK>, 3060 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 3061 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 3062 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3063 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 3064 <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>, 3065 <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>, 3066 <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 3067 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", 3068 "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys"; 3069 3070 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3071 <&gcc GCC_USB30_SEC_MASTER_CLK>; 3072 assigned-clock-rates = <19200000>, <200000000>; 3073 3074 interrupts-extended = <&intc GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>, 3075 <&pdc 12 IRQ_TYPE_EDGE_BOTH>, 3076 <&pdc 13 IRQ_TYPE_EDGE_BOTH>, 3077 <&pdc 136 IRQ_TYPE_LEVEL_HIGH>; 3078 interrupt-names = "pwr_event", 3079 "dp_hs_phy_irq", 3080 "dm_hs_phy_irq", 3081 "ss_phy_irq"; 3082 3083 power-domains = <&gcc USB30_SEC_GDSC>; 3084 required-opps = <&rpmhpd_opp_nom>; 3085 3086 resets = <&gcc GCC_USB30_SEC_BCR>; 3087 3088 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>, 3089 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>; 3090 interconnect-names = "usb-ddr", "apps-usb"; 3091 3092 wakeup-source; 3093 3094 status = "disabled"; 3095 3096 usb_1_dwc3: usb@a800000 { 3097 compatible = "snps,dwc3"; 3098 reg = <0 0x0a800000 0 0xcd00>; 3099 interrupts = <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>; 3100 iommus = <&apps_smmu 0x860 0x0>; 3101 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 3102 phy-names = "usb2-phy", "usb3-phy"; 3103 3104 port { 3105 usb_1_role_switch: endpoint { 3106 }; 3107 }; 3108 }; 3109 }; 3110 3111 mdss0: display-subsystem@ae00000 { 3112 compatible = "qcom,sc8280xp-mdss"; 3113 reg = <0 0x0ae00000 0 0x1000>; 3114 reg-names = "mdss"; 3115 3116 clocks = <&gcc GCC_DISP_AHB_CLK>, 3117 <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 3118 <&dispcc0 DISP_CC_MDSS_MDP_CLK>; 3119 clock-names = "iface", 3120 "ahb", 3121 "core"; 3122 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 3123 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>, 3124 <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>; 3125 interconnect-names = "mdp0-mem", "mdp1-mem"; 3126 iommus = <&apps_smmu 0x1000 0x402>; 3127 power-domains = <&dispcc0 MDSS_GDSC>; 3128 resets = <&dispcc0 DISP_CC_MDSS_CORE_BCR>; 3129 3130 interrupt-controller; 3131 #interrupt-cells = <1>; 3132 #address-cells = <2>; 3133 #size-cells = <2>; 3134 ranges; 3135 3136 status = "disabled"; 3137 3138 mdss0_mdp: display-controller@ae01000 { 3139 compatible = "qcom,sc8280xp-dpu"; 3140 reg = <0 0x0ae01000 0 0x8f000>, 3141 <0 0x0aeb0000 0 0x2008>; 3142 reg-names = "mdp", "vbif"; 3143 3144 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 3145 <&gcc GCC_DISP_SF_AXI_CLK>, 3146 <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 3147 <&dispcc0 DISP_CC_MDSS_MDP_LUT_CLK>, 3148 <&dispcc0 DISP_CC_MDSS_MDP_CLK>, 3149 <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>; 3150 clock-names = "bus", 3151 "nrt_bus", 3152 "iface", 3153 "lut", 3154 "core", 3155 "vsync"; 3156 interrupt-parent = <&mdss0>; 3157 interrupts = <0>; 3158 power-domains = <&rpmhpd SC8280XP_MMCX>; 3159 3160 assigned-clocks = <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>; 3161 assigned-clock-rates = <19200000>; 3162 operating-points-v2 = <&mdss0_mdp_opp_table>; 3163 3164 ports { 3165 #address-cells = <1>; 3166 #size-cells = <0>; 3167 3168 port@0 { 3169 reg = <0>; 3170 mdss0_intf0_out: endpoint { 3171 remote-endpoint = <&mdss0_dp0_in>; 3172 }; 3173 }; 3174 3175 port@4 { 3176 reg = <4>; 3177 mdss0_intf4_out: endpoint { 3178 remote-endpoint = <&mdss0_dp1_in>; 3179 }; 3180 }; 3181 3182 port@5 { 3183 reg = <5>; 3184 mdss0_intf5_out: endpoint { 3185 remote-endpoint = <&mdss0_dp3_in>; 3186 }; 3187 }; 3188 3189 port@6 { 3190 reg = <6>; 3191 mdss0_intf6_out: endpoint { 3192 remote-endpoint = <&mdss0_dp2_in>; 3193 }; 3194 }; 3195 }; 3196 3197 mdss0_mdp_opp_table: opp-table { 3198 compatible = "operating-points-v2"; 3199 3200 opp-200000000 { 3201 opp-hz = /bits/ 64 <200000000>; 3202 required-opps = <&rpmhpd_opp_low_svs>; 3203 }; 3204 3205 opp-300000000 { 3206 opp-hz = /bits/ 64 <300000000>; 3207 required-opps = <&rpmhpd_opp_svs>; 3208 }; 3209 3210 opp-375000000 { 3211 opp-hz = /bits/ 64 <375000000>; 3212 required-opps = <&rpmhpd_opp_svs_l1>; 3213 }; 3214 3215 opp-500000000 { 3216 opp-hz = /bits/ 64 <500000000>; 3217 required-opps = <&rpmhpd_opp_nom>; 3218 }; 3219 opp-600000000 { 3220 opp-hz = /bits/ 64 <600000000>; 3221 required-opps = <&rpmhpd_opp_turbo_l1>; 3222 }; 3223 }; 3224 }; 3225 3226 mdss0_dp0: displayport-controller@ae90000 { 3227 compatible = "qcom,sc8280xp-dp"; 3228 reg = <0 0xae90000 0 0x200>, 3229 <0 0xae90200 0 0x200>, 3230 <0 0xae90400 0 0x600>, 3231 <0 0xae91000 0 0x400>, 3232 <0 0xae91400 0 0x400>; 3233 interrupt-parent = <&mdss0>; 3234 interrupts = <12>; 3235 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 3236 <&dispcc0 DISP_CC_MDSS_DPTX0_AUX_CLK>, 3237 <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_CLK>, 3238 <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 3239 <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; 3240 clock-names = "core_iface", "core_aux", 3241 "ctrl_link", 3242 "ctrl_link_iface", 3243 "stream_pixel"; 3244 3245 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 3246 <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; 3247 assigned-clock-parents = <&usb_0_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3248 <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 3249 3250 phys = <&usb_0_qmpphy QMP_USB43DP_DP_PHY>; 3251 phy-names = "dp"; 3252 3253 #sound-dai-cells = <0>; 3254 3255 operating-points-v2 = <&mdss0_dp0_opp_table>; 3256 power-domains = <&rpmhpd SC8280XP_CX>; 3257 3258 status = "disabled"; 3259 3260 ports { 3261 #address-cells = <1>; 3262 #size-cells = <0>; 3263 3264 port@0 { 3265 reg = <0>; 3266 3267 mdss0_dp0_in: endpoint { 3268 remote-endpoint = <&mdss0_intf0_out>; 3269 }; 3270 }; 3271 3272 port@1 { 3273 reg = <1>; 3274 3275 mdss0_dp0_out: endpoint { 3276 }; 3277 }; 3278 }; 3279 3280 mdss0_dp0_opp_table: opp-table { 3281 compatible = "operating-points-v2"; 3282 3283 opp-160000000 { 3284 opp-hz = /bits/ 64 <160000000>; 3285 required-opps = <&rpmhpd_opp_low_svs>; 3286 }; 3287 3288 opp-270000000 { 3289 opp-hz = /bits/ 64 <270000000>; 3290 required-opps = <&rpmhpd_opp_svs>; 3291 }; 3292 3293 opp-540000000 { 3294 opp-hz = /bits/ 64 <540000000>; 3295 required-opps = <&rpmhpd_opp_svs_l1>; 3296 }; 3297 3298 opp-810000000 { 3299 opp-hz = /bits/ 64 <810000000>; 3300 required-opps = <&rpmhpd_opp_nom>; 3301 }; 3302 }; 3303 }; 3304 3305 mdss0_dp1: displayport-controller@ae98000 { 3306 compatible = "qcom,sc8280xp-dp"; 3307 reg = <0 0xae98000 0 0x200>, 3308 <0 0xae98200 0 0x200>, 3309 <0 0xae98400 0 0x600>, 3310 <0 0xae99000 0 0x400>, 3311 <0 0xae99400 0 0x400>; 3312 interrupt-parent = <&mdss0>; 3313 interrupts = <13>; 3314 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 3315 <&dispcc0 DISP_CC_MDSS_DPTX1_AUX_CLK>, 3316 <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_CLK>, 3317 <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, 3318 <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>; 3319 clock-names = "core_iface", "core_aux", 3320 "ctrl_link", 3321 "ctrl_link_iface", "stream_pixel"; 3322 3323 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, 3324 <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>; 3325 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3326 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 3327 3328 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; 3329 phy-names = "dp"; 3330 3331 #sound-dai-cells = <0>; 3332 3333 operating-points-v2 = <&mdss0_dp1_opp_table>; 3334 power-domains = <&rpmhpd SC8280XP_CX>; 3335 3336 status = "disabled"; 3337 3338 ports { 3339 #address-cells = <1>; 3340 #size-cells = <0>; 3341 3342 port@0 { 3343 reg = <0>; 3344 3345 mdss0_dp1_in: endpoint { 3346 remote-endpoint = <&mdss0_intf4_out>; 3347 }; 3348 }; 3349 3350 port@1 { 3351 reg = <1>; 3352 3353 mdss0_dp1_out: endpoint { 3354 }; 3355 }; 3356 }; 3357 3358 mdss0_dp1_opp_table: opp-table { 3359 compatible = "operating-points-v2"; 3360 3361 opp-160000000 { 3362 opp-hz = /bits/ 64 <160000000>; 3363 required-opps = <&rpmhpd_opp_low_svs>; 3364 }; 3365 3366 opp-270000000 { 3367 opp-hz = /bits/ 64 <270000000>; 3368 required-opps = <&rpmhpd_opp_svs>; 3369 }; 3370 3371 opp-540000000 { 3372 opp-hz = /bits/ 64 <540000000>; 3373 required-opps = <&rpmhpd_opp_svs_l1>; 3374 }; 3375 3376 opp-810000000 { 3377 opp-hz = /bits/ 64 <810000000>; 3378 required-opps = <&rpmhpd_opp_nom>; 3379 }; 3380 }; 3381 }; 3382 3383 mdss0_dp2: displayport-controller@ae9a000 { 3384 compatible = "qcom,sc8280xp-dp"; 3385 reg = <0 0xae9a000 0 0x200>, 3386 <0 0xae9a200 0 0x200>, 3387 <0 0xae9a400 0 0x600>, 3388 <0 0xae9b000 0 0x400>, 3389 <0 0xae9b400 0 0x400>; 3390 3391 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 3392 <&dispcc0 DISP_CC_MDSS_DPTX2_AUX_CLK>, 3393 <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_CLK>, 3394 <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>, 3395 <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>; 3396 clock-names = "core_iface", "core_aux", 3397 "ctrl_link", 3398 "ctrl_link_iface", "stream_pixel"; 3399 interrupt-parent = <&mdss0>; 3400 interrupts = <14>; 3401 phys = <&mdss0_dp2_phy>; 3402 phy-names = "dp"; 3403 power-domains = <&rpmhpd SC8280XP_MMCX>; 3404 3405 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>, 3406 <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>; 3407 assigned-clock-parents = <&mdss0_dp2_phy 0>, <&mdss0_dp2_phy 1>; 3408 operating-points-v2 = <&mdss0_dp2_opp_table>; 3409 3410 #sound-dai-cells = <0>; 3411 3412 status = "disabled"; 3413 3414 ports { 3415 #address-cells = <1>; 3416 #size-cells = <0>; 3417 3418 port@0 { 3419 reg = <0>; 3420 mdss0_dp2_in: endpoint { 3421 remote-endpoint = <&mdss0_intf6_out>; 3422 }; 3423 }; 3424 3425 port@1 { 3426 reg = <1>; 3427 }; 3428 }; 3429 3430 mdss0_dp2_opp_table: opp-table { 3431 compatible = "operating-points-v2"; 3432 3433 opp-160000000 { 3434 opp-hz = /bits/ 64 <160000000>; 3435 required-opps = <&rpmhpd_opp_low_svs>; 3436 }; 3437 3438 opp-270000000 { 3439 opp-hz = /bits/ 64 <270000000>; 3440 required-opps = <&rpmhpd_opp_svs>; 3441 }; 3442 3443 opp-540000000 { 3444 opp-hz = /bits/ 64 <540000000>; 3445 required-opps = <&rpmhpd_opp_svs_l1>; 3446 }; 3447 3448 opp-810000000 { 3449 opp-hz = /bits/ 64 <810000000>; 3450 required-opps = <&rpmhpd_opp_nom>; 3451 }; 3452 }; 3453 }; 3454 3455 mdss0_dp3: displayport-controller@aea0000 { 3456 compatible = "qcom,sc8280xp-dp"; 3457 reg = <0 0xaea0000 0 0x200>, 3458 <0 0xaea0200 0 0x200>, 3459 <0 0xaea0400 0 0x600>, 3460 <0 0xaea1000 0 0x400>, 3461 <0 0xaea1400 0 0x400>; 3462 3463 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 3464 <&dispcc0 DISP_CC_MDSS_DPTX3_AUX_CLK>, 3465 <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_CLK>, 3466 <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>, 3467 <&dispcc0 DISP_CC_MDSS_DPTX3_PIXEL0_CLK>; 3468 clock-names = "core_iface", "core_aux", 3469 "ctrl_link", 3470 "ctrl_link_iface", "stream_pixel"; 3471 interrupt-parent = <&mdss0>; 3472 interrupts = <15>; 3473 phys = <&mdss0_dp3_phy>; 3474 phy-names = "dp"; 3475 power-domains = <&rpmhpd SC8280XP_MMCX>; 3476 3477 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>, 3478 <&dispcc0 DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>; 3479 assigned-clock-parents = <&mdss0_dp3_phy 0>, <&mdss0_dp3_phy 1>; 3480 operating-points-v2 = <&mdss0_dp3_opp_table>; 3481 3482 #sound-dai-cells = <0>; 3483 3484 status = "disabled"; 3485 3486 ports { 3487 #address-cells = <1>; 3488 #size-cells = <0>; 3489 3490 port@0 { 3491 reg = <0>; 3492 mdss0_dp3_in: endpoint { 3493 remote-endpoint = <&mdss0_intf5_out>; 3494 }; 3495 }; 3496 3497 port@1 { 3498 reg = <1>; 3499 }; 3500 }; 3501 3502 mdss0_dp3_opp_table: opp-table { 3503 compatible = "operating-points-v2"; 3504 3505 opp-160000000 { 3506 opp-hz = /bits/ 64 <160000000>; 3507 required-opps = <&rpmhpd_opp_low_svs>; 3508 }; 3509 3510 opp-270000000 { 3511 opp-hz = /bits/ 64 <270000000>; 3512 required-opps = <&rpmhpd_opp_svs>; 3513 }; 3514 3515 opp-540000000 { 3516 opp-hz = /bits/ 64 <540000000>; 3517 required-opps = <&rpmhpd_opp_svs_l1>; 3518 }; 3519 3520 opp-810000000 { 3521 opp-hz = /bits/ 64 <810000000>; 3522 required-opps = <&rpmhpd_opp_nom>; 3523 }; 3524 }; 3525 }; 3526 }; 3527 3528 mdss0_dp2_phy: phy@aec2a00 { 3529 compatible = "qcom,sc8280xp-dp-phy"; 3530 reg = <0 0x0aec2a00 0 0x19c>, 3531 <0 0x0aec2200 0 0xec>, 3532 <0 0x0aec2600 0 0xec>, 3533 <0 0x0aec2000 0 0x1c8>; 3534 3535 clocks = <&dispcc0 DISP_CC_MDSS_DPTX2_AUX_CLK>, 3536 <&dispcc0 DISP_CC_MDSS_AHB_CLK>; 3537 clock-names = "aux", "cfg_ahb"; 3538 power-domains = <&rpmhpd SC8280XP_MX>; 3539 3540 #clock-cells = <1>; 3541 #phy-cells = <0>; 3542 3543 status = "disabled"; 3544 }; 3545 3546 mdss0_dp3_phy: phy@aec5a00 { 3547 compatible = "qcom,sc8280xp-dp-phy"; 3548 reg = <0 0x0aec5a00 0 0x19c>, 3549 <0 0x0aec5200 0 0xec>, 3550 <0 0x0aec5600 0 0xec>, 3551 <0 0x0aec5000 0 0x1c8>; 3552 3553 clocks = <&dispcc0 DISP_CC_MDSS_DPTX3_AUX_CLK>, 3554 <&dispcc0 DISP_CC_MDSS_AHB_CLK>; 3555 clock-names = "aux", "cfg_ahb"; 3556 power-domains = <&rpmhpd SC8280XP_MX>; 3557 3558 #clock-cells = <1>; 3559 #phy-cells = <0>; 3560 3561 status = "disabled"; 3562 }; 3563 3564 dispcc0: clock-controller@af00000 { 3565 compatible = "qcom,sc8280xp-dispcc0"; 3566 reg = <0 0x0af00000 0 0x20000>; 3567 3568 clocks = <&gcc GCC_DISP_AHB_CLK>, 3569 <&rpmhcc RPMH_CXO_CLK>, 3570 <&sleep_clk>, 3571 <&usb_0_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3572 <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 3573 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3574 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 3575 <&mdss0_dp2_phy 0>, 3576 <&mdss0_dp2_phy 1>, 3577 <&mdss0_dp3_phy 0>, 3578 <&mdss0_dp3_phy 1>, 3579 <0>, 3580 <0>, 3581 <0>, 3582 <0>; 3583 power-domains = <&rpmhpd SC8280XP_MMCX>; 3584 3585 #clock-cells = <1>; 3586 #power-domain-cells = <1>; 3587 #reset-cells = <1>; 3588 3589 status = "disabled"; 3590 }; 3591 3592 pdc: interrupt-controller@b220000 { 3593 compatible = "qcom,sc8280xp-pdc", "qcom,pdc"; 3594 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; 3595 qcom,pdc-ranges = <0 480 40>, 3596 <40 140 14>, 3597 <54 263 1>, 3598 <55 306 4>, 3599 <59 312 3>, 3600 <62 374 2>, 3601 <64 434 2>, 3602 <66 438 3>, 3603 <69 86 1>, 3604 <70 520 54>, 3605 <124 609 28>, 3606 <159 638 1>, 3607 <160 720 8>, 3608 <168 801 1>, 3609 <169 728 30>, 3610 <199 416 2>, 3611 <201 449 1>, 3612 <202 89 1>, 3613 <203 451 1>, 3614 <204 462 1>, 3615 <205 264 1>, 3616 <206 579 1>, 3617 <207 653 1>, 3618 <208 656 1>, 3619 <209 659 1>, 3620 <210 122 1>, 3621 <211 699 1>, 3622 <212 705 1>, 3623 <213 450 1>, 3624 <214 643 1>, 3625 <216 646 5>, 3626 <221 390 5>, 3627 <226 700 3>, 3628 <229 240 3>, 3629 <232 269 1>, 3630 <233 377 1>, 3631 <234 372 1>, 3632 <235 138 1>, 3633 <236 857 1>, 3634 <237 860 1>, 3635 <238 137 1>, 3636 <239 668 1>, 3637 <240 366 1>, 3638 <241 949 1>, 3639 <242 815 5>, 3640 <247 769 1>, 3641 <248 768 1>, 3642 <249 663 1>, 3643 <250 799 2>, 3644 <252 798 1>, 3645 <253 765 1>, 3646 <254 763 1>, 3647 <255 454 1>, 3648 <258 139 1>, 3649 <259 786 2>, 3650 <261 370 2>, 3651 <263 158 2>; 3652 #interrupt-cells = <2>; 3653 interrupt-parent = <&intc>; 3654 interrupt-controller; 3655 }; 3656 3657 tsens0: thermal-sensor@c263000 { 3658 compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2"; 3659 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 3660 <0 0x0c222000 0 0x8>; /* SROT */ 3661 #qcom,sensors = <14>; 3662 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, 3663 <&pdc 28 IRQ_TYPE_LEVEL_HIGH>; 3664 interrupt-names = "uplow", "critical"; 3665 #thermal-sensor-cells = <1>; 3666 }; 3667 3668 tsens1: thermal-sensor@c265000 { 3669 compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2"; 3670 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 3671 <0 0x0c223000 0 0x8>; /* SROT */ 3672 #qcom,sensors = <16>; 3673 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, 3674 <&pdc 29 IRQ_TYPE_LEVEL_HIGH>; 3675 interrupt-names = "uplow", "critical"; 3676 #thermal-sensor-cells = <1>; 3677 }; 3678 3679 aoss_qmp: power-management@c300000 { 3680 compatible = "qcom,sc8280xp-aoss-qmp", "qcom,aoss-qmp"; 3681 reg = <0 0x0c300000 0 0x400>; 3682 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>; 3683 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 3684 3685 #clock-cells = <0>; 3686 }; 3687 3688 sram@c3f0000 { 3689 compatible = "qcom,rpmh-stats"; 3690 reg = <0 0x0c3f0000 0 0x400>; 3691 }; 3692 3693 spmi_bus: spmi@c440000 { 3694 compatible = "qcom,spmi-pmic-arb"; 3695 reg = <0 0x0c440000 0 0x1100>, 3696 <0 0x0c600000 0 0x2000000>, 3697 <0 0x0e600000 0 0x100000>, 3698 <0 0x0e700000 0 0xa0000>, 3699 <0 0x0c40a000 0 0x26000>; 3700 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 3701 interrupt-names = "periph_irq"; 3702 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 3703 qcom,ee = <0>; 3704 qcom,channel = <0>; 3705 #address-cells = <2>; 3706 #size-cells = <0>; 3707 interrupt-controller; 3708 #interrupt-cells = <4>; 3709 }; 3710 3711 tlmm: pinctrl@f100000 { 3712 compatible = "qcom,sc8280xp-tlmm"; 3713 reg = <0 0x0f100000 0 0x300000>; 3714 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 3715 gpio-controller; 3716 #gpio-cells = <2>; 3717 interrupt-controller; 3718 #interrupt-cells = <2>; 3719 gpio-ranges = <&tlmm 0 0 230>; 3720 }; 3721 3722 apps_smmu: iommu@15000000 { 3723 compatible = "qcom,sc8280xp-smmu-500", "arm,mmu-500"; 3724 reg = <0 0x15000000 0 0x100000>; 3725 #iommu-cells = <2>; 3726 #global-interrupts = <2>; 3727 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 3728 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3729 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3730 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3731 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3732 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3733 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3734 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3735 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3736 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3737 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3738 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3739 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3740 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3741 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3742 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3743 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3744 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3745 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3746 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3747 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3748 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3749 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3750 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3751 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3752 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3753 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3754 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3755 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3756 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3757 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3758 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3759 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3760 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3761 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3762 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3763 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3764 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3765 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3766 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3767 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3768 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3769 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3770 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3771 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3772 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3773 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3774 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3775 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3776 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3777 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3778 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3779 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3780 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3781 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3782 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3783 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3784 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3785 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3786 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3787 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3788 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 3789 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 3790 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 3791 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 3792 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 3793 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 3794 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3795 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3796 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3797 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3798 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3799 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3800 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3801 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 3802 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 3803 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 3804 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 3805 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 3806 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 3807 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, 3808 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 3809 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 3810 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 3811 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, 3812 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 3813 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 3814 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 3815 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 3816 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 3817 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 3818 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 3819 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 3820 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 3821 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 3822 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>, 3823 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 3824 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 3825 <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>, 3826 <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>, 3827 <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>, 3828 <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>, 3829 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 3830 <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>, 3831 <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>, 3832 <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>, 3833 <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>, 3834 <GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH>, 3835 <GIC_SPI 911 IRQ_TYPE_LEVEL_HIGH>, 3836 <GIC_SPI 910 IRQ_TYPE_LEVEL_HIGH>, 3837 <GIC_SPI 909 IRQ_TYPE_LEVEL_HIGH>, 3838 <GIC_SPI 908 IRQ_TYPE_LEVEL_HIGH>, 3839 <GIC_SPI 907 IRQ_TYPE_LEVEL_HIGH>, 3840 <GIC_SPI 906 IRQ_TYPE_LEVEL_HIGH>, 3841 <GIC_SPI 905 IRQ_TYPE_LEVEL_HIGH>, 3842 <GIC_SPI 904 IRQ_TYPE_LEVEL_HIGH>, 3843 <GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>, 3844 <GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>, 3845 <GIC_SPI 901 IRQ_TYPE_LEVEL_HIGH>, 3846 <GIC_SPI 900 IRQ_TYPE_LEVEL_HIGH>, 3847 <GIC_SPI 899 IRQ_TYPE_LEVEL_HIGH>, 3848 <GIC_SPI 898 IRQ_TYPE_LEVEL_HIGH>, 3849 <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>, 3850 <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>, 3851 <GIC_SPI 895 IRQ_TYPE_LEVEL_HIGH>, 3852 <GIC_SPI 894 IRQ_TYPE_LEVEL_HIGH>, 3853 <GIC_SPI 893 IRQ_TYPE_LEVEL_HIGH>, 3854 <GIC_SPI 892 IRQ_TYPE_LEVEL_HIGH>, 3855 <GIC_SPI 891 IRQ_TYPE_LEVEL_HIGH>, 3856 <GIC_SPI 890 IRQ_TYPE_LEVEL_HIGH>; 3857 }; 3858 3859 intc: interrupt-controller@17a00000 { 3860 compatible = "arm,gic-v3"; 3861 interrupt-controller; 3862 #interrupt-cells = <3>; 3863 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 3864 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 3865 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3866 #redistributor-regions = <1>; 3867 redistributor-stride = <0 0x20000>; 3868 3869 #address-cells = <2>; 3870 #size-cells = <2>; 3871 ranges; 3872 3873 gic-its@17a40000 { 3874 compatible = "arm,gic-v3-its"; 3875 reg = <0 0x17a40000 0 0x20000>; 3876 msi-controller; 3877 #msi-cells = <1>; 3878 }; 3879 }; 3880 3881 watchdog@17c10000 { 3882 compatible = "qcom,apss-wdt-sc8280xp", "qcom,kpss-wdt"; 3883 reg = <0 0x17c10000 0 0x1000>; 3884 clocks = <&sleep_clk>; 3885 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 3886 }; 3887 3888 timer@17c20000 { 3889 compatible = "arm,armv7-timer-mem"; 3890 reg = <0x0 0x17c20000 0x0 0x1000>; 3891 #address-cells = <1>; 3892 #size-cells = <1>; 3893 ranges = <0x0 0x0 0x0 0x20000000>; 3894 3895 frame@17c21000 { 3896 frame-number = <0>; 3897 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3898 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3899 reg = <0x17c21000 0x1000>, 3900 <0x17c22000 0x1000>; 3901 }; 3902 3903 frame@17c23000 { 3904 frame-number = <1>; 3905 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3906 reg = <0x17c23000 0x1000>; 3907 status = "disabled"; 3908 }; 3909 3910 frame@17c25000 { 3911 frame-number = <2>; 3912 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3913 reg = <0x17c25000 0x1000>; 3914 status = "disabled"; 3915 }; 3916 3917 frame@17c27000 { 3918 frame-number = <3>; 3919 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3920 reg = <0x17c26000 0x1000>; 3921 status = "disabled"; 3922 }; 3923 3924 frame@17c29000 { 3925 frame-number = <4>; 3926 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3927 reg = <0x17c29000 0x1000>; 3928 status = "disabled"; 3929 }; 3930 3931 frame@17c2b000 { 3932 frame-number = <5>; 3933 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3934 reg = <0x17c2b000 0x1000>; 3935 status = "disabled"; 3936 }; 3937 3938 frame@17c2d000 { 3939 frame-number = <6>; 3940 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3941 reg = <0x17c2d000 0x1000>; 3942 status = "disabled"; 3943 }; 3944 }; 3945 3946 apps_rsc: rsc@18200000 { 3947 compatible = "qcom,rpmh-rsc"; 3948 reg = <0x0 0x18200000 0x0 0x10000>, 3949 <0x0 0x18210000 0x0 0x10000>, 3950 <0x0 0x18220000 0x0 0x10000>; 3951 reg-names = "drv-0", "drv-1", "drv-2"; 3952 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3953 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3954 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3955 qcom,tcs-offset = <0xd00>; 3956 qcom,drv-id = <2>; 3957 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 3958 <WAKE_TCS 3>, <CONTROL_TCS 1>; 3959 label = "apps_rsc"; 3960 3961 apps_bcm_voter: bcm-voter { 3962 compatible = "qcom,bcm-voter"; 3963 }; 3964 3965 rpmhcc: clock-controller { 3966 compatible = "qcom,sc8280xp-rpmh-clk"; 3967 #clock-cells = <1>; 3968 clock-names = "xo"; 3969 clocks = <&xo_board_clk>; 3970 }; 3971 3972 rpmhpd: power-controller { 3973 compatible = "qcom,sc8280xp-rpmhpd"; 3974 #power-domain-cells = <1>; 3975 operating-points-v2 = <&rpmhpd_opp_table>; 3976 3977 rpmhpd_opp_table: opp-table { 3978 compatible = "operating-points-v2"; 3979 3980 rpmhpd_opp_ret: opp1 { 3981 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3982 }; 3983 3984 rpmhpd_opp_min_svs: opp2 { 3985 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3986 }; 3987 3988 rpmhpd_opp_low_svs: opp3 { 3989 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3990 }; 3991 3992 rpmhpd_opp_svs: opp4 { 3993 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3994 }; 3995 3996 rpmhpd_opp_svs_l1: opp5 { 3997 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3998 }; 3999 4000 rpmhpd_opp_nom: opp6 { 4001 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4002 }; 4003 4004 rpmhpd_opp_nom_l1: opp7 { 4005 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4006 }; 4007 4008 rpmhpd_opp_nom_l2: opp8 { 4009 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 4010 }; 4011 4012 rpmhpd_opp_turbo: opp9 { 4013 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4014 }; 4015 4016 rpmhpd_opp_turbo_l1: opp10 { 4017 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4018 }; 4019 }; 4020 }; 4021 }; 4022 4023 epss_l3: interconnect@18590000 { 4024 compatible = "qcom,sc8280xp-epss-l3", "qcom,epss-l3"; 4025 reg = <0 0x18590000 0 0x1000>; 4026 4027 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 4028 clock-names = "xo", "alternate"; 4029 4030 #interconnect-cells = <1>; 4031 }; 4032 4033 cpufreq_hw: cpufreq@18591000 { 4034 compatible = "qcom,sc8280xp-cpufreq-epss", "qcom,cpufreq-epss"; 4035 reg = <0 0x18591000 0 0x1000>, 4036 <0 0x18592000 0 0x1000>; 4037 reg-names = "freq-domain0", "freq-domain1"; 4038 4039 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 4040 clock-names = "xo", "alternate"; 4041 4042 #freq-domain-cells = <1>; 4043 }; 4044 4045 remoteproc_nsp0: remoteproc@1b300000 { 4046 compatible = "qcom,sc8280xp-nsp0-pas"; 4047 reg = <0 0x1b300000 0 0x100>; 4048 4049 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, 4050 <&smp2p_nsp0_in 0 IRQ_TYPE_EDGE_RISING>, 4051 <&smp2p_nsp0_in 1 IRQ_TYPE_EDGE_RISING>, 4052 <&smp2p_nsp0_in 2 IRQ_TYPE_EDGE_RISING>, 4053 <&smp2p_nsp0_in 3 IRQ_TYPE_EDGE_RISING>; 4054 interrupt-names = "wdog", "fatal", "ready", 4055 "handover", "stop-ack"; 4056 4057 clocks = <&rpmhcc RPMH_CXO_CLK>; 4058 clock-names = "xo"; 4059 4060 power-domains = <&rpmhpd SC8280XP_NSP>; 4061 power-domain-names = "nsp"; 4062 4063 memory-region = <&pil_nsp0_mem>; 4064 4065 qcom,smem-states = <&smp2p_nsp0_out 0>; 4066 qcom,smem-state-names = "stop"; 4067 4068 interconnects = <&nspa_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>; 4069 4070 status = "disabled"; 4071 4072 glink-edge { 4073 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 4074 IPCC_MPROC_SIGNAL_GLINK_QMP 4075 IRQ_TYPE_EDGE_RISING>; 4076 mboxes = <&ipcc IPCC_CLIENT_CDSP 4077 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4078 4079 label = "nsp0"; 4080 qcom,remote-pid = <5>; 4081 4082 fastrpc { 4083 compatible = "qcom,fastrpc"; 4084 qcom,glink-channels = "fastrpcglink-apps-dsp"; 4085 label = "cdsp"; 4086 #address-cells = <1>; 4087 #size-cells = <0>; 4088 4089 compute-cb@1 { 4090 compatible = "qcom,fastrpc-compute-cb"; 4091 reg = <1>; 4092 iommus = <&apps_smmu 0x3181 0x0420>; 4093 }; 4094 4095 compute-cb@2 { 4096 compatible = "qcom,fastrpc-compute-cb"; 4097 reg = <2>; 4098 iommus = <&apps_smmu 0x3182 0x0420>; 4099 }; 4100 4101 compute-cb@3 { 4102 compatible = "qcom,fastrpc-compute-cb"; 4103 reg = <3>; 4104 iommus = <&apps_smmu 0x3183 0x0420>; 4105 }; 4106 4107 compute-cb@4 { 4108 compatible = "qcom,fastrpc-compute-cb"; 4109 reg = <4>; 4110 iommus = <&apps_smmu 0x3184 0x0420>; 4111 }; 4112 4113 compute-cb@5 { 4114 compatible = "qcom,fastrpc-compute-cb"; 4115 reg = <5>; 4116 iommus = <&apps_smmu 0x3185 0x0420>; 4117 }; 4118 4119 compute-cb@6 { 4120 compatible = "qcom,fastrpc-compute-cb"; 4121 reg = <6>; 4122 iommus = <&apps_smmu 0x3186 0x0420>; 4123 }; 4124 4125 compute-cb@7 { 4126 compatible = "qcom,fastrpc-compute-cb"; 4127 reg = <7>; 4128 iommus = <&apps_smmu 0x3187 0x0420>; 4129 }; 4130 4131 compute-cb@8 { 4132 compatible = "qcom,fastrpc-compute-cb"; 4133 reg = <8>; 4134 iommus = <&apps_smmu 0x3188 0x0420>; 4135 }; 4136 4137 compute-cb@9 { 4138 compatible = "qcom,fastrpc-compute-cb"; 4139 reg = <9>; 4140 iommus = <&apps_smmu 0x318b 0x0420>; 4141 }; 4142 4143 compute-cb@10 { 4144 compatible = "qcom,fastrpc-compute-cb"; 4145 reg = <10>; 4146 iommus = <&apps_smmu 0x318b 0x0420>; 4147 }; 4148 4149 compute-cb@11 { 4150 compatible = "qcom,fastrpc-compute-cb"; 4151 reg = <11>; 4152 iommus = <&apps_smmu 0x318c 0x0420>; 4153 }; 4154 4155 compute-cb@12 { 4156 compatible = "qcom,fastrpc-compute-cb"; 4157 reg = <12>; 4158 iommus = <&apps_smmu 0x318d 0x0420>; 4159 }; 4160 4161 compute-cb@13 { 4162 compatible = "qcom,fastrpc-compute-cb"; 4163 reg = <13>; 4164 iommus = <&apps_smmu 0x318e 0x0420>; 4165 }; 4166 4167 compute-cb@14 { 4168 compatible = "qcom,fastrpc-compute-cb"; 4169 reg = <14>; 4170 iommus = <&apps_smmu 0x318f 0x0420>; 4171 }; 4172 }; 4173 }; 4174 }; 4175 4176 remoteproc_nsp1: remoteproc@21300000 { 4177 compatible = "qcom,sc8280xp-nsp1-pas"; 4178 reg = <0 0x21300000 0 0x100>; 4179 4180 interrupts-extended = <&intc GIC_SPI 887 IRQ_TYPE_LEVEL_HIGH>, 4181 <&smp2p_nsp1_in 0 IRQ_TYPE_EDGE_RISING>, 4182 <&smp2p_nsp1_in 1 IRQ_TYPE_EDGE_RISING>, 4183 <&smp2p_nsp1_in 2 IRQ_TYPE_EDGE_RISING>, 4184 <&smp2p_nsp1_in 3 IRQ_TYPE_EDGE_RISING>; 4185 interrupt-names = "wdog", "fatal", "ready", 4186 "handover", "stop-ack"; 4187 4188 clocks = <&rpmhcc RPMH_CXO_CLK>; 4189 clock-names = "xo"; 4190 4191 power-domains = <&rpmhpd SC8280XP_NSP>; 4192 power-domain-names = "nsp"; 4193 4194 memory-region = <&pil_nsp1_mem>; 4195 4196 qcom,smem-states = <&smp2p_nsp1_out 0>; 4197 qcom,smem-state-names = "stop"; 4198 4199 interconnects = <&nspb_noc MASTER_CDSP_PROC_B 0 &mc_virt SLAVE_EBI1 0>; 4200 4201 status = "disabled"; 4202 4203 glink-edge { 4204 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1 4205 IPCC_MPROC_SIGNAL_GLINK_QMP 4206 IRQ_TYPE_EDGE_RISING>; 4207 mboxes = <&ipcc IPCC_CLIENT_NSP1 4208 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4209 4210 label = "nsp1"; 4211 qcom,remote-pid = <12>; 4212 }; 4213 }; 4214 4215 mdss1: display-subsystem@22000000 { 4216 compatible = "qcom,sc8280xp-mdss"; 4217 reg = <0 0x22000000 0 0x1000>; 4218 reg-names = "mdss"; 4219 4220 clocks = <&gcc GCC_DISP_AHB_CLK>, 4221 <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 4222 <&dispcc1 DISP_CC_MDSS_MDP_CLK>; 4223 clock-names = "iface", 4224 "ahb", 4225 "core"; 4226 interconnects = <&mmss_noc MASTER_MDP_CORE1_0 0 &mc_virt SLAVE_EBI1 0>, 4227 <&mmss_noc MASTER_MDP_CORE1_1 0 &mc_virt SLAVE_EBI1 0>; 4228 interconnect-names = "mdp0-mem", "mdp1-mem"; 4229 interrupts = <GIC_SPI 865 IRQ_TYPE_LEVEL_HIGH>; 4230 4231 iommus = <&apps_smmu 0x1800 0x402>; 4232 power-domains = <&dispcc1 MDSS_GDSC>; 4233 resets = <&dispcc1 DISP_CC_MDSS_CORE_BCR>; 4234 4235 interrupt-controller; 4236 #interrupt-cells = <1>; 4237 #address-cells = <2>; 4238 #size-cells = <2>; 4239 ranges; 4240 4241 status = "disabled"; 4242 4243 mdss1_mdp: display-controller@22001000 { 4244 compatible = "qcom,sc8280xp-dpu"; 4245 reg = <0 0x22001000 0 0x8f000>, 4246 <0 0x220b0000 0 0x2008>; 4247 reg-names = "mdp", "vbif"; 4248 4249 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 4250 <&gcc GCC_DISP_SF_AXI_CLK>, 4251 <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 4252 <&dispcc1 DISP_CC_MDSS_MDP_LUT_CLK>, 4253 <&dispcc1 DISP_CC_MDSS_MDP_CLK>, 4254 <&dispcc1 DISP_CC_MDSS_VSYNC_CLK>; 4255 clock-names = "bus", 4256 "nrt_bus", 4257 "iface", 4258 "lut", 4259 "core", 4260 "vsync"; 4261 interrupt-parent = <&mdss1>; 4262 interrupts = <0>; 4263 power-domains = <&rpmhpd SC8280XP_MMCX>; 4264 4265 assigned-clocks = <&dispcc1 DISP_CC_MDSS_VSYNC_CLK>; 4266 assigned-clock-rates = <19200000>; 4267 operating-points-v2 = <&mdss1_mdp_opp_table>; 4268 4269 ports { 4270 #address-cells = <1>; 4271 #size-cells = <0>; 4272 4273 port@0 { 4274 reg = <0>; 4275 mdss1_intf0_out: endpoint { 4276 remote-endpoint = <&mdss1_dp0_in>; 4277 }; 4278 }; 4279 4280 port@4 { 4281 reg = <4>; 4282 mdss1_intf4_out: endpoint { 4283 remote-endpoint = <&mdss1_dp1_in>; 4284 }; 4285 }; 4286 4287 port@5 { 4288 reg = <5>; 4289 mdss1_intf5_out: endpoint { 4290 remote-endpoint = <&mdss1_dp3_in>; 4291 }; 4292 }; 4293 4294 port@6 { 4295 reg = <6>; 4296 mdss1_intf6_out: endpoint { 4297 remote-endpoint = <&mdss1_dp2_in>; 4298 }; 4299 }; 4300 }; 4301 4302 mdss1_mdp_opp_table: opp-table { 4303 compatible = "operating-points-v2"; 4304 4305 opp-200000000 { 4306 opp-hz = /bits/ 64 <200000000>; 4307 required-opps = <&rpmhpd_opp_low_svs>; 4308 }; 4309 4310 opp-300000000 { 4311 opp-hz = /bits/ 64 <300000000>; 4312 required-opps = <&rpmhpd_opp_svs>; 4313 }; 4314 4315 opp-375000000 { 4316 opp-hz = /bits/ 64 <375000000>; 4317 required-opps = <&rpmhpd_opp_svs_l1>; 4318 }; 4319 4320 opp-500000000 { 4321 opp-hz = /bits/ 64 <500000000>; 4322 required-opps = <&rpmhpd_opp_nom>; 4323 }; 4324 opp-600000000 { 4325 opp-hz = /bits/ 64 <600000000>; 4326 required-opps = <&rpmhpd_opp_turbo_l1>; 4327 }; 4328 }; 4329 }; 4330 4331 mdss1_dp0: displayport-controller@22090000 { 4332 compatible = "qcom,sc8280xp-dp"; 4333 reg = <0 0x22090000 0 0x200>, 4334 <0 0x22090200 0 0x200>, 4335 <0 0x22090400 0 0x600>, 4336 <0 0x22091000 0 0x400>, 4337 <0 0x22091400 0 0x400>; 4338 4339 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 4340 <&dispcc1 DISP_CC_MDSS_DPTX0_AUX_CLK>, 4341 <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_CLK>, 4342 <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 4343 <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; 4344 clock-names = "core_iface", "core_aux", 4345 "ctrl_link", 4346 "ctrl_link_iface", "stream_pixel"; 4347 interrupt-parent = <&mdss1>; 4348 interrupts = <12>; 4349 phys = <&mdss1_dp0_phy>; 4350 phy-names = "dp"; 4351 power-domains = <&rpmhpd SC8280XP_MMCX>; 4352 4353 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 4354 <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; 4355 assigned-clock-parents = <&mdss1_dp0_phy 0>, <&mdss1_dp0_phy 1>; 4356 operating-points-v2 = <&mdss1_dp0_opp_table>; 4357 4358 #sound-dai-cells = <0>; 4359 4360 status = "disabled"; 4361 4362 ports { 4363 #address-cells = <1>; 4364 #size-cells = <0>; 4365 4366 port@0 { 4367 reg = <0>; 4368 mdss1_dp0_in: endpoint { 4369 remote-endpoint = <&mdss1_intf0_out>; 4370 }; 4371 }; 4372 4373 port@1 { 4374 reg = <1>; 4375 }; 4376 }; 4377 4378 mdss1_dp0_opp_table: opp-table { 4379 compatible = "operating-points-v2"; 4380 4381 opp-160000000 { 4382 opp-hz = /bits/ 64 <160000000>; 4383 required-opps = <&rpmhpd_opp_low_svs>; 4384 }; 4385 4386 opp-270000000 { 4387 opp-hz = /bits/ 64 <270000000>; 4388 required-opps = <&rpmhpd_opp_svs>; 4389 }; 4390 4391 opp-540000000 { 4392 opp-hz = /bits/ 64 <540000000>; 4393 required-opps = <&rpmhpd_opp_svs_l1>; 4394 }; 4395 4396 opp-810000000 { 4397 opp-hz = /bits/ 64 <810000000>; 4398 required-opps = <&rpmhpd_opp_nom>; 4399 }; 4400 }; 4401 4402 }; 4403 4404 mdss1_dp1: displayport-controller@22098000 { 4405 compatible = "qcom,sc8280xp-dp"; 4406 reg = <0 0x22098000 0 0x200>, 4407 <0 0x22098200 0 0x200>, 4408 <0 0x22098400 0 0x600>, 4409 <0 0x22099000 0 0x400>, 4410 <0 0x22099400 0 0x400>; 4411 4412 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 4413 <&dispcc1 DISP_CC_MDSS_DPTX1_AUX_CLK>, 4414 <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_CLK>, 4415 <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, 4416 <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>; 4417 clock-names = "core_iface", "core_aux", 4418 "ctrl_link", 4419 "ctrl_link_iface", "stream_pixel"; 4420 interrupt-parent = <&mdss1>; 4421 interrupts = <13>; 4422 phys = <&mdss1_dp1_phy>; 4423 phy-names = "dp"; 4424 power-domains = <&rpmhpd SC8280XP_MMCX>; 4425 4426 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, 4427 <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>; 4428 assigned-clock-parents = <&mdss1_dp1_phy 0>, <&mdss1_dp1_phy 1>; 4429 operating-points-v2 = <&mdss1_dp1_opp_table>; 4430 4431 #sound-dai-cells = <0>; 4432 4433 status = "disabled"; 4434 4435 ports { 4436 #address-cells = <1>; 4437 #size-cells = <0>; 4438 4439 port@0 { 4440 reg = <0>; 4441 mdss1_dp1_in: endpoint { 4442 remote-endpoint = <&mdss1_intf4_out>; 4443 }; 4444 }; 4445 4446 port@1 { 4447 reg = <1>; 4448 }; 4449 }; 4450 4451 mdss1_dp1_opp_table: opp-table { 4452 compatible = "operating-points-v2"; 4453 4454 opp-160000000 { 4455 opp-hz = /bits/ 64 <160000000>; 4456 required-opps = <&rpmhpd_opp_low_svs>; 4457 }; 4458 4459 opp-270000000 { 4460 opp-hz = /bits/ 64 <270000000>; 4461 required-opps = <&rpmhpd_opp_svs>; 4462 }; 4463 4464 opp-540000000 { 4465 opp-hz = /bits/ 64 <540000000>; 4466 required-opps = <&rpmhpd_opp_svs_l1>; 4467 }; 4468 4469 opp-810000000 { 4470 opp-hz = /bits/ 64 <810000000>; 4471 required-opps = <&rpmhpd_opp_nom>; 4472 }; 4473 }; 4474 }; 4475 4476 mdss1_dp2: displayport-controller@2209a000 { 4477 compatible = "qcom,sc8280xp-dp"; 4478 reg = <0 0x2209a000 0 0x200>, 4479 <0 0x2209a200 0 0x200>, 4480 <0 0x2209a400 0 0x600>, 4481 <0 0x2209b000 0 0x400>, 4482 <0 0x2209b400 0 0x400>; 4483 4484 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 4485 <&dispcc1 DISP_CC_MDSS_DPTX2_AUX_CLK>, 4486 <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_CLK>, 4487 <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>, 4488 <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>; 4489 clock-names = "core_iface", "core_aux", 4490 "ctrl_link", 4491 "ctrl_link_iface", "stream_pixel"; 4492 interrupt-parent = <&mdss1>; 4493 interrupts = <14>; 4494 phys = <&mdss1_dp2_phy>; 4495 phy-names = "dp"; 4496 power-domains = <&rpmhpd SC8280XP_MMCX>; 4497 4498 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>, 4499 <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>; 4500 assigned-clock-parents = <&mdss1_dp2_phy 0>, <&mdss1_dp2_phy 1>; 4501 operating-points-v2 = <&mdss1_dp2_opp_table>; 4502 4503 #sound-dai-cells = <0>; 4504 4505 status = "disabled"; 4506 4507 ports { 4508 #address-cells = <1>; 4509 #size-cells = <0>; 4510 4511 port@0 { 4512 reg = <0>; 4513 mdss1_dp2_in: endpoint { 4514 remote-endpoint = <&mdss1_intf6_out>; 4515 }; 4516 }; 4517 4518 port@1 { 4519 reg = <1>; 4520 }; 4521 }; 4522 4523 mdss1_dp2_opp_table: opp-table { 4524 compatible = "operating-points-v2"; 4525 4526 opp-160000000 { 4527 opp-hz = /bits/ 64 <160000000>; 4528 required-opps = <&rpmhpd_opp_low_svs>; 4529 }; 4530 4531 opp-270000000 { 4532 opp-hz = /bits/ 64 <270000000>; 4533 required-opps = <&rpmhpd_opp_svs>; 4534 }; 4535 4536 opp-540000000 { 4537 opp-hz = /bits/ 64 <540000000>; 4538 required-opps = <&rpmhpd_opp_svs_l1>; 4539 }; 4540 4541 opp-810000000 { 4542 opp-hz = /bits/ 64 <810000000>; 4543 required-opps = <&rpmhpd_opp_nom>; 4544 }; 4545 }; 4546 }; 4547 4548 mdss1_dp3: displayport-controller@220a0000 { 4549 compatible = "qcom,sc8280xp-dp"; 4550 reg = <0 0x220a0000 0 0x200>, 4551 <0 0x220a0200 0 0x200>, 4552 <0 0x220a0400 0 0x600>, 4553 <0 0x220a1000 0 0x400>, 4554 <0 0x220a1400 0 0x400>; 4555 4556 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 4557 <&dispcc1 DISP_CC_MDSS_DPTX3_AUX_CLK>, 4558 <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_CLK>, 4559 <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>, 4560 <&dispcc1 DISP_CC_MDSS_DPTX3_PIXEL0_CLK>; 4561 clock-names = "core_iface", "core_aux", 4562 "ctrl_link", 4563 "ctrl_link_iface", "stream_pixel"; 4564 interrupt-parent = <&mdss1>; 4565 interrupts = <15>; 4566 phys = <&mdss1_dp3_phy>; 4567 phy-names = "dp"; 4568 power-domains = <&rpmhpd SC8280XP_MMCX>; 4569 4570 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>, 4571 <&dispcc1 DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>; 4572 assigned-clock-parents = <&mdss1_dp3_phy 0>, <&mdss1_dp3_phy 1>; 4573 operating-points-v2 = <&mdss1_dp3_opp_table>; 4574 4575 #sound-dai-cells = <0>; 4576 4577 status = "disabled"; 4578 4579 ports { 4580 #address-cells = <1>; 4581 #size-cells = <0>; 4582 4583 port@0 { 4584 reg = <0>; 4585 mdss1_dp3_in: endpoint { 4586 remote-endpoint = <&mdss1_intf5_out>; 4587 }; 4588 }; 4589 4590 port@1 { 4591 reg = <1>; 4592 }; 4593 }; 4594 4595 mdss1_dp3_opp_table: opp-table { 4596 compatible = "operating-points-v2"; 4597 4598 opp-160000000 { 4599 opp-hz = /bits/ 64 <160000000>; 4600 required-opps = <&rpmhpd_opp_low_svs>; 4601 }; 4602 4603 opp-270000000 { 4604 opp-hz = /bits/ 64 <270000000>; 4605 required-opps = <&rpmhpd_opp_svs>; 4606 }; 4607 4608 opp-540000000 { 4609 opp-hz = /bits/ 64 <540000000>; 4610 required-opps = <&rpmhpd_opp_svs_l1>; 4611 }; 4612 4613 opp-810000000 { 4614 opp-hz = /bits/ 64 <810000000>; 4615 required-opps = <&rpmhpd_opp_nom>; 4616 }; 4617 }; 4618 }; 4619 }; 4620 4621 mdss1_dp2_phy: phy@220c2a00 { 4622 compatible = "qcom,sc8280xp-dp-phy"; 4623 reg = <0 0x220c2a00 0 0x19c>, 4624 <0 0x220c2200 0 0xec>, 4625 <0 0x220c2600 0 0xec>, 4626 <0 0x220c2000 0 0x1c8>; 4627 4628 clocks = <&dispcc1 DISP_CC_MDSS_DPTX2_AUX_CLK>, 4629 <&dispcc1 DISP_CC_MDSS_AHB_CLK>; 4630 clock-names = "aux", "cfg_ahb"; 4631 power-domains = <&rpmhpd SC8280XP_MX>; 4632 4633 #clock-cells = <1>; 4634 #phy-cells = <0>; 4635 4636 status = "disabled"; 4637 }; 4638 4639 mdss1_dp3_phy: phy@220c5a00 { 4640 compatible = "qcom,sc8280xp-dp-phy"; 4641 reg = <0 0x220c5a00 0 0x19c>, 4642 <0 0x220c5200 0 0xec>, 4643 <0 0x220c5600 0 0xec>, 4644 <0 0x220c5000 0 0x1c8>; 4645 4646 clocks = <&dispcc1 DISP_CC_MDSS_DPTX3_AUX_CLK>, 4647 <&dispcc1 DISP_CC_MDSS_AHB_CLK>; 4648 clock-names = "aux", "cfg_ahb"; 4649 power-domains = <&rpmhpd SC8280XP_MX>; 4650 4651 #clock-cells = <1>; 4652 #phy-cells = <0>; 4653 4654 status = "disabled"; 4655 }; 4656 4657 dispcc1: clock-controller@22100000 { 4658 compatible = "qcom,sc8280xp-dispcc1"; 4659 reg = <0 0x22100000 0 0x20000>; 4660 4661 clocks = <&gcc GCC_DISP_AHB_CLK>, 4662 <&rpmhcc RPMH_CXO_CLK>, 4663 <0>, 4664 <&mdss1_dp0_phy 0>, 4665 <&mdss1_dp0_phy 1>, 4666 <&mdss1_dp1_phy 0>, 4667 <&mdss1_dp1_phy 1>, 4668 <&mdss1_dp2_phy 0>, 4669 <&mdss1_dp2_phy 1>, 4670 <&mdss1_dp3_phy 0>, 4671 <&mdss1_dp3_phy 1>, 4672 <0>, 4673 <0>, 4674 <0>, 4675 <0>; 4676 power-domains = <&rpmhpd SC8280XP_MMCX>; 4677 4678 #clock-cells = <1>; 4679 #power-domain-cells = <1>; 4680 #reset-cells = <1>; 4681 4682 status = "disabled"; 4683 }; 4684 }; 4685 4686 sound: sound { 4687 }; 4688 4689 thermal-zones { 4690 cpu0-thermal { 4691 polling-delay-passive = <250>; 4692 polling-delay = <1000>; 4693 4694 thermal-sensors = <&tsens0 1>; 4695 4696 trips { 4697 cpu-crit { 4698 temperature = <110000>; 4699 hysteresis = <1000>; 4700 type = "critical"; 4701 }; 4702 }; 4703 }; 4704 4705 cpu1-thermal { 4706 polling-delay-passive = <250>; 4707 polling-delay = <1000>; 4708 4709 thermal-sensors = <&tsens0 2>; 4710 4711 trips { 4712 cpu-crit { 4713 temperature = <110000>; 4714 hysteresis = <1000>; 4715 type = "critical"; 4716 }; 4717 }; 4718 }; 4719 4720 cpu2-thermal { 4721 polling-delay-passive = <250>; 4722 polling-delay = <1000>; 4723 4724 thermal-sensors = <&tsens0 3>; 4725 4726 trips { 4727 cpu-crit { 4728 temperature = <110000>; 4729 hysteresis = <1000>; 4730 type = "critical"; 4731 }; 4732 }; 4733 }; 4734 4735 cpu3-thermal { 4736 polling-delay-passive = <250>; 4737 polling-delay = <1000>; 4738 4739 thermal-sensors = <&tsens0 4>; 4740 4741 trips { 4742 cpu-crit { 4743 temperature = <110000>; 4744 hysteresis = <1000>; 4745 type = "critical"; 4746 }; 4747 }; 4748 }; 4749 4750 cpu4-thermal { 4751 polling-delay-passive = <250>; 4752 polling-delay = <1000>; 4753 4754 thermal-sensors = <&tsens0 5>; 4755 4756 trips { 4757 cpu-crit { 4758 temperature = <110000>; 4759 hysteresis = <1000>; 4760 type = "critical"; 4761 }; 4762 }; 4763 }; 4764 4765 cpu5-thermal { 4766 polling-delay-passive = <250>; 4767 polling-delay = <1000>; 4768 4769 thermal-sensors = <&tsens0 6>; 4770 4771 trips { 4772 cpu-crit { 4773 temperature = <110000>; 4774 hysteresis = <1000>; 4775 type = "critical"; 4776 }; 4777 }; 4778 }; 4779 4780 cpu6-thermal { 4781 polling-delay-passive = <250>; 4782 polling-delay = <1000>; 4783 4784 thermal-sensors = <&tsens0 7>; 4785 4786 trips { 4787 cpu-crit { 4788 temperature = <110000>; 4789 hysteresis = <1000>; 4790 type = "critical"; 4791 }; 4792 }; 4793 }; 4794 4795 cpu7-thermal { 4796 polling-delay-passive = <250>; 4797 polling-delay = <1000>; 4798 4799 thermal-sensors = <&tsens0 8>; 4800 4801 trips { 4802 cpu-crit { 4803 temperature = <110000>; 4804 hysteresis = <1000>; 4805 type = "critical"; 4806 }; 4807 }; 4808 }; 4809 4810 cluster0-thermal { 4811 polling-delay-passive = <250>; 4812 polling-delay = <1000>; 4813 4814 thermal-sensors = <&tsens0 9>; 4815 4816 trips { 4817 cpu-crit { 4818 temperature = <110000>; 4819 hysteresis = <1000>; 4820 type = "critical"; 4821 }; 4822 }; 4823 }; 4824 4825 mem-thermal { 4826 polling-delay-passive = <250>; 4827 polling-delay = <1000>; 4828 4829 thermal-sensors = <&tsens1 15>; 4830 4831 trips { 4832 trip-point0 { 4833 temperature = <90000>; 4834 hysteresis = <2000>; 4835 type = "hot"; 4836 }; 4837 }; 4838 }; 4839 }; 4840 4841 timer { 4842 compatible = "arm,armv8-timer"; 4843 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4844 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4845 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4846 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 4847 }; 4848}; 4849