1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2021, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2022, Linaro Limited 5 */ 6 7#include <dt-bindings/clock/qcom,dispcc-sc8280xp.h> 8#include <dt-bindings/clock/qcom,gcc-sc8280xp.h> 9#include <dt-bindings/clock/qcom,gpucc-sc8280xp.h> 10#include <dt-bindings/clock/qcom,rpmh.h> 11#include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h> 12#include <dt-bindings/interconnect/qcom,osm-l3.h> 13#include <dt-bindings/interconnect/qcom,sc8280xp.h> 14#include <dt-bindings/interrupt-controller/arm-gic.h> 15#include <dt-bindings/mailbox/qcom-ipcc.h> 16#include <dt-bindings/phy/phy-qcom-qmp.h> 17#include <dt-bindings/power/qcom-rpmpd.h> 18#include <dt-bindings/soc/qcom,gpr.h> 19#include <dt-bindings/soc/qcom,rpmh-rsc.h> 20#include <dt-bindings/sound/qcom,q6afe.h> 21#include <dt-bindings/thermal/thermal.h> 22 23/ { 24 interrupt-parent = <&intc>; 25 26 #address-cells = <2>; 27 #size-cells = <2>; 28 29 clocks { 30 xo_board_clk: xo-board-clk { 31 compatible = "fixed-clock"; 32 #clock-cells = <0>; 33 }; 34 35 sleep_clk: sleep-clk { 36 compatible = "fixed-clock"; 37 #clock-cells = <0>; 38 clock-frequency = <32764>; 39 }; 40 }; 41 42 cpus { 43 #address-cells = <2>; 44 #size-cells = <0>; 45 46 CPU0: cpu@0 { 47 device_type = "cpu"; 48 compatible = "arm,cortex-a78c"; 49 reg = <0x0 0x0>; 50 clocks = <&cpufreq_hw 0>; 51 enable-method = "psci"; 52 capacity-dmips-mhz = <602>; 53 next-level-cache = <&L2_0>; 54 power-domains = <&CPU_PD0>; 55 power-domain-names = "psci"; 56 qcom,freq-domain = <&cpufreq_hw 0>; 57 operating-points-v2 = <&cpu0_opp_table>; 58 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 59 #cooling-cells = <2>; 60 L2_0: l2-cache { 61 compatible = "cache"; 62 cache-level = <2>; 63 cache-unified; 64 next-level-cache = <&L3_0>; 65 L3_0: l3-cache { 66 compatible = "cache"; 67 cache-level = <3>; 68 cache-unified; 69 }; 70 }; 71 }; 72 73 CPU1: cpu@100 { 74 device_type = "cpu"; 75 compatible = "arm,cortex-a78c"; 76 reg = <0x0 0x100>; 77 clocks = <&cpufreq_hw 0>; 78 enable-method = "psci"; 79 capacity-dmips-mhz = <602>; 80 next-level-cache = <&L2_100>; 81 power-domains = <&CPU_PD1>; 82 power-domain-names = "psci"; 83 qcom,freq-domain = <&cpufreq_hw 0>; 84 operating-points-v2 = <&cpu0_opp_table>; 85 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 86 #cooling-cells = <2>; 87 L2_100: l2-cache { 88 compatible = "cache"; 89 cache-level = <2>; 90 cache-unified; 91 next-level-cache = <&L3_0>; 92 }; 93 }; 94 95 CPU2: cpu@200 { 96 device_type = "cpu"; 97 compatible = "arm,cortex-a78c"; 98 reg = <0x0 0x200>; 99 clocks = <&cpufreq_hw 0>; 100 enable-method = "psci"; 101 capacity-dmips-mhz = <602>; 102 next-level-cache = <&L2_200>; 103 power-domains = <&CPU_PD2>; 104 power-domain-names = "psci"; 105 qcom,freq-domain = <&cpufreq_hw 0>; 106 operating-points-v2 = <&cpu0_opp_table>; 107 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 108 #cooling-cells = <2>; 109 L2_200: l2-cache { 110 compatible = "cache"; 111 cache-level = <2>; 112 cache-unified; 113 next-level-cache = <&L3_0>; 114 }; 115 }; 116 117 CPU3: cpu@300 { 118 device_type = "cpu"; 119 compatible = "arm,cortex-a78c"; 120 reg = <0x0 0x300>; 121 clocks = <&cpufreq_hw 0>; 122 enable-method = "psci"; 123 capacity-dmips-mhz = <602>; 124 next-level-cache = <&L2_300>; 125 power-domains = <&CPU_PD3>; 126 power-domain-names = "psci"; 127 qcom,freq-domain = <&cpufreq_hw 0>; 128 operating-points-v2 = <&cpu0_opp_table>; 129 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 130 #cooling-cells = <2>; 131 L2_300: l2-cache { 132 compatible = "cache"; 133 cache-level = <2>; 134 cache-unified; 135 next-level-cache = <&L3_0>; 136 }; 137 }; 138 139 CPU4: cpu@400 { 140 device_type = "cpu"; 141 compatible = "arm,cortex-x1c"; 142 reg = <0x0 0x400>; 143 clocks = <&cpufreq_hw 1>; 144 enable-method = "psci"; 145 capacity-dmips-mhz = <1024>; 146 next-level-cache = <&L2_400>; 147 power-domains = <&CPU_PD4>; 148 power-domain-names = "psci"; 149 qcom,freq-domain = <&cpufreq_hw 1>; 150 operating-points-v2 = <&cpu4_opp_table>; 151 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 152 #cooling-cells = <2>; 153 L2_400: l2-cache { 154 compatible = "cache"; 155 cache-level = <2>; 156 cache-unified; 157 next-level-cache = <&L3_0>; 158 }; 159 }; 160 161 CPU5: cpu@500 { 162 device_type = "cpu"; 163 compatible = "arm,cortex-x1c"; 164 reg = <0x0 0x500>; 165 clocks = <&cpufreq_hw 1>; 166 enable-method = "psci"; 167 capacity-dmips-mhz = <1024>; 168 next-level-cache = <&L2_500>; 169 power-domains = <&CPU_PD5>; 170 power-domain-names = "psci"; 171 qcom,freq-domain = <&cpufreq_hw 1>; 172 operating-points-v2 = <&cpu4_opp_table>; 173 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 174 #cooling-cells = <2>; 175 L2_500: l2-cache { 176 compatible = "cache"; 177 cache-level = <2>; 178 cache-unified; 179 next-level-cache = <&L3_0>; 180 }; 181 }; 182 183 CPU6: cpu@600 { 184 device_type = "cpu"; 185 compatible = "arm,cortex-x1c"; 186 reg = <0x0 0x600>; 187 clocks = <&cpufreq_hw 1>; 188 enable-method = "psci"; 189 capacity-dmips-mhz = <1024>; 190 next-level-cache = <&L2_600>; 191 power-domains = <&CPU_PD6>; 192 power-domain-names = "psci"; 193 qcom,freq-domain = <&cpufreq_hw 1>; 194 operating-points-v2 = <&cpu4_opp_table>; 195 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 196 #cooling-cells = <2>; 197 L2_600: l2-cache { 198 compatible = "cache"; 199 cache-level = <2>; 200 cache-unified; 201 next-level-cache = <&L3_0>; 202 }; 203 }; 204 205 CPU7: cpu@700 { 206 device_type = "cpu"; 207 compatible = "arm,cortex-x1c"; 208 reg = <0x0 0x700>; 209 clocks = <&cpufreq_hw 1>; 210 enable-method = "psci"; 211 capacity-dmips-mhz = <1024>; 212 next-level-cache = <&L2_700>; 213 power-domains = <&CPU_PD7>; 214 power-domain-names = "psci"; 215 qcom,freq-domain = <&cpufreq_hw 1>; 216 operating-points-v2 = <&cpu4_opp_table>; 217 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 218 #cooling-cells = <2>; 219 L2_700: l2-cache { 220 compatible = "cache"; 221 cache-level = <2>; 222 cache-unified; 223 next-level-cache = <&L3_0>; 224 }; 225 }; 226 227 cpu-map { 228 cluster0 { 229 core0 { 230 cpu = <&CPU0>; 231 }; 232 233 core1 { 234 cpu = <&CPU1>; 235 }; 236 237 core2 { 238 cpu = <&CPU2>; 239 }; 240 241 core3 { 242 cpu = <&CPU3>; 243 }; 244 245 core4 { 246 cpu = <&CPU4>; 247 }; 248 249 core5 { 250 cpu = <&CPU5>; 251 }; 252 253 core6 { 254 cpu = <&CPU6>; 255 }; 256 257 core7 { 258 cpu = <&CPU7>; 259 }; 260 }; 261 }; 262 263 idle-states { 264 entry-method = "psci"; 265 266 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 267 compatible = "arm,idle-state"; 268 idle-state-name = "little-rail-power-collapse"; 269 arm,psci-suspend-param = <0x40000004>; 270 entry-latency-us = <355>; 271 exit-latency-us = <909>; 272 min-residency-us = <3934>; 273 local-timer-stop; 274 }; 275 276 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 277 compatible = "arm,idle-state"; 278 idle-state-name = "big-rail-power-collapse"; 279 arm,psci-suspend-param = <0x40000004>; 280 entry-latency-us = <241>; 281 exit-latency-us = <1461>; 282 min-residency-us = <4488>; 283 local-timer-stop; 284 }; 285 }; 286 287 domain-idle-states { 288 CLUSTER_SLEEP_0: cluster-sleep-0 { 289 compatible = "domain-idle-state"; 290 arm,psci-suspend-param = <0x4100c344>; 291 entry-latency-us = <3263>; 292 exit-latency-us = <6562>; 293 min-residency-us = <9987>; 294 }; 295 }; 296 }; 297 298 firmware { 299 scm: scm { 300 compatible = "qcom,scm-sc8280xp", "qcom,scm"; 301 }; 302 }; 303 304 aggre1_noc: interconnect-aggre1-noc { 305 compatible = "qcom,sc8280xp-aggre1-noc"; 306 #interconnect-cells = <2>; 307 qcom,bcm-voters = <&apps_bcm_voter>; 308 }; 309 310 aggre2_noc: interconnect-aggre2-noc { 311 compatible = "qcom,sc8280xp-aggre2-noc"; 312 #interconnect-cells = <2>; 313 qcom,bcm-voters = <&apps_bcm_voter>; 314 }; 315 316 clk_virt: interconnect-clk-virt { 317 compatible = "qcom,sc8280xp-clk-virt"; 318 #interconnect-cells = <2>; 319 qcom,bcm-voters = <&apps_bcm_voter>; 320 }; 321 322 config_noc: interconnect-config-noc { 323 compatible = "qcom,sc8280xp-config-noc"; 324 #interconnect-cells = <2>; 325 qcom,bcm-voters = <&apps_bcm_voter>; 326 }; 327 328 dc_noc: interconnect-dc-noc { 329 compatible = "qcom,sc8280xp-dc-noc"; 330 #interconnect-cells = <2>; 331 qcom,bcm-voters = <&apps_bcm_voter>; 332 }; 333 334 gem_noc: interconnect-gem-noc { 335 compatible = "qcom,sc8280xp-gem-noc"; 336 #interconnect-cells = <2>; 337 qcom,bcm-voters = <&apps_bcm_voter>; 338 }; 339 340 lpass_noc: interconnect-lpass-ag-noc { 341 compatible = "qcom,sc8280xp-lpass-ag-noc"; 342 #interconnect-cells = <2>; 343 qcom,bcm-voters = <&apps_bcm_voter>; 344 }; 345 346 mc_virt: interconnect-mc-virt { 347 compatible = "qcom,sc8280xp-mc-virt"; 348 #interconnect-cells = <2>; 349 qcom,bcm-voters = <&apps_bcm_voter>; 350 }; 351 352 mmss_noc: interconnect-mmss-noc { 353 compatible = "qcom,sc8280xp-mmss-noc"; 354 #interconnect-cells = <2>; 355 qcom,bcm-voters = <&apps_bcm_voter>; 356 }; 357 358 nspa_noc: interconnect-nspa-noc { 359 compatible = "qcom,sc8280xp-nspa-noc"; 360 #interconnect-cells = <2>; 361 qcom,bcm-voters = <&apps_bcm_voter>; 362 }; 363 364 nspb_noc: interconnect-nspb-noc { 365 compatible = "qcom,sc8280xp-nspb-noc"; 366 #interconnect-cells = <2>; 367 qcom,bcm-voters = <&apps_bcm_voter>; 368 }; 369 370 system_noc: interconnect-system-noc { 371 compatible = "qcom,sc8280xp-system-noc"; 372 #interconnect-cells = <2>; 373 qcom,bcm-voters = <&apps_bcm_voter>; 374 }; 375 376 memory@80000000 { 377 device_type = "memory"; 378 /* We expect the bootloader to fill in the size */ 379 reg = <0x0 0x80000000 0x0 0x0>; 380 }; 381 382 cpu0_opp_table: opp-table-cpu0 { 383 compatible = "operating-points-v2"; 384 opp-shared; 385 386 opp-300000000 { 387 opp-hz = /bits/ 64 <300000000>; 388 opp-peak-kBps = <(300000 * 32)>; 389 }; 390 opp-403200000 { 391 opp-hz = /bits/ 64 <403200000>; 392 opp-peak-kBps = <(384000 * 32)>; 393 }; 394 opp-499200000 { 395 opp-hz = /bits/ 64 <499200000>; 396 opp-peak-kBps = <(480000 * 32)>; 397 }; 398 opp-595200000 { 399 opp-hz = /bits/ 64 <595200000>; 400 opp-peak-kBps = <(576000 * 32)>; 401 }; 402 opp-691200000 { 403 opp-hz = /bits/ 64 <691200000>; 404 opp-peak-kBps = <(672000 * 32)>; 405 }; 406 opp-806400000 { 407 opp-hz = /bits/ 64 <806400000>; 408 opp-peak-kBps = <(768000 * 32)>; 409 }; 410 opp-902400000 { 411 opp-hz = /bits/ 64 <902400000>; 412 opp-peak-kBps = <(864000 * 32)>; 413 }; 414 opp-1017600000 { 415 opp-hz = /bits/ 64 <1017600000>; 416 opp-peak-kBps = <(960000 * 32)>; 417 }; 418 opp-1113600000 { 419 opp-hz = /bits/ 64 <1113600000>; 420 opp-peak-kBps = <(1075200 * 32)>; 421 }; 422 opp-1209600000 { 423 opp-hz = /bits/ 64 <1209600000>; 424 opp-peak-kBps = <(1171200 * 32)>; 425 }; 426 opp-1324800000 { 427 opp-hz = /bits/ 64 <1324800000>; 428 opp-peak-kBps = <(1267200 * 32)>; 429 }; 430 opp-1440000000 { 431 opp-hz = /bits/ 64 <1440000000>; 432 opp-peak-kBps = <(1363200 * 32)>; 433 }; 434 opp-1555200000 { 435 opp-hz = /bits/ 64 <1555200000>; 436 opp-peak-kBps = <(1536000 * 32)>; 437 }; 438 opp-1670400000 { 439 opp-hz = /bits/ 64 <1670400000>; 440 opp-peak-kBps = <(1612800 * 32)>; 441 }; 442 opp-1785600000 { 443 opp-hz = /bits/ 64 <1785600000>; 444 opp-peak-kBps = <(1689600 * 32)>; 445 }; 446 opp-1881600000 { 447 opp-hz = /bits/ 64 <1881600000>; 448 opp-peak-kBps = <(1689600 * 32)>; 449 }; 450 opp-1996800000 { 451 opp-hz = /bits/ 64 <1996800000>; 452 opp-peak-kBps = <(1689600 * 32)>; 453 }; 454 opp-2112000000 { 455 opp-hz = /bits/ 64 <2112000000>; 456 opp-peak-kBps = <(1689600 * 32)>; 457 }; 458 opp-2227200000 { 459 opp-hz = /bits/ 64 <2227200000>; 460 opp-peak-kBps = <(1689600 * 32)>; 461 }; 462 opp-2342400000 { 463 opp-hz = /bits/ 64 <2342400000>; 464 opp-peak-kBps = <(1689600 * 32)>; 465 }; 466 opp-2438400000 { 467 opp-hz = /bits/ 64 <2438400000>; 468 opp-peak-kBps = <(1689600 * 32)>; 469 }; 470 }; 471 472 cpu4_opp_table: opp-table-cpu4 { 473 compatible = "operating-points-v2"; 474 opp-shared; 475 476 opp-825600000 { 477 opp-hz = /bits/ 64 <825600000>; 478 opp-peak-kBps = <(768000 * 32)>; 479 }; 480 opp-940800000 { 481 opp-hz = /bits/ 64 <940800000>; 482 opp-peak-kBps = <(864000 * 32)>; 483 }; 484 opp-1056000000 { 485 opp-hz = /bits/ 64 <1056000000>; 486 opp-peak-kBps = <(960000 * 32)>; 487 }; 488 opp-1171200000 { 489 opp-hz = /bits/ 64 <1171200000>; 490 opp-peak-kBps = <(1171200 * 32)>; 491 }; 492 opp-1286400000 { 493 opp-hz = /bits/ 64 <1286400000>; 494 opp-peak-kBps = <(1267200 * 32)>; 495 }; 496 opp-1401600000 { 497 opp-hz = /bits/ 64 <1401600000>; 498 opp-peak-kBps = <(1363200 * 32)>; 499 }; 500 opp-1516800000 { 501 opp-hz = /bits/ 64 <1516800000>; 502 opp-peak-kBps = <(1459200 * 32)>; 503 }; 504 opp-1632000000 { 505 opp-hz = /bits/ 64 <1632000000>; 506 opp-peak-kBps = <(1612800 * 32)>; 507 }; 508 opp-1747200000 { 509 opp-hz = /bits/ 64 <1747200000>; 510 opp-peak-kBps = <(1689600 * 32)>; 511 }; 512 opp-1862400000 { 513 opp-hz = /bits/ 64 <1862400000>; 514 opp-peak-kBps = <(1689600 * 32)>; 515 }; 516 opp-1977600000 { 517 opp-hz = /bits/ 64 <1977600000>; 518 opp-peak-kBps = <(1689600 * 32)>; 519 }; 520 opp-2073600000 { 521 opp-hz = /bits/ 64 <2073600000>; 522 opp-peak-kBps = <(1689600 * 32)>; 523 }; 524 opp-2169600000 { 525 opp-hz = /bits/ 64 <2169600000>; 526 opp-peak-kBps = <(1689600 * 32)>; 527 }; 528 opp-2284800000 { 529 opp-hz = /bits/ 64 <2284800000>; 530 opp-peak-kBps = <(1689600 * 32)>; 531 }; 532 opp-2400000000 { 533 opp-hz = /bits/ 64 <2400000000>; 534 opp-peak-kBps = <(1689600 * 32)>; 535 }; 536 opp-2496000000 { 537 opp-hz = /bits/ 64 <2496000000>; 538 opp-peak-kBps = <(1689600 * 32)>; 539 }; 540 opp-2592000000 { 541 opp-hz = /bits/ 64 <2592000000>; 542 opp-peak-kBps = <(1689600 * 32)>; 543 }; 544 opp-2688000000 { 545 opp-hz = /bits/ 64 <2688000000>; 546 opp-peak-kBps = <(1689600 * 32)>; 547 }; 548 opp-2803200000 { 549 opp-hz = /bits/ 64 <2803200000>; 550 opp-peak-kBps = <(1689600 * 32)>; 551 }; 552 opp-2899200000 { 553 opp-hz = /bits/ 64 <2899200000>; 554 opp-peak-kBps = <(1689600 * 32)>; 555 }; 556 opp-2995200000 { 557 opp-hz = /bits/ 64 <2995200000>; 558 opp-peak-kBps = <(1689600 * 32)>; 559 }; 560 }; 561 562 qup_opp_table_100mhz: opp-table-qup100mhz { 563 compatible = "operating-points-v2"; 564 565 opp-75000000 { 566 opp-hz = /bits/ 64 <75000000>; 567 required-opps = <&rpmhpd_opp_low_svs>; 568 }; 569 570 opp-100000000 { 571 opp-hz = /bits/ 64 <100000000>; 572 required-opps = <&rpmhpd_opp_svs>; 573 }; 574 }; 575 576 pmu { 577 compatible = "arm,armv8-pmuv3"; 578 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 579 }; 580 581 psci { 582 compatible = "arm,psci-1.0"; 583 method = "smc"; 584 585 CPU_PD0: power-domain-cpu0 { 586 #power-domain-cells = <0>; 587 power-domains = <&CLUSTER_PD>; 588 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 589 }; 590 591 CPU_PD1: power-domain-cpu1 { 592 #power-domain-cells = <0>; 593 power-domains = <&CLUSTER_PD>; 594 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 595 }; 596 597 CPU_PD2: power-domain-cpu2 { 598 #power-domain-cells = <0>; 599 power-domains = <&CLUSTER_PD>; 600 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 601 }; 602 603 CPU_PD3: power-domain-cpu3 { 604 #power-domain-cells = <0>; 605 power-domains = <&CLUSTER_PD>; 606 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 607 }; 608 609 CPU_PD4: power-domain-cpu4 { 610 #power-domain-cells = <0>; 611 power-domains = <&CLUSTER_PD>; 612 domain-idle-states = <&BIG_CPU_SLEEP_0>; 613 }; 614 615 CPU_PD5: power-domain-cpu5 { 616 #power-domain-cells = <0>; 617 power-domains = <&CLUSTER_PD>; 618 domain-idle-states = <&BIG_CPU_SLEEP_0>; 619 }; 620 621 CPU_PD6: power-domain-cpu6 { 622 #power-domain-cells = <0>; 623 power-domains = <&CLUSTER_PD>; 624 domain-idle-states = <&BIG_CPU_SLEEP_0>; 625 }; 626 627 CPU_PD7: power-domain-cpu7 { 628 #power-domain-cells = <0>; 629 power-domains = <&CLUSTER_PD>; 630 domain-idle-states = <&BIG_CPU_SLEEP_0>; 631 }; 632 633 CLUSTER_PD: power-domain-cpu-cluster0 { 634 #power-domain-cells = <0>; 635 domain-idle-states = <&CLUSTER_SLEEP_0>; 636 }; 637 }; 638 639 reserved-memory { 640 #address-cells = <2>; 641 #size-cells = <2>; 642 ranges; 643 644 reserved-region@80000000 { 645 reg = <0 0x80000000 0 0x860000>; 646 no-map; 647 }; 648 649 cmd_db: cmd-db-region@80860000 { 650 compatible = "qcom,cmd-db"; 651 reg = <0 0x80860000 0 0x20000>; 652 no-map; 653 }; 654 655 reserved-region@80880000 { 656 reg = <0 0x80880000 0 0x80000>; 657 no-map; 658 }; 659 660 smem_mem: smem-region@80900000 { 661 compatible = "qcom,smem"; 662 reg = <0 0x80900000 0 0x200000>; 663 no-map; 664 hwlocks = <&tcsr_mutex 3>; 665 }; 666 667 reserved-region@80b00000 { 668 reg = <0 0x80b00000 0 0x100000>; 669 no-map; 670 }; 671 672 reserved-region@83b00000 { 673 reg = <0 0x83b00000 0 0x1700000>; 674 no-map; 675 }; 676 677 reserved-region@85b00000 { 678 reg = <0 0x85b00000 0 0xc00000>; 679 no-map; 680 }; 681 682 pil_adsp_mem: adsp-region@86c00000 { 683 reg = <0 0x86c00000 0 0x2000000>; 684 no-map; 685 }; 686 687 pil_nsp0_mem: cdsp0-region@8a100000 { 688 reg = <0 0x8a100000 0 0x1e00000>; 689 no-map; 690 }; 691 692 pil_nsp1_mem: cdsp1-region@8c600000 { 693 reg = <0 0x8c600000 0 0x1e00000>; 694 no-map; 695 }; 696 697 reserved-region@aeb00000 { 698 reg = <0 0xaeb00000 0 0x16600000>; 699 no-map; 700 }; 701 }; 702 703 smp2p-adsp { 704 compatible = "qcom,smp2p"; 705 qcom,smem = <443>, <429>; 706 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 707 IPCC_MPROC_SIGNAL_SMP2P 708 IRQ_TYPE_EDGE_RISING>; 709 mboxes = <&ipcc IPCC_CLIENT_LPASS 710 IPCC_MPROC_SIGNAL_SMP2P>; 711 712 qcom,local-pid = <0>; 713 qcom,remote-pid = <2>; 714 715 smp2p_adsp_out: master-kernel { 716 qcom,entry-name = "master-kernel"; 717 #qcom,smem-state-cells = <1>; 718 }; 719 720 smp2p_adsp_in: slave-kernel { 721 qcom,entry-name = "slave-kernel"; 722 interrupt-controller; 723 #interrupt-cells = <2>; 724 }; 725 }; 726 727 smp2p-nsp0 { 728 compatible = "qcom,smp2p"; 729 qcom,smem = <94>, <432>; 730 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 731 IPCC_MPROC_SIGNAL_SMP2P 732 IRQ_TYPE_EDGE_RISING>; 733 mboxes = <&ipcc IPCC_CLIENT_CDSP 734 IPCC_MPROC_SIGNAL_SMP2P>; 735 736 qcom,local-pid = <0>; 737 qcom,remote-pid = <5>; 738 739 smp2p_nsp0_out: master-kernel { 740 qcom,entry-name = "master-kernel"; 741 #qcom,smem-state-cells = <1>; 742 }; 743 744 smp2p_nsp0_in: slave-kernel { 745 qcom,entry-name = "slave-kernel"; 746 interrupt-controller; 747 #interrupt-cells = <2>; 748 }; 749 }; 750 751 smp2p-nsp1 { 752 compatible = "qcom,smp2p"; 753 qcom,smem = <617>, <616>; 754 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1 755 IPCC_MPROC_SIGNAL_SMP2P 756 IRQ_TYPE_EDGE_RISING>; 757 mboxes = <&ipcc IPCC_CLIENT_NSP1 758 IPCC_MPROC_SIGNAL_SMP2P>; 759 760 qcom,local-pid = <0>; 761 qcom,remote-pid = <12>; 762 763 smp2p_nsp1_out: master-kernel { 764 qcom,entry-name = "master-kernel"; 765 #qcom,smem-state-cells = <1>; 766 }; 767 768 smp2p_nsp1_in: slave-kernel { 769 qcom,entry-name = "slave-kernel"; 770 interrupt-controller; 771 #interrupt-cells = <2>; 772 }; 773 }; 774 775 soc: soc@0 { 776 compatible = "simple-bus"; 777 #address-cells = <2>; 778 #size-cells = <2>; 779 ranges = <0 0 0 0 0x10 0>; 780 dma-ranges = <0 0 0 0 0x10 0>; 781 782 ethernet0: ethernet@20000 { 783 compatible = "qcom,sc8280xp-ethqos"; 784 reg = <0x0 0x00020000 0x0 0x10000>, 785 <0x0 0x00036000 0x0 0x100>; 786 reg-names = "stmmaceth", "rgmii"; 787 788 clocks = <&gcc GCC_EMAC0_AXI_CLK>, 789 <&gcc GCC_EMAC0_SLV_AHB_CLK>, 790 <&gcc GCC_EMAC0_PTP_CLK>, 791 <&gcc GCC_EMAC0_RGMII_CLK>; 792 clock-names = "stmmaceth", 793 "pclk", 794 "ptp_ref", 795 "rgmii"; 796 797 interrupts = <GIC_SPI 946 IRQ_TYPE_LEVEL_HIGH>, 798 <GIC_SPI 936 IRQ_TYPE_LEVEL_HIGH>; 799 interrupt-names = "macirq", "eth_lpi"; 800 801 iommus = <&apps_smmu 0x4c0 0xf>; 802 power-domains = <&gcc EMAC_0_GDSC>; 803 804 snps,tso; 805 snps,pbl = <32>; 806 rx-fifo-depth = <4096>; 807 tx-fifo-depth = <4096>; 808 809 status = "disabled"; 810 }; 811 812 gcc: clock-controller@100000 { 813 compatible = "qcom,gcc-sc8280xp"; 814 reg = <0x0 0x00100000 0x0 0x1f0000>; 815 #clock-cells = <1>; 816 #reset-cells = <1>; 817 #power-domain-cells = <1>; 818 clocks = <&rpmhcc RPMH_CXO_CLK>, 819 <&sleep_clk>, 820 <0>, 821 <0>, 822 <0>, 823 <0>, 824 <0>, 825 <0>, 826 <&usb_0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 827 <0>, 828 <0>, 829 <0>, 830 <0>, 831 <0>, 832 <0>, 833 <0>, 834 <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 835 <0>, 836 <0>, 837 <0>, 838 <0>, 839 <0>, 840 <0>, 841 <0>, 842 <0>, 843 <0>, 844 <&pcie2a_phy>, 845 <&pcie2b_phy>, 846 <&pcie3a_phy>, 847 <&pcie3b_phy>, 848 <&pcie4_phy>, 849 <0>, 850 <0>; 851 power-domains = <&rpmhpd SC8280XP_CX>; 852 }; 853 854 ipcc: mailbox@408000 { 855 compatible = "qcom,sc8280xp-ipcc", "qcom,ipcc"; 856 reg = <0 0x00408000 0 0x1000>; 857 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 858 interrupt-controller; 859 #interrupt-cells = <3>; 860 #mbox-cells = <2>; 861 }; 862 863 qup2: geniqup@8c0000 { 864 compatible = "qcom,geni-se-qup"; 865 reg = <0 0x008c0000 0 0x2000>; 866 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 867 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 868 clock-names = "m-ahb", "s-ahb"; 869 iommus = <&apps_smmu 0xa3 0>; 870 871 #address-cells = <2>; 872 #size-cells = <2>; 873 ranges; 874 875 status = "disabled"; 876 877 i2c16: i2c@880000 { 878 compatible = "qcom,geni-i2c"; 879 reg = <0 0x00880000 0 0x4000>; 880 #address-cells = <1>; 881 #size-cells = <0>; 882 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 883 clock-names = "se"; 884 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 885 power-domains = <&rpmhpd SC8280XP_CX>; 886 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 887 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 888 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 889 interconnect-names = "qup-core", "qup-config", "qup-memory"; 890 status = "disabled"; 891 }; 892 893 spi16: spi@880000 { 894 compatible = "qcom,geni-spi"; 895 reg = <0 0x00880000 0 0x4000>; 896 #address-cells = <1>; 897 #size-cells = <0>; 898 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 899 clock-names = "se"; 900 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 901 power-domains = <&rpmhpd SC8280XP_CX>; 902 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 903 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 904 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 905 interconnect-names = "qup-core", "qup-config", "qup-memory"; 906 status = "disabled"; 907 }; 908 909 i2c17: i2c@884000 { 910 compatible = "qcom,geni-i2c"; 911 reg = <0 0x00884000 0 0x4000>; 912 #address-cells = <1>; 913 #size-cells = <0>; 914 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 915 clock-names = "se"; 916 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 917 power-domains = <&rpmhpd SC8280XP_CX>; 918 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 919 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 920 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 921 interconnect-names = "qup-core", "qup-config", "qup-memory"; 922 status = "disabled"; 923 }; 924 925 spi17: spi@884000 { 926 compatible = "qcom,geni-spi"; 927 reg = <0 0x00884000 0 0x4000>; 928 #address-cells = <1>; 929 #size-cells = <0>; 930 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 931 clock-names = "se"; 932 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 933 power-domains = <&rpmhpd SC8280XP_CX>; 934 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 935 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 936 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 937 interconnect-names = "qup-core", "qup-config", "qup-memory"; 938 status = "disabled"; 939 }; 940 941 uart17: serial@884000 { 942 compatible = "qcom,geni-uart"; 943 reg = <0 0x00884000 0 0x4000>; 944 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 945 clock-names = "se"; 946 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 947 operating-points-v2 = <&qup_opp_table_100mhz>; 948 power-domains = <&rpmhpd SC8280XP_CX>; 949 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 950 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>; 951 interconnect-names = "qup-core", "qup-config"; 952 status = "disabled"; 953 }; 954 955 i2c18: i2c@888000 { 956 compatible = "qcom,geni-i2c"; 957 reg = <0 0x00888000 0 0x4000>; 958 #address-cells = <1>; 959 #size-cells = <0>; 960 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 961 clock-names = "se"; 962 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 963 power-domains = <&rpmhpd SC8280XP_CX>; 964 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 965 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 966 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 967 interconnect-names = "qup-core", "qup-config", "qup-memory"; 968 status = "disabled"; 969 }; 970 971 spi18: spi@888000 { 972 compatible = "qcom,geni-spi"; 973 reg = <0 0x00888000 0 0x4000>; 974 #address-cells = <1>; 975 #size-cells = <0>; 976 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 977 clock-names = "se"; 978 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 979 power-domains = <&rpmhpd SC8280XP_CX>; 980 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 981 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 982 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 983 interconnect-names = "qup-core", "qup-config", "qup-memory"; 984 status = "disabled"; 985 }; 986 987 i2c19: i2c@88c000 { 988 compatible = "qcom,geni-i2c"; 989 reg = <0 0x0088c000 0 0x4000>; 990 #address-cells = <1>; 991 #size-cells = <0>; 992 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 993 clock-names = "se"; 994 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 995 power-domains = <&rpmhpd SC8280XP_CX>; 996 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 997 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 998 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 999 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1000 status = "disabled"; 1001 }; 1002 1003 spi19: spi@88c000 { 1004 compatible = "qcom,geni-spi"; 1005 reg = <0 0x0088c000 0 0x4000>; 1006 #address-cells = <1>; 1007 #size-cells = <0>; 1008 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1009 clock-names = "se"; 1010 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1011 power-domains = <&rpmhpd SC8280XP_CX>; 1012 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1013 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1014 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1015 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1016 status = "disabled"; 1017 }; 1018 1019 i2c20: i2c@890000 { 1020 compatible = "qcom,geni-i2c"; 1021 reg = <0 0x00890000 0 0x4000>; 1022 #address-cells = <1>; 1023 #size-cells = <0>; 1024 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1025 clock-names = "se"; 1026 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1027 power-domains = <&rpmhpd SC8280XP_CX>; 1028 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1029 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1030 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1031 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1032 status = "disabled"; 1033 }; 1034 1035 spi20: spi@890000 { 1036 compatible = "qcom,geni-spi"; 1037 reg = <0 0x00890000 0 0x4000>; 1038 #address-cells = <1>; 1039 #size-cells = <0>; 1040 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1041 clock-names = "se"; 1042 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1043 power-domains = <&rpmhpd SC8280XP_CX>; 1044 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1045 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1046 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1047 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1048 status = "disabled"; 1049 }; 1050 1051 i2c21: i2c@894000 { 1052 compatible = "qcom,geni-i2c"; 1053 reg = <0 0x00894000 0 0x4000>; 1054 clock-names = "se"; 1055 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1056 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1057 #address-cells = <1>; 1058 #size-cells = <0>; 1059 power-domains = <&rpmhpd SC8280XP_CX>; 1060 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1061 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1062 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1063 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1064 status = "disabled"; 1065 }; 1066 1067 spi21: spi@894000 { 1068 compatible = "qcom,geni-spi"; 1069 reg = <0 0x00894000 0 0x4000>; 1070 #address-cells = <1>; 1071 #size-cells = <0>; 1072 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1073 clock-names = "se"; 1074 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1075 power-domains = <&rpmhpd SC8280XP_CX>; 1076 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1077 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1078 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1079 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1080 status = "disabled"; 1081 }; 1082 1083 i2c22: i2c@898000 { 1084 compatible = "qcom,geni-i2c"; 1085 reg = <0 0x00898000 0 0x4000>; 1086 #address-cells = <1>; 1087 #size-cells = <0>; 1088 clock-names = "se"; 1089 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1090 interrupts = <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>; 1091 power-domains = <&rpmhpd SC8280XP_CX>; 1092 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1093 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1094 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1095 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1096 status = "disabled"; 1097 }; 1098 1099 spi22: spi@898000 { 1100 compatible = "qcom,geni-spi"; 1101 reg = <0 0x00898000 0 0x4000>; 1102 #address-cells = <1>; 1103 #size-cells = <0>; 1104 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1105 clock-names = "se"; 1106 interrupts = <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>; 1107 power-domains = <&rpmhpd SC8280XP_CX>; 1108 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1109 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1110 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1111 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1112 status = "disabled"; 1113 }; 1114 1115 i2c23: i2c@89c000 { 1116 compatible = "qcom,geni-i2c"; 1117 reg = <0 0x0089c000 0 0x4000>; 1118 #address-cells = <1>; 1119 #size-cells = <0>; 1120 clock-names = "se"; 1121 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1122 interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>; 1123 power-domains = <&rpmhpd SC8280XP_CX>; 1124 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1125 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1126 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1127 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1128 status = "disabled"; 1129 }; 1130 1131 spi23: spi@89c000 { 1132 compatible = "qcom,geni-spi"; 1133 reg = <0 0x0089c000 0 0x4000>; 1134 #address-cells = <1>; 1135 #size-cells = <0>; 1136 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1137 clock-names = "se"; 1138 interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>; 1139 power-domains = <&rpmhpd SC8280XP_CX>; 1140 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1141 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1142 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1143 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1144 status = "disabled"; 1145 }; 1146 }; 1147 1148 qup0: geniqup@9c0000 { 1149 compatible = "qcom,geni-se-qup"; 1150 reg = <0 0x009c0000 0 0x6000>; 1151 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1152 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1153 clock-names = "m-ahb", "s-ahb"; 1154 iommus = <&apps_smmu 0x563 0>; 1155 1156 #address-cells = <2>; 1157 #size-cells = <2>; 1158 ranges; 1159 1160 status = "disabled"; 1161 1162 i2c0: i2c@980000 { 1163 compatible = "qcom,geni-i2c"; 1164 reg = <0 0x00980000 0 0x4000>; 1165 #address-cells = <1>; 1166 #size-cells = <0>; 1167 clock-names = "se"; 1168 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1169 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1170 power-domains = <&rpmhpd SC8280XP_CX>; 1171 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1172 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1173 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1174 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1175 status = "disabled"; 1176 }; 1177 1178 spi0: spi@980000 { 1179 compatible = "qcom,geni-spi"; 1180 reg = <0 0x00980000 0 0x4000>; 1181 #address-cells = <1>; 1182 #size-cells = <0>; 1183 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1184 clock-names = "se"; 1185 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1186 power-domains = <&rpmhpd SC8280XP_CX>; 1187 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1188 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1189 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1190 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1191 status = "disabled"; 1192 }; 1193 1194 i2c1: i2c@984000 { 1195 compatible = "qcom,geni-i2c"; 1196 reg = <0 0x00984000 0 0x4000>; 1197 #address-cells = <1>; 1198 #size-cells = <0>; 1199 clock-names = "se"; 1200 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1201 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1202 power-domains = <&rpmhpd SC8280XP_CX>; 1203 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1204 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1205 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1206 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1207 status = "disabled"; 1208 }; 1209 1210 spi1: spi@984000 { 1211 compatible = "qcom,geni-spi"; 1212 reg = <0 0x00984000 0 0x4000>; 1213 #address-cells = <1>; 1214 #size-cells = <0>; 1215 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1216 clock-names = "se"; 1217 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1218 power-domains = <&rpmhpd SC8280XP_CX>; 1219 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1220 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1221 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1222 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1223 status = "disabled"; 1224 }; 1225 1226 i2c2: i2c@988000 { 1227 compatible = "qcom,geni-i2c"; 1228 reg = <0 0x00988000 0 0x4000>; 1229 #address-cells = <1>; 1230 #size-cells = <0>; 1231 clock-names = "se"; 1232 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1233 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1234 power-domains = <&rpmhpd SC8280XP_CX>; 1235 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1236 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1237 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1238 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1239 status = "disabled"; 1240 }; 1241 1242 spi2: spi@988000 { 1243 compatible = "qcom,geni-spi"; 1244 reg = <0 0x00988000 0 0x4000>; 1245 #address-cells = <1>; 1246 #size-cells = <0>; 1247 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1248 clock-names = "se"; 1249 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1250 power-domains = <&rpmhpd SC8280XP_CX>; 1251 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1252 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1253 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1254 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1255 status = "disabled"; 1256 }; 1257 1258 uart2: serial@988000 { 1259 compatible = "qcom,geni-uart"; 1260 reg = <0 0x00988000 0 0x4000>; 1261 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1262 clock-names = "se"; 1263 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1264 operating-points-v2 = <&qup_opp_table_100mhz>; 1265 power-domains = <&rpmhpd SC8280XP_CX>; 1266 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1267 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 1268 interconnect-names = "qup-core", "qup-config"; 1269 status = "disabled"; 1270 }; 1271 1272 i2c3: i2c@98c000 { 1273 compatible = "qcom,geni-i2c"; 1274 reg = <0 0x0098c000 0 0x4000>; 1275 #address-cells = <1>; 1276 #size-cells = <0>; 1277 clock-names = "se"; 1278 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1279 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1280 power-domains = <&rpmhpd SC8280XP_CX>; 1281 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1282 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1283 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1284 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1285 status = "disabled"; 1286 }; 1287 1288 spi3: spi@98c000 { 1289 compatible = "qcom,geni-spi"; 1290 reg = <0 0x0098c000 0 0x4000>; 1291 #address-cells = <1>; 1292 #size-cells = <0>; 1293 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1294 clock-names = "se"; 1295 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1296 power-domains = <&rpmhpd SC8280XP_CX>; 1297 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1298 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1299 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1300 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1301 status = "disabled"; 1302 }; 1303 1304 i2c4: i2c@990000 { 1305 compatible = "qcom,geni-i2c"; 1306 reg = <0 0x00990000 0 0x4000>; 1307 clock-names = "se"; 1308 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1309 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1310 #address-cells = <1>; 1311 #size-cells = <0>; 1312 power-domains = <&rpmhpd SC8280XP_CX>; 1313 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1314 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1315 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1316 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1317 status = "disabled"; 1318 }; 1319 1320 spi4: spi@990000 { 1321 compatible = "qcom,geni-spi"; 1322 reg = <0 0x00990000 0 0x4000>; 1323 #address-cells = <1>; 1324 #size-cells = <0>; 1325 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1326 clock-names = "se"; 1327 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1328 power-domains = <&rpmhpd SC8280XP_CX>; 1329 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1330 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1331 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1332 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1333 status = "disabled"; 1334 }; 1335 1336 i2c5: i2c@994000 { 1337 compatible = "qcom,geni-i2c"; 1338 reg = <0 0x00994000 0 0x4000>; 1339 #address-cells = <1>; 1340 #size-cells = <0>; 1341 clock-names = "se"; 1342 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1343 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1344 power-domains = <&rpmhpd SC8280XP_CX>; 1345 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1346 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1347 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1348 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1349 status = "disabled"; 1350 }; 1351 1352 spi5: spi@994000 { 1353 compatible = "qcom,geni-spi"; 1354 reg = <0 0x00994000 0 0x4000>; 1355 #address-cells = <1>; 1356 #size-cells = <0>; 1357 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1358 clock-names = "se"; 1359 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1360 power-domains = <&rpmhpd SC8280XP_CX>; 1361 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1362 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1363 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1364 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1365 status = "disabled"; 1366 }; 1367 1368 i2c6: i2c@998000 { 1369 compatible = "qcom,geni-i2c"; 1370 reg = <0 0x00998000 0 0x4000>; 1371 #address-cells = <1>; 1372 #size-cells = <0>; 1373 clock-names = "se"; 1374 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1375 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1376 power-domains = <&rpmhpd SC8280XP_CX>; 1377 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1378 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1379 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1380 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1381 status = "disabled"; 1382 }; 1383 1384 spi6: spi@998000 { 1385 compatible = "qcom,geni-spi"; 1386 reg = <0 0x00998000 0 0x4000>; 1387 #address-cells = <1>; 1388 #size-cells = <0>; 1389 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1390 clock-names = "se"; 1391 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1392 power-domains = <&rpmhpd SC8280XP_CX>; 1393 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1394 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1395 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1396 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1397 status = "disabled"; 1398 }; 1399 1400 i2c7: i2c@99c000 { 1401 compatible = "qcom,geni-i2c"; 1402 reg = <0 0x0099c000 0 0x4000>; 1403 #address-cells = <1>; 1404 #size-cells = <0>; 1405 clock-names = "se"; 1406 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1407 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1408 power-domains = <&rpmhpd SC8280XP_CX>; 1409 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1410 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1411 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1412 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1413 status = "disabled"; 1414 }; 1415 1416 spi7: spi@99c000 { 1417 compatible = "qcom,geni-spi"; 1418 reg = <0 0x0099c000 0 0x4000>; 1419 #address-cells = <1>; 1420 #size-cells = <0>; 1421 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1422 clock-names = "se"; 1423 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1424 power-domains = <&rpmhpd SC8280XP_CX>; 1425 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1426 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1427 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1428 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1429 status = "disabled"; 1430 }; 1431 }; 1432 1433 qup1: geniqup@ac0000 { 1434 compatible = "qcom,geni-se-qup"; 1435 reg = <0 0x00ac0000 0 0x6000>; 1436 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1437 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1438 clock-names = "m-ahb", "s-ahb"; 1439 iommus = <&apps_smmu 0x83 0>; 1440 1441 #address-cells = <2>; 1442 #size-cells = <2>; 1443 ranges; 1444 1445 status = "disabled"; 1446 1447 i2c8: i2c@a80000 { 1448 compatible = "qcom,geni-i2c"; 1449 reg = <0 0x00a80000 0 0x4000>; 1450 #address-cells = <1>; 1451 #size-cells = <0>; 1452 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1453 clock-names = "se"; 1454 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1455 power-domains = <&rpmhpd SC8280XP_CX>; 1456 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1457 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1458 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1459 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1460 status = "disabled"; 1461 }; 1462 1463 spi8: spi@a80000 { 1464 compatible = "qcom,geni-spi"; 1465 reg = <0 0x00a80000 0 0x4000>; 1466 #address-cells = <1>; 1467 #size-cells = <0>; 1468 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1469 clock-names = "se"; 1470 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1471 power-domains = <&rpmhpd SC8280XP_CX>; 1472 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1473 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1474 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1475 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1476 status = "disabled"; 1477 }; 1478 1479 i2c9: i2c@a84000 { 1480 compatible = "qcom,geni-i2c"; 1481 reg = <0 0x00a84000 0 0x4000>; 1482 #address-cells = <1>; 1483 #size-cells = <0>; 1484 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1485 clock-names = "se"; 1486 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1487 power-domains = <&rpmhpd SC8280XP_CX>; 1488 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1489 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1490 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1491 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1492 status = "disabled"; 1493 }; 1494 1495 spi9: spi@a84000 { 1496 compatible = "qcom,geni-spi"; 1497 reg = <0 0x00a84000 0 0x4000>; 1498 #address-cells = <1>; 1499 #size-cells = <0>; 1500 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1501 clock-names = "se"; 1502 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1503 power-domains = <&rpmhpd SC8280XP_CX>; 1504 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1505 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1506 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1507 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1508 status = "disabled"; 1509 }; 1510 1511 i2c10: i2c@a88000 { 1512 compatible = "qcom,geni-i2c"; 1513 reg = <0 0x00a88000 0 0x4000>; 1514 #address-cells = <1>; 1515 #size-cells = <0>; 1516 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1517 clock-names = "se"; 1518 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1519 power-domains = <&rpmhpd SC8280XP_CX>; 1520 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1521 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1522 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1523 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1524 status = "disabled"; 1525 }; 1526 1527 spi10: spi@a88000 { 1528 compatible = "qcom,geni-spi"; 1529 reg = <0 0x00a88000 0 0x4000>; 1530 #address-cells = <1>; 1531 #size-cells = <0>; 1532 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1533 clock-names = "se"; 1534 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1535 power-domains = <&rpmhpd SC8280XP_CX>; 1536 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1537 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1538 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1539 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1540 status = "disabled"; 1541 }; 1542 1543 i2c11: i2c@a8c000 { 1544 compatible = "qcom,geni-i2c"; 1545 reg = <0 0x00a8c000 0 0x4000>; 1546 #address-cells = <1>; 1547 #size-cells = <0>; 1548 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1549 clock-names = "se"; 1550 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1551 power-domains = <&rpmhpd SC8280XP_CX>; 1552 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1553 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1554 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1555 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1556 status = "disabled"; 1557 }; 1558 1559 spi11: spi@a8c000 { 1560 compatible = "qcom,geni-spi"; 1561 reg = <0 0x00a8c000 0 0x4000>; 1562 #address-cells = <1>; 1563 #size-cells = <0>; 1564 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1565 clock-names = "se"; 1566 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1567 power-domains = <&rpmhpd SC8280XP_CX>; 1568 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1569 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1570 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1571 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1572 status = "disabled"; 1573 }; 1574 1575 i2c12: i2c@a90000 { 1576 compatible = "qcom,geni-i2c"; 1577 reg = <0 0x00a90000 0 0x4000>; 1578 #address-cells = <1>; 1579 #size-cells = <0>; 1580 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1581 clock-names = "se"; 1582 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1583 power-domains = <&rpmhpd SC8280XP_CX>; 1584 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1585 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1586 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1587 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1588 status = "disabled"; 1589 }; 1590 1591 spi12: spi@a90000 { 1592 compatible = "qcom,geni-spi"; 1593 reg = <0 0x00a90000 0 0x4000>; 1594 #address-cells = <1>; 1595 #size-cells = <0>; 1596 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1597 clock-names = "se"; 1598 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1599 power-domains = <&rpmhpd SC8280XP_CX>; 1600 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1601 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1602 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1603 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1604 status = "disabled"; 1605 }; 1606 1607 i2c13: i2c@a94000 { 1608 compatible = "qcom,geni-i2c"; 1609 reg = <0 0x00a94000 0 0x4000>; 1610 #address-cells = <1>; 1611 #size-cells = <0>; 1612 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1613 clock-names = "se"; 1614 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1615 power-domains = <&rpmhpd SC8280XP_CX>; 1616 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1617 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1618 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1619 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1620 status = "disabled"; 1621 }; 1622 1623 spi13: spi@a94000 { 1624 compatible = "qcom,geni-spi"; 1625 reg = <0 0x00a94000 0 0x4000>; 1626 #address-cells = <1>; 1627 #size-cells = <0>; 1628 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1629 clock-names = "se"; 1630 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1631 power-domains = <&rpmhpd SC8280XP_CX>; 1632 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1633 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1634 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1635 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1636 status = "disabled"; 1637 }; 1638 1639 i2c14: i2c@a98000 { 1640 compatible = "qcom,geni-i2c"; 1641 reg = <0 0x00a98000 0 0x4000>; 1642 #address-cells = <1>; 1643 #size-cells = <0>; 1644 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1645 clock-names = "se"; 1646 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>; 1647 power-domains = <&rpmhpd SC8280XP_CX>; 1648 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1649 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1650 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1651 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1652 status = "disabled"; 1653 }; 1654 1655 spi14: spi@a98000 { 1656 compatible = "qcom,geni-spi"; 1657 reg = <0 0x00a98000 0 0x4000>; 1658 #address-cells = <1>; 1659 #size-cells = <0>; 1660 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1661 clock-names = "se"; 1662 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>; 1663 power-domains = <&rpmhpd SC8280XP_CX>; 1664 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1665 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1666 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1667 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1668 status = "disabled"; 1669 }; 1670 1671 i2c15: i2c@a9c000 { 1672 compatible = "qcom,geni-i2c"; 1673 reg = <0 0x00a9c000 0 0x4000>; 1674 #address-cells = <1>; 1675 #size-cells = <0>; 1676 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1677 clock-names = "se"; 1678 interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>; 1679 power-domains = <&rpmhpd SC8280XP_CX>; 1680 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1681 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1682 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1683 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1684 status = "disabled"; 1685 }; 1686 1687 spi15: spi@a9c000 { 1688 compatible = "qcom,geni-spi"; 1689 reg = <0 0x00a9c000 0 0x4000>; 1690 #address-cells = <1>; 1691 #size-cells = <0>; 1692 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1693 clock-names = "se"; 1694 interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>; 1695 power-domains = <&rpmhpd SC8280XP_CX>; 1696 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1697 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1698 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1699 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1700 status = "disabled"; 1701 }; 1702 }; 1703 1704 rng: rng@10d3000 { 1705 compatible = "qcom,prng-ee"; 1706 reg = <0 0x010d3000 0 0x1000>; 1707 clocks = <&rpmhcc RPMH_HWKM_CLK>; 1708 clock-names = "core"; 1709 }; 1710 1711 pcie4: pcie@1c00000 { 1712 device_type = "pci"; 1713 compatible = "qcom,pcie-sc8280xp"; 1714 reg = <0x0 0x01c00000 0x0 0x3000>, 1715 <0x0 0x30000000 0x0 0xf1d>, 1716 <0x0 0x30000f20 0x0 0xa8>, 1717 <0x0 0x30001000 0x0 0x1000>, 1718 <0x0 0x30100000 0x0 0x100000>, 1719 <0x0 0x01c03000 0x0 0x1000>; 1720 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 1721 #address-cells = <3>; 1722 #size-cells = <2>; 1723 ranges = <0x01000000 0x0 0x00000000 0x0 0x30200000 0x0 0x100000>, 1724 <0x02000000 0x0 0x30300000 0x0 0x30300000 0x0 0x1d00000>; 1725 bus-range = <0x00 0xff>; 1726 1727 dma-coherent; 1728 1729 linux,pci-domain = <6>; 1730 num-lanes = <1>; 1731 1732 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 1733 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1734 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 1735 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 1736 interrupt-names = "msi0", "msi1", "msi2", "msi3"; 1737 1738 #interrupt-cells = <1>; 1739 interrupt-map-mask = <0 0 0 0x7>; 1740 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 1741 <0 0 0 2 &intc 0 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 1742 <0 0 0 3 &intc 0 0 GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 1743 <0 0 0 4 &intc 0 0 GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 1744 1745 clocks = <&gcc GCC_PCIE_4_AUX_CLK>, 1746 <&gcc GCC_PCIE_4_CFG_AHB_CLK>, 1747 <&gcc GCC_PCIE_4_MSTR_AXI_CLK>, 1748 <&gcc GCC_PCIE_4_SLV_AXI_CLK>, 1749 <&gcc GCC_PCIE_4_SLV_Q2A_AXI_CLK>, 1750 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 1751 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, 1752 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>, 1753 <&gcc GCC_CNOC_PCIE4_QX_CLK>; 1754 clock-names = "aux", 1755 "cfg", 1756 "bus_master", 1757 "bus_slave", 1758 "slave_q2a", 1759 "ddrss_sf_tbu", 1760 "noc_aggr_4", 1761 "noc_aggr_south_sf", 1762 "cnoc_qx"; 1763 1764 assigned-clocks = <&gcc GCC_PCIE_4_AUX_CLK>; 1765 assigned-clock-rates = <19200000>; 1766 1767 interconnects = <&aggre2_noc MASTER_PCIE_4 0 &mc_virt SLAVE_EBI1 0>, 1768 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_4 0>; 1769 interconnect-names = "pcie-mem", "cpu-pcie"; 1770 1771 resets = <&gcc GCC_PCIE_4_BCR>; 1772 reset-names = "pci"; 1773 1774 power-domains = <&gcc PCIE_4_GDSC>; 1775 1776 phys = <&pcie4_phy>; 1777 phy-names = "pciephy"; 1778 1779 status = "disabled"; 1780 }; 1781 1782 pcie4_phy: phy@1c06000 { 1783 compatible = "qcom,sc8280xp-qmp-gen3x1-pcie-phy"; 1784 reg = <0x0 0x01c06000 0x0 0x2000>; 1785 1786 clocks = <&gcc GCC_PCIE_4_AUX_CLK>, 1787 <&gcc GCC_PCIE_4_CFG_AHB_CLK>, 1788 <&gcc GCC_PCIE_4_CLKREF_CLK>, 1789 <&gcc GCC_PCIE4_PHY_RCHNG_CLK>, 1790 <&gcc GCC_PCIE_4_PIPE_CLK>, 1791 <&gcc GCC_PCIE_4_PIPEDIV2_CLK>; 1792 clock-names = "aux", "cfg_ahb", "ref", "rchng", 1793 "pipe", "pipediv2"; 1794 1795 assigned-clocks = <&gcc GCC_PCIE4_PHY_RCHNG_CLK>; 1796 assigned-clock-rates = <100000000>; 1797 1798 power-domains = <&gcc PCIE_4_GDSC>; 1799 1800 resets = <&gcc GCC_PCIE_4_PHY_BCR>; 1801 reset-names = "phy"; 1802 1803 #clock-cells = <0>; 1804 clock-output-names = "pcie_4_pipe_clk"; 1805 1806 #phy-cells = <0>; 1807 1808 status = "disabled"; 1809 }; 1810 1811 pcie3b: pcie@1c08000 { 1812 device_type = "pci"; 1813 compatible = "qcom,pcie-sc8280xp"; 1814 reg = <0x0 0x01c08000 0x0 0x3000>, 1815 <0x0 0x32000000 0x0 0xf1d>, 1816 <0x0 0x32000f20 0x0 0xa8>, 1817 <0x0 0x32001000 0x0 0x1000>, 1818 <0x0 0x32100000 0x0 0x100000>, 1819 <0x0 0x01c0b000 0x0 0x1000>; 1820 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 1821 #address-cells = <3>; 1822 #size-cells = <2>; 1823 ranges = <0x01000000 0x0 0x00000000 0x0 0x32200000 0x0 0x100000>, 1824 <0x02000000 0x0 0x32300000 0x0 0x32300000 0x0 0x1d00000>; 1825 bus-range = <0x00 0xff>; 1826 1827 dma-coherent; 1828 1829 linux,pci-domain = <5>; 1830 num-lanes = <2>; 1831 1832 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1833 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1834 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1835 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 1836 interrupt-names = "msi0", "msi1", "msi2", "msi3"; 1837 1838 #interrupt-cells = <1>; 1839 interrupt-map-mask = <0 0 0 0x7>; 1840 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 526 IRQ_TYPE_LEVEL_HIGH>, 1841 <0 0 0 2 &intc 0 0 GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>, 1842 <0 0 0 3 &intc 0 0 GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH>, 1843 <0 0 0 4 &intc 0 0 GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>; 1844 1845 clocks = <&gcc GCC_PCIE_3B_AUX_CLK>, 1846 <&gcc GCC_PCIE_3B_CFG_AHB_CLK>, 1847 <&gcc GCC_PCIE_3B_MSTR_AXI_CLK>, 1848 <&gcc GCC_PCIE_3B_SLV_AXI_CLK>, 1849 <&gcc GCC_PCIE_3B_SLV_Q2A_AXI_CLK>, 1850 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 1851 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, 1852 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>; 1853 clock-names = "aux", 1854 "cfg", 1855 "bus_master", 1856 "bus_slave", 1857 "slave_q2a", 1858 "ddrss_sf_tbu", 1859 "noc_aggr_4", 1860 "noc_aggr_south_sf"; 1861 1862 assigned-clocks = <&gcc GCC_PCIE_3B_AUX_CLK>; 1863 assigned-clock-rates = <19200000>; 1864 1865 interconnects = <&aggre2_noc MASTER_PCIE_3B 0 &mc_virt SLAVE_EBI1 0>, 1866 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_3B 0>; 1867 interconnect-names = "pcie-mem", "cpu-pcie"; 1868 1869 resets = <&gcc GCC_PCIE_3B_BCR>; 1870 reset-names = "pci"; 1871 1872 power-domains = <&gcc PCIE_3B_GDSC>; 1873 1874 phys = <&pcie3b_phy>; 1875 phy-names = "pciephy"; 1876 1877 status = "disabled"; 1878 }; 1879 1880 pcie3b_phy: phy@1c0e000 { 1881 compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy"; 1882 reg = <0x0 0x01c0e000 0x0 0x2000>; 1883 1884 clocks = <&gcc GCC_PCIE_3B_AUX_CLK>, 1885 <&gcc GCC_PCIE_3B_CFG_AHB_CLK>, 1886 <&gcc GCC_PCIE_3A3B_CLKREF_CLK>, 1887 <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>, 1888 <&gcc GCC_PCIE_3B_PIPE_CLK>, 1889 <&gcc GCC_PCIE_3B_PIPEDIV2_CLK>; 1890 clock-names = "aux", "cfg_ahb", "ref", "rchng", 1891 "pipe", "pipediv2"; 1892 1893 assigned-clocks = <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>; 1894 assigned-clock-rates = <100000000>; 1895 1896 power-domains = <&gcc PCIE_3B_GDSC>; 1897 1898 resets = <&gcc GCC_PCIE_3B_PHY_BCR>; 1899 reset-names = "phy"; 1900 1901 #clock-cells = <0>; 1902 clock-output-names = "pcie_3b_pipe_clk"; 1903 1904 #phy-cells = <0>; 1905 1906 status = "disabled"; 1907 }; 1908 1909 pcie3a: pcie@1c10000 { 1910 device_type = "pci"; 1911 compatible = "qcom,pcie-sc8280xp"; 1912 reg = <0x0 0x01c10000 0x0 0x3000>, 1913 <0x0 0x34000000 0x0 0xf1d>, 1914 <0x0 0x34000f20 0x0 0xa8>, 1915 <0x0 0x34001000 0x0 0x1000>, 1916 <0x0 0x34100000 0x0 0x100000>, 1917 <0x0 0x01c13000 0x0 0x1000>; 1918 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 1919 #address-cells = <3>; 1920 #size-cells = <2>; 1921 ranges = <0x01000000 0x0 0x00000000 0x0 0x34200000 0x0 0x100000>, 1922 <0x02000000 0x0 0x34300000 0x0 0x34300000 0x0 0x1d00000>; 1923 bus-range = <0x00 0xff>; 1924 1925 dma-coherent; 1926 1927 linux,pci-domain = <4>; 1928 num-lanes = <4>; 1929 1930 interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 1931 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 1932 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 1933 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; 1934 interrupt-names = "msi0", "msi1", "msi2", "msi3"; 1935 1936 #interrupt-cells = <1>; 1937 interrupt-map-mask = <0 0 0 0x7>; 1938 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>, 1939 <0 0 0 2 &intc 0 0 GIC_SPI 542 IRQ_TYPE_LEVEL_HIGH>, 1940 <0 0 0 3 &intc 0 0 GIC_SPI 543 IRQ_TYPE_LEVEL_HIGH>, 1941 <0 0 0 4 &intc 0 0 GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>; 1942 1943 clocks = <&gcc GCC_PCIE_3A_AUX_CLK>, 1944 <&gcc GCC_PCIE_3A_CFG_AHB_CLK>, 1945 <&gcc GCC_PCIE_3A_MSTR_AXI_CLK>, 1946 <&gcc GCC_PCIE_3A_SLV_AXI_CLK>, 1947 <&gcc GCC_PCIE_3A_SLV_Q2A_AXI_CLK>, 1948 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 1949 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, 1950 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>; 1951 clock-names = "aux", 1952 "cfg", 1953 "bus_master", 1954 "bus_slave", 1955 "slave_q2a", 1956 "ddrss_sf_tbu", 1957 "noc_aggr_4", 1958 "noc_aggr_south_sf"; 1959 1960 assigned-clocks = <&gcc GCC_PCIE_3A_AUX_CLK>; 1961 assigned-clock-rates = <19200000>; 1962 1963 interconnects = <&aggre2_noc MASTER_PCIE_3A 0 &mc_virt SLAVE_EBI1 0>, 1964 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_3A 0>; 1965 interconnect-names = "pcie-mem", "cpu-pcie"; 1966 1967 resets = <&gcc GCC_PCIE_3A_BCR>; 1968 reset-names = "pci"; 1969 1970 power-domains = <&gcc PCIE_3A_GDSC>; 1971 1972 phys = <&pcie3a_phy>; 1973 phy-names = "pciephy"; 1974 1975 status = "disabled"; 1976 }; 1977 1978 pcie3a_phy: phy@1c14000 { 1979 compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy"; 1980 reg = <0x0 0x01c14000 0x0 0x2000>, 1981 <0x0 0x01c16000 0x0 0x2000>; 1982 1983 clocks = <&gcc GCC_PCIE_3A_AUX_CLK>, 1984 <&gcc GCC_PCIE_3A_CFG_AHB_CLK>, 1985 <&gcc GCC_PCIE_3A3B_CLKREF_CLK>, 1986 <&gcc GCC_PCIE3A_PHY_RCHNG_CLK>, 1987 <&gcc GCC_PCIE_3A_PIPE_CLK>, 1988 <&gcc GCC_PCIE_3A_PIPEDIV2_CLK>; 1989 clock-names = "aux", "cfg_ahb", "ref", "rchng", 1990 "pipe", "pipediv2"; 1991 1992 assigned-clocks = <&gcc GCC_PCIE3A_PHY_RCHNG_CLK>; 1993 assigned-clock-rates = <100000000>; 1994 1995 power-domains = <&gcc PCIE_3A_GDSC>; 1996 1997 resets = <&gcc GCC_PCIE_3A_PHY_BCR>; 1998 reset-names = "phy"; 1999 2000 qcom,4ln-config-sel = <&tcsr 0xa044 1>; 2001 2002 #clock-cells = <0>; 2003 clock-output-names = "pcie_3a_pipe_clk"; 2004 2005 #phy-cells = <0>; 2006 2007 status = "disabled"; 2008 }; 2009 2010 pcie2b: pcie@1c18000 { 2011 device_type = "pci"; 2012 compatible = "qcom,pcie-sc8280xp"; 2013 reg = <0x0 0x01c18000 0x0 0x3000>, 2014 <0x0 0x38000000 0x0 0xf1d>, 2015 <0x0 0x38000f20 0x0 0xa8>, 2016 <0x0 0x38001000 0x0 0x1000>, 2017 <0x0 0x38100000 0x0 0x100000>, 2018 <0x0 0x01c1b000 0x0 0x1000>; 2019 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 2020 #address-cells = <3>; 2021 #size-cells = <2>; 2022 ranges = <0x01000000 0x0 0x00000000 0x0 0x38200000 0x0 0x100000>, 2023 <0x02000000 0x0 0x38300000 0x0 0x38300000 0x0 0x1d00000>; 2024 bus-range = <0x00 0xff>; 2025 2026 dma-coherent; 2027 2028 linux,pci-domain = <3>; 2029 num-lanes = <2>; 2030 2031 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 2032 <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 2033 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 2034 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>; 2035 interrupt-names = "msi0", "msi1", "msi2", "msi3"; 2036 2037 #interrupt-cells = <1>; 2038 interrupt-map-mask = <0 0 0 0x7>; 2039 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, 2040 <0 0 0 2 &intc 0 0 GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, 2041 <0 0 0 3 &intc 0 0 GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, 2042 <0 0 0 4 &intc 0 0 GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>; 2043 2044 clocks = <&gcc GCC_PCIE_2B_AUX_CLK>, 2045 <&gcc GCC_PCIE_2B_CFG_AHB_CLK>, 2046 <&gcc GCC_PCIE_2B_MSTR_AXI_CLK>, 2047 <&gcc GCC_PCIE_2B_SLV_AXI_CLK>, 2048 <&gcc GCC_PCIE_2B_SLV_Q2A_AXI_CLK>, 2049 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 2050 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, 2051 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>; 2052 clock-names = "aux", 2053 "cfg", 2054 "bus_master", 2055 "bus_slave", 2056 "slave_q2a", 2057 "ddrss_sf_tbu", 2058 "noc_aggr_4", 2059 "noc_aggr_south_sf"; 2060 2061 assigned-clocks = <&gcc GCC_PCIE_2B_AUX_CLK>; 2062 assigned-clock-rates = <19200000>; 2063 2064 interconnects = <&aggre2_noc MASTER_PCIE_2B 0 &mc_virt SLAVE_EBI1 0>, 2065 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_2B 0>; 2066 interconnect-names = "pcie-mem", "cpu-pcie"; 2067 2068 resets = <&gcc GCC_PCIE_2B_BCR>; 2069 reset-names = "pci"; 2070 2071 power-domains = <&gcc PCIE_2B_GDSC>; 2072 2073 phys = <&pcie2b_phy>; 2074 phy-names = "pciephy"; 2075 2076 status = "disabled"; 2077 }; 2078 2079 pcie2b_phy: phy@1c1e000 { 2080 compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy"; 2081 reg = <0x0 0x01c1e000 0x0 0x2000>; 2082 2083 clocks = <&gcc GCC_PCIE_2B_AUX_CLK>, 2084 <&gcc GCC_PCIE_2B_CFG_AHB_CLK>, 2085 <&gcc GCC_PCIE_2A2B_CLKREF_CLK>, 2086 <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>, 2087 <&gcc GCC_PCIE_2B_PIPE_CLK>, 2088 <&gcc GCC_PCIE_2B_PIPEDIV2_CLK>; 2089 clock-names = "aux", "cfg_ahb", "ref", "rchng", 2090 "pipe", "pipediv2"; 2091 2092 assigned-clocks = <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>; 2093 assigned-clock-rates = <100000000>; 2094 2095 power-domains = <&gcc PCIE_2B_GDSC>; 2096 2097 resets = <&gcc GCC_PCIE_2B_PHY_BCR>; 2098 reset-names = "phy"; 2099 2100 #clock-cells = <0>; 2101 clock-output-names = "pcie_2b_pipe_clk"; 2102 2103 #phy-cells = <0>; 2104 2105 status = "disabled"; 2106 }; 2107 2108 pcie2a: pcie@1c20000 { 2109 device_type = "pci"; 2110 compatible = "qcom,pcie-sc8280xp"; 2111 reg = <0x0 0x01c20000 0x0 0x3000>, 2112 <0x0 0x3c000000 0x0 0xf1d>, 2113 <0x0 0x3c000f20 0x0 0xa8>, 2114 <0x0 0x3c001000 0x0 0x1000>, 2115 <0x0 0x3c100000 0x0 0x100000>, 2116 <0x0 0x01c23000 0x0 0x1000>; 2117 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 2118 #address-cells = <3>; 2119 #size-cells = <2>; 2120 ranges = <0x01000000 0x0 0x00000000 0x0 0x3c200000 0x0 0x100000>, 2121 <0x02000000 0x0 0x3c300000 0x0 0x3c300000 0x0 0x1d00000>; 2122 bus-range = <0x00 0xff>; 2123 2124 dma-coherent; 2125 2126 linux,pci-domain = <2>; 2127 num-lanes = <4>; 2128 2129 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 2130 <GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH>, 2131 <GIC_SPI 524 IRQ_TYPE_LEVEL_HIGH>, 2132 <GIC_SPI 525 IRQ_TYPE_LEVEL_HIGH>; 2133 interrupt-names = "msi0", "msi1", "msi2", "msi3"; 2134 2135 #interrupt-cells = <1>; 2136 interrupt-map-mask = <0 0 0 0x7>; 2137 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>, 2138 <0 0 0 2 &intc 0 0 GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>, 2139 <0 0 0 3 &intc 0 0 GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>, 2140 <0 0 0 4 &intc 0 0 GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>; 2141 2142 clocks = <&gcc GCC_PCIE_2A_AUX_CLK>, 2143 <&gcc GCC_PCIE_2A_CFG_AHB_CLK>, 2144 <&gcc GCC_PCIE_2A_MSTR_AXI_CLK>, 2145 <&gcc GCC_PCIE_2A_SLV_AXI_CLK>, 2146 <&gcc GCC_PCIE_2A_SLV_Q2A_AXI_CLK>, 2147 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 2148 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, 2149 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>; 2150 clock-names = "aux", 2151 "cfg", 2152 "bus_master", 2153 "bus_slave", 2154 "slave_q2a", 2155 "ddrss_sf_tbu", 2156 "noc_aggr_4", 2157 "noc_aggr_south_sf"; 2158 2159 assigned-clocks = <&gcc GCC_PCIE_2A_AUX_CLK>; 2160 assigned-clock-rates = <19200000>; 2161 2162 interconnects = <&aggre2_noc MASTER_PCIE_2A 0 &mc_virt SLAVE_EBI1 0>, 2163 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_2A 0>; 2164 interconnect-names = "pcie-mem", "cpu-pcie"; 2165 2166 resets = <&gcc GCC_PCIE_2A_BCR>; 2167 reset-names = "pci"; 2168 2169 power-domains = <&gcc PCIE_2A_GDSC>; 2170 2171 phys = <&pcie2a_phy>; 2172 phy-names = "pciephy"; 2173 2174 status = "disabled"; 2175 }; 2176 2177 pcie2a_phy: phy@1c24000 { 2178 compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy"; 2179 reg = <0x0 0x01c24000 0x0 0x2000>, 2180 <0x0 0x01c26000 0x0 0x2000>; 2181 2182 clocks = <&gcc GCC_PCIE_2A_AUX_CLK>, 2183 <&gcc GCC_PCIE_2A_CFG_AHB_CLK>, 2184 <&gcc GCC_PCIE_2A2B_CLKREF_CLK>, 2185 <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>, 2186 <&gcc GCC_PCIE_2A_PIPE_CLK>, 2187 <&gcc GCC_PCIE_2A_PIPEDIV2_CLK>; 2188 clock-names = "aux", "cfg_ahb", "ref", "rchng", 2189 "pipe", "pipediv2"; 2190 2191 assigned-clocks = <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>; 2192 assigned-clock-rates = <100000000>; 2193 2194 power-domains = <&gcc PCIE_2A_GDSC>; 2195 2196 resets = <&gcc GCC_PCIE_2A_PHY_BCR>; 2197 reset-names = "phy"; 2198 2199 qcom,4ln-config-sel = <&tcsr 0xa044 0>; 2200 2201 #clock-cells = <0>; 2202 clock-output-names = "pcie_2a_pipe_clk"; 2203 2204 #phy-cells = <0>; 2205 2206 status = "disabled"; 2207 }; 2208 2209 ufs_mem_hc: ufs@1d84000 { 2210 compatible = "qcom,sc8280xp-ufshc", "qcom,ufshc", 2211 "jedec,ufs-2.0"; 2212 reg = <0 0x01d84000 0 0x3000>; 2213 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2214 phys = <&ufs_mem_phy>; 2215 phy-names = "ufsphy"; 2216 lanes-per-direction = <2>; 2217 #reset-cells = <1>; 2218 resets = <&gcc GCC_UFS_PHY_BCR>; 2219 reset-names = "rst"; 2220 2221 power-domains = <&gcc UFS_PHY_GDSC>; 2222 required-opps = <&rpmhpd_opp_nom>; 2223 2224 iommus = <&apps_smmu 0xe0 0x0>; 2225 dma-coherent; 2226 2227 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 2228 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2229 <&gcc GCC_UFS_PHY_AHB_CLK>, 2230 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2231 <&gcc GCC_UFS_REF_CLKREF_CLK>, 2232 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2233 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2234 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 2235 clock-names = "core_clk", 2236 "bus_aggr_clk", 2237 "iface_clk", 2238 "core_clk_unipro", 2239 "ref_clk", 2240 "tx_lane0_sync_clk", 2241 "rx_lane0_sync_clk", 2242 "rx_lane1_sync_clk"; 2243 freq-table-hz = <75000000 300000000>, 2244 <0 0>, 2245 <0 0>, 2246 <75000000 300000000>, 2247 <0 0>, 2248 <0 0>, 2249 <0 0>, 2250 <0 0>; 2251 status = "disabled"; 2252 }; 2253 2254 ufs_mem_phy: phy@1d87000 { 2255 compatible = "qcom,sc8280xp-qmp-ufs-phy"; 2256 reg = <0 0x01d87000 0 0x1000>; 2257 2258 clocks = <&gcc GCC_UFS_CARD_CLKREF_CLK>, 2259 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 2260 clock-names = "ref", "ref_aux"; 2261 2262 power-domains = <&gcc UFS_PHY_GDSC>; 2263 2264 resets = <&ufs_mem_hc 0>; 2265 reset-names = "ufsphy"; 2266 2267 #phy-cells = <0>; 2268 2269 status = "disabled"; 2270 }; 2271 2272 ufs_card_hc: ufs@1da4000 { 2273 compatible = "qcom,sc8280xp-ufshc", "qcom,ufshc", 2274 "jedec,ufs-2.0"; 2275 reg = <0 0x01da4000 0 0x3000>; 2276 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 2277 phys = <&ufs_card_phy>; 2278 phy-names = "ufsphy"; 2279 lanes-per-direction = <2>; 2280 #reset-cells = <1>; 2281 resets = <&gcc GCC_UFS_CARD_BCR>; 2282 reset-names = "rst"; 2283 2284 power-domains = <&gcc UFS_CARD_GDSC>; 2285 2286 iommus = <&apps_smmu 0x4a0 0x0>; 2287 dma-coherent; 2288 2289 clocks = <&gcc GCC_UFS_CARD_AXI_CLK>, 2290 <&gcc GCC_AGGRE_UFS_CARD_AXI_CLK>, 2291 <&gcc GCC_UFS_CARD_AHB_CLK>, 2292 <&gcc GCC_UFS_CARD_UNIPRO_CORE_CLK>, 2293 <&gcc GCC_UFS_REF_CLKREF_CLK>, 2294 <&gcc GCC_UFS_CARD_TX_SYMBOL_0_CLK>, 2295 <&gcc GCC_UFS_CARD_RX_SYMBOL_0_CLK>, 2296 <&gcc GCC_UFS_CARD_RX_SYMBOL_1_CLK>; 2297 clock-names = "core_clk", 2298 "bus_aggr_clk", 2299 "iface_clk", 2300 "core_clk_unipro", 2301 "ref_clk", 2302 "tx_lane0_sync_clk", 2303 "rx_lane0_sync_clk", 2304 "rx_lane1_sync_clk"; 2305 freq-table-hz = <75000000 300000000>, 2306 <0 0>, 2307 <0 0>, 2308 <75000000 300000000>, 2309 <0 0>, 2310 <0 0>, 2311 <0 0>, 2312 <0 0>; 2313 status = "disabled"; 2314 }; 2315 2316 ufs_card_phy: phy@1da7000 { 2317 compatible = "qcom,sc8280xp-qmp-ufs-phy"; 2318 reg = <0 0x01da7000 0 0x1000>; 2319 2320 clocks = <&gcc GCC_UFS_1_CARD_CLKREF_CLK>, 2321 <&gcc GCC_UFS_CARD_PHY_AUX_CLK>; 2322 clock-names = "ref", "ref_aux"; 2323 2324 power-domains = <&gcc UFS_CARD_GDSC>; 2325 2326 resets = <&ufs_card_hc 0>; 2327 reset-names = "ufsphy"; 2328 2329 #phy-cells = <0>; 2330 2331 status = "disabled"; 2332 }; 2333 2334 tcsr_mutex: hwlock@1f40000 { 2335 compatible = "qcom,tcsr-mutex"; 2336 reg = <0x0 0x01f40000 0x0 0x20000>; 2337 #hwlock-cells = <1>; 2338 }; 2339 2340 tcsr: syscon@1fc0000 { 2341 compatible = "qcom,sc8280xp-tcsr", "syscon"; 2342 reg = <0x0 0x01fc0000 0x0 0x30000>; 2343 }; 2344 2345 gpu: gpu@3d00000 { 2346 compatible = "qcom,adreno-690.0", "qcom,adreno"; 2347 2348 reg = <0 0x03d00000 0 0x40000>, 2349 <0 0x03d9e000 0 0x1000>, 2350 <0 0x03d61000 0 0x800>; 2351 reg-names = "kgsl_3d0_reg_memory", 2352 "cx_mem", 2353 "cx_dbgc"; 2354 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2355 iommus = <&gpu_smmu 0 0xc00>, <&gpu_smmu 1 0xc00>; 2356 operating-points-v2 = <&gpu_opp_table>; 2357 2358 qcom,gmu = <&gmu>; 2359 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 2360 interconnect-names = "gfx-mem"; 2361 #cooling-cells = <2>; 2362 2363 status = "disabled"; 2364 2365 gpu_opp_table: opp-table { 2366 compatible = "operating-points-v2"; 2367 2368 opp-270000000 { 2369 opp-hz = /bits/ 64 <270000000>; 2370 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2371 opp-peak-kBps = <451000>; 2372 }; 2373 2374 opp-410000000 { 2375 opp-hz = /bits/ 64 <410000000>; 2376 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2377 opp-peak-kBps = <1555000>; 2378 }; 2379 2380 opp-500000000 { 2381 opp-hz = /bits/ 64 <500000000>; 2382 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2383 opp-peak-kBps = <1555000>; 2384 }; 2385 2386 opp-547000000 { 2387 opp-hz = /bits/ 64 <547000000>; 2388 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 2389 opp-peak-kBps = <1555000>; 2390 }; 2391 2392 opp-606000000 { 2393 opp-hz = /bits/ 64 <606000000>; 2394 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2395 opp-peak-kBps = <2736000>; 2396 }; 2397 2398 opp-640000000 { 2399 opp-hz = /bits/ 64 <640000000>; 2400 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2401 opp-peak-kBps = <2736000>; 2402 }; 2403 2404 opp-655000000 { 2405 opp-hz = /bits/ 64 <655000000>; 2406 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2407 opp-peak-kBps = <2736000>; 2408 }; 2409 2410 opp-690000000 { 2411 opp-hz = /bits/ 64 <690000000>; 2412 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 2413 opp-peak-kBps = <2736000>; 2414 }; 2415 }; 2416 }; 2417 2418 gmu: gmu@3d6a000 { 2419 compatible = "qcom,adreno-gmu-690.0", "qcom,adreno-gmu"; 2420 reg = <0 0x03d6a000 0 0x34000>, 2421 <0 0x03de0000 0 0x10000>, 2422 <0 0x0b290000 0 0x10000>; 2423 reg-names = "gmu", "rscc", "gmu_pdc"; 2424 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2425 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2426 interrupt-names = "hfi", "gmu"; 2427 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 2428 <&gpucc GPU_CC_CXO_CLK>, 2429 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2430 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2431 <&gpucc GPU_CC_AHB_CLK>, 2432 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2433 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; 2434 clock-names = "gmu", 2435 "cxo", 2436 "axi", 2437 "memnoc", 2438 "ahb", 2439 "hub", 2440 "smmu_vote"; 2441 power-domains = <&gpucc GPU_CC_CX_GDSC>, 2442 <&gpucc GPU_CC_GX_GDSC>; 2443 power-domain-names = "cx", 2444 "gx"; 2445 iommus = <&gpu_smmu 5 0xc00>; 2446 operating-points-v2 = <&gmu_opp_table>; 2447 2448 gmu_opp_table: opp-table { 2449 compatible = "operating-points-v2"; 2450 2451 opp-200000000 { 2452 opp-hz = /bits/ 64 <200000000>; 2453 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2454 }; 2455 2456 opp-500000000 { 2457 opp-hz = /bits/ 64 <500000000>; 2458 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2459 }; 2460 }; 2461 }; 2462 2463 gpucc: clock-controller@3d90000 { 2464 compatible = "qcom,sc8280xp-gpucc"; 2465 reg = <0 0x03d90000 0 0x9000>; 2466 clocks = <&rpmhcc RPMH_CXO_CLK>, 2467 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2468 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2469 clock-names = "bi_tcxo", 2470 "gcc_gpu_gpll0_clk_src", 2471 "gcc_gpu_gpll0_div_clk_src"; 2472 2473 power-domains = <&rpmhpd SC8280XP_GFX>; 2474 #clock-cells = <1>; 2475 #reset-cells = <1>; 2476 #power-domain-cells = <1>; 2477 }; 2478 2479 gpu_smmu: iommu@3da0000 { 2480 compatible = "qcom,sc8280xp-smmu-500", "qcom,adreno-smmu", 2481 "qcom,smmu-500", "arm,mmu-500"; 2482 reg = <0 0x03da0000 0 0x20000>; 2483 #iommu-cells = <2>; 2484 #global-interrupts = <2>; 2485 interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>, 2486 <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 2487 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 2488 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 2489 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 2490 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2491 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2492 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2493 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2494 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 2495 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 2496 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>, 2497 <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>, 2498 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>; 2499 2500 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2501 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 2502 <&gpucc GPU_CC_AHB_CLK>, 2503 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 2504 <&gpucc GPU_CC_CX_GMU_CLK>, 2505 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2506 <&gpucc GPU_CC_HUB_AON_CLK>; 2507 clock-names = "gcc_gpu_memnoc_gfx_clk", 2508 "gcc_gpu_snoc_dvm_gfx_clk", 2509 "gpu_cc_ahb_clk", 2510 "gpu_cc_hlos1_vote_gpu_smmu_clk", 2511 "gpu_cc_cx_gmu_clk", 2512 "gpu_cc_hub_cx_int_clk", 2513 "gpu_cc_hub_aon_clk"; 2514 2515 power-domains = <&gpucc GPU_CC_CX_GDSC>; 2516 dma-coherent; 2517 }; 2518 2519 usb_0_hsphy: phy@88e5000 { 2520 compatible = "qcom,sc8280xp-usb-hs-phy", 2521 "qcom,usb-snps-hs-5nm-phy"; 2522 reg = <0 0x088e5000 0 0x400>; 2523 clocks = <&rpmhcc RPMH_CXO_CLK>; 2524 clock-names = "ref"; 2525 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2526 2527 #phy-cells = <0>; 2528 2529 status = "disabled"; 2530 }; 2531 2532 usb_2_hsphy0: phy@88e7000 { 2533 compatible = "qcom,sc8280xp-usb-hs-phy", 2534 "qcom,usb-snps-hs-5nm-phy"; 2535 reg = <0 0x088e7000 0 0x400>; 2536 clocks = <&gcc GCC_USB2_HS0_CLKREF_CLK>; 2537 clock-names = "ref"; 2538 resets = <&gcc GCC_QUSB2PHY_HS0_MP_BCR>; 2539 2540 #phy-cells = <0>; 2541 2542 status = "disabled"; 2543 }; 2544 2545 usb_2_hsphy1: phy@88e8000 { 2546 compatible = "qcom,sc8280xp-usb-hs-phy", 2547 "qcom,usb-snps-hs-5nm-phy"; 2548 reg = <0 0x088e8000 0 0x400>; 2549 clocks = <&gcc GCC_USB2_HS1_CLKREF_CLK>; 2550 clock-names = "ref"; 2551 resets = <&gcc GCC_QUSB2PHY_HS1_MP_BCR>; 2552 2553 #phy-cells = <0>; 2554 2555 status = "disabled"; 2556 }; 2557 2558 usb_2_hsphy2: phy@88e9000 { 2559 compatible = "qcom,sc8280xp-usb-hs-phy", 2560 "qcom,usb-snps-hs-5nm-phy"; 2561 reg = <0 0x088e9000 0 0x400>; 2562 clocks = <&gcc GCC_USB2_HS2_CLKREF_CLK>; 2563 clock-names = "ref"; 2564 resets = <&gcc GCC_QUSB2PHY_HS2_MP_BCR>; 2565 2566 #phy-cells = <0>; 2567 2568 status = "disabled"; 2569 }; 2570 2571 usb_2_hsphy3: phy@88ea000 { 2572 compatible = "qcom,sc8280xp-usb-hs-phy", 2573 "qcom,usb-snps-hs-5nm-phy"; 2574 reg = <0 0x088ea000 0 0x400>; 2575 clocks = <&gcc GCC_USB2_HS3_CLKREF_CLK>; 2576 clock-names = "ref"; 2577 resets = <&gcc GCC_QUSB2PHY_HS3_MP_BCR>; 2578 2579 #phy-cells = <0>; 2580 2581 status = "disabled"; 2582 }; 2583 2584 usb_2_qmpphy0: phy@88ef000 { 2585 compatible = "qcom,sc8280xp-qmp-usb3-uni-phy"; 2586 reg = <0 0x088ef000 0 0x2000>; 2587 2588 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, 2589 <&gcc GCC_USB3_MP0_CLKREF_CLK>, 2590 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, 2591 <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>; 2592 clock-names = "aux", "ref", "com_aux", "pipe"; 2593 2594 resets = <&gcc GCC_USB3_UNIPHY_MP0_BCR>, 2595 <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>; 2596 reset-names = "phy", "phy_phy"; 2597 2598 power-domains = <&gcc USB30_MP_GDSC>; 2599 2600 #clock-cells = <0>; 2601 clock-output-names = "usb2_phy0_pipe_clk"; 2602 2603 #phy-cells = <0>; 2604 2605 status = "disabled"; 2606 }; 2607 2608 usb_2_qmpphy1: phy@88f1000 { 2609 compatible = "qcom,sc8280xp-qmp-usb3-uni-phy"; 2610 reg = <0 0x088f1000 0 0x2000>; 2611 2612 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, 2613 <&gcc GCC_USB3_MP1_CLKREF_CLK>, 2614 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, 2615 <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>; 2616 clock-names = "aux", "ref", "com_aux", "pipe"; 2617 2618 resets = <&gcc GCC_USB3_UNIPHY_MP1_BCR>, 2619 <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>; 2620 reset-names = "phy", "phy_phy"; 2621 2622 power-domains = <&gcc USB30_MP_GDSC>; 2623 2624 #clock-cells = <0>; 2625 clock-output-names = "usb2_phy1_pipe_clk"; 2626 2627 #phy-cells = <0>; 2628 2629 status = "disabled"; 2630 }; 2631 2632 remoteproc_adsp: remoteproc@3000000 { 2633 compatible = "qcom,sc8280xp-adsp-pas"; 2634 reg = <0 0x03000000 0 0x100>; 2635 2636 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, 2637 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 2638 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 2639 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 2640 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>, 2641 <&smp2p_adsp_in 7 IRQ_TYPE_EDGE_RISING>; 2642 interrupt-names = "wdog", "fatal", "ready", 2643 "handover", "stop-ack", "shutdown-ack"; 2644 2645 clocks = <&rpmhcc RPMH_CXO_CLK>; 2646 clock-names = "xo"; 2647 2648 power-domains = <&rpmhpd SC8280XP_LCX>, 2649 <&rpmhpd SC8280XP_LMX>; 2650 power-domain-names = "lcx", "lmx"; 2651 2652 memory-region = <&pil_adsp_mem>; 2653 2654 qcom,qmp = <&aoss_qmp>; 2655 2656 qcom,smem-states = <&smp2p_adsp_out 0>; 2657 qcom,smem-state-names = "stop"; 2658 2659 status = "disabled"; 2660 2661 remoteproc_adsp_glink: glink-edge { 2662 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 2663 IPCC_MPROC_SIGNAL_GLINK_QMP 2664 IRQ_TYPE_EDGE_RISING>; 2665 mboxes = <&ipcc IPCC_CLIENT_LPASS 2666 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2667 2668 label = "lpass"; 2669 qcom,remote-pid = <2>; 2670 2671 gpr { 2672 compatible = "qcom,gpr"; 2673 qcom,glink-channels = "adsp_apps"; 2674 qcom,domain = <GPR_DOMAIN_ID_ADSP>; 2675 qcom,intents = <512 20>; 2676 #address-cells = <1>; 2677 #size-cells = <0>; 2678 2679 q6apm: service@1 { 2680 compatible = "qcom,q6apm"; 2681 reg = <GPR_APM_MODULE_IID>; 2682 #sound-dai-cells = <0>; 2683 qcom,protection-domain = "avs/audio", 2684 "msm/adsp/audio_pd"; 2685 q6apmdai: dais { 2686 compatible = "qcom,q6apm-dais"; 2687 iommus = <&apps_smmu 0x0c01 0x0>; 2688 }; 2689 2690 q6apmbedai: bedais { 2691 compatible = "qcom,q6apm-lpass-dais"; 2692 #sound-dai-cells = <1>; 2693 }; 2694 }; 2695 2696 q6prm: service@2 { 2697 compatible = "qcom,q6prm"; 2698 reg = <GPR_PRM_MODULE_IID>; 2699 qcom,protection-domain = "avs/audio", 2700 "msm/adsp/audio_pd"; 2701 q6prmcc: clock-controller { 2702 compatible = "qcom,q6prm-lpass-clocks"; 2703 #clock-cells = <2>; 2704 }; 2705 }; 2706 }; 2707 }; 2708 }; 2709 2710 rxmacro: rxmacro@3200000 { 2711 compatible = "qcom,sc8280xp-lpass-rx-macro"; 2712 reg = <0 0x03200000 0 0x1000>; 2713 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2714 <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2715 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2716 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2717 <&vamacro>; 2718 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2719 assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2720 <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2721 assigned-clock-rates = <19200000>, <19200000>; 2722 2723 clock-output-names = "mclk"; 2724 #clock-cells = <0>; 2725 #sound-dai-cells = <1>; 2726 2727 pinctrl-names = "default"; 2728 pinctrl-0 = <&rx_swr_default>; 2729 2730 status = "disabled"; 2731 }; 2732 2733 swr1: soundwire-controller@3210000 { 2734 compatible = "qcom,soundwire-v1.6.0"; 2735 reg = <0 0x03210000 0 0x2000>; 2736 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 2737 clocks = <&rxmacro>; 2738 clock-names = "iface"; 2739 resets = <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>; 2740 reset-names = "swr_audio_cgcr"; 2741 label = "RX"; 2742 2743 qcom,din-ports = <0>; 2744 qcom,dout-ports = <5>; 2745 2746 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>; 2747 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0B 0x01 0x00>; 2748 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0B 0x00 0x00>; 2749 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0x00 0xff 0xff>; 2750 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0x0f 0xff 0xff>; 2751 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>; 2752 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff>; 2753 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; 2754 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 2755 2756 #sound-dai-cells = <1>; 2757 #address-cells = <2>; 2758 #size-cells = <0>; 2759 2760 status = "disabled"; 2761 }; 2762 2763 txmacro: txmacro@3220000 { 2764 compatible = "qcom,sc8280xp-lpass-tx-macro"; 2765 reg = <0 0x03220000 0 0x1000>; 2766 pinctrl-names = "default"; 2767 pinctrl-0 = <&tx_swr_default>; 2768 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2769 <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2770 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2771 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2772 <&vamacro>; 2773 2774 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2775 assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2776 <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2777 assigned-clock-rates = <19200000>, <19200000>; 2778 clock-output-names = "mclk"; 2779 2780 #clock-cells = <0>; 2781 #sound-dai-cells = <1>; 2782 2783 status = "disabled"; 2784 }; 2785 2786 wsamacro: codec@3240000 { 2787 compatible = "qcom,sc8280xp-lpass-wsa-macro"; 2788 reg = <0 0x03240000 0 0x1000>; 2789 clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2790 <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2791 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2792 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2793 <&vamacro>; 2794 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2795 assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2796 <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2797 assigned-clock-rates = <19200000>, <19200000>; 2798 2799 #clock-cells = <0>; 2800 clock-output-names = "mclk"; 2801 #sound-dai-cells = <1>; 2802 2803 pinctrl-names = "default"; 2804 pinctrl-0 = <&wsa_swr_default>; 2805 2806 status = "disabled"; 2807 }; 2808 2809 swr0: soundwire-controller@3250000 { 2810 reg = <0 0x03250000 0 0x2000>; 2811 compatible = "qcom,soundwire-v1.6.0"; 2812 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 2813 clocks = <&wsamacro>; 2814 clock-names = "iface"; 2815 resets = <&lpass_audiocc LPASS_AUDIO_SWR_WSA_CGCR>; 2816 reset-names = "swr_audio_cgcr"; 2817 label = "WSA"; 2818 2819 qcom,din-ports = <2>; 2820 qcom,dout-ports = <6>; 2821 2822 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>; 2823 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>; 2824 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>; 2825 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2826 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2827 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2828 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>; 2829 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2830 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2831 2832 #sound-dai-cells = <1>; 2833 #address-cells = <2>; 2834 #size-cells = <0>; 2835 2836 status = "disabled"; 2837 }; 2838 2839 lpass_audiocc: clock-controller@32a9000 { 2840 compatible = "qcom,sc8280xp-lpassaudiocc"; 2841 reg = <0 0x032a9000 0 0x1000>; 2842 #clock-cells = <1>; 2843 #reset-cells = <1>; 2844 }; 2845 2846 swr2: soundwire-controller@3330000 { 2847 compatible = "qcom,soundwire-v1.6.0"; 2848 reg = <0 0x03330000 0 0x2000>; 2849 interrupts = <GIC_SPI 959 IRQ_TYPE_LEVEL_HIGH>, 2850 <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>; 2851 interrupt-names = "core", "wakeup"; 2852 2853 clocks = <&txmacro>; 2854 clock-names = "iface"; 2855 resets = <&lpasscc LPASS_AUDIO_SWR_TX_CGCR>; 2856 reset-names = "swr_audio_cgcr"; 2857 label = "TX"; 2858 #sound-dai-cells = <1>; 2859 #address-cells = <2>; 2860 #size-cells = <0>; 2861 2862 qcom,din-ports = <4>; 2863 qcom,dout-ports = <0>; 2864 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>; 2865 qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02 0x00>; 2866 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>; 2867 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>; 2868 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>; 2869 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>; 2870 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>; 2871 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>; 2872 qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00 0x01>; 2873 2874 status = "disabled"; 2875 }; 2876 2877 vamacro: codec@3370000 { 2878 compatible = "qcom,sc8280xp-lpass-va-macro"; 2879 reg = <0 0x03370000 0 0x1000>; 2880 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2881 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2882 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2883 <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2884 clock-names = "mclk", "macro", "dcodec", "npl"; 2885 assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2886 assigned-clock-rates = <19200000>; 2887 2888 #clock-cells = <0>; 2889 clock-output-names = "fsgen"; 2890 #sound-dai-cells = <1>; 2891 2892 status = "disabled"; 2893 }; 2894 2895 lpass_tlmm: pinctrl@33c0000 { 2896 compatible = "qcom,sc8280xp-lpass-lpi-pinctrl"; 2897 reg = <0 0x33c0000 0x0 0x20000>, 2898 <0 0x3550000 0x0 0x10000>; 2899 gpio-controller; 2900 #gpio-cells = <2>; 2901 gpio-ranges = <&lpass_tlmm 0 0 19>; 2902 2903 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2904 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2905 clock-names = "core", "audio"; 2906 2907 status = "disabled"; 2908 2909 tx_swr_default: tx-swr-default-state { 2910 clk-pins { 2911 pins = "gpio0"; 2912 function = "swr_tx_clk"; 2913 drive-strength = <2>; 2914 slew-rate = <1>; 2915 bias-disable; 2916 }; 2917 2918 data-pins { 2919 pins = "gpio1", "gpio2"; 2920 function = "swr_tx_data"; 2921 drive-strength = <2>; 2922 slew-rate = <1>; 2923 bias-bus-hold; 2924 }; 2925 }; 2926 2927 rx_swr_default: rx-swr-default-state { 2928 clk-pins { 2929 pins = "gpio3"; 2930 function = "swr_rx_clk"; 2931 drive-strength = <2>; 2932 slew-rate = <1>; 2933 bias-disable; 2934 }; 2935 2936 data-pins { 2937 pins = "gpio4", "gpio5"; 2938 function = "swr_rx_data"; 2939 drive-strength = <2>; 2940 slew-rate = <1>; 2941 bias-bus-hold; 2942 }; 2943 }; 2944 2945 dmic01_default: dmic01-default-state { 2946 clk-pins { 2947 pins = "gpio6"; 2948 function = "dmic1_clk"; 2949 drive-strength = <8>; 2950 output-high; 2951 }; 2952 2953 data-pins { 2954 pins = "gpio7"; 2955 function = "dmic1_data"; 2956 drive-strength = <8>; 2957 input-enable; 2958 }; 2959 }; 2960 2961 dmic01_sleep: dmic01-sleep-state { 2962 clk-pins { 2963 pins = "gpio6"; 2964 function = "dmic1_clk"; 2965 drive-strength = <2>; 2966 bias-disable; 2967 output-low; 2968 }; 2969 2970 data-pins { 2971 pins = "gpio7"; 2972 function = "dmic1_data"; 2973 drive-strength = <2>; 2974 bias-pull-down; 2975 input-enable; 2976 }; 2977 }; 2978 2979 dmic02_default: dmic02-default-state { 2980 clk-pins { 2981 pins = "gpio8"; 2982 function = "dmic2_clk"; 2983 drive-strength = <8>; 2984 output-high; 2985 }; 2986 2987 data-pins { 2988 pins = "gpio9"; 2989 function = "dmic2_data"; 2990 drive-strength = <8>; 2991 input-enable; 2992 }; 2993 }; 2994 2995 dmic02_sleep: dmic02-sleep-state { 2996 clk-pins { 2997 pins = "gpio8"; 2998 function = "dmic2_clk"; 2999 drive-strength = <2>; 3000 bias-disable; 3001 output-low; 3002 }; 3003 3004 data-pins { 3005 pins = "gpio9"; 3006 function = "dmic2_data"; 3007 drive-strength = <2>; 3008 bias-pull-down; 3009 input-enable; 3010 }; 3011 }; 3012 3013 wsa_swr_default: wsa-swr-default-state { 3014 clk-pins { 3015 pins = "gpio10"; 3016 function = "wsa_swr_clk"; 3017 drive-strength = <2>; 3018 slew-rate = <1>; 3019 bias-disable; 3020 }; 3021 3022 data-pins { 3023 pins = "gpio11"; 3024 function = "wsa_swr_data"; 3025 drive-strength = <2>; 3026 slew-rate = <1>; 3027 bias-bus-hold; 3028 }; 3029 }; 3030 3031 wsa2_swr_default: wsa2-swr-default-state { 3032 clk-pins { 3033 pins = "gpio15"; 3034 function = "wsa2_swr_clk"; 3035 drive-strength = <2>; 3036 slew-rate = <1>; 3037 bias-disable; 3038 }; 3039 3040 data-pins { 3041 pins = "gpio16"; 3042 function = "wsa2_swr_data"; 3043 drive-strength = <2>; 3044 slew-rate = <1>; 3045 bias-bus-hold; 3046 }; 3047 }; 3048 }; 3049 3050 lpasscc: clock-controller@33e0000 { 3051 compatible = "qcom,sc8280xp-lpasscc"; 3052 reg = <0 0x033e0000 0 0x12000>; 3053 #clock-cells = <1>; 3054 #reset-cells = <1>; 3055 }; 3056 3057 sdc2: mmc@8804000 { 3058 compatible = "qcom,sc8280xp-sdhci", "qcom,sdhci-msm-v5"; 3059 reg = <0 0x08804000 0 0x1000>; 3060 3061 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 3062 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 3063 interrupt-names = "hc_irq", "pwr_irq"; 3064 3065 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3066 <&gcc GCC_SDCC2_APPS_CLK>, 3067 <&rpmhcc RPMH_CXO_CLK>; 3068 clock-names = "iface", "core", "xo"; 3069 resets = <&gcc GCC_SDCC2_BCR>; 3070 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 3071 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; 3072 interconnect-names = "sdhc-ddr","cpu-sdhc"; 3073 iommus = <&apps_smmu 0x4e0 0x0>; 3074 power-domains = <&rpmhpd SC8280XP_CX>; 3075 operating-points-v2 = <&sdc2_opp_table>; 3076 bus-width = <4>; 3077 dma-coherent; 3078 3079 status = "disabled"; 3080 3081 sdc2_opp_table: opp-table { 3082 compatible = "operating-points-v2"; 3083 3084 opp-100000000 { 3085 opp-hz = /bits/ 64 <100000000>; 3086 required-opps = <&rpmhpd_opp_low_svs>; 3087 opp-peak-kBps = <1800000 400000>; 3088 opp-avg-kBps = <100000 0>; 3089 }; 3090 3091 opp-202000000 { 3092 opp-hz = /bits/ 64 <202000000>; 3093 required-opps = <&rpmhpd_opp_svs_l1>; 3094 opp-peak-kBps = <5400000 1600000>; 3095 opp-avg-kBps = <200000 0>; 3096 }; 3097 }; 3098 }; 3099 3100 usb_0_qmpphy: phy@88eb000 { 3101 compatible = "qcom,sc8280xp-qmp-usb43dp-phy"; 3102 reg = <0 0x088eb000 0 0x4000>; 3103 3104 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3105 <&gcc GCC_USB4_EUD_CLKREF_CLK>, 3106 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 3107 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3108 clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 3109 3110 power-domains = <&gcc USB30_PRIM_GDSC>; 3111 3112 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 3113 <&gcc GCC_USB4_DP_PHY_PRIM_BCR>; 3114 reset-names = "phy", "common"; 3115 3116 #clock-cells = <1>; 3117 #phy-cells = <1>; 3118 3119 status = "disabled"; 3120 3121 ports { 3122 #address-cells = <1>; 3123 #size-cells = <0>; 3124 3125 port@0 { 3126 reg = <0>; 3127 3128 usb_0_qmpphy_out: endpoint {}; 3129 }; 3130 3131 port@2 { 3132 reg = <2>; 3133 3134 usb_0_qmpphy_dp_in: endpoint {}; 3135 }; 3136 }; 3137 }; 3138 3139 usb_1_hsphy: phy@8902000 { 3140 compatible = "qcom,sc8280xp-usb-hs-phy", 3141 "qcom,usb-snps-hs-5nm-phy"; 3142 reg = <0 0x08902000 0 0x400>; 3143 #phy-cells = <0>; 3144 3145 clocks = <&rpmhcc RPMH_CXO_CLK>; 3146 clock-names = "ref"; 3147 3148 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3149 3150 status = "disabled"; 3151 }; 3152 3153 usb_1_qmpphy: phy@8903000 { 3154 compatible = "qcom,sc8280xp-qmp-usb43dp-phy"; 3155 reg = <0 0x08903000 0 0x4000>; 3156 3157 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 3158 <&gcc GCC_USB4_CLKREF_CLK>, 3159 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, 3160 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 3161 clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 3162 3163 power-domains = <&gcc USB30_SEC_GDSC>; 3164 3165 resets = <&gcc GCC_USB3_PHY_SEC_BCR>, 3166 <&gcc GCC_USB4_1_DP_PHY_PRIM_BCR>; 3167 reset-names = "phy", "common"; 3168 3169 #clock-cells = <1>; 3170 #phy-cells = <1>; 3171 3172 status = "disabled"; 3173 3174 ports { 3175 #address-cells = <1>; 3176 #size-cells = <0>; 3177 3178 port@0 { 3179 reg = <0>; 3180 3181 usb_1_qmpphy_out: endpoint {}; 3182 }; 3183 3184 port@2 { 3185 reg = <2>; 3186 3187 usb_1_qmpphy_dp_in: endpoint {}; 3188 }; 3189 }; 3190 }; 3191 3192 mdss1_dp0_phy: phy@8909a00 { 3193 compatible = "qcom,sc8280xp-dp-phy"; 3194 reg = <0 0x08909a00 0 0x19c>, 3195 <0 0x08909200 0 0xec>, 3196 <0 0x08909600 0 0xec>, 3197 <0 0x08909000 0 0x1c8>; 3198 3199 clocks = <&dispcc1 DISP_CC_MDSS_DPTX0_AUX_CLK>, 3200 <&dispcc1 DISP_CC_MDSS_AHB_CLK>; 3201 clock-names = "aux", "cfg_ahb"; 3202 power-domains = <&rpmhpd SC8280XP_MX>; 3203 3204 #clock-cells = <1>; 3205 #phy-cells = <0>; 3206 3207 status = "disabled"; 3208 }; 3209 3210 mdss1_dp1_phy: phy@890ca00 { 3211 compatible = "qcom,sc8280xp-dp-phy"; 3212 reg = <0 0x0890ca00 0 0x19c>, 3213 <0 0x0890c200 0 0xec>, 3214 <0 0x0890c600 0 0xec>, 3215 <0 0x0890c000 0 0x1c8>; 3216 3217 clocks = <&dispcc1 DISP_CC_MDSS_DPTX1_AUX_CLK>, 3218 <&dispcc1 DISP_CC_MDSS_AHB_CLK>; 3219 clock-names = "aux", "cfg_ahb"; 3220 power-domains = <&rpmhpd SC8280XP_MX>; 3221 3222 #clock-cells = <1>; 3223 #phy-cells = <0>; 3224 3225 status = "disabled"; 3226 }; 3227 3228 pmu@9091000 { 3229 compatible = "qcom,sc8280xp-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; 3230 reg = <0 0x09091000 0 0x1000>; 3231 3232 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 3233 3234 interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>; 3235 3236 operating-points-v2 = <&llcc_bwmon_opp_table>; 3237 3238 llcc_bwmon_opp_table: opp-table { 3239 compatible = "operating-points-v2"; 3240 3241 opp-0 { 3242 opp-peak-kBps = <762000>; 3243 }; 3244 opp-1 { 3245 opp-peak-kBps = <1720000>; 3246 }; 3247 opp-2 { 3248 opp-peak-kBps = <2086000>; 3249 }; 3250 opp-3 { 3251 opp-peak-kBps = <2597000>; 3252 }; 3253 opp-4 { 3254 opp-peak-kBps = <2929000>; 3255 }; 3256 opp-5 { 3257 opp-peak-kBps = <3879000>; 3258 }; 3259 opp-6 { 3260 opp-peak-kBps = <5161000>; 3261 }; 3262 opp-7 { 3263 opp-peak-kBps = <5931000>; 3264 }; 3265 opp-8 { 3266 opp-peak-kBps = <6515000>; 3267 }; 3268 opp-9 { 3269 opp-peak-kBps = <7980000>; 3270 }; 3271 opp-10 { 3272 opp-peak-kBps = <8136000>; 3273 }; 3274 opp-11 { 3275 opp-peak-kBps = <10437000>; 3276 }; 3277 opp-12 { 3278 opp-peak-kBps = <12191000>; 3279 }; 3280 }; 3281 }; 3282 3283 pmu@90b6400 { 3284 compatible = "qcom,sc8280xp-cpu-bwmon", "qcom,sdm845-bwmon"; 3285 reg = <0 0x090b6400 0 0x600>; 3286 3287 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 3288 3289 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>; 3290 operating-points-v2 = <&cpu_bwmon_opp_table>; 3291 3292 cpu_bwmon_opp_table: opp-table { 3293 compatible = "operating-points-v2"; 3294 3295 opp-0 { 3296 opp-peak-kBps = <2288000>; 3297 }; 3298 opp-1 { 3299 opp-peak-kBps = <4577000>; 3300 }; 3301 opp-2 { 3302 opp-peak-kBps = <7110000>; 3303 }; 3304 opp-3 { 3305 opp-peak-kBps = <9155000>; 3306 }; 3307 opp-4 { 3308 opp-peak-kBps = <12298000>; 3309 }; 3310 opp-5 { 3311 opp-peak-kBps = <14236000>; 3312 }; 3313 opp-6 { 3314 opp-peak-kBps = <15258001>; 3315 }; 3316 }; 3317 }; 3318 3319 system-cache-controller@9200000 { 3320 compatible = "qcom,sc8280xp-llcc"; 3321 reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, 3322 <0 0x09300000 0 0x58000>, <0 0x09380000 0 0x58000>, 3323 <0 0x09400000 0 0x58000>, <0 0x09480000 0 0x58000>, 3324 <0 0x09500000 0 0x58000>, <0 0x09580000 0 0x58000>, 3325 <0 0x09600000 0 0x58000>; 3326 reg-names = "llcc0_base", "llcc1_base", "llcc2_base", 3327 "llcc3_base", "llcc4_base", "llcc5_base", 3328 "llcc6_base", "llcc7_base", "llcc_broadcast_base"; 3329 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 3330 }; 3331 3332 usb_0: usb@a6f8800 { 3333 compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3"; 3334 reg = <0 0x0a6f8800 0 0x400>; 3335 #address-cells = <2>; 3336 #size-cells = <2>; 3337 ranges; 3338 3339 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3340 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3341 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3342 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 3343 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3344 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 3345 <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>, 3346 <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>, 3347 <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 3348 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", 3349 "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys"; 3350 3351 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3352 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3353 assigned-clock-rates = <19200000>, <200000000>; 3354 3355 interrupts-extended = <&intc GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>, 3356 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 3357 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 3358 <&pdc 138 IRQ_TYPE_LEVEL_HIGH>; 3359 interrupt-names = "pwr_event", 3360 "dp_hs_phy_irq", 3361 "dm_hs_phy_irq", 3362 "ss_phy_irq"; 3363 3364 power-domains = <&gcc USB30_PRIM_GDSC>; 3365 required-opps = <&rpmhpd_opp_nom>; 3366 3367 resets = <&gcc GCC_USB30_PRIM_BCR>; 3368 3369 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 3370 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; 3371 interconnect-names = "usb-ddr", "apps-usb"; 3372 3373 wakeup-source; 3374 3375 status = "disabled"; 3376 3377 usb_0_dwc3: usb@a600000 { 3378 compatible = "snps,dwc3"; 3379 reg = <0 0x0a600000 0 0xcd00>; 3380 interrupts = <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>; 3381 iommus = <&apps_smmu 0x820 0x0>; 3382 phys = <&usb_0_hsphy>, <&usb_0_qmpphy QMP_USB43DP_USB3_PHY>; 3383 phy-names = "usb2-phy", "usb3-phy"; 3384 3385 port { 3386 usb_0_role_switch: endpoint { 3387 }; 3388 }; 3389 }; 3390 }; 3391 3392 usb_1: usb@a8f8800 { 3393 compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3"; 3394 reg = <0 0x0a8f8800 0 0x400>; 3395 #address-cells = <2>; 3396 #size-cells = <2>; 3397 ranges; 3398 3399 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 3400 <&gcc GCC_USB30_SEC_MASTER_CLK>, 3401 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 3402 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 3403 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3404 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 3405 <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>, 3406 <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>, 3407 <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 3408 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", 3409 "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys"; 3410 3411 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3412 <&gcc GCC_USB30_SEC_MASTER_CLK>; 3413 assigned-clock-rates = <19200000>, <200000000>; 3414 3415 interrupts-extended = <&intc GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>, 3416 <&pdc 12 IRQ_TYPE_EDGE_BOTH>, 3417 <&pdc 13 IRQ_TYPE_EDGE_BOTH>, 3418 <&pdc 136 IRQ_TYPE_LEVEL_HIGH>; 3419 interrupt-names = "pwr_event", 3420 "dp_hs_phy_irq", 3421 "dm_hs_phy_irq", 3422 "ss_phy_irq"; 3423 3424 power-domains = <&gcc USB30_SEC_GDSC>; 3425 required-opps = <&rpmhpd_opp_nom>; 3426 3427 resets = <&gcc GCC_USB30_SEC_BCR>; 3428 3429 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>, 3430 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>; 3431 interconnect-names = "usb-ddr", "apps-usb"; 3432 3433 wakeup-source; 3434 3435 status = "disabled"; 3436 3437 usb_1_dwc3: usb@a800000 { 3438 compatible = "snps,dwc3"; 3439 reg = <0 0x0a800000 0 0xcd00>; 3440 interrupts = <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>; 3441 iommus = <&apps_smmu 0x860 0x0>; 3442 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 3443 phy-names = "usb2-phy", "usb3-phy"; 3444 3445 port { 3446 usb_1_role_switch: endpoint { 3447 }; 3448 }; 3449 }; 3450 }; 3451 3452 mdss0: display-subsystem@ae00000 { 3453 compatible = "qcom,sc8280xp-mdss"; 3454 reg = <0 0x0ae00000 0 0x1000>; 3455 reg-names = "mdss"; 3456 3457 clocks = <&gcc GCC_DISP_AHB_CLK>, 3458 <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 3459 <&dispcc0 DISP_CC_MDSS_MDP_CLK>; 3460 clock-names = "iface", 3461 "ahb", 3462 "core"; 3463 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 3464 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>, 3465 <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>; 3466 interconnect-names = "mdp0-mem", "mdp1-mem"; 3467 iommus = <&apps_smmu 0x1000 0x402>; 3468 power-domains = <&dispcc0 MDSS_GDSC>; 3469 resets = <&dispcc0 DISP_CC_MDSS_CORE_BCR>; 3470 3471 interrupt-controller; 3472 #interrupt-cells = <1>; 3473 #address-cells = <2>; 3474 #size-cells = <2>; 3475 ranges; 3476 3477 status = "disabled"; 3478 3479 mdss0_mdp: display-controller@ae01000 { 3480 compatible = "qcom,sc8280xp-dpu"; 3481 reg = <0 0x0ae01000 0 0x8f000>, 3482 <0 0x0aeb0000 0 0x2008>; 3483 reg-names = "mdp", "vbif"; 3484 3485 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 3486 <&gcc GCC_DISP_SF_AXI_CLK>, 3487 <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 3488 <&dispcc0 DISP_CC_MDSS_MDP_LUT_CLK>, 3489 <&dispcc0 DISP_CC_MDSS_MDP_CLK>, 3490 <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>; 3491 clock-names = "bus", 3492 "nrt_bus", 3493 "iface", 3494 "lut", 3495 "core", 3496 "vsync"; 3497 interrupt-parent = <&mdss0>; 3498 interrupts = <0>; 3499 power-domains = <&rpmhpd SC8280XP_MMCX>; 3500 3501 assigned-clocks = <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>; 3502 assigned-clock-rates = <19200000>; 3503 operating-points-v2 = <&mdss0_mdp_opp_table>; 3504 3505 ports { 3506 #address-cells = <1>; 3507 #size-cells = <0>; 3508 3509 port@0 { 3510 reg = <0>; 3511 mdss0_intf0_out: endpoint { 3512 remote-endpoint = <&mdss0_dp0_in>; 3513 }; 3514 }; 3515 3516 port@4 { 3517 reg = <4>; 3518 mdss0_intf4_out: endpoint { 3519 remote-endpoint = <&mdss0_dp1_in>; 3520 }; 3521 }; 3522 3523 port@5 { 3524 reg = <5>; 3525 mdss0_intf5_out: endpoint { 3526 remote-endpoint = <&mdss0_dp3_in>; 3527 }; 3528 }; 3529 3530 port@6 { 3531 reg = <6>; 3532 mdss0_intf6_out: endpoint { 3533 remote-endpoint = <&mdss0_dp2_in>; 3534 }; 3535 }; 3536 }; 3537 3538 mdss0_mdp_opp_table: opp-table { 3539 compatible = "operating-points-v2"; 3540 3541 opp-200000000 { 3542 opp-hz = /bits/ 64 <200000000>; 3543 required-opps = <&rpmhpd_opp_low_svs>; 3544 }; 3545 3546 opp-300000000 { 3547 opp-hz = /bits/ 64 <300000000>; 3548 required-opps = <&rpmhpd_opp_svs>; 3549 }; 3550 3551 opp-375000000 { 3552 opp-hz = /bits/ 64 <375000000>; 3553 required-opps = <&rpmhpd_opp_svs_l1>; 3554 }; 3555 3556 opp-500000000 { 3557 opp-hz = /bits/ 64 <500000000>; 3558 required-opps = <&rpmhpd_opp_nom>; 3559 }; 3560 opp-600000000 { 3561 opp-hz = /bits/ 64 <600000000>; 3562 required-opps = <&rpmhpd_opp_turbo_l1>; 3563 }; 3564 }; 3565 }; 3566 3567 mdss0_dp0: displayport-controller@ae90000 { 3568 compatible = "qcom,sc8280xp-dp"; 3569 reg = <0 0xae90000 0 0x200>, 3570 <0 0xae90200 0 0x200>, 3571 <0 0xae90400 0 0x600>, 3572 <0 0xae91000 0 0x400>, 3573 <0 0xae91400 0 0x400>; 3574 interrupt-parent = <&mdss0>; 3575 interrupts = <12>; 3576 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 3577 <&dispcc0 DISP_CC_MDSS_DPTX0_AUX_CLK>, 3578 <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_CLK>, 3579 <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 3580 <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; 3581 clock-names = "core_iface", "core_aux", 3582 "ctrl_link", 3583 "ctrl_link_iface", 3584 "stream_pixel"; 3585 3586 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 3587 <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; 3588 assigned-clock-parents = <&usb_0_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3589 <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 3590 3591 phys = <&usb_0_qmpphy QMP_USB43DP_DP_PHY>; 3592 phy-names = "dp"; 3593 3594 #sound-dai-cells = <0>; 3595 3596 operating-points-v2 = <&mdss0_dp0_opp_table>; 3597 power-domains = <&rpmhpd SC8280XP_MMCX>; 3598 3599 status = "disabled"; 3600 3601 ports { 3602 #address-cells = <1>; 3603 #size-cells = <0>; 3604 3605 port@0 { 3606 reg = <0>; 3607 3608 mdss0_dp0_in: endpoint { 3609 remote-endpoint = <&mdss0_intf0_out>; 3610 }; 3611 }; 3612 3613 port@1 { 3614 reg = <1>; 3615 3616 mdss0_dp0_out: endpoint { 3617 }; 3618 }; 3619 }; 3620 3621 mdss0_dp0_opp_table: opp-table { 3622 compatible = "operating-points-v2"; 3623 3624 opp-160000000 { 3625 opp-hz = /bits/ 64 <160000000>; 3626 required-opps = <&rpmhpd_opp_low_svs>; 3627 }; 3628 3629 opp-270000000 { 3630 opp-hz = /bits/ 64 <270000000>; 3631 required-opps = <&rpmhpd_opp_svs>; 3632 }; 3633 3634 opp-540000000 { 3635 opp-hz = /bits/ 64 <540000000>; 3636 required-opps = <&rpmhpd_opp_svs_l1>; 3637 }; 3638 3639 opp-810000000 { 3640 opp-hz = /bits/ 64 <810000000>; 3641 required-opps = <&rpmhpd_opp_nom>; 3642 }; 3643 }; 3644 }; 3645 3646 mdss0_dp1: displayport-controller@ae98000 { 3647 compatible = "qcom,sc8280xp-dp"; 3648 reg = <0 0xae98000 0 0x200>, 3649 <0 0xae98200 0 0x200>, 3650 <0 0xae98400 0 0x600>, 3651 <0 0xae99000 0 0x400>, 3652 <0 0xae99400 0 0x400>; 3653 interrupt-parent = <&mdss0>; 3654 interrupts = <13>; 3655 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 3656 <&dispcc0 DISP_CC_MDSS_DPTX1_AUX_CLK>, 3657 <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_CLK>, 3658 <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, 3659 <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>; 3660 clock-names = "core_iface", "core_aux", 3661 "ctrl_link", 3662 "ctrl_link_iface", "stream_pixel"; 3663 3664 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, 3665 <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>; 3666 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3667 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 3668 3669 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; 3670 phy-names = "dp"; 3671 3672 #sound-dai-cells = <0>; 3673 3674 operating-points-v2 = <&mdss0_dp1_opp_table>; 3675 power-domains = <&rpmhpd SC8280XP_MMCX>; 3676 3677 status = "disabled"; 3678 3679 ports { 3680 #address-cells = <1>; 3681 #size-cells = <0>; 3682 3683 port@0 { 3684 reg = <0>; 3685 3686 mdss0_dp1_in: endpoint { 3687 remote-endpoint = <&mdss0_intf4_out>; 3688 }; 3689 }; 3690 3691 port@1 { 3692 reg = <1>; 3693 3694 mdss0_dp1_out: endpoint { 3695 }; 3696 }; 3697 }; 3698 3699 mdss0_dp1_opp_table: opp-table { 3700 compatible = "operating-points-v2"; 3701 3702 opp-160000000 { 3703 opp-hz = /bits/ 64 <160000000>; 3704 required-opps = <&rpmhpd_opp_low_svs>; 3705 }; 3706 3707 opp-270000000 { 3708 opp-hz = /bits/ 64 <270000000>; 3709 required-opps = <&rpmhpd_opp_svs>; 3710 }; 3711 3712 opp-540000000 { 3713 opp-hz = /bits/ 64 <540000000>; 3714 required-opps = <&rpmhpd_opp_svs_l1>; 3715 }; 3716 3717 opp-810000000 { 3718 opp-hz = /bits/ 64 <810000000>; 3719 required-opps = <&rpmhpd_opp_nom>; 3720 }; 3721 }; 3722 }; 3723 3724 mdss0_dp2: displayport-controller@ae9a000 { 3725 compatible = "qcom,sc8280xp-dp"; 3726 reg = <0 0xae9a000 0 0x200>, 3727 <0 0xae9a200 0 0x200>, 3728 <0 0xae9a400 0 0x600>, 3729 <0 0xae9b000 0 0x400>, 3730 <0 0xae9b400 0 0x400>; 3731 3732 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 3733 <&dispcc0 DISP_CC_MDSS_DPTX2_AUX_CLK>, 3734 <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_CLK>, 3735 <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>, 3736 <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>; 3737 clock-names = "core_iface", "core_aux", 3738 "ctrl_link", 3739 "ctrl_link_iface", "stream_pixel"; 3740 interrupt-parent = <&mdss0>; 3741 interrupts = <14>; 3742 phys = <&mdss0_dp2_phy>; 3743 phy-names = "dp"; 3744 power-domains = <&rpmhpd SC8280XP_MMCX>; 3745 3746 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>, 3747 <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>; 3748 assigned-clock-parents = <&mdss0_dp2_phy 0>, <&mdss0_dp2_phy 1>; 3749 operating-points-v2 = <&mdss0_dp2_opp_table>; 3750 3751 #sound-dai-cells = <0>; 3752 3753 status = "disabled"; 3754 3755 ports { 3756 #address-cells = <1>; 3757 #size-cells = <0>; 3758 3759 port@0 { 3760 reg = <0>; 3761 mdss0_dp2_in: endpoint { 3762 remote-endpoint = <&mdss0_intf6_out>; 3763 }; 3764 }; 3765 3766 port@1 { 3767 reg = <1>; 3768 }; 3769 }; 3770 3771 mdss0_dp2_opp_table: opp-table { 3772 compatible = "operating-points-v2"; 3773 3774 opp-160000000 { 3775 opp-hz = /bits/ 64 <160000000>; 3776 required-opps = <&rpmhpd_opp_low_svs>; 3777 }; 3778 3779 opp-270000000 { 3780 opp-hz = /bits/ 64 <270000000>; 3781 required-opps = <&rpmhpd_opp_svs>; 3782 }; 3783 3784 opp-540000000 { 3785 opp-hz = /bits/ 64 <540000000>; 3786 required-opps = <&rpmhpd_opp_svs_l1>; 3787 }; 3788 3789 opp-810000000 { 3790 opp-hz = /bits/ 64 <810000000>; 3791 required-opps = <&rpmhpd_opp_nom>; 3792 }; 3793 }; 3794 }; 3795 3796 mdss0_dp3: displayport-controller@aea0000 { 3797 compatible = "qcom,sc8280xp-dp"; 3798 reg = <0 0xaea0000 0 0x200>, 3799 <0 0xaea0200 0 0x200>, 3800 <0 0xaea0400 0 0x600>, 3801 <0 0xaea1000 0 0x400>, 3802 <0 0xaea1400 0 0x400>; 3803 3804 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 3805 <&dispcc0 DISP_CC_MDSS_DPTX3_AUX_CLK>, 3806 <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_CLK>, 3807 <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>, 3808 <&dispcc0 DISP_CC_MDSS_DPTX3_PIXEL0_CLK>; 3809 clock-names = "core_iface", "core_aux", 3810 "ctrl_link", 3811 "ctrl_link_iface", "stream_pixel"; 3812 interrupt-parent = <&mdss0>; 3813 interrupts = <15>; 3814 phys = <&mdss0_dp3_phy>; 3815 phy-names = "dp"; 3816 power-domains = <&rpmhpd SC8280XP_MMCX>; 3817 3818 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>, 3819 <&dispcc0 DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>; 3820 assigned-clock-parents = <&mdss0_dp3_phy 0>, <&mdss0_dp3_phy 1>; 3821 operating-points-v2 = <&mdss0_dp3_opp_table>; 3822 3823 #sound-dai-cells = <0>; 3824 3825 status = "disabled"; 3826 3827 ports { 3828 #address-cells = <1>; 3829 #size-cells = <0>; 3830 3831 port@0 { 3832 reg = <0>; 3833 mdss0_dp3_in: endpoint { 3834 remote-endpoint = <&mdss0_intf5_out>; 3835 }; 3836 }; 3837 3838 port@1 { 3839 reg = <1>; 3840 }; 3841 }; 3842 3843 mdss0_dp3_opp_table: opp-table { 3844 compatible = "operating-points-v2"; 3845 3846 opp-160000000 { 3847 opp-hz = /bits/ 64 <160000000>; 3848 required-opps = <&rpmhpd_opp_low_svs>; 3849 }; 3850 3851 opp-270000000 { 3852 opp-hz = /bits/ 64 <270000000>; 3853 required-opps = <&rpmhpd_opp_svs>; 3854 }; 3855 3856 opp-540000000 { 3857 opp-hz = /bits/ 64 <540000000>; 3858 required-opps = <&rpmhpd_opp_svs_l1>; 3859 }; 3860 3861 opp-810000000 { 3862 opp-hz = /bits/ 64 <810000000>; 3863 required-opps = <&rpmhpd_opp_nom>; 3864 }; 3865 }; 3866 }; 3867 }; 3868 3869 mdss0_dp2_phy: phy@aec2a00 { 3870 compatible = "qcom,sc8280xp-dp-phy"; 3871 reg = <0 0x0aec2a00 0 0x19c>, 3872 <0 0x0aec2200 0 0xec>, 3873 <0 0x0aec2600 0 0xec>, 3874 <0 0x0aec2000 0 0x1c8>; 3875 3876 clocks = <&dispcc0 DISP_CC_MDSS_DPTX2_AUX_CLK>, 3877 <&dispcc0 DISP_CC_MDSS_AHB_CLK>; 3878 clock-names = "aux", "cfg_ahb"; 3879 power-domains = <&rpmhpd SC8280XP_MX>; 3880 3881 #clock-cells = <1>; 3882 #phy-cells = <0>; 3883 3884 status = "disabled"; 3885 }; 3886 3887 mdss0_dp3_phy: phy@aec5a00 { 3888 compatible = "qcom,sc8280xp-dp-phy"; 3889 reg = <0 0x0aec5a00 0 0x19c>, 3890 <0 0x0aec5200 0 0xec>, 3891 <0 0x0aec5600 0 0xec>, 3892 <0 0x0aec5000 0 0x1c8>; 3893 3894 clocks = <&dispcc0 DISP_CC_MDSS_DPTX3_AUX_CLK>, 3895 <&dispcc0 DISP_CC_MDSS_AHB_CLK>; 3896 clock-names = "aux", "cfg_ahb"; 3897 power-domains = <&rpmhpd SC8280XP_MX>; 3898 3899 #clock-cells = <1>; 3900 #phy-cells = <0>; 3901 3902 status = "disabled"; 3903 }; 3904 3905 dispcc0: clock-controller@af00000 { 3906 compatible = "qcom,sc8280xp-dispcc0"; 3907 reg = <0 0x0af00000 0 0x20000>; 3908 3909 clocks = <&gcc GCC_DISP_AHB_CLK>, 3910 <&rpmhcc RPMH_CXO_CLK>, 3911 <&sleep_clk>, 3912 <&usb_0_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3913 <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 3914 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3915 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 3916 <&mdss0_dp2_phy 0>, 3917 <&mdss0_dp2_phy 1>, 3918 <&mdss0_dp3_phy 0>, 3919 <&mdss0_dp3_phy 1>, 3920 <0>, 3921 <0>, 3922 <0>, 3923 <0>; 3924 power-domains = <&rpmhpd SC8280XP_MMCX>; 3925 3926 #clock-cells = <1>; 3927 #power-domain-cells = <1>; 3928 #reset-cells = <1>; 3929 3930 status = "disabled"; 3931 }; 3932 3933 pdc: interrupt-controller@b220000 { 3934 compatible = "qcom,sc8280xp-pdc", "qcom,pdc"; 3935 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; 3936 qcom,pdc-ranges = <0 480 40>, 3937 <40 140 14>, 3938 <54 263 1>, 3939 <55 306 4>, 3940 <59 312 3>, 3941 <62 374 2>, 3942 <64 434 2>, 3943 <66 438 3>, 3944 <69 86 1>, 3945 <70 520 54>, 3946 <124 609 28>, 3947 <159 638 1>, 3948 <160 720 8>, 3949 <168 801 1>, 3950 <169 728 30>, 3951 <199 416 2>, 3952 <201 449 1>, 3953 <202 89 1>, 3954 <203 451 1>, 3955 <204 462 1>, 3956 <205 264 1>, 3957 <206 579 1>, 3958 <207 653 1>, 3959 <208 656 1>, 3960 <209 659 1>, 3961 <210 122 1>, 3962 <211 699 1>, 3963 <212 705 1>, 3964 <213 450 1>, 3965 <214 643 1>, 3966 <216 646 5>, 3967 <221 390 5>, 3968 <226 700 3>, 3969 <229 240 3>, 3970 <232 269 1>, 3971 <233 377 1>, 3972 <234 372 1>, 3973 <235 138 1>, 3974 <236 857 1>, 3975 <237 860 1>, 3976 <238 137 1>, 3977 <239 668 1>, 3978 <240 366 1>, 3979 <241 949 1>, 3980 <242 815 5>, 3981 <247 769 1>, 3982 <248 768 1>, 3983 <249 663 1>, 3984 <250 799 2>, 3985 <252 798 1>, 3986 <253 765 1>, 3987 <254 763 1>, 3988 <255 454 1>, 3989 <258 139 1>, 3990 <259 786 2>, 3991 <261 370 2>, 3992 <263 158 2>; 3993 #interrupt-cells = <2>; 3994 interrupt-parent = <&intc>; 3995 interrupt-controller; 3996 }; 3997 3998 tsens0: thermal-sensor@c263000 { 3999 compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2"; 4000 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 4001 <0 0x0c222000 0 0x8>; /* SROT */ 4002 #qcom,sensors = <14>; 4003 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, 4004 <&pdc 28 IRQ_TYPE_LEVEL_HIGH>; 4005 interrupt-names = "uplow", "critical"; 4006 #thermal-sensor-cells = <1>; 4007 }; 4008 4009 tsens1: thermal-sensor@c265000 { 4010 compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2"; 4011 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 4012 <0 0x0c223000 0 0x8>; /* SROT */ 4013 #qcom,sensors = <16>; 4014 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, 4015 <&pdc 29 IRQ_TYPE_LEVEL_HIGH>; 4016 interrupt-names = "uplow", "critical"; 4017 #thermal-sensor-cells = <1>; 4018 }; 4019 4020 aoss_qmp: power-management@c300000 { 4021 compatible = "qcom,sc8280xp-aoss-qmp", "qcom,aoss-qmp"; 4022 reg = <0 0x0c300000 0 0x400>; 4023 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>; 4024 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 4025 4026 #clock-cells = <0>; 4027 }; 4028 4029 sram@c3f0000 { 4030 compatible = "qcom,rpmh-stats"; 4031 reg = <0 0x0c3f0000 0 0x400>; 4032 }; 4033 4034 spmi_bus: spmi@c440000 { 4035 compatible = "qcom,spmi-pmic-arb"; 4036 reg = <0 0x0c440000 0 0x1100>, 4037 <0 0x0c600000 0 0x2000000>, 4038 <0 0x0e600000 0 0x100000>, 4039 <0 0x0e700000 0 0xa0000>, 4040 <0 0x0c40a000 0 0x26000>; 4041 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 4042 interrupt-names = "periph_irq"; 4043 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 4044 qcom,ee = <0>; 4045 qcom,channel = <0>; 4046 #address-cells = <2>; 4047 #size-cells = <0>; 4048 interrupt-controller; 4049 #interrupt-cells = <4>; 4050 }; 4051 4052 tlmm: pinctrl@f100000 { 4053 compatible = "qcom,sc8280xp-tlmm"; 4054 reg = <0 0x0f100000 0 0x300000>; 4055 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 4056 gpio-controller; 4057 #gpio-cells = <2>; 4058 interrupt-controller; 4059 #interrupt-cells = <2>; 4060 gpio-ranges = <&tlmm 0 0 230>; 4061 }; 4062 4063 apps_smmu: iommu@15000000 { 4064 compatible = "qcom,sc8280xp-smmu-500", "arm,mmu-500"; 4065 reg = <0 0x15000000 0 0x100000>; 4066 #iommu-cells = <2>; 4067 #global-interrupts = <2>; 4068 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 4069 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 4070 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 4071 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 4072 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 4073 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 4074 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 4075 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 4076 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 4077 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 4078 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 4079 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 4080 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 4081 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 4082 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 4083 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 4084 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 4085 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 4086 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 4087 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 4088 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 4089 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 4090 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 4091 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 4092 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 4093 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 4094 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 4095 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 4096 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 4097 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 4098 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 4099 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 4100 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 4101 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 4102 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 4103 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 4104 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 4105 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 4106 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 4107 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 4108 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 4109 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 4110 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 4111 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 4112 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 4113 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 4114 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 4115 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 4116 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 4117 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 4118 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 4119 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 4120 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 4121 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 4122 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 4123 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 4124 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 4125 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 4126 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 4127 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 4128 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 4129 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 4130 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 4131 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 4132 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 4133 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 4134 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 4135 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 4136 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 4137 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 4138 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 4139 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 4140 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 4141 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 4142 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 4143 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 4144 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 4145 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 4146 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 4147 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 4148 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, 4149 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 4150 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 4151 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 4152 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, 4153 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 4154 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 4155 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 4156 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 4157 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 4158 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 4159 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 4160 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 4161 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 4162 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 4163 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>, 4164 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 4165 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 4166 <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>, 4167 <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>, 4168 <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>, 4169 <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>, 4170 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 4171 <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>, 4172 <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>, 4173 <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>, 4174 <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>, 4175 <GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH>, 4176 <GIC_SPI 911 IRQ_TYPE_LEVEL_HIGH>, 4177 <GIC_SPI 910 IRQ_TYPE_LEVEL_HIGH>, 4178 <GIC_SPI 909 IRQ_TYPE_LEVEL_HIGH>, 4179 <GIC_SPI 908 IRQ_TYPE_LEVEL_HIGH>, 4180 <GIC_SPI 907 IRQ_TYPE_LEVEL_HIGH>, 4181 <GIC_SPI 906 IRQ_TYPE_LEVEL_HIGH>, 4182 <GIC_SPI 905 IRQ_TYPE_LEVEL_HIGH>, 4183 <GIC_SPI 904 IRQ_TYPE_LEVEL_HIGH>, 4184 <GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>, 4185 <GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>, 4186 <GIC_SPI 901 IRQ_TYPE_LEVEL_HIGH>, 4187 <GIC_SPI 900 IRQ_TYPE_LEVEL_HIGH>, 4188 <GIC_SPI 899 IRQ_TYPE_LEVEL_HIGH>, 4189 <GIC_SPI 898 IRQ_TYPE_LEVEL_HIGH>, 4190 <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>, 4191 <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>, 4192 <GIC_SPI 895 IRQ_TYPE_LEVEL_HIGH>, 4193 <GIC_SPI 894 IRQ_TYPE_LEVEL_HIGH>, 4194 <GIC_SPI 893 IRQ_TYPE_LEVEL_HIGH>, 4195 <GIC_SPI 892 IRQ_TYPE_LEVEL_HIGH>, 4196 <GIC_SPI 891 IRQ_TYPE_LEVEL_HIGH>, 4197 <GIC_SPI 890 IRQ_TYPE_LEVEL_HIGH>; 4198 }; 4199 4200 intc: interrupt-controller@17a00000 { 4201 compatible = "arm,gic-v3"; 4202 interrupt-controller; 4203 #interrupt-cells = <3>; 4204 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 4205 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 4206 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 4207 #redistributor-regions = <1>; 4208 redistributor-stride = <0 0x20000>; 4209 4210 #address-cells = <2>; 4211 #size-cells = <2>; 4212 ranges; 4213 4214 msi-controller@17a40000 { 4215 compatible = "arm,gic-v3-its"; 4216 reg = <0 0x17a40000 0 0x20000>; 4217 msi-controller; 4218 #msi-cells = <1>; 4219 }; 4220 }; 4221 4222 watchdog@17c10000 { 4223 compatible = "qcom,apss-wdt-sc8280xp", "qcom,kpss-wdt"; 4224 reg = <0 0x17c10000 0 0x1000>; 4225 clocks = <&sleep_clk>; 4226 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 4227 }; 4228 4229 timer@17c20000 { 4230 compatible = "arm,armv7-timer-mem"; 4231 reg = <0x0 0x17c20000 0x0 0x1000>; 4232 #address-cells = <1>; 4233 #size-cells = <1>; 4234 ranges = <0x0 0x0 0x0 0x20000000>; 4235 4236 frame@17c21000 { 4237 frame-number = <0>; 4238 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 4239 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 4240 reg = <0x17c21000 0x1000>, 4241 <0x17c22000 0x1000>; 4242 }; 4243 4244 frame@17c23000 { 4245 frame-number = <1>; 4246 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 4247 reg = <0x17c23000 0x1000>; 4248 status = "disabled"; 4249 }; 4250 4251 frame@17c25000 { 4252 frame-number = <2>; 4253 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 4254 reg = <0x17c25000 0x1000>; 4255 status = "disabled"; 4256 }; 4257 4258 frame@17c27000 { 4259 frame-number = <3>; 4260 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 4261 reg = <0x17c26000 0x1000>; 4262 status = "disabled"; 4263 }; 4264 4265 frame@17c29000 { 4266 frame-number = <4>; 4267 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 4268 reg = <0x17c29000 0x1000>; 4269 status = "disabled"; 4270 }; 4271 4272 frame@17c2b000 { 4273 frame-number = <5>; 4274 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 4275 reg = <0x17c2b000 0x1000>; 4276 status = "disabled"; 4277 }; 4278 4279 frame@17c2d000 { 4280 frame-number = <6>; 4281 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 4282 reg = <0x17c2d000 0x1000>; 4283 status = "disabled"; 4284 }; 4285 }; 4286 4287 apps_rsc: rsc@18200000 { 4288 compatible = "qcom,rpmh-rsc"; 4289 reg = <0x0 0x18200000 0x0 0x10000>, 4290 <0x0 0x18210000 0x0 0x10000>, 4291 <0x0 0x18220000 0x0 0x10000>; 4292 reg-names = "drv-0", "drv-1", "drv-2"; 4293 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 4294 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 4295 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 4296 qcom,tcs-offset = <0xd00>; 4297 qcom,drv-id = <2>; 4298 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 4299 <WAKE_TCS 3>, <CONTROL_TCS 1>; 4300 label = "apps_rsc"; 4301 power-domains = <&CLUSTER_PD>; 4302 4303 apps_bcm_voter: bcm-voter { 4304 compatible = "qcom,bcm-voter"; 4305 }; 4306 4307 rpmhcc: clock-controller { 4308 compatible = "qcom,sc8280xp-rpmh-clk"; 4309 #clock-cells = <1>; 4310 clock-names = "xo"; 4311 clocks = <&xo_board_clk>; 4312 }; 4313 4314 rpmhpd: power-controller { 4315 compatible = "qcom,sc8280xp-rpmhpd"; 4316 #power-domain-cells = <1>; 4317 operating-points-v2 = <&rpmhpd_opp_table>; 4318 4319 rpmhpd_opp_table: opp-table { 4320 compatible = "operating-points-v2"; 4321 4322 rpmhpd_opp_ret: opp1 { 4323 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 4324 }; 4325 4326 rpmhpd_opp_min_svs: opp2 { 4327 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 4328 }; 4329 4330 rpmhpd_opp_low_svs: opp3 { 4331 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4332 }; 4333 4334 rpmhpd_opp_svs: opp4 { 4335 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4336 }; 4337 4338 rpmhpd_opp_svs_l1: opp5 { 4339 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4340 }; 4341 4342 rpmhpd_opp_nom: opp6 { 4343 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4344 }; 4345 4346 rpmhpd_opp_nom_l1: opp7 { 4347 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4348 }; 4349 4350 rpmhpd_opp_nom_l2: opp8 { 4351 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 4352 }; 4353 4354 rpmhpd_opp_turbo: opp9 { 4355 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4356 }; 4357 4358 rpmhpd_opp_turbo_l1: opp10 { 4359 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4360 }; 4361 }; 4362 }; 4363 }; 4364 4365 epss_l3: interconnect@18590000 { 4366 compatible = "qcom,sc8280xp-epss-l3", "qcom,epss-l3"; 4367 reg = <0 0x18590000 0 0x1000>; 4368 4369 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 4370 clock-names = "xo", "alternate"; 4371 4372 #interconnect-cells = <1>; 4373 }; 4374 4375 cpufreq_hw: cpufreq@18591000 { 4376 compatible = "qcom,sc8280xp-cpufreq-epss", "qcom,cpufreq-epss"; 4377 reg = <0 0x18591000 0 0x1000>, 4378 <0 0x18592000 0 0x1000>; 4379 reg-names = "freq-domain0", "freq-domain1"; 4380 4381 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 4382 clock-names = "xo", "alternate"; 4383 4384 #freq-domain-cells = <1>; 4385 #clock-cells = <1>; 4386 }; 4387 4388 remoteproc_nsp0: remoteproc@1b300000 { 4389 compatible = "qcom,sc8280xp-nsp0-pas"; 4390 reg = <0 0x1b300000 0 0x100>; 4391 4392 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, 4393 <&smp2p_nsp0_in 0 IRQ_TYPE_EDGE_RISING>, 4394 <&smp2p_nsp0_in 1 IRQ_TYPE_EDGE_RISING>, 4395 <&smp2p_nsp0_in 2 IRQ_TYPE_EDGE_RISING>, 4396 <&smp2p_nsp0_in 3 IRQ_TYPE_EDGE_RISING>; 4397 interrupt-names = "wdog", "fatal", "ready", 4398 "handover", "stop-ack"; 4399 4400 clocks = <&rpmhcc RPMH_CXO_CLK>; 4401 clock-names = "xo"; 4402 4403 power-domains = <&rpmhpd SC8280XP_NSP>; 4404 power-domain-names = "nsp"; 4405 4406 memory-region = <&pil_nsp0_mem>; 4407 4408 qcom,smem-states = <&smp2p_nsp0_out 0>; 4409 qcom,smem-state-names = "stop"; 4410 4411 interconnects = <&nspa_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>; 4412 4413 status = "disabled"; 4414 4415 glink-edge { 4416 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 4417 IPCC_MPROC_SIGNAL_GLINK_QMP 4418 IRQ_TYPE_EDGE_RISING>; 4419 mboxes = <&ipcc IPCC_CLIENT_CDSP 4420 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4421 4422 label = "nsp0"; 4423 qcom,remote-pid = <5>; 4424 4425 fastrpc { 4426 compatible = "qcom,fastrpc"; 4427 qcom,glink-channels = "fastrpcglink-apps-dsp"; 4428 label = "cdsp"; 4429 #address-cells = <1>; 4430 #size-cells = <0>; 4431 4432 compute-cb@1 { 4433 compatible = "qcom,fastrpc-compute-cb"; 4434 reg = <1>; 4435 iommus = <&apps_smmu 0x3181 0x0420>; 4436 }; 4437 4438 compute-cb@2 { 4439 compatible = "qcom,fastrpc-compute-cb"; 4440 reg = <2>; 4441 iommus = <&apps_smmu 0x3182 0x0420>; 4442 }; 4443 4444 compute-cb@3 { 4445 compatible = "qcom,fastrpc-compute-cb"; 4446 reg = <3>; 4447 iommus = <&apps_smmu 0x3183 0x0420>; 4448 }; 4449 4450 compute-cb@4 { 4451 compatible = "qcom,fastrpc-compute-cb"; 4452 reg = <4>; 4453 iommus = <&apps_smmu 0x3184 0x0420>; 4454 }; 4455 4456 compute-cb@5 { 4457 compatible = "qcom,fastrpc-compute-cb"; 4458 reg = <5>; 4459 iommus = <&apps_smmu 0x3185 0x0420>; 4460 }; 4461 4462 compute-cb@6 { 4463 compatible = "qcom,fastrpc-compute-cb"; 4464 reg = <6>; 4465 iommus = <&apps_smmu 0x3186 0x0420>; 4466 }; 4467 4468 compute-cb@7 { 4469 compatible = "qcom,fastrpc-compute-cb"; 4470 reg = <7>; 4471 iommus = <&apps_smmu 0x3187 0x0420>; 4472 }; 4473 4474 compute-cb@8 { 4475 compatible = "qcom,fastrpc-compute-cb"; 4476 reg = <8>; 4477 iommus = <&apps_smmu 0x3188 0x0420>; 4478 }; 4479 4480 compute-cb@9 { 4481 compatible = "qcom,fastrpc-compute-cb"; 4482 reg = <9>; 4483 iommus = <&apps_smmu 0x318b 0x0420>; 4484 }; 4485 4486 compute-cb@10 { 4487 compatible = "qcom,fastrpc-compute-cb"; 4488 reg = <10>; 4489 iommus = <&apps_smmu 0x318b 0x0420>; 4490 }; 4491 4492 compute-cb@11 { 4493 compatible = "qcom,fastrpc-compute-cb"; 4494 reg = <11>; 4495 iommus = <&apps_smmu 0x318c 0x0420>; 4496 }; 4497 4498 compute-cb@12 { 4499 compatible = "qcom,fastrpc-compute-cb"; 4500 reg = <12>; 4501 iommus = <&apps_smmu 0x318d 0x0420>; 4502 }; 4503 4504 compute-cb@13 { 4505 compatible = "qcom,fastrpc-compute-cb"; 4506 reg = <13>; 4507 iommus = <&apps_smmu 0x318e 0x0420>; 4508 }; 4509 4510 compute-cb@14 { 4511 compatible = "qcom,fastrpc-compute-cb"; 4512 reg = <14>; 4513 iommus = <&apps_smmu 0x318f 0x0420>; 4514 }; 4515 }; 4516 }; 4517 }; 4518 4519 remoteproc_nsp1: remoteproc@21300000 { 4520 compatible = "qcom,sc8280xp-nsp1-pas"; 4521 reg = <0 0x21300000 0 0x100>; 4522 4523 interrupts-extended = <&intc GIC_SPI 887 IRQ_TYPE_LEVEL_HIGH>, 4524 <&smp2p_nsp1_in 0 IRQ_TYPE_EDGE_RISING>, 4525 <&smp2p_nsp1_in 1 IRQ_TYPE_EDGE_RISING>, 4526 <&smp2p_nsp1_in 2 IRQ_TYPE_EDGE_RISING>, 4527 <&smp2p_nsp1_in 3 IRQ_TYPE_EDGE_RISING>; 4528 interrupt-names = "wdog", "fatal", "ready", 4529 "handover", "stop-ack"; 4530 4531 clocks = <&rpmhcc RPMH_CXO_CLK>; 4532 clock-names = "xo"; 4533 4534 power-domains = <&rpmhpd SC8280XP_NSP>; 4535 power-domain-names = "nsp"; 4536 4537 memory-region = <&pil_nsp1_mem>; 4538 4539 qcom,smem-states = <&smp2p_nsp1_out 0>; 4540 qcom,smem-state-names = "stop"; 4541 4542 interconnects = <&nspb_noc MASTER_CDSP_PROC_B 0 &mc_virt SLAVE_EBI1 0>; 4543 4544 status = "disabled"; 4545 4546 glink-edge { 4547 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1 4548 IPCC_MPROC_SIGNAL_GLINK_QMP 4549 IRQ_TYPE_EDGE_RISING>; 4550 mboxes = <&ipcc IPCC_CLIENT_NSP1 4551 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4552 4553 label = "nsp1"; 4554 qcom,remote-pid = <12>; 4555 }; 4556 }; 4557 4558 mdss1: display-subsystem@22000000 { 4559 compatible = "qcom,sc8280xp-mdss"; 4560 reg = <0 0x22000000 0 0x1000>; 4561 reg-names = "mdss"; 4562 4563 clocks = <&gcc GCC_DISP_AHB_CLK>, 4564 <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 4565 <&dispcc1 DISP_CC_MDSS_MDP_CLK>; 4566 clock-names = "iface", 4567 "ahb", 4568 "core"; 4569 interconnects = <&mmss_noc MASTER_MDP_CORE1_0 0 &mc_virt SLAVE_EBI1 0>, 4570 <&mmss_noc MASTER_MDP_CORE1_1 0 &mc_virt SLAVE_EBI1 0>; 4571 interconnect-names = "mdp0-mem", "mdp1-mem"; 4572 interrupts = <GIC_SPI 865 IRQ_TYPE_LEVEL_HIGH>; 4573 4574 iommus = <&apps_smmu 0x1800 0x402>; 4575 power-domains = <&dispcc1 MDSS_GDSC>; 4576 resets = <&dispcc1 DISP_CC_MDSS_CORE_BCR>; 4577 4578 interrupt-controller; 4579 #interrupt-cells = <1>; 4580 #address-cells = <2>; 4581 #size-cells = <2>; 4582 ranges; 4583 4584 status = "disabled"; 4585 4586 mdss1_mdp: display-controller@22001000 { 4587 compatible = "qcom,sc8280xp-dpu"; 4588 reg = <0 0x22001000 0 0x8f000>, 4589 <0 0x220b0000 0 0x2008>; 4590 reg-names = "mdp", "vbif"; 4591 4592 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 4593 <&gcc GCC_DISP_SF_AXI_CLK>, 4594 <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 4595 <&dispcc1 DISP_CC_MDSS_MDP_LUT_CLK>, 4596 <&dispcc1 DISP_CC_MDSS_MDP_CLK>, 4597 <&dispcc1 DISP_CC_MDSS_VSYNC_CLK>; 4598 clock-names = "bus", 4599 "nrt_bus", 4600 "iface", 4601 "lut", 4602 "core", 4603 "vsync"; 4604 interrupt-parent = <&mdss1>; 4605 interrupts = <0>; 4606 power-domains = <&rpmhpd SC8280XP_MMCX>; 4607 4608 assigned-clocks = <&dispcc1 DISP_CC_MDSS_VSYNC_CLK>; 4609 assigned-clock-rates = <19200000>; 4610 operating-points-v2 = <&mdss1_mdp_opp_table>; 4611 4612 ports { 4613 #address-cells = <1>; 4614 #size-cells = <0>; 4615 4616 port@0 { 4617 reg = <0>; 4618 mdss1_intf0_out: endpoint { 4619 remote-endpoint = <&mdss1_dp0_in>; 4620 }; 4621 }; 4622 4623 port@4 { 4624 reg = <4>; 4625 mdss1_intf4_out: endpoint { 4626 remote-endpoint = <&mdss1_dp1_in>; 4627 }; 4628 }; 4629 4630 port@5 { 4631 reg = <5>; 4632 mdss1_intf5_out: endpoint { 4633 remote-endpoint = <&mdss1_dp3_in>; 4634 }; 4635 }; 4636 4637 port@6 { 4638 reg = <6>; 4639 mdss1_intf6_out: endpoint { 4640 remote-endpoint = <&mdss1_dp2_in>; 4641 }; 4642 }; 4643 }; 4644 4645 mdss1_mdp_opp_table: opp-table { 4646 compatible = "operating-points-v2"; 4647 4648 opp-200000000 { 4649 opp-hz = /bits/ 64 <200000000>; 4650 required-opps = <&rpmhpd_opp_low_svs>; 4651 }; 4652 4653 opp-300000000 { 4654 opp-hz = /bits/ 64 <300000000>; 4655 required-opps = <&rpmhpd_opp_svs>; 4656 }; 4657 4658 opp-375000000 { 4659 opp-hz = /bits/ 64 <375000000>; 4660 required-opps = <&rpmhpd_opp_svs_l1>; 4661 }; 4662 4663 opp-500000000 { 4664 opp-hz = /bits/ 64 <500000000>; 4665 required-opps = <&rpmhpd_opp_nom>; 4666 }; 4667 opp-600000000 { 4668 opp-hz = /bits/ 64 <600000000>; 4669 required-opps = <&rpmhpd_opp_turbo_l1>; 4670 }; 4671 }; 4672 }; 4673 4674 mdss1_dp0: displayport-controller@22090000 { 4675 compatible = "qcom,sc8280xp-dp"; 4676 reg = <0 0x22090000 0 0x200>, 4677 <0 0x22090200 0 0x200>, 4678 <0 0x22090400 0 0x600>, 4679 <0 0x22091000 0 0x400>, 4680 <0 0x22091400 0 0x400>; 4681 4682 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 4683 <&dispcc1 DISP_CC_MDSS_DPTX0_AUX_CLK>, 4684 <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_CLK>, 4685 <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 4686 <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; 4687 clock-names = "core_iface", "core_aux", 4688 "ctrl_link", 4689 "ctrl_link_iface", "stream_pixel"; 4690 interrupt-parent = <&mdss1>; 4691 interrupts = <12>; 4692 phys = <&mdss1_dp0_phy>; 4693 phy-names = "dp"; 4694 power-domains = <&rpmhpd SC8280XP_MMCX>; 4695 4696 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 4697 <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; 4698 assigned-clock-parents = <&mdss1_dp0_phy 0>, <&mdss1_dp0_phy 1>; 4699 operating-points-v2 = <&mdss1_dp0_opp_table>; 4700 4701 #sound-dai-cells = <0>; 4702 4703 status = "disabled"; 4704 4705 ports { 4706 #address-cells = <1>; 4707 #size-cells = <0>; 4708 4709 port@0 { 4710 reg = <0>; 4711 mdss1_dp0_in: endpoint { 4712 remote-endpoint = <&mdss1_intf0_out>; 4713 }; 4714 }; 4715 4716 port@1 { 4717 reg = <1>; 4718 }; 4719 }; 4720 4721 mdss1_dp0_opp_table: opp-table { 4722 compatible = "operating-points-v2"; 4723 4724 opp-160000000 { 4725 opp-hz = /bits/ 64 <160000000>; 4726 required-opps = <&rpmhpd_opp_low_svs>; 4727 }; 4728 4729 opp-270000000 { 4730 opp-hz = /bits/ 64 <270000000>; 4731 required-opps = <&rpmhpd_opp_svs>; 4732 }; 4733 4734 opp-540000000 { 4735 opp-hz = /bits/ 64 <540000000>; 4736 required-opps = <&rpmhpd_opp_svs_l1>; 4737 }; 4738 4739 opp-810000000 { 4740 opp-hz = /bits/ 64 <810000000>; 4741 required-opps = <&rpmhpd_opp_nom>; 4742 }; 4743 }; 4744 }; 4745 4746 mdss1_dp1: displayport-controller@22098000 { 4747 compatible = "qcom,sc8280xp-dp"; 4748 reg = <0 0x22098000 0 0x200>, 4749 <0 0x22098200 0 0x200>, 4750 <0 0x22098400 0 0x600>, 4751 <0 0x22099000 0 0x400>, 4752 <0 0x22099400 0 0x400>; 4753 4754 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 4755 <&dispcc1 DISP_CC_MDSS_DPTX1_AUX_CLK>, 4756 <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_CLK>, 4757 <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, 4758 <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>; 4759 clock-names = "core_iface", "core_aux", 4760 "ctrl_link", 4761 "ctrl_link_iface", "stream_pixel"; 4762 interrupt-parent = <&mdss1>; 4763 interrupts = <13>; 4764 phys = <&mdss1_dp1_phy>; 4765 phy-names = "dp"; 4766 power-domains = <&rpmhpd SC8280XP_MMCX>; 4767 4768 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, 4769 <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>; 4770 assigned-clock-parents = <&mdss1_dp1_phy 0>, <&mdss1_dp1_phy 1>; 4771 operating-points-v2 = <&mdss1_dp1_opp_table>; 4772 4773 #sound-dai-cells = <0>; 4774 4775 status = "disabled"; 4776 4777 ports { 4778 #address-cells = <1>; 4779 #size-cells = <0>; 4780 4781 port@0 { 4782 reg = <0>; 4783 mdss1_dp1_in: endpoint { 4784 remote-endpoint = <&mdss1_intf4_out>; 4785 }; 4786 }; 4787 4788 port@1 { 4789 reg = <1>; 4790 }; 4791 }; 4792 4793 mdss1_dp1_opp_table: opp-table { 4794 compatible = "operating-points-v2"; 4795 4796 opp-160000000 { 4797 opp-hz = /bits/ 64 <160000000>; 4798 required-opps = <&rpmhpd_opp_low_svs>; 4799 }; 4800 4801 opp-270000000 { 4802 opp-hz = /bits/ 64 <270000000>; 4803 required-opps = <&rpmhpd_opp_svs>; 4804 }; 4805 4806 opp-540000000 { 4807 opp-hz = /bits/ 64 <540000000>; 4808 required-opps = <&rpmhpd_opp_svs_l1>; 4809 }; 4810 4811 opp-810000000 { 4812 opp-hz = /bits/ 64 <810000000>; 4813 required-opps = <&rpmhpd_opp_nom>; 4814 }; 4815 }; 4816 }; 4817 4818 mdss1_dp2: displayport-controller@2209a000 { 4819 compatible = "qcom,sc8280xp-dp"; 4820 reg = <0 0x2209a000 0 0x200>, 4821 <0 0x2209a200 0 0x200>, 4822 <0 0x2209a400 0 0x600>, 4823 <0 0x2209b000 0 0x400>, 4824 <0 0x2209b400 0 0x400>; 4825 4826 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 4827 <&dispcc1 DISP_CC_MDSS_DPTX2_AUX_CLK>, 4828 <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_CLK>, 4829 <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>, 4830 <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>; 4831 clock-names = "core_iface", "core_aux", 4832 "ctrl_link", 4833 "ctrl_link_iface", "stream_pixel"; 4834 interrupt-parent = <&mdss1>; 4835 interrupts = <14>; 4836 phys = <&mdss1_dp2_phy>; 4837 phy-names = "dp"; 4838 power-domains = <&rpmhpd SC8280XP_MMCX>; 4839 4840 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>, 4841 <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>; 4842 assigned-clock-parents = <&mdss1_dp2_phy 0>, <&mdss1_dp2_phy 1>; 4843 operating-points-v2 = <&mdss1_dp2_opp_table>; 4844 4845 #sound-dai-cells = <0>; 4846 4847 status = "disabled"; 4848 4849 ports { 4850 #address-cells = <1>; 4851 #size-cells = <0>; 4852 4853 port@0 { 4854 reg = <0>; 4855 mdss1_dp2_in: endpoint { 4856 remote-endpoint = <&mdss1_intf6_out>; 4857 }; 4858 }; 4859 4860 port@1 { 4861 reg = <1>; 4862 }; 4863 }; 4864 4865 mdss1_dp2_opp_table: opp-table { 4866 compatible = "operating-points-v2"; 4867 4868 opp-160000000 { 4869 opp-hz = /bits/ 64 <160000000>; 4870 required-opps = <&rpmhpd_opp_low_svs>; 4871 }; 4872 4873 opp-270000000 { 4874 opp-hz = /bits/ 64 <270000000>; 4875 required-opps = <&rpmhpd_opp_svs>; 4876 }; 4877 4878 opp-540000000 { 4879 opp-hz = /bits/ 64 <540000000>; 4880 required-opps = <&rpmhpd_opp_svs_l1>; 4881 }; 4882 4883 opp-810000000 { 4884 opp-hz = /bits/ 64 <810000000>; 4885 required-opps = <&rpmhpd_opp_nom>; 4886 }; 4887 }; 4888 }; 4889 4890 mdss1_dp3: displayport-controller@220a0000 { 4891 compatible = "qcom,sc8280xp-dp"; 4892 reg = <0 0x220a0000 0 0x200>, 4893 <0 0x220a0200 0 0x200>, 4894 <0 0x220a0400 0 0x600>, 4895 <0 0x220a1000 0 0x400>, 4896 <0 0x220a1400 0 0x400>; 4897 4898 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 4899 <&dispcc1 DISP_CC_MDSS_DPTX3_AUX_CLK>, 4900 <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_CLK>, 4901 <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>, 4902 <&dispcc1 DISP_CC_MDSS_DPTX3_PIXEL0_CLK>; 4903 clock-names = "core_iface", "core_aux", 4904 "ctrl_link", 4905 "ctrl_link_iface", "stream_pixel"; 4906 interrupt-parent = <&mdss1>; 4907 interrupts = <15>; 4908 phys = <&mdss1_dp3_phy>; 4909 phy-names = "dp"; 4910 power-domains = <&rpmhpd SC8280XP_MMCX>; 4911 4912 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>, 4913 <&dispcc1 DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>; 4914 assigned-clock-parents = <&mdss1_dp3_phy 0>, <&mdss1_dp3_phy 1>; 4915 operating-points-v2 = <&mdss1_dp3_opp_table>; 4916 4917 #sound-dai-cells = <0>; 4918 4919 status = "disabled"; 4920 4921 ports { 4922 #address-cells = <1>; 4923 #size-cells = <0>; 4924 4925 port@0 { 4926 reg = <0>; 4927 mdss1_dp3_in: endpoint { 4928 remote-endpoint = <&mdss1_intf5_out>; 4929 }; 4930 }; 4931 4932 port@1 { 4933 reg = <1>; 4934 }; 4935 }; 4936 4937 mdss1_dp3_opp_table: opp-table { 4938 compatible = "operating-points-v2"; 4939 4940 opp-160000000 { 4941 opp-hz = /bits/ 64 <160000000>; 4942 required-opps = <&rpmhpd_opp_low_svs>; 4943 }; 4944 4945 opp-270000000 { 4946 opp-hz = /bits/ 64 <270000000>; 4947 required-opps = <&rpmhpd_opp_svs>; 4948 }; 4949 4950 opp-540000000 { 4951 opp-hz = /bits/ 64 <540000000>; 4952 required-opps = <&rpmhpd_opp_svs_l1>; 4953 }; 4954 4955 opp-810000000 { 4956 opp-hz = /bits/ 64 <810000000>; 4957 required-opps = <&rpmhpd_opp_nom>; 4958 }; 4959 }; 4960 }; 4961 }; 4962 4963 mdss1_dp2_phy: phy@220c2a00 { 4964 compatible = "qcom,sc8280xp-dp-phy"; 4965 reg = <0 0x220c2a00 0 0x19c>, 4966 <0 0x220c2200 0 0xec>, 4967 <0 0x220c2600 0 0xec>, 4968 <0 0x220c2000 0 0x1c8>; 4969 4970 clocks = <&dispcc1 DISP_CC_MDSS_DPTX2_AUX_CLK>, 4971 <&dispcc1 DISP_CC_MDSS_AHB_CLK>; 4972 clock-names = "aux", "cfg_ahb"; 4973 power-domains = <&rpmhpd SC8280XP_MX>; 4974 4975 #clock-cells = <1>; 4976 #phy-cells = <0>; 4977 4978 status = "disabled"; 4979 }; 4980 4981 mdss1_dp3_phy: phy@220c5a00 { 4982 compatible = "qcom,sc8280xp-dp-phy"; 4983 reg = <0 0x220c5a00 0 0x19c>, 4984 <0 0x220c5200 0 0xec>, 4985 <0 0x220c5600 0 0xec>, 4986 <0 0x220c5000 0 0x1c8>; 4987 4988 clocks = <&dispcc1 DISP_CC_MDSS_DPTX3_AUX_CLK>, 4989 <&dispcc1 DISP_CC_MDSS_AHB_CLK>; 4990 clock-names = "aux", "cfg_ahb"; 4991 power-domains = <&rpmhpd SC8280XP_MX>; 4992 4993 #clock-cells = <1>; 4994 #phy-cells = <0>; 4995 4996 status = "disabled"; 4997 }; 4998 4999 dispcc1: clock-controller@22100000 { 5000 compatible = "qcom,sc8280xp-dispcc1"; 5001 reg = <0 0x22100000 0 0x20000>; 5002 5003 clocks = <&gcc GCC_DISP_AHB_CLK>, 5004 <&rpmhcc RPMH_CXO_CLK>, 5005 <0>, 5006 <&mdss1_dp0_phy 0>, 5007 <&mdss1_dp0_phy 1>, 5008 <&mdss1_dp1_phy 0>, 5009 <&mdss1_dp1_phy 1>, 5010 <&mdss1_dp2_phy 0>, 5011 <&mdss1_dp2_phy 1>, 5012 <&mdss1_dp3_phy 0>, 5013 <&mdss1_dp3_phy 1>, 5014 <0>, 5015 <0>, 5016 <0>, 5017 <0>; 5018 power-domains = <&rpmhpd SC8280XP_MMCX>; 5019 5020 #clock-cells = <1>; 5021 #power-domain-cells = <1>; 5022 #reset-cells = <1>; 5023 5024 status = "disabled"; 5025 }; 5026 5027 ethernet1: ethernet@23000000 { 5028 compatible = "qcom,sc8280xp-ethqos"; 5029 reg = <0x0 0x23000000 0x0 0x10000>, 5030 <0x0 0x23016000 0x0 0x100>; 5031 reg-names = "stmmaceth", "rgmii"; 5032 5033 clocks = <&gcc GCC_EMAC1_AXI_CLK>, 5034 <&gcc GCC_EMAC1_SLV_AHB_CLK>, 5035 <&gcc GCC_EMAC1_PTP_CLK>, 5036 <&gcc GCC_EMAC1_RGMII_CLK>; 5037 clock-names = "stmmaceth", 5038 "pclk", 5039 "ptp_ref", 5040 "rgmii"; 5041 5042 interrupts = <GIC_SPI 929 IRQ_TYPE_LEVEL_HIGH>, 5043 <GIC_SPI 919 IRQ_TYPE_LEVEL_HIGH>; 5044 interrupt-names = "macirq", "eth_lpi"; 5045 5046 iommus = <&apps_smmu 0x40 0xf>; 5047 power-domains = <&gcc EMAC_1_GDSC>; 5048 5049 snps,tso; 5050 snps,pbl = <32>; 5051 rx-fifo-depth = <4096>; 5052 tx-fifo-depth = <4096>; 5053 5054 status = "disabled"; 5055 }; 5056 }; 5057 5058 sound: sound { 5059 }; 5060 5061 thermal-zones { 5062 cpu0-thermal { 5063 polling-delay-passive = <250>; 5064 polling-delay = <1000>; 5065 5066 thermal-sensors = <&tsens0 1>; 5067 5068 trips { 5069 cpu-crit { 5070 temperature = <110000>; 5071 hysteresis = <1000>; 5072 type = "critical"; 5073 }; 5074 }; 5075 }; 5076 5077 cpu1-thermal { 5078 polling-delay-passive = <250>; 5079 polling-delay = <1000>; 5080 5081 thermal-sensors = <&tsens0 2>; 5082 5083 trips { 5084 cpu-crit { 5085 temperature = <110000>; 5086 hysteresis = <1000>; 5087 type = "critical"; 5088 }; 5089 }; 5090 }; 5091 5092 cpu2-thermal { 5093 polling-delay-passive = <250>; 5094 polling-delay = <1000>; 5095 5096 thermal-sensors = <&tsens0 3>; 5097 5098 trips { 5099 cpu-crit { 5100 temperature = <110000>; 5101 hysteresis = <1000>; 5102 type = "critical"; 5103 }; 5104 }; 5105 }; 5106 5107 cpu3-thermal { 5108 polling-delay-passive = <250>; 5109 polling-delay = <1000>; 5110 5111 thermal-sensors = <&tsens0 4>; 5112 5113 trips { 5114 cpu-crit { 5115 temperature = <110000>; 5116 hysteresis = <1000>; 5117 type = "critical"; 5118 }; 5119 }; 5120 }; 5121 5122 cpu4-thermal { 5123 polling-delay-passive = <250>; 5124 polling-delay = <1000>; 5125 5126 thermal-sensors = <&tsens0 5>; 5127 5128 trips { 5129 cpu-crit { 5130 temperature = <110000>; 5131 hysteresis = <1000>; 5132 type = "critical"; 5133 }; 5134 }; 5135 }; 5136 5137 cpu5-thermal { 5138 polling-delay-passive = <250>; 5139 polling-delay = <1000>; 5140 5141 thermal-sensors = <&tsens0 6>; 5142 5143 trips { 5144 cpu-crit { 5145 temperature = <110000>; 5146 hysteresis = <1000>; 5147 type = "critical"; 5148 }; 5149 }; 5150 }; 5151 5152 cpu6-thermal { 5153 polling-delay-passive = <250>; 5154 polling-delay = <1000>; 5155 5156 thermal-sensors = <&tsens0 7>; 5157 5158 trips { 5159 cpu-crit { 5160 temperature = <110000>; 5161 hysteresis = <1000>; 5162 type = "critical"; 5163 }; 5164 }; 5165 }; 5166 5167 cpu7-thermal { 5168 polling-delay-passive = <250>; 5169 polling-delay = <1000>; 5170 5171 thermal-sensors = <&tsens0 8>; 5172 5173 trips { 5174 cpu-crit { 5175 temperature = <110000>; 5176 hysteresis = <1000>; 5177 type = "critical"; 5178 }; 5179 }; 5180 }; 5181 5182 cluster0-thermal { 5183 polling-delay-passive = <250>; 5184 polling-delay = <1000>; 5185 5186 thermal-sensors = <&tsens0 9>; 5187 5188 trips { 5189 cpu-crit { 5190 temperature = <110000>; 5191 hysteresis = <1000>; 5192 type = "critical"; 5193 }; 5194 }; 5195 }; 5196 5197 mem-thermal { 5198 polling-delay-passive = <250>; 5199 polling-delay = <1000>; 5200 5201 thermal-sensors = <&tsens1 15>; 5202 5203 trips { 5204 trip-point0 { 5205 temperature = <90000>; 5206 hysteresis = <2000>; 5207 type = "hot"; 5208 }; 5209 }; 5210 }; 5211 }; 5212 5213 timer { 5214 compatible = "arm,armv8-timer"; 5215 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5216 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5217 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5218 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 5219 }; 5220}; 5221