1// SPDX-License-Identifier: BSD-3-Clause
2/*
3 * Copyright (c) 2021, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2022, Linaro Limited
5 */
6
7#include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
8#include <dt-bindings/clock/qcom,rpmh.h>
9#include <dt-bindings/interconnect/qcom,sc8280xp.h>
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11#include <dt-bindings/mailbox/qcom-ipcc.h>
12#include <dt-bindings/power/qcom-rpmpd.h>
13#include <dt-bindings/soc/qcom,rpmh-rsc.h>
14#include <dt-bindings/thermal/thermal.h>
15
16/ {
17	interrupt-parent = <&intc>;
18
19	#address-cells = <2>;
20	#size-cells = <2>;
21
22	clocks {
23		xo_board_clk: xo-board-clk {
24			compatible = "fixed-clock";
25			#clock-cells = <0>;
26		};
27
28		sleep_clk: sleep-clk {
29			compatible = "fixed-clock";
30			#clock-cells = <0>;
31			clock-frequency = <32764>;
32		};
33	};
34
35	cpu0_opp_table: cpu0-opp-table {
36		compatible = "operating-points-v2";
37		opp-shared;
38
39		opp-300000000 {
40			opp-hz = /bits/ 64 <300000000>;
41		};
42		opp-403200000 {
43			opp-hz = /bits/ 64 <403200000>;
44		};
45		opp-499200000 {
46			opp-hz = /bits/ 64 <499200000>;
47		};
48		opp-595200000 {
49			opp-hz = /bits/ 64 <595200000>;
50		};
51		opp-691200000 {
52			opp-hz = /bits/ 64 <691200000>;
53		};
54		opp-806400000 {
55			opp-hz = /bits/ 64 <806400000>;
56		};
57		opp-902400000 {
58			opp-hz = /bits/ 64 <902400000>;
59		};
60		opp-1017600000 {
61			opp-hz = /bits/ 64 <1017600000>;
62		};
63		opp-1113600000 {
64			opp-hz = /bits/ 64 <1113600000>;
65		};
66		opp-1209600000 {
67			opp-hz = /bits/ 64 <1209600000>;
68		};
69		opp-1324800000 {
70			opp-hz = /bits/ 64 <1324800000>;
71		};
72		opp-1440000000 {
73			opp-hz = /bits/ 64 <1440000000>;
74		};
75		opp-1555200000 {
76			opp-hz = /bits/ 64 <1555200000>;
77		};
78		opp-1670400000 {
79			opp-hz = /bits/ 64 <1670400000>;
80		};
81		opp-1785600000 {
82			opp-hz = /bits/ 64 <1785600000>;
83		};
84		opp-1881600000 {
85			opp-hz = /bits/ 64 <1881600000>;
86		};
87		opp-1996800000 {
88			opp-hz = /bits/ 64 <1996800000>;
89		};
90		opp-2112000000 {
91			opp-hz = /bits/ 64 <2112000000>;
92		};
93		opp-2227200000 {
94			opp-hz = /bits/ 64 <2227200000>;
95		};
96		opp-2342400000 {
97			opp-hz = /bits/ 64 <2342400000>;
98		};
99		opp-2438400000 {
100			opp-hz = /bits/ 64 <2438400000>;
101		};
102	};
103
104	cpu4_opp_table: cpu4-opp-table {
105		compatible = "operating-points-v2";
106		opp-shared;
107
108		opp-825600000 {
109			opp-hz = /bits/ 64 <825600000>;
110		};
111		opp-940800000 {
112			opp-hz = /bits/ 64 <940800000>;
113		};
114		opp-1056000000 {
115			opp-hz = /bits/ 64 <1056000000>;
116		};
117		opp-1171200000 {
118			opp-hz = /bits/ 64 <1171200000>;
119		};
120		opp-1286400000 {
121			opp-hz = /bits/ 64 <1286400000>;
122		};
123		opp-1401600000 {
124			opp-hz = /bits/ 64 <1401600000>;
125		};
126		opp-1516800000 {
127			opp-hz = /bits/ 64 <1516800000>;
128		};
129		opp-1632000000 {
130			opp-hz = /bits/ 64 <1632000000>;
131		};
132		opp-1747200000 {
133			opp-hz = /bits/ 64 <1747200000>;
134		};
135		opp-1862400000 {
136			opp-hz = /bits/ 64 <1862400000>;
137		};
138		opp-1977600000 {
139			opp-hz = /bits/ 64 <1977600000>;
140		};
141		opp-2073600000 {
142			opp-hz = /bits/ 64 <2073600000>;
143		};
144		opp-2169600000 {
145			opp-hz = /bits/ 64 <2169600000>;
146		};
147		opp-2284800000 {
148			opp-hz = /bits/ 64 <2284800000>;
149		};
150		opp-2400000000 {
151			opp-hz = /bits/ 64 <2400000000>;
152		};
153		opp-2496000000 {
154			opp-hz = /bits/ 64 <2496000000>;
155		};
156		opp-2592000000 {
157			opp-hz = /bits/ 64 <2592000000>;
158		};
159		opp-2688000000 {
160			opp-hz = /bits/ 64 <2688000000>;
161		};
162		opp-2803200000 {
163			opp-hz = /bits/ 64 <2803200000>;
164		};
165		opp-2899200000 {
166			opp-hz = /bits/ 64 <2899200000>;
167		};
168		opp-2995200000 {
169			opp-hz = /bits/ 64 <2995200000>;
170		};
171	};
172
173	cpus {
174		#address-cells = <2>;
175		#size-cells = <0>;
176
177		CPU0: cpu@0 {
178			device_type = "cpu";
179			compatible = "qcom,kryo";
180			reg = <0x0 0x0>;
181			enable-method = "psci";
182			capacity-dmips-mhz = <602>;
183			next-level-cache = <&L2_0>;
184			power-domains = <&CPU_PD0>;
185			power-domain-names = "psci";
186			qcom,freq-domain = <&cpufreq_hw 0>;
187			operating-points-v2 = <&cpu0_opp_table>;
188			#cooling-cells = <2>;
189			L2_0: l2-cache {
190				compatible = "cache";
191				next-level-cache = <&L3_0>;
192				L3_0: l3-cache {
193				      compatible = "cache";
194				};
195			};
196		};
197
198		CPU1: cpu@100 {
199			device_type = "cpu";
200			compatible = "qcom,kryo";
201			reg = <0x0 0x100>;
202			enable-method = "psci";
203			capacity-dmips-mhz = <602>;
204			next-level-cache = <&L2_100>;
205			power-domains = <&CPU_PD1>;
206			power-domain-names = "psci";
207			qcom,freq-domain = <&cpufreq_hw 0>;
208			operating-points-v2 = <&cpu0_opp_table>;
209			#cooling-cells = <2>;
210			L2_100: l2-cache {
211				compatible = "cache";
212				next-level-cache = <&L3_0>;
213			};
214		};
215
216		CPU2: cpu@200 {
217			device_type = "cpu";
218			compatible = "qcom,kryo";
219			reg = <0x0 0x200>;
220			enable-method = "psci";
221			capacity-dmips-mhz = <602>;
222			next-level-cache = <&L2_200>;
223			power-domains = <&CPU_PD2>;
224			power-domain-names = "psci";
225			qcom,freq-domain = <&cpufreq_hw 0>;
226			operating-points-v2 = <&cpu0_opp_table>;
227			#cooling-cells = <2>;
228			L2_200: l2-cache {
229				compatible = "cache";
230				next-level-cache = <&L3_0>;
231			};
232		};
233
234		CPU3: cpu@300 {
235			device_type = "cpu";
236			compatible = "qcom,kryo";
237			reg = <0x0 0x300>;
238			enable-method = "psci";
239			capacity-dmips-mhz = <602>;
240			next-level-cache = <&L2_300>;
241			power-domains = <&CPU_PD3>;
242			power-domain-names = "psci";
243			qcom,freq-domain = <&cpufreq_hw 0>;
244			operating-points-v2 = <&cpu0_opp_table>;
245			#cooling-cells = <2>;
246			L2_300: l2-cache {
247				compatible = "cache";
248				next-level-cache = <&L3_0>;
249			};
250		};
251
252		CPU4: cpu@400 {
253			device_type = "cpu";
254			compatible = "qcom,kryo";
255			reg = <0x0 0x400>;
256			enable-method = "psci";
257			capacity-dmips-mhz = <1024>;
258			next-level-cache = <&L2_400>;
259			power-domains = <&CPU_PD4>;
260			power-domain-names = "psci";
261			qcom,freq-domain = <&cpufreq_hw 1>;
262			operating-points-v2 = <&cpu4_opp_table>;
263			#cooling-cells = <2>;
264			L2_400: l2-cache {
265				compatible = "cache";
266				next-level-cache = <&L3_0>;
267			};
268		};
269
270		CPU5: cpu@500 {
271			device_type = "cpu";
272			compatible = "qcom,kryo";
273			reg = <0x0 0x500>;
274			enable-method = "psci";
275			capacity-dmips-mhz = <1024>;
276			next-level-cache = <&L2_500>;
277			power-domains = <&CPU_PD5>;
278			power-domain-names = "psci";
279			qcom,freq-domain = <&cpufreq_hw 1>;
280			operating-points-v2 = <&cpu4_opp_table>;
281			#cooling-cells = <2>;
282			L2_500: l2-cache {
283				compatible = "cache";
284				next-level-cache = <&L3_0>;
285			};
286		};
287
288		CPU6: cpu@600 {
289			device_type = "cpu";
290			compatible = "qcom,kryo";
291			reg = <0x0 0x600>;
292			enable-method = "psci";
293			capacity-dmips-mhz = <1024>;
294			next-level-cache = <&L2_600>;
295			power-domains = <&CPU_PD6>;
296			power-domain-names = "psci";
297			qcom,freq-domain = <&cpufreq_hw 1>;
298			operating-points-v2 = <&cpu4_opp_table>;
299			#cooling-cells = <2>;
300			L2_600: l2-cache {
301				compatible = "cache";
302				next-level-cache = <&L3_0>;
303			};
304		};
305
306		CPU7: cpu@700 {
307			device_type = "cpu";
308			compatible = "qcom,kryo";
309			reg = <0x0 0x700>;
310			enable-method = "psci";
311			capacity-dmips-mhz = <1024>;
312			next-level-cache = <&L2_700>;
313			power-domains = <&CPU_PD7>;
314			power-domain-names = "psci";
315			qcom,freq-domain = <&cpufreq_hw 1>;
316			operating-points-v2 = <&cpu4_opp_table>;
317			#cooling-cells = <2>;
318			L2_700: l2-cache {
319				compatible = "cache";
320				next-level-cache = <&L3_0>;
321			};
322		};
323
324		cpu-map {
325			cluster0 {
326				core0 {
327					cpu = <&CPU0>;
328				};
329
330				core1 {
331					cpu = <&CPU1>;
332				};
333
334				core2 {
335					cpu = <&CPU2>;
336				};
337
338				core3 {
339					cpu = <&CPU3>;
340				};
341
342				core4 {
343					cpu = <&CPU4>;
344				};
345
346				core5 {
347					cpu = <&CPU5>;
348				};
349
350				core6 {
351					cpu = <&CPU6>;
352				};
353
354				core7 {
355					cpu = <&CPU7>;
356				};
357			};
358		};
359
360		idle-states {
361			entry-method = "psci";
362
363			LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
364				compatible = "arm,idle-state";
365				idle-state-name = "little-rail-power-collapse";
366				arm,psci-suspend-param = <0x40000004>;
367				entry-latency-us = <355>;
368				exit-latency-us = <909>;
369				min-residency-us = <3934>;
370				local-timer-stop;
371			};
372
373			BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
374				compatible = "arm,idle-state";
375				idle-state-name = "big-rail-power-collapse";
376				arm,psci-suspend-param = <0x40000004>;
377				entry-latency-us = <241>;
378				exit-latency-us = <1461>;
379				min-residency-us = <4488>;
380				local-timer-stop;
381			};
382		};
383
384		domain-idle-states {
385			CLUSTER_SLEEP_0: cluster-sleep-0 {
386				compatible = "domain-idle-state";
387				idle-state-name = "cluster-power-collapse";
388				arm,psci-suspend-param = <0x4100c344>;
389				entry-latency-us = <3263>;
390				exit-latency-us = <6562>;
391				min-residency-us = <9987>;
392			};
393		};
394	};
395
396	firmware {
397		scm: scm {
398			compatible = "qcom,scm-sc8280xp", "qcom,scm";
399		};
400	};
401
402	aggre1_noc: interconnect-aggre1-noc {
403		compatible = "qcom,sc8280xp-aggre1-noc";
404		#interconnect-cells = <2>;
405		qcom,bcm-voters = <&apps_bcm_voter>;
406	};
407
408	aggre2_noc: interconnect-aggre2-noc {
409		compatible = "qcom,sc8280xp-aggre2-noc";
410		#interconnect-cells = <2>;
411		qcom,bcm-voters = <&apps_bcm_voter>;
412	};
413
414	clk_virt: interconnect-clk-virt {
415		compatible = "qcom,sc8280xp-clk-virt";
416		#interconnect-cells = <2>;
417		qcom,bcm-voters = <&apps_bcm_voter>;
418	};
419
420	config_noc: interconnect-config-noc {
421		compatible = "qcom,sc8280xp-config-noc";
422		#interconnect-cells = <2>;
423		qcom,bcm-voters = <&apps_bcm_voter>;
424	};
425
426	dc_noc: interconnect-dc-noc {
427		compatible = "qcom,sc8280xp-dc-noc";
428		#interconnect-cells = <2>;
429		qcom,bcm-voters = <&apps_bcm_voter>;
430	};
431
432	gem_noc: interconnect-gem-noc {
433		compatible = "qcom,sc8280xp-gem-noc";
434		#interconnect-cells = <2>;
435		qcom,bcm-voters = <&apps_bcm_voter>;
436	};
437
438	lpass_noc: interconnect-lpass-ag-noc {
439		compatible = "qcom,sc8280xp-lpass-ag-noc";
440		#interconnect-cells = <2>;
441		qcom,bcm-voters = <&apps_bcm_voter>;
442	};
443
444	mc_virt: interconnect-mc-virt {
445		compatible = "qcom,sc8280xp-mc-virt";
446		#interconnect-cells = <2>;
447		qcom,bcm-voters = <&apps_bcm_voter>;
448	};
449
450	mmss_noc: interconnect-mmss-noc {
451		compatible = "qcom,sc8280xp-mmss-noc";
452		#interconnect-cells = <2>;
453		qcom,bcm-voters = <&apps_bcm_voter>;
454	};
455
456	nspa_noc: interconnect-nspa-noc {
457		compatible = "qcom,sc8280xp-nspa-noc";
458		#interconnect-cells = <2>;
459		qcom,bcm-voters = <&apps_bcm_voter>;
460	};
461
462	nspb_noc: interconnect-nspb-noc {
463		compatible = "qcom,sc8280xp-nspb-noc";
464		#interconnect-cells = <2>;
465		qcom,bcm-voters = <&apps_bcm_voter>;
466	};
467
468	system_noc: interconnect-system-noc {
469		compatible = "qcom,sc8280xp-system-noc";
470		#interconnect-cells = <2>;
471		qcom,bcm-voters = <&apps_bcm_voter>;
472	};
473
474	memory@80000000 {
475		device_type = "memory";
476		/* We expect the bootloader to fill in the size */
477		reg = <0x0 0x80000000 0x0 0x0>;
478	};
479
480	pmu {
481		compatible = "arm,armv8-pmuv3";
482		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
483	};
484
485	psci {
486		compatible = "arm,psci-1.0";
487		method = "smc";
488
489		CPU_PD0: cpu0 {
490			#power-domain-cells = <0>;
491			power-domains = <&CLUSTER_PD>;
492			domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
493		};
494
495		CPU_PD1: cpu1 {
496			#power-domain-cells = <0>;
497			power-domains = <&CLUSTER_PD>;
498			domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
499		};
500
501		CPU_PD2: cpu2 {
502			#power-domain-cells = <0>;
503			power-domains = <&CLUSTER_PD>;
504			domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
505		};
506
507		CPU_PD3: cpu3 {
508			#power-domain-cells = <0>;
509			power-domains = <&CLUSTER_PD>;
510			domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
511		};
512
513		CPU_PD4: cpu4 {
514			#power-domain-cells = <0>;
515			power-domains = <&CLUSTER_PD>;
516			domain-idle-states = <&BIG_CPU_SLEEP_0>;
517		};
518
519		CPU_PD5: cpu5 {
520			#power-domain-cells = <0>;
521			power-domains = <&CLUSTER_PD>;
522			domain-idle-states = <&BIG_CPU_SLEEP_0>;
523		};
524
525		CPU_PD6: cpu6 {
526			#power-domain-cells = <0>;
527			power-domains = <&CLUSTER_PD>;
528			domain-idle-states = <&BIG_CPU_SLEEP_0>;
529		};
530
531		CPU_PD7: cpu7 {
532			#power-domain-cells = <0>;
533			power-domains = <&CLUSTER_PD>;
534			domain-idle-states = <&BIG_CPU_SLEEP_0>;
535		};
536
537		CLUSTER_PD: cpu-cluster0 {
538			#power-domain-cells = <0>;
539			domain-idle-states = <&CLUSTER_SLEEP_0>;
540		};
541	};
542
543	qup_opp_table_100mhz: qup-100mhz-opp-table {
544		compatible = "operating-points-v2";
545
546		opp-75000000 {
547			opp-hz = /bits/ 64 <75000000>;
548			required-opps = <&rpmhpd_opp_low_svs>;
549		};
550
551		opp-100000000 {
552			opp-hz = /bits/ 64 <100000000>;
553			required-opps = <&rpmhpd_opp_svs>;
554		};
555	};
556
557	reserved-memory {
558		#address-cells = <2>;
559		#size-cells = <2>;
560		ranges;
561
562		reserved-region@80000000 {
563			reg = <0 0x80000000 0 0x860000>;
564			no-map;
565		};
566
567		cmd_db: cmd-db-region@80860000 {
568			compatible = "qcom,cmd-db";
569			reg = <0 0x80860000 0 0x20000>;
570			no-map;
571		};
572
573		reserved-region@80880000 {
574			reg = <0 0x80880000 0 0x80000>;
575			no-map;
576		};
577
578		smem_mem: smem-region@80900000 {
579			compatible = "qcom,smem";
580			reg = <0 0x80900000 0 0x200000>;
581			no-map;
582			hwlocks = <&tcsr_mutex 3>;
583		};
584
585		reserved-region@80b00000 {
586			reg = <0 0x80b00000 0 0x100000>;
587			no-map;
588		};
589
590		reserved-region@83b00000 {
591			reg = <0 0x83b00000 0 0x1700000>;
592			no-map;
593		};
594
595		reserved-region@85b00000 {
596			reg = <0 0x85b00000 0 0xc00000>;
597			no-map;
598		};
599
600		pil_adsp_mem: adsp-region@86c00000 {
601			reg = <0 0x86c00000 0 0x2000000>;
602			no-map;
603		};
604
605		pil_nsp0_mem: cdsp0-region@8a100000 {
606			reg = <0 0x8a100000 0 0x1e00000>;
607			no-map;
608		};
609
610		pil_nsp1_mem: cdsp1-region@8c600000 {
611			reg = <0 0x8c600000 0 0x1e00000>;
612			no-map;
613		};
614
615		reserved-region@aeb00000 {
616			reg = <0 0xaeb00000 0 0x16600000>;
617			no-map;
618		};
619	};
620
621	smp2p-adsp {
622		compatible = "qcom,smp2p";
623		qcom,smem = <443>, <429>;
624		interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
625					     IPCC_MPROC_SIGNAL_SMP2P
626					     IRQ_TYPE_EDGE_RISING>;
627		mboxes = <&ipcc IPCC_CLIENT_LPASS
628				IPCC_MPROC_SIGNAL_SMP2P>;
629
630		qcom,local-pid = <0>;
631		qcom,remote-pid = <2>;
632
633		smp2p_adsp_out: master-kernel {
634			qcom,entry-name = "master-kernel";
635			#qcom,smem-state-cells = <1>;
636		};
637
638		smp2p_adsp_in: slave-kernel {
639			qcom,entry-name = "slave-kernel";
640			interrupt-controller;
641			#interrupt-cells = <2>;
642		};
643	};
644
645	smp2p-nsp0 {
646		compatible = "qcom,smp2p";
647		qcom,smem = <94>, <432>;
648		interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
649					     IPCC_MPROC_SIGNAL_SMP2P
650					     IRQ_TYPE_EDGE_RISING>;
651		mboxes = <&ipcc IPCC_CLIENT_CDSP
652				IPCC_MPROC_SIGNAL_SMP2P>;
653
654		qcom,local-pid = <0>;
655		qcom,remote-pid = <5>;
656
657		smp2p_nsp0_out: master-kernel {
658			qcom,entry-name = "master-kernel";
659			#qcom,smem-state-cells = <1>;
660		};
661
662		smp2p_nsp0_in: slave-kernel {
663			qcom,entry-name = "slave-kernel";
664			interrupt-controller;
665			#interrupt-cells = <2>;
666		};
667	};
668
669	smp2p-nsp1 {
670		compatible = "qcom,smp2p";
671		qcom,smem = <617>, <616>;
672		interrupts-extended = <&ipcc IPCC_CLIENT_NSP1
673					     IPCC_MPROC_SIGNAL_SMP2P
674					     IRQ_TYPE_EDGE_RISING>;
675		mboxes = <&ipcc IPCC_CLIENT_NSP1
676				IPCC_MPROC_SIGNAL_SMP2P>;
677
678		qcom,local-pid = <0>;
679		qcom,remote-pid = <12>;
680
681		smp2p_nsp1_out: master-kernel {
682			qcom,entry-name = "master-kernel";
683			#qcom,smem-state-cells = <1>;
684		};
685
686		smp2p_nsp1_in: slave-kernel {
687			qcom,entry-name = "slave-kernel";
688			interrupt-controller;
689			#interrupt-cells = <2>;
690		};
691	};
692
693	soc: soc@0 {
694		compatible = "simple-bus";
695		#address-cells = <2>;
696		#size-cells = <2>;
697		ranges = <0 0 0 0 0x10 0>;
698		dma-ranges = <0 0 0 0 0x10 0>;
699
700		gcc: clock-controller@100000 {
701			compatible = "qcom,gcc-sc8280xp";
702			reg = <0x0 0x00100000 0x0 0x1f0000>;
703			#clock-cells = <1>;
704			#reset-cells = <1>;
705			#power-domain-cells = <1>;
706			clocks = <&rpmhcc RPMH_CXO_CLK>,
707				 <&sleep_clk>,
708				 <0>,
709				 <0>,
710				 <0>,
711				 <0>,
712				 <0>,
713				 <0>,
714				 <&usb_0_ssphy>,
715				 <0>,
716				 <0>,
717				 <0>,
718				 <0>,
719				 <0>,
720				 <0>,
721				 <0>,
722				 <&usb_1_ssphy>,
723				 <0>,
724				 <0>,
725				 <0>,
726				 <0>,
727				 <0>,
728				 <0>,
729				 <0>,
730				 <0>,
731				 <0>,
732				 <0>,
733				 <0>,
734				 <0>,
735				 <0>,
736				 <0>,
737				 <0>,
738				 <0>;
739			power-domains = <&rpmhpd SC8280XP_CX>;
740		};
741
742		ipcc: mailbox@408000 {
743			compatible = "qcom,sc8280xp-ipcc", "qcom,ipcc";
744			reg = <0 0x00408000 0 0x1000>;
745			interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
746			interrupt-controller;
747			#interrupt-cells = <3>;
748			#mbox-cells = <2>;
749		};
750
751		qup2: geniqup@8c0000 {
752			compatible = "qcom,geni-se-qup";
753			reg = <0 0x008c0000 0 0x2000>;
754			clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
755				 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
756			clock-names = "m-ahb", "s-ahb";
757			iommus = <&apps_smmu 0xa3 0>;
758
759			#address-cells = <2>;
760			#size-cells = <2>;
761			ranges;
762
763			status = "disabled";
764
765			qup2_uart17: serial@884000 {
766				compatible = "qcom,geni-uart";
767				reg = <0 0x00884000 0 0x4000>;
768				clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
769				clock-names = "se";
770				interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
771				operating-points-v2 = <&qup_opp_table_100mhz>;
772				power-domains = <&rpmhpd SC8280XP_CX>;
773				interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
774						<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>;
775				interconnect-names = "qup-core", "qup-config";
776				status = "disabled";
777			};
778
779			qup2_i2c5: i2c@894000 {
780				compatible = "qcom,geni-i2c";
781				reg = <0 0x00894000 0 0x4000>;
782				clock-names = "se";
783				clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
784				interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
785				#address-cells = <1>;
786				#size-cells = <0>;
787				power-domains = <&rpmhpd SC8280XP_CX>;
788				interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
789						<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
790						<&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
791				interconnect-names = "qup-core", "qup-config", "qup-memory";
792				status = "disabled";
793			};
794		};
795
796		qup0: geniqup@9c0000 {
797			compatible = "qcom,geni-se-qup";
798			reg = <0 0x009c0000 0 0x6000>;
799			clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
800				 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
801			clock-names = "m-ahb", "s-ahb";
802			iommus = <&apps_smmu 0x563 0>;
803
804			#address-cells = <2>;
805			#size-cells = <2>;
806			ranges;
807
808			status = "disabled";
809
810			qup0_i2c4: i2c@990000 {
811				compatible = "qcom,geni-i2c";
812				reg = <0 0x00990000 0 0x4000>;
813				clock-names = "se";
814				clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
815				interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
816				#address-cells = <1>;
817				#size-cells = <0>;
818				power-domains = <&rpmhpd SC8280XP_CX>;
819				interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
820						<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
821						<&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
822				interconnect-names = "qup-core", "qup-config", "qup-memory";
823				status = "disabled";
824			};
825		};
826
827		qup1: geniqup@ac0000 {
828			compatible = "qcom,geni-se-qup";
829			reg = <0 0x00ac0000 0 0x6000>;
830			clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
831				 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
832			clock-names = "m-ahb", "s-ahb";
833			iommus = <&apps_smmu 0x83 0>;
834
835			#address-cells = <2>;
836			#size-cells = <2>;
837			ranges;
838
839			status = "disabled";
840		};
841
842		ufs_mem_hc: ufs@1d84000 {
843			compatible = "qcom,sc8280xp-ufshc", "qcom,ufshc",
844				     "jedec,ufs-2.0";
845			reg = <0 0x01d84000 0 0x3000>;
846			interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
847			phys = <&ufs_mem_phy_lanes>;
848			phy-names = "ufsphy";
849			lanes-per-direction = <2>;
850			#reset-cells = <1>;
851			resets = <&gcc GCC_UFS_PHY_BCR>;
852			reset-names = "rst";
853
854			power-domains = <&gcc UFS_PHY_GDSC>;
855			required-opps = <&rpmhpd_opp_nom>;
856
857			iommus = <&apps_smmu 0xe0 0x0>;
858
859			clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
860				 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
861				 <&gcc GCC_UFS_PHY_AHB_CLK>,
862				 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
863				 <&rpmhcc RPMH_CXO_CLK>,
864				 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
865				 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
866				 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
867			clock-names = "core_clk",
868				      "bus_aggr_clk",
869				      "iface_clk",
870				      "core_clk_unipro",
871				      "ref_clk",
872				      "tx_lane0_sync_clk",
873				      "rx_lane0_sync_clk",
874				      "rx_lane1_sync_clk";
875			freq-table-hz = <75000000 300000000>,
876					<0 0>,
877					<0 0>,
878					<75000000 300000000>,
879					<0 0>,
880					<0 0>,
881					<0 0>,
882					<0 0>;
883			status = "disabled";
884		};
885
886		ufs_mem_phy: phy@1d87000 {
887			compatible = "qcom,sc8280xp-qmp-ufs-phy";
888			reg = <0 0x01d87000 0 0xe10>;
889			#address-cells = <2>;
890			#size-cells = <2>;
891			ranges;
892			clock-names = "ref",
893				      "ref_aux";
894			clocks = <&rpmhcc RPMH_CXO_CLK>,
895				 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
896
897			resets = <&ufs_mem_hc 0>;
898			reset-names = "ufsphy";
899			status = "disabled";
900
901			ufs_mem_phy_lanes: phy@1d87400 {
902				reg = <0 0x01d87400 0 0x108>,
903				      <0 0x01d87600 0 0x1e0>,
904				      <0 0x01d87c00 0 0x1dc>,
905				      <0 0x01d87800 0 0x108>,
906				      <0 0x01d87a00 0 0x1e0>;
907				#phy-cells = <0>;
908			};
909		};
910
911		ufs_card_hc: ufs@1da4000 {
912			compatible = "qcom,sc8280xp-ufshc", "qcom,ufshc",
913				     "jedec,ufs-2.0";
914			reg = <0 0x01da4000 0 0x3000>;
915			interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
916			phys = <&ufs_card_phy_lanes>;
917			phy-names = "ufsphy";
918			lanes-per-direction = <2>;
919			#reset-cells = <1>;
920			resets = <&gcc GCC_UFS_CARD_BCR>;
921			reset-names = "rst";
922
923			power-domains = <&gcc UFS_CARD_GDSC>;
924
925			iommus = <&apps_smmu 0x4a0 0x0>;
926
927			clocks = <&gcc GCC_UFS_CARD_AXI_CLK>,
928				 <&gcc GCC_AGGRE_UFS_CARD_AXI_CLK>,
929				 <&gcc GCC_UFS_CARD_AHB_CLK>,
930				 <&gcc GCC_UFS_CARD_UNIPRO_CORE_CLK>,
931				 <&rpmhcc RPMH_CXO_CLK>,
932				 <&gcc GCC_UFS_CARD_TX_SYMBOL_0_CLK>,
933				 <&gcc GCC_UFS_CARD_RX_SYMBOL_0_CLK>,
934				 <&gcc GCC_UFS_CARD_RX_SYMBOL_1_CLK>;
935			clock-names = "core_clk",
936				      "bus_aggr_clk",
937				      "iface_clk",
938				      "core_clk_unipro",
939				      "ref_clk",
940				      "tx_lane0_sync_clk",
941				      "rx_lane0_sync_clk",
942				      "rx_lane1_sync_clk";
943			freq-table-hz = <75000000 300000000>,
944					<0 0>,
945					<0 0>,
946					<75000000 300000000>,
947					<0 0>,
948					<0 0>,
949					<0 0>,
950					<0 0>;
951			status = "disabled";
952		};
953
954		ufs_card_phy: phy@1da7000 {
955			compatible = "qcom,sc8280xp-qmp-ufs-phy";
956			reg = <0 0x01da7000 0 0xe10>;
957			#address-cells = <2>;
958			#size-cells = <2>;
959			ranges;
960			clock-names = "ref",
961				      "ref_aux";
962			clocks = <&gcc GCC_UFS_1_CARD_CLKREF_CLK>,
963				 <&gcc GCC_UFS_CARD_PHY_AUX_CLK>;
964
965			resets = <&ufs_card_hc 0>;
966			reset-names = "ufsphy";
967
968			status = "disabled";
969
970			ufs_card_phy_lanes: phy@1da7400 {
971				reg = <0 0x01da7400 0 0x108>,
972				      <0 0x01da7600 0 0x1e0>,
973				      <0 0x01da7c00 0 0x1dc>,
974				      <0 0x01da7800 0 0x108>,
975				      <0 0x01da7a00 0 0x1e0>;
976				#phy-cells = <0>;
977			};
978		};
979
980		tcsr_mutex: hwlock@1f40000 {
981			compatible = "qcom,tcsr-mutex";
982			reg = <0x0 0x01f40000 0x0 0x20000>;
983			#hwlock-cells = <1>;
984		};
985
986		usb_0_hsphy: phy@88e5000 {
987			compatible = "qcom,sc8280xp-usb-hs-phy",
988				     "qcom,usb-snps-hs-5nm-phy";
989			reg = <0 0x088e5000 0 0x400>;
990			clocks = <&rpmhcc RPMH_CXO_CLK>;
991			clock-names = "ref";
992			resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
993
994			#phy-cells = <0>;
995
996			status = "disabled";
997		};
998
999		usb_2_hsphy0: phy@88e7000 {
1000			compatible = "qcom,sc8280xp-usb-hs-phy",
1001				     "qcom,usb-snps-hs-5nm-phy";
1002			reg = <0 0x088e7000 0 0x400>;
1003			clocks = <&gcc GCC_USB2_HS0_CLKREF_CLK>;
1004			clock-names = "ref";
1005			resets = <&gcc GCC_QUSB2PHY_HS0_MP_BCR>;
1006
1007			#phy-cells = <0>;
1008
1009			status = "disabled";
1010		};
1011
1012		usb_2_hsphy1: phy@88e8000 {
1013			compatible = "qcom,sc8280xp-usb-hs-phy",
1014				     "qcom,usb-snps-hs-5nm-phy";
1015			reg = <0 0x088e8000 0 0x400>;
1016			clocks = <&gcc GCC_USB2_HS1_CLKREF_CLK>;
1017			clock-names = "ref";
1018			resets = <&gcc GCC_QUSB2PHY_HS1_MP_BCR>;
1019
1020			#phy-cells = <0>;
1021
1022			status = "disabled";
1023		};
1024
1025		usb_2_hsphy2: phy@88e9000 {
1026			compatible = "qcom,sc8280xp-usb-hs-phy",
1027				     "qcom,usb-snps-hs-5nm-phy";
1028			reg = <0 0x088e9000 0 0x400>;
1029			clocks = <&gcc GCC_USB2_HS2_CLKREF_CLK>;
1030			clock-names = "ref";
1031			resets = <&gcc GCC_QUSB2PHY_HS2_MP_BCR>;
1032
1033			#phy-cells = <0>;
1034
1035			status = "disabled";
1036		};
1037
1038		usb_2_hsphy3: phy@88ea000 {
1039			compatible = "qcom,sc8280xp-usb-hs-phy",
1040				     "qcom,usb-snps-hs-5nm-phy";
1041			reg = <0 0x088ea000 0 0x400>;
1042			clocks = <&gcc GCC_USB2_HS3_CLKREF_CLK>;
1043			clock-names = "ref";
1044			resets = <&gcc GCC_QUSB2PHY_HS3_MP_BCR>;
1045
1046			#phy-cells = <0>;
1047
1048			status = "disabled";
1049		};
1050
1051		usb_2_qmpphy0: phy-wrapper@88ef000 {
1052			compatible = "qcom,sc8280xp-qmp-usb3-uni-phy";
1053			reg = <0 0x088ef000 0 0x1c8>;
1054			#address-cells = <2>;
1055			#size-cells = <2>;
1056			ranges;
1057
1058			clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>,
1059				 <&rpmhcc RPMH_CXO_CLK>,
1060				 <&gcc GCC_USB3_MP0_CLKREF_CLK>,
1061				 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>;
1062			clock-names = "aux", "ref_clk_src", "ref", "com_aux";
1063
1064			resets = <&gcc GCC_USB3_UNIPHY_MP0_BCR>,
1065				 <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>;
1066			reset-names = "phy", "common";
1067
1068			power-domains = <&gcc USB30_MP_GDSC>;
1069
1070			status = "disabled";
1071
1072			usb_2_ssphy0: phy@88efe00 {
1073				reg = <0 0x088efe00 0 0x160>,
1074				      <0 0x088f0000 0 0x1ec>,
1075				      <0 0x088ef200 0 0x1f0>;
1076				#phy-cells = <0>;
1077				#clock-cells = <0>;
1078				clocks = <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>;
1079				clock-names = "pipe0";
1080				clock-output-names = "usb2_phy0_pipe_clk";
1081			};
1082		};
1083
1084		usb_2_qmpphy1: phy-wrapper@88f1000 {
1085			compatible = "qcom,sc8280xp-qmp-usb3-uni-phy";
1086			reg = <0 0x088f1000 0 0x1c8>;
1087			#address-cells = <2>;
1088			#size-cells = <2>;
1089			ranges;
1090
1091			clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>,
1092				 <&rpmhcc RPMH_CXO_CLK>,
1093				 <&gcc GCC_USB3_MP1_CLKREF_CLK>,
1094				 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>;
1095			clock-names = "aux", "ref_clk_src", "ref", "com_aux";
1096
1097			resets = <&gcc GCC_USB3_UNIPHY_MP1_BCR>,
1098				 <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>;
1099			reset-names = "phy", "common";
1100
1101			power-domains = <&gcc USB30_MP_GDSC>;
1102
1103			status = "disabled";
1104
1105			usb_2_ssphy1: phy@88f1e00 {
1106				reg = <0 0x088f1e00 0 0x160>,
1107				      <0 0x088f2000 0 0x1ec>,
1108				      <0 0x088f1200 0 0x1f0>;
1109				#phy-cells = <0>;
1110				#clock-cells = <0>;
1111				clocks = <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>;
1112				clock-names = "pipe0";
1113				clock-output-names = "usb2_phy1_pipe_clk";
1114			};
1115		};
1116
1117		remoteproc_adsp: remoteproc@3000000 {
1118			compatible = "qcom,sc8280xp-adsp-pas";
1119			reg = <0 0x03000000 0 0x100>;
1120
1121			interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
1122					      <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
1123					      <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
1124					      <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
1125					      <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>,
1126					      <&smp2p_adsp_in 7 IRQ_TYPE_EDGE_RISING>;
1127			interrupt-names = "wdog", "fatal", "ready",
1128					  "handover", "stop-ack", "shutdown-ack";
1129
1130			clocks = <&rpmhcc RPMH_CXO_CLK>;
1131			clock-names = "xo";
1132
1133			power-domains = <&rpmhpd SC8280XP_LCX>,
1134					<&rpmhpd SC8280XP_LMX>;
1135			power-domain-names = "lcx", "lmx";
1136
1137			memory-region = <&pil_adsp_mem>;
1138
1139			qcom,qmp = <&aoss_qmp>;
1140
1141			qcom,smem-states = <&smp2p_adsp_out 0>;
1142			qcom,smem-state-names = "stop";
1143
1144			status = "disabled";
1145
1146			remoteproc_adsp_glink: glink-edge {
1147				interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
1148							     IPCC_MPROC_SIGNAL_GLINK_QMP
1149							     IRQ_TYPE_EDGE_RISING>;
1150				mboxes = <&ipcc IPCC_CLIENT_LPASS
1151						IPCC_MPROC_SIGNAL_GLINK_QMP>;
1152
1153				label = "lpass";
1154				qcom,remote-pid = <2>;
1155			};
1156		};
1157
1158		usb_0_qmpphy: phy-wrapper@88ec000 {
1159			compatible = "qcom,sc8280xp-qmp-usb43dp-phy";
1160			reg = <0 0x088ec000 0 0x1e4>,
1161			      <0 0x088eb000 0 0x40>,
1162			      <0 0x088ed000 0 0x1c8>;
1163			#address-cells = <2>;
1164			#size-cells = <2>;
1165			ranges;
1166
1167			clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
1168				 <&rpmhcc RPMH_CXO_CLK>,
1169				 <&gcc GCC_USB4_EUD_CLKREF_CLK>,
1170				 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
1171			clock-names = "aux", "ref_clk_src", "ref", "com_aux";
1172
1173			resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
1174				 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
1175			reset-names = "phy", "common";
1176
1177			power-domains = <&gcc USB30_PRIM_GDSC>;
1178
1179			status = "disabled";
1180
1181			usb_0_ssphy: usb3-phy@88eb400 {
1182				reg = <0 0x088eb400 0 0x100>,
1183				      <0 0x088eb600 0 0x3ec>,
1184				      <0 0x088ec400 0 0x1f0>,
1185				      <0 0x088eba00 0 0x100>,
1186				      <0 0x088ebc00 0 0x3ec>,
1187				      <0 0x088ec700 0 0x64>;
1188				#phy-cells = <0>;
1189				#clock-cells = <0>;
1190				clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
1191				clock-names = "pipe0";
1192				clock-output-names = "usb0_phy_pipe_clk_src";
1193			};
1194
1195			usb_0_dpphy: dp-phy@88ed200 {
1196				reg = <0 0x088ed200 0 0x200>,
1197				      <0 0x088ed400 0 0x200>,
1198				      <0 0x088eda00 0 0x200>,
1199				      <0 0x088ea600 0 0x200>,
1200				      <0 0x088ea800 0 0x200>;
1201				#clock-cells = <1>;
1202				#phy-cells = <0>;
1203			};
1204		};
1205
1206		usb_1_hsphy: phy@8902000 {
1207			compatible = "qcom,sc8280xp-usb-hs-phy",
1208				     "qcom,usb-snps-hs-5nm-phy";
1209			reg = <0 0x08902000 0 0x400>;
1210			#phy-cells = <0>;
1211
1212			clocks = <&rpmhcc RPMH_CXO_CLK>;
1213			clock-names = "ref";
1214
1215			resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
1216
1217			status = "disabled";
1218		};
1219
1220		usb_1_qmpphy: phy-wrapper@8904000 {
1221			compatible = "qcom,sc8280xp-qmp-usb43dp-phy";
1222			reg = <0 0x08904000 0 0x1e4>,
1223			      <0 0x08903000 0 0x40>,
1224			      <0 0x08905000 0 0x1c8>;
1225			#address-cells = <2>;
1226			#size-cells = <2>;
1227			ranges;
1228
1229			clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
1230				 <&rpmhcc RPMH_CXO_CLK>,
1231				 <&gcc GCC_USB4_CLKREF_CLK>,
1232				 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
1233			clock-names = "aux", "ref_clk_src", "ref", "com_aux";
1234
1235			resets = <&gcc GCC_USB3_PHY_SEC_BCR>,
1236				 <&gcc GCC_USB4_1_DP_PHY_PRIM_BCR>;
1237			reset-names = "phy", "common";
1238
1239			power-domains = <&gcc USB30_SEC_GDSC>;
1240
1241			status = "disabled";
1242
1243			usb_1_ssphy: usb3-phy@8903400 {
1244				reg = <0 0x08903400 0 0x100>,
1245				      <0 0x08903c00 0 0x3ec>,
1246				      <0 0x08904400 0 0x1f0>,
1247				      <0 0x08903a00 0 0x100>,
1248				      <0 0x08903c00 0 0x3ec>,
1249				      <0 0x08904200 0 0x18>;
1250				#phy-cells = <0>;
1251				#clock-cells = <0>;
1252				clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
1253				clock-names = "pipe0";
1254				clock-output-names = "usb1_phy_pipe_clk_src";
1255			};
1256
1257			usb_1_dpphy: dp-phy@8904200 {
1258				reg = <0 0x08904200 0 0x200>,
1259				      <0 0x08904400 0 0x200>,
1260				      <0 0x08904a00 0 0x200>,
1261				      <0 0x08904600 0 0x200>,
1262				      <0 0x08904800 0 0x200>;
1263				#clock-cells = <1>;
1264				#phy-cells = <0>;
1265			};
1266		};
1267
1268		system-cache-controller@9200000 {
1269			compatible = "qcom,sc8280xp-llcc";
1270			reg = <0 0x09200000 0 0x58000>, <0 0x09600000 0 0x58000>;
1271			reg-names = "llcc_base", "llcc_broadcast_base";
1272			interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
1273		};
1274
1275		usb_0: usb@a6f8800 {
1276			compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3";
1277			reg = <0 0x0a6f8800 0 0x400>;
1278			#address-cells = <2>;
1279			#size-cells = <2>;
1280			ranges;
1281
1282			clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
1283				 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
1284				 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
1285				 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
1286				 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1287				 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
1288				 <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>,
1289				 <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>,
1290				 <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
1291			clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi",
1292				      "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys";
1293
1294			assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1295					  <&gcc GCC_USB30_PRIM_MASTER_CLK>;
1296			assigned-clock-rates = <19200000>, <200000000>;
1297
1298			interrupts-extended = <&intc GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>,
1299					      <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
1300					      <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
1301					      <&pdc 138 IRQ_TYPE_LEVEL_HIGH>;
1302			interrupt-names = "pwr_event",
1303					  "dp_hs_phy_irq",
1304					  "dm_hs_phy_irq",
1305					  "ss_phy_irq";
1306
1307			power-domains = <&gcc USB30_PRIM_GDSC>;
1308
1309			resets = <&gcc GCC_USB30_PRIM_BCR>;
1310
1311			interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
1312					<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
1313			interconnect-names = "usb-ddr", "apps-usb";
1314
1315			wakeup-source;
1316
1317			status = "disabled";
1318
1319			usb_0_dwc3: usb@a600000 {
1320				compatible = "snps,dwc3";
1321				reg = <0 0x0a600000 0 0xcd00>;
1322				interrupts = <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>;
1323				iommus = <&apps_smmu 0x820 0x0>;
1324				phys = <&usb_0_hsphy>, <&usb_0_ssphy>;
1325				phy-names = "usb2-phy", "usb3-phy";
1326			};
1327		};
1328
1329		usb_1: usb@a8f8800 {
1330			compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3";
1331			reg = <0 0x0a8f8800 0 0x400>;
1332			#address-cells = <2>;
1333			#size-cells = <2>;
1334			ranges;
1335
1336			clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
1337				 <&gcc GCC_USB30_SEC_MASTER_CLK>,
1338				 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
1339				 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
1340				 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
1341				 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
1342				 <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>,
1343				 <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>,
1344				 <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
1345			clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi",
1346				      "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys";
1347
1348			assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
1349					  <&gcc GCC_USB30_SEC_MASTER_CLK>;
1350			assigned-clock-rates = <19200000>, <200000000>;
1351
1352			interrupts-extended = <&intc GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>,
1353					      <&pdc 12 IRQ_TYPE_EDGE_BOTH>,
1354					      <&pdc 13 IRQ_TYPE_EDGE_BOTH>,
1355					      <&pdc 136 IRQ_TYPE_LEVEL_HIGH>;
1356			interrupt-names = "pwr_event",
1357					  "dp_hs_phy_irq",
1358					  "dm_hs_phy_irq",
1359					  "ss_phy_irq";
1360
1361			power-domains = <&gcc USB30_SEC_GDSC>;
1362
1363			resets = <&gcc GCC_USB30_SEC_BCR>;
1364
1365			interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>,
1366					<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>;
1367			interconnect-names = "usb-ddr", "apps-usb";
1368
1369			wakeup-source;
1370
1371			status = "disabled";
1372
1373			usb_1_dwc3: usb@a800000 {
1374				compatible = "snps,dwc3";
1375				reg = <0 0x0a800000 0 0xcd00>;
1376				interrupts = <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>;
1377				iommus = <&apps_smmu 0x860 0x0>;
1378				phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
1379				phy-names = "usb2-phy", "usb3-phy";
1380			};
1381		};
1382
1383		pdc: interrupt-controller@b220000 {
1384			compatible = "qcom,sc8280xp-pdc", "qcom,pdc";
1385			reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
1386			qcom,pdc-ranges = <0 480 40>,
1387					  <40 140 14>,
1388					  <54 263 1>,
1389					  <55 306 4>,
1390					  <59 312 3>,
1391					  <62 374 2>,
1392					  <64 434 2>,
1393					  <66 438 3>,
1394					  <69 86 1>,
1395					  <70 520 54>,
1396					  <124 609 28>,
1397					  <159 638 1>,
1398					  <160 720 8>,
1399					  <168 801 1>,
1400					  <169 728 30>,
1401					  <199 416 2>,
1402					  <201 449 1>,
1403					  <202 89 1>,
1404					  <203 451 1>,
1405					  <204 462 1>,
1406					  <205 264 1>,
1407					  <206 579 1>,
1408					  <207 653 1>,
1409					  <208 656 1>,
1410					  <209 659 1>,
1411					  <210 122 1>,
1412					  <211 699 1>,
1413					  <212 705 1>,
1414					  <213 450 1>,
1415					  <214 643 1>,
1416					  <216 646 5>,
1417					  <221 390 5>,
1418					  <226 700 3>,
1419					  <229 240 3>,
1420					  <232 269 1>,
1421					  <233 377 1>,
1422					  <234 372 1>,
1423					  <235 138 1>,
1424					  <236 857 1>,
1425					  <237 860 1>,
1426					  <238 137 1>,
1427					  <239 668 1>,
1428					  <240 366 1>,
1429					  <241 949 1>,
1430					  <242 815 5>,
1431					  <247 769 1>,
1432					  <248 768 1>,
1433					  <249 663 1>,
1434					  <250 799 2>,
1435					  <252 798 1>,
1436					  <253 765 1>,
1437					  <254 763 1>,
1438					  <255 454 1>,
1439					  <258 139 1>,
1440					  <259 786 2>,
1441					  <261 370 2>,
1442					  <263 158 2>;
1443			#interrupt-cells = <2>;
1444			interrupt-parent = <&intc>;
1445			interrupt-controller;
1446		};
1447
1448		tsens0: thermal-sensor@c263000 {
1449			compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2";
1450			reg = <0 0x0c263000 0 0x1ff>, /* TM */
1451			      <0 0x0c222000 0 0x8>; /* SROT */
1452			#qcom,sensors = <14>;
1453			interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>,
1454					      <&pdc 28 IRQ_TYPE_LEVEL_HIGH>;
1455			interrupt-names = "uplow", "critical";
1456			#thermal-sensor-cells = <1>;
1457		};
1458
1459		tsens1: thermal-sensor@c265000 {
1460			compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2";
1461			reg = <0 0x0c265000 0 0x1ff>, /* TM */
1462			      <0 0x0c223000 0 0x8>; /* SROT */
1463			#qcom,sensors = <16>;
1464			interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>,
1465					      <&pdc 29 IRQ_TYPE_LEVEL_HIGH>;
1466			interrupt-names = "uplow", "critical";
1467			#thermal-sensor-cells = <1>;
1468		};
1469
1470		aoss_qmp: power-controller@c300000 {
1471			compatible = "qcom,sc8280xp-aoss-qmp", "qcom,aoss-qmp";
1472			reg = <0 0x0c300000 0 0x400>;
1473			interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>;
1474			mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
1475
1476			#clock-cells = <0>;
1477		};
1478
1479		spmi_bus: spmi@c440000 {
1480			compatible = "qcom,spmi-pmic-arb";
1481			reg = <0 0x0c440000 0 0x1100>,
1482			      <0 0x0c600000 0 0x2000000>,
1483			      <0 0x0e600000 0 0x100000>,
1484			      <0 0x0e700000 0 0xa0000>,
1485			      <0 0x0c40a000 0 0x26000>;
1486			reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1487			interrupt-names = "periph_irq";
1488			interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
1489			qcom,ee = <0>;
1490			qcom,channel = <0>;
1491			#address-cells = <1>;
1492			#size-cells = <1>;
1493			interrupt-controller;
1494			#interrupt-cells = <4>;
1495		};
1496
1497		tlmm: pinctrl@f100000 {
1498			compatible = "qcom,sc8280xp-tlmm";
1499			reg = <0 0x0f100000 0 0x300000>;
1500			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1501			gpio-controller;
1502			#gpio-cells = <2>;
1503			interrupt-controller;
1504			#interrupt-cells = <2>;
1505			gpio-ranges = <&tlmm 0 0 230>;
1506		};
1507
1508		apps_smmu: iommu@15000000 {
1509			compatible = "qcom,sc8280xp-smmu-500", "arm,mmu-500";
1510			reg = <0 0x15000000 0 0x100000>;
1511			#iommu-cells = <2>;
1512			#global-interrupts = <2>;
1513			interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
1514				     <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
1515				     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
1516				     <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1517				     <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
1518				     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
1519				     <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
1520				     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
1521				     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
1522				     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
1523				     <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
1524				     <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
1525				     <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
1526				     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
1527				     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
1528				     <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1529				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
1530				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
1531				     <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
1532				     <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
1533				     <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
1534				     <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
1535				     <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
1536				     <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
1537				     <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
1538				     <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
1539				     <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
1540				     <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
1541				     <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
1542				     <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
1543				     <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
1544				     <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
1545				     <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
1546				     <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
1547				     <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
1548				     <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
1549				     <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
1550				     <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
1551				     <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
1552				     <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
1553				     <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
1554				     <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
1555				     <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
1556				     <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
1557				     <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
1558				     <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
1559				     <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
1560				     <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
1561				     <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
1562				     <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
1563				     <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
1564				     <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
1565				     <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
1566				     <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
1567				     <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
1568				     <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
1569				     <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
1570				     <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
1571				     <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
1572				     <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
1573				     <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
1574				     <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
1575				     <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
1576				     <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
1577				     <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
1578				     <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
1579				     <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
1580				     <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
1581				     <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
1582				     <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
1583				     <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
1584				     <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
1585				     <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
1586				     <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
1587				     <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
1588				     <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
1589				     <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
1590				     <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
1591				     <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
1592				     <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
1593				     <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>,
1594				     <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
1595				     <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
1596				     <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
1597				     <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>,
1598				     <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
1599				     <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
1600				     <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
1601				     <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
1602				     <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
1603				     <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
1604				     <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
1605				     <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
1606				     <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
1607				     <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
1608				     <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
1609				     <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
1610				     <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
1611				     <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>,
1612				     <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>,
1613				     <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>,
1614				     <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>,
1615				     <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
1616				     <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>,
1617				     <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>,
1618				     <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>,
1619				     <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>,
1620				     <GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH>,
1621				     <GIC_SPI 911 IRQ_TYPE_LEVEL_HIGH>,
1622				     <GIC_SPI 910 IRQ_TYPE_LEVEL_HIGH>,
1623				     <GIC_SPI 909 IRQ_TYPE_LEVEL_HIGH>,
1624				     <GIC_SPI 908 IRQ_TYPE_LEVEL_HIGH>,
1625				     <GIC_SPI 907 IRQ_TYPE_LEVEL_HIGH>,
1626				     <GIC_SPI 906 IRQ_TYPE_LEVEL_HIGH>,
1627				     <GIC_SPI 905 IRQ_TYPE_LEVEL_HIGH>,
1628				     <GIC_SPI 904 IRQ_TYPE_LEVEL_HIGH>,
1629				     <GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>,
1630				     <GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>,
1631				     <GIC_SPI 901 IRQ_TYPE_LEVEL_HIGH>,
1632				     <GIC_SPI 900 IRQ_TYPE_LEVEL_HIGH>,
1633				     <GIC_SPI 899 IRQ_TYPE_LEVEL_HIGH>,
1634				     <GIC_SPI 898 IRQ_TYPE_LEVEL_HIGH>,
1635				     <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>,
1636				     <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>,
1637				     <GIC_SPI 895 IRQ_TYPE_LEVEL_HIGH>,
1638				     <GIC_SPI 894 IRQ_TYPE_LEVEL_HIGH>,
1639				     <GIC_SPI 893 IRQ_TYPE_LEVEL_HIGH>,
1640				     <GIC_SPI 892 IRQ_TYPE_LEVEL_HIGH>,
1641				     <GIC_SPI 891 IRQ_TYPE_LEVEL_HIGH>,
1642				     <GIC_SPI 890 IRQ_TYPE_LEVEL_HIGH>;
1643		};
1644
1645		intc: interrupt-controller@17a00000 {
1646			compatible = "arm,gic-v3";
1647			interrupt-controller;
1648			#interrupt-cells = <3>;
1649			reg = <0x0 0x17a00000 0x0 0x10000>,	/* GICD */
1650			      <0x0 0x17a60000 0x0 0x100000>;	/* GICR * 8 */
1651			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
1652			#redistributor-regions = <1>;
1653			redistributor-stride = <0 0x20000>;
1654
1655			#address-cells = <2>;
1656			#size-cells = <2>;
1657			ranges;
1658
1659			gic-its@17a40000 {
1660				compatible = "arm,gic-v3-its";
1661				reg = <0 0x17a40000 0 0x20000>;
1662				msi-controller;
1663				#msi-cells = <1>;
1664			};
1665		};
1666
1667		watchdog@17c10000 {
1668			compatible = "qcom,apss-wdt-sc8280xp", "qcom,kpss-wdt";
1669			reg = <0 0x17c10000 0 0x1000>;
1670			clocks = <&sleep_clk>;
1671			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
1672		};
1673
1674		timer@17c20000 {
1675			compatible = "arm,armv7-timer-mem";
1676			reg = <0x0 0x17c20000 0x0 0x1000>;
1677			#address-cells = <1>;
1678			#size-cells = <1>;
1679			ranges = <0x0 0x0 0x0 0x20000000>;
1680
1681			frame@17c21000 {
1682				frame-number = <0>;
1683				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
1684					     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1685				reg = <0x17c21000 0x1000>,
1686				      <0x17c22000 0x1000>;
1687			};
1688
1689			frame@17c23000 {
1690				frame-number = <1>;
1691				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1692				reg = <0x17c23000 0x1000>;
1693				status = "disabled";
1694			};
1695
1696			frame@17c25000 {
1697				frame-number = <2>;
1698				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1699				reg = <0x17c25000 0x1000>;
1700				status = "disabled";
1701			};
1702
1703			frame@17c27000 {
1704				frame-number = <3>;
1705				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1706				reg = <0x17c26000 0x1000>;
1707				status = "disabled";
1708			};
1709
1710			frame@17c29000 {
1711				frame-number = <4>;
1712				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1713				reg = <0x17c29000 0x1000>;
1714				status = "disabled";
1715			};
1716
1717			frame@17c2b000 {
1718				frame-number = <5>;
1719				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1720				reg = <0x17c2b000 0x1000>;
1721				status = "disabled";
1722			};
1723
1724			frame@17c2d000 {
1725				frame-number = <6>;
1726				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1727				reg = <0x17c2d000 0x1000>;
1728				status = "disabled";
1729			};
1730		};
1731
1732		apps_rsc: rsc@18200000 {
1733			compatible = "qcom,rpmh-rsc";
1734			reg = <0x0 0x18200000 0x0 0x10000>,
1735				<0x0 0x18210000 0x0 0x10000>,
1736				<0x0 0x18220000 0x0 0x10000>;
1737			reg-names = "drv-0", "drv-1", "drv-2";
1738			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
1739				     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
1740				     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1741			qcom,tcs-offset = <0xd00>;
1742			qcom,drv-id = <2>;
1743			qcom,tcs-config = <ACTIVE_TCS  2>, <SLEEP_TCS   3>,
1744					  <WAKE_TCS    3>, <CONTROL_TCS 1>;
1745			label = "apps_rsc";
1746
1747			apps_bcm_voter: bcm-voter {
1748				compatible = "qcom,bcm-voter";
1749			};
1750
1751			rpmhcc: clock-controller {
1752				compatible = "qcom,sc8280xp-rpmh-clk";
1753				#clock-cells = <1>;
1754				clock-names = "xo";
1755				clocks = <&xo_board_clk>;
1756			};
1757
1758			rpmhpd: power-controller {
1759				compatible = "qcom,sc8280xp-rpmhpd";
1760				#power-domain-cells = <1>;
1761				operating-points-v2 = <&rpmhpd_opp_table>;
1762
1763				rpmhpd_opp_table: opp-table {
1764					compatible = "operating-points-v2";
1765
1766					rpmhpd_opp_ret: opp1 {
1767						opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
1768					};
1769
1770					rpmhpd_opp_min_svs: opp2 {
1771						opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
1772					};
1773
1774					rpmhpd_opp_low_svs: opp3 {
1775						opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
1776					};
1777
1778					rpmhpd_opp_svs: opp4 {
1779						opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
1780					};
1781
1782					rpmhpd_opp_svs_l1: opp5 {
1783						opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
1784					};
1785
1786					rpmhpd_opp_nom: opp6 {
1787						opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
1788					};
1789
1790					rpmhpd_opp_nom_l1: opp7 {
1791						opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
1792					};
1793
1794					rpmhpd_opp_nom_l2: opp8 {
1795						opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
1796					};
1797
1798					rpmhpd_opp_turbo: opp9 {
1799						opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
1800					};
1801
1802					rpmhpd_opp_turbo_l1: opp10 {
1803						opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
1804					};
1805				};
1806			};
1807		};
1808
1809		cpufreq_hw: cpufreq@18591000 {
1810			compatible = "qcom,sc8280xp-cpufreq-epss", "qcom,cpufreq-epss";
1811			reg = <0 0x18591000 0 0x1000>,
1812			      <0 0x18592000 0 0x1000>;
1813			reg-names = "freq-domain0", "freq-domain1";
1814
1815			clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
1816			clock-names = "xo", "alternate";
1817
1818			#freq-domain-cells = <1>;
1819		};
1820
1821		remoteproc_nsp0: remoteproc@1b300000 {
1822			compatible = "qcom,sc8280xp-nsp0-pas";
1823			reg = <0 0x1b300000 0 0x100>;
1824
1825			interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
1826					      <&smp2p_nsp0_in 0 IRQ_TYPE_EDGE_RISING>,
1827					      <&smp2p_nsp0_in 1 IRQ_TYPE_EDGE_RISING>,
1828					      <&smp2p_nsp0_in 2 IRQ_TYPE_EDGE_RISING>,
1829					      <&smp2p_nsp0_in 3 IRQ_TYPE_EDGE_RISING>;
1830			interrupt-names = "wdog", "fatal", "ready",
1831					  "handover", "stop-ack";
1832
1833			clocks = <&rpmhcc RPMH_CXO_CLK>;
1834			clock-names = "xo";
1835
1836			power-domains = <&rpmhpd SC8280XP_NSP>;
1837			power-domain-names = "nsp";
1838
1839			memory-region = <&pil_nsp0_mem>;
1840
1841			qcom,smem-states = <&smp2p_nsp0_out 0>;
1842			qcom,smem-state-names = "stop";
1843
1844			interconnects = <&nspa_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>;
1845
1846			status = "disabled";
1847
1848			glink-edge {
1849				interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
1850							     IPCC_MPROC_SIGNAL_GLINK_QMP
1851							     IRQ_TYPE_EDGE_RISING>;
1852				mboxes = <&ipcc IPCC_CLIENT_CDSP
1853						IPCC_MPROC_SIGNAL_GLINK_QMP>;
1854
1855				label = "nsp0";
1856				qcom,remote-pid = <5>;
1857
1858				fastrpc {
1859					compatible = "qcom,fastrpc";
1860					qcom,glink-channels = "fastrpcglink-apps-dsp";
1861					label = "cdsp";
1862					#address-cells = <1>;
1863					#size-cells = <0>;
1864
1865					compute-cb@1 {
1866						compatible = "qcom,fastrpc-compute-cb";
1867						reg = <1>;
1868						iommus = <&apps_smmu 0x3181 0x0420>;
1869					};
1870
1871					compute-cb@2 {
1872						compatible = "qcom,fastrpc-compute-cb";
1873						reg = <2>;
1874						iommus = <&apps_smmu 0x3182 0x0420>;
1875					};
1876
1877					compute-cb@3 {
1878						compatible = "qcom,fastrpc-compute-cb";
1879						reg = <3>;
1880						iommus = <&apps_smmu 0x3183 0x0420>;
1881					};
1882
1883					compute-cb@4 {
1884						compatible = "qcom,fastrpc-compute-cb";
1885						reg = <4>;
1886						iommus = <&apps_smmu 0x3184 0x0420>;
1887					};
1888
1889					compute-cb@5 {
1890						compatible = "qcom,fastrpc-compute-cb";
1891						reg = <5>;
1892						iommus = <&apps_smmu 0x3185 0x0420>;
1893					};
1894
1895					compute-cb@6 {
1896						compatible = "qcom,fastrpc-compute-cb";
1897						reg = <6>;
1898						iommus = <&apps_smmu 0x3186 0x0420>;
1899					};
1900
1901					compute-cb@7 {
1902						compatible = "qcom,fastrpc-compute-cb";
1903						reg = <7>;
1904						iommus = <&apps_smmu 0x3187 0x0420>;
1905					};
1906
1907					compute-cb@8 {
1908						compatible = "qcom,fastrpc-compute-cb";
1909						reg = <8>;
1910						iommus = <&apps_smmu 0x3188 0x0420>;
1911					};
1912
1913					compute-cb@9 {
1914						compatible = "qcom,fastrpc-compute-cb";
1915						reg = <9>;
1916						iommus = <&apps_smmu 0x318b 0x0420>;
1917					};
1918
1919					compute-cb@10 {
1920						compatible = "qcom,fastrpc-compute-cb";
1921						reg = <10>;
1922						iommus = <&apps_smmu 0x318b 0x0420>;
1923					};
1924
1925					compute-cb@11 {
1926						compatible = "qcom,fastrpc-compute-cb";
1927						reg = <11>;
1928						iommus = <&apps_smmu 0x318c 0x0420>;
1929					};
1930
1931					compute-cb@12 {
1932						compatible = "qcom,fastrpc-compute-cb";
1933						reg = <12>;
1934						iommus = <&apps_smmu 0x318d 0x0420>;
1935					};
1936
1937					compute-cb@13 {
1938						compatible = "qcom,fastrpc-compute-cb";
1939						reg = <13>;
1940						iommus = <&apps_smmu 0x318e 0x0420>;
1941					};
1942
1943					compute-cb@14 {
1944						compatible = "qcom,fastrpc-compute-cb";
1945						reg = <14>;
1946						iommus = <&apps_smmu 0x318f 0x0420>;
1947					};
1948				};
1949			};
1950		};
1951
1952		remoteproc_nsp1: remoteproc@21300000 {
1953			compatible = "qcom,sc8280xp-nsp1-pas";
1954			reg = <0 0x21300000 0 0x100>;
1955
1956			interrupts-extended = <&intc GIC_SPI 887 IRQ_TYPE_LEVEL_HIGH>,
1957					      <&smp2p_nsp1_in 0 IRQ_TYPE_EDGE_RISING>,
1958					      <&smp2p_nsp1_in 1 IRQ_TYPE_EDGE_RISING>,
1959					      <&smp2p_nsp1_in 2 IRQ_TYPE_EDGE_RISING>,
1960					      <&smp2p_nsp1_in 3 IRQ_TYPE_EDGE_RISING>;
1961			interrupt-names = "wdog", "fatal", "ready",
1962					  "handover", "stop-ack";
1963
1964			clocks = <&rpmhcc RPMH_CXO_CLK>;
1965			clock-names = "xo";
1966
1967			power-domains = <&rpmhpd SC8280XP_NSP>;
1968			power-domain-names = "nsp";
1969
1970			memory-region = <&pil_nsp1_mem>;
1971
1972			qcom,smem-states = <&smp2p_nsp1_out 0>;
1973			qcom,smem-state-names = "stop";
1974
1975			interconnects = <&nspb_noc MASTER_CDSP_PROC_B 0 &mc_virt SLAVE_EBI1 0>;
1976
1977			status = "disabled";
1978
1979			glink-edge {
1980				interrupts-extended = <&ipcc IPCC_CLIENT_NSP1
1981							     IPCC_MPROC_SIGNAL_GLINK_QMP
1982							     IRQ_TYPE_EDGE_RISING>;
1983				mboxes = <&ipcc IPCC_CLIENT_NSP1
1984						IPCC_MPROC_SIGNAL_GLINK_QMP>;
1985
1986				label = "nsp1";
1987				qcom,remote-pid = <12>;
1988			};
1989		};
1990	};
1991
1992	thermal-zones {
1993		cpu0-thermal {
1994			polling-delay-passive = <250>;
1995			polling-delay = <1000>;
1996
1997			thermal-sensors = <&tsens0 1>;
1998
1999			trips {
2000				cpu-crit {
2001					temperature = <110000>;
2002					hysteresis = <1000>;
2003					type = "critical";
2004				};
2005			};
2006		};
2007
2008		cpu1-thermal {
2009			polling-delay-passive = <250>;
2010			polling-delay = <1000>;
2011
2012			thermal-sensors = <&tsens0 2>;
2013
2014			trips {
2015				cpu-crit {
2016					temperature = <110000>;
2017					hysteresis = <1000>;
2018					type = "critical";
2019				};
2020			};
2021		};
2022
2023		cpu2-thermal {
2024			polling-delay-passive = <250>;
2025			polling-delay = <1000>;
2026
2027			thermal-sensors = <&tsens0 3>;
2028
2029			trips {
2030				cpu-crit {
2031					temperature = <110000>;
2032					hysteresis = <1000>;
2033					type = "critical";
2034				};
2035			};
2036		};
2037
2038		cpu3-thermal {
2039			polling-delay-passive = <250>;
2040			polling-delay = <1000>;
2041
2042			thermal-sensors = <&tsens0 4>;
2043
2044			trips {
2045				cpu-crit {
2046					temperature = <110000>;
2047					hysteresis = <1000>;
2048					type = "critical";
2049				};
2050			};
2051		};
2052
2053		cpu4-thermal {
2054			polling-delay-passive = <250>;
2055			polling-delay = <1000>;
2056
2057			thermal-sensors = <&tsens0 5>;
2058
2059			trips {
2060				cpu-crit {
2061					temperature = <110000>;
2062					hysteresis = <1000>;
2063					type = "critical";
2064				};
2065			};
2066		};
2067
2068		cpu5-thermal {
2069			polling-delay-passive = <250>;
2070			polling-delay = <1000>;
2071
2072			thermal-sensors = <&tsens0 6>;
2073
2074			trips {
2075				cpu-crit {
2076					temperature = <110000>;
2077					hysteresis = <1000>;
2078					type = "critical";
2079				};
2080			};
2081		};
2082
2083		cpu6-thermal {
2084			polling-delay-passive = <250>;
2085			polling-delay = <1000>;
2086
2087			thermal-sensors = <&tsens0 7>;
2088
2089			trips {
2090				cpu-crit {
2091					temperature = <110000>;
2092					hysteresis = <1000>;
2093					type = "critical";
2094				};
2095			};
2096		};
2097
2098		cpu7-thermal {
2099			polling-delay-passive = <250>;
2100			polling-delay = <1000>;
2101
2102			thermal-sensors = <&tsens0 8>;
2103
2104			trips {
2105				cpu-crit {
2106					temperature = <110000>;
2107					hysteresis = <1000>;
2108					type = "critical";
2109				};
2110			};
2111		};
2112
2113		cluster0-thermal {
2114			polling-delay-passive = <250>;
2115			polling-delay = <1000>;
2116
2117			thermal-sensors = <&tsens0 9>;
2118
2119			trips {
2120				cpu-crit {
2121					temperature = <110000>;
2122					hysteresis = <1000>;
2123					type = "critical";
2124				};
2125			};
2126		};
2127
2128		mem-thermal {
2129			polling-delay-passive = <250>;
2130			polling-delay = <1000>;
2131
2132			thermal-sensors = <&tsens1 15>;
2133
2134			trips {
2135				trip-point0 {
2136					temperature = <90000>;
2137					hysteresis = <2000>;
2138					type = "hot";
2139				};
2140			};
2141		};
2142	};
2143
2144	timer {
2145		compatible = "arm,armv8-timer";
2146		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
2147			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
2148			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
2149			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
2150	};
2151};
2152