1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2021, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2022, Linaro Limited 5 */ 6 7#include <dt-bindings/clock/qcom,dispcc-sc8280xp.h> 8#include <dt-bindings/clock/qcom,gcc-sc8280xp.h> 9#include <dt-bindings/clock/qcom,rpmh.h> 10#include <dt-bindings/interconnect/qcom,osm-l3.h> 11#include <dt-bindings/interconnect/qcom,sc8280xp.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/mailbox/qcom-ipcc.h> 14#include <dt-bindings/phy/phy-qcom-qmp.h> 15#include <dt-bindings/power/qcom-rpmpd.h> 16#include <dt-bindings/soc/qcom,gpr.h> 17#include <dt-bindings/soc/qcom,rpmh-rsc.h> 18#include <dt-bindings/sound/qcom,q6afe.h> 19#include <dt-bindings/thermal/thermal.h> 20 21/ { 22 interrupt-parent = <&intc>; 23 24 #address-cells = <2>; 25 #size-cells = <2>; 26 27 clocks { 28 xo_board_clk: xo-board-clk { 29 compatible = "fixed-clock"; 30 #clock-cells = <0>; 31 }; 32 33 sleep_clk: sleep-clk { 34 compatible = "fixed-clock"; 35 #clock-cells = <0>; 36 clock-frequency = <32764>; 37 }; 38 }; 39 40 cpus { 41 #address-cells = <2>; 42 #size-cells = <0>; 43 44 CPU0: cpu@0 { 45 device_type = "cpu"; 46 compatible = "arm,cortex-a78c"; 47 reg = <0x0 0x0>; 48 clocks = <&cpufreq_hw 0>; 49 enable-method = "psci"; 50 capacity-dmips-mhz = <602>; 51 next-level-cache = <&L2_0>; 52 power-domains = <&CPU_PD0>; 53 power-domain-names = "psci"; 54 qcom,freq-domain = <&cpufreq_hw 0>; 55 operating-points-v2 = <&cpu0_opp_table>; 56 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 57 #cooling-cells = <2>; 58 L2_0: l2-cache { 59 compatible = "cache"; 60 cache-level = <2>; 61 next-level-cache = <&L3_0>; 62 L3_0: l3-cache { 63 compatible = "cache"; 64 cache-level = <3>; 65 }; 66 }; 67 }; 68 69 CPU1: cpu@100 { 70 device_type = "cpu"; 71 compatible = "arm,cortex-a78c"; 72 reg = <0x0 0x100>; 73 clocks = <&cpufreq_hw 0>; 74 enable-method = "psci"; 75 capacity-dmips-mhz = <602>; 76 next-level-cache = <&L2_100>; 77 power-domains = <&CPU_PD1>; 78 power-domain-names = "psci"; 79 qcom,freq-domain = <&cpufreq_hw 0>; 80 operating-points-v2 = <&cpu0_opp_table>; 81 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 82 #cooling-cells = <2>; 83 L2_100: l2-cache { 84 compatible = "cache"; 85 cache-level = <2>; 86 next-level-cache = <&L3_0>; 87 }; 88 }; 89 90 CPU2: cpu@200 { 91 device_type = "cpu"; 92 compatible = "arm,cortex-a78c"; 93 reg = <0x0 0x200>; 94 clocks = <&cpufreq_hw 0>; 95 enable-method = "psci"; 96 capacity-dmips-mhz = <602>; 97 next-level-cache = <&L2_200>; 98 power-domains = <&CPU_PD2>; 99 power-domain-names = "psci"; 100 qcom,freq-domain = <&cpufreq_hw 0>; 101 operating-points-v2 = <&cpu0_opp_table>; 102 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 103 #cooling-cells = <2>; 104 L2_200: l2-cache { 105 compatible = "cache"; 106 cache-level = <2>; 107 next-level-cache = <&L3_0>; 108 }; 109 }; 110 111 CPU3: cpu@300 { 112 device_type = "cpu"; 113 compatible = "arm,cortex-a78c"; 114 reg = <0x0 0x300>; 115 clocks = <&cpufreq_hw 0>; 116 enable-method = "psci"; 117 capacity-dmips-mhz = <602>; 118 next-level-cache = <&L2_300>; 119 power-domains = <&CPU_PD3>; 120 power-domain-names = "psci"; 121 qcom,freq-domain = <&cpufreq_hw 0>; 122 operating-points-v2 = <&cpu0_opp_table>; 123 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 124 #cooling-cells = <2>; 125 L2_300: l2-cache { 126 compatible = "cache"; 127 cache-level = <2>; 128 next-level-cache = <&L3_0>; 129 }; 130 }; 131 132 CPU4: cpu@400 { 133 device_type = "cpu"; 134 compatible = "arm,cortex-x1c"; 135 reg = <0x0 0x400>; 136 clocks = <&cpufreq_hw 1>; 137 enable-method = "psci"; 138 capacity-dmips-mhz = <1024>; 139 next-level-cache = <&L2_400>; 140 power-domains = <&CPU_PD4>; 141 power-domain-names = "psci"; 142 qcom,freq-domain = <&cpufreq_hw 1>; 143 operating-points-v2 = <&cpu4_opp_table>; 144 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 145 #cooling-cells = <2>; 146 L2_400: l2-cache { 147 compatible = "cache"; 148 cache-level = <2>; 149 next-level-cache = <&L3_0>; 150 }; 151 }; 152 153 CPU5: cpu@500 { 154 device_type = "cpu"; 155 compatible = "arm,cortex-x1c"; 156 reg = <0x0 0x500>; 157 clocks = <&cpufreq_hw 1>; 158 enable-method = "psci"; 159 capacity-dmips-mhz = <1024>; 160 next-level-cache = <&L2_500>; 161 power-domains = <&CPU_PD5>; 162 power-domain-names = "psci"; 163 qcom,freq-domain = <&cpufreq_hw 1>; 164 operating-points-v2 = <&cpu4_opp_table>; 165 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 166 #cooling-cells = <2>; 167 L2_500: l2-cache { 168 compatible = "cache"; 169 cache-level = <2>; 170 next-level-cache = <&L3_0>; 171 }; 172 }; 173 174 CPU6: cpu@600 { 175 device_type = "cpu"; 176 compatible = "arm,cortex-x1c"; 177 reg = <0x0 0x600>; 178 clocks = <&cpufreq_hw 1>; 179 enable-method = "psci"; 180 capacity-dmips-mhz = <1024>; 181 next-level-cache = <&L2_600>; 182 power-domains = <&CPU_PD6>; 183 power-domain-names = "psci"; 184 qcom,freq-domain = <&cpufreq_hw 1>; 185 operating-points-v2 = <&cpu4_opp_table>; 186 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 187 #cooling-cells = <2>; 188 L2_600: l2-cache { 189 compatible = "cache"; 190 cache-level = <2>; 191 next-level-cache = <&L3_0>; 192 }; 193 }; 194 195 CPU7: cpu@700 { 196 device_type = "cpu"; 197 compatible = "arm,cortex-x1c"; 198 reg = <0x0 0x700>; 199 clocks = <&cpufreq_hw 1>; 200 enable-method = "psci"; 201 capacity-dmips-mhz = <1024>; 202 next-level-cache = <&L2_700>; 203 power-domains = <&CPU_PD7>; 204 power-domain-names = "psci"; 205 qcom,freq-domain = <&cpufreq_hw 1>; 206 operating-points-v2 = <&cpu4_opp_table>; 207 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 208 #cooling-cells = <2>; 209 L2_700: l2-cache { 210 compatible = "cache"; 211 cache-level = <2>; 212 next-level-cache = <&L3_0>; 213 }; 214 }; 215 216 cpu-map { 217 cluster0 { 218 core0 { 219 cpu = <&CPU0>; 220 }; 221 222 core1 { 223 cpu = <&CPU1>; 224 }; 225 226 core2 { 227 cpu = <&CPU2>; 228 }; 229 230 core3 { 231 cpu = <&CPU3>; 232 }; 233 234 core4 { 235 cpu = <&CPU4>; 236 }; 237 238 core5 { 239 cpu = <&CPU5>; 240 }; 241 242 core6 { 243 cpu = <&CPU6>; 244 }; 245 246 core7 { 247 cpu = <&CPU7>; 248 }; 249 }; 250 }; 251 252 idle-states { 253 entry-method = "psci"; 254 255 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 256 compatible = "arm,idle-state"; 257 idle-state-name = "little-rail-power-collapse"; 258 arm,psci-suspend-param = <0x40000004>; 259 entry-latency-us = <355>; 260 exit-latency-us = <909>; 261 min-residency-us = <3934>; 262 local-timer-stop; 263 }; 264 265 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 266 compatible = "arm,idle-state"; 267 idle-state-name = "big-rail-power-collapse"; 268 arm,psci-suspend-param = <0x40000004>; 269 entry-latency-us = <241>; 270 exit-latency-us = <1461>; 271 min-residency-us = <4488>; 272 local-timer-stop; 273 }; 274 }; 275 276 domain-idle-states { 277 CLUSTER_SLEEP_0: cluster-sleep-0 { 278 compatible = "domain-idle-state"; 279 arm,psci-suspend-param = <0x4100c344>; 280 entry-latency-us = <3263>; 281 exit-latency-us = <6562>; 282 min-residency-us = <9987>; 283 }; 284 }; 285 }; 286 287 firmware { 288 scm: scm { 289 compatible = "qcom,scm-sc8280xp", "qcom,scm"; 290 }; 291 }; 292 293 aggre1_noc: interconnect-aggre1-noc { 294 compatible = "qcom,sc8280xp-aggre1-noc"; 295 #interconnect-cells = <2>; 296 qcom,bcm-voters = <&apps_bcm_voter>; 297 }; 298 299 aggre2_noc: interconnect-aggre2-noc { 300 compatible = "qcom,sc8280xp-aggre2-noc"; 301 #interconnect-cells = <2>; 302 qcom,bcm-voters = <&apps_bcm_voter>; 303 }; 304 305 clk_virt: interconnect-clk-virt { 306 compatible = "qcom,sc8280xp-clk-virt"; 307 #interconnect-cells = <2>; 308 qcom,bcm-voters = <&apps_bcm_voter>; 309 }; 310 311 config_noc: interconnect-config-noc { 312 compatible = "qcom,sc8280xp-config-noc"; 313 #interconnect-cells = <2>; 314 qcom,bcm-voters = <&apps_bcm_voter>; 315 }; 316 317 dc_noc: interconnect-dc-noc { 318 compatible = "qcom,sc8280xp-dc-noc"; 319 #interconnect-cells = <2>; 320 qcom,bcm-voters = <&apps_bcm_voter>; 321 }; 322 323 gem_noc: interconnect-gem-noc { 324 compatible = "qcom,sc8280xp-gem-noc"; 325 #interconnect-cells = <2>; 326 qcom,bcm-voters = <&apps_bcm_voter>; 327 }; 328 329 lpass_noc: interconnect-lpass-ag-noc { 330 compatible = "qcom,sc8280xp-lpass-ag-noc"; 331 #interconnect-cells = <2>; 332 qcom,bcm-voters = <&apps_bcm_voter>; 333 }; 334 335 mc_virt: interconnect-mc-virt { 336 compatible = "qcom,sc8280xp-mc-virt"; 337 #interconnect-cells = <2>; 338 qcom,bcm-voters = <&apps_bcm_voter>; 339 }; 340 341 mmss_noc: interconnect-mmss-noc { 342 compatible = "qcom,sc8280xp-mmss-noc"; 343 #interconnect-cells = <2>; 344 qcom,bcm-voters = <&apps_bcm_voter>; 345 }; 346 347 nspa_noc: interconnect-nspa-noc { 348 compatible = "qcom,sc8280xp-nspa-noc"; 349 #interconnect-cells = <2>; 350 qcom,bcm-voters = <&apps_bcm_voter>; 351 }; 352 353 nspb_noc: interconnect-nspb-noc { 354 compatible = "qcom,sc8280xp-nspb-noc"; 355 #interconnect-cells = <2>; 356 qcom,bcm-voters = <&apps_bcm_voter>; 357 }; 358 359 system_noc: interconnect-system-noc { 360 compatible = "qcom,sc8280xp-system-noc"; 361 #interconnect-cells = <2>; 362 qcom,bcm-voters = <&apps_bcm_voter>; 363 }; 364 365 memory@80000000 { 366 device_type = "memory"; 367 /* We expect the bootloader to fill in the size */ 368 reg = <0x0 0x80000000 0x0 0x0>; 369 }; 370 371 cpu0_opp_table: opp-table-cpu0 { 372 compatible = "operating-points-v2"; 373 opp-shared; 374 375 opp-300000000 { 376 opp-hz = /bits/ 64 <300000000>; 377 opp-peak-kBps = <(300000 * 32)>; 378 }; 379 opp-403200000 { 380 opp-hz = /bits/ 64 <403200000>; 381 opp-peak-kBps = <(384000 * 32)>; 382 }; 383 opp-499200000 { 384 opp-hz = /bits/ 64 <499200000>; 385 opp-peak-kBps = <(480000 * 32)>; 386 }; 387 opp-595200000 { 388 opp-hz = /bits/ 64 <595200000>; 389 opp-peak-kBps = <(576000 * 32)>; 390 }; 391 opp-691200000 { 392 opp-hz = /bits/ 64 <691200000>; 393 opp-peak-kBps = <(672000 * 32)>; 394 }; 395 opp-806400000 { 396 opp-hz = /bits/ 64 <806400000>; 397 opp-peak-kBps = <(768000 * 32)>; 398 }; 399 opp-902400000 { 400 opp-hz = /bits/ 64 <902400000>; 401 opp-peak-kBps = <(864000 * 32)>; 402 }; 403 opp-1017600000 { 404 opp-hz = /bits/ 64 <1017600000>; 405 opp-peak-kBps = <(960000 * 32)>; 406 }; 407 opp-1113600000 { 408 opp-hz = /bits/ 64 <1113600000>; 409 opp-peak-kBps = <(1075200 * 32)>; 410 }; 411 opp-1209600000 { 412 opp-hz = /bits/ 64 <1209600000>; 413 opp-peak-kBps = <(1171200 * 32)>; 414 }; 415 opp-1324800000 { 416 opp-hz = /bits/ 64 <1324800000>; 417 opp-peak-kBps = <(1267200 * 32)>; 418 }; 419 opp-1440000000 { 420 opp-hz = /bits/ 64 <1440000000>; 421 opp-peak-kBps = <(1363200 * 32)>; 422 }; 423 opp-1555200000 { 424 opp-hz = /bits/ 64 <1555200000>; 425 opp-peak-kBps = <(1536000 * 32)>; 426 }; 427 opp-1670400000 { 428 opp-hz = /bits/ 64 <1670400000>; 429 opp-peak-kBps = <(1612800 * 32)>; 430 }; 431 opp-1785600000 { 432 opp-hz = /bits/ 64 <1785600000>; 433 opp-peak-kBps = <(1689600 * 32)>; 434 }; 435 opp-1881600000 { 436 opp-hz = /bits/ 64 <1881600000>; 437 opp-peak-kBps = <(1689600 * 32)>; 438 }; 439 opp-1996800000 { 440 opp-hz = /bits/ 64 <1996800000>; 441 opp-peak-kBps = <(1689600 * 32)>; 442 }; 443 opp-2112000000 { 444 opp-hz = /bits/ 64 <2112000000>; 445 opp-peak-kBps = <(1689600 * 32)>; 446 }; 447 opp-2227200000 { 448 opp-hz = /bits/ 64 <2227200000>; 449 opp-peak-kBps = <(1689600 * 32)>; 450 }; 451 opp-2342400000 { 452 opp-hz = /bits/ 64 <2342400000>; 453 opp-peak-kBps = <(1689600 * 32)>; 454 }; 455 opp-2438400000 { 456 opp-hz = /bits/ 64 <2438400000>; 457 opp-peak-kBps = <(1689600 * 32)>; 458 }; 459 }; 460 461 cpu4_opp_table: opp-table-cpu4 { 462 compatible = "operating-points-v2"; 463 opp-shared; 464 465 opp-825600000 { 466 opp-hz = /bits/ 64 <825600000>; 467 opp-peak-kBps = <(768000 * 32)>; 468 }; 469 opp-940800000 { 470 opp-hz = /bits/ 64 <940800000>; 471 opp-peak-kBps = <(864000 * 32)>; 472 }; 473 opp-1056000000 { 474 opp-hz = /bits/ 64 <1056000000>; 475 opp-peak-kBps = <(960000 * 32)>; 476 }; 477 opp-1171200000 { 478 opp-hz = /bits/ 64 <1171200000>; 479 opp-peak-kBps = <(1171200 * 32)>; 480 }; 481 opp-1286400000 { 482 opp-hz = /bits/ 64 <1286400000>; 483 opp-peak-kBps = <(1267200 * 32)>; 484 }; 485 opp-1401600000 { 486 opp-hz = /bits/ 64 <1401600000>; 487 opp-peak-kBps = <(1363200 * 32)>; 488 }; 489 opp-1516800000 { 490 opp-hz = /bits/ 64 <1516800000>; 491 opp-peak-kBps = <(1459200 * 32)>; 492 }; 493 opp-1632000000 { 494 opp-hz = /bits/ 64 <1632000000>; 495 opp-peak-kBps = <(1612800 * 32)>; 496 }; 497 opp-1747200000 { 498 opp-hz = /bits/ 64 <1747200000>; 499 opp-peak-kBps = <(1689600 * 32)>; 500 }; 501 opp-1862400000 { 502 opp-hz = /bits/ 64 <1862400000>; 503 opp-peak-kBps = <(1689600 * 32)>; 504 }; 505 opp-1977600000 { 506 opp-hz = /bits/ 64 <1977600000>; 507 opp-peak-kBps = <(1689600 * 32)>; 508 }; 509 opp-2073600000 { 510 opp-hz = /bits/ 64 <2073600000>; 511 opp-peak-kBps = <(1689600 * 32)>; 512 }; 513 opp-2169600000 { 514 opp-hz = /bits/ 64 <2169600000>; 515 opp-peak-kBps = <(1689600 * 32)>; 516 }; 517 opp-2284800000 { 518 opp-hz = /bits/ 64 <2284800000>; 519 opp-peak-kBps = <(1689600 * 32)>; 520 }; 521 opp-2400000000 { 522 opp-hz = /bits/ 64 <2400000000>; 523 opp-peak-kBps = <(1689600 * 32)>; 524 }; 525 opp-2496000000 { 526 opp-hz = /bits/ 64 <2496000000>; 527 opp-peak-kBps = <(1689600 * 32)>; 528 }; 529 opp-2592000000 { 530 opp-hz = /bits/ 64 <2592000000>; 531 opp-peak-kBps = <(1689600 * 32)>; 532 }; 533 opp-2688000000 { 534 opp-hz = /bits/ 64 <2688000000>; 535 opp-peak-kBps = <(1689600 * 32)>; 536 }; 537 opp-2803200000 { 538 opp-hz = /bits/ 64 <2803200000>; 539 opp-peak-kBps = <(1689600 * 32)>; 540 }; 541 opp-2899200000 { 542 opp-hz = /bits/ 64 <2899200000>; 543 opp-peak-kBps = <(1689600 * 32)>; 544 }; 545 opp-2995200000 { 546 opp-hz = /bits/ 64 <2995200000>; 547 opp-peak-kBps = <(1689600 * 32)>; 548 }; 549 }; 550 551 qup_opp_table_100mhz: opp-table-qup100mhz { 552 compatible = "operating-points-v2"; 553 554 opp-75000000 { 555 opp-hz = /bits/ 64 <75000000>; 556 required-opps = <&rpmhpd_opp_low_svs>; 557 }; 558 559 opp-100000000 { 560 opp-hz = /bits/ 64 <100000000>; 561 required-opps = <&rpmhpd_opp_svs>; 562 }; 563 }; 564 565 pmu { 566 compatible = "arm,armv8-pmuv3"; 567 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 568 }; 569 570 psci { 571 compatible = "arm,psci-1.0"; 572 method = "smc"; 573 574 CPU_PD0: power-domain-cpu0 { 575 #power-domain-cells = <0>; 576 power-domains = <&CLUSTER_PD>; 577 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 578 }; 579 580 CPU_PD1: power-domain-cpu1 { 581 #power-domain-cells = <0>; 582 power-domains = <&CLUSTER_PD>; 583 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 584 }; 585 586 CPU_PD2: power-domain-cpu2 { 587 #power-domain-cells = <0>; 588 power-domains = <&CLUSTER_PD>; 589 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 590 }; 591 592 CPU_PD3: power-domain-cpu3 { 593 #power-domain-cells = <0>; 594 power-domains = <&CLUSTER_PD>; 595 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 596 }; 597 598 CPU_PD4: power-domain-cpu4 { 599 #power-domain-cells = <0>; 600 power-domains = <&CLUSTER_PD>; 601 domain-idle-states = <&BIG_CPU_SLEEP_0>; 602 }; 603 604 CPU_PD5: power-domain-cpu5 { 605 #power-domain-cells = <0>; 606 power-domains = <&CLUSTER_PD>; 607 domain-idle-states = <&BIG_CPU_SLEEP_0>; 608 }; 609 610 CPU_PD6: power-domain-cpu6 { 611 #power-domain-cells = <0>; 612 power-domains = <&CLUSTER_PD>; 613 domain-idle-states = <&BIG_CPU_SLEEP_0>; 614 }; 615 616 CPU_PD7: power-domain-cpu7 { 617 #power-domain-cells = <0>; 618 power-domains = <&CLUSTER_PD>; 619 domain-idle-states = <&BIG_CPU_SLEEP_0>; 620 }; 621 622 CLUSTER_PD: power-domain-cpu-cluster0 { 623 #power-domain-cells = <0>; 624 domain-idle-states = <&CLUSTER_SLEEP_0>; 625 }; 626 }; 627 628 reserved-memory { 629 #address-cells = <2>; 630 #size-cells = <2>; 631 ranges; 632 633 reserved-region@80000000 { 634 reg = <0 0x80000000 0 0x860000>; 635 no-map; 636 }; 637 638 cmd_db: cmd-db-region@80860000 { 639 compatible = "qcom,cmd-db"; 640 reg = <0 0x80860000 0 0x20000>; 641 no-map; 642 }; 643 644 reserved-region@80880000 { 645 reg = <0 0x80880000 0 0x80000>; 646 no-map; 647 }; 648 649 smem_mem: smem-region@80900000 { 650 compatible = "qcom,smem"; 651 reg = <0 0x80900000 0 0x200000>; 652 no-map; 653 hwlocks = <&tcsr_mutex 3>; 654 }; 655 656 reserved-region@80b00000 { 657 reg = <0 0x80b00000 0 0x100000>; 658 no-map; 659 }; 660 661 reserved-region@83b00000 { 662 reg = <0 0x83b00000 0 0x1700000>; 663 no-map; 664 }; 665 666 reserved-region@85b00000 { 667 reg = <0 0x85b00000 0 0xc00000>; 668 no-map; 669 }; 670 671 pil_adsp_mem: adsp-region@86c00000 { 672 reg = <0 0x86c00000 0 0x2000000>; 673 no-map; 674 }; 675 676 pil_nsp0_mem: cdsp0-region@8a100000 { 677 reg = <0 0x8a100000 0 0x1e00000>; 678 no-map; 679 }; 680 681 pil_nsp1_mem: cdsp1-region@8c600000 { 682 reg = <0 0x8c600000 0 0x1e00000>; 683 no-map; 684 }; 685 686 reserved-region@aeb00000 { 687 reg = <0 0xaeb00000 0 0x16600000>; 688 no-map; 689 }; 690 }; 691 692 smp2p-adsp { 693 compatible = "qcom,smp2p"; 694 qcom,smem = <443>, <429>; 695 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 696 IPCC_MPROC_SIGNAL_SMP2P 697 IRQ_TYPE_EDGE_RISING>; 698 mboxes = <&ipcc IPCC_CLIENT_LPASS 699 IPCC_MPROC_SIGNAL_SMP2P>; 700 701 qcom,local-pid = <0>; 702 qcom,remote-pid = <2>; 703 704 smp2p_adsp_out: master-kernel { 705 qcom,entry-name = "master-kernel"; 706 #qcom,smem-state-cells = <1>; 707 }; 708 709 smp2p_adsp_in: slave-kernel { 710 qcom,entry-name = "slave-kernel"; 711 interrupt-controller; 712 #interrupt-cells = <2>; 713 }; 714 }; 715 716 smp2p-nsp0 { 717 compatible = "qcom,smp2p"; 718 qcom,smem = <94>, <432>; 719 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 720 IPCC_MPROC_SIGNAL_SMP2P 721 IRQ_TYPE_EDGE_RISING>; 722 mboxes = <&ipcc IPCC_CLIENT_CDSP 723 IPCC_MPROC_SIGNAL_SMP2P>; 724 725 qcom,local-pid = <0>; 726 qcom,remote-pid = <5>; 727 728 smp2p_nsp0_out: master-kernel { 729 qcom,entry-name = "master-kernel"; 730 #qcom,smem-state-cells = <1>; 731 }; 732 733 smp2p_nsp0_in: slave-kernel { 734 qcom,entry-name = "slave-kernel"; 735 interrupt-controller; 736 #interrupt-cells = <2>; 737 }; 738 }; 739 740 smp2p-nsp1 { 741 compatible = "qcom,smp2p"; 742 qcom,smem = <617>, <616>; 743 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1 744 IPCC_MPROC_SIGNAL_SMP2P 745 IRQ_TYPE_EDGE_RISING>; 746 mboxes = <&ipcc IPCC_CLIENT_NSP1 747 IPCC_MPROC_SIGNAL_SMP2P>; 748 749 qcom,local-pid = <0>; 750 qcom,remote-pid = <12>; 751 752 smp2p_nsp1_out: master-kernel { 753 qcom,entry-name = "master-kernel"; 754 #qcom,smem-state-cells = <1>; 755 }; 756 757 smp2p_nsp1_in: slave-kernel { 758 qcom,entry-name = "slave-kernel"; 759 interrupt-controller; 760 #interrupt-cells = <2>; 761 }; 762 }; 763 764 soc: soc@0 { 765 compatible = "simple-bus"; 766 #address-cells = <2>; 767 #size-cells = <2>; 768 ranges = <0 0 0 0 0x10 0>; 769 dma-ranges = <0 0 0 0 0x10 0>; 770 771 ethernet0: ethernet@20000 { 772 compatible = "qcom,sc8280xp-ethqos"; 773 reg = <0x0 0x00020000 0x0 0x10000>, 774 <0x0 0x00036000 0x0 0x100>; 775 reg-names = "stmmaceth", "rgmii"; 776 777 clocks = <&gcc GCC_EMAC0_AXI_CLK>, 778 <&gcc GCC_EMAC0_SLV_AHB_CLK>, 779 <&gcc GCC_EMAC0_PTP_CLK>, 780 <&gcc GCC_EMAC0_RGMII_CLK>; 781 clock-names = "stmmaceth", 782 "pclk", 783 "ptp_ref", 784 "rgmii"; 785 786 interrupts = <GIC_SPI 946 IRQ_TYPE_LEVEL_HIGH>, 787 <GIC_SPI 936 IRQ_TYPE_LEVEL_HIGH>; 788 interrupt-names = "macirq", "eth_lpi"; 789 790 iommus = <&apps_smmu 0x4c0 0xf>; 791 power-domains = <&gcc EMAC_0_GDSC>; 792 793 snps,tso; 794 snps,pbl = <32>; 795 rx-fifo-depth = <4096>; 796 tx-fifo-depth = <4096>; 797 798 status = "disabled"; 799 }; 800 801 gcc: clock-controller@100000 { 802 compatible = "qcom,gcc-sc8280xp"; 803 reg = <0x0 0x00100000 0x0 0x1f0000>; 804 #clock-cells = <1>; 805 #reset-cells = <1>; 806 #power-domain-cells = <1>; 807 clocks = <&rpmhcc RPMH_CXO_CLK>, 808 <&sleep_clk>, 809 <0>, 810 <0>, 811 <0>, 812 <0>, 813 <0>, 814 <0>, 815 <&usb_0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 816 <0>, 817 <0>, 818 <0>, 819 <0>, 820 <0>, 821 <0>, 822 <0>, 823 <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 824 <0>, 825 <0>, 826 <0>, 827 <0>, 828 <0>, 829 <0>, 830 <0>, 831 <0>, 832 <0>, 833 <&pcie2a_phy>, 834 <&pcie2b_phy>, 835 <&pcie3a_phy>, 836 <&pcie3b_phy>, 837 <&pcie4_phy>, 838 <0>, 839 <0>; 840 power-domains = <&rpmhpd SC8280XP_CX>; 841 }; 842 843 ipcc: mailbox@408000 { 844 compatible = "qcom,sc8280xp-ipcc", "qcom,ipcc"; 845 reg = <0 0x00408000 0 0x1000>; 846 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 847 interrupt-controller; 848 #interrupt-cells = <3>; 849 #mbox-cells = <2>; 850 }; 851 852 qup2: geniqup@8c0000 { 853 compatible = "qcom,geni-se-qup"; 854 reg = <0 0x008c0000 0 0x2000>; 855 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 856 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 857 clock-names = "m-ahb", "s-ahb"; 858 iommus = <&apps_smmu 0xa3 0>; 859 860 #address-cells = <2>; 861 #size-cells = <2>; 862 ranges; 863 864 status = "disabled"; 865 866 i2c16: i2c@880000 { 867 compatible = "qcom,geni-i2c"; 868 reg = <0 0x00880000 0 0x4000>; 869 #address-cells = <1>; 870 #size-cells = <0>; 871 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 872 clock-names = "se"; 873 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 874 power-domains = <&rpmhpd SC8280XP_CX>; 875 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 876 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 877 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 878 interconnect-names = "qup-core", "qup-config", "qup-memory"; 879 status = "disabled"; 880 }; 881 882 spi16: spi@880000 { 883 compatible = "qcom,geni-spi"; 884 reg = <0 0x00880000 0 0x4000>; 885 #address-cells = <1>; 886 #size-cells = <0>; 887 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 888 clock-names = "se"; 889 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 890 power-domains = <&rpmhpd SC8280XP_CX>; 891 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 892 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 893 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 894 interconnect-names = "qup-core", "qup-config", "qup-memory"; 895 status = "disabled"; 896 }; 897 898 i2c17: i2c@884000 { 899 compatible = "qcom,geni-i2c"; 900 reg = <0 0x00884000 0 0x4000>; 901 #address-cells = <1>; 902 #size-cells = <0>; 903 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 904 clock-names = "se"; 905 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 906 power-domains = <&rpmhpd SC8280XP_CX>; 907 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 908 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 909 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 910 interconnect-names = "qup-core", "qup-config", "qup-memory"; 911 status = "disabled"; 912 }; 913 914 spi17: spi@884000 { 915 compatible = "qcom,geni-spi"; 916 reg = <0 0x00884000 0 0x4000>; 917 #address-cells = <1>; 918 #size-cells = <0>; 919 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 920 clock-names = "se"; 921 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 922 power-domains = <&rpmhpd SC8280XP_CX>; 923 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 924 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 925 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 926 interconnect-names = "qup-core", "qup-config", "qup-memory"; 927 status = "disabled"; 928 }; 929 930 uart17: serial@884000 { 931 compatible = "qcom,geni-uart"; 932 reg = <0 0x00884000 0 0x4000>; 933 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 934 clock-names = "se"; 935 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 936 operating-points-v2 = <&qup_opp_table_100mhz>; 937 power-domains = <&rpmhpd SC8280XP_CX>; 938 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 939 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>; 940 interconnect-names = "qup-core", "qup-config"; 941 status = "disabled"; 942 }; 943 944 i2c18: i2c@888000 { 945 compatible = "qcom,geni-i2c"; 946 reg = <0 0x00888000 0 0x4000>; 947 #address-cells = <1>; 948 #size-cells = <0>; 949 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 950 clock-names = "se"; 951 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 952 power-domains = <&rpmhpd SC8280XP_CX>; 953 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 954 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 955 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 956 interconnect-names = "qup-core", "qup-config", "qup-memory"; 957 status = "disabled"; 958 }; 959 960 spi18: spi@888000 { 961 compatible = "qcom,geni-spi"; 962 reg = <0 0x00888000 0 0x4000>; 963 #address-cells = <1>; 964 #size-cells = <0>; 965 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 966 clock-names = "se"; 967 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 968 power-domains = <&rpmhpd SC8280XP_CX>; 969 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 970 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 971 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 972 interconnect-names = "qup-core", "qup-config", "qup-memory"; 973 status = "disabled"; 974 }; 975 976 i2c19: i2c@88c000 { 977 compatible = "qcom,geni-i2c"; 978 reg = <0 0x0088c000 0 0x4000>; 979 #address-cells = <1>; 980 #size-cells = <0>; 981 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 982 clock-names = "se"; 983 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 984 power-domains = <&rpmhpd SC8280XP_CX>; 985 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 986 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 987 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 988 interconnect-names = "qup-core", "qup-config", "qup-memory"; 989 status = "disabled"; 990 }; 991 992 spi19: spi@88c000 { 993 compatible = "qcom,geni-spi"; 994 reg = <0 0x0088c000 0 0x4000>; 995 #address-cells = <1>; 996 #size-cells = <0>; 997 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 998 clock-names = "se"; 999 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1000 power-domains = <&rpmhpd SC8280XP_CX>; 1001 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1002 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1003 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1004 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1005 status = "disabled"; 1006 }; 1007 1008 i2c20: i2c@890000 { 1009 compatible = "qcom,geni-i2c"; 1010 reg = <0 0x00890000 0 0x4000>; 1011 #address-cells = <1>; 1012 #size-cells = <0>; 1013 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1014 clock-names = "se"; 1015 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1016 power-domains = <&rpmhpd SC8280XP_CX>; 1017 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1018 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1019 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1020 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1021 status = "disabled"; 1022 }; 1023 1024 spi20: spi@890000 { 1025 compatible = "qcom,geni-spi"; 1026 reg = <0 0x00890000 0 0x4000>; 1027 #address-cells = <1>; 1028 #size-cells = <0>; 1029 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1030 clock-names = "se"; 1031 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1032 power-domains = <&rpmhpd SC8280XP_CX>; 1033 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1034 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1035 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1036 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1037 status = "disabled"; 1038 }; 1039 1040 i2c21: i2c@894000 { 1041 compatible = "qcom,geni-i2c"; 1042 reg = <0 0x00894000 0 0x4000>; 1043 clock-names = "se"; 1044 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1045 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1046 #address-cells = <1>; 1047 #size-cells = <0>; 1048 power-domains = <&rpmhpd SC8280XP_CX>; 1049 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1050 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1051 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1052 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1053 status = "disabled"; 1054 }; 1055 1056 spi21: spi@894000 { 1057 compatible = "qcom,geni-spi"; 1058 reg = <0 0x00894000 0 0x4000>; 1059 #address-cells = <1>; 1060 #size-cells = <0>; 1061 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1062 clock-names = "se"; 1063 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1064 power-domains = <&rpmhpd SC8280XP_CX>; 1065 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1066 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1067 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1068 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1069 status = "disabled"; 1070 }; 1071 1072 i2c22: i2c@898000 { 1073 compatible = "qcom,geni-i2c"; 1074 reg = <0 0x00898000 0 0x4000>; 1075 #address-cells = <1>; 1076 #size-cells = <0>; 1077 clock-names = "se"; 1078 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1079 interrupts = <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>; 1080 power-domains = <&rpmhpd SC8280XP_CX>; 1081 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1082 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1083 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1084 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1085 status = "disabled"; 1086 }; 1087 1088 spi22: spi@898000 { 1089 compatible = "qcom,geni-spi"; 1090 reg = <0 0x00898000 0 0x4000>; 1091 #address-cells = <1>; 1092 #size-cells = <0>; 1093 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1094 clock-names = "se"; 1095 interrupts = <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>; 1096 power-domains = <&rpmhpd SC8280XP_CX>; 1097 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1098 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1099 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1100 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1101 status = "disabled"; 1102 }; 1103 1104 i2c23: i2c@89c000 { 1105 compatible = "qcom,geni-i2c"; 1106 reg = <0 0x0089c000 0 0x4000>; 1107 #address-cells = <1>; 1108 #size-cells = <0>; 1109 clock-names = "se"; 1110 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1111 interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>; 1112 power-domains = <&rpmhpd SC8280XP_CX>; 1113 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1114 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1115 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1116 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1117 status = "disabled"; 1118 }; 1119 1120 spi23: spi@89c000 { 1121 compatible = "qcom,geni-spi"; 1122 reg = <0 0x0089c000 0 0x4000>; 1123 #address-cells = <1>; 1124 #size-cells = <0>; 1125 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1126 clock-names = "se"; 1127 interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>; 1128 power-domains = <&rpmhpd SC8280XP_CX>; 1129 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1130 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1131 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1132 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1133 status = "disabled"; 1134 }; 1135 }; 1136 1137 qup0: geniqup@9c0000 { 1138 compatible = "qcom,geni-se-qup"; 1139 reg = <0 0x009c0000 0 0x6000>; 1140 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1141 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1142 clock-names = "m-ahb", "s-ahb"; 1143 iommus = <&apps_smmu 0x563 0>; 1144 1145 #address-cells = <2>; 1146 #size-cells = <2>; 1147 ranges; 1148 1149 status = "disabled"; 1150 1151 i2c0: i2c@980000 { 1152 compatible = "qcom,geni-i2c"; 1153 reg = <0 0x00980000 0 0x4000>; 1154 #address-cells = <1>; 1155 #size-cells = <0>; 1156 clock-names = "se"; 1157 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1158 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1159 power-domains = <&rpmhpd SC8280XP_CX>; 1160 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1161 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1162 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1163 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1164 status = "disabled"; 1165 }; 1166 1167 spi0: spi@980000 { 1168 compatible = "qcom,geni-spi"; 1169 reg = <0 0x00980000 0 0x4000>; 1170 #address-cells = <1>; 1171 #size-cells = <0>; 1172 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1173 clock-names = "se"; 1174 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1175 power-domains = <&rpmhpd SC8280XP_CX>; 1176 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1177 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1178 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1179 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1180 status = "disabled"; 1181 }; 1182 1183 i2c1: i2c@984000 { 1184 compatible = "qcom,geni-i2c"; 1185 reg = <0 0x00984000 0 0x4000>; 1186 #address-cells = <1>; 1187 #size-cells = <0>; 1188 clock-names = "se"; 1189 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1190 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1191 power-domains = <&rpmhpd SC8280XP_CX>; 1192 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1193 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1194 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1195 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1196 status = "disabled"; 1197 }; 1198 1199 spi1: spi@984000 { 1200 compatible = "qcom,geni-spi"; 1201 reg = <0 0x00984000 0 0x4000>; 1202 #address-cells = <1>; 1203 #size-cells = <0>; 1204 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1205 clock-names = "se"; 1206 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1207 power-domains = <&rpmhpd SC8280XP_CX>; 1208 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1209 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1210 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1211 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1212 status = "disabled"; 1213 }; 1214 1215 i2c2: i2c@988000 { 1216 compatible = "qcom,geni-i2c"; 1217 reg = <0 0x00988000 0 0x4000>; 1218 #address-cells = <1>; 1219 #size-cells = <0>; 1220 clock-names = "se"; 1221 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1222 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1223 power-domains = <&rpmhpd SC8280XP_CX>; 1224 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1225 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1226 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1227 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1228 status = "disabled"; 1229 }; 1230 1231 spi2: spi@988000 { 1232 compatible = "qcom,geni-spi"; 1233 reg = <0 0x00988000 0 0x4000>; 1234 #address-cells = <1>; 1235 #size-cells = <0>; 1236 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1237 clock-names = "se"; 1238 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1239 power-domains = <&rpmhpd SC8280XP_CX>; 1240 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1241 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1242 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1243 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1244 status = "disabled"; 1245 }; 1246 1247 uart2: serial@988000 { 1248 compatible = "qcom,geni-uart"; 1249 reg = <0 0x00988000 0 0x4000>; 1250 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1251 clock-names = "se"; 1252 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1253 operating-points-v2 = <&qup_opp_table_100mhz>; 1254 power-domains = <&rpmhpd SC8280XP_CX>; 1255 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1256 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 1257 interconnect-names = "qup-core", "qup-config"; 1258 status = "disabled"; 1259 }; 1260 1261 i2c3: i2c@98c000 { 1262 compatible = "qcom,geni-i2c"; 1263 reg = <0 0x0098c000 0 0x4000>; 1264 #address-cells = <1>; 1265 #size-cells = <0>; 1266 clock-names = "se"; 1267 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1268 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1269 power-domains = <&rpmhpd SC8280XP_CX>; 1270 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1271 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1272 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1273 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1274 status = "disabled"; 1275 }; 1276 1277 spi3: spi@98c000 { 1278 compatible = "qcom,geni-spi"; 1279 reg = <0 0x0098c000 0 0x4000>; 1280 #address-cells = <1>; 1281 #size-cells = <0>; 1282 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1283 clock-names = "se"; 1284 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1285 power-domains = <&rpmhpd SC8280XP_CX>; 1286 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1287 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1288 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1289 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1290 status = "disabled"; 1291 }; 1292 1293 i2c4: i2c@990000 { 1294 compatible = "qcom,geni-i2c"; 1295 reg = <0 0x00990000 0 0x4000>; 1296 clock-names = "se"; 1297 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1298 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1299 #address-cells = <1>; 1300 #size-cells = <0>; 1301 power-domains = <&rpmhpd SC8280XP_CX>; 1302 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1303 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1304 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1305 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1306 status = "disabled"; 1307 }; 1308 1309 spi4: spi@990000 { 1310 compatible = "qcom,geni-spi"; 1311 reg = <0 0x00990000 0 0x4000>; 1312 #address-cells = <1>; 1313 #size-cells = <0>; 1314 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1315 clock-names = "se"; 1316 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1317 power-domains = <&rpmhpd SC8280XP_CX>; 1318 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1319 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1320 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1321 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1322 status = "disabled"; 1323 }; 1324 1325 i2c5: i2c@994000 { 1326 compatible = "qcom,geni-i2c"; 1327 reg = <0 0x00994000 0 0x4000>; 1328 #address-cells = <1>; 1329 #size-cells = <0>; 1330 clock-names = "se"; 1331 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1332 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1333 power-domains = <&rpmhpd SC8280XP_CX>; 1334 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1335 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1336 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1337 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1338 status = "disabled"; 1339 }; 1340 1341 spi5: spi@994000 { 1342 compatible = "qcom,geni-spi"; 1343 reg = <0 0x00994000 0 0x4000>; 1344 #address-cells = <1>; 1345 #size-cells = <0>; 1346 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1347 clock-names = "se"; 1348 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1349 power-domains = <&rpmhpd SC8280XP_CX>; 1350 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1351 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1352 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1353 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1354 status = "disabled"; 1355 }; 1356 1357 i2c6: i2c@998000 { 1358 compatible = "qcom,geni-i2c"; 1359 reg = <0 0x00998000 0 0x4000>; 1360 #address-cells = <1>; 1361 #size-cells = <0>; 1362 clock-names = "se"; 1363 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1364 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1365 power-domains = <&rpmhpd SC8280XP_CX>; 1366 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1367 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1368 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1369 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1370 status = "disabled"; 1371 }; 1372 1373 spi6: spi@998000 { 1374 compatible = "qcom,geni-spi"; 1375 reg = <0 0x00998000 0 0x4000>; 1376 #address-cells = <1>; 1377 #size-cells = <0>; 1378 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1379 clock-names = "se"; 1380 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1381 power-domains = <&rpmhpd SC8280XP_CX>; 1382 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1383 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1384 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1385 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1386 status = "disabled"; 1387 }; 1388 1389 i2c7: i2c@99c000 { 1390 compatible = "qcom,geni-i2c"; 1391 reg = <0 0x0099c000 0 0x4000>; 1392 #address-cells = <1>; 1393 #size-cells = <0>; 1394 clock-names = "se"; 1395 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1396 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1397 power-domains = <&rpmhpd SC8280XP_CX>; 1398 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1399 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1400 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1401 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1402 status = "disabled"; 1403 }; 1404 1405 spi7: spi@99c000 { 1406 compatible = "qcom,geni-spi"; 1407 reg = <0 0x0099c000 0 0x4000>; 1408 #address-cells = <1>; 1409 #size-cells = <0>; 1410 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1411 clock-names = "se"; 1412 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1413 power-domains = <&rpmhpd SC8280XP_CX>; 1414 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1415 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1416 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1417 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1418 status = "disabled"; 1419 }; 1420 }; 1421 1422 qup1: geniqup@ac0000 { 1423 compatible = "qcom,geni-se-qup"; 1424 reg = <0 0x00ac0000 0 0x6000>; 1425 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1426 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1427 clock-names = "m-ahb", "s-ahb"; 1428 iommus = <&apps_smmu 0x83 0>; 1429 1430 #address-cells = <2>; 1431 #size-cells = <2>; 1432 ranges; 1433 1434 status = "disabled"; 1435 1436 i2c8: i2c@a80000 { 1437 compatible = "qcom,geni-i2c"; 1438 reg = <0 0x00a80000 0 0x4000>; 1439 #address-cells = <1>; 1440 #size-cells = <0>; 1441 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1442 clock-names = "se"; 1443 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1444 power-domains = <&rpmhpd SC8280XP_CX>; 1445 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1446 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1447 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1448 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1449 status = "disabled"; 1450 }; 1451 1452 spi8: spi@a80000 { 1453 compatible = "qcom,geni-spi"; 1454 reg = <0 0x00a80000 0 0x4000>; 1455 #address-cells = <1>; 1456 #size-cells = <0>; 1457 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1458 clock-names = "se"; 1459 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1460 power-domains = <&rpmhpd SC8280XP_CX>; 1461 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1462 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1463 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1464 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1465 status = "disabled"; 1466 }; 1467 1468 i2c9: i2c@a84000 { 1469 compatible = "qcom,geni-i2c"; 1470 reg = <0 0x00a84000 0 0x4000>; 1471 #address-cells = <1>; 1472 #size-cells = <0>; 1473 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1474 clock-names = "se"; 1475 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1476 power-domains = <&rpmhpd SC8280XP_CX>; 1477 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1478 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1479 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1480 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1481 status = "disabled"; 1482 }; 1483 1484 spi9: spi@a84000 { 1485 compatible = "qcom,geni-spi"; 1486 reg = <0 0x00a84000 0 0x4000>; 1487 #address-cells = <1>; 1488 #size-cells = <0>; 1489 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1490 clock-names = "se"; 1491 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1492 power-domains = <&rpmhpd SC8280XP_CX>; 1493 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1494 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1495 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1496 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1497 status = "disabled"; 1498 }; 1499 1500 i2c10: i2c@a88000 { 1501 compatible = "qcom,geni-i2c"; 1502 reg = <0 0x00a88000 0 0x4000>; 1503 #address-cells = <1>; 1504 #size-cells = <0>; 1505 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1506 clock-names = "se"; 1507 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1508 power-domains = <&rpmhpd SC8280XP_CX>; 1509 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1510 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1511 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1512 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1513 status = "disabled"; 1514 }; 1515 1516 spi10: spi@a88000 { 1517 compatible = "qcom,geni-spi"; 1518 reg = <0 0x00a88000 0 0x4000>; 1519 #address-cells = <1>; 1520 #size-cells = <0>; 1521 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1522 clock-names = "se"; 1523 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1524 power-domains = <&rpmhpd SC8280XP_CX>; 1525 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1526 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1527 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1528 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1529 status = "disabled"; 1530 }; 1531 1532 i2c11: i2c@a8c000 { 1533 compatible = "qcom,geni-i2c"; 1534 reg = <0 0x00a8c000 0 0x4000>; 1535 #address-cells = <1>; 1536 #size-cells = <0>; 1537 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1538 clock-names = "se"; 1539 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1540 power-domains = <&rpmhpd SC8280XP_CX>; 1541 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1542 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1543 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1544 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1545 status = "disabled"; 1546 }; 1547 1548 spi11: spi@a8c000 { 1549 compatible = "qcom,geni-spi"; 1550 reg = <0 0x00a8c000 0 0x4000>; 1551 #address-cells = <1>; 1552 #size-cells = <0>; 1553 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1554 clock-names = "se"; 1555 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1556 power-domains = <&rpmhpd SC8280XP_CX>; 1557 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1558 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1559 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1560 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1561 status = "disabled"; 1562 }; 1563 1564 i2c12: i2c@a90000 { 1565 compatible = "qcom,geni-i2c"; 1566 reg = <0 0x00a90000 0 0x4000>; 1567 #address-cells = <1>; 1568 #size-cells = <0>; 1569 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1570 clock-names = "se"; 1571 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1572 power-domains = <&rpmhpd SC8280XP_CX>; 1573 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1574 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1575 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1576 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1577 status = "disabled"; 1578 }; 1579 1580 spi12: spi@a90000 { 1581 compatible = "qcom,geni-spi"; 1582 reg = <0 0x00a90000 0 0x4000>; 1583 #address-cells = <1>; 1584 #size-cells = <0>; 1585 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1586 clock-names = "se"; 1587 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1588 power-domains = <&rpmhpd SC8280XP_CX>; 1589 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1590 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1591 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1592 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1593 status = "disabled"; 1594 }; 1595 1596 i2c13: i2c@a94000 { 1597 compatible = "qcom,geni-i2c"; 1598 reg = <0 0x00a94000 0 0x4000>; 1599 #address-cells = <1>; 1600 #size-cells = <0>; 1601 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1602 clock-names = "se"; 1603 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1604 power-domains = <&rpmhpd SC8280XP_CX>; 1605 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1606 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1607 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1608 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1609 status = "disabled"; 1610 }; 1611 1612 spi13: spi@a94000 { 1613 compatible = "qcom,geni-spi"; 1614 reg = <0 0x00a94000 0 0x4000>; 1615 #address-cells = <1>; 1616 #size-cells = <0>; 1617 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1618 clock-names = "se"; 1619 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1620 power-domains = <&rpmhpd SC8280XP_CX>; 1621 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1622 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1623 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1624 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1625 status = "disabled"; 1626 }; 1627 1628 i2c14: i2c@a98000 { 1629 compatible = "qcom,geni-i2c"; 1630 reg = <0 0x00a98000 0 0x4000>; 1631 #address-cells = <1>; 1632 #size-cells = <0>; 1633 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1634 clock-names = "se"; 1635 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>; 1636 power-domains = <&rpmhpd SC8280XP_CX>; 1637 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1638 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1639 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1640 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1641 status = "disabled"; 1642 }; 1643 1644 spi14: spi@a98000 { 1645 compatible = "qcom,geni-spi"; 1646 reg = <0 0x00a98000 0 0x4000>; 1647 #address-cells = <1>; 1648 #size-cells = <0>; 1649 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1650 clock-names = "se"; 1651 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>; 1652 power-domains = <&rpmhpd SC8280XP_CX>; 1653 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1654 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1655 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1656 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1657 status = "disabled"; 1658 }; 1659 1660 i2c15: i2c@a9c000 { 1661 compatible = "qcom,geni-i2c"; 1662 reg = <0 0x00a9c000 0 0x4000>; 1663 #address-cells = <1>; 1664 #size-cells = <0>; 1665 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1666 clock-names = "se"; 1667 interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>; 1668 power-domains = <&rpmhpd SC8280XP_CX>; 1669 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1670 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1671 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1672 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1673 status = "disabled"; 1674 }; 1675 1676 spi15: spi@a9c000 { 1677 compatible = "qcom,geni-spi"; 1678 reg = <0 0x00a9c000 0 0x4000>; 1679 #address-cells = <1>; 1680 #size-cells = <0>; 1681 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1682 clock-names = "se"; 1683 interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>; 1684 power-domains = <&rpmhpd SC8280XP_CX>; 1685 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1686 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1687 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1688 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1689 status = "disabled"; 1690 }; 1691 }; 1692 1693 rng: rng@10d3000 { 1694 compatible = "qcom,prng-ee"; 1695 reg = <0 0x010d3000 0 0x1000>; 1696 clocks = <&rpmhcc RPMH_HWKM_CLK>; 1697 clock-names = "core"; 1698 }; 1699 1700 pcie4: pcie@1c00000 { 1701 device_type = "pci"; 1702 compatible = "qcom,pcie-sc8280xp"; 1703 reg = <0x0 0x01c00000 0x0 0x3000>, 1704 <0x0 0x30000000 0x0 0xf1d>, 1705 <0x0 0x30000f20 0x0 0xa8>, 1706 <0x0 0x30001000 0x0 0x1000>, 1707 <0x0 0x30100000 0x0 0x100000>, 1708 <0x0 0x01c03000 0x0 0x1000>; 1709 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 1710 #address-cells = <3>; 1711 #size-cells = <2>; 1712 ranges = <0x01000000 0x0 0x00000000 0x0 0x30200000 0x0 0x100000>, 1713 <0x02000000 0x0 0x30300000 0x0 0x30300000 0x0 0x1d00000>; 1714 bus-range = <0x00 0xff>; 1715 1716 dma-coherent; 1717 1718 linux,pci-domain = <6>; 1719 num-lanes = <1>; 1720 1721 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 1722 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1723 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 1724 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 1725 interrupt-names = "msi0", "msi1", "msi2", "msi3"; 1726 1727 #interrupt-cells = <1>; 1728 interrupt-map-mask = <0 0 0 0x7>; 1729 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 1730 <0 0 0 2 &intc 0 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 1731 <0 0 0 3 &intc 0 0 GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 1732 <0 0 0 4 &intc 0 0 GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 1733 1734 clocks = <&gcc GCC_PCIE_4_AUX_CLK>, 1735 <&gcc GCC_PCIE_4_CFG_AHB_CLK>, 1736 <&gcc GCC_PCIE_4_MSTR_AXI_CLK>, 1737 <&gcc GCC_PCIE_4_SLV_AXI_CLK>, 1738 <&gcc GCC_PCIE_4_SLV_Q2A_AXI_CLK>, 1739 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 1740 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, 1741 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>, 1742 <&gcc GCC_CNOC_PCIE4_QX_CLK>; 1743 clock-names = "aux", 1744 "cfg", 1745 "bus_master", 1746 "bus_slave", 1747 "slave_q2a", 1748 "ddrss_sf_tbu", 1749 "noc_aggr_4", 1750 "noc_aggr_south_sf", 1751 "cnoc_qx"; 1752 1753 assigned-clocks = <&gcc GCC_PCIE_4_AUX_CLK>; 1754 assigned-clock-rates = <19200000>; 1755 1756 interconnects = <&aggre2_noc MASTER_PCIE_4 0 &mc_virt SLAVE_EBI1 0>, 1757 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_4 0>; 1758 interconnect-names = "pcie-mem", "cpu-pcie"; 1759 1760 resets = <&gcc GCC_PCIE_4_BCR>; 1761 reset-names = "pci"; 1762 1763 power-domains = <&gcc PCIE_4_GDSC>; 1764 1765 phys = <&pcie4_phy>; 1766 phy-names = "pciephy"; 1767 1768 status = "disabled"; 1769 }; 1770 1771 pcie4_phy: phy@1c06000 { 1772 compatible = "qcom,sc8280xp-qmp-gen3x1-pcie-phy"; 1773 reg = <0x0 0x01c06000 0x0 0x2000>; 1774 1775 clocks = <&gcc GCC_PCIE_4_AUX_CLK>, 1776 <&gcc GCC_PCIE_4_CFG_AHB_CLK>, 1777 <&gcc GCC_PCIE_4_CLKREF_CLK>, 1778 <&gcc GCC_PCIE4_PHY_RCHNG_CLK>, 1779 <&gcc GCC_PCIE_4_PIPE_CLK>, 1780 <&gcc GCC_PCIE_4_PIPEDIV2_CLK>; 1781 clock-names = "aux", "cfg_ahb", "ref", "rchng", 1782 "pipe", "pipediv2"; 1783 1784 assigned-clocks = <&gcc GCC_PCIE4_PHY_RCHNG_CLK>; 1785 assigned-clock-rates = <100000000>; 1786 1787 power-domains = <&gcc PCIE_4_GDSC>; 1788 1789 resets = <&gcc GCC_PCIE_4_PHY_BCR>; 1790 reset-names = "phy"; 1791 1792 #clock-cells = <0>; 1793 clock-output-names = "pcie_4_pipe_clk"; 1794 1795 #phy-cells = <0>; 1796 1797 status = "disabled"; 1798 }; 1799 1800 pcie3b: pcie@1c08000 { 1801 device_type = "pci"; 1802 compatible = "qcom,pcie-sc8280xp"; 1803 reg = <0x0 0x01c08000 0x0 0x3000>, 1804 <0x0 0x32000000 0x0 0xf1d>, 1805 <0x0 0x32000f20 0x0 0xa8>, 1806 <0x0 0x32001000 0x0 0x1000>, 1807 <0x0 0x32100000 0x0 0x100000>, 1808 <0x0 0x01c0b000 0x0 0x1000>; 1809 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 1810 #address-cells = <3>; 1811 #size-cells = <2>; 1812 ranges = <0x01000000 0x0 0x00000000 0x0 0x32200000 0x0 0x100000>, 1813 <0x02000000 0x0 0x32300000 0x0 0x32300000 0x0 0x1d00000>; 1814 bus-range = <0x00 0xff>; 1815 1816 dma-coherent; 1817 1818 linux,pci-domain = <5>; 1819 num-lanes = <2>; 1820 1821 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1822 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1823 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1824 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 1825 interrupt-names = "msi0", "msi1", "msi2", "msi3"; 1826 1827 #interrupt-cells = <1>; 1828 interrupt-map-mask = <0 0 0 0x7>; 1829 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 526 IRQ_TYPE_LEVEL_HIGH>, 1830 <0 0 0 2 &intc 0 0 GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>, 1831 <0 0 0 3 &intc 0 0 GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH>, 1832 <0 0 0 4 &intc 0 0 GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>; 1833 1834 clocks = <&gcc GCC_PCIE_3B_AUX_CLK>, 1835 <&gcc GCC_PCIE_3B_CFG_AHB_CLK>, 1836 <&gcc GCC_PCIE_3B_MSTR_AXI_CLK>, 1837 <&gcc GCC_PCIE_3B_SLV_AXI_CLK>, 1838 <&gcc GCC_PCIE_3B_SLV_Q2A_AXI_CLK>, 1839 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 1840 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, 1841 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>; 1842 clock-names = "aux", 1843 "cfg", 1844 "bus_master", 1845 "bus_slave", 1846 "slave_q2a", 1847 "ddrss_sf_tbu", 1848 "noc_aggr_4", 1849 "noc_aggr_south_sf"; 1850 1851 assigned-clocks = <&gcc GCC_PCIE_3B_AUX_CLK>; 1852 assigned-clock-rates = <19200000>; 1853 1854 interconnects = <&aggre2_noc MASTER_PCIE_3B 0 &mc_virt SLAVE_EBI1 0>, 1855 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_3B 0>; 1856 interconnect-names = "pcie-mem", "cpu-pcie"; 1857 1858 resets = <&gcc GCC_PCIE_3B_BCR>; 1859 reset-names = "pci"; 1860 1861 power-domains = <&gcc PCIE_3B_GDSC>; 1862 1863 phys = <&pcie3b_phy>; 1864 phy-names = "pciephy"; 1865 1866 status = "disabled"; 1867 }; 1868 1869 pcie3b_phy: phy@1c0e000 { 1870 compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy"; 1871 reg = <0x0 0x01c0e000 0x0 0x2000>; 1872 1873 clocks = <&gcc GCC_PCIE_3B_AUX_CLK>, 1874 <&gcc GCC_PCIE_3B_CFG_AHB_CLK>, 1875 <&gcc GCC_PCIE_3A3B_CLKREF_CLK>, 1876 <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>, 1877 <&gcc GCC_PCIE_3B_PIPE_CLK>, 1878 <&gcc GCC_PCIE_3B_PIPEDIV2_CLK>; 1879 clock-names = "aux", "cfg_ahb", "ref", "rchng", 1880 "pipe", "pipediv2"; 1881 1882 assigned-clocks = <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>; 1883 assigned-clock-rates = <100000000>; 1884 1885 power-domains = <&gcc PCIE_3B_GDSC>; 1886 1887 resets = <&gcc GCC_PCIE_3B_PHY_BCR>; 1888 reset-names = "phy"; 1889 1890 #clock-cells = <0>; 1891 clock-output-names = "pcie_3b_pipe_clk"; 1892 1893 #phy-cells = <0>; 1894 1895 status = "disabled"; 1896 }; 1897 1898 pcie3a: pcie@1c10000 { 1899 device_type = "pci"; 1900 compatible = "qcom,pcie-sc8280xp"; 1901 reg = <0x0 0x01c10000 0x0 0x3000>, 1902 <0x0 0x34000000 0x0 0xf1d>, 1903 <0x0 0x34000f20 0x0 0xa8>, 1904 <0x0 0x34001000 0x0 0x1000>, 1905 <0x0 0x34100000 0x0 0x100000>, 1906 <0x0 0x01c13000 0x0 0x1000>; 1907 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 1908 #address-cells = <3>; 1909 #size-cells = <2>; 1910 ranges = <0x01000000 0x0 0x00000000 0x0 0x34200000 0x0 0x100000>, 1911 <0x02000000 0x0 0x34300000 0x0 0x34300000 0x0 0x1d00000>; 1912 bus-range = <0x00 0xff>; 1913 1914 dma-coherent; 1915 1916 linux,pci-domain = <4>; 1917 num-lanes = <4>; 1918 1919 interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 1920 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 1921 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 1922 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; 1923 interrupt-names = "msi0", "msi1", "msi2", "msi3"; 1924 1925 #interrupt-cells = <1>; 1926 interrupt-map-mask = <0 0 0 0x7>; 1927 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>, 1928 <0 0 0 2 &intc 0 0 GIC_SPI 542 IRQ_TYPE_LEVEL_HIGH>, 1929 <0 0 0 3 &intc 0 0 GIC_SPI 543 IRQ_TYPE_LEVEL_HIGH>, 1930 <0 0 0 4 &intc 0 0 GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>; 1931 1932 clocks = <&gcc GCC_PCIE_3A_AUX_CLK>, 1933 <&gcc GCC_PCIE_3A_CFG_AHB_CLK>, 1934 <&gcc GCC_PCIE_3A_MSTR_AXI_CLK>, 1935 <&gcc GCC_PCIE_3A_SLV_AXI_CLK>, 1936 <&gcc GCC_PCIE_3A_SLV_Q2A_AXI_CLK>, 1937 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 1938 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, 1939 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>; 1940 clock-names = "aux", 1941 "cfg", 1942 "bus_master", 1943 "bus_slave", 1944 "slave_q2a", 1945 "ddrss_sf_tbu", 1946 "noc_aggr_4", 1947 "noc_aggr_south_sf"; 1948 1949 assigned-clocks = <&gcc GCC_PCIE_3A_AUX_CLK>; 1950 assigned-clock-rates = <19200000>; 1951 1952 interconnects = <&aggre2_noc MASTER_PCIE_3A 0 &mc_virt SLAVE_EBI1 0>, 1953 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_3A 0>; 1954 interconnect-names = "pcie-mem", "cpu-pcie"; 1955 1956 resets = <&gcc GCC_PCIE_3A_BCR>; 1957 reset-names = "pci"; 1958 1959 power-domains = <&gcc PCIE_3A_GDSC>; 1960 1961 phys = <&pcie3a_phy>; 1962 phy-names = "pciephy"; 1963 1964 status = "disabled"; 1965 }; 1966 1967 pcie3a_phy: phy@1c14000 { 1968 compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy"; 1969 reg = <0x0 0x01c14000 0x0 0x2000>, 1970 <0x0 0x01c16000 0x0 0x2000>; 1971 1972 clocks = <&gcc GCC_PCIE_3A_AUX_CLK>, 1973 <&gcc GCC_PCIE_3A_CFG_AHB_CLK>, 1974 <&gcc GCC_PCIE_3A3B_CLKREF_CLK>, 1975 <&gcc GCC_PCIE3A_PHY_RCHNG_CLK>, 1976 <&gcc GCC_PCIE_3A_PIPE_CLK>, 1977 <&gcc GCC_PCIE_3A_PIPEDIV2_CLK>; 1978 clock-names = "aux", "cfg_ahb", "ref", "rchng", 1979 "pipe", "pipediv2"; 1980 1981 assigned-clocks = <&gcc GCC_PCIE3A_PHY_RCHNG_CLK>; 1982 assigned-clock-rates = <100000000>; 1983 1984 power-domains = <&gcc PCIE_3A_GDSC>; 1985 1986 resets = <&gcc GCC_PCIE_3A_PHY_BCR>; 1987 reset-names = "phy"; 1988 1989 qcom,4ln-config-sel = <&tcsr 0xa044 1>; 1990 1991 #clock-cells = <0>; 1992 clock-output-names = "pcie_3a_pipe_clk"; 1993 1994 #phy-cells = <0>; 1995 1996 status = "disabled"; 1997 }; 1998 1999 pcie2b: pcie@1c18000 { 2000 device_type = "pci"; 2001 compatible = "qcom,pcie-sc8280xp"; 2002 reg = <0x0 0x01c18000 0x0 0x3000>, 2003 <0x0 0x38000000 0x0 0xf1d>, 2004 <0x0 0x38000f20 0x0 0xa8>, 2005 <0x0 0x38001000 0x0 0x1000>, 2006 <0x0 0x38100000 0x0 0x100000>, 2007 <0x0 0x01c1b000 0x0 0x1000>; 2008 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 2009 #address-cells = <3>; 2010 #size-cells = <2>; 2011 ranges = <0x01000000 0x0 0x00000000 0x0 0x38200000 0x0 0x100000>, 2012 <0x02000000 0x0 0x38300000 0x0 0x38300000 0x0 0x1d00000>; 2013 bus-range = <0x00 0xff>; 2014 2015 dma-coherent; 2016 2017 linux,pci-domain = <3>; 2018 num-lanes = <2>; 2019 2020 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 2021 <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 2022 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 2023 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>; 2024 interrupt-names = "msi0", "msi1", "msi2", "msi3"; 2025 2026 #interrupt-cells = <1>; 2027 interrupt-map-mask = <0 0 0 0x7>; 2028 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, 2029 <0 0 0 2 &intc 0 0 GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, 2030 <0 0 0 3 &intc 0 0 GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, 2031 <0 0 0 4 &intc 0 0 GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>; 2032 2033 clocks = <&gcc GCC_PCIE_2B_AUX_CLK>, 2034 <&gcc GCC_PCIE_2B_CFG_AHB_CLK>, 2035 <&gcc GCC_PCIE_2B_MSTR_AXI_CLK>, 2036 <&gcc GCC_PCIE_2B_SLV_AXI_CLK>, 2037 <&gcc GCC_PCIE_2B_SLV_Q2A_AXI_CLK>, 2038 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 2039 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, 2040 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>; 2041 clock-names = "aux", 2042 "cfg", 2043 "bus_master", 2044 "bus_slave", 2045 "slave_q2a", 2046 "ddrss_sf_tbu", 2047 "noc_aggr_4", 2048 "noc_aggr_south_sf"; 2049 2050 assigned-clocks = <&gcc GCC_PCIE_2B_AUX_CLK>; 2051 assigned-clock-rates = <19200000>; 2052 2053 interconnects = <&aggre2_noc MASTER_PCIE_2B 0 &mc_virt SLAVE_EBI1 0>, 2054 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_2B 0>; 2055 interconnect-names = "pcie-mem", "cpu-pcie"; 2056 2057 resets = <&gcc GCC_PCIE_2B_BCR>; 2058 reset-names = "pci"; 2059 2060 power-domains = <&gcc PCIE_2B_GDSC>; 2061 2062 phys = <&pcie2b_phy>; 2063 phy-names = "pciephy"; 2064 2065 status = "disabled"; 2066 }; 2067 2068 pcie2b_phy: phy@1c1e000 { 2069 compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy"; 2070 reg = <0x0 0x01c1e000 0x0 0x2000>; 2071 2072 clocks = <&gcc GCC_PCIE_2B_AUX_CLK>, 2073 <&gcc GCC_PCIE_2B_CFG_AHB_CLK>, 2074 <&gcc GCC_PCIE_2A2B_CLKREF_CLK>, 2075 <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>, 2076 <&gcc GCC_PCIE_2B_PIPE_CLK>, 2077 <&gcc GCC_PCIE_2B_PIPEDIV2_CLK>; 2078 clock-names = "aux", "cfg_ahb", "ref", "rchng", 2079 "pipe", "pipediv2"; 2080 2081 assigned-clocks = <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>; 2082 assigned-clock-rates = <100000000>; 2083 2084 power-domains = <&gcc PCIE_2B_GDSC>; 2085 2086 resets = <&gcc GCC_PCIE_2B_PHY_BCR>; 2087 reset-names = "phy"; 2088 2089 #clock-cells = <0>; 2090 clock-output-names = "pcie_2b_pipe_clk"; 2091 2092 #phy-cells = <0>; 2093 2094 status = "disabled"; 2095 }; 2096 2097 pcie2a: pcie@1c20000 { 2098 device_type = "pci"; 2099 compatible = "qcom,pcie-sc8280xp"; 2100 reg = <0x0 0x01c20000 0x0 0x3000>, 2101 <0x0 0x3c000000 0x0 0xf1d>, 2102 <0x0 0x3c000f20 0x0 0xa8>, 2103 <0x0 0x3c001000 0x0 0x1000>, 2104 <0x0 0x3c100000 0x0 0x100000>, 2105 <0x0 0x01c23000 0x0 0x1000>; 2106 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 2107 #address-cells = <3>; 2108 #size-cells = <2>; 2109 ranges = <0x01000000 0x0 0x00000000 0x0 0x3c200000 0x0 0x100000>, 2110 <0x02000000 0x0 0x3c300000 0x0 0x3c300000 0x0 0x1d00000>; 2111 bus-range = <0x00 0xff>; 2112 2113 dma-coherent; 2114 2115 linux,pci-domain = <2>; 2116 num-lanes = <4>; 2117 2118 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 2119 <GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH>, 2120 <GIC_SPI 524 IRQ_TYPE_LEVEL_HIGH>, 2121 <GIC_SPI 525 IRQ_TYPE_LEVEL_HIGH>; 2122 interrupt-names = "msi0", "msi1", "msi2", "msi3"; 2123 2124 #interrupt-cells = <1>; 2125 interrupt-map-mask = <0 0 0 0x7>; 2126 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>, 2127 <0 0 0 2 &intc 0 0 GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>, 2128 <0 0 0 3 &intc 0 0 GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>, 2129 <0 0 0 4 &intc 0 0 GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>; 2130 2131 clocks = <&gcc GCC_PCIE_2A_AUX_CLK>, 2132 <&gcc GCC_PCIE_2A_CFG_AHB_CLK>, 2133 <&gcc GCC_PCIE_2A_MSTR_AXI_CLK>, 2134 <&gcc GCC_PCIE_2A_SLV_AXI_CLK>, 2135 <&gcc GCC_PCIE_2A_SLV_Q2A_AXI_CLK>, 2136 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 2137 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, 2138 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>; 2139 clock-names = "aux", 2140 "cfg", 2141 "bus_master", 2142 "bus_slave", 2143 "slave_q2a", 2144 "ddrss_sf_tbu", 2145 "noc_aggr_4", 2146 "noc_aggr_south_sf"; 2147 2148 assigned-clocks = <&gcc GCC_PCIE_2A_AUX_CLK>; 2149 assigned-clock-rates = <19200000>; 2150 2151 interconnects = <&aggre2_noc MASTER_PCIE_2A 0 &mc_virt SLAVE_EBI1 0>, 2152 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_2A 0>; 2153 interconnect-names = "pcie-mem", "cpu-pcie"; 2154 2155 resets = <&gcc GCC_PCIE_2A_BCR>; 2156 reset-names = "pci"; 2157 2158 power-domains = <&gcc PCIE_2A_GDSC>; 2159 2160 phys = <&pcie2a_phy>; 2161 phy-names = "pciephy"; 2162 2163 status = "disabled"; 2164 }; 2165 2166 pcie2a_phy: phy@1c24000 { 2167 compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy"; 2168 reg = <0x0 0x01c24000 0x0 0x2000>, 2169 <0x0 0x01c26000 0x0 0x2000>; 2170 2171 clocks = <&gcc GCC_PCIE_2A_AUX_CLK>, 2172 <&gcc GCC_PCIE_2A_CFG_AHB_CLK>, 2173 <&gcc GCC_PCIE_2A2B_CLKREF_CLK>, 2174 <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>, 2175 <&gcc GCC_PCIE_2A_PIPE_CLK>, 2176 <&gcc GCC_PCIE_2A_PIPEDIV2_CLK>; 2177 clock-names = "aux", "cfg_ahb", "ref", "rchng", 2178 "pipe", "pipediv2"; 2179 2180 assigned-clocks = <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>; 2181 assigned-clock-rates = <100000000>; 2182 2183 power-domains = <&gcc PCIE_2A_GDSC>; 2184 2185 resets = <&gcc GCC_PCIE_2A_PHY_BCR>; 2186 reset-names = "phy"; 2187 2188 qcom,4ln-config-sel = <&tcsr 0xa044 0>; 2189 2190 #clock-cells = <0>; 2191 clock-output-names = "pcie_2a_pipe_clk"; 2192 2193 #phy-cells = <0>; 2194 2195 status = "disabled"; 2196 }; 2197 2198 ufs_mem_hc: ufs@1d84000 { 2199 compatible = "qcom,sc8280xp-ufshc", "qcom,ufshc", 2200 "jedec,ufs-2.0"; 2201 reg = <0 0x01d84000 0 0x3000>; 2202 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2203 phys = <&ufs_mem_phy>; 2204 phy-names = "ufsphy"; 2205 lanes-per-direction = <2>; 2206 #reset-cells = <1>; 2207 resets = <&gcc GCC_UFS_PHY_BCR>; 2208 reset-names = "rst"; 2209 2210 power-domains = <&gcc UFS_PHY_GDSC>; 2211 required-opps = <&rpmhpd_opp_nom>; 2212 2213 iommus = <&apps_smmu 0xe0 0x0>; 2214 dma-coherent; 2215 2216 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 2217 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2218 <&gcc GCC_UFS_PHY_AHB_CLK>, 2219 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2220 <&gcc GCC_UFS_REF_CLKREF_CLK>, 2221 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2222 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2223 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 2224 clock-names = "core_clk", 2225 "bus_aggr_clk", 2226 "iface_clk", 2227 "core_clk_unipro", 2228 "ref_clk", 2229 "tx_lane0_sync_clk", 2230 "rx_lane0_sync_clk", 2231 "rx_lane1_sync_clk"; 2232 freq-table-hz = <75000000 300000000>, 2233 <0 0>, 2234 <0 0>, 2235 <75000000 300000000>, 2236 <0 0>, 2237 <0 0>, 2238 <0 0>, 2239 <0 0>; 2240 status = "disabled"; 2241 }; 2242 2243 ufs_mem_phy: phy@1d87000 { 2244 compatible = "qcom,sc8280xp-qmp-ufs-phy"; 2245 reg = <0 0x01d87000 0 0x1000>; 2246 2247 clocks = <&gcc GCC_UFS_CARD_CLKREF_CLK>, 2248 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 2249 clock-names = "ref", "ref_aux"; 2250 2251 power-domains = <&gcc UFS_PHY_GDSC>; 2252 2253 resets = <&ufs_mem_hc 0>; 2254 reset-names = "ufsphy"; 2255 2256 #phy-cells = <0>; 2257 2258 status = "disabled"; 2259 }; 2260 2261 ufs_card_hc: ufs@1da4000 { 2262 compatible = "qcom,sc8280xp-ufshc", "qcom,ufshc", 2263 "jedec,ufs-2.0"; 2264 reg = <0 0x01da4000 0 0x3000>; 2265 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 2266 phys = <&ufs_card_phy>; 2267 phy-names = "ufsphy"; 2268 lanes-per-direction = <2>; 2269 #reset-cells = <1>; 2270 resets = <&gcc GCC_UFS_CARD_BCR>; 2271 reset-names = "rst"; 2272 2273 power-domains = <&gcc UFS_CARD_GDSC>; 2274 2275 iommus = <&apps_smmu 0x4a0 0x0>; 2276 dma-coherent; 2277 2278 clocks = <&gcc GCC_UFS_CARD_AXI_CLK>, 2279 <&gcc GCC_AGGRE_UFS_CARD_AXI_CLK>, 2280 <&gcc GCC_UFS_CARD_AHB_CLK>, 2281 <&gcc GCC_UFS_CARD_UNIPRO_CORE_CLK>, 2282 <&gcc GCC_UFS_REF_CLKREF_CLK>, 2283 <&gcc GCC_UFS_CARD_TX_SYMBOL_0_CLK>, 2284 <&gcc GCC_UFS_CARD_RX_SYMBOL_0_CLK>, 2285 <&gcc GCC_UFS_CARD_RX_SYMBOL_1_CLK>; 2286 clock-names = "core_clk", 2287 "bus_aggr_clk", 2288 "iface_clk", 2289 "core_clk_unipro", 2290 "ref_clk", 2291 "tx_lane0_sync_clk", 2292 "rx_lane0_sync_clk", 2293 "rx_lane1_sync_clk"; 2294 freq-table-hz = <75000000 300000000>, 2295 <0 0>, 2296 <0 0>, 2297 <75000000 300000000>, 2298 <0 0>, 2299 <0 0>, 2300 <0 0>, 2301 <0 0>; 2302 status = "disabled"; 2303 }; 2304 2305 ufs_card_phy: phy@1da7000 { 2306 compatible = "qcom,sc8280xp-qmp-ufs-phy"; 2307 reg = <0 0x01da7000 0 0x1000>; 2308 2309 clocks = <&gcc GCC_UFS_1_CARD_CLKREF_CLK>, 2310 <&gcc GCC_UFS_CARD_PHY_AUX_CLK>; 2311 clock-names = "ref", "ref_aux"; 2312 2313 power-domains = <&gcc UFS_CARD_GDSC>; 2314 2315 resets = <&ufs_card_hc 0>; 2316 reset-names = "ufsphy"; 2317 2318 #phy-cells = <0>; 2319 2320 status = "disabled"; 2321 }; 2322 2323 tcsr_mutex: hwlock@1f40000 { 2324 compatible = "qcom,tcsr-mutex"; 2325 reg = <0x0 0x01f40000 0x0 0x20000>; 2326 #hwlock-cells = <1>; 2327 }; 2328 2329 tcsr: syscon@1fc0000 { 2330 compatible = "qcom,sc8280xp-tcsr", "syscon"; 2331 reg = <0x0 0x01fc0000 0x0 0x30000>; 2332 }; 2333 2334 usb_0_hsphy: phy@88e5000 { 2335 compatible = "qcom,sc8280xp-usb-hs-phy", 2336 "qcom,usb-snps-hs-5nm-phy"; 2337 reg = <0 0x088e5000 0 0x400>; 2338 clocks = <&rpmhcc RPMH_CXO_CLK>; 2339 clock-names = "ref"; 2340 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2341 2342 #phy-cells = <0>; 2343 2344 status = "disabled"; 2345 }; 2346 2347 usb_2_hsphy0: phy@88e7000 { 2348 compatible = "qcom,sc8280xp-usb-hs-phy", 2349 "qcom,usb-snps-hs-5nm-phy"; 2350 reg = <0 0x088e7000 0 0x400>; 2351 clocks = <&gcc GCC_USB2_HS0_CLKREF_CLK>; 2352 clock-names = "ref"; 2353 resets = <&gcc GCC_QUSB2PHY_HS0_MP_BCR>; 2354 2355 #phy-cells = <0>; 2356 2357 status = "disabled"; 2358 }; 2359 2360 usb_2_hsphy1: phy@88e8000 { 2361 compatible = "qcom,sc8280xp-usb-hs-phy", 2362 "qcom,usb-snps-hs-5nm-phy"; 2363 reg = <0 0x088e8000 0 0x400>; 2364 clocks = <&gcc GCC_USB2_HS1_CLKREF_CLK>; 2365 clock-names = "ref"; 2366 resets = <&gcc GCC_QUSB2PHY_HS1_MP_BCR>; 2367 2368 #phy-cells = <0>; 2369 2370 status = "disabled"; 2371 }; 2372 2373 usb_2_hsphy2: phy@88e9000 { 2374 compatible = "qcom,sc8280xp-usb-hs-phy", 2375 "qcom,usb-snps-hs-5nm-phy"; 2376 reg = <0 0x088e9000 0 0x400>; 2377 clocks = <&gcc GCC_USB2_HS2_CLKREF_CLK>; 2378 clock-names = "ref"; 2379 resets = <&gcc GCC_QUSB2PHY_HS2_MP_BCR>; 2380 2381 #phy-cells = <0>; 2382 2383 status = "disabled"; 2384 }; 2385 2386 usb_2_hsphy3: phy@88ea000 { 2387 compatible = "qcom,sc8280xp-usb-hs-phy", 2388 "qcom,usb-snps-hs-5nm-phy"; 2389 reg = <0 0x088ea000 0 0x400>; 2390 clocks = <&gcc GCC_USB2_HS3_CLKREF_CLK>; 2391 clock-names = "ref"; 2392 resets = <&gcc GCC_QUSB2PHY_HS3_MP_BCR>; 2393 2394 #phy-cells = <0>; 2395 2396 status = "disabled"; 2397 }; 2398 2399 usb_2_qmpphy0: phy@88ef000 { 2400 compatible = "qcom,sc8280xp-qmp-usb3-uni-phy"; 2401 reg = <0 0x088ef000 0 0x2000>; 2402 2403 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, 2404 <&gcc GCC_USB3_MP0_CLKREF_CLK>, 2405 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, 2406 <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>; 2407 clock-names = "aux", "ref", "com_aux", "pipe"; 2408 2409 resets = <&gcc GCC_USB3_UNIPHY_MP0_BCR>, 2410 <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>; 2411 reset-names = "phy", "phy_phy"; 2412 2413 power-domains = <&gcc USB30_MP_GDSC>; 2414 2415 #clock-cells = <0>; 2416 clock-output-names = "usb2_phy0_pipe_clk"; 2417 2418 #phy-cells = <0>; 2419 2420 status = "disabled"; 2421 }; 2422 2423 usb_2_qmpphy1: phy@88f1000 { 2424 compatible = "qcom,sc8280xp-qmp-usb3-uni-phy"; 2425 reg = <0 0x088f1000 0 0x2000>; 2426 2427 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, 2428 <&gcc GCC_USB3_MP1_CLKREF_CLK>, 2429 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, 2430 <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>; 2431 clock-names = "aux", "ref", "com_aux", "pipe"; 2432 2433 resets = <&gcc GCC_USB3_UNIPHY_MP1_BCR>, 2434 <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>; 2435 reset-names = "phy", "phy_phy"; 2436 2437 power-domains = <&gcc USB30_MP_GDSC>; 2438 2439 #clock-cells = <0>; 2440 clock-output-names = "usb2_phy1_pipe_clk"; 2441 2442 #phy-cells = <0>; 2443 2444 status = "disabled"; 2445 }; 2446 2447 remoteproc_adsp: remoteproc@3000000 { 2448 compatible = "qcom,sc8280xp-adsp-pas"; 2449 reg = <0 0x03000000 0 0x100>; 2450 2451 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, 2452 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 2453 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 2454 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 2455 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>, 2456 <&smp2p_adsp_in 7 IRQ_TYPE_EDGE_RISING>; 2457 interrupt-names = "wdog", "fatal", "ready", 2458 "handover", "stop-ack", "shutdown-ack"; 2459 2460 clocks = <&rpmhcc RPMH_CXO_CLK>; 2461 clock-names = "xo"; 2462 2463 power-domains = <&rpmhpd SC8280XP_LCX>, 2464 <&rpmhpd SC8280XP_LMX>; 2465 power-domain-names = "lcx", "lmx"; 2466 2467 memory-region = <&pil_adsp_mem>; 2468 2469 qcom,qmp = <&aoss_qmp>; 2470 2471 qcom,smem-states = <&smp2p_adsp_out 0>; 2472 qcom,smem-state-names = "stop"; 2473 2474 status = "disabled"; 2475 2476 remoteproc_adsp_glink: glink-edge { 2477 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 2478 IPCC_MPROC_SIGNAL_GLINK_QMP 2479 IRQ_TYPE_EDGE_RISING>; 2480 mboxes = <&ipcc IPCC_CLIENT_LPASS 2481 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2482 2483 label = "lpass"; 2484 qcom,remote-pid = <2>; 2485 2486 gpr { 2487 compatible = "qcom,gpr"; 2488 qcom,glink-channels = "adsp_apps"; 2489 qcom,domain = <GPR_DOMAIN_ID_ADSP>; 2490 qcom,intents = <512 20>; 2491 #address-cells = <1>; 2492 #size-cells = <0>; 2493 2494 q6apm: service@1 { 2495 compatible = "qcom,q6apm"; 2496 reg = <GPR_APM_MODULE_IID>; 2497 #sound-dai-cells = <0>; 2498 qcom,protection-domain = "avs/audio", 2499 "msm/adsp/audio_pd"; 2500 q6apmdai: dais { 2501 compatible = "qcom,q6apm-dais"; 2502 iommus = <&apps_smmu 0x0c01 0x0>; 2503 }; 2504 2505 q6apmbedai: bedais { 2506 compatible = "qcom,q6apm-lpass-dais"; 2507 #sound-dai-cells = <1>; 2508 }; 2509 }; 2510 2511 q6prm: service@2 { 2512 compatible = "qcom,q6prm"; 2513 reg = <GPR_PRM_MODULE_IID>; 2514 qcom,protection-domain = "avs/audio", 2515 "msm/adsp/audio_pd"; 2516 q6prmcc: clock-controller { 2517 compatible = "qcom,q6prm-lpass-clocks"; 2518 #clock-cells = <2>; 2519 }; 2520 }; 2521 }; 2522 }; 2523 }; 2524 2525 rxmacro: rxmacro@3200000 { 2526 compatible = "qcom,sc8280xp-lpass-rx-macro"; 2527 reg = <0 0x03200000 0 0x1000>; 2528 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2529 <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2530 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2531 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2532 <&vamacro>; 2533 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2534 assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2535 <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2536 assigned-clock-rates = <19200000>, <19200000>; 2537 2538 clock-output-names = "mclk"; 2539 #clock-cells = <0>; 2540 #sound-dai-cells = <1>; 2541 2542 pinctrl-names = "default"; 2543 pinctrl-0 = <&rx_swr_default>; 2544 2545 status = "disabled"; 2546 }; 2547 2548 swr1: soundwire-controller@3210000 { 2549 compatible = "qcom,soundwire-v1.6.0"; 2550 reg = <0 0x03210000 0 0x2000>; 2551 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 2552 clocks = <&rxmacro>; 2553 clock-names = "iface"; 2554 label = "RX"; 2555 2556 qcom,din-ports = <0>; 2557 qcom,dout-ports = <5>; 2558 2559 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>; 2560 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0B 0x01 0x00>; 2561 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0B 0x00 0x00>; 2562 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0x00 0xff 0xff>; 2563 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0x0f 0xff 0xff>; 2564 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>; 2565 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff>; 2566 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; 2567 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 2568 2569 #sound-dai-cells = <1>; 2570 #address-cells = <2>; 2571 #size-cells = <0>; 2572 2573 status = "disabled"; 2574 }; 2575 2576 txmacro: txmacro@3220000 { 2577 compatible = "qcom,sc8280xp-lpass-tx-macro"; 2578 reg = <0 0x03220000 0 0x1000>; 2579 pinctrl-names = "default"; 2580 pinctrl-0 = <&tx_swr_default>; 2581 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2582 <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2583 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2584 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2585 <&vamacro>; 2586 2587 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2588 assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2589 <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2590 assigned-clock-rates = <19200000>, <19200000>; 2591 clock-output-names = "mclk"; 2592 2593 #clock-cells = <0>; 2594 #sound-dai-cells = <1>; 2595 2596 status = "disabled"; 2597 }; 2598 2599 wsamacro: codec@3240000 { 2600 compatible = "qcom,sc8280xp-lpass-wsa-macro"; 2601 reg = <0 0x03240000 0 0x1000>; 2602 clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2603 <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2604 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2605 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2606 <&vamacro>; 2607 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2608 assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2609 <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2610 assigned-clock-rates = <19200000>, <19200000>; 2611 2612 #clock-cells = <0>; 2613 clock-output-names = "mclk"; 2614 #sound-dai-cells = <1>; 2615 2616 pinctrl-names = "default"; 2617 pinctrl-0 = <&wsa_swr_default>; 2618 2619 status = "disabled"; 2620 }; 2621 2622 swr0: soundwire-controller@3250000 { 2623 reg = <0 0x03250000 0 0x2000>; 2624 compatible = "qcom,soundwire-v1.6.0"; 2625 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 2626 clocks = <&wsamacro>; 2627 clock-names = "iface"; 2628 label = "WSA"; 2629 2630 qcom,din-ports = <2>; 2631 qcom,dout-ports = <6>; 2632 2633 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>; 2634 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>; 2635 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>; 2636 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2637 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2638 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2639 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>; 2640 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2641 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2642 2643 #sound-dai-cells = <1>; 2644 #address-cells = <2>; 2645 #size-cells = <0>; 2646 2647 status = "disabled"; 2648 }; 2649 2650 swr2: soundwire-controller@3330000 { 2651 compatible = "qcom,soundwire-v1.6.0"; 2652 reg = <0 0x03330000 0 0x2000>; 2653 interrupts = <GIC_SPI 959 IRQ_TYPE_LEVEL_HIGH>, 2654 <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>; 2655 interrupt-names = "core", "wakeup"; 2656 2657 clocks = <&txmacro>; 2658 clock-names = "iface"; 2659 label = "TX"; 2660 #sound-dai-cells = <1>; 2661 #address-cells = <2>; 2662 #size-cells = <0>; 2663 2664 qcom,din-ports = <4>; 2665 qcom,dout-ports = <0>; 2666 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>; 2667 qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02 0x00>; 2668 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>; 2669 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>; 2670 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>; 2671 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>; 2672 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>; 2673 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>; 2674 qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00 0x01>; 2675 2676 status = "disabled"; 2677 }; 2678 2679 vamacro: codec@3370000 { 2680 compatible = "qcom,sc8280xp-lpass-va-macro"; 2681 reg = <0 0x03370000 0 0x1000>; 2682 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2683 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2684 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2685 <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2686 clock-names = "mclk", "macro", "dcodec", "npl"; 2687 assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2688 assigned-clock-rates = <19200000>; 2689 2690 #clock-cells = <0>; 2691 clock-output-names = "fsgen"; 2692 #sound-dai-cells = <1>; 2693 2694 status = "disabled"; 2695 }; 2696 2697 lpass_tlmm: pinctrl@33c0000 { 2698 compatible = "qcom,sc8280xp-lpass-lpi-pinctrl"; 2699 reg = <0 0x33c0000 0x0 0x20000>, 2700 <0 0x3550000 0x0 0x10000>; 2701 gpio-controller; 2702 #gpio-cells = <2>; 2703 gpio-ranges = <&lpass_tlmm 0 0 19>; 2704 2705 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2706 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2707 clock-names = "core", "audio"; 2708 2709 status = "disabled"; 2710 2711 tx_swr_default: tx-swr-default-state { 2712 clk-pins { 2713 pins = "gpio0"; 2714 function = "swr_tx_clk"; 2715 drive-strength = <2>; 2716 slew-rate = <1>; 2717 bias-disable; 2718 }; 2719 2720 data-pins { 2721 pins = "gpio1", "gpio2"; 2722 function = "swr_tx_data"; 2723 drive-strength = <2>; 2724 slew-rate = <1>; 2725 bias-bus-hold; 2726 }; 2727 }; 2728 2729 rx_swr_default: rx-swr-default-state { 2730 clk-pins { 2731 pins = "gpio3"; 2732 function = "swr_rx_clk"; 2733 drive-strength = <2>; 2734 slew-rate = <1>; 2735 bias-disable; 2736 }; 2737 2738 data-pins { 2739 pins = "gpio4", "gpio5"; 2740 function = "swr_rx_data"; 2741 drive-strength = <2>; 2742 slew-rate = <1>; 2743 bias-bus-hold; 2744 }; 2745 }; 2746 2747 dmic01_default: dmic01-default-state { 2748 clk-pins { 2749 pins = "gpio6"; 2750 function = "dmic1_clk"; 2751 drive-strength = <8>; 2752 output-high; 2753 }; 2754 2755 data-pins { 2756 pins = "gpio7"; 2757 function = "dmic1_data"; 2758 drive-strength = <8>; 2759 }; 2760 }; 2761 2762 dmic01_sleep: dmic01-sleep-state { 2763 clk-pins { 2764 pins = "gpio6"; 2765 function = "dmic1_clk"; 2766 drive-strength = <2>; 2767 bias-disable; 2768 output-low; 2769 }; 2770 2771 data-pins { 2772 pins = "gpio7"; 2773 function = "dmic1_data"; 2774 drive-strength = <2>; 2775 bias-pull-down; 2776 }; 2777 }; 2778 2779 dmic02_default: dmic02-default-state { 2780 clk-pins { 2781 pins = "gpio8"; 2782 function = "dmic2_clk"; 2783 drive-strength = <8>; 2784 output-high; 2785 }; 2786 2787 data-pins { 2788 pins = "gpio9"; 2789 function = "dmic2_data"; 2790 drive-strength = <8>; 2791 }; 2792 }; 2793 2794 dmic02_sleep: dmic02-sleep-state { 2795 clk-pins { 2796 pins = "gpio8"; 2797 function = "dmic2_clk"; 2798 drive-strength = <2>; 2799 bias-disable; 2800 output-low; 2801 }; 2802 2803 data-pins { 2804 pins = "gpio9"; 2805 function = "dmic2_data"; 2806 drive-strength = <2>; 2807 bias-pull-down; 2808 }; 2809 }; 2810 2811 wsa_swr_default: wsa-swr-default-state { 2812 clk-pins { 2813 pins = "gpio10"; 2814 function = "wsa_swr_clk"; 2815 drive-strength = <2>; 2816 slew-rate = <1>; 2817 bias-disable; 2818 }; 2819 2820 data-pins { 2821 pins = "gpio11"; 2822 function = "wsa_swr_data"; 2823 drive-strength = <2>; 2824 slew-rate = <1>; 2825 bias-bus-hold; 2826 }; 2827 }; 2828 2829 wsa2_swr_default: wsa2-swr-default-state { 2830 clk-pins { 2831 pins = "gpio15"; 2832 function = "wsa2_swr_clk"; 2833 drive-strength = <2>; 2834 slew-rate = <1>; 2835 bias-disable; 2836 }; 2837 2838 data-pins { 2839 pins = "gpio16"; 2840 function = "wsa2_swr_data"; 2841 drive-strength = <2>; 2842 slew-rate = <1>; 2843 bias-bus-hold; 2844 }; 2845 }; 2846 }; 2847 2848 sdc2: mmc@8804000 { 2849 compatible = "qcom,sc8280xp-sdhci", "qcom,sdhci-msm-v5"; 2850 reg = <0 0x08804000 0 0x1000>; 2851 2852 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 2853 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 2854 interrupt-names = "hc_irq", "pwr_irq"; 2855 2856 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 2857 <&gcc GCC_SDCC2_APPS_CLK>, 2858 <&rpmhcc RPMH_CXO_CLK>; 2859 clock-names = "iface", "core", "xo"; 2860 resets = <&gcc GCC_SDCC2_BCR>; 2861 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 2862 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; 2863 interconnect-names = "sdhc-ddr","cpu-sdhc"; 2864 iommus = <&apps_smmu 0x4e0 0x0>; 2865 power-domains = <&rpmhpd SC8280XP_CX>; 2866 operating-points-v2 = <&sdc2_opp_table>; 2867 bus-width = <4>; 2868 dma-coherent; 2869 2870 status = "disabled"; 2871 2872 sdc2_opp_table: opp-table { 2873 compatible = "operating-points-v2"; 2874 2875 opp-100000000 { 2876 opp-hz = /bits/ 64 <100000000>; 2877 required-opps = <&rpmhpd_opp_low_svs>; 2878 opp-peak-kBps = <1800000 400000>; 2879 opp-avg-kBps = <100000 0>; 2880 }; 2881 2882 opp-202000000 { 2883 opp-hz = /bits/ 64 <202000000>; 2884 required-opps = <&rpmhpd_opp_svs_l1>; 2885 opp-peak-kBps = <5400000 1600000>; 2886 opp-avg-kBps = <200000 0>; 2887 }; 2888 }; 2889 }; 2890 2891 usb_0_qmpphy: phy@88eb000 { 2892 compatible = "qcom,sc8280xp-qmp-usb43dp-phy"; 2893 reg = <0 0x088eb000 0 0x4000>; 2894 2895 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2896 <&gcc GCC_USB4_EUD_CLKREF_CLK>, 2897 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 2898 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2899 clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 2900 2901 power-domains = <&gcc USB30_PRIM_GDSC>; 2902 2903 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 2904 <&gcc GCC_USB4_DP_PHY_PRIM_BCR>; 2905 reset-names = "phy", "common"; 2906 2907 #clock-cells = <1>; 2908 #phy-cells = <1>; 2909 2910 status = "disabled"; 2911 2912 ports { 2913 #address-cells = <1>; 2914 #size-cells = <0>; 2915 2916 port@0 { 2917 reg = <0>; 2918 2919 usb_0_qmpphy_out: endpoint {}; 2920 }; 2921 2922 port@2 { 2923 reg = <2>; 2924 2925 usb_0_qmpphy_dp_in: endpoint {}; 2926 }; 2927 }; 2928 }; 2929 2930 usb_1_hsphy: phy@8902000 { 2931 compatible = "qcom,sc8280xp-usb-hs-phy", 2932 "qcom,usb-snps-hs-5nm-phy"; 2933 reg = <0 0x08902000 0 0x400>; 2934 #phy-cells = <0>; 2935 2936 clocks = <&rpmhcc RPMH_CXO_CLK>; 2937 clock-names = "ref"; 2938 2939 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 2940 2941 status = "disabled"; 2942 }; 2943 2944 usb_1_qmpphy: phy@8903000 { 2945 compatible = "qcom,sc8280xp-qmp-usb43dp-phy"; 2946 reg = <0 0x08903000 0 0x4000>; 2947 2948 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 2949 <&gcc GCC_USB4_CLKREF_CLK>, 2950 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, 2951 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 2952 clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 2953 2954 power-domains = <&gcc USB30_SEC_GDSC>; 2955 2956 resets = <&gcc GCC_USB3_PHY_SEC_BCR>, 2957 <&gcc GCC_USB4_1_DP_PHY_PRIM_BCR>; 2958 reset-names = "phy", "common"; 2959 2960 #clock-cells = <1>; 2961 #phy-cells = <1>; 2962 2963 status = "disabled"; 2964 2965 ports { 2966 #address-cells = <1>; 2967 #size-cells = <0>; 2968 2969 port@0 { 2970 reg = <0>; 2971 2972 usb_1_qmpphy_out: endpoint {}; 2973 }; 2974 2975 port@2 { 2976 reg = <2>; 2977 2978 usb_1_qmpphy_dp_in: endpoint {}; 2979 }; 2980 }; 2981 }; 2982 2983 mdss1_dp0_phy: phy@8909a00 { 2984 compatible = "qcom,sc8280xp-dp-phy"; 2985 reg = <0 0x08909a00 0 0x19c>, 2986 <0 0x08909200 0 0xec>, 2987 <0 0x08909600 0 0xec>, 2988 <0 0x08909000 0 0x1c8>; 2989 2990 clocks = <&dispcc1 DISP_CC_MDSS_DPTX0_AUX_CLK>, 2991 <&dispcc1 DISP_CC_MDSS_AHB_CLK>; 2992 clock-names = "aux", "cfg_ahb"; 2993 power-domains = <&rpmhpd SC8280XP_MX>; 2994 2995 #clock-cells = <1>; 2996 #phy-cells = <0>; 2997 2998 status = "disabled"; 2999 }; 3000 3001 mdss1_dp1_phy: phy@890ca00 { 3002 compatible = "qcom,sc8280xp-dp-phy"; 3003 reg = <0 0x0890ca00 0 0x19c>, 3004 <0 0x0890c200 0 0xec>, 3005 <0 0x0890c600 0 0xec>, 3006 <0 0x0890c000 0 0x1c8>; 3007 3008 clocks = <&dispcc1 DISP_CC_MDSS_DPTX1_AUX_CLK>, 3009 <&dispcc1 DISP_CC_MDSS_AHB_CLK>; 3010 clock-names = "aux", "cfg_ahb"; 3011 power-domains = <&rpmhpd SC8280XP_MX>; 3012 3013 #clock-cells = <1>; 3014 #phy-cells = <0>; 3015 3016 status = "disabled"; 3017 }; 3018 3019 pmu@9091000 { 3020 compatible = "qcom,sc8280xp-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; 3021 reg = <0 0x09091000 0 0x1000>; 3022 3023 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 3024 3025 interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>; 3026 3027 operating-points-v2 = <&llcc_bwmon_opp_table>; 3028 3029 llcc_bwmon_opp_table: opp-table { 3030 compatible = "operating-points-v2"; 3031 3032 opp-0 { 3033 opp-peak-kBps = <762000>; 3034 }; 3035 opp-1 { 3036 opp-peak-kBps = <1720000>; 3037 }; 3038 opp-2 { 3039 opp-peak-kBps = <2086000>; 3040 }; 3041 opp-3 { 3042 opp-peak-kBps = <2597000>; 3043 }; 3044 opp-4 { 3045 opp-peak-kBps = <2929000>; 3046 }; 3047 opp-5 { 3048 opp-peak-kBps = <3879000>; 3049 }; 3050 opp-6 { 3051 opp-peak-kBps = <5161000>; 3052 }; 3053 opp-7 { 3054 opp-peak-kBps = <5931000>; 3055 }; 3056 opp-8 { 3057 opp-peak-kBps = <6515000>; 3058 }; 3059 opp-9 { 3060 opp-peak-kBps = <7980000>; 3061 }; 3062 opp-10 { 3063 opp-peak-kBps = <8136000>; 3064 }; 3065 opp-11 { 3066 opp-peak-kBps = <10437000>; 3067 }; 3068 opp-12 { 3069 opp-peak-kBps = <12191000>; 3070 }; 3071 }; 3072 }; 3073 3074 pmu@90b6400 { 3075 compatible = "qcom,sc8280xp-cpu-bwmon", "qcom,sdm845-bwmon"; 3076 reg = <0 0x090b6400 0 0x600>; 3077 3078 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 3079 3080 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>; 3081 operating-points-v2 = <&cpu_bwmon_opp_table>; 3082 3083 cpu_bwmon_opp_table: opp-table { 3084 compatible = "operating-points-v2"; 3085 3086 opp-0 { 3087 opp-peak-kBps = <2288000>; 3088 }; 3089 opp-1 { 3090 opp-peak-kBps = <4577000>; 3091 }; 3092 opp-2 { 3093 opp-peak-kBps = <7110000>; 3094 }; 3095 opp-3 { 3096 opp-peak-kBps = <9155000>; 3097 }; 3098 opp-4 { 3099 opp-peak-kBps = <12298000>; 3100 }; 3101 opp-5 { 3102 opp-peak-kBps = <14236000>; 3103 }; 3104 opp-6 { 3105 opp-peak-kBps = <15258001>; 3106 }; 3107 }; 3108 }; 3109 3110 system-cache-controller@9200000 { 3111 compatible = "qcom,sc8280xp-llcc"; 3112 reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, 3113 <0 0x09300000 0 0x58000>, <0 0x09380000 0 0x58000>, 3114 <0 0x09400000 0 0x58000>, <0 0x09480000 0 0x58000>, 3115 <0 0x09500000 0 0x58000>, <0 0x09580000 0 0x58000>, 3116 <0 0x09600000 0 0x58000>; 3117 reg-names = "llcc0_base", "llcc1_base", "llcc2_base", 3118 "llcc3_base", "llcc4_base", "llcc5_base", 3119 "llcc6_base", "llcc7_base", "llcc_broadcast_base"; 3120 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 3121 }; 3122 3123 usb_0: usb@a6f8800 { 3124 compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3"; 3125 reg = <0 0x0a6f8800 0 0x400>; 3126 #address-cells = <2>; 3127 #size-cells = <2>; 3128 ranges; 3129 3130 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3131 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3132 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3133 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 3134 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3135 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 3136 <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>, 3137 <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>, 3138 <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 3139 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", 3140 "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys"; 3141 3142 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3143 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3144 assigned-clock-rates = <19200000>, <200000000>; 3145 3146 interrupts-extended = <&intc GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>, 3147 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 3148 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 3149 <&pdc 138 IRQ_TYPE_LEVEL_HIGH>; 3150 interrupt-names = "pwr_event", 3151 "dp_hs_phy_irq", 3152 "dm_hs_phy_irq", 3153 "ss_phy_irq"; 3154 3155 power-domains = <&gcc USB30_PRIM_GDSC>; 3156 required-opps = <&rpmhpd_opp_nom>; 3157 3158 resets = <&gcc GCC_USB30_PRIM_BCR>; 3159 3160 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 3161 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; 3162 interconnect-names = "usb-ddr", "apps-usb"; 3163 3164 wakeup-source; 3165 3166 status = "disabled"; 3167 3168 usb_0_dwc3: usb@a600000 { 3169 compatible = "snps,dwc3"; 3170 reg = <0 0x0a600000 0 0xcd00>; 3171 interrupts = <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>; 3172 iommus = <&apps_smmu 0x820 0x0>; 3173 phys = <&usb_0_hsphy>, <&usb_0_qmpphy QMP_USB43DP_USB3_PHY>; 3174 phy-names = "usb2-phy", "usb3-phy"; 3175 3176 port { 3177 usb_0_role_switch: endpoint { 3178 }; 3179 }; 3180 }; 3181 }; 3182 3183 usb_1: usb@a8f8800 { 3184 compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3"; 3185 reg = <0 0x0a8f8800 0 0x400>; 3186 #address-cells = <2>; 3187 #size-cells = <2>; 3188 ranges; 3189 3190 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 3191 <&gcc GCC_USB30_SEC_MASTER_CLK>, 3192 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 3193 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 3194 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3195 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 3196 <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>, 3197 <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>, 3198 <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 3199 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", 3200 "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys"; 3201 3202 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3203 <&gcc GCC_USB30_SEC_MASTER_CLK>; 3204 assigned-clock-rates = <19200000>, <200000000>; 3205 3206 interrupts-extended = <&intc GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>, 3207 <&pdc 12 IRQ_TYPE_EDGE_BOTH>, 3208 <&pdc 13 IRQ_TYPE_EDGE_BOTH>, 3209 <&pdc 136 IRQ_TYPE_LEVEL_HIGH>; 3210 interrupt-names = "pwr_event", 3211 "dp_hs_phy_irq", 3212 "dm_hs_phy_irq", 3213 "ss_phy_irq"; 3214 3215 power-domains = <&gcc USB30_SEC_GDSC>; 3216 required-opps = <&rpmhpd_opp_nom>; 3217 3218 resets = <&gcc GCC_USB30_SEC_BCR>; 3219 3220 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>, 3221 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>; 3222 interconnect-names = "usb-ddr", "apps-usb"; 3223 3224 wakeup-source; 3225 3226 status = "disabled"; 3227 3228 usb_1_dwc3: usb@a800000 { 3229 compatible = "snps,dwc3"; 3230 reg = <0 0x0a800000 0 0xcd00>; 3231 interrupts = <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>; 3232 iommus = <&apps_smmu 0x860 0x0>; 3233 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 3234 phy-names = "usb2-phy", "usb3-phy"; 3235 3236 port { 3237 usb_1_role_switch: endpoint { 3238 }; 3239 }; 3240 }; 3241 }; 3242 3243 mdss0: display-subsystem@ae00000 { 3244 compatible = "qcom,sc8280xp-mdss"; 3245 reg = <0 0x0ae00000 0 0x1000>; 3246 reg-names = "mdss"; 3247 3248 clocks = <&gcc GCC_DISP_AHB_CLK>, 3249 <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 3250 <&dispcc0 DISP_CC_MDSS_MDP_CLK>; 3251 clock-names = "iface", 3252 "ahb", 3253 "core"; 3254 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 3255 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>, 3256 <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>; 3257 interconnect-names = "mdp0-mem", "mdp1-mem"; 3258 iommus = <&apps_smmu 0x1000 0x402>; 3259 power-domains = <&dispcc0 MDSS_GDSC>; 3260 resets = <&dispcc0 DISP_CC_MDSS_CORE_BCR>; 3261 3262 interrupt-controller; 3263 #interrupt-cells = <1>; 3264 #address-cells = <2>; 3265 #size-cells = <2>; 3266 ranges; 3267 3268 status = "disabled"; 3269 3270 mdss0_mdp: display-controller@ae01000 { 3271 compatible = "qcom,sc8280xp-dpu"; 3272 reg = <0 0x0ae01000 0 0x8f000>, 3273 <0 0x0aeb0000 0 0x2008>; 3274 reg-names = "mdp", "vbif"; 3275 3276 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 3277 <&gcc GCC_DISP_SF_AXI_CLK>, 3278 <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 3279 <&dispcc0 DISP_CC_MDSS_MDP_LUT_CLK>, 3280 <&dispcc0 DISP_CC_MDSS_MDP_CLK>, 3281 <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>; 3282 clock-names = "bus", 3283 "nrt_bus", 3284 "iface", 3285 "lut", 3286 "core", 3287 "vsync"; 3288 interrupt-parent = <&mdss0>; 3289 interrupts = <0>; 3290 power-domains = <&rpmhpd SC8280XP_MMCX>; 3291 3292 assigned-clocks = <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>; 3293 assigned-clock-rates = <19200000>; 3294 operating-points-v2 = <&mdss0_mdp_opp_table>; 3295 3296 ports { 3297 #address-cells = <1>; 3298 #size-cells = <0>; 3299 3300 port@0 { 3301 reg = <0>; 3302 mdss0_intf0_out: endpoint { 3303 remote-endpoint = <&mdss0_dp0_in>; 3304 }; 3305 }; 3306 3307 port@4 { 3308 reg = <4>; 3309 mdss0_intf4_out: endpoint { 3310 remote-endpoint = <&mdss0_dp1_in>; 3311 }; 3312 }; 3313 3314 port@5 { 3315 reg = <5>; 3316 mdss0_intf5_out: endpoint { 3317 remote-endpoint = <&mdss0_dp3_in>; 3318 }; 3319 }; 3320 3321 port@6 { 3322 reg = <6>; 3323 mdss0_intf6_out: endpoint { 3324 remote-endpoint = <&mdss0_dp2_in>; 3325 }; 3326 }; 3327 }; 3328 3329 mdss0_mdp_opp_table: opp-table { 3330 compatible = "operating-points-v2"; 3331 3332 opp-200000000 { 3333 opp-hz = /bits/ 64 <200000000>; 3334 required-opps = <&rpmhpd_opp_low_svs>; 3335 }; 3336 3337 opp-300000000 { 3338 opp-hz = /bits/ 64 <300000000>; 3339 required-opps = <&rpmhpd_opp_svs>; 3340 }; 3341 3342 opp-375000000 { 3343 opp-hz = /bits/ 64 <375000000>; 3344 required-opps = <&rpmhpd_opp_svs_l1>; 3345 }; 3346 3347 opp-500000000 { 3348 opp-hz = /bits/ 64 <500000000>; 3349 required-opps = <&rpmhpd_opp_nom>; 3350 }; 3351 opp-600000000 { 3352 opp-hz = /bits/ 64 <600000000>; 3353 required-opps = <&rpmhpd_opp_turbo_l1>; 3354 }; 3355 }; 3356 }; 3357 3358 mdss0_dp0: displayport-controller@ae90000 { 3359 compatible = "qcom,sc8280xp-dp"; 3360 reg = <0 0xae90000 0 0x200>, 3361 <0 0xae90200 0 0x200>, 3362 <0 0xae90400 0 0x600>, 3363 <0 0xae91000 0 0x400>, 3364 <0 0xae91400 0 0x400>; 3365 interrupt-parent = <&mdss0>; 3366 interrupts = <12>; 3367 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 3368 <&dispcc0 DISP_CC_MDSS_DPTX0_AUX_CLK>, 3369 <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_CLK>, 3370 <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 3371 <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; 3372 clock-names = "core_iface", "core_aux", 3373 "ctrl_link", 3374 "ctrl_link_iface", 3375 "stream_pixel"; 3376 3377 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 3378 <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; 3379 assigned-clock-parents = <&usb_0_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3380 <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 3381 3382 phys = <&usb_0_qmpphy QMP_USB43DP_DP_PHY>; 3383 phy-names = "dp"; 3384 3385 #sound-dai-cells = <0>; 3386 3387 operating-points-v2 = <&mdss0_dp0_opp_table>; 3388 power-domains = <&rpmhpd SC8280XP_MMCX>; 3389 3390 status = "disabled"; 3391 3392 ports { 3393 #address-cells = <1>; 3394 #size-cells = <0>; 3395 3396 port@0 { 3397 reg = <0>; 3398 3399 mdss0_dp0_in: endpoint { 3400 remote-endpoint = <&mdss0_intf0_out>; 3401 }; 3402 }; 3403 3404 port@1 { 3405 reg = <1>; 3406 3407 mdss0_dp0_out: endpoint { 3408 }; 3409 }; 3410 }; 3411 3412 mdss0_dp0_opp_table: opp-table { 3413 compatible = "operating-points-v2"; 3414 3415 opp-160000000 { 3416 opp-hz = /bits/ 64 <160000000>; 3417 required-opps = <&rpmhpd_opp_low_svs>; 3418 }; 3419 3420 opp-270000000 { 3421 opp-hz = /bits/ 64 <270000000>; 3422 required-opps = <&rpmhpd_opp_svs>; 3423 }; 3424 3425 opp-540000000 { 3426 opp-hz = /bits/ 64 <540000000>; 3427 required-opps = <&rpmhpd_opp_svs_l1>; 3428 }; 3429 3430 opp-810000000 { 3431 opp-hz = /bits/ 64 <810000000>; 3432 required-opps = <&rpmhpd_opp_nom>; 3433 }; 3434 }; 3435 }; 3436 3437 mdss0_dp1: displayport-controller@ae98000 { 3438 compatible = "qcom,sc8280xp-dp"; 3439 reg = <0 0xae98000 0 0x200>, 3440 <0 0xae98200 0 0x200>, 3441 <0 0xae98400 0 0x600>, 3442 <0 0xae99000 0 0x400>, 3443 <0 0xae99400 0 0x400>; 3444 interrupt-parent = <&mdss0>; 3445 interrupts = <13>; 3446 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 3447 <&dispcc0 DISP_CC_MDSS_DPTX1_AUX_CLK>, 3448 <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_CLK>, 3449 <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, 3450 <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>; 3451 clock-names = "core_iface", "core_aux", 3452 "ctrl_link", 3453 "ctrl_link_iface", "stream_pixel"; 3454 3455 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, 3456 <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>; 3457 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3458 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 3459 3460 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; 3461 phy-names = "dp"; 3462 3463 #sound-dai-cells = <0>; 3464 3465 operating-points-v2 = <&mdss0_dp1_opp_table>; 3466 power-domains = <&rpmhpd SC8280XP_MMCX>; 3467 3468 status = "disabled"; 3469 3470 ports { 3471 #address-cells = <1>; 3472 #size-cells = <0>; 3473 3474 port@0 { 3475 reg = <0>; 3476 3477 mdss0_dp1_in: endpoint { 3478 remote-endpoint = <&mdss0_intf4_out>; 3479 }; 3480 }; 3481 3482 port@1 { 3483 reg = <1>; 3484 3485 mdss0_dp1_out: endpoint { 3486 }; 3487 }; 3488 }; 3489 3490 mdss0_dp1_opp_table: opp-table { 3491 compatible = "operating-points-v2"; 3492 3493 opp-160000000 { 3494 opp-hz = /bits/ 64 <160000000>; 3495 required-opps = <&rpmhpd_opp_low_svs>; 3496 }; 3497 3498 opp-270000000 { 3499 opp-hz = /bits/ 64 <270000000>; 3500 required-opps = <&rpmhpd_opp_svs>; 3501 }; 3502 3503 opp-540000000 { 3504 opp-hz = /bits/ 64 <540000000>; 3505 required-opps = <&rpmhpd_opp_svs_l1>; 3506 }; 3507 3508 opp-810000000 { 3509 opp-hz = /bits/ 64 <810000000>; 3510 required-opps = <&rpmhpd_opp_nom>; 3511 }; 3512 }; 3513 }; 3514 3515 mdss0_dp2: displayport-controller@ae9a000 { 3516 compatible = "qcom,sc8280xp-dp"; 3517 reg = <0 0xae9a000 0 0x200>, 3518 <0 0xae9a200 0 0x200>, 3519 <0 0xae9a400 0 0x600>, 3520 <0 0xae9b000 0 0x400>, 3521 <0 0xae9b400 0 0x400>; 3522 3523 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 3524 <&dispcc0 DISP_CC_MDSS_DPTX2_AUX_CLK>, 3525 <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_CLK>, 3526 <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>, 3527 <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>; 3528 clock-names = "core_iface", "core_aux", 3529 "ctrl_link", 3530 "ctrl_link_iface", "stream_pixel"; 3531 interrupt-parent = <&mdss0>; 3532 interrupts = <14>; 3533 phys = <&mdss0_dp2_phy>; 3534 phy-names = "dp"; 3535 power-domains = <&rpmhpd SC8280XP_MMCX>; 3536 3537 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>, 3538 <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>; 3539 assigned-clock-parents = <&mdss0_dp2_phy 0>, <&mdss0_dp2_phy 1>; 3540 operating-points-v2 = <&mdss0_dp2_opp_table>; 3541 3542 #sound-dai-cells = <0>; 3543 3544 status = "disabled"; 3545 3546 ports { 3547 #address-cells = <1>; 3548 #size-cells = <0>; 3549 3550 port@0 { 3551 reg = <0>; 3552 mdss0_dp2_in: endpoint { 3553 remote-endpoint = <&mdss0_intf6_out>; 3554 }; 3555 }; 3556 3557 port@1 { 3558 reg = <1>; 3559 }; 3560 }; 3561 3562 mdss0_dp2_opp_table: opp-table { 3563 compatible = "operating-points-v2"; 3564 3565 opp-160000000 { 3566 opp-hz = /bits/ 64 <160000000>; 3567 required-opps = <&rpmhpd_opp_low_svs>; 3568 }; 3569 3570 opp-270000000 { 3571 opp-hz = /bits/ 64 <270000000>; 3572 required-opps = <&rpmhpd_opp_svs>; 3573 }; 3574 3575 opp-540000000 { 3576 opp-hz = /bits/ 64 <540000000>; 3577 required-opps = <&rpmhpd_opp_svs_l1>; 3578 }; 3579 3580 opp-810000000 { 3581 opp-hz = /bits/ 64 <810000000>; 3582 required-opps = <&rpmhpd_opp_nom>; 3583 }; 3584 }; 3585 }; 3586 3587 mdss0_dp3: displayport-controller@aea0000 { 3588 compatible = "qcom,sc8280xp-dp"; 3589 reg = <0 0xaea0000 0 0x200>, 3590 <0 0xaea0200 0 0x200>, 3591 <0 0xaea0400 0 0x600>, 3592 <0 0xaea1000 0 0x400>, 3593 <0 0xaea1400 0 0x400>; 3594 3595 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 3596 <&dispcc0 DISP_CC_MDSS_DPTX3_AUX_CLK>, 3597 <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_CLK>, 3598 <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>, 3599 <&dispcc0 DISP_CC_MDSS_DPTX3_PIXEL0_CLK>; 3600 clock-names = "core_iface", "core_aux", 3601 "ctrl_link", 3602 "ctrl_link_iface", "stream_pixel"; 3603 interrupt-parent = <&mdss0>; 3604 interrupts = <15>; 3605 phys = <&mdss0_dp3_phy>; 3606 phy-names = "dp"; 3607 power-domains = <&rpmhpd SC8280XP_MMCX>; 3608 3609 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>, 3610 <&dispcc0 DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>; 3611 assigned-clock-parents = <&mdss0_dp3_phy 0>, <&mdss0_dp3_phy 1>; 3612 operating-points-v2 = <&mdss0_dp3_opp_table>; 3613 3614 #sound-dai-cells = <0>; 3615 3616 status = "disabled"; 3617 3618 ports { 3619 #address-cells = <1>; 3620 #size-cells = <0>; 3621 3622 port@0 { 3623 reg = <0>; 3624 mdss0_dp3_in: endpoint { 3625 remote-endpoint = <&mdss0_intf5_out>; 3626 }; 3627 }; 3628 3629 port@1 { 3630 reg = <1>; 3631 }; 3632 }; 3633 3634 mdss0_dp3_opp_table: opp-table { 3635 compatible = "operating-points-v2"; 3636 3637 opp-160000000 { 3638 opp-hz = /bits/ 64 <160000000>; 3639 required-opps = <&rpmhpd_opp_low_svs>; 3640 }; 3641 3642 opp-270000000 { 3643 opp-hz = /bits/ 64 <270000000>; 3644 required-opps = <&rpmhpd_opp_svs>; 3645 }; 3646 3647 opp-540000000 { 3648 opp-hz = /bits/ 64 <540000000>; 3649 required-opps = <&rpmhpd_opp_svs_l1>; 3650 }; 3651 3652 opp-810000000 { 3653 opp-hz = /bits/ 64 <810000000>; 3654 required-opps = <&rpmhpd_opp_nom>; 3655 }; 3656 }; 3657 }; 3658 }; 3659 3660 mdss0_dp2_phy: phy@aec2a00 { 3661 compatible = "qcom,sc8280xp-dp-phy"; 3662 reg = <0 0x0aec2a00 0 0x19c>, 3663 <0 0x0aec2200 0 0xec>, 3664 <0 0x0aec2600 0 0xec>, 3665 <0 0x0aec2000 0 0x1c8>; 3666 3667 clocks = <&dispcc0 DISP_CC_MDSS_DPTX2_AUX_CLK>, 3668 <&dispcc0 DISP_CC_MDSS_AHB_CLK>; 3669 clock-names = "aux", "cfg_ahb"; 3670 power-domains = <&rpmhpd SC8280XP_MX>; 3671 3672 #clock-cells = <1>; 3673 #phy-cells = <0>; 3674 3675 status = "disabled"; 3676 }; 3677 3678 mdss0_dp3_phy: phy@aec5a00 { 3679 compatible = "qcom,sc8280xp-dp-phy"; 3680 reg = <0 0x0aec5a00 0 0x19c>, 3681 <0 0x0aec5200 0 0xec>, 3682 <0 0x0aec5600 0 0xec>, 3683 <0 0x0aec5000 0 0x1c8>; 3684 3685 clocks = <&dispcc0 DISP_CC_MDSS_DPTX3_AUX_CLK>, 3686 <&dispcc0 DISP_CC_MDSS_AHB_CLK>; 3687 clock-names = "aux", "cfg_ahb"; 3688 power-domains = <&rpmhpd SC8280XP_MX>; 3689 3690 #clock-cells = <1>; 3691 #phy-cells = <0>; 3692 3693 status = "disabled"; 3694 }; 3695 3696 dispcc0: clock-controller@af00000 { 3697 compatible = "qcom,sc8280xp-dispcc0"; 3698 reg = <0 0x0af00000 0 0x20000>; 3699 3700 clocks = <&gcc GCC_DISP_AHB_CLK>, 3701 <&rpmhcc RPMH_CXO_CLK>, 3702 <&sleep_clk>, 3703 <&usb_0_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3704 <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 3705 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3706 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 3707 <&mdss0_dp2_phy 0>, 3708 <&mdss0_dp2_phy 1>, 3709 <&mdss0_dp3_phy 0>, 3710 <&mdss0_dp3_phy 1>, 3711 <0>, 3712 <0>, 3713 <0>, 3714 <0>; 3715 power-domains = <&rpmhpd SC8280XP_MMCX>; 3716 3717 #clock-cells = <1>; 3718 #power-domain-cells = <1>; 3719 #reset-cells = <1>; 3720 3721 status = "disabled"; 3722 }; 3723 3724 pdc: interrupt-controller@b220000 { 3725 compatible = "qcom,sc8280xp-pdc", "qcom,pdc"; 3726 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; 3727 qcom,pdc-ranges = <0 480 40>, 3728 <40 140 14>, 3729 <54 263 1>, 3730 <55 306 4>, 3731 <59 312 3>, 3732 <62 374 2>, 3733 <64 434 2>, 3734 <66 438 3>, 3735 <69 86 1>, 3736 <70 520 54>, 3737 <124 609 28>, 3738 <159 638 1>, 3739 <160 720 8>, 3740 <168 801 1>, 3741 <169 728 30>, 3742 <199 416 2>, 3743 <201 449 1>, 3744 <202 89 1>, 3745 <203 451 1>, 3746 <204 462 1>, 3747 <205 264 1>, 3748 <206 579 1>, 3749 <207 653 1>, 3750 <208 656 1>, 3751 <209 659 1>, 3752 <210 122 1>, 3753 <211 699 1>, 3754 <212 705 1>, 3755 <213 450 1>, 3756 <214 643 1>, 3757 <216 646 5>, 3758 <221 390 5>, 3759 <226 700 3>, 3760 <229 240 3>, 3761 <232 269 1>, 3762 <233 377 1>, 3763 <234 372 1>, 3764 <235 138 1>, 3765 <236 857 1>, 3766 <237 860 1>, 3767 <238 137 1>, 3768 <239 668 1>, 3769 <240 366 1>, 3770 <241 949 1>, 3771 <242 815 5>, 3772 <247 769 1>, 3773 <248 768 1>, 3774 <249 663 1>, 3775 <250 799 2>, 3776 <252 798 1>, 3777 <253 765 1>, 3778 <254 763 1>, 3779 <255 454 1>, 3780 <258 139 1>, 3781 <259 786 2>, 3782 <261 370 2>, 3783 <263 158 2>; 3784 #interrupt-cells = <2>; 3785 interrupt-parent = <&intc>; 3786 interrupt-controller; 3787 }; 3788 3789 tsens0: thermal-sensor@c263000 { 3790 compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2"; 3791 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 3792 <0 0x0c222000 0 0x8>; /* SROT */ 3793 #qcom,sensors = <14>; 3794 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, 3795 <&pdc 28 IRQ_TYPE_LEVEL_HIGH>; 3796 interrupt-names = "uplow", "critical"; 3797 #thermal-sensor-cells = <1>; 3798 }; 3799 3800 tsens1: thermal-sensor@c265000 { 3801 compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2"; 3802 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 3803 <0 0x0c223000 0 0x8>; /* SROT */ 3804 #qcom,sensors = <16>; 3805 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, 3806 <&pdc 29 IRQ_TYPE_LEVEL_HIGH>; 3807 interrupt-names = "uplow", "critical"; 3808 #thermal-sensor-cells = <1>; 3809 }; 3810 3811 aoss_qmp: power-management@c300000 { 3812 compatible = "qcom,sc8280xp-aoss-qmp", "qcom,aoss-qmp"; 3813 reg = <0 0x0c300000 0 0x400>; 3814 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>; 3815 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 3816 3817 #clock-cells = <0>; 3818 }; 3819 3820 sram@c3f0000 { 3821 compatible = "qcom,rpmh-stats"; 3822 reg = <0 0x0c3f0000 0 0x400>; 3823 }; 3824 3825 spmi_bus: spmi@c440000 { 3826 compatible = "qcom,spmi-pmic-arb"; 3827 reg = <0 0x0c440000 0 0x1100>, 3828 <0 0x0c600000 0 0x2000000>, 3829 <0 0x0e600000 0 0x100000>, 3830 <0 0x0e700000 0 0xa0000>, 3831 <0 0x0c40a000 0 0x26000>; 3832 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 3833 interrupt-names = "periph_irq"; 3834 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 3835 qcom,ee = <0>; 3836 qcom,channel = <0>; 3837 #address-cells = <2>; 3838 #size-cells = <0>; 3839 interrupt-controller; 3840 #interrupt-cells = <4>; 3841 }; 3842 3843 tlmm: pinctrl@f100000 { 3844 compatible = "qcom,sc8280xp-tlmm"; 3845 reg = <0 0x0f100000 0 0x300000>; 3846 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 3847 gpio-controller; 3848 #gpio-cells = <2>; 3849 interrupt-controller; 3850 #interrupt-cells = <2>; 3851 gpio-ranges = <&tlmm 0 0 230>; 3852 }; 3853 3854 apps_smmu: iommu@15000000 { 3855 compatible = "qcom,sc8280xp-smmu-500", "arm,mmu-500"; 3856 reg = <0 0x15000000 0 0x100000>; 3857 #iommu-cells = <2>; 3858 #global-interrupts = <2>; 3859 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 3860 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3861 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3862 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3863 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3864 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3865 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3866 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3867 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3868 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3869 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3870 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3871 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3872 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3873 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3874 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3875 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3876 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3877 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3878 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3879 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3880 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3881 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3882 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3883 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3884 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3885 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3886 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3887 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3888 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3889 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3890 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3891 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3892 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3893 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3894 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3895 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3896 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3897 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3898 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3899 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3900 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3901 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3902 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3903 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3904 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3905 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3906 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3907 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3908 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3909 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3910 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3911 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3912 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3913 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3914 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3915 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3916 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3917 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3918 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3919 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3920 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 3921 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 3922 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 3923 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 3924 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 3925 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 3926 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3927 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3928 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3929 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3930 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3931 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3932 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3933 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 3934 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 3935 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 3936 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 3937 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 3938 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 3939 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, 3940 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 3941 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 3942 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 3943 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, 3944 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 3945 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 3946 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 3947 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 3948 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 3949 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 3950 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 3951 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 3952 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 3953 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 3954 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>, 3955 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 3956 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 3957 <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>, 3958 <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>, 3959 <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>, 3960 <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>, 3961 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 3962 <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>, 3963 <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>, 3964 <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>, 3965 <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>, 3966 <GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH>, 3967 <GIC_SPI 911 IRQ_TYPE_LEVEL_HIGH>, 3968 <GIC_SPI 910 IRQ_TYPE_LEVEL_HIGH>, 3969 <GIC_SPI 909 IRQ_TYPE_LEVEL_HIGH>, 3970 <GIC_SPI 908 IRQ_TYPE_LEVEL_HIGH>, 3971 <GIC_SPI 907 IRQ_TYPE_LEVEL_HIGH>, 3972 <GIC_SPI 906 IRQ_TYPE_LEVEL_HIGH>, 3973 <GIC_SPI 905 IRQ_TYPE_LEVEL_HIGH>, 3974 <GIC_SPI 904 IRQ_TYPE_LEVEL_HIGH>, 3975 <GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>, 3976 <GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>, 3977 <GIC_SPI 901 IRQ_TYPE_LEVEL_HIGH>, 3978 <GIC_SPI 900 IRQ_TYPE_LEVEL_HIGH>, 3979 <GIC_SPI 899 IRQ_TYPE_LEVEL_HIGH>, 3980 <GIC_SPI 898 IRQ_TYPE_LEVEL_HIGH>, 3981 <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>, 3982 <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>, 3983 <GIC_SPI 895 IRQ_TYPE_LEVEL_HIGH>, 3984 <GIC_SPI 894 IRQ_TYPE_LEVEL_HIGH>, 3985 <GIC_SPI 893 IRQ_TYPE_LEVEL_HIGH>, 3986 <GIC_SPI 892 IRQ_TYPE_LEVEL_HIGH>, 3987 <GIC_SPI 891 IRQ_TYPE_LEVEL_HIGH>, 3988 <GIC_SPI 890 IRQ_TYPE_LEVEL_HIGH>; 3989 }; 3990 3991 intc: interrupt-controller@17a00000 { 3992 compatible = "arm,gic-v3"; 3993 interrupt-controller; 3994 #interrupt-cells = <3>; 3995 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 3996 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 3997 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3998 #redistributor-regions = <1>; 3999 redistributor-stride = <0 0x20000>; 4000 4001 #address-cells = <2>; 4002 #size-cells = <2>; 4003 ranges; 4004 4005 msi-controller@17a40000 { 4006 compatible = "arm,gic-v3-its"; 4007 reg = <0 0x17a40000 0 0x20000>; 4008 msi-controller; 4009 #msi-cells = <1>; 4010 }; 4011 }; 4012 4013 watchdog@17c10000 { 4014 compatible = "qcom,apss-wdt-sc8280xp", "qcom,kpss-wdt"; 4015 reg = <0 0x17c10000 0 0x1000>; 4016 clocks = <&sleep_clk>; 4017 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 4018 }; 4019 4020 timer@17c20000 { 4021 compatible = "arm,armv7-timer-mem"; 4022 reg = <0x0 0x17c20000 0x0 0x1000>; 4023 #address-cells = <1>; 4024 #size-cells = <1>; 4025 ranges = <0x0 0x0 0x0 0x20000000>; 4026 4027 frame@17c21000 { 4028 frame-number = <0>; 4029 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 4030 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 4031 reg = <0x17c21000 0x1000>, 4032 <0x17c22000 0x1000>; 4033 }; 4034 4035 frame@17c23000 { 4036 frame-number = <1>; 4037 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 4038 reg = <0x17c23000 0x1000>; 4039 status = "disabled"; 4040 }; 4041 4042 frame@17c25000 { 4043 frame-number = <2>; 4044 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 4045 reg = <0x17c25000 0x1000>; 4046 status = "disabled"; 4047 }; 4048 4049 frame@17c27000 { 4050 frame-number = <3>; 4051 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 4052 reg = <0x17c26000 0x1000>; 4053 status = "disabled"; 4054 }; 4055 4056 frame@17c29000 { 4057 frame-number = <4>; 4058 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 4059 reg = <0x17c29000 0x1000>; 4060 status = "disabled"; 4061 }; 4062 4063 frame@17c2b000 { 4064 frame-number = <5>; 4065 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 4066 reg = <0x17c2b000 0x1000>; 4067 status = "disabled"; 4068 }; 4069 4070 frame@17c2d000 { 4071 frame-number = <6>; 4072 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 4073 reg = <0x17c2d000 0x1000>; 4074 status = "disabled"; 4075 }; 4076 }; 4077 4078 apps_rsc: rsc@18200000 { 4079 compatible = "qcom,rpmh-rsc"; 4080 reg = <0x0 0x18200000 0x0 0x10000>, 4081 <0x0 0x18210000 0x0 0x10000>, 4082 <0x0 0x18220000 0x0 0x10000>; 4083 reg-names = "drv-0", "drv-1", "drv-2"; 4084 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 4085 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 4086 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 4087 qcom,tcs-offset = <0xd00>; 4088 qcom,drv-id = <2>; 4089 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 4090 <WAKE_TCS 3>, <CONTROL_TCS 1>; 4091 label = "apps_rsc"; 4092 4093 apps_bcm_voter: bcm-voter { 4094 compatible = "qcom,bcm-voter"; 4095 }; 4096 4097 rpmhcc: clock-controller { 4098 compatible = "qcom,sc8280xp-rpmh-clk"; 4099 #clock-cells = <1>; 4100 clock-names = "xo"; 4101 clocks = <&xo_board_clk>; 4102 }; 4103 4104 rpmhpd: power-controller { 4105 compatible = "qcom,sc8280xp-rpmhpd"; 4106 #power-domain-cells = <1>; 4107 operating-points-v2 = <&rpmhpd_opp_table>; 4108 4109 rpmhpd_opp_table: opp-table { 4110 compatible = "operating-points-v2"; 4111 4112 rpmhpd_opp_ret: opp1 { 4113 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 4114 }; 4115 4116 rpmhpd_opp_min_svs: opp2 { 4117 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 4118 }; 4119 4120 rpmhpd_opp_low_svs: opp3 { 4121 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4122 }; 4123 4124 rpmhpd_opp_svs: opp4 { 4125 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4126 }; 4127 4128 rpmhpd_opp_svs_l1: opp5 { 4129 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4130 }; 4131 4132 rpmhpd_opp_nom: opp6 { 4133 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4134 }; 4135 4136 rpmhpd_opp_nom_l1: opp7 { 4137 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4138 }; 4139 4140 rpmhpd_opp_nom_l2: opp8 { 4141 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 4142 }; 4143 4144 rpmhpd_opp_turbo: opp9 { 4145 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4146 }; 4147 4148 rpmhpd_opp_turbo_l1: opp10 { 4149 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4150 }; 4151 }; 4152 }; 4153 }; 4154 4155 epss_l3: interconnect@18590000 { 4156 compatible = "qcom,sc8280xp-epss-l3", "qcom,epss-l3"; 4157 reg = <0 0x18590000 0 0x1000>; 4158 4159 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 4160 clock-names = "xo", "alternate"; 4161 4162 #interconnect-cells = <1>; 4163 }; 4164 4165 cpufreq_hw: cpufreq@18591000 { 4166 compatible = "qcom,sc8280xp-cpufreq-epss", "qcom,cpufreq-epss"; 4167 reg = <0 0x18591000 0 0x1000>, 4168 <0 0x18592000 0 0x1000>; 4169 reg-names = "freq-domain0", "freq-domain1"; 4170 4171 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 4172 clock-names = "xo", "alternate"; 4173 4174 #freq-domain-cells = <1>; 4175 #clock-cells = <1>; 4176 }; 4177 4178 remoteproc_nsp0: remoteproc@1b300000 { 4179 compatible = "qcom,sc8280xp-nsp0-pas"; 4180 reg = <0 0x1b300000 0 0x100>; 4181 4182 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, 4183 <&smp2p_nsp0_in 0 IRQ_TYPE_EDGE_RISING>, 4184 <&smp2p_nsp0_in 1 IRQ_TYPE_EDGE_RISING>, 4185 <&smp2p_nsp0_in 2 IRQ_TYPE_EDGE_RISING>, 4186 <&smp2p_nsp0_in 3 IRQ_TYPE_EDGE_RISING>; 4187 interrupt-names = "wdog", "fatal", "ready", 4188 "handover", "stop-ack"; 4189 4190 clocks = <&rpmhcc RPMH_CXO_CLK>; 4191 clock-names = "xo"; 4192 4193 power-domains = <&rpmhpd SC8280XP_NSP>; 4194 power-domain-names = "nsp"; 4195 4196 memory-region = <&pil_nsp0_mem>; 4197 4198 qcom,smem-states = <&smp2p_nsp0_out 0>; 4199 qcom,smem-state-names = "stop"; 4200 4201 interconnects = <&nspa_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>; 4202 4203 status = "disabled"; 4204 4205 glink-edge { 4206 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 4207 IPCC_MPROC_SIGNAL_GLINK_QMP 4208 IRQ_TYPE_EDGE_RISING>; 4209 mboxes = <&ipcc IPCC_CLIENT_CDSP 4210 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4211 4212 label = "nsp0"; 4213 qcom,remote-pid = <5>; 4214 4215 fastrpc { 4216 compatible = "qcom,fastrpc"; 4217 qcom,glink-channels = "fastrpcglink-apps-dsp"; 4218 label = "cdsp"; 4219 #address-cells = <1>; 4220 #size-cells = <0>; 4221 4222 compute-cb@1 { 4223 compatible = "qcom,fastrpc-compute-cb"; 4224 reg = <1>; 4225 iommus = <&apps_smmu 0x3181 0x0420>; 4226 }; 4227 4228 compute-cb@2 { 4229 compatible = "qcom,fastrpc-compute-cb"; 4230 reg = <2>; 4231 iommus = <&apps_smmu 0x3182 0x0420>; 4232 }; 4233 4234 compute-cb@3 { 4235 compatible = "qcom,fastrpc-compute-cb"; 4236 reg = <3>; 4237 iommus = <&apps_smmu 0x3183 0x0420>; 4238 }; 4239 4240 compute-cb@4 { 4241 compatible = "qcom,fastrpc-compute-cb"; 4242 reg = <4>; 4243 iommus = <&apps_smmu 0x3184 0x0420>; 4244 }; 4245 4246 compute-cb@5 { 4247 compatible = "qcom,fastrpc-compute-cb"; 4248 reg = <5>; 4249 iommus = <&apps_smmu 0x3185 0x0420>; 4250 }; 4251 4252 compute-cb@6 { 4253 compatible = "qcom,fastrpc-compute-cb"; 4254 reg = <6>; 4255 iommus = <&apps_smmu 0x3186 0x0420>; 4256 }; 4257 4258 compute-cb@7 { 4259 compatible = "qcom,fastrpc-compute-cb"; 4260 reg = <7>; 4261 iommus = <&apps_smmu 0x3187 0x0420>; 4262 }; 4263 4264 compute-cb@8 { 4265 compatible = "qcom,fastrpc-compute-cb"; 4266 reg = <8>; 4267 iommus = <&apps_smmu 0x3188 0x0420>; 4268 }; 4269 4270 compute-cb@9 { 4271 compatible = "qcom,fastrpc-compute-cb"; 4272 reg = <9>; 4273 iommus = <&apps_smmu 0x318b 0x0420>; 4274 }; 4275 4276 compute-cb@10 { 4277 compatible = "qcom,fastrpc-compute-cb"; 4278 reg = <10>; 4279 iommus = <&apps_smmu 0x318b 0x0420>; 4280 }; 4281 4282 compute-cb@11 { 4283 compatible = "qcom,fastrpc-compute-cb"; 4284 reg = <11>; 4285 iommus = <&apps_smmu 0x318c 0x0420>; 4286 }; 4287 4288 compute-cb@12 { 4289 compatible = "qcom,fastrpc-compute-cb"; 4290 reg = <12>; 4291 iommus = <&apps_smmu 0x318d 0x0420>; 4292 }; 4293 4294 compute-cb@13 { 4295 compatible = "qcom,fastrpc-compute-cb"; 4296 reg = <13>; 4297 iommus = <&apps_smmu 0x318e 0x0420>; 4298 }; 4299 4300 compute-cb@14 { 4301 compatible = "qcom,fastrpc-compute-cb"; 4302 reg = <14>; 4303 iommus = <&apps_smmu 0x318f 0x0420>; 4304 }; 4305 }; 4306 }; 4307 }; 4308 4309 remoteproc_nsp1: remoteproc@21300000 { 4310 compatible = "qcom,sc8280xp-nsp1-pas"; 4311 reg = <0 0x21300000 0 0x100>; 4312 4313 interrupts-extended = <&intc GIC_SPI 887 IRQ_TYPE_LEVEL_HIGH>, 4314 <&smp2p_nsp1_in 0 IRQ_TYPE_EDGE_RISING>, 4315 <&smp2p_nsp1_in 1 IRQ_TYPE_EDGE_RISING>, 4316 <&smp2p_nsp1_in 2 IRQ_TYPE_EDGE_RISING>, 4317 <&smp2p_nsp1_in 3 IRQ_TYPE_EDGE_RISING>; 4318 interrupt-names = "wdog", "fatal", "ready", 4319 "handover", "stop-ack"; 4320 4321 clocks = <&rpmhcc RPMH_CXO_CLK>; 4322 clock-names = "xo"; 4323 4324 power-domains = <&rpmhpd SC8280XP_NSP>; 4325 power-domain-names = "nsp"; 4326 4327 memory-region = <&pil_nsp1_mem>; 4328 4329 qcom,smem-states = <&smp2p_nsp1_out 0>; 4330 qcom,smem-state-names = "stop"; 4331 4332 interconnects = <&nspb_noc MASTER_CDSP_PROC_B 0 &mc_virt SLAVE_EBI1 0>; 4333 4334 status = "disabled"; 4335 4336 glink-edge { 4337 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1 4338 IPCC_MPROC_SIGNAL_GLINK_QMP 4339 IRQ_TYPE_EDGE_RISING>; 4340 mboxes = <&ipcc IPCC_CLIENT_NSP1 4341 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4342 4343 label = "nsp1"; 4344 qcom,remote-pid = <12>; 4345 }; 4346 }; 4347 4348 mdss1: display-subsystem@22000000 { 4349 compatible = "qcom,sc8280xp-mdss"; 4350 reg = <0 0x22000000 0 0x1000>; 4351 reg-names = "mdss"; 4352 4353 clocks = <&gcc GCC_DISP_AHB_CLK>, 4354 <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 4355 <&dispcc1 DISP_CC_MDSS_MDP_CLK>; 4356 clock-names = "iface", 4357 "ahb", 4358 "core"; 4359 interconnects = <&mmss_noc MASTER_MDP_CORE1_0 0 &mc_virt SLAVE_EBI1 0>, 4360 <&mmss_noc MASTER_MDP_CORE1_1 0 &mc_virt SLAVE_EBI1 0>; 4361 interconnect-names = "mdp0-mem", "mdp1-mem"; 4362 interrupts = <GIC_SPI 865 IRQ_TYPE_LEVEL_HIGH>; 4363 4364 iommus = <&apps_smmu 0x1800 0x402>; 4365 power-domains = <&dispcc1 MDSS_GDSC>; 4366 resets = <&dispcc1 DISP_CC_MDSS_CORE_BCR>; 4367 4368 interrupt-controller; 4369 #interrupt-cells = <1>; 4370 #address-cells = <2>; 4371 #size-cells = <2>; 4372 ranges; 4373 4374 status = "disabled"; 4375 4376 mdss1_mdp: display-controller@22001000 { 4377 compatible = "qcom,sc8280xp-dpu"; 4378 reg = <0 0x22001000 0 0x8f000>, 4379 <0 0x220b0000 0 0x2008>; 4380 reg-names = "mdp", "vbif"; 4381 4382 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 4383 <&gcc GCC_DISP_SF_AXI_CLK>, 4384 <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 4385 <&dispcc1 DISP_CC_MDSS_MDP_LUT_CLK>, 4386 <&dispcc1 DISP_CC_MDSS_MDP_CLK>, 4387 <&dispcc1 DISP_CC_MDSS_VSYNC_CLK>; 4388 clock-names = "bus", 4389 "nrt_bus", 4390 "iface", 4391 "lut", 4392 "core", 4393 "vsync"; 4394 interrupt-parent = <&mdss1>; 4395 interrupts = <0>; 4396 power-domains = <&rpmhpd SC8280XP_MMCX>; 4397 4398 assigned-clocks = <&dispcc1 DISP_CC_MDSS_VSYNC_CLK>; 4399 assigned-clock-rates = <19200000>; 4400 operating-points-v2 = <&mdss1_mdp_opp_table>; 4401 4402 ports { 4403 #address-cells = <1>; 4404 #size-cells = <0>; 4405 4406 port@0 { 4407 reg = <0>; 4408 mdss1_intf0_out: endpoint { 4409 remote-endpoint = <&mdss1_dp0_in>; 4410 }; 4411 }; 4412 4413 port@4 { 4414 reg = <4>; 4415 mdss1_intf4_out: endpoint { 4416 remote-endpoint = <&mdss1_dp1_in>; 4417 }; 4418 }; 4419 4420 port@5 { 4421 reg = <5>; 4422 mdss1_intf5_out: endpoint { 4423 remote-endpoint = <&mdss1_dp3_in>; 4424 }; 4425 }; 4426 4427 port@6 { 4428 reg = <6>; 4429 mdss1_intf6_out: endpoint { 4430 remote-endpoint = <&mdss1_dp2_in>; 4431 }; 4432 }; 4433 }; 4434 4435 mdss1_mdp_opp_table: opp-table { 4436 compatible = "operating-points-v2"; 4437 4438 opp-200000000 { 4439 opp-hz = /bits/ 64 <200000000>; 4440 required-opps = <&rpmhpd_opp_low_svs>; 4441 }; 4442 4443 opp-300000000 { 4444 opp-hz = /bits/ 64 <300000000>; 4445 required-opps = <&rpmhpd_opp_svs>; 4446 }; 4447 4448 opp-375000000 { 4449 opp-hz = /bits/ 64 <375000000>; 4450 required-opps = <&rpmhpd_opp_svs_l1>; 4451 }; 4452 4453 opp-500000000 { 4454 opp-hz = /bits/ 64 <500000000>; 4455 required-opps = <&rpmhpd_opp_nom>; 4456 }; 4457 opp-600000000 { 4458 opp-hz = /bits/ 64 <600000000>; 4459 required-opps = <&rpmhpd_opp_turbo_l1>; 4460 }; 4461 }; 4462 }; 4463 4464 mdss1_dp0: displayport-controller@22090000 { 4465 compatible = "qcom,sc8280xp-dp"; 4466 reg = <0 0x22090000 0 0x200>, 4467 <0 0x22090200 0 0x200>, 4468 <0 0x22090400 0 0x600>, 4469 <0 0x22091000 0 0x400>, 4470 <0 0x22091400 0 0x400>; 4471 4472 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 4473 <&dispcc1 DISP_CC_MDSS_DPTX0_AUX_CLK>, 4474 <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_CLK>, 4475 <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 4476 <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; 4477 clock-names = "core_iface", "core_aux", 4478 "ctrl_link", 4479 "ctrl_link_iface", "stream_pixel"; 4480 interrupt-parent = <&mdss1>; 4481 interrupts = <12>; 4482 phys = <&mdss1_dp0_phy>; 4483 phy-names = "dp"; 4484 power-domains = <&rpmhpd SC8280XP_MMCX>; 4485 4486 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 4487 <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; 4488 assigned-clock-parents = <&mdss1_dp0_phy 0>, <&mdss1_dp0_phy 1>; 4489 operating-points-v2 = <&mdss1_dp0_opp_table>; 4490 4491 #sound-dai-cells = <0>; 4492 4493 status = "disabled"; 4494 4495 ports { 4496 #address-cells = <1>; 4497 #size-cells = <0>; 4498 4499 port@0 { 4500 reg = <0>; 4501 mdss1_dp0_in: endpoint { 4502 remote-endpoint = <&mdss1_intf0_out>; 4503 }; 4504 }; 4505 4506 port@1 { 4507 reg = <1>; 4508 }; 4509 }; 4510 4511 mdss1_dp0_opp_table: opp-table { 4512 compatible = "operating-points-v2"; 4513 4514 opp-160000000 { 4515 opp-hz = /bits/ 64 <160000000>; 4516 required-opps = <&rpmhpd_opp_low_svs>; 4517 }; 4518 4519 opp-270000000 { 4520 opp-hz = /bits/ 64 <270000000>; 4521 required-opps = <&rpmhpd_opp_svs>; 4522 }; 4523 4524 opp-540000000 { 4525 opp-hz = /bits/ 64 <540000000>; 4526 required-opps = <&rpmhpd_opp_svs_l1>; 4527 }; 4528 4529 opp-810000000 { 4530 opp-hz = /bits/ 64 <810000000>; 4531 required-opps = <&rpmhpd_opp_nom>; 4532 }; 4533 }; 4534 }; 4535 4536 mdss1_dp1: displayport-controller@22098000 { 4537 compatible = "qcom,sc8280xp-dp"; 4538 reg = <0 0x22098000 0 0x200>, 4539 <0 0x22098200 0 0x200>, 4540 <0 0x22098400 0 0x600>, 4541 <0 0x22099000 0 0x400>, 4542 <0 0x22099400 0 0x400>; 4543 4544 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 4545 <&dispcc1 DISP_CC_MDSS_DPTX1_AUX_CLK>, 4546 <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_CLK>, 4547 <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, 4548 <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>; 4549 clock-names = "core_iface", "core_aux", 4550 "ctrl_link", 4551 "ctrl_link_iface", "stream_pixel"; 4552 interrupt-parent = <&mdss1>; 4553 interrupts = <13>; 4554 phys = <&mdss1_dp1_phy>; 4555 phy-names = "dp"; 4556 power-domains = <&rpmhpd SC8280XP_MMCX>; 4557 4558 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, 4559 <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>; 4560 assigned-clock-parents = <&mdss1_dp1_phy 0>, <&mdss1_dp1_phy 1>; 4561 operating-points-v2 = <&mdss1_dp1_opp_table>; 4562 4563 #sound-dai-cells = <0>; 4564 4565 status = "disabled"; 4566 4567 ports { 4568 #address-cells = <1>; 4569 #size-cells = <0>; 4570 4571 port@0 { 4572 reg = <0>; 4573 mdss1_dp1_in: endpoint { 4574 remote-endpoint = <&mdss1_intf4_out>; 4575 }; 4576 }; 4577 4578 port@1 { 4579 reg = <1>; 4580 }; 4581 }; 4582 4583 mdss1_dp1_opp_table: opp-table { 4584 compatible = "operating-points-v2"; 4585 4586 opp-160000000 { 4587 opp-hz = /bits/ 64 <160000000>; 4588 required-opps = <&rpmhpd_opp_low_svs>; 4589 }; 4590 4591 opp-270000000 { 4592 opp-hz = /bits/ 64 <270000000>; 4593 required-opps = <&rpmhpd_opp_svs>; 4594 }; 4595 4596 opp-540000000 { 4597 opp-hz = /bits/ 64 <540000000>; 4598 required-opps = <&rpmhpd_opp_svs_l1>; 4599 }; 4600 4601 opp-810000000 { 4602 opp-hz = /bits/ 64 <810000000>; 4603 required-opps = <&rpmhpd_opp_nom>; 4604 }; 4605 }; 4606 }; 4607 4608 mdss1_dp2: displayport-controller@2209a000 { 4609 compatible = "qcom,sc8280xp-dp"; 4610 reg = <0 0x2209a000 0 0x200>, 4611 <0 0x2209a200 0 0x200>, 4612 <0 0x2209a400 0 0x600>, 4613 <0 0x2209b000 0 0x400>, 4614 <0 0x2209b400 0 0x400>; 4615 4616 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 4617 <&dispcc1 DISP_CC_MDSS_DPTX2_AUX_CLK>, 4618 <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_CLK>, 4619 <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>, 4620 <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>; 4621 clock-names = "core_iface", "core_aux", 4622 "ctrl_link", 4623 "ctrl_link_iface", "stream_pixel"; 4624 interrupt-parent = <&mdss1>; 4625 interrupts = <14>; 4626 phys = <&mdss1_dp2_phy>; 4627 phy-names = "dp"; 4628 power-domains = <&rpmhpd SC8280XP_MMCX>; 4629 4630 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>, 4631 <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>; 4632 assigned-clock-parents = <&mdss1_dp2_phy 0>, <&mdss1_dp2_phy 1>; 4633 operating-points-v2 = <&mdss1_dp2_opp_table>; 4634 4635 #sound-dai-cells = <0>; 4636 4637 status = "disabled"; 4638 4639 ports { 4640 #address-cells = <1>; 4641 #size-cells = <0>; 4642 4643 port@0 { 4644 reg = <0>; 4645 mdss1_dp2_in: endpoint { 4646 remote-endpoint = <&mdss1_intf6_out>; 4647 }; 4648 }; 4649 4650 port@1 { 4651 reg = <1>; 4652 }; 4653 }; 4654 4655 mdss1_dp2_opp_table: opp-table { 4656 compatible = "operating-points-v2"; 4657 4658 opp-160000000 { 4659 opp-hz = /bits/ 64 <160000000>; 4660 required-opps = <&rpmhpd_opp_low_svs>; 4661 }; 4662 4663 opp-270000000 { 4664 opp-hz = /bits/ 64 <270000000>; 4665 required-opps = <&rpmhpd_opp_svs>; 4666 }; 4667 4668 opp-540000000 { 4669 opp-hz = /bits/ 64 <540000000>; 4670 required-opps = <&rpmhpd_opp_svs_l1>; 4671 }; 4672 4673 opp-810000000 { 4674 opp-hz = /bits/ 64 <810000000>; 4675 required-opps = <&rpmhpd_opp_nom>; 4676 }; 4677 }; 4678 }; 4679 4680 mdss1_dp3: displayport-controller@220a0000 { 4681 compatible = "qcom,sc8280xp-dp"; 4682 reg = <0 0x220a0000 0 0x200>, 4683 <0 0x220a0200 0 0x200>, 4684 <0 0x220a0400 0 0x600>, 4685 <0 0x220a1000 0 0x400>, 4686 <0 0x220a1400 0 0x400>; 4687 4688 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 4689 <&dispcc1 DISP_CC_MDSS_DPTX3_AUX_CLK>, 4690 <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_CLK>, 4691 <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>, 4692 <&dispcc1 DISP_CC_MDSS_DPTX3_PIXEL0_CLK>; 4693 clock-names = "core_iface", "core_aux", 4694 "ctrl_link", 4695 "ctrl_link_iface", "stream_pixel"; 4696 interrupt-parent = <&mdss1>; 4697 interrupts = <15>; 4698 phys = <&mdss1_dp3_phy>; 4699 phy-names = "dp"; 4700 power-domains = <&rpmhpd SC8280XP_MMCX>; 4701 4702 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>, 4703 <&dispcc1 DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>; 4704 assigned-clock-parents = <&mdss1_dp3_phy 0>, <&mdss1_dp3_phy 1>; 4705 operating-points-v2 = <&mdss1_dp3_opp_table>; 4706 4707 #sound-dai-cells = <0>; 4708 4709 status = "disabled"; 4710 4711 ports { 4712 #address-cells = <1>; 4713 #size-cells = <0>; 4714 4715 port@0 { 4716 reg = <0>; 4717 mdss1_dp3_in: endpoint { 4718 remote-endpoint = <&mdss1_intf5_out>; 4719 }; 4720 }; 4721 4722 port@1 { 4723 reg = <1>; 4724 }; 4725 }; 4726 4727 mdss1_dp3_opp_table: opp-table { 4728 compatible = "operating-points-v2"; 4729 4730 opp-160000000 { 4731 opp-hz = /bits/ 64 <160000000>; 4732 required-opps = <&rpmhpd_opp_low_svs>; 4733 }; 4734 4735 opp-270000000 { 4736 opp-hz = /bits/ 64 <270000000>; 4737 required-opps = <&rpmhpd_opp_svs>; 4738 }; 4739 4740 opp-540000000 { 4741 opp-hz = /bits/ 64 <540000000>; 4742 required-opps = <&rpmhpd_opp_svs_l1>; 4743 }; 4744 4745 opp-810000000 { 4746 opp-hz = /bits/ 64 <810000000>; 4747 required-opps = <&rpmhpd_opp_nom>; 4748 }; 4749 }; 4750 }; 4751 }; 4752 4753 mdss1_dp2_phy: phy@220c2a00 { 4754 compatible = "qcom,sc8280xp-dp-phy"; 4755 reg = <0 0x220c2a00 0 0x19c>, 4756 <0 0x220c2200 0 0xec>, 4757 <0 0x220c2600 0 0xec>, 4758 <0 0x220c2000 0 0x1c8>; 4759 4760 clocks = <&dispcc1 DISP_CC_MDSS_DPTX2_AUX_CLK>, 4761 <&dispcc1 DISP_CC_MDSS_AHB_CLK>; 4762 clock-names = "aux", "cfg_ahb"; 4763 power-domains = <&rpmhpd SC8280XP_MX>; 4764 4765 #clock-cells = <1>; 4766 #phy-cells = <0>; 4767 4768 status = "disabled"; 4769 }; 4770 4771 mdss1_dp3_phy: phy@220c5a00 { 4772 compatible = "qcom,sc8280xp-dp-phy"; 4773 reg = <0 0x220c5a00 0 0x19c>, 4774 <0 0x220c5200 0 0xec>, 4775 <0 0x220c5600 0 0xec>, 4776 <0 0x220c5000 0 0x1c8>; 4777 4778 clocks = <&dispcc1 DISP_CC_MDSS_DPTX3_AUX_CLK>, 4779 <&dispcc1 DISP_CC_MDSS_AHB_CLK>; 4780 clock-names = "aux", "cfg_ahb"; 4781 power-domains = <&rpmhpd SC8280XP_MX>; 4782 4783 #clock-cells = <1>; 4784 #phy-cells = <0>; 4785 4786 status = "disabled"; 4787 }; 4788 4789 dispcc1: clock-controller@22100000 { 4790 compatible = "qcom,sc8280xp-dispcc1"; 4791 reg = <0 0x22100000 0 0x20000>; 4792 4793 clocks = <&gcc GCC_DISP_AHB_CLK>, 4794 <&rpmhcc RPMH_CXO_CLK>, 4795 <0>, 4796 <&mdss1_dp0_phy 0>, 4797 <&mdss1_dp0_phy 1>, 4798 <&mdss1_dp1_phy 0>, 4799 <&mdss1_dp1_phy 1>, 4800 <&mdss1_dp2_phy 0>, 4801 <&mdss1_dp2_phy 1>, 4802 <&mdss1_dp3_phy 0>, 4803 <&mdss1_dp3_phy 1>, 4804 <0>, 4805 <0>, 4806 <0>, 4807 <0>; 4808 power-domains = <&rpmhpd SC8280XP_MMCX>; 4809 4810 #clock-cells = <1>; 4811 #power-domain-cells = <1>; 4812 #reset-cells = <1>; 4813 4814 status = "disabled"; 4815 }; 4816 4817 ethernet1: ethernet@23000000 { 4818 compatible = "qcom,sc8280xp-ethqos"; 4819 reg = <0x0 0x23000000 0x0 0x10000>, 4820 <0x0 0x23016000 0x0 0x100>; 4821 reg-names = "stmmaceth", "rgmii"; 4822 4823 clocks = <&gcc GCC_EMAC1_AXI_CLK>, 4824 <&gcc GCC_EMAC1_SLV_AHB_CLK>, 4825 <&gcc GCC_EMAC1_PTP_CLK>, 4826 <&gcc GCC_EMAC1_RGMII_CLK>; 4827 clock-names = "stmmaceth", 4828 "pclk", 4829 "ptp_ref", 4830 "rgmii"; 4831 4832 interrupts = <GIC_SPI 929 IRQ_TYPE_LEVEL_HIGH>, 4833 <GIC_SPI 919 IRQ_TYPE_LEVEL_HIGH>; 4834 interrupt-names = "macirq", "eth_lpi"; 4835 4836 iommus = <&apps_smmu 0x40 0xf>; 4837 power-domains = <&gcc EMAC_1_GDSC>; 4838 4839 snps,tso; 4840 snps,pbl = <32>; 4841 rx-fifo-depth = <4096>; 4842 tx-fifo-depth = <4096>; 4843 4844 status = "disabled"; 4845 }; 4846 }; 4847 4848 sound: sound { 4849 }; 4850 4851 thermal-zones { 4852 cpu0-thermal { 4853 polling-delay-passive = <250>; 4854 polling-delay = <1000>; 4855 4856 thermal-sensors = <&tsens0 1>; 4857 4858 trips { 4859 cpu-crit { 4860 temperature = <110000>; 4861 hysteresis = <1000>; 4862 type = "critical"; 4863 }; 4864 }; 4865 }; 4866 4867 cpu1-thermal { 4868 polling-delay-passive = <250>; 4869 polling-delay = <1000>; 4870 4871 thermal-sensors = <&tsens0 2>; 4872 4873 trips { 4874 cpu-crit { 4875 temperature = <110000>; 4876 hysteresis = <1000>; 4877 type = "critical"; 4878 }; 4879 }; 4880 }; 4881 4882 cpu2-thermal { 4883 polling-delay-passive = <250>; 4884 polling-delay = <1000>; 4885 4886 thermal-sensors = <&tsens0 3>; 4887 4888 trips { 4889 cpu-crit { 4890 temperature = <110000>; 4891 hysteresis = <1000>; 4892 type = "critical"; 4893 }; 4894 }; 4895 }; 4896 4897 cpu3-thermal { 4898 polling-delay-passive = <250>; 4899 polling-delay = <1000>; 4900 4901 thermal-sensors = <&tsens0 4>; 4902 4903 trips { 4904 cpu-crit { 4905 temperature = <110000>; 4906 hysteresis = <1000>; 4907 type = "critical"; 4908 }; 4909 }; 4910 }; 4911 4912 cpu4-thermal { 4913 polling-delay-passive = <250>; 4914 polling-delay = <1000>; 4915 4916 thermal-sensors = <&tsens0 5>; 4917 4918 trips { 4919 cpu-crit { 4920 temperature = <110000>; 4921 hysteresis = <1000>; 4922 type = "critical"; 4923 }; 4924 }; 4925 }; 4926 4927 cpu5-thermal { 4928 polling-delay-passive = <250>; 4929 polling-delay = <1000>; 4930 4931 thermal-sensors = <&tsens0 6>; 4932 4933 trips { 4934 cpu-crit { 4935 temperature = <110000>; 4936 hysteresis = <1000>; 4937 type = "critical"; 4938 }; 4939 }; 4940 }; 4941 4942 cpu6-thermal { 4943 polling-delay-passive = <250>; 4944 polling-delay = <1000>; 4945 4946 thermal-sensors = <&tsens0 7>; 4947 4948 trips { 4949 cpu-crit { 4950 temperature = <110000>; 4951 hysteresis = <1000>; 4952 type = "critical"; 4953 }; 4954 }; 4955 }; 4956 4957 cpu7-thermal { 4958 polling-delay-passive = <250>; 4959 polling-delay = <1000>; 4960 4961 thermal-sensors = <&tsens0 8>; 4962 4963 trips { 4964 cpu-crit { 4965 temperature = <110000>; 4966 hysteresis = <1000>; 4967 type = "critical"; 4968 }; 4969 }; 4970 }; 4971 4972 cluster0-thermal { 4973 polling-delay-passive = <250>; 4974 polling-delay = <1000>; 4975 4976 thermal-sensors = <&tsens0 9>; 4977 4978 trips { 4979 cpu-crit { 4980 temperature = <110000>; 4981 hysteresis = <1000>; 4982 type = "critical"; 4983 }; 4984 }; 4985 }; 4986 4987 mem-thermal { 4988 polling-delay-passive = <250>; 4989 polling-delay = <1000>; 4990 4991 thermal-sensors = <&tsens1 15>; 4992 4993 trips { 4994 trip-point0 { 4995 temperature = <90000>; 4996 hysteresis = <2000>; 4997 type = "hot"; 4998 }; 4999 }; 5000 }; 5001 }; 5002 5003 timer { 5004 compatible = "arm,armv8-timer"; 5005 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5006 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5007 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5008 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 5009 }; 5010}; 5011