1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2021, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2022, Linaro Limited 5 */ 6 7#include <dt-bindings/clock/qcom,dispcc-sc8280xp.h> 8#include <dt-bindings/clock/qcom,gcc-sc8280xp.h> 9#include <dt-bindings/clock/qcom,rpmh.h> 10#include <dt-bindings/interconnect/qcom,osm-l3.h> 11#include <dt-bindings/interconnect/qcom,sc8280xp.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/mailbox/qcom-ipcc.h> 14#include <dt-bindings/phy/phy-qcom-qmp.h> 15#include <dt-bindings/power/qcom-rpmpd.h> 16#include <dt-bindings/soc/qcom,gpr.h> 17#include <dt-bindings/soc/qcom,rpmh-rsc.h> 18#include <dt-bindings/sound/qcom,q6afe.h> 19#include <dt-bindings/thermal/thermal.h> 20 21/ { 22 interrupt-parent = <&intc>; 23 24 #address-cells = <2>; 25 #size-cells = <2>; 26 27 clocks { 28 xo_board_clk: xo-board-clk { 29 compatible = "fixed-clock"; 30 #clock-cells = <0>; 31 }; 32 33 sleep_clk: sleep-clk { 34 compatible = "fixed-clock"; 35 #clock-cells = <0>; 36 clock-frequency = <32764>; 37 }; 38 }; 39 40 cpus { 41 #address-cells = <2>; 42 #size-cells = <0>; 43 44 CPU0: cpu@0 { 45 device_type = "cpu"; 46 compatible = "arm,cortex-a78c"; 47 reg = <0x0 0x0>; 48 clocks = <&cpufreq_hw 0>; 49 enable-method = "psci"; 50 capacity-dmips-mhz = <602>; 51 next-level-cache = <&L2_0>; 52 power-domains = <&CPU_PD0>; 53 power-domain-names = "psci"; 54 qcom,freq-domain = <&cpufreq_hw 0>; 55 operating-points-v2 = <&cpu0_opp_table>; 56 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 57 #cooling-cells = <2>; 58 L2_0: l2-cache { 59 compatible = "cache"; 60 cache-level = <2>; 61 next-level-cache = <&L3_0>; 62 L3_0: l3-cache { 63 compatible = "cache"; 64 cache-level = <3>; 65 }; 66 }; 67 }; 68 69 CPU1: cpu@100 { 70 device_type = "cpu"; 71 compatible = "arm,cortex-a78c"; 72 reg = <0x0 0x100>; 73 clocks = <&cpufreq_hw 0>; 74 enable-method = "psci"; 75 capacity-dmips-mhz = <602>; 76 next-level-cache = <&L2_100>; 77 power-domains = <&CPU_PD1>; 78 power-domain-names = "psci"; 79 qcom,freq-domain = <&cpufreq_hw 0>; 80 operating-points-v2 = <&cpu0_opp_table>; 81 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 82 #cooling-cells = <2>; 83 L2_100: l2-cache { 84 compatible = "cache"; 85 cache-level = <2>; 86 next-level-cache = <&L3_0>; 87 }; 88 }; 89 90 CPU2: cpu@200 { 91 device_type = "cpu"; 92 compatible = "arm,cortex-a78c"; 93 reg = <0x0 0x200>; 94 clocks = <&cpufreq_hw 0>; 95 enable-method = "psci"; 96 capacity-dmips-mhz = <602>; 97 next-level-cache = <&L2_200>; 98 power-domains = <&CPU_PD2>; 99 power-domain-names = "psci"; 100 qcom,freq-domain = <&cpufreq_hw 0>; 101 operating-points-v2 = <&cpu0_opp_table>; 102 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 103 #cooling-cells = <2>; 104 L2_200: l2-cache { 105 compatible = "cache"; 106 cache-level = <2>; 107 next-level-cache = <&L3_0>; 108 }; 109 }; 110 111 CPU3: cpu@300 { 112 device_type = "cpu"; 113 compatible = "arm,cortex-a78c"; 114 reg = <0x0 0x300>; 115 clocks = <&cpufreq_hw 0>; 116 enable-method = "psci"; 117 capacity-dmips-mhz = <602>; 118 next-level-cache = <&L2_300>; 119 power-domains = <&CPU_PD3>; 120 power-domain-names = "psci"; 121 qcom,freq-domain = <&cpufreq_hw 0>; 122 operating-points-v2 = <&cpu0_opp_table>; 123 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 124 #cooling-cells = <2>; 125 L2_300: l2-cache { 126 compatible = "cache"; 127 cache-level = <2>; 128 next-level-cache = <&L3_0>; 129 }; 130 }; 131 132 CPU4: cpu@400 { 133 device_type = "cpu"; 134 compatible = "arm,cortex-x1c"; 135 reg = <0x0 0x400>; 136 clocks = <&cpufreq_hw 1>; 137 enable-method = "psci"; 138 capacity-dmips-mhz = <1024>; 139 next-level-cache = <&L2_400>; 140 power-domains = <&CPU_PD4>; 141 power-domain-names = "psci"; 142 qcom,freq-domain = <&cpufreq_hw 1>; 143 operating-points-v2 = <&cpu4_opp_table>; 144 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 145 #cooling-cells = <2>; 146 L2_400: l2-cache { 147 compatible = "cache"; 148 cache-level = <2>; 149 next-level-cache = <&L3_0>; 150 }; 151 }; 152 153 CPU5: cpu@500 { 154 device_type = "cpu"; 155 compatible = "arm,cortex-x1c"; 156 reg = <0x0 0x500>; 157 clocks = <&cpufreq_hw 1>; 158 enable-method = "psci"; 159 capacity-dmips-mhz = <1024>; 160 next-level-cache = <&L2_500>; 161 power-domains = <&CPU_PD5>; 162 power-domain-names = "psci"; 163 qcom,freq-domain = <&cpufreq_hw 1>; 164 operating-points-v2 = <&cpu4_opp_table>; 165 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 166 #cooling-cells = <2>; 167 L2_500: l2-cache { 168 compatible = "cache"; 169 cache-level = <2>; 170 next-level-cache = <&L3_0>; 171 }; 172 }; 173 174 CPU6: cpu@600 { 175 device_type = "cpu"; 176 compatible = "arm,cortex-x1c"; 177 reg = <0x0 0x600>; 178 clocks = <&cpufreq_hw 1>; 179 enable-method = "psci"; 180 capacity-dmips-mhz = <1024>; 181 next-level-cache = <&L2_600>; 182 power-domains = <&CPU_PD6>; 183 power-domain-names = "psci"; 184 qcom,freq-domain = <&cpufreq_hw 1>; 185 operating-points-v2 = <&cpu4_opp_table>; 186 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 187 #cooling-cells = <2>; 188 L2_600: l2-cache { 189 compatible = "cache"; 190 cache-level = <2>; 191 next-level-cache = <&L3_0>; 192 }; 193 }; 194 195 CPU7: cpu@700 { 196 device_type = "cpu"; 197 compatible = "arm,cortex-x1c"; 198 reg = <0x0 0x700>; 199 clocks = <&cpufreq_hw 1>; 200 enable-method = "psci"; 201 capacity-dmips-mhz = <1024>; 202 next-level-cache = <&L2_700>; 203 power-domains = <&CPU_PD7>; 204 power-domain-names = "psci"; 205 qcom,freq-domain = <&cpufreq_hw 1>; 206 operating-points-v2 = <&cpu4_opp_table>; 207 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 208 #cooling-cells = <2>; 209 L2_700: l2-cache { 210 compatible = "cache"; 211 cache-level = <2>; 212 next-level-cache = <&L3_0>; 213 }; 214 }; 215 216 cpu-map { 217 cluster0 { 218 core0 { 219 cpu = <&CPU0>; 220 }; 221 222 core1 { 223 cpu = <&CPU1>; 224 }; 225 226 core2 { 227 cpu = <&CPU2>; 228 }; 229 230 core3 { 231 cpu = <&CPU3>; 232 }; 233 234 core4 { 235 cpu = <&CPU4>; 236 }; 237 238 core5 { 239 cpu = <&CPU5>; 240 }; 241 242 core6 { 243 cpu = <&CPU6>; 244 }; 245 246 core7 { 247 cpu = <&CPU7>; 248 }; 249 }; 250 }; 251 252 idle-states { 253 entry-method = "psci"; 254 255 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 256 compatible = "arm,idle-state"; 257 idle-state-name = "little-rail-power-collapse"; 258 arm,psci-suspend-param = <0x40000004>; 259 entry-latency-us = <355>; 260 exit-latency-us = <909>; 261 min-residency-us = <3934>; 262 local-timer-stop; 263 }; 264 265 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 266 compatible = "arm,idle-state"; 267 idle-state-name = "big-rail-power-collapse"; 268 arm,psci-suspend-param = <0x40000004>; 269 entry-latency-us = <241>; 270 exit-latency-us = <1461>; 271 min-residency-us = <4488>; 272 local-timer-stop; 273 }; 274 }; 275 276 domain-idle-states { 277 CLUSTER_SLEEP_0: cluster-sleep-0 { 278 compatible = "domain-idle-state"; 279 arm,psci-suspend-param = <0x4100c344>; 280 entry-latency-us = <3263>; 281 exit-latency-us = <6562>; 282 min-residency-us = <9987>; 283 }; 284 }; 285 }; 286 287 firmware { 288 scm: scm { 289 compatible = "qcom,scm-sc8280xp", "qcom,scm"; 290 }; 291 }; 292 293 aggre1_noc: interconnect-aggre1-noc { 294 compatible = "qcom,sc8280xp-aggre1-noc"; 295 #interconnect-cells = <2>; 296 qcom,bcm-voters = <&apps_bcm_voter>; 297 }; 298 299 aggre2_noc: interconnect-aggre2-noc { 300 compatible = "qcom,sc8280xp-aggre2-noc"; 301 #interconnect-cells = <2>; 302 qcom,bcm-voters = <&apps_bcm_voter>; 303 }; 304 305 clk_virt: interconnect-clk-virt { 306 compatible = "qcom,sc8280xp-clk-virt"; 307 #interconnect-cells = <2>; 308 qcom,bcm-voters = <&apps_bcm_voter>; 309 }; 310 311 config_noc: interconnect-config-noc { 312 compatible = "qcom,sc8280xp-config-noc"; 313 #interconnect-cells = <2>; 314 qcom,bcm-voters = <&apps_bcm_voter>; 315 }; 316 317 dc_noc: interconnect-dc-noc { 318 compatible = "qcom,sc8280xp-dc-noc"; 319 #interconnect-cells = <2>; 320 qcom,bcm-voters = <&apps_bcm_voter>; 321 }; 322 323 gem_noc: interconnect-gem-noc { 324 compatible = "qcom,sc8280xp-gem-noc"; 325 #interconnect-cells = <2>; 326 qcom,bcm-voters = <&apps_bcm_voter>; 327 }; 328 329 lpass_noc: interconnect-lpass-ag-noc { 330 compatible = "qcom,sc8280xp-lpass-ag-noc"; 331 #interconnect-cells = <2>; 332 qcom,bcm-voters = <&apps_bcm_voter>; 333 }; 334 335 mc_virt: interconnect-mc-virt { 336 compatible = "qcom,sc8280xp-mc-virt"; 337 #interconnect-cells = <2>; 338 qcom,bcm-voters = <&apps_bcm_voter>; 339 }; 340 341 mmss_noc: interconnect-mmss-noc { 342 compatible = "qcom,sc8280xp-mmss-noc"; 343 #interconnect-cells = <2>; 344 qcom,bcm-voters = <&apps_bcm_voter>; 345 }; 346 347 nspa_noc: interconnect-nspa-noc { 348 compatible = "qcom,sc8280xp-nspa-noc"; 349 #interconnect-cells = <2>; 350 qcom,bcm-voters = <&apps_bcm_voter>; 351 }; 352 353 nspb_noc: interconnect-nspb-noc { 354 compatible = "qcom,sc8280xp-nspb-noc"; 355 #interconnect-cells = <2>; 356 qcom,bcm-voters = <&apps_bcm_voter>; 357 }; 358 359 system_noc: interconnect-system-noc { 360 compatible = "qcom,sc8280xp-system-noc"; 361 #interconnect-cells = <2>; 362 qcom,bcm-voters = <&apps_bcm_voter>; 363 }; 364 365 memory@80000000 { 366 device_type = "memory"; 367 /* We expect the bootloader to fill in the size */ 368 reg = <0x0 0x80000000 0x0 0x0>; 369 }; 370 371 cpu0_opp_table: opp-table-cpu0 { 372 compatible = "operating-points-v2"; 373 opp-shared; 374 375 opp-300000000 { 376 opp-hz = /bits/ 64 <300000000>; 377 opp-peak-kBps = <(300000 * 32)>; 378 }; 379 opp-403200000 { 380 opp-hz = /bits/ 64 <403200000>; 381 opp-peak-kBps = <(384000 * 32)>; 382 }; 383 opp-499200000 { 384 opp-hz = /bits/ 64 <499200000>; 385 opp-peak-kBps = <(480000 * 32)>; 386 }; 387 opp-595200000 { 388 opp-hz = /bits/ 64 <595200000>; 389 opp-peak-kBps = <(576000 * 32)>; 390 }; 391 opp-691200000 { 392 opp-hz = /bits/ 64 <691200000>; 393 opp-peak-kBps = <(672000 * 32)>; 394 }; 395 opp-806400000 { 396 opp-hz = /bits/ 64 <806400000>; 397 opp-peak-kBps = <(768000 * 32)>; 398 }; 399 opp-902400000 { 400 opp-hz = /bits/ 64 <902400000>; 401 opp-peak-kBps = <(864000 * 32)>; 402 }; 403 opp-1017600000 { 404 opp-hz = /bits/ 64 <1017600000>; 405 opp-peak-kBps = <(960000 * 32)>; 406 }; 407 opp-1113600000 { 408 opp-hz = /bits/ 64 <1113600000>; 409 opp-peak-kBps = <(1075200 * 32)>; 410 }; 411 opp-1209600000 { 412 opp-hz = /bits/ 64 <1209600000>; 413 opp-peak-kBps = <(1171200 * 32)>; 414 }; 415 opp-1324800000 { 416 opp-hz = /bits/ 64 <1324800000>; 417 opp-peak-kBps = <(1267200 * 32)>; 418 }; 419 opp-1440000000 { 420 opp-hz = /bits/ 64 <1440000000>; 421 opp-peak-kBps = <(1363200 * 32)>; 422 }; 423 opp-1555200000 { 424 opp-hz = /bits/ 64 <1555200000>; 425 opp-peak-kBps = <(1536000 * 32)>; 426 }; 427 opp-1670400000 { 428 opp-hz = /bits/ 64 <1670400000>; 429 opp-peak-kBps = <(1612800 * 32)>; 430 }; 431 opp-1785600000 { 432 opp-hz = /bits/ 64 <1785600000>; 433 opp-peak-kBps = <(1689600 * 32)>; 434 }; 435 opp-1881600000 { 436 opp-hz = /bits/ 64 <1881600000>; 437 opp-peak-kBps = <(1689600 * 32)>; 438 }; 439 opp-1996800000 { 440 opp-hz = /bits/ 64 <1996800000>; 441 opp-peak-kBps = <(1689600 * 32)>; 442 }; 443 opp-2112000000 { 444 opp-hz = /bits/ 64 <2112000000>; 445 opp-peak-kBps = <(1689600 * 32)>; 446 }; 447 opp-2227200000 { 448 opp-hz = /bits/ 64 <2227200000>; 449 opp-peak-kBps = <(1689600 * 32)>; 450 }; 451 opp-2342400000 { 452 opp-hz = /bits/ 64 <2342400000>; 453 opp-peak-kBps = <(1689600 * 32)>; 454 }; 455 opp-2438400000 { 456 opp-hz = /bits/ 64 <2438400000>; 457 opp-peak-kBps = <(1689600 * 32)>; 458 }; 459 }; 460 461 cpu4_opp_table: opp-table-cpu4 { 462 compatible = "operating-points-v2"; 463 opp-shared; 464 465 opp-825600000 { 466 opp-hz = /bits/ 64 <825600000>; 467 opp-peak-kBps = <(768000 * 32)>; 468 }; 469 opp-940800000 { 470 opp-hz = /bits/ 64 <940800000>; 471 opp-peak-kBps = <(864000 * 32)>; 472 }; 473 opp-1056000000 { 474 opp-hz = /bits/ 64 <1056000000>; 475 opp-peak-kBps = <(960000 * 32)>; 476 }; 477 opp-1171200000 { 478 opp-hz = /bits/ 64 <1171200000>; 479 opp-peak-kBps = <(1171200 * 32)>; 480 }; 481 opp-1286400000 { 482 opp-hz = /bits/ 64 <1286400000>; 483 opp-peak-kBps = <(1267200 * 32)>; 484 }; 485 opp-1401600000 { 486 opp-hz = /bits/ 64 <1401600000>; 487 opp-peak-kBps = <(1363200 * 32)>; 488 }; 489 opp-1516800000 { 490 opp-hz = /bits/ 64 <1516800000>; 491 opp-peak-kBps = <(1459200 * 32)>; 492 }; 493 opp-1632000000 { 494 opp-hz = /bits/ 64 <1632000000>; 495 opp-peak-kBps = <(1612800 * 32)>; 496 }; 497 opp-1747200000 { 498 opp-hz = /bits/ 64 <1747200000>; 499 opp-peak-kBps = <(1689600 * 32)>; 500 }; 501 opp-1862400000 { 502 opp-hz = /bits/ 64 <1862400000>; 503 opp-peak-kBps = <(1689600 * 32)>; 504 }; 505 opp-1977600000 { 506 opp-hz = /bits/ 64 <1977600000>; 507 opp-peak-kBps = <(1689600 * 32)>; 508 }; 509 opp-2073600000 { 510 opp-hz = /bits/ 64 <2073600000>; 511 opp-peak-kBps = <(1689600 * 32)>; 512 }; 513 opp-2169600000 { 514 opp-hz = /bits/ 64 <2169600000>; 515 opp-peak-kBps = <(1689600 * 32)>; 516 }; 517 opp-2284800000 { 518 opp-hz = /bits/ 64 <2284800000>; 519 opp-peak-kBps = <(1689600 * 32)>; 520 }; 521 opp-2400000000 { 522 opp-hz = /bits/ 64 <2400000000>; 523 opp-peak-kBps = <(1689600 * 32)>; 524 }; 525 opp-2496000000 { 526 opp-hz = /bits/ 64 <2496000000>; 527 opp-peak-kBps = <(1689600 * 32)>; 528 }; 529 opp-2592000000 { 530 opp-hz = /bits/ 64 <2592000000>; 531 opp-peak-kBps = <(1689600 * 32)>; 532 }; 533 opp-2688000000 { 534 opp-hz = /bits/ 64 <2688000000>; 535 opp-peak-kBps = <(1689600 * 32)>; 536 }; 537 opp-2803200000 { 538 opp-hz = /bits/ 64 <2803200000>; 539 opp-peak-kBps = <(1689600 * 32)>; 540 }; 541 opp-2899200000 { 542 opp-hz = /bits/ 64 <2899200000>; 543 opp-peak-kBps = <(1689600 * 32)>; 544 }; 545 opp-2995200000 { 546 opp-hz = /bits/ 64 <2995200000>; 547 opp-peak-kBps = <(1689600 * 32)>; 548 }; 549 }; 550 551 qup_opp_table_100mhz: opp-table-qup100mhz { 552 compatible = "operating-points-v2"; 553 554 opp-75000000 { 555 opp-hz = /bits/ 64 <75000000>; 556 required-opps = <&rpmhpd_opp_low_svs>; 557 }; 558 559 opp-100000000 { 560 opp-hz = /bits/ 64 <100000000>; 561 required-opps = <&rpmhpd_opp_svs>; 562 }; 563 }; 564 565 pmu { 566 compatible = "arm,armv8-pmuv3"; 567 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 568 }; 569 570 psci { 571 compatible = "arm,psci-1.0"; 572 method = "smc"; 573 574 CPU_PD0: power-domain-cpu0 { 575 #power-domain-cells = <0>; 576 power-domains = <&CLUSTER_PD>; 577 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 578 }; 579 580 CPU_PD1: power-domain-cpu1 { 581 #power-domain-cells = <0>; 582 power-domains = <&CLUSTER_PD>; 583 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 584 }; 585 586 CPU_PD2: power-domain-cpu2 { 587 #power-domain-cells = <0>; 588 power-domains = <&CLUSTER_PD>; 589 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 590 }; 591 592 CPU_PD3: power-domain-cpu3 { 593 #power-domain-cells = <0>; 594 power-domains = <&CLUSTER_PD>; 595 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 596 }; 597 598 CPU_PD4: power-domain-cpu4 { 599 #power-domain-cells = <0>; 600 power-domains = <&CLUSTER_PD>; 601 domain-idle-states = <&BIG_CPU_SLEEP_0>; 602 }; 603 604 CPU_PD5: power-domain-cpu5 { 605 #power-domain-cells = <0>; 606 power-domains = <&CLUSTER_PD>; 607 domain-idle-states = <&BIG_CPU_SLEEP_0>; 608 }; 609 610 CPU_PD6: power-domain-cpu6 { 611 #power-domain-cells = <0>; 612 power-domains = <&CLUSTER_PD>; 613 domain-idle-states = <&BIG_CPU_SLEEP_0>; 614 }; 615 616 CPU_PD7: power-domain-cpu7 { 617 #power-domain-cells = <0>; 618 power-domains = <&CLUSTER_PD>; 619 domain-idle-states = <&BIG_CPU_SLEEP_0>; 620 }; 621 622 CLUSTER_PD: power-domain-cpu-cluster0 { 623 #power-domain-cells = <0>; 624 domain-idle-states = <&CLUSTER_SLEEP_0>; 625 }; 626 }; 627 628 reserved-memory { 629 #address-cells = <2>; 630 #size-cells = <2>; 631 ranges; 632 633 reserved-region@80000000 { 634 reg = <0 0x80000000 0 0x860000>; 635 no-map; 636 }; 637 638 cmd_db: cmd-db-region@80860000 { 639 compatible = "qcom,cmd-db"; 640 reg = <0 0x80860000 0 0x20000>; 641 no-map; 642 }; 643 644 reserved-region@80880000 { 645 reg = <0 0x80880000 0 0x80000>; 646 no-map; 647 }; 648 649 smem_mem: smem-region@80900000 { 650 compatible = "qcom,smem"; 651 reg = <0 0x80900000 0 0x200000>; 652 no-map; 653 hwlocks = <&tcsr_mutex 3>; 654 }; 655 656 reserved-region@80b00000 { 657 reg = <0 0x80b00000 0 0x100000>; 658 no-map; 659 }; 660 661 reserved-region@83b00000 { 662 reg = <0 0x83b00000 0 0x1700000>; 663 no-map; 664 }; 665 666 reserved-region@85b00000 { 667 reg = <0 0x85b00000 0 0xc00000>; 668 no-map; 669 }; 670 671 pil_adsp_mem: adsp-region@86c00000 { 672 reg = <0 0x86c00000 0 0x2000000>; 673 no-map; 674 }; 675 676 pil_nsp0_mem: cdsp0-region@8a100000 { 677 reg = <0 0x8a100000 0 0x1e00000>; 678 no-map; 679 }; 680 681 pil_nsp1_mem: cdsp1-region@8c600000 { 682 reg = <0 0x8c600000 0 0x1e00000>; 683 no-map; 684 }; 685 686 reserved-region@aeb00000 { 687 reg = <0 0xaeb00000 0 0x16600000>; 688 no-map; 689 }; 690 }; 691 692 smp2p-adsp { 693 compatible = "qcom,smp2p"; 694 qcom,smem = <443>, <429>; 695 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 696 IPCC_MPROC_SIGNAL_SMP2P 697 IRQ_TYPE_EDGE_RISING>; 698 mboxes = <&ipcc IPCC_CLIENT_LPASS 699 IPCC_MPROC_SIGNAL_SMP2P>; 700 701 qcom,local-pid = <0>; 702 qcom,remote-pid = <2>; 703 704 smp2p_adsp_out: master-kernel { 705 qcom,entry-name = "master-kernel"; 706 #qcom,smem-state-cells = <1>; 707 }; 708 709 smp2p_adsp_in: slave-kernel { 710 qcom,entry-name = "slave-kernel"; 711 interrupt-controller; 712 #interrupt-cells = <2>; 713 }; 714 }; 715 716 smp2p-nsp0 { 717 compatible = "qcom,smp2p"; 718 qcom,smem = <94>, <432>; 719 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 720 IPCC_MPROC_SIGNAL_SMP2P 721 IRQ_TYPE_EDGE_RISING>; 722 mboxes = <&ipcc IPCC_CLIENT_CDSP 723 IPCC_MPROC_SIGNAL_SMP2P>; 724 725 qcom,local-pid = <0>; 726 qcom,remote-pid = <5>; 727 728 smp2p_nsp0_out: master-kernel { 729 qcom,entry-name = "master-kernel"; 730 #qcom,smem-state-cells = <1>; 731 }; 732 733 smp2p_nsp0_in: slave-kernel { 734 qcom,entry-name = "slave-kernel"; 735 interrupt-controller; 736 #interrupt-cells = <2>; 737 }; 738 }; 739 740 smp2p-nsp1 { 741 compatible = "qcom,smp2p"; 742 qcom,smem = <617>, <616>; 743 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1 744 IPCC_MPROC_SIGNAL_SMP2P 745 IRQ_TYPE_EDGE_RISING>; 746 mboxes = <&ipcc IPCC_CLIENT_NSP1 747 IPCC_MPROC_SIGNAL_SMP2P>; 748 749 qcom,local-pid = <0>; 750 qcom,remote-pid = <12>; 751 752 smp2p_nsp1_out: master-kernel { 753 qcom,entry-name = "master-kernel"; 754 #qcom,smem-state-cells = <1>; 755 }; 756 757 smp2p_nsp1_in: slave-kernel { 758 qcom,entry-name = "slave-kernel"; 759 interrupt-controller; 760 #interrupt-cells = <2>; 761 }; 762 }; 763 764 soc: soc@0 { 765 compatible = "simple-bus"; 766 #address-cells = <2>; 767 #size-cells = <2>; 768 ranges = <0 0 0 0 0x10 0>; 769 dma-ranges = <0 0 0 0 0x10 0>; 770 771 gcc: clock-controller@100000 { 772 compatible = "qcom,gcc-sc8280xp"; 773 reg = <0x0 0x00100000 0x0 0x1f0000>; 774 #clock-cells = <1>; 775 #reset-cells = <1>; 776 #power-domain-cells = <1>; 777 clocks = <&rpmhcc RPMH_CXO_CLK>, 778 <&sleep_clk>, 779 <0>, 780 <0>, 781 <0>, 782 <0>, 783 <0>, 784 <0>, 785 <&usb_0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 786 <0>, 787 <0>, 788 <0>, 789 <0>, 790 <0>, 791 <0>, 792 <0>, 793 <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 794 <0>, 795 <0>, 796 <0>, 797 <0>, 798 <0>, 799 <0>, 800 <0>, 801 <0>, 802 <0>, 803 <&pcie2a_phy>, 804 <&pcie2b_phy>, 805 <&pcie3a_phy>, 806 <&pcie3b_phy>, 807 <&pcie4_phy>, 808 <0>, 809 <0>; 810 power-domains = <&rpmhpd SC8280XP_CX>; 811 }; 812 813 ipcc: mailbox@408000 { 814 compatible = "qcom,sc8280xp-ipcc", "qcom,ipcc"; 815 reg = <0 0x00408000 0 0x1000>; 816 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 817 interrupt-controller; 818 #interrupt-cells = <3>; 819 #mbox-cells = <2>; 820 }; 821 822 qup2: geniqup@8c0000 { 823 compatible = "qcom,geni-se-qup"; 824 reg = <0 0x008c0000 0 0x2000>; 825 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 826 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 827 clock-names = "m-ahb", "s-ahb"; 828 iommus = <&apps_smmu 0xa3 0>; 829 830 #address-cells = <2>; 831 #size-cells = <2>; 832 ranges; 833 834 status = "disabled"; 835 836 i2c16: i2c@880000 { 837 compatible = "qcom,geni-i2c"; 838 reg = <0 0x00880000 0 0x4000>; 839 #address-cells = <1>; 840 #size-cells = <0>; 841 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 842 clock-names = "se"; 843 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 844 power-domains = <&rpmhpd SC8280XP_CX>; 845 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 846 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 847 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 848 interconnect-names = "qup-core", "qup-config", "qup-memory"; 849 status = "disabled"; 850 }; 851 852 spi16: spi@880000 { 853 compatible = "qcom,geni-spi"; 854 reg = <0 0x00880000 0 0x4000>; 855 #address-cells = <1>; 856 #size-cells = <0>; 857 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 858 clock-names = "se"; 859 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 860 power-domains = <&rpmhpd SC8280XP_CX>; 861 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 862 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 863 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 864 interconnect-names = "qup-core", "qup-config", "qup-memory"; 865 status = "disabled"; 866 }; 867 868 i2c17: i2c@884000 { 869 compatible = "qcom,geni-i2c"; 870 reg = <0 0x00884000 0 0x4000>; 871 #address-cells = <1>; 872 #size-cells = <0>; 873 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 874 clock-names = "se"; 875 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 876 power-domains = <&rpmhpd SC8280XP_CX>; 877 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 878 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 879 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 880 interconnect-names = "qup-core", "qup-config", "qup-memory"; 881 status = "disabled"; 882 }; 883 884 spi17: spi@884000 { 885 compatible = "qcom,geni-spi"; 886 reg = <0 0x00884000 0 0x4000>; 887 #address-cells = <1>; 888 #size-cells = <0>; 889 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 890 clock-names = "se"; 891 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 892 power-domains = <&rpmhpd SC8280XP_CX>; 893 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 894 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 895 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 896 interconnect-names = "qup-core", "qup-config", "qup-memory"; 897 status = "disabled"; 898 }; 899 900 uart17: serial@884000 { 901 compatible = "qcom,geni-uart"; 902 reg = <0 0x00884000 0 0x4000>; 903 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 904 clock-names = "se"; 905 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 906 operating-points-v2 = <&qup_opp_table_100mhz>; 907 power-domains = <&rpmhpd SC8280XP_CX>; 908 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 909 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>; 910 interconnect-names = "qup-core", "qup-config"; 911 status = "disabled"; 912 }; 913 914 i2c18: i2c@888000 { 915 compatible = "qcom,geni-i2c"; 916 reg = <0 0x00888000 0 0x4000>; 917 #address-cells = <1>; 918 #size-cells = <0>; 919 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 920 clock-names = "se"; 921 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 922 power-domains = <&rpmhpd SC8280XP_CX>; 923 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 924 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 925 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 926 interconnect-names = "qup-core", "qup-config", "qup-memory"; 927 status = "disabled"; 928 }; 929 930 spi18: spi@888000 { 931 compatible = "qcom,geni-spi"; 932 reg = <0 0x00888000 0 0x4000>; 933 #address-cells = <1>; 934 #size-cells = <0>; 935 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 936 clock-names = "se"; 937 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 938 power-domains = <&rpmhpd SC8280XP_CX>; 939 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 940 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 941 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 942 interconnect-names = "qup-core", "qup-config", "qup-memory"; 943 status = "disabled"; 944 }; 945 946 i2c19: i2c@88c000 { 947 compatible = "qcom,geni-i2c"; 948 reg = <0 0x0088c000 0 0x4000>; 949 #address-cells = <1>; 950 #size-cells = <0>; 951 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 952 clock-names = "se"; 953 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 954 power-domains = <&rpmhpd SC8280XP_CX>; 955 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 956 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 957 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 958 interconnect-names = "qup-core", "qup-config", "qup-memory"; 959 status = "disabled"; 960 }; 961 962 spi19: spi@88c000 { 963 compatible = "qcom,geni-spi"; 964 reg = <0 0x0088c000 0 0x4000>; 965 #address-cells = <1>; 966 #size-cells = <0>; 967 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 968 clock-names = "se"; 969 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 970 power-domains = <&rpmhpd SC8280XP_CX>; 971 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 972 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 973 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 974 interconnect-names = "qup-core", "qup-config", "qup-memory"; 975 status = "disabled"; 976 }; 977 978 i2c20: i2c@890000 { 979 compatible = "qcom,geni-i2c"; 980 reg = <0 0x00890000 0 0x4000>; 981 #address-cells = <1>; 982 #size-cells = <0>; 983 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 984 clock-names = "se"; 985 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 986 power-domains = <&rpmhpd SC8280XP_CX>; 987 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 988 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 989 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 990 interconnect-names = "qup-core", "qup-config", "qup-memory"; 991 status = "disabled"; 992 }; 993 994 spi20: spi@890000 { 995 compatible = "qcom,geni-spi"; 996 reg = <0 0x00890000 0 0x4000>; 997 #address-cells = <1>; 998 #size-cells = <0>; 999 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1000 clock-names = "se"; 1001 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1002 power-domains = <&rpmhpd SC8280XP_CX>; 1003 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1004 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1005 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1006 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1007 status = "disabled"; 1008 }; 1009 1010 i2c21: i2c@894000 { 1011 compatible = "qcom,geni-i2c"; 1012 reg = <0 0x00894000 0 0x4000>; 1013 clock-names = "se"; 1014 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1015 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1016 #address-cells = <1>; 1017 #size-cells = <0>; 1018 power-domains = <&rpmhpd SC8280XP_CX>; 1019 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1020 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1021 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1022 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1023 status = "disabled"; 1024 }; 1025 1026 spi21: spi@894000 { 1027 compatible = "qcom,geni-spi"; 1028 reg = <0 0x00894000 0 0x4000>; 1029 #address-cells = <1>; 1030 #size-cells = <0>; 1031 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1032 clock-names = "se"; 1033 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1034 power-domains = <&rpmhpd SC8280XP_CX>; 1035 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1036 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1037 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1038 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1039 status = "disabled"; 1040 }; 1041 1042 i2c22: i2c@898000 { 1043 compatible = "qcom,geni-i2c"; 1044 reg = <0 0x00898000 0 0x4000>; 1045 #address-cells = <1>; 1046 #size-cells = <0>; 1047 clock-names = "se"; 1048 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1049 interrupts = <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>; 1050 power-domains = <&rpmhpd SC8280XP_CX>; 1051 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1052 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1053 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1054 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1055 status = "disabled"; 1056 }; 1057 1058 spi22: spi@898000 { 1059 compatible = "qcom,geni-spi"; 1060 reg = <0 0x00898000 0 0x4000>; 1061 #address-cells = <1>; 1062 #size-cells = <0>; 1063 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1064 clock-names = "se"; 1065 interrupts = <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>; 1066 power-domains = <&rpmhpd SC8280XP_CX>; 1067 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1068 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1069 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1070 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1071 status = "disabled"; 1072 }; 1073 1074 i2c23: i2c@89c000 { 1075 compatible = "qcom,geni-i2c"; 1076 reg = <0 0x0089c000 0 0x4000>; 1077 #address-cells = <1>; 1078 #size-cells = <0>; 1079 clock-names = "se"; 1080 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1081 interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>; 1082 power-domains = <&rpmhpd SC8280XP_CX>; 1083 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1084 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1085 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1086 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1087 status = "disabled"; 1088 }; 1089 1090 spi23: spi@89c000 { 1091 compatible = "qcom,geni-spi"; 1092 reg = <0 0x0089c000 0 0x4000>; 1093 #address-cells = <1>; 1094 #size-cells = <0>; 1095 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1096 clock-names = "se"; 1097 interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>; 1098 power-domains = <&rpmhpd SC8280XP_CX>; 1099 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1100 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1101 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1102 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1103 status = "disabled"; 1104 }; 1105 }; 1106 1107 qup0: geniqup@9c0000 { 1108 compatible = "qcom,geni-se-qup"; 1109 reg = <0 0x009c0000 0 0x6000>; 1110 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1111 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1112 clock-names = "m-ahb", "s-ahb"; 1113 iommus = <&apps_smmu 0x563 0>; 1114 1115 #address-cells = <2>; 1116 #size-cells = <2>; 1117 ranges; 1118 1119 status = "disabled"; 1120 1121 i2c0: i2c@980000 { 1122 compatible = "qcom,geni-i2c"; 1123 reg = <0 0x00980000 0 0x4000>; 1124 #address-cells = <1>; 1125 #size-cells = <0>; 1126 clock-names = "se"; 1127 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1128 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1129 power-domains = <&rpmhpd SC8280XP_CX>; 1130 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1131 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1132 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1133 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1134 status = "disabled"; 1135 }; 1136 1137 spi0: spi@980000 { 1138 compatible = "qcom,geni-spi"; 1139 reg = <0 0x00980000 0 0x4000>; 1140 #address-cells = <1>; 1141 #size-cells = <0>; 1142 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1143 clock-names = "se"; 1144 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1145 power-domains = <&rpmhpd SC8280XP_CX>; 1146 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1147 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1148 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1149 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1150 status = "disabled"; 1151 }; 1152 1153 i2c1: i2c@984000 { 1154 compatible = "qcom,geni-i2c"; 1155 reg = <0 0x00984000 0 0x4000>; 1156 #address-cells = <1>; 1157 #size-cells = <0>; 1158 clock-names = "se"; 1159 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1160 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1161 power-domains = <&rpmhpd SC8280XP_CX>; 1162 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1163 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1164 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1165 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1166 status = "disabled"; 1167 }; 1168 1169 spi1: spi@984000 { 1170 compatible = "qcom,geni-spi"; 1171 reg = <0 0x00984000 0 0x4000>; 1172 #address-cells = <1>; 1173 #size-cells = <0>; 1174 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1175 clock-names = "se"; 1176 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1177 power-domains = <&rpmhpd SC8280XP_CX>; 1178 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1179 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1180 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1181 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1182 status = "disabled"; 1183 }; 1184 1185 i2c2: i2c@988000 { 1186 compatible = "qcom,geni-i2c"; 1187 reg = <0 0x00988000 0 0x4000>; 1188 #address-cells = <1>; 1189 #size-cells = <0>; 1190 clock-names = "se"; 1191 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1192 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1193 power-domains = <&rpmhpd SC8280XP_CX>; 1194 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1195 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1196 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1197 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1198 status = "disabled"; 1199 }; 1200 1201 spi2: spi@988000 { 1202 compatible = "qcom,geni-spi"; 1203 reg = <0 0x00988000 0 0x4000>; 1204 #address-cells = <1>; 1205 #size-cells = <0>; 1206 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1207 clock-names = "se"; 1208 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1209 power-domains = <&rpmhpd SC8280XP_CX>; 1210 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1211 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1212 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1213 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1214 status = "disabled"; 1215 }; 1216 1217 uart2: serial@988000 { 1218 compatible = "qcom,geni-uart"; 1219 reg = <0 0x00988000 0 0x4000>; 1220 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1221 clock-names = "se"; 1222 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1223 operating-points-v2 = <&qup_opp_table_100mhz>; 1224 power-domains = <&rpmhpd SC8280XP_CX>; 1225 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1226 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 1227 interconnect-names = "qup-core", "qup-config"; 1228 status = "disabled"; 1229 }; 1230 1231 i2c3: i2c@98c000 { 1232 compatible = "qcom,geni-i2c"; 1233 reg = <0 0x0098c000 0 0x4000>; 1234 #address-cells = <1>; 1235 #size-cells = <0>; 1236 clock-names = "se"; 1237 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1238 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1239 power-domains = <&rpmhpd SC8280XP_CX>; 1240 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1241 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1242 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1243 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1244 status = "disabled"; 1245 }; 1246 1247 spi3: spi@98c000 { 1248 compatible = "qcom,geni-spi"; 1249 reg = <0 0x0098c000 0 0x4000>; 1250 #address-cells = <1>; 1251 #size-cells = <0>; 1252 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1253 clock-names = "se"; 1254 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1255 power-domains = <&rpmhpd SC8280XP_CX>; 1256 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1257 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1258 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1259 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1260 status = "disabled"; 1261 }; 1262 1263 i2c4: i2c@990000 { 1264 compatible = "qcom,geni-i2c"; 1265 reg = <0 0x00990000 0 0x4000>; 1266 clock-names = "se"; 1267 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1268 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1269 #address-cells = <1>; 1270 #size-cells = <0>; 1271 power-domains = <&rpmhpd SC8280XP_CX>; 1272 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1273 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1274 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1275 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1276 status = "disabled"; 1277 }; 1278 1279 spi4: spi@990000 { 1280 compatible = "qcom,geni-spi"; 1281 reg = <0 0x00990000 0 0x4000>; 1282 #address-cells = <1>; 1283 #size-cells = <0>; 1284 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1285 clock-names = "se"; 1286 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1287 power-domains = <&rpmhpd SC8280XP_CX>; 1288 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1289 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1290 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1291 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1292 status = "disabled"; 1293 }; 1294 1295 i2c5: i2c@994000 { 1296 compatible = "qcom,geni-i2c"; 1297 reg = <0 0x00994000 0 0x4000>; 1298 #address-cells = <1>; 1299 #size-cells = <0>; 1300 clock-names = "se"; 1301 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1302 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1303 power-domains = <&rpmhpd SC8280XP_CX>; 1304 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1305 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1306 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1307 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1308 status = "disabled"; 1309 }; 1310 1311 spi5: spi@994000 { 1312 compatible = "qcom,geni-spi"; 1313 reg = <0 0x00994000 0 0x4000>; 1314 #address-cells = <1>; 1315 #size-cells = <0>; 1316 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1317 clock-names = "se"; 1318 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1319 power-domains = <&rpmhpd SC8280XP_CX>; 1320 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1321 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1322 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1323 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1324 status = "disabled"; 1325 }; 1326 1327 i2c6: i2c@998000 { 1328 compatible = "qcom,geni-i2c"; 1329 reg = <0 0x00998000 0 0x4000>; 1330 #address-cells = <1>; 1331 #size-cells = <0>; 1332 clock-names = "se"; 1333 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1334 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1335 power-domains = <&rpmhpd SC8280XP_CX>; 1336 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1337 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1338 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1339 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1340 status = "disabled"; 1341 }; 1342 1343 spi6: spi@998000 { 1344 compatible = "qcom,geni-spi"; 1345 reg = <0 0x00998000 0 0x4000>; 1346 #address-cells = <1>; 1347 #size-cells = <0>; 1348 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1349 clock-names = "se"; 1350 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1351 power-domains = <&rpmhpd SC8280XP_CX>; 1352 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1353 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1354 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1355 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1356 status = "disabled"; 1357 }; 1358 1359 i2c7: i2c@99c000 { 1360 compatible = "qcom,geni-i2c"; 1361 reg = <0 0x0099c000 0 0x4000>; 1362 #address-cells = <1>; 1363 #size-cells = <0>; 1364 clock-names = "se"; 1365 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1366 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1367 power-domains = <&rpmhpd SC8280XP_CX>; 1368 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1369 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1370 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1371 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1372 status = "disabled"; 1373 }; 1374 1375 spi7: spi@99c000 { 1376 compatible = "qcom,geni-spi"; 1377 reg = <0 0x0099c000 0 0x4000>; 1378 #address-cells = <1>; 1379 #size-cells = <0>; 1380 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1381 clock-names = "se"; 1382 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1383 power-domains = <&rpmhpd SC8280XP_CX>; 1384 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1385 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1386 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1387 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1388 status = "disabled"; 1389 }; 1390 }; 1391 1392 qup1: geniqup@ac0000 { 1393 compatible = "qcom,geni-se-qup"; 1394 reg = <0 0x00ac0000 0 0x6000>; 1395 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1396 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1397 clock-names = "m-ahb", "s-ahb"; 1398 iommus = <&apps_smmu 0x83 0>; 1399 1400 #address-cells = <2>; 1401 #size-cells = <2>; 1402 ranges; 1403 1404 status = "disabled"; 1405 1406 i2c8: i2c@a80000 { 1407 compatible = "qcom,geni-i2c"; 1408 reg = <0 0x00a80000 0 0x4000>; 1409 #address-cells = <1>; 1410 #size-cells = <0>; 1411 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1412 clock-names = "se"; 1413 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1414 power-domains = <&rpmhpd SC8280XP_CX>; 1415 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1416 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1417 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1418 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1419 status = "disabled"; 1420 }; 1421 1422 spi8: spi@a80000 { 1423 compatible = "qcom,geni-spi"; 1424 reg = <0 0x00a80000 0 0x4000>; 1425 #address-cells = <1>; 1426 #size-cells = <0>; 1427 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1428 clock-names = "se"; 1429 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1430 power-domains = <&rpmhpd SC8280XP_CX>; 1431 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1432 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1433 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1434 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1435 status = "disabled"; 1436 }; 1437 1438 i2c9: i2c@a84000 { 1439 compatible = "qcom,geni-i2c"; 1440 reg = <0 0x00a84000 0 0x4000>; 1441 #address-cells = <1>; 1442 #size-cells = <0>; 1443 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1444 clock-names = "se"; 1445 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1446 power-domains = <&rpmhpd SC8280XP_CX>; 1447 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1448 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1449 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1450 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1451 status = "disabled"; 1452 }; 1453 1454 spi9: spi@a84000 { 1455 compatible = "qcom,geni-spi"; 1456 reg = <0 0x00a84000 0 0x4000>; 1457 #address-cells = <1>; 1458 #size-cells = <0>; 1459 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1460 clock-names = "se"; 1461 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1462 power-domains = <&rpmhpd SC8280XP_CX>; 1463 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1464 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1465 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1466 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1467 status = "disabled"; 1468 }; 1469 1470 i2c10: i2c@a88000 { 1471 compatible = "qcom,geni-i2c"; 1472 reg = <0 0x00a88000 0 0x4000>; 1473 #address-cells = <1>; 1474 #size-cells = <0>; 1475 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1476 clock-names = "se"; 1477 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1478 power-domains = <&rpmhpd SC8280XP_CX>; 1479 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1480 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1481 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1482 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1483 status = "disabled"; 1484 }; 1485 1486 spi10: spi@a88000 { 1487 compatible = "qcom,geni-spi"; 1488 reg = <0 0x00a88000 0 0x4000>; 1489 #address-cells = <1>; 1490 #size-cells = <0>; 1491 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1492 clock-names = "se"; 1493 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1494 power-domains = <&rpmhpd SC8280XP_CX>; 1495 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1496 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1497 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1498 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1499 status = "disabled"; 1500 }; 1501 1502 i2c11: i2c@a8c000 { 1503 compatible = "qcom,geni-i2c"; 1504 reg = <0 0x00a8c000 0 0x4000>; 1505 #address-cells = <1>; 1506 #size-cells = <0>; 1507 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1508 clock-names = "se"; 1509 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1510 power-domains = <&rpmhpd SC8280XP_CX>; 1511 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1512 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1513 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1514 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1515 status = "disabled"; 1516 }; 1517 1518 spi11: spi@a8c000 { 1519 compatible = "qcom,geni-spi"; 1520 reg = <0 0x00a8c000 0 0x4000>; 1521 #address-cells = <1>; 1522 #size-cells = <0>; 1523 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1524 clock-names = "se"; 1525 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1526 power-domains = <&rpmhpd SC8280XP_CX>; 1527 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1528 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1529 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1530 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1531 status = "disabled"; 1532 }; 1533 1534 i2c12: i2c@a90000 { 1535 compatible = "qcom,geni-i2c"; 1536 reg = <0 0x00a90000 0 0x4000>; 1537 #address-cells = <1>; 1538 #size-cells = <0>; 1539 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1540 clock-names = "se"; 1541 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1542 power-domains = <&rpmhpd SC8280XP_CX>; 1543 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1544 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1545 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1546 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1547 status = "disabled"; 1548 }; 1549 1550 spi12: spi@a90000 { 1551 compatible = "qcom,geni-spi"; 1552 reg = <0 0x00a90000 0 0x4000>; 1553 #address-cells = <1>; 1554 #size-cells = <0>; 1555 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1556 clock-names = "se"; 1557 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1558 power-domains = <&rpmhpd SC8280XP_CX>; 1559 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1560 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1561 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1562 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1563 status = "disabled"; 1564 }; 1565 1566 i2c13: i2c@a94000 { 1567 compatible = "qcom,geni-i2c"; 1568 reg = <0 0x00a94000 0 0x4000>; 1569 #address-cells = <1>; 1570 #size-cells = <0>; 1571 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1572 clock-names = "se"; 1573 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1574 power-domains = <&rpmhpd SC8280XP_CX>; 1575 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1576 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1577 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1578 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1579 status = "disabled"; 1580 }; 1581 1582 spi13: spi@a94000 { 1583 compatible = "qcom,geni-spi"; 1584 reg = <0 0x00a94000 0 0x4000>; 1585 #address-cells = <1>; 1586 #size-cells = <0>; 1587 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1588 clock-names = "se"; 1589 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1590 power-domains = <&rpmhpd SC8280XP_CX>; 1591 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1592 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1593 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1594 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1595 status = "disabled"; 1596 }; 1597 1598 i2c14: i2c@a98000 { 1599 compatible = "qcom,geni-i2c"; 1600 reg = <0 0x00a98000 0 0x4000>; 1601 #address-cells = <1>; 1602 #size-cells = <0>; 1603 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1604 clock-names = "se"; 1605 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>; 1606 power-domains = <&rpmhpd SC8280XP_CX>; 1607 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1608 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1609 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1610 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1611 status = "disabled"; 1612 }; 1613 1614 spi14: spi@a98000 { 1615 compatible = "qcom,geni-spi"; 1616 reg = <0 0x00a98000 0 0x4000>; 1617 #address-cells = <1>; 1618 #size-cells = <0>; 1619 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1620 clock-names = "se"; 1621 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>; 1622 power-domains = <&rpmhpd SC8280XP_CX>; 1623 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1624 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1625 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1626 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1627 status = "disabled"; 1628 }; 1629 1630 i2c15: i2c@a9c000 { 1631 compatible = "qcom,geni-i2c"; 1632 reg = <0 0x00a9c000 0 0x4000>; 1633 #address-cells = <1>; 1634 #size-cells = <0>; 1635 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1636 clock-names = "se"; 1637 interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>; 1638 power-domains = <&rpmhpd SC8280XP_CX>; 1639 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1640 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1641 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1642 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1643 status = "disabled"; 1644 }; 1645 1646 spi15: spi@a9c000 { 1647 compatible = "qcom,geni-spi"; 1648 reg = <0 0x00a9c000 0 0x4000>; 1649 #address-cells = <1>; 1650 #size-cells = <0>; 1651 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1652 clock-names = "se"; 1653 interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>; 1654 power-domains = <&rpmhpd SC8280XP_CX>; 1655 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1656 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1657 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1658 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1659 status = "disabled"; 1660 }; 1661 }; 1662 1663 rng: rng@10d3000 { 1664 compatible = "qcom,prng-ee"; 1665 reg = <0 0x010d3000 0 0x1000>; 1666 clocks = <&rpmhcc RPMH_HWKM_CLK>; 1667 clock-names = "core"; 1668 }; 1669 1670 pcie4: pcie@1c00000 { 1671 device_type = "pci"; 1672 compatible = "qcom,pcie-sc8280xp"; 1673 reg = <0x0 0x01c00000 0x0 0x3000>, 1674 <0x0 0x30000000 0x0 0xf1d>, 1675 <0x0 0x30000f20 0x0 0xa8>, 1676 <0x0 0x30001000 0x0 0x1000>, 1677 <0x0 0x30100000 0x0 0x100000>, 1678 <0x0 0x01c03000 0x0 0x1000>; 1679 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 1680 #address-cells = <3>; 1681 #size-cells = <2>; 1682 ranges = <0x01000000 0x0 0x00000000 0x0 0x30200000 0x0 0x100000>, 1683 <0x02000000 0x0 0x30300000 0x0 0x30300000 0x0 0x1d00000>; 1684 bus-range = <0x00 0xff>; 1685 1686 dma-coherent; 1687 1688 linux,pci-domain = <6>; 1689 num-lanes = <1>; 1690 1691 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 1692 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1693 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 1694 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 1695 interrupt-names = "msi0", "msi1", "msi2", "msi3"; 1696 1697 #interrupt-cells = <1>; 1698 interrupt-map-mask = <0 0 0 0x7>; 1699 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 1700 <0 0 0 2 &intc 0 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 1701 <0 0 0 3 &intc 0 0 GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 1702 <0 0 0 4 &intc 0 0 GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 1703 1704 clocks = <&gcc GCC_PCIE_4_AUX_CLK>, 1705 <&gcc GCC_PCIE_4_CFG_AHB_CLK>, 1706 <&gcc GCC_PCIE_4_MSTR_AXI_CLK>, 1707 <&gcc GCC_PCIE_4_SLV_AXI_CLK>, 1708 <&gcc GCC_PCIE_4_SLV_Q2A_AXI_CLK>, 1709 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 1710 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, 1711 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>, 1712 <&gcc GCC_CNOC_PCIE4_QX_CLK>; 1713 clock-names = "aux", 1714 "cfg", 1715 "bus_master", 1716 "bus_slave", 1717 "slave_q2a", 1718 "ddrss_sf_tbu", 1719 "noc_aggr_4", 1720 "noc_aggr_south_sf", 1721 "cnoc_qx"; 1722 1723 assigned-clocks = <&gcc GCC_PCIE_4_AUX_CLK>; 1724 assigned-clock-rates = <19200000>; 1725 1726 interconnects = <&aggre2_noc MASTER_PCIE_4 0 &mc_virt SLAVE_EBI1 0>, 1727 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_4 0>; 1728 interconnect-names = "pcie-mem", "cpu-pcie"; 1729 1730 resets = <&gcc GCC_PCIE_4_BCR>; 1731 reset-names = "pci"; 1732 1733 power-domains = <&gcc PCIE_4_GDSC>; 1734 1735 phys = <&pcie4_phy>; 1736 phy-names = "pciephy"; 1737 1738 status = "disabled"; 1739 }; 1740 1741 pcie4_phy: phy@1c06000 { 1742 compatible = "qcom,sc8280xp-qmp-gen3x1-pcie-phy"; 1743 reg = <0x0 0x01c06000 0x0 0x2000>; 1744 1745 clocks = <&gcc GCC_PCIE_4_AUX_CLK>, 1746 <&gcc GCC_PCIE_4_CFG_AHB_CLK>, 1747 <&gcc GCC_PCIE_4_CLKREF_CLK>, 1748 <&gcc GCC_PCIE4_PHY_RCHNG_CLK>, 1749 <&gcc GCC_PCIE_4_PIPE_CLK>, 1750 <&gcc GCC_PCIE_4_PIPEDIV2_CLK>; 1751 clock-names = "aux", "cfg_ahb", "ref", "rchng", 1752 "pipe", "pipediv2"; 1753 1754 assigned-clocks = <&gcc GCC_PCIE4_PHY_RCHNG_CLK>; 1755 assigned-clock-rates = <100000000>; 1756 1757 power-domains = <&gcc PCIE_4_GDSC>; 1758 1759 resets = <&gcc GCC_PCIE_4_PHY_BCR>; 1760 reset-names = "phy"; 1761 1762 #clock-cells = <0>; 1763 clock-output-names = "pcie_4_pipe_clk"; 1764 1765 #phy-cells = <0>; 1766 1767 status = "disabled"; 1768 }; 1769 1770 pcie3b: pcie@1c08000 { 1771 device_type = "pci"; 1772 compatible = "qcom,pcie-sc8280xp"; 1773 reg = <0x0 0x01c08000 0x0 0x3000>, 1774 <0x0 0x32000000 0x0 0xf1d>, 1775 <0x0 0x32000f20 0x0 0xa8>, 1776 <0x0 0x32001000 0x0 0x1000>, 1777 <0x0 0x32100000 0x0 0x100000>, 1778 <0x0 0x01c0b000 0x0 0x1000>; 1779 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 1780 #address-cells = <3>; 1781 #size-cells = <2>; 1782 ranges = <0x01000000 0x0 0x00000000 0x0 0x32200000 0x0 0x100000>, 1783 <0x02000000 0x0 0x32300000 0x0 0x32300000 0x0 0x1d00000>; 1784 bus-range = <0x00 0xff>; 1785 1786 dma-coherent; 1787 1788 linux,pci-domain = <5>; 1789 num-lanes = <2>; 1790 1791 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1792 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1793 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1794 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 1795 interrupt-names = "msi0", "msi1", "msi2", "msi3"; 1796 1797 #interrupt-cells = <1>; 1798 interrupt-map-mask = <0 0 0 0x7>; 1799 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 526 IRQ_TYPE_LEVEL_HIGH>, 1800 <0 0 0 2 &intc 0 0 GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>, 1801 <0 0 0 3 &intc 0 0 GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH>, 1802 <0 0 0 4 &intc 0 0 GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>; 1803 1804 clocks = <&gcc GCC_PCIE_3B_AUX_CLK>, 1805 <&gcc GCC_PCIE_3B_CFG_AHB_CLK>, 1806 <&gcc GCC_PCIE_3B_MSTR_AXI_CLK>, 1807 <&gcc GCC_PCIE_3B_SLV_AXI_CLK>, 1808 <&gcc GCC_PCIE_3B_SLV_Q2A_AXI_CLK>, 1809 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 1810 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, 1811 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>; 1812 clock-names = "aux", 1813 "cfg", 1814 "bus_master", 1815 "bus_slave", 1816 "slave_q2a", 1817 "ddrss_sf_tbu", 1818 "noc_aggr_4", 1819 "noc_aggr_south_sf"; 1820 1821 assigned-clocks = <&gcc GCC_PCIE_3B_AUX_CLK>; 1822 assigned-clock-rates = <19200000>; 1823 1824 interconnects = <&aggre2_noc MASTER_PCIE_3B 0 &mc_virt SLAVE_EBI1 0>, 1825 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_3B 0>; 1826 interconnect-names = "pcie-mem", "cpu-pcie"; 1827 1828 resets = <&gcc GCC_PCIE_3B_BCR>; 1829 reset-names = "pci"; 1830 1831 power-domains = <&gcc PCIE_3B_GDSC>; 1832 1833 phys = <&pcie3b_phy>; 1834 phy-names = "pciephy"; 1835 1836 status = "disabled"; 1837 }; 1838 1839 pcie3b_phy: phy@1c0e000 { 1840 compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy"; 1841 reg = <0x0 0x01c0e000 0x0 0x2000>; 1842 1843 clocks = <&gcc GCC_PCIE_3B_AUX_CLK>, 1844 <&gcc GCC_PCIE_3B_CFG_AHB_CLK>, 1845 <&gcc GCC_PCIE_3A3B_CLKREF_CLK>, 1846 <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>, 1847 <&gcc GCC_PCIE_3B_PIPE_CLK>, 1848 <&gcc GCC_PCIE_3B_PIPEDIV2_CLK>; 1849 clock-names = "aux", "cfg_ahb", "ref", "rchng", 1850 "pipe", "pipediv2"; 1851 1852 assigned-clocks = <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>; 1853 assigned-clock-rates = <100000000>; 1854 1855 power-domains = <&gcc PCIE_3B_GDSC>; 1856 1857 resets = <&gcc GCC_PCIE_3B_PHY_BCR>; 1858 reset-names = "phy"; 1859 1860 #clock-cells = <0>; 1861 clock-output-names = "pcie_3b_pipe_clk"; 1862 1863 #phy-cells = <0>; 1864 1865 status = "disabled"; 1866 }; 1867 1868 pcie3a: pcie@1c10000 { 1869 device_type = "pci"; 1870 compatible = "qcom,pcie-sc8280xp"; 1871 reg = <0x0 0x01c10000 0x0 0x3000>, 1872 <0x0 0x34000000 0x0 0xf1d>, 1873 <0x0 0x34000f20 0x0 0xa8>, 1874 <0x0 0x34001000 0x0 0x1000>, 1875 <0x0 0x34100000 0x0 0x100000>, 1876 <0x0 0x01c13000 0x0 0x1000>; 1877 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 1878 #address-cells = <3>; 1879 #size-cells = <2>; 1880 ranges = <0x01000000 0x0 0x00000000 0x0 0x34200000 0x0 0x100000>, 1881 <0x02000000 0x0 0x34300000 0x0 0x34300000 0x0 0x1d00000>; 1882 bus-range = <0x00 0xff>; 1883 1884 dma-coherent; 1885 1886 linux,pci-domain = <4>; 1887 num-lanes = <4>; 1888 1889 interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 1890 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 1891 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 1892 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; 1893 interrupt-names = "msi0", "msi1", "msi2", "msi3"; 1894 1895 #interrupt-cells = <1>; 1896 interrupt-map-mask = <0 0 0 0x7>; 1897 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>, 1898 <0 0 0 2 &intc 0 0 GIC_SPI 542 IRQ_TYPE_LEVEL_HIGH>, 1899 <0 0 0 3 &intc 0 0 GIC_SPI 543 IRQ_TYPE_LEVEL_HIGH>, 1900 <0 0 0 4 &intc 0 0 GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>; 1901 1902 clocks = <&gcc GCC_PCIE_3A_AUX_CLK>, 1903 <&gcc GCC_PCIE_3A_CFG_AHB_CLK>, 1904 <&gcc GCC_PCIE_3A_MSTR_AXI_CLK>, 1905 <&gcc GCC_PCIE_3A_SLV_AXI_CLK>, 1906 <&gcc GCC_PCIE_3A_SLV_Q2A_AXI_CLK>, 1907 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 1908 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, 1909 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>; 1910 clock-names = "aux", 1911 "cfg", 1912 "bus_master", 1913 "bus_slave", 1914 "slave_q2a", 1915 "ddrss_sf_tbu", 1916 "noc_aggr_4", 1917 "noc_aggr_south_sf"; 1918 1919 assigned-clocks = <&gcc GCC_PCIE_3A_AUX_CLK>; 1920 assigned-clock-rates = <19200000>; 1921 1922 interconnects = <&aggre2_noc MASTER_PCIE_3A 0 &mc_virt SLAVE_EBI1 0>, 1923 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_3A 0>; 1924 interconnect-names = "pcie-mem", "cpu-pcie"; 1925 1926 resets = <&gcc GCC_PCIE_3A_BCR>; 1927 reset-names = "pci"; 1928 1929 power-domains = <&gcc PCIE_3A_GDSC>; 1930 1931 phys = <&pcie3a_phy>; 1932 phy-names = "pciephy"; 1933 1934 status = "disabled"; 1935 }; 1936 1937 pcie3a_phy: phy@1c14000 { 1938 compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy"; 1939 reg = <0x0 0x01c14000 0x0 0x2000>, 1940 <0x0 0x01c16000 0x0 0x2000>; 1941 1942 clocks = <&gcc GCC_PCIE_3A_AUX_CLK>, 1943 <&gcc GCC_PCIE_3A_CFG_AHB_CLK>, 1944 <&gcc GCC_PCIE_3A3B_CLKREF_CLK>, 1945 <&gcc GCC_PCIE3A_PHY_RCHNG_CLK>, 1946 <&gcc GCC_PCIE_3A_PIPE_CLK>, 1947 <&gcc GCC_PCIE_3A_PIPEDIV2_CLK>; 1948 clock-names = "aux", "cfg_ahb", "ref", "rchng", 1949 "pipe", "pipediv2"; 1950 1951 assigned-clocks = <&gcc GCC_PCIE3A_PHY_RCHNG_CLK>; 1952 assigned-clock-rates = <100000000>; 1953 1954 power-domains = <&gcc PCIE_3A_GDSC>; 1955 1956 resets = <&gcc GCC_PCIE_3A_PHY_BCR>; 1957 reset-names = "phy"; 1958 1959 qcom,4ln-config-sel = <&tcsr 0xa044 1>; 1960 1961 #clock-cells = <0>; 1962 clock-output-names = "pcie_3a_pipe_clk"; 1963 1964 #phy-cells = <0>; 1965 1966 status = "disabled"; 1967 }; 1968 1969 pcie2b: pcie@1c18000 { 1970 device_type = "pci"; 1971 compatible = "qcom,pcie-sc8280xp"; 1972 reg = <0x0 0x01c18000 0x0 0x3000>, 1973 <0x0 0x38000000 0x0 0xf1d>, 1974 <0x0 0x38000f20 0x0 0xa8>, 1975 <0x0 0x38001000 0x0 0x1000>, 1976 <0x0 0x38100000 0x0 0x100000>, 1977 <0x0 0x01c1b000 0x0 0x1000>; 1978 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 1979 #address-cells = <3>; 1980 #size-cells = <2>; 1981 ranges = <0x01000000 0x0 0x00000000 0x0 0x38200000 0x0 0x100000>, 1982 <0x02000000 0x0 0x38300000 0x0 0x38300000 0x0 0x1d00000>; 1983 bus-range = <0x00 0xff>; 1984 1985 dma-coherent; 1986 1987 linux,pci-domain = <3>; 1988 num-lanes = <2>; 1989 1990 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 1991 <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 1992 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 1993 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>; 1994 interrupt-names = "msi0", "msi1", "msi2", "msi3"; 1995 1996 #interrupt-cells = <1>; 1997 interrupt-map-mask = <0 0 0 0x7>; 1998 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, 1999 <0 0 0 2 &intc 0 0 GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, 2000 <0 0 0 3 &intc 0 0 GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, 2001 <0 0 0 4 &intc 0 0 GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>; 2002 2003 clocks = <&gcc GCC_PCIE_2B_AUX_CLK>, 2004 <&gcc GCC_PCIE_2B_CFG_AHB_CLK>, 2005 <&gcc GCC_PCIE_2B_MSTR_AXI_CLK>, 2006 <&gcc GCC_PCIE_2B_SLV_AXI_CLK>, 2007 <&gcc GCC_PCIE_2B_SLV_Q2A_AXI_CLK>, 2008 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 2009 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, 2010 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>; 2011 clock-names = "aux", 2012 "cfg", 2013 "bus_master", 2014 "bus_slave", 2015 "slave_q2a", 2016 "ddrss_sf_tbu", 2017 "noc_aggr_4", 2018 "noc_aggr_south_sf"; 2019 2020 assigned-clocks = <&gcc GCC_PCIE_2B_AUX_CLK>; 2021 assigned-clock-rates = <19200000>; 2022 2023 interconnects = <&aggre2_noc MASTER_PCIE_2B 0 &mc_virt SLAVE_EBI1 0>, 2024 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_2B 0>; 2025 interconnect-names = "pcie-mem", "cpu-pcie"; 2026 2027 resets = <&gcc GCC_PCIE_2B_BCR>; 2028 reset-names = "pci"; 2029 2030 power-domains = <&gcc PCIE_2B_GDSC>; 2031 2032 phys = <&pcie2b_phy>; 2033 phy-names = "pciephy"; 2034 2035 status = "disabled"; 2036 }; 2037 2038 pcie2b_phy: phy@1c1e000 { 2039 compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy"; 2040 reg = <0x0 0x01c1e000 0x0 0x2000>; 2041 2042 clocks = <&gcc GCC_PCIE_2B_AUX_CLK>, 2043 <&gcc GCC_PCIE_2B_CFG_AHB_CLK>, 2044 <&gcc GCC_PCIE_2A2B_CLKREF_CLK>, 2045 <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>, 2046 <&gcc GCC_PCIE_2B_PIPE_CLK>, 2047 <&gcc GCC_PCIE_2B_PIPEDIV2_CLK>; 2048 clock-names = "aux", "cfg_ahb", "ref", "rchng", 2049 "pipe", "pipediv2"; 2050 2051 assigned-clocks = <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>; 2052 assigned-clock-rates = <100000000>; 2053 2054 power-domains = <&gcc PCIE_2B_GDSC>; 2055 2056 resets = <&gcc GCC_PCIE_2B_PHY_BCR>; 2057 reset-names = "phy"; 2058 2059 #clock-cells = <0>; 2060 clock-output-names = "pcie_2b_pipe_clk"; 2061 2062 #phy-cells = <0>; 2063 2064 status = "disabled"; 2065 }; 2066 2067 pcie2a: pcie@1c20000 { 2068 device_type = "pci"; 2069 compatible = "qcom,pcie-sc8280xp"; 2070 reg = <0x0 0x01c20000 0x0 0x3000>, 2071 <0x0 0x3c000000 0x0 0xf1d>, 2072 <0x0 0x3c000f20 0x0 0xa8>, 2073 <0x0 0x3c001000 0x0 0x1000>, 2074 <0x0 0x3c100000 0x0 0x100000>, 2075 <0x0 0x01c23000 0x0 0x1000>; 2076 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 2077 #address-cells = <3>; 2078 #size-cells = <2>; 2079 ranges = <0x01000000 0x0 0x00000000 0x0 0x3c200000 0x0 0x100000>, 2080 <0x02000000 0x0 0x3c300000 0x0 0x3c300000 0x0 0x1d00000>; 2081 bus-range = <0x00 0xff>; 2082 2083 dma-coherent; 2084 2085 linux,pci-domain = <2>; 2086 num-lanes = <4>; 2087 2088 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 2089 <GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH>, 2090 <GIC_SPI 524 IRQ_TYPE_LEVEL_HIGH>, 2091 <GIC_SPI 525 IRQ_TYPE_LEVEL_HIGH>; 2092 interrupt-names = "msi0", "msi1", "msi2", "msi3"; 2093 2094 #interrupt-cells = <1>; 2095 interrupt-map-mask = <0 0 0 0x7>; 2096 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>, 2097 <0 0 0 2 &intc 0 0 GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>, 2098 <0 0 0 3 &intc 0 0 GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>, 2099 <0 0 0 4 &intc 0 0 GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>; 2100 2101 clocks = <&gcc GCC_PCIE_2A_AUX_CLK>, 2102 <&gcc GCC_PCIE_2A_CFG_AHB_CLK>, 2103 <&gcc GCC_PCIE_2A_MSTR_AXI_CLK>, 2104 <&gcc GCC_PCIE_2A_SLV_AXI_CLK>, 2105 <&gcc GCC_PCIE_2A_SLV_Q2A_AXI_CLK>, 2106 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 2107 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, 2108 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>; 2109 clock-names = "aux", 2110 "cfg", 2111 "bus_master", 2112 "bus_slave", 2113 "slave_q2a", 2114 "ddrss_sf_tbu", 2115 "noc_aggr_4", 2116 "noc_aggr_south_sf"; 2117 2118 assigned-clocks = <&gcc GCC_PCIE_2A_AUX_CLK>; 2119 assigned-clock-rates = <19200000>; 2120 2121 interconnects = <&aggre2_noc MASTER_PCIE_2A 0 &mc_virt SLAVE_EBI1 0>, 2122 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_2A 0>; 2123 interconnect-names = "pcie-mem", "cpu-pcie"; 2124 2125 resets = <&gcc GCC_PCIE_2A_BCR>; 2126 reset-names = "pci"; 2127 2128 power-domains = <&gcc PCIE_2A_GDSC>; 2129 2130 phys = <&pcie2a_phy>; 2131 phy-names = "pciephy"; 2132 2133 status = "disabled"; 2134 }; 2135 2136 pcie2a_phy: phy@1c24000 { 2137 compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy"; 2138 reg = <0x0 0x01c24000 0x0 0x2000>, 2139 <0x0 0x01c26000 0x0 0x2000>; 2140 2141 clocks = <&gcc GCC_PCIE_2A_AUX_CLK>, 2142 <&gcc GCC_PCIE_2A_CFG_AHB_CLK>, 2143 <&gcc GCC_PCIE_2A2B_CLKREF_CLK>, 2144 <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>, 2145 <&gcc GCC_PCIE_2A_PIPE_CLK>, 2146 <&gcc GCC_PCIE_2A_PIPEDIV2_CLK>; 2147 clock-names = "aux", "cfg_ahb", "ref", "rchng", 2148 "pipe", "pipediv2"; 2149 2150 assigned-clocks = <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>; 2151 assigned-clock-rates = <100000000>; 2152 2153 power-domains = <&gcc PCIE_2A_GDSC>; 2154 2155 resets = <&gcc GCC_PCIE_2A_PHY_BCR>; 2156 reset-names = "phy"; 2157 2158 qcom,4ln-config-sel = <&tcsr 0xa044 0>; 2159 2160 #clock-cells = <0>; 2161 clock-output-names = "pcie_2a_pipe_clk"; 2162 2163 #phy-cells = <0>; 2164 2165 status = "disabled"; 2166 }; 2167 2168 ufs_mem_hc: ufs@1d84000 { 2169 compatible = "qcom,sc8280xp-ufshc", "qcom,ufshc", 2170 "jedec,ufs-2.0"; 2171 reg = <0 0x01d84000 0 0x3000>; 2172 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2173 phys = <&ufs_mem_phy>; 2174 phy-names = "ufsphy"; 2175 lanes-per-direction = <2>; 2176 #reset-cells = <1>; 2177 resets = <&gcc GCC_UFS_PHY_BCR>; 2178 reset-names = "rst"; 2179 2180 power-domains = <&gcc UFS_PHY_GDSC>; 2181 required-opps = <&rpmhpd_opp_nom>; 2182 2183 iommus = <&apps_smmu 0xe0 0x0>; 2184 dma-coherent; 2185 2186 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 2187 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2188 <&gcc GCC_UFS_PHY_AHB_CLK>, 2189 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2190 <&gcc GCC_UFS_REF_CLKREF_CLK>, 2191 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2192 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2193 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 2194 clock-names = "core_clk", 2195 "bus_aggr_clk", 2196 "iface_clk", 2197 "core_clk_unipro", 2198 "ref_clk", 2199 "tx_lane0_sync_clk", 2200 "rx_lane0_sync_clk", 2201 "rx_lane1_sync_clk"; 2202 freq-table-hz = <75000000 300000000>, 2203 <0 0>, 2204 <0 0>, 2205 <75000000 300000000>, 2206 <0 0>, 2207 <0 0>, 2208 <0 0>, 2209 <0 0>; 2210 status = "disabled"; 2211 }; 2212 2213 ufs_mem_phy: phy@1d87000 { 2214 compatible = "qcom,sc8280xp-qmp-ufs-phy"; 2215 reg = <0 0x01d87000 0 0x1000>; 2216 2217 clocks = <&gcc GCC_UFS_CARD_CLKREF_CLK>, 2218 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 2219 clock-names = "ref", "ref_aux"; 2220 2221 power-domains = <&gcc UFS_PHY_GDSC>; 2222 2223 resets = <&ufs_mem_hc 0>; 2224 reset-names = "ufsphy"; 2225 2226 #phy-cells = <0>; 2227 2228 status = "disabled"; 2229 }; 2230 2231 ufs_card_hc: ufs@1da4000 { 2232 compatible = "qcom,sc8280xp-ufshc", "qcom,ufshc", 2233 "jedec,ufs-2.0"; 2234 reg = <0 0x01da4000 0 0x3000>; 2235 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 2236 phys = <&ufs_card_phy>; 2237 phy-names = "ufsphy"; 2238 lanes-per-direction = <2>; 2239 #reset-cells = <1>; 2240 resets = <&gcc GCC_UFS_CARD_BCR>; 2241 reset-names = "rst"; 2242 2243 power-domains = <&gcc UFS_CARD_GDSC>; 2244 2245 iommus = <&apps_smmu 0x4a0 0x0>; 2246 dma-coherent; 2247 2248 clocks = <&gcc GCC_UFS_CARD_AXI_CLK>, 2249 <&gcc GCC_AGGRE_UFS_CARD_AXI_CLK>, 2250 <&gcc GCC_UFS_CARD_AHB_CLK>, 2251 <&gcc GCC_UFS_CARD_UNIPRO_CORE_CLK>, 2252 <&gcc GCC_UFS_REF_CLKREF_CLK>, 2253 <&gcc GCC_UFS_CARD_TX_SYMBOL_0_CLK>, 2254 <&gcc GCC_UFS_CARD_RX_SYMBOL_0_CLK>, 2255 <&gcc GCC_UFS_CARD_RX_SYMBOL_1_CLK>; 2256 clock-names = "core_clk", 2257 "bus_aggr_clk", 2258 "iface_clk", 2259 "core_clk_unipro", 2260 "ref_clk", 2261 "tx_lane0_sync_clk", 2262 "rx_lane0_sync_clk", 2263 "rx_lane1_sync_clk"; 2264 freq-table-hz = <75000000 300000000>, 2265 <0 0>, 2266 <0 0>, 2267 <75000000 300000000>, 2268 <0 0>, 2269 <0 0>, 2270 <0 0>, 2271 <0 0>; 2272 status = "disabled"; 2273 }; 2274 2275 ufs_card_phy: phy@1da7000 { 2276 compatible = "qcom,sc8280xp-qmp-ufs-phy"; 2277 reg = <0 0x01da7000 0 0x1000>; 2278 2279 clocks = <&gcc GCC_UFS_1_CARD_CLKREF_CLK>, 2280 <&gcc GCC_UFS_CARD_PHY_AUX_CLK>; 2281 clock-names = "ref", "ref_aux"; 2282 2283 power-domains = <&gcc UFS_CARD_GDSC>; 2284 2285 resets = <&ufs_card_hc 0>; 2286 reset-names = "ufsphy"; 2287 2288 #phy-cells = <0>; 2289 2290 status = "disabled"; 2291 }; 2292 2293 tcsr_mutex: hwlock@1f40000 { 2294 compatible = "qcom,tcsr-mutex"; 2295 reg = <0x0 0x01f40000 0x0 0x20000>; 2296 #hwlock-cells = <1>; 2297 }; 2298 2299 tcsr: syscon@1fc0000 { 2300 compatible = "qcom,sc8280xp-tcsr", "syscon"; 2301 reg = <0x0 0x01fc0000 0x0 0x30000>; 2302 }; 2303 2304 usb_0_hsphy: phy@88e5000 { 2305 compatible = "qcom,sc8280xp-usb-hs-phy", 2306 "qcom,usb-snps-hs-5nm-phy"; 2307 reg = <0 0x088e5000 0 0x400>; 2308 clocks = <&rpmhcc RPMH_CXO_CLK>; 2309 clock-names = "ref"; 2310 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2311 2312 #phy-cells = <0>; 2313 2314 status = "disabled"; 2315 }; 2316 2317 usb_2_hsphy0: phy@88e7000 { 2318 compatible = "qcom,sc8280xp-usb-hs-phy", 2319 "qcom,usb-snps-hs-5nm-phy"; 2320 reg = <0 0x088e7000 0 0x400>; 2321 clocks = <&gcc GCC_USB2_HS0_CLKREF_CLK>; 2322 clock-names = "ref"; 2323 resets = <&gcc GCC_QUSB2PHY_HS0_MP_BCR>; 2324 2325 #phy-cells = <0>; 2326 2327 status = "disabled"; 2328 }; 2329 2330 usb_2_hsphy1: phy@88e8000 { 2331 compatible = "qcom,sc8280xp-usb-hs-phy", 2332 "qcom,usb-snps-hs-5nm-phy"; 2333 reg = <0 0x088e8000 0 0x400>; 2334 clocks = <&gcc GCC_USB2_HS1_CLKREF_CLK>; 2335 clock-names = "ref"; 2336 resets = <&gcc GCC_QUSB2PHY_HS1_MP_BCR>; 2337 2338 #phy-cells = <0>; 2339 2340 status = "disabled"; 2341 }; 2342 2343 usb_2_hsphy2: phy@88e9000 { 2344 compatible = "qcom,sc8280xp-usb-hs-phy", 2345 "qcom,usb-snps-hs-5nm-phy"; 2346 reg = <0 0x088e9000 0 0x400>; 2347 clocks = <&gcc GCC_USB2_HS2_CLKREF_CLK>; 2348 clock-names = "ref"; 2349 resets = <&gcc GCC_QUSB2PHY_HS2_MP_BCR>; 2350 2351 #phy-cells = <0>; 2352 2353 status = "disabled"; 2354 }; 2355 2356 usb_2_hsphy3: phy@88ea000 { 2357 compatible = "qcom,sc8280xp-usb-hs-phy", 2358 "qcom,usb-snps-hs-5nm-phy"; 2359 reg = <0 0x088ea000 0 0x400>; 2360 clocks = <&gcc GCC_USB2_HS3_CLKREF_CLK>; 2361 clock-names = "ref"; 2362 resets = <&gcc GCC_QUSB2PHY_HS3_MP_BCR>; 2363 2364 #phy-cells = <0>; 2365 2366 status = "disabled"; 2367 }; 2368 2369 usb_2_qmpphy0: phy@88ef000 { 2370 compatible = "qcom,sc8280xp-qmp-usb3-uni-phy"; 2371 reg = <0 0x088ef000 0 0x2000>; 2372 2373 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, 2374 <&gcc GCC_USB3_MP0_CLKREF_CLK>, 2375 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, 2376 <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>; 2377 clock-names = "aux", "ref", "com_aux", "pipe"; 2378 2379 resets = <&gcc GCC_USB3_UNIPHY_MP0_BCR>, 2380 <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>; 2381 reset-names = "phy", "phy_phy"; 2382 2383 power-domains = <&gcc USB30_MP_GDSC>; 2384 2385 #clock-cells = <0>; 2386 clock-output-names = "usb2_phy0_pipe_clk"; 2387 2388 #phy-cells = <0>; 2389 2390 status = "disabled"; 2391 }; 2392 2393 usb_2_qmpphy1: phy@88f1000 { 2394 compatible = "qcom,sc8280xp-qmp-usb3-uni-phy"; 2395 reg = <0 0x088f1000 0 0x2000>; 2396 2397 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, 2398 <&gcc GCC_USB3_MP1_CLKREF_CLK>, 2399 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, 2400 <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>; 2401 clock-names = "aux", "ref", "com_aux", "pipe"; 2402 2403 resets = <&gcc GCC_USB3_UNIPHY_MP1_BCR>, 2404 <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>; 2405 reset-names = "phy", "phy_phy"; 2406 2407 power-domains = <&gcc USB30_MP_GDSC>; 2408 2409 #clock-cells = <0>; 2410 clock-output-names = "usb2_phy1_pipe_clk"; 2411 2412 #phy-cells = <0>; 2413 2414 status = "disabled"; 2415 }; 2416 2417 remoteproc_adsp: remoteproc@3000000 { 2418 compatible = "qcom,sc8280xp-adsp-pas"; 2419 reg = <0 0x03000000 0 0x100>; 2420 2421 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, 2422 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 2423 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 2424 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 2425 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>, 2426 <&smp2p_adsp_in 7 IRQ_TYPE_EDGE_RISING>; 2427 interrupt-names = "wdog", "fatal", "ready", 2428 "handover", "stop-ack", "shutdown-ack"; 2429 2430 clocks = <&rpmhcc RPMH_CXO_CLK>; 2431 clock-names = "xo"; 2432 2433 power-domains = <&rpmhpd SC8280XP_LCX>, 2434 <&rpmhpd SC8280XP_LMX>; 2435 power-domain-names = "lcx", "lmx"; 2436 2437 memory-region = <&pil_adsp_mem>; 2438 2439 qcom,qmp = <&aoss_qmp>; 2440 2441 qcom,smem-states = <&smp2p_adsp_out 0>; 2442 qcom,smem-state-names = "stop"; 2443 2444 status = "disabled"; 2445 2446 remoteproc_adsp_glink: glink-edge { 2447 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 2448 IPCC_MPROC_SIGNAL_GLINK_QMP 2449 IRQ_TYPE_EDGE_RISING>; 2450 mboxes = <&ipcc IPCC_CLIENT_LPASS 2451 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2452 2453 label = "lpass"; 2454 qcom,remote-pid = <2>; 2455 2456 gpr { 2457 compatible = "qcom,gpr"; 2458 qcom,glink-channels = "adsp_apps"; 2459 qcom,domain = <GPR_DOMAIN_ID_ADSP>; 2460 qcom,intents = <512 20>; 2461 #address-cells = <1>; 2462 #size-cells = <0>; 2463 2464 q6apm: service@1 { 2465 compatible = "qcom,q6apm"; 2466 reg = <GPR_APM_MODULE_IID>; 2467 #sound-dai-cells = <0>; 2468 qcom,protection-domain = "avs/audio", 2469 "msm/adsp/audio_pd"; 2470 q6apmdai: dais { 2471 compatible = "qcom,q6apm-dais"; 2472 iommus = <&apps_smmu 0x0c01 0x0>; 2473 }; 2474 2475 q6apmbedai: bedais { 2476 compatible = "qcom,q6apm-lpass-dais"; 2477 #sound-dai-cells = <1>; 2478 }; 2479 }; 2480 2481 q6prm: service@2 { 2482 compatible = "qcom,q6prm"; 2483 reg = <GPR_PRM_MODULE_IID>; 2484 qcom,protection-domain = "avs/audio", 2485 "msm/adsp/audio_pd"; 2486 q6prmcc: clock-controller { 2487 compatible = "qcom,q6prm-lpass-clocks"; 2488 #clock-cells = <2>; 2489 }; 2490 }; 2491 }; 2492 }; 2493 }; 2494 2495 rxmacro: rxmacro@3200000 { 2496 compatible = "qcom,sc8280xp-lpass-rx-macro"; 2497 reg = <0 0x03200000 0 0x1000>; 2498 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2499 <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2500 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2501 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2502 <&vamacro>; 2503 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2504 assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2505 <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2506 assigned-clock-rates = <19200000>, <19200000>; 2507 2508 clock-output-names = "mclk"; 2509 #clock-cells = <0>; 2510 #sound-dai-cells = <1>; 2511 2512 pinctrl-names = "default"; 2513 pinctrl-0 = <&rx_swr_default>; 2514 2515 status = "disabled"; 2516 }; 2517 2518 swr1: soundwire-controller@3210000 { 2519 compatible = "qcom,soundwire-v1.6.0"; 2520 reg = <0 0x03210000 0 0x2000>; 2521 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 2522 clocks = <&rxmacro>; 2523 clock-names = "iface"; 2524 label = "RX"; 2525 2526 qcom,din-ports = <0>; 2527 qcom,dout-ports = <5>; 2528 2529 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>; 2530 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0B 0x01 0x00>; 2531 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0B 0x00 0x00>; 2532 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0x00 0xff 0xff>; 2533 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0x0f 0xff 0xff>; 2534 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>; 2535 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff>; 2536 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; 2537 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 2538 2539 #sound-dai-cells = <1>; 2540 #address-cells = <2>; 2541 #size-cells = <0>; 2542 2543 status = "disabled"; 2544 }; 2545 2546 txmacro: txmacro@3220000 { 2547 compatible = "qcom,sc8280xp-lpass-tx-macro"; 2548 reg = <0 0x03220000 0 0x1000>; 2549 pinctrl-names = "default"; 2550 pinctrl-0 = <&tx_swr_default>; 2551 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2552 <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2553 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2554 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2555 <&vamacro>; 2556 2557 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2558 assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2559 <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2560 assigned-clock-rates = <19200000>, <19200000>; 2561 clock-output-names = "mclk"; 2562 2563 #clock-cells = <0>; 2564 #sound-dai-cells = <1>; 2565 2566 status = "disabled"; 2567 }; 2568 2569 wsamacro: codec@3240000 { 2570 compatible = "qcom,sc8280xp-lpass-wsa-macro"; 2571 reg = <0 0x03240000 0 0x1000>; 2572 clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2573 <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2574 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2575 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2576 <&vamacro>; 2577 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2578 assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2579 <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2580 assigned-clock-rates = <19200000>, <19200000>; 2581 2582 #clock-cells = <0>; 2583 clock-output-names = "mclk"; 2584 #sound-dai-cells = <1>; 2585 2586 pinctrl-names = "default"; 2587 pinctrl-0 = <&wsa_swr_default>; 2588 2589 status = "disabled"; 2590 }; 2591 2592 swr0: soundwire-controller@3250000 { 2593 reg = <0 0x03250000 0 0x2000>; 2594 compatible = "qcom,soundwire-v1.6.0"; 2595 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 2596 clocks = <&wsamacro>; 2597 clock-names = "iface"; 2598 label = "WSA"; 2599 2600 qcom,din-ports = <2>; 2601 qcom,dout-ports = <6>; 2602 2603 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>; 2604 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>; 2605 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>; 2606 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2607 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2608 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2609 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>; 2610 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2611 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2612 2613 #sound-dai-cells = <1>; 2614 #address-cells = <2>; 2615 #size-cells = <0>; 2616 2617 status = "disabled"; 2618 }; 2619 2620 swr2: soundwire-controller@3330000 { 2621 compatible = "qcom,soundwire-v1.6.0"; 2622 reg = <0 0x03330000 0 0x2000>; 2623 interrupts = <GIC_SPI 959 IRQ_TYPE_LEVEL_HIGH>, 2624 <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>; 2625 interrupt-names = "core", "wakeup"; 2626 2627 clocks = <&txmacro>; 2628 clock-names = "iface"; 2629 label = "TX"; 2630 #sound-dai-cells = <1>; 2631 #address-cells = <2>; 2632 #size-cells = <0>; 2633 2634 qcom,din-ports = <4>; 2635 qcom,dout-ports = <0>; 2636 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>; 2637 qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02 0x00>; 2638 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>; 2639 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>; 2640 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>; 2641 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>; 2642 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>; 2643 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>; 2644 qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00 0x01>; 2645 2646 status = "disabled"; 2647 }; 2648 2649 vamacro: codec@3370000 { 2650 compatible = "qcom,sc8280xp-lpass-va-macro"; 2651 reg = <0 0x03370000 0 0x1000>; 2652 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2653 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2654 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2655 <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2656 clock-names = "mclk", "macro", "dcodec", "npl"; 2657 assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2658 assigned-clock-rates = <19200000>; 2659 2660 #clock-cells = <0>; 2661 clock-output-names = "fsgen"; 2662 #sound-dai-cells = <1>; 2663 2664 status = "disabled"; 2665 }; 2666 2667 lpass_tlmm: pinctrl@33c0000 { 2668 compatible = "qcom,sc8280xp-lpass-lpi-pinctrl"; 2669 reg = <0 0x33c0000 0x0 0x20000>, 2670 <0 0x3550000 0x0 0x10000>; 2671 gpio-controller; 2672 #gpio-cells = <2>; 2673 gpio-ranges = <&lpass_tlmm 0 0 19>; 2674 2675 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2676 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2677 clock-names = "core", "audio"; 2678 2679 status = "disabled"; 2680 2681 tx_swr_default: tx-swr-default-state { 2682 clk-pins { 2683 pins = "gpio0"; 2684 function = "swr_tx_clk"; 2685 drive-strength = <2>; 2686 slew-rate = <1>; 2687 bias-disable; 2688 }; 2689 2690 data-pins { 2691 pins = "gpio1", "gpio2"; 2692 function = "swr_tx_data"; 2693 drive-strength = <2>; 2694 slew-rate = <1>; 2695 bias-bus-hold; 2696 }; 2697 }; 2698 2699 rx_swr_default: rx-swr-default-state { 2700 clk-pins { 2701 pins = "gpio3"; 2702 function = "swr_rx_clk"; 2703 drive-strength = <2>; 2704 slew-rate = <1>; 2705 bias-disable; 2706 }; 2707 2708 data-pins { 2709 pins = "gpio4", "gpio5"; 2710 function = "swr_rx_data"; 2711 drive-strength = <2>; 2712 slew-rate = <1>; 2713 bias-bus-hold; 2714 }; 2715 }; 2716 2717 dmic01_default: dmic01-default-state { 2718 clk-pins { 2719 pins = "gpio6"; 2720 function = "dmic1_clk"; 2721 drive-strength = <8>; 2722 output-high; 2723 }; 2724 2725 data-pins { 2726 pins = "gpio7"; 2727 function = "dmic1_data"; 2728 drive-strength = <8>; 2729 }; 2730 }; 2731 2732 dmic01_sleep: dmic01-sleep-state { 2733 clk-pins { 2734 pins = "gpio6"; 2735 function = "dmic1_clk"; 2736 drive-strength = <2>; 2737 bias-disable; 2738 output-low; 2739 }; 2740 2741 data-pins { 2742 pins = "gpio7"; 2743 function = "dmic1_data"; 2744 drive-strength = <2>; 2745 bias-pull-down; 2746 }; 2747 }; 2748 2749 dmic02_default: dmic02-default-state { 2750 clk-pins { 2751 pins = "gpio8"; 2752 function = "dmic2_clk"; 2753 drive-strength = <8>; 2754 output-high; 2755 }; 2756 2757 data-pins { 2758 pins = "gpio9"; 2759 function = "dmic2_data"; 2760 drive-strength = <8>; 2761 }; 2762 }; 2763 2764 dmic02_sleep: dmic02-sleep-state { 2765 clk-pins { 2766 pins = "gpio8"; 2767 function = "dmic2_clk"; 2768 drive-strength = <2>; 2769 bias-disable; 2770 output-low; 2771 }; 2772 2773 data-pins { 2774 pins = "gpio9"; 2775 function = "dmic2_data"; 2776 drive-strength = <2>; 2777 bias-pull-down; 2778 }; 2779 }; 2780 2781 wsa_swr_default: wsa-swr-default-state { 2782 clk-pins { 2783 pins = "gpio10"; 2784 function = "wsa_swr_clk"; 2785 drive-strength = <2>; 2786 slew-rate = <1>; 2787 bias-disable; 2788 }; 2789 2790 data-pins { 2791 pins = "gpio11"; 2792 function = "wsa_swr_data"; 2793 drive-strength = <2>; 2794 slew-rate = <1>; 2795 bias-bus-hold; 2796 }; 2797 }; 2798 2799 wsa2_swr_default: wsa2-swr-default-state { 2800 clk-pins { 2801 pins = "gpio15"; 2802 function = "wsa2_swr_clk"; 2803 drive-strength = <2>; 2804 slew-rate = <1>; 2805 bias-disable; 2806 }; 2807 2808 data-pins { 2809 pins = "gpio16"; 2810 function = "wsa2_swr_data"; 2811 drive-strength = <2>; 2812 slew-rate = <1>; 2813 bias-bus-hold; 2814 }; 2815 }; 2816 }; 2817 2818 usb_0_qmpphy: phy@88eb000 { 2819 compatible = "qcom,sc8280xp-qmp-usb43dp-phy"; 2820 reg = <0 0x088eb000 0 0x4000>; 2821 2822 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2823 <&gcc GCC_USB4_EUD_CLKREF_CLK>, 2824 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 2825 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2826 clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 2827 2828 power-domains = <&gcc USB30_PRIM_GDSC>; 2829 2830 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 2831 <&gcc GCC_USB4_DP_PHY_PRIM_BCR>; 2832 reset-names = "phy", "common"; 2833 2834 #clock-cells = <1>; 2835 #phy-cells = <1>; 2836 2837 status = "disabled"; 2838 }; 2839 2840 usb_1_hsphy: phy@8902000 { 2841 compatible = "qcom,sc8280xp-usb-hs-phy", 2842 "qcom,usb-snps-hs-5nm-phy"; 2843 reg = <0 0x08902000 0 0x400>; 2844 #phy-cells = <0>; 2845 2846 clocks = <&rpmhcc RPMH_CXO_CLK>; 2847 clock-names = "ref"; 2848 2849 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 2850 2851 status = "disabled"; 2852 }; 2853 2854 usb_1_qmpphy: phy@8903000 { 2855 compatible = "qcom,sc8280xp-qmp-usb43dp-phy"; 2856 reg = <0 0x08903000 0 0x4000>; 2857 2858 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 2859 <&gcc GCC_USB4_CLKREF_CLK>, 2860 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, 2861 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 2862 clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 2863 2864 power-domains = <&gcc USB30_SEC_GDSC>; 2865 2866 resets = <&gcc GCC_USB3_PHY_SEC_BCR>, 2867 <&gcc GCC_USB4_1_DP_PHY_PRIM_BCR>; 2868 reset-names = "phy", "common"; 2869 2870 #clock-cells = <1>; 2871 #phy-cells = <1>; 2872 2873 status = "disabled"; 2874 }; 2875 2876 mdss1_dp0_phy: phy@8909a00 { 2877 compatible = "qcom,sc8280xp-dp-phy"; 2878 reg = <0 0x08909a00 0 0x19c>, 2879 <0 0x08909200 0 0xec>, 2880 <0 0x08909600 0 0xec>, 2881 <0 0x08909000 0 0x1c8>; 2882 2883 clocks = <&dispcc1 DISP_CC_MDSS_DPTX0_AUX_CLK>, 2884 <&dispcc1 DISP_CC_MDSS_AHB_CLK>; 2885 clock-names = "aux", "cfg_ahb"; 2886 power-domains = <&rpmhpd SC8280XP_MX>; 2887 2888 #clock-cells = <1>; 2889 #phy-cells = <0>; 2890 2891 status = "disabled"; 2892 }; 2893 2894 mdss1_dp1_phy: phy@890ca00 { 2895 compatible = "qcom,sc8280xp-dp-phy"; 2896 reg = <0 0x0890ca00 0 0x19c>, 2897 <0 0x0890c200 0 0xec>, 2898 <0 0x0890c600 0 0xec>, 2899 <0 0x0890c000 0 0x1c8>; 2900 2901 clocks = <&dispcc1 DISP_CC_MDSS_DPTX1_AUX_CLK>, 2902 <&dispcc1 DISP_CC_MDSS_AHB_CLK>; 2903 clock-names = "aux", "cfg_ahb"; 2904 power-domains = <&rpmhpd SC8280XP_MX>; 2905 2906 #clock-cells = <1>; 2907 #phy-cells = <0>; 2908 2909 status = "disabled"; 2910 }; 2911 2912 pmu@9091000 { 2913 compatible = "qcom,sc8280xp-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; 2914 reg = <0 0x09091000 0 0x1000>; 2915 2916 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 2917 2918 interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>; 2919 2920 operating-points-v2 = <&llcc_bwmon_opp_table>; 2921 2922 llcc_bwmon_opp_table: opp-table { 2923 compatible = "operating-points-v2"; 2924 2925 opp-0 { 2926 opp-peak-kBps = <762000>; 2927 }; 2928 opp-1 { 2929 opp-peak-kBps = <1720000>; 2930 }; 2931 opp-2 { 2932 opp-peak-kBps = <2086000>; 2933 }; 2934 opp-3 { 2935 opp-peak-kBps = <2597000>; 2936 }; 2937 opp-4 { 2938 opp-peak-kBps = <2929000>; 2939 }; 2940 opp-5 { 2941 opp-peak-kBps = <3879000>; 2942 }; 2943 opp-6 { 2944 opp-peak-kBps = <5161000>; 2945 }; 2946 opp-7 { 2947 opp-peak-kBps = <5931000>; 2948 }; 2949 opp-8 { 2950 opp-peak-kBps = <6515000>; 2951 }; 2952 opp-9 { 2953 opp-peak-kBps = <7980000>; 2954 }; 2955 opp-10 { 2956 opp-peak-kBps = <8136000>; 2957 }; 2958 opp-11 { 2959 opp-peak-kBps = <10437000>; 2960 }; 2961 opp-12 { 2962 opp-peak-kBps = <12191000>; 2963 }; 2964 }; 2965 }; 2966 2967 pmu@90b6400 { 2968 compatible = "qcom,sc8280xp-cpu-bwmon", "qcom,sdm845-bwmon"; 2969 reg = <0 0x090b6400 0 0x600>; 2970 2971 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 2972 2973 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>; 2974 operating-points-v2 = <&cpu_bwmon_opp_table>; 2975 2976 cpu_bwmon_opp_table: opp-table { 2977 compatible = "operating-points-v2"; 2978 2979 opp-0 { 2980 opp-peak-kBps = <2288000>; 2981 }; 2982 opp-1 { 2983 opp-peak-kBps = <4577000>; 2984 }; 2985 opp-2 { 2986 opp-peak-kBps = <7110000>; 2987 }; 2988 opp-3 { 2989 opp-peak-kBps = <9155000>; 2990 }; 2991 opp-4 { 2992 opp-peak-kBps = <12298000>; 2993 }; 2994 opp-5 { 2995 opp-peak-kBps = <14236000>; 2996 }; 2997 opp-6 { 2998 opp-peak-kBps = <15258001>; 2999 }; 3000 }; 3001 }; 3002 3003 system-cache-controller@9200000 { 3004 compatible = "qcom,sc8280xp-llcc"; 3005 reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, 3006 <0 0x09300000 0 0x58000>, <0 0x09380000 0 0x58000>, 3007 <0 0x09400000 0 0x58000>, <0 0x09480000 0 0x58000>, 3008 <0 0x09500000 0 0x58000>, <0 0x09580000 0 0x58000>, 3009 <0 0x09600000 0 0x58000>; 3010 reg-names = "llcc0_base", "llcc1_base", "llcc2_base", 3011 "llcc3_base", "llcc4_base", "llcc5_base", 3012 "llcc6_base", "llcc7_base", "llcc_broadcast_base"; 3013 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 3014 }; 3015 3016 usb_0: usb@a6f8800 { 3017 compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3"; 3018 reg = <0 0x0a6f8800 0 0x400>; 3019 #address-cells = <2>; 3020 #size-cells = <2>; 3021 ranges; 3022 3023 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3024 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3025 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3026 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 3027 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3028 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 3029 <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>, 3030 <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>, 3031 <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 3032 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", 3033 "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys"; 3034 3035 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3036 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3037 assigned-clock-rates = <19200000>, <200000000>; 3038 3039 interrupts-extended = <&intc GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>, 3040 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 3041 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 3042 <&pdc 138 IRQ_TYPE_LEVEL_HIGH>; 3043 interrupt-names = "pwr_event", 3044 "dp_hs_phy_irq", 3045 "dm_hs_phy_irq", 3046 "ss_phy_irq"; 3047 3048 power-domains = <&gcc USB30_PRIM_GDSC>; 3049 required-opps = <&rpmhpd_opp_nom>; 3050 3051 resets = <&gcc GCC_USB30_PRIM_BCR>; 3052 3053 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 3054 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; 3055 interconnect-names = "usb-ddr", "apps-usb"; 3056 3057 wakeup-source; 3058 3059 status = "disabled"; 3060 3061 usb_0_dwc3: usb@a600000 { 3062 compatible = "snps,dwc3"; 3063 reg = <0 0x0a600000 0 0xcd00>; 3064 interrupts = <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>; 3065 iommus = <&apps_smmu 0x820 0x0>; 3066 phys = <&usb_0_hsphy>, <&usb_0_qmpphy QMP_USB43DP_USB3_PHY>; 3067 phy-names = "usb2-phy", "usb3-phy"; 3068 3069 port { 3070 usb_0_role_switch: endpoint { 3071 }; 3072 }; 3073 }; 3074 }; 3075 3076 usb_1: usb@a8f8800 { 3077 compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3"; 3078 reg = <0 0x0a8f8800 0 0x400>; 3079 #address-cells = <2>; 3080 #size-cells = <2>; 3081 ranges; 3082 3083 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 3084 <&gcc GCC_USB30_SEC_MASTER_CLK>, 3085 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 3086 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 3087 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3088 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 3089 <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>, 3090 <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>, 3091 <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 3092 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", 3093 "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys"; 3094 3095 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3096 <&gcc GCC_USB30_SEC_MASTER_CLK>; 3097 assigned-clock-rates = <19200000>, <200000000>; 3098 3099 interrupts-extended = <&intc GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>, 3100 <&pdc 12 IRQ_TYPE_EDGE_BOTH>, 3101 <&pdc 13 IRQ_TYPE_EDGE_BOTH>, 3102 <&pdc 136 IRQ_TYPE_LEVEL_HIGH>; 3103 interrupt-names = "pwr_event", 3104 "dp_hs_phy_irq", 3105 "dm_hs_phy_irq", 3106 "ss_phy_irq"; 3107 3108 power-domains = <&gcc USB30_SEC_GDSC>; 3109 required-opps = <&rpmhpd_opp_nom>; 3110 3111 resets = <&gcc GCC_USB30_SEC_BCR>; 3112 3113 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>, 3114 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>; 3115 interconnect-names = "usb-ddr", "apps-usb"; 3116 3117 wakeup-source; 3118 3119 status = "disabled"; 3120 3121 usb_1_dwc3: usb@a800000 { 3122 compatible = "snps,dwc3"; 3123 reg = <0 0x0a800000 0 0xcd00>; 3124 interrupts = <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>; 3125 iommus = <&apps_smmu 0x860 0x0>; 3126 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 3127 phy-names = "usb2-phy", "usb3-phy"; 3128 3129 port { 3130 usb_1_role_switch: endpoint { 3131 }; 3132 }; 3133 }; 3134 }; 3135 3136 mdss0: display-subsystem@ae00000 { 3137 compatible = "qcom,sc8280xp-mdss"; 3138 reg = <0 0x0ae00000 0 0x1000>; 3139 reg-names = "mdss"; 3140 3141 clocks = <&gcc GCC_DISP_AHB_CLK>, 3142 <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 3143 <&dispcc0 DISP_CC_MDSS_MDP_CLK>; 3144 clock-names = "iface", 3145 "ahb", 3146 "core"; 3147 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 3148 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>, 3149 <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>; 3150 interconnect-names = "mdp0-mem", "mdp1-mem"; 3151 iommus = <&apps_smmu 0x1000 0x402>; 3152 power-domains = <&dispcc0 MDSS_GDSC>; 3153 resets = <&dispcc0 DISP_CC_MDSS_CORE_BCR>; 3154 3155 interrupt-controller; 3156 #interrupt-cells = <1>; 3157 #address-cells = <2>; 3158 #size-cells = <2>; 3159 ranges; 3160 3161 status = "disabled"; 3162 3163 mdss0_mdp: display-controller@ae01000 { 3164 compatible = "qcom,sc8280xp-dpu"; 3165 reg = <0 0x0ae01000 0 0x8f000>, 3166 <0 0x0aeb0000 0 0x2008>; 3167 reg-names = "mdp", "vbif"; 3168 3169 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 3170 <&gcc GCC_DISP_SF_AXI_CLK>, 3171 <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 3172 <&dispcc0 DISP_CC_MDSS_MDP_LUT_CLK>, 3173 <&dispcc0 DISP_CC_MDSS_MDP_CLK>, 3174 <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>; 3175 clock-names = "bus", 3176 "nrt_bus", 3177 "iface", 3178 "lut", 3179 "core", 3180 "vsync"; 3181 interrupt-parent = <&mdss0>; 3182 interrupts = <0>; 3183 power-domains = <&rpmhpd SC8280XP_MMCX>; 3184 3185 assigned-clocks = <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>; 3186 assigned-clock-rates = <19200000>; 3187 operating-points-v2 = <&mdss0_mdp_opp_table>; 3188 3189 ports { 3190 #address-cells = <1>; 3191 #size-cells = <0>; 3192 3193 port@0 { 3194 reg = <0>; 3195 mdss0_intf0_out: endpoint { 3196 remote-endpoint = <&mdss0_dp0_in>; 3197 }; 3198 }; 3199 3200 port@4 { 3201 reg = <4>; 3202 mdss0_intf4_out: endpoint { 3203 remote-endpoint = <&mdss0_dp1_in>; 3204 }; 3205 }; 3206 3207 port@5 { 3208 reg = <5>; 3209 mdss0_intf5_out: endpoint { 3210 remote-endpoint = <&mdss0_dp3_in>; 3211 }; 3212 }; 3213 3214 port@6 { 3215 reg = <6>; 3216 mdss0_intf6_out: endpoint { 3217 remote-endpoint = <&mdss0_dp2_in>; 3218 }; 3219 }; 3220 }; 3221 3222 mdss0_mdp_opp_table: opp-table { 3223 compatible = "operating-points-v2"; 3224 3225 opp-200000000 { 3226 opp-hz = /bits/ 64 <200000000>; 3227 required-opps = <&rpmhpd_opp_low_svs>; 3228 }; 3229 3230 opp-300000000 { 3231 opp-hz = /bits/ 64 <300000000>; 3232 required-opps = <&rpmhpd_opp_svs>; 3233 }; 3234 3235 opp-375000000 { 3236 opp-hz = /bits/ 64 <375000000>; 3237 required-opps = <&rpmhpd_opp_svs_l1>; 3238 }; 3239 3240 opp-500000000 { 3241 opp-hz = /bits/ 64 <500000000>; 3242 required-opps = <&rpmhpd_opp_nom>; 3243 }; 3244 opp-600000000 { 3245 opp-hz = /bits/ 64 <600000000>; 3246 required-opps = <&rpmhpd_opp_turbo_l1>; 3247 }; 3248 }; 3249 }; 3250 3251 mdss0_dp0: displayport-controller@ae90000 { 3252 compatible = "qcom,sc8280xp-dp"; 3253 reg = <0 0xae90000 0 0x200>, 3254 <0 0xae90200 0 0x200>, 3255 <0 0xae90400 0 0x600>, 3256 <0 0xae91000 0 0x400>, 3257 <0 0xae91400 0 0x400>; 3258 interrupt-parent = <&mdss0>; 3259 interrupts = <12>; 3260 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 3261 <&dispcc0 DISP_CC_MDSS_DPTX0_AUX_CLK>, 3262 <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_CLK>, 3263 <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 3264 <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; 3265 clock-names = "core_iface", "core_aux", 3266 "ctrl_link", 3267 "ctrl_link_iface", 3268 "stream_pixel"; 3269 3270 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 3271 <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; 3272 assigned-clock-parents = <&usb_0_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3273 <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 3274 3275 phys = <&usb_0_qmpphy QMP_USB43DP_DP_PHY>; 3276 phy-names = "dp"; 3277 3278 #sound-dai-cells = <0>; 3279 3280 operating-points-v2 = <&mdss0_dp0_opp_table>; 3281 power-domains = <&rpmhpd SC8280XP_MMCX>; 3282 3283 status = "disabled"; 3284 3285 ports { 3286 #address-cells = <1>; 3287 #size-cells = <0>; 3288 3289 port@0 { 3290 reg = <0>; 3291 3292 mdss0_dp0_in: endpoint { 3293 remote-endpoint = <&mdss0_intf0_out>; 3294 }; 3295 }; 3296 3297 port@1 { 3298 reg = <1>; 3299 3300 mdss0_dp0_out: endpoint { 3301 }; 3302 }; 3303 }; 3304 3305 mdss0_dp0_opp_table: opp-table { 3306 compatible = "operating-points-v2"; 3307 3308 opp-160000000 { 3309 opp-hz = /bits/ 64 <160000000>; 3310 required-opps = <&rpmhpd_opp_low_svs>; 3311 }; 3312 3313 opp-270000000 { 3314 opp-hz = /bits/ 64 <270000000>; 3315 required-opps = <&rpmhpd_opp_svs>; 3316 }; 3317 3318 opp-540000000 { 3319 opp-hz = /bits/ 64 <540000000>; 3320 required-opps = <&rpmhpd_opp_svs_l1>; 3321 }; 3322 3323 opp-810000000 { 3324 opp-hz = /bits/ 64 <810000000>; 3325 required-opps = <&rpmhpd_opp_nom>; 3326 }; 3327 }; 3328 }; 3329 3330 mdss0_dp1: displayport-controller@ae98000 { 3331 compatible = "qcom,sc8280xp-dp"; 3332 reg = <0 0xae98000 0 0x200>, 3333 <0 0xae98200 0 0x200>, 3334 <0 0xae98400 0 0x600>, 3335 <0 0xae99000 0 0x400>, 3336 <0 0xae99400 0 0x400>; 3337 interrupt-parent = <&mdss0>; 3338 interrupts = <13>; 3339 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 3340 <&dispcc0 DISP_CC_MDSS_DPTX1_AUX_CLK>, 3341 <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_CLK>, 3342 <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, 3343 <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>; 3344 clock-names = "core_iface", "core_aux", 3345 "ctrl_link", 3346 "ctrl_link_iface", "stream_pixel"; 3347 3348 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, 3349 <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>; 3350 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3351 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 3352 3353 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; 3354 phy-names = "dp"; 3355 3356 #sound-dai-cells = <0>; 3357 3358 operating-points-v2 = <&mdss0_dp1_opp_table>; 3359 power-domains = <&rpmhpd SC8280XP_MMCX>; 3360 3361 status = "disabled"; 3362 3363 ports { 3364 #address-cells = <1>; 3365 #size-cells = <0>; 3366 3367 port@0 { 3368 reg = <0>; 3369 3370 mdss0_dp1_in: endpoint { 3371 remote-endpoint = <&mdss0_intf4_out>; 3372 }; 3373 }; 3374 3375 port@1 { 3376 reg = <1>; 3377 3378 mdss0_dp1_out: endpoint { 3379 }; 3380 }; 3381 }; 3382 3383 mdss0_dp1_opp_table: opp-table { 3384 compatible = "operating-points-v2"; 3385 3386 opp-160000000 { 3387 opp-hz = /bits/ 64 <160000000>; 3388 required-opps = <&rpmhpd_opp_low_svs>; 3389 }; 3390 3391 opp-270000000 { 3392 opp-hz = /bits/ 64 <270000000>; 3393 required-opps = <&rpmhpd_opp_svs>; 3394 }; 3395 3396 opp-540000000 { 3397 opp-hz = /bits/ 64 <540000000>; 3398 required-opps = <&rpmhpd_opp_svs_l1>; 3399 }; 3400 3401 opp-810000000 { 3402 opp-hz = /bits/ 64 <810000000>; 3403 required-opps = <&rpmhpd_opp_nom>; 3404 }; 3405 }; 3406 }; 3407 3408 mdss0_dp2: displayport-controller@ae9a000 { 3409 compatible = "qcom,sc8280xp-dp"; 3410 reg = <0 0xae9a000 0 0x200>, 3411 <0 0xae9a200 0 0x200>, 3412 <0 0xae9a400 0 0x600>, 3413 <0 0xae9b000 0 0x400>, 3414 <0 0xae9b400 0 0x400>; 3415 3416 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 3417 <&dispcc0 DISP_CC_MDSS_DPTX2_AUX_CLK>, 3418 <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_CLK>, 3419 <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>, 3420 <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>; 3421 clock-names = "core_iface", "core_aux", 3422 "ctrl_link", 3423 "ctrl_link_iface", "stream_pixel"; 3424 interrupt-parent = <&mdss0>; 3425 interrupts = <14>; 3426 phys = <&mdss0_dp2_phy>; 3427 phy-names = "dp"; 3428 power-domains = <&rpmhpd SC8280XP_MMCX>; 3429 3430 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>, 3431 <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>; 3432 assigned-clock-parents = <&mdss0_dp2_phy 0>, <&mdss0_dp2_phy 1>; 3433 operating-points-v2 = <&mdss0_dp2_opp_table>; 3434 3435 #sound-dai-cells = <0>; 3436 3437 status = "disabled"; 3438 3439 ports { 3440 #address-cells = <1>; 3441 #size-cells = <0>; 3442 3443 port@0 { 3444 reg = <0>; 3445 mdss0_dp2_in: endpoint { 3446 remote-endpoint = <&mdss0_intf6_out>; 3447 }; 3448 }; 3449 3450 port@1 { 3451 reg = <1>; 3452 }; 3453 }; 3454 3455 mdss0_dp2_opp_table: opp-table { 3456 compatible = "operating-points-v2"; 3457 3458 opp-160000000 { 3459 opp-hz = /bits/ 64 <160000000>; 3460 required-opps = <&rpmhpd_opp_low_svs>; 3461 }; 3462 3463 opp-270000000 { 3464 opp-hz = /bits/ 64 <270000000>; 3465 required-opps = <&rpmhpd_opp_svs>; 3466 }; 3467 3468 opp-540000000 { 3469 opp-hz = /bits/ 64 <540000000>; 3470 required-opps = <&rpmhpd_opp_svs_l1>; 3471 }; 3472 3473 opp-810000000 { 3474 opp-hz = /bits/ 64 <810000000>; 3475 required-opps = <&rpmhpd_opp_nom>; 3476 }; 3477 }; 3478 }; 3479 3480 mdss0_dp3: displayport-controller@aea0000 { 3481 compatible = "qcom,sc8280xp-dp"; 3482 reg = <0 0xaea0000 0 0x200>, 3483 <0 0xaea0200 0 0x200>, 3484 <0 0xaea0400 0 0x600>, 3485 <0 0xaea1000 0 0x400>, 3486 <0 0xaea1400 0 0x400>; 3487 3488 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 3489 <&dispcc0 DISP_CC_MDSS_DPTX3_AUX_CLK>, 3490 <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_CLK>, 3491 <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>, 3492 <&dispcc0 DISP_CC_MDSS_DPTX3_PIXEL0_CLK>; 3493 clock-names = "core_iface", "core_aux", 3494 "ctrl_link", 3495 "ctrl_link_iface", "stream_pixel"; 3496 interrupt-parent = <&mdss0>; 3497 interrupts = <15>; 3498 phys = <&mdss0_dp3_phy>; 3499 phy-names = "dp"; 3500 power-domains = <&rpmhpd SC8280XP_MMCX>; 3501 3502 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>, 3503 <&dispcc0 DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>; 3504 assigned-clock-parents = <&mdss0_dp3_phy 0>, <&mdss0_dp3_phy 1>; 3505 operating-points-v2 = <&mdss0_dp3_opp_table>; 3506 3507 #sound-dai-cells = <0>; 3508 3509 status = "disabled"; 3510 3511 ports { 3512 #address-cells = <1>; 3513 #size-cells = <0>; 3514 3515 port@0 { 3516 reg = <0>; 3517 mdss0_dp3_in: endpoint { 3518 remote-endpoint = <&mdss0_intf5_out>; 3519 }; 3520 }; 3521 3522 port@1 { 3523 reg = <1>; 3524 }; 3525 }; 3526 3527 mdss0_dp3_opp_table: opp-table { 3528 compatible = "operating-points-v2"; 3529 3530 opp-160000000 { 3531 opp-hz = /bits/ 64 <160000000>; 3532 required-opps = <&rpmhpd_opp_low_svs>; 3533 }; 3534 3535 opp-270000000 { 3536 opp-hz = /bits/ 64 <270000000>; 3537 required-opps = <&rpmhpd_opp_svs>; 3538 }; 3539 3540 opp-540000000 { 3541 opp-hz = /bits/ 64 <540000000>; 3542 required-opps = <&rpmhpd_opp_svs_l1>; 3543 }; 3544 3545 opp-810000000 { 3546 opp-hz = /bits/ 64 <810000000>; 3547 required-opps = <&rpmhpd_opp_nom>; 3548 }; 3549 }; 3550 }; 3551 }; 3552 3553 mdss0_dp2_phy: phy@aec2a00 { 3554 compatible = "qcom,sc8280xp-dp-phy"; 3555 reg = <0 0x0aec2a00 0 0x19c>, 3556 <0 0x0aec2200 0 0xec>, 3557 <0 0x0aec2600 0 0xec>, 3558 <0 0x0aec2000 0 0x1c8>; 3559 3560 clocks = <&dispcc0 DISP_CC_MDSS_DPTX2_AUX_CLK>, 3561 <&dispcc0 DISP_CC_MDSS_AHB_CLK>; 3562 clock-names = "aux", "cfg_ahb"; 3563 power-domains = <&rpmhpd SC8280XP_MX>; 3564 3565 #clock-cells = <1>; 3566 #phy-cells = <0>; 3567 3568 status = "disabled"; 3569 }; 3570 3571 mdss0_dp3_phy: phy@aec5a00 { 3572 compatible = "qcom,sc8280xp-dp-phy"; 3573 reg = <0 0x0aec5a00 0 0x19c>, 3574 <0 0x0aec5200 0 0xec>, 3575 <0 0x0aec5600 0 0xec>, 3576 <0 0x0aec5000 0 0x1c8>; 3577 3578 clocks = <&dispcc0 DISP_CC_MDSS_DPTX3_AUX_CLK>, 3579 <&dispcc0 DISP_CC_MDSS_AHB_CLK>; 3580 clock-names = "aux", "cfg_ahb"; 3581 power-domains = <&rpmhpd SC8280XP_MX>; 3582 3583 #clock-cells = <1>; 3584 #phy-cells = <0>; 3585 3586 status = "disabled"; 3587 }; 3588 3589 dispcc0: clock-controller@af00000 { 3590 compatible = "qcom,sc8280xp-dispcc0"; 3591 reg = <0 0x0af00000 0 0x20000>; 3592 3593 clocks = <&gcc GCC_DISP_AHB_CLK>, 3594 <&rpmhcc RPMH_CXO_CLK>, 3595 <&sleep_clk>, 3596 <&usb_0_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3597 <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 3598 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3599 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 3600 <&mdss0_dp2_phy 0>, 3601 <&mdss0_dp2_phy 1>, 3602 <&mdss0_dp3_phy 0>, 3603 <&mdss0_dp3_phy 1>, 3604 <0>, 3605 <0>, 3606 <0>, 3607 <0>; 3608 power-domains = <&rpmhpd SC8280XP_MMCX>; 3609 3610 #clock-cells = <1>; 3611 #power-domain-cells = <1>; 3612 #reset-cells = <1>; 3613 3614 status = "disabled"; 3615 }; 3616 3617 pdc: interrupt-controller@b220000 { 3618 compatible = "qcom,sc8280xp-pdc", "qcom,pdc"; 3619 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; 3620 qcom,pdc-ranges = <0 480 40>, 3621 <40 140 14>, 3622 <54 263 1>, 3623 <55 306 4>, 3624 <59 312 3>, 3625 <62 374 2>, 3626 <64 434 2>, 3627 <66 438 3>, 3628 <69 86 1>, 3629 <70 520 54>, 3630 <124 609 28>, 3631 <159 638 1>, 3632 <160 720 8>, 3633 <168 801 1>, 3634 <169 728 30>, 3635 <199 416 2>, 3636 <201 449 1>, 3637 <202 89 1>, 3638 <203 451 1>, 3639 <204 462 1>, 3640 <205 264 1>, 3641 <206 579 1>, 3642 <207 653 1>, 3643 <208 656 1>, 3644 <209 659 1>, 3645 <210 122 1>, 3646 <211 699 1>, 3647 <212 705 1>, 3648 <213 450 1>, 3649 <214 643 1>, 3650 <216 646 5>, 3651 <221 390 5>, 3652 <226 700 3>, 3653 <229 240 3>, 3654 <232 269 1>, 3655 <233 377 1>, 3656 <234 372 1>, 3657 <235 138 1>, 3658 <236 857 1>, 3659 <237 860 1>, 3660 <238 137 1>, 3661 <239 668 1>, 3662 <240 366 1>, 3663 <241 949 1>, 3664 <242 815 5>, 3665 <247 769 1>, 3666 <248 768 1>, 3667 <249 663 1>, 3668 <250 799 2>, 3669 <252 798 1>, 3670 <253 765 1>, 3671 <254 763 1>, 3672 <255 454 1>, 3673 <258 139 1>, 3674 <259 786 2>, 3675 <261 370 2>, 3676 <263 158 2>; 3677 #interrupt-cells = <2>; 3678 interrupt-parent = <&intc>; 3679 interrupt-controller; 3680 }; 3681 3682 tsens0: thermal-sensor@c263000 { 3683 compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2"; 3684 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 3685 <0 0x0c222000 0 0x8>; /* SROT */ 3686 #qcom,sensors = <14>; 3687 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, 3688 <&pdc 28 IRQ_TYPE_LEVEL_HIGH>; 3689 interrupt-names = "uplow", "critical"; 3690 #thermal-sensor-cells = <1>; 3691 }; 3692 3693 tsens1: thermal-sensor@c265000 { 3694 compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2"; 3695 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 3696 <0 0x0c223000 0 0x8>; /* SROT */ 3697 #qcom,sensors = <16>; 3698 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, 3699 <&pdc 29 IRQ_TYPE_LEVEL_HIGH>; 3700 interrupt-names = "uplow", "critical"; 3701 #thermal-sensor-cells = <1>; 3702 }; 3703 3704 aoss_qmp: power-management@c300000 { 3705 compatible = "qcom,sc8280xp-aoss-qmp", "qcom,aoss-qmp"; 3706 reg = <0 0x0c300000 0 0x400>; 3707 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>; 3708 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 3709 3710 #clock-cells = <0>; 3711 }; 3712 3713 sram@c3f0000 { 3714 compatible = "qcom,rpmh-stats"; 3715 reg = <0 0x0c3f0000 0 0x400>; 3716 }; 3717 3718 spmi_bus: spmi@c440000 { 3719 compatible = "qcom,spmi-pmic-arb"; 3720 reg = <0 0x0c440000 0 0x1100>, 3721 <0 0x0c600000 0 0x2000000>, 3722 <0 0x0e600000 0 0x100000>, 3723 <0 0x0e700000 0 0xa0000>, 3724 <0 0x0c40a000 0 0x26000>; 3725 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 3726 interrupt-names = "periph_irq"; 3727 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 3728 qcom,ee = <0>; 3729 qcom,channel = <0>; 3730 #address-cells = <2>; 3731 #size-cells = <0>; 3732 interrupt-controller; 3733 #interrupt-cells = <4>; 3734 }; 3735 3736 tlmm: pinctrl@f100000 { 3737 compatible = "qcom,sc8280xp-tlmm"; 3738 reg = <0 0x0f100000 0 0x300000>; 3739 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 3740 gpio-controller; 3741 #gpio-cells = <2>; 3742 interrupt-controller; 3743 #interrupt-cells = <2>; 3744 gpio-ranges = <&tlmm 0 0 230>; 3745 }; 3746 3747 apps_smmu: iommu@15000000 { 3748 compatible = "qcom,sc8280xp-smmu-500", "arm,mmu-500"; 3749 reg = <0 0x15000000 0 0x100000>; 3750 #iommu-cells = <2>; 3751 #global-interrupts = <2>; 3752 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 3753 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3754 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3755 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3756 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3757 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3758 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3759 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3760 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3761 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3762 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3763 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3764 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3765 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3766 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3767 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3768 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3769 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3770 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3771 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3772 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3773 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3774 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3775 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3776 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3777 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3778 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3779 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3780 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3781 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3782 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3783 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3784 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3785 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3786 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3787 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3788 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3789 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3790 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3791 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3792 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3793 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3794 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3795 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3796 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3797 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3798 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3799 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3800 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3801 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3802 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3803 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3804 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3805 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3806 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3807 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3808 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3809 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3810 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3811 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3812 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3813 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 3814 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 3815 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 3816 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 3817 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 3818 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 3819 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3820 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3821 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3822 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3823 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3824 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3825 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3826 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 3827 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 3828 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 3829 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 3830 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 3831 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 3832 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, 3833 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 3834 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 3835 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 3836 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, 3837 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 3838 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 3839 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 3840 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 3841 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 3842 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 3843 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 3844 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 3845 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 3846 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 3847 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>, 3848 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 3849 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 3850 <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>, 3851 <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>, 3852 <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>, 3853 <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>, 3854 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 3855 <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>, 3856 <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>, 3857 <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>, 3858 <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>, 3859 <GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH>, 3860 <GIC_SPI 911 IRQ_TYPE_LEVEL_HIGH>, 3861 <GIC_SPI 910 IRQ_TYPE_LEVEL_HIGH>, 3862 <GIC_SPI 909 IRQ_TYPE_LEVEL_HIGH>, 3863 <GIC_SPI 908 IRQ_TYPE_LEVEL_HIGH>, 3864 <GIC_SPI 907 IRQ_TYPE_LEVEL_HIGH>, 3865 <GIC_SPI 906 IRQ_TYPE_LEVEL_HIGH>, 3866 <GIC_SPI 905 IRQ_TYPE_LEVEL_HIGH>, 3867 <GIC_SPI 904 IRQ_TYPE_LEVEL_HIGH>, 3868 <GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>, 3869 <GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>, 3870 <GIC_SPI 901 IRQ_TYPE_LEVEL_HIGH>, 3871 <GIC_SPI 900 IRQ_TYPE_LEVEL_HIGH>, 3872 <GIC_SPI 899 IRQ_TYPE_LEVEL_HIGH>, 3873 <GIC_SPI 898 IRQ_TYPE_LEVEL_HIGH>, 3874 <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>, 3875 <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>, 3876 <GIC_SPI 895 IRQ_TYPE_LEVEL_HIGH>, 3877 <GIC_SPI 894 IRQ_TYPE_LEVEL_HIGH>, 3878 <GIC_SPI 893 IRQ_TYPE_LEVEL_HIGH>, 3879 <GIC_SPI 892 IRQ_TYPE_LEVEL_HIGH>, 3880 <GIC_SPI 891 IRQ_TYPE_LEVEL_HIGH>, 3881 <GIC_SPI 890 IRQ_TYPE_LEVEL_HIGH>; 3882 }; 3883 3884 intc: interrupt-controller@17a00000 { 3885 compatible = "arm,gic-v3"; 3886 interrupt-controller; 3887 #interrupt-cells = <3>; 3888 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 3889 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 3890 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3891 #redistributor-regions = <1>; 3892 redistributor-stride = <0 0x20000>; 3893 3894 #address-cells = <2>; 3895 #size-cells = <2>; 3896 ranges; 3897 3898 gic-its@17a40000 { 3899 compatible = "arm,gic-v3-its"; 3900 reg = <0 0x17a40000 0 0x20000>; 3901 msi-controller; 3902 #msi-cells = <1>; 3903 }; 3904 }; 3905 3906 watchdog@17c10000 { 3907 compatible = "qcom,apss-wdt-sc8280xp", "qcom,kpss-wdt"; 3908 reg = <0 0x17c10000 0 0x1000>; 3909 clocks = <&sleep_clk>; 3910 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 3911 }; 3912 3913 timer@17c20000 { 3914 compatible = "arm,armv7-timer-mem"; 3915 reg = <0x0 0x17c20000 0x0 0x1000>; 3916 #address-cells = <1>; 3917 #size-cells = <1>; 3918 ranges = <0x0 0x0 0x0 0x20000000>; 3919 3920 frame@17c21000 { 3921 frame-number = <0>; 3922 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3923 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3924 reg = <0x17c21000 0x1000>, 3925 <0x17c22000 0x1000>; 3926 }; 3927 3928 frame@17c23000 { 3929 frame-number = <1>; 3930 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3931 reg = <0x17c23000 0x1000>; 3932 status = "disabled"; 3933 }; 3934 3935 frame@17c25000 { 3936 frame-number = <2>; 3937 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3938 reg = <0x17c25000 0x1000>; 3939 status = "disabled"; 3940 }; 3941 3942 frame@17c27000 { 3943 frame-number = <3>; 3944 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3945 reg = <0x17c26000 0x1000>; 3946 status = "disabled"; 3947 }; 3948 3949 frame@17c29000 { 3950 frame-number = <4>; 3951 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3952 reg = <0x17c29000 0x1000>; 3953 status = "disabled"; 3954 }; 3955 3956 frame@17c2b000 { 3957 frame-number = <5>; 3958 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3959 reg = <0x17c2b000 0x1000>; 3960 status = "disabled"; 3961 }; 3962 3963 frame@17c2d000 { 3964 frame-number = <6>; 3965 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3966 reg = <0x17c2d000 0x1000>; 3967 status = "disabled"; 3968 }; 3969 }; 3970 3971 apps_rsc: rsc@18200000 { 3972 compatible = "qcom,rpmh-rsc"; 3973 reg = <0x0 0x18200000 0x0 0x10000>, 3974 <0x0 0x18210000 0x0 0x10000>, 3975 <0x0 0x18220000 0x0 0x10000>; 3976 reg-names = "drv-0", "drv-1", "drv-2"; 3977 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3978 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3979 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3980 qcom,tcs-offset = <0xd00>; 3981 qcom,drv-id = <2>; 3982 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 3983 <WAKE_TCS 3>, <CONTROL_TCS 1>; 3984 label = "apps_rsc"; 3985 3986 apps_bcm_voter: bcm-voter { 3987 compatible = "qcom,bcm-voter"; 3988 }; 3989 3990 rpmhcc: clock-controller { 3991 compatible = "qcom,sc8280xp-rpmh-clk"; 3992 #clock-cells = <1>; 3993 clock-names = "xo"; 3994 clocks = <&xo_board_clk>; 3995 }; 3996 3997 rpmhpd: power-controller { 3998 compatible = "qcom,sc8280xp-rpmhpd"; 3999 #power-domain-cells = <1>; 4000 operating-points-v2 = <&rpmhpd_opp_table>; 4001 4002 rpmhpd_opp_table: opp-table { 4003 compatible = "operating-points-v2"; 4004 4005 rpmhpd_opp_ret: opp1 { 4006 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 4007 }; 4008 4009 rpmhpd_opp_min_svs: opp2 { 4010 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 4011 }; 4012 4013 rpmhpd_opp_low_svs: opp3 { 4014 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4015 }; 4016 4017 rpmhpd_opp_svs: opp4 { 4018 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4019 }; 4020 4021 rpmhpd_opp_svs_l1: opp5 { 4022 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4023 }; 4024 4025 rpmhpd_opp_nom: opp6 { 4026 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4027 }; 4028 4029 rpmhpd_opp_nom_l1: opp7 { 4030 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4031 }; 4032 4033 rpmhpd_opp_nom_l2: opp8 { 4034 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 4035 }; 4036 4037 rpmhpd_opp_turbo: opp9 { 4038 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4039 }; 4040 4041 rpmhpd_opp_turbo_l1: opp10 { 4042 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4043 }; 4044 }; 4045 }; 4046 }; 4047 4048 epss_l3: interconnect@18590000 { 4049 compatible = "qcom,sc8280xp-epss-l3", "qcom,epss-l3"; 4050 reg = <0 0x18590000 0 0x1000>; 4051 4052 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 4053 clock-names = "xo", "alternate"; 4054 4055 #interconnect-cells = <1>; 4056 }; 4057 4058 cpufreq_hw: cpufreq@18591000 { 4059 compatible = "qcom,sc8280xp-cpufreq-epss", "qcom,cpufreq-epss"; 4060 reg = <0 0x18591000 0 0x1000>, 4061 <0 0x18592000 0 0x1000>; 4062 reg-names = "freq-domain0", "freq-domain1"; 4063 4064 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 4065 clock-names = "xo", "alternate"; 4066 4067 #freq-domain-cells = <1>; 4068 #clock-cells = <1>; 4069 }; 4070 4071 remoteproc_nsp0: remoteproc@1b300000 { 4072 compatible = "qcom,sc8280xp-nsp0-pas"; 4073 reg = <0 0x1b300000 0 0x100>; 4074 4075 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, 4076 <&smp2p_nsp0_in 0 IRQ_TYPE_EDGE_RISING>, 4077 <&smp2p_nsp0_in 1 IRQ_TYPE_EDGE_RISING>, 4078 <&smp2p_nsp0_in 2 IRQ_TYPE_EDGE_RISING>, 4079 <&smp2p_nsp0_in 3 IRQ_TYPE_EDGE_RISING>; 4080 interrupt-names = "wdog", "fatal", "ready", 4081 "handover", "stop-ack"; 4082 4083 clocks = <&rpmhcc RPMH_CXO_CLK>; 4084 clock-names = "xo"; 4085 4086 power-domains = <&rpmhpd SC8280XP_NSP>; 4087 power-domain-names = "nsp"; 4088 4089 memory-region = <&pil_nsp0_mem>; 4090 4091 qcom,smem-states = <&smp2p_nsp0_out 0>; 4092 qcom,smem-state-names = "stop"; 4093 4094 interconnects = <&nspa_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>; 4095 4096 status = "disabled"; 4097 4098 glink-edge { 4099 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 4100 IPCC_MPROC_SIGNAL_GLINK_QMP 4101 IRQ_TYPE_EDGE_RISING>; 4102 mboxes = <&ipcc IPCC_CLIENT_CDSP 4103 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4104 4105 label = "nsp0"; 4106 qcom,remote-pid = <5>; 4107 4108 fastrpc { 4109 compatible = "qcom,fastrpc"; 4110 qcom,glink-channels = "fastrpcglink-apps-dsp"; 4111 label = "cdsp"; 4112 #address-cells = <1>; 4113 #size-cells = <0>; 4114 4115 compute-cb@1 { 4116 compatible = "qcom,fastrpc-compute-cb"; 4117 reg = <1>; 4118 iommus = <&apps_smmu 0x3181 0x0420>; 4119 }; 4120 4121 compute-cb@2 { 4122 compatible = "qcom,fastrpc-compute-cb"; 4123 reg = <2>; 4124 iommus = <&apps_smmu 0x3182 0x0420>; 4125 }; 4126 4127 compute-cb@3 { 4128 compatible = "qcom,fastrpc-compute-cb"; 4129 reg = <3>; 4130 iommus = <&apps_smmu 0x3183 0x0420>; 4131 }; 4132 4133 compute-cb@4 { 4134 compatible = "qcom,fastrpc-compute-cb"; 4135 reg = <4>; 4136 iommus = <&apps_smmu 0x3184 0x0420>; 4137 }; 4138 4139 compute-cb@5 { 4140 compatible = "qcom,fastrpc-compute-cb"; 4141 reg = <5>; 4142 iommus = <&apps_smmu 0x3185 0x0420>; 4143 }; 4144 4145 compute-cb@6 { 4146 compatible = "qcom,fastrpc-compute-cb"; 4147 reg = <6>; 4148 iommus = <&apps_smmu 0x3186 0x0420>; 4149 }; 4150 4151 compute-cb@7 { 4152 compatible = "qcom,fastrpc-compute-cb"; 4153 reg = <7>; 4154 iommus = <&apps_smmu 0x3187 0x0420>; 4155 }; 4156 4157 compute-cb@8 { 4158 compatible = "qcom,fastrpc-compute-cb"; 4159 reg = <8>; 4160 iommus = <&apps_smmu 0x3188 0x0420>; 4161 }; 4162 4163 compute-cb@9 { 4164 compatible = "qcom,fastrpc-compute-cb"; 4165 reg = <9>; 4166 iommus = <&apps_smmu 0x318b 0x0420>; 4167 }; 4168 4169 compute-cb@10 { 4170 compatible = "qcom,fastrpc-compute-cb"; 4171 reg = <10>; 4172 iommus = <&apps_smmu 0x318b 0x0420>; 4173 }; 4174 4175 compute-cb@11 { 4176 compatible = "qcom,fastrpc-compute-cb"; 4177 reg = <11>; 4178 iommus = <&apps_smmu 0x318c 0x0420>; 4179 }; 4180 4181 compute-cb@12 { 4182 compatible = "qcom,fastrpc-compute-cb"; 4183 reg = <12>; 4184 iommus = <&apps_smmu 0x318d 0x0420>; 4185 }; 4186 4187 compute-cb@13 { 4188 compatible = "qcom,fastrpc-compute-cb"; 4189 reg = <13>; 4190 iommus = <&apps_smmu 0x318e 0x0420>; 4191 }; 4192 4193 compute-cb@14 { 4194 compatible = "qcom,fastrpc-compute-cb"; 4195 reg = <14>; 4196 iommus = <&apps_smmu 0x318f 0x0420>; 4197 }; 4198 }; 4199 }; 4200 }; 4201 4202 remoteproc_nsp1: remoteproc@21300000 { 4203 compatible = "qcom,sc8280xp-nsp1-pas"; 4204 reg = <0 0x21300000 0 0x100>; 4205 4206 interrupts-extended = <&intc GIC_SPI 887 IRQ_TYPE_LEVEL_HIGH>, 4207 <&smp2p_nsp1_in 0 IRQ_TYPE_EDGE_RISING>, 4208 <&smp2p_nsp1_in 1 IRQ_TYPE_EDGE_RISING>, 4209 <&smp2p_nsp1_in 2 IRQ_TYPE_EDGE_RISING>, 4210 <&smp2p_nsp1_in 3 IRQ_TYPE_EDGE_RISING>; 4211 interrupt-names = "wdog", "fatal", "ready", 4212 "handover", "stop-ack"; 4213 4214 clocks = <&rpmhcc RPMH_CXO_CLK>; 4215 clock-names = "xo"; 4216 4217 power-domains = <&rpmhpd SC8280XP_NSP>; 4218 power-domain-names = "nsp"; 4219 4220 memory-region = <&pil_nsp1_mem>; 4221 4222 qcom,smem-states = <&smp2p_nsp1_out 0>; 4223 qcom,smem-state-names = "stop"; 4224 4225 interconnects = <&nspb_noc MASTER_CDSP_PROC_B 0 &mc_virt SLAVE_EBI1 0>; 4226 4227 status = "disabled"; 4228 4229 glink-edge { 4230 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1 4231 IPCC_MPROC_SIGNAL_GLINK_QMP 4232 IRQ_TYPE_EDGE_RISING>; 4233 mboxes = <&ipcc IPCC_CLIENT_NSP1 4234 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4235 4236 label = "nsp1"; 4237 qcom,remote-pid = <12>; 4238 }; 4239 }; 4240 4241 mdss1: display-subsystem@22000000 { 4242 compatible = "qcom,sc8280xp-mdss"; 4243 reg = <0 0x22000000 0 0x1000>; 4244 reg-names = "mdss"; 4245 4246 clocks = <&gcc GCC_DISP_AHB_CLK>, 4247 <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 4248 <&dispcc1 DISP_CC_MDSS_MDP_CLK>; 4249 clock-names = "iface", 4250 "ahb", 4251 "core"; 4252 interconnects = <&mmss_noc MASTER_MDP_CORE1_0 0 &mc_virt SLAVE_EBI1 0>, 4253 <&mmss_noc MASTER_MDP_CORE1_1 0 &mc_virt SLAVE_EBI1 0>; 4254 interconnect-names = "mdp0-mem", "mdp1-mem"; 4255 interrupts = <GIC_SPI 865 IRQ_TYPE_LEVEL_HIGH>; 4256 4257 iommus = <&apps_smmu 0x1800 0x402>; 4258 power-domains = <&dispcc1 MDSS_GDSC>; 4259 resets = <&dispcc1 DISP_CC_MDSS_CORE_BCR>; 4260 4261 interrupt-controller; 4262 #interrupt-cells = <1>; 4263 #address-cells = <2>; 4264 #size-cells = <2>; 4265 ranges; 4266 4267 status = "disabled"; 4268 4269 mdss1_mdp: display-controller@22001000 { 4270 compatible = "qcom,sc8280xp-dpu"; 4271 reg = <0 0x22001000 0 0x8f000>, 4272 <0 0x220b0000 0 0x2008>; 4273 reg-names = "mdp", "vbif"; 4274 4275 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 4276 <&gcc GCC_DISP_SF_AXI_CLK>, 4277 <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 4278 <&dispcc1 DISP_CC_MDSS_MDP_LUT_CLK>, 4279 <&dispcc1 DISP_CC_MDSS_MDP_CLK>, 4280 <&dispcc1 DISP_CC_MDSS_VSYNC_CLK>; 4281 clock-names = "bus", 4282 "nrt_bus", 4283 "iface", 4284 "lut", 4285 "core", 4286 "vsync"; 4287 interrupt-parent = <&mdss1>; 4288 interrupts = <0>; 4289 power-domains = <&rpmhpd SC8280XP_MMCX>; 4290 4291 assigned-clocks = <&dispcc1 DISP_CC_MDSS_VSYNC_CLK>; 4292 assigned-clock-rates = <19200000>; 4293 operating-points-v2 = <&mdss1_mdp_opp_table>; 4294 4295 ports { 4296 #address-cells = <1>; 4297 #size-cells = <0>; 4298 4299 port@0 { 4300 reg = <0>; 4301 mdss1_intf0_out: endpoint { 4302 remote-endpoint = <&mdss1_dp0_in>; 4303 }; 4304 }; 4305 4306 port@4 { 4307 reg = <4>; 4308 mdss1_intf4_out: endpoint { 4309 remote-endpoint = <&mdss1_dp1_in>; 4310 }; 4311 }; 4312 4313 port@5 { 4314 reg = <5>; 4315 mdss1_intf5_out: endpoint { 4316 remote-endpoint = <&mdss1_dp3_in>; 4317 }; 4318 }; 4319 4320 port@6 { 4321 reg = <6>; 4322 mdss1_intf6_out: endpoint { 4323 remote-endpoint = <&mdss1_dp2_in>; 4324 }; 4325 }; 4326 }; 4327 4328 mdss1_mdp_opp_table: opp-table { 4329 compatible = "operating-points-v2"; 4330 4331 opp-200000000 { 4332 opp-hz = /bits/ 64 <200000000>; 4333 required-opps = <&rpmhpd_opp_low_svs>; 4334 }; 4335 4336 opp-300000000 { 4337 opp-hz = /bits/ 64 <300000000>; 4338 required-opps = <&rpmhpd_opp_svs>; 4339 }; 4340 4341 opp-375000000 { 4342 opp-hz = /bits/ 64 <375000000>; 4343 required-opps = <&rpmhpd_opp_svs_l1>; 4344 }; 4345 4346 opp-500000000 { 4347 opp-hz = /bits/ 64 <500000000>; 4348 required-opps = <&rpmhpd_opp_nom>; 4349 }; 4350 opp-600000000 { 4351 opp-hz = /bits/ 64 <600000000>; 4352 required-opps = <&rpmhpd_opp_turbo_l1>; 4353 }; 4354 }; 4355 }; 4356 4357 mdss1_dp0: displayport-controller@22090000 { 4358 compatible = "qcom,sc8280xp-dp"; 4359 reg = <0 0x22090000 0 0x200>, 4360 <0 0x22090200 0 0x200>, 4361 <0 0x22090400 0 0x600>, 4362 <0 0x22091000 0 0x400>, 4363 <0 0x22091400 0 0x400>; 4364 4365 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 4366 <&dispcc1 DISP_CC_MDSS_DPTX0_AUX_CLK>, 4367 <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_CLK>, 4368 <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 4369 <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; 4370 clock-names = "core_iface", "core_aux", 4371 "ctrl_link", 4372 "ctrl_link_iface", "stream_pixel"; 4373 interrupt-parent = <&mdss1>; 4374 interrupts = <12>; 4375 phys = <&mdss1_dp0_phy>; 4376 phy-names = "dp"; 4377 power-domains = <&rpmhpd SC8280XP_MMCX>; 4378 4379 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 4380 <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; 4381 assigned-clock-parents = <&mdss1_dp0_phy 0>, <&mdss1_dp0_phy 1>; 4382 operating-points-v2 = <&mdss1_dp0_opp_table>; 4383 4384 #sound-dai-cells = <0>; 4385 4386 status = "disabled"; 4387 4388 ports { 4389 #address-cells = <1>; 4390 #size-cells = <0>; 4391 4392 port@0 { 4393 reg = <0>; 4394 mdss1_dp0_in: endpoint { 4395 remote-endpoint = <&mdss1_intf0_out>; 4396 }; 4397 }; 4398 4399 port@1 { 4400 reg = <1>; 4401 }; 4402 }; 4403 4404 mdss1_dp0_opp_table: opp-table { 4405 compatible = "operating-points-v2"; 4406 4407 opp-160000000 { 4408 opp-hz = /bits/ 64 <160000000>; 4409 required-opps = <&rpmhpd_opp_low_svs>; 4410 }; 4411 4412 opp-270000000 { 4413 opp-hz = /bits/ 64 <270000000>; 4414 required-opps = <&rpmhpd_opp_svs>; 4415 }; 4416 4417 opp-540000000 { 4418 opp-hz = /bits/ 64 <540000000>; 4419 required-opps = <&rpmhpd_opp_svs_l1>; 4420 }; 4421 4422 opp-810000000 { 4423 opp-hz = /bits/ 64 <810000000>; 4424 required-opps = <&rpmhpd_opp_nom>; 4425 }; 4426 }; 4427 }; 4428 4429 mdss1_dp1: displayport-controller@22098000 { 4430 compatible = "qcom,sc8280xp-dp"; 4431 reg = <0 0x22098000 0 0x200>, 4432 <0 0x22098200 0 0x200>, 4433 <0 0x22098400 0 0x600>, 4434 <0 0x22099000 0 0x400>, 4435 <0 0x22099400 0 0x400>; 4436 4437 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 4438 <&dispcc1 DISP_CC_MDSS_DPTX1_AUX_CLK>, 4439 <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_CLK>, 4440 <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, 4441 <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>; 4442 clock-names = "core_iface", "core_aux", 4443 "ctrl_link", 4444 "ctrl_link_iface", "stream_pixel"; 4445 interrupt-parent = <&mdss1>; 4446 interrupts = <13>; 4447 phys = <&mdss1_dp1_phy>; 4448 phy-names = "dp"; 4449 power-domains = <&rpmhpd SC8280XP_MMCX>; 4450 4451 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, 4452 <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>; 4453 assigned-clock-parents = <&mdss1_dp1_phy 0>, <&mdss1_dp1_phy 1>; 4454 operating-points-v2 = <&mdss1_dp1_opp_table>; 4455 4456 #sound-dai-cells = <0>; 4457 4458 status = "disabled"; 4459 4460 ports { 4461 #address-cells = <1>; 4462 #size-cells = <0>; 4463 4464 port@0 { 4465 reg = <0>; 4466 mdss1_dp1_in: endpoint { 4467 remote-endpoint = <&mdss1_intf4_out>; 4468 }; 4469 }; 4470 4471 port@1 { 4472 reg = <1>; 4473 }; 4474 }; 4475 4476 mdss1_dp1_opp_table: opp-table { 4477 compatible = "operating-points-v2"; 4478 4479 opp-160000000 { 4480 opp-hz = /bits/ 64 <160000000>; 4481 required-opps = <&rpmhpd_opp_low_svs>; 4482 }; 4483 4484 opp-270000000 { 4485 opp-hz = /bits/ 64 <270000000>; 4486 required-opps = <&rpmhpd_opp_svs>; 4487 }; 4488 4489 opp-540000000 { 4490 opp-hz = /bits/ 64 <540000000>; 4491 required-opps = <&rpmhpd_opp_svs_l1>; 4492 }; 4493 4494 opp-810000000 { 4495 opp-hz = /bits/ 64 <810000000>; 4496 required-opps = <&rpmhpd_opp_nom>; 4497 }; 4498 }; 4499 }; 4500 4501 mdss1_dp2: displayport-controller@2209a000 { 4502 compatible = "qcom,sc8280xp-dp"; 4503 reg = <0 0x2209a000 0 0x200>, 4504 <0 0x2209a200 0 0x200>, 4505 <0 0x2209a400 0 0x600>, 4506 <0 0x2209b000 0 0x400>, 4507 <0 0x2209b400 0 0x400>; 4508 4509 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 4510 <&dispcc1 DISP_CC_MDSS_DPTX2_AUX_CLK>, 4511 <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_CLK>, 4512 <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>, 4513 <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>; 4514 clock-names = "core_iface", "core_aux", 4515 "ctrl_link", 4516 "ctrl_link_iface", "stream_pixel"; 4517 interrupt-parent = <&mdss1>; 4518 interrupts = <14>; 4519 phys = <&mdss1_dp2_phy>; 4520 phy-names = "dp"; 4521 power-domains = <&rpmhpd SC8280XP_MMCX>; 4522 4523 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>, 4524 <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>; 4525 assigned-clock-parents = <&mdss1_dp2_phy 0>, <&mdss1_dp2_phy 1>; 4526 operating-points-v2 = <&mdss1_dp2_opp_table>; 4527 4528 #sound-dai-cells = <0>; 4529 4530 status = "disabled"; 4531 4532 ports { 4533 #address-cells = <1>; 4534 #size-cells = <0>; 4535 4536 port@0 { 4537 reg = <0>; 4538 mdss1_dp2_in: endpoint { 4539 remote-endpoint = <&mdss1_intf6_out>; 4540 }; 4541 }; 4542 4543 port@1 { 4544 reg = <1>; 4545 }; 4546 }; 4547 4548 mdss1_dp2_opp_table: opp-table { 4549 compatible = "operating-points-v2"; 4550 4551 opp-160000000 { 4552 opp-hz = /bits/ 64 <160000000>; 4553 required-opps = <&rpmhpd_opp_low_svs>; 4554 }; 4555 4556 opp-270000000 { 4557 opp-hz = /bits/ 64 <270000000>; 4558 required-opps = <&rpmhpd_opp_svs>; 4559 }; 4560 4561 opp-540000000 { 4562 opp-hz = /bits/ 64 <540000000>; 4563 required-opps = <&rpmhpd_opp_svs_l1>; 4564 }; 4565 4566 opp-810000000 { 4567 opp-hz = /bits/ 64 <810000000>; 4568 required-opps = <&rpmhpd_opp_nom>; 4569 }; 4570 }; 4571 }; 4572 4573 mdss1_dp3: displayport-controller@220a0000 { 4574 compatible = "qcom,sc8280xp-dp"; 4575 reg = <0 0x220a0000 0 0x200>, 4576 <0 0x220a0200 0 0x200>, 4577 <0 0x220a0400 0 0x600>, 4578 <0 0x220a1000 0 0x400>, 4579 <0 0x220a1400 0 0x400>; 4580 4581 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 4582 <&dispcc1 DISP_CC_MDSS_DPTX3_AUX_CLK>, 4583 <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_CLK>, 4584 <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>, 4585 <&dispcc1 DISP_CC_MDSS_DPTX3_PIXEL0_CLK>; 4586 clock-names = "core_iface", "core_aux", 4587 "ctrl_link", 4588 "ctrl_link_iface", "stream_pixel"; 4589 interrupt-parent = <&mdss1>; 4590 interrupts = <15>; 4591 phys = <&mdss1_dp3_phy>; 4592 phy-names = "dp"; 4593 power-domains = <&rpmhpd SC8280XP_MMCX>; 4594 4595 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>, 4596 <&dispcc1 DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>; 4597 assigned-clock-parents = <&mdss1_dp3_phy 0>, <&mdss1_dp3_phy 1>; 4598 operating-points-v2 = <&mdss1_dp3_opp_table>; 4599 4600 #sound-dai-cells = <0>; 4601 4602 status = "disabled"; 4603 4604 ports { 4605 #address-cells = <1>; 4606 #size-cells = <0>; 4607 4608 port@0 { 4609 reg = <0>; 4610 mdss1_dp3_in: endpoint { 4611 remote-endpoint = <&mdss1_intf5_out>; 4612 }; 4613 }; 4614 4615 port@1 { 4616 reg = <1>; 4617 }; 4618 }; 4619 4620 mdss1_dp3_opp_table: opp-table { 4621 compatible = "operating-points-v2"; 4622 4623 opp-160000000 { 4624 opp-hz = /bits/ 64 <160000000>; 4625 required-opps = <&rpmhpd_opp_low_svs>; 4626 }; 4627 4628 opp-270000000 { 4629 opp-hz = /bits/ 64 <270000000>; 4630 required-opps = <&rpmhpd_opp_svs>; 4631 }; 4632 4633 opp-540000000 { 4634 opp-hz = /bits/ 64 <540000000>; 4635 required-opps = <&rpmhpd_opp_svs_l1>; 4636 }; 4637 4638 opp-810000000 { 4639 opp-hz = /bits/ 64 <810000000>; 4640 required-opps = <&rpmhpd_opp_nom>; 4641 }; 4642 }; 4643 }; 4644 }; 4645 4646 mdss1_dp2_phy: phy@220c2a00 { 4647 compatible = "qcom,sc8280xp-dp-phy"; 4648 reg = <0 0x220c2a00 0 0x19c>, 4649 <0 0x220c2200 0 0xec>, 4650 <0 0x220c2600 0 0xec>, 4651 <0 0x220c2000 0 0x1c8>; 4652 4653 clocks = <&dispcc1 DISP_CC_MDSS_DPTX2_AUX_CLK>, 4654 <&dispcc1 DISP_CC_MDSS_AHB_CLK>; 4655 clock-names = "aux", "cfg_ahb"; 4656 power-domains = <&rpmhpd SC8280XP_MX>; 4657 4658 #clock-cells = <1>; 4659 #phy-cells = <0>; 4660 4661 status = "disabled"; 4662 }; 4663 4664 mdss1_dp3_phy: phy@220c5a00 { 4665 compatible = "qcom,sc8280xp-dp-phy"; 4666 reg = <0 0x220c5a00 0 0x19c>, 4667 <0 0x220c5200 0 0xec>, 4668 <0 0x220c5600 0 0xec>, 4669 <0 0x220c5000 0 0x1c8>; 4670 4671 clocks = <&dispcc1 DISP_CC_MDSS_DPTX3_AUX_CLK>, 4672 <&dispcc1 DISP_CC_MDSS_AHB_CLK>; 4673 clock-names = "aux", "cfg_ahb"; 4674 power-domains = <&rpmhpd SC8280XP_MX>; 4675 4676 #clock-cells = <1>; 4677 #phy-cells = <0>; 4678 4679 status = "disabled"; 4680 }; 4681 4682 dispcc1: clock-controller@22100000 { 4683 compatible = "qcom,sc8280xp-dispcc1"; 4684 reg = <0 0x22100000 0 0x20000>; 4685 4686 clocks = <&gcc GCC_DISP_AHB_CLK>, 4687 <&rpmhcc RPMH_CXO_CLK>, 4688 <0>, 4689 <&mdss1_dp0_phy 0>, 4690 <&mdss1_dp0_phy 1>, 4691 <&mdss1_dp1_phy 0>, 4692 <&mdss1_dp1_phy 1>, 4693 <&mdss1_dp2_phy 0>, 4694 <&mdss1_dp2_phy 1>, 4695 <&mdss1_dp3_phy 0>, 4696 <&mdss1_dp3_phy 1>, 4697 <0>, 4698 <0>, 4699 <0>, 4700 <0>; 4701 power-domains = <&rpmhpd SC8280XP_MMCX>; 4702 4703 #clock-cells = <1>; 4704 #power-domain-cells = <1>; 4705 #reset-cells = <1>; 4706 4707 status = "disabled"; 4708 }; 4709 }; 4710 4711 sound: sound { 4712 }; 4713 4714 thermal-zones { 4715 cpu0-thermal { 4716 polling-delay-passive = <250>; 4717 polling-delay = <1000>; 4718 4719 thermal-sensors = <&tsens0 1>; 4720 4721 trips { 4722 cpu-crit { 4723 temperature = <110000>; 4724 hysteresis = <1000>; 4725 type = "critical"; 4726 }; 4727 }; 4728 }; 4729 4730 cpu1-thermal { 4731 polling-delay-passive = <250>; 4732 polling-delay = <1000>; 4733 4734 thermal-sensors = <&tsens0 2>; 4735 4736 trips { 4737 cpu-crit { 4738 temperature = <110000>; 4739 hysteresis = <1000>; 4740 type = "critical"; 4741 }; 4742 }; 4743 }; 4744 4745 cpu2-thermal { 4746 polling-delay-passive = <250>; 4747 polling-delay = <1000>; 4748 4749 thermal-sensors = <&tsens0 3>; 4750 4751 trips { 4752 cpu-crit { 4753 temperature = <110000>; 4754 hysteresis = <1000>; 4755 type = "critical"; 4756 }; 4757 }; 4758 }; 4759 4760 cpu3-thermal { 4761 polling-delay-passive = <250>; 4762 polling-delay = <1000>; 4763 4764 thermal-sensors = <&tsens0 4>; 4765 4766 trips { 4767 cpu-crit { 4768 temperature = <110000>; 4769 hysteresis = <1000>; 4770 type = "critical"; 4771 }; 4772 }; 4773 }; 4774 4775 cpu4-thermal { 4776 polling-delay-passive = <250>; 4777 polling-delay = <1000>; 4778 4779 thermal-sensors = <&tsens0 5>; 4780 4781 trips { 4782 cpu-crit { 4783 temperature = <110000>; 4784 hysteresis = <1000>; 4785 type = "critical"; 4786 }; 4787 }; 4788 }; 4789 4790 cpu5-thermal { 4791 polling-delay-passive = <250>; 4792 polling-delay = <1000>; 4793 4794 thermal-sensors = <&tsens0 6>; 4795 4796 trips { 4797 cpu-crit { 4798 temperature = <110000>; 4799 hysteresis = <1000>; 4800 type = "critical"; 4801 }; 4802 }; 4803 }; 4804 4805 cpu6-thermal { 4806 polling-delay-passive = <250>; 4807 polling-delay = <1000>; 4808 4809 thermal-sensors = <&tsens0 7>; 4810 4811 trips { 4812 cpu-crit { 4813 temperature = <110000>; 4814 hysteresis = <1000>; 4815 type = "critical"; 4816 }; 4817 }; 4818 }; 4819 4820 cpu7-thermal { 4821 polling-delay-passive = <250>; 4822 polling-delay = <1000>; 4823 4824 thermal-sensors = <&tsens0 8>; 4825 4826 trips { 4827 cpu-crit { 4828 temperature = <110000>; 4829 hysteresis = <1000>; 4830 type = "critical"; 4831 }; 4832 }; 4833 }; 4834 4835 cluster0-thermal { 4836 polling-delay-passive = <250>; 4837 polling-delay = <1000>; 4838 4839 thermal-sensors = <&tsens0 9>; 4840 4841 trips { 4842 cpu-crit { 4843 temperature = <110000>; 4844 hysteresis = <1000>; 4845 type = "critical"; 4846 }; 4847 }; 4848 }; 4849 4850 mem-thermal { 4851 polling-delay-passive = <250>; 4852 polling-delay = <1000>; 4853 4854 thermal-sensors = <&tsens1 15>; 4855 4856 trips { 4857 trip-point0 { 4858 temperature = <90000>; 4859 hysteresis = <2000>; 4860 type = "hot"; 4861 }; 4862 }; 4863 }; 4864 }; 4865 4866 timer { 4867 compatible = "arm,armv8-timer"; 4868 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4869 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4870 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4871 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 4872 }; 4873}; 4874