1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2020-2023, Linaro Limited 5 */ 6 7#include <dt-bindings/clock/qcom,dispcc-sm8250.h> 8#include <dt-bindings/clock/qcom,gcc-sc8180x.h> 9#include <dt-bindings/clock/qcom,gpucc-sm8150.h> 10#include <dt-bindings/clock/qcom,rpmh.h> 11#include <dt-bindings/interconnect/qcom,osm-l3.h> 12#include <dt-bindings/interconnect/qcom,sc8180x.h> 13#include <dt-bindings/interrupt-controller/arm-gic.h> 14#include <dt-bindings/power/qcom-rpmpd.h> 15#include <dt-bindings/soc/qcom,rpmh-rsc.h> 16#include <dt-bindings/thermal/thermal.h> 17 18/ { 19 interrupt-parent = <&intc>; 20 21 #address-cells = <2>; 22 #size-cells = <2>; 23 24 clocks { 25 xo_board_clk: xo-board { 26 compatible = "fixed-clock"; 27 #clock-cells = <0>; 28 clock-frequency = <38400000>; 29 }; 30 31 sleep_clk: sleep-clk { 32 compatible = "fixed-clock"; 33 #clock-cells = <0>; 34 clock-frequency = <32764>; 35 clock-output-names = "sleep_clk"; 36 }; 37 }; 38 39 cpus { 40 #address-cells = <2>; 41 #size-cells = <0>; 42 43 CPU0: cpu@0 { 44 device_type = "cpu"; 45 compatible = "qcom,kryo485"; 46 reg = <0x0 0x0>; 47 enable-method = "psci"; 48 capacity-dmips-mhz = <602>; 49 next-level-cache = <&L2_0>; 50 qcom,freq-domain = <&cpufreq_hw 0>; 51 operating-points-v2 = <&cpu0_opp_table>; 52 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, 53 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 54 power-domains = <&CPU_PD0>; 55 power-domain-names = "psci"; 56 #cooling-cells = <2>; 57 clocks = <&cpufreq_hw 0>; 58 59 L2_0: l2-cache { 60 compatible = "cache"; 61 cache-level = <2>; 62 cache-unified; 63 next-level-cache = <&L3_0>; 64 L3_0: l3-cache { 65 compatible = "cache"; 66 cache-level = <3>; 67 cache-unified; 68 }; 69 }; 70 }; 71 72 CPU1: cpu@100 { 73 device_type = "cpu"; 74 compatible = "qcom,kryo485"; 75 reg = <0x0 0x100>; 76 enable-method = "psci"; 77 capacity-dmips-mhz = <602>; 78 next-level-cache = <&L2_100>; 79 qcom,freq-domain = <&cpufreq_hw 0>; 80 operating-points-v2 = <&cpu0_opp_table>; 81 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, 82 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 83 power-domains = <&CPU_PD1>; 84 power-domain-names = "psci"; 85 #cooling-cells = <2>; 86 clocks = <&cpufreq_hw 0>; 87 88 L2_100: l2-cache { 89 compatible = "cache"; 90 cache-level = <2>; 91 cache-unified; 92 next-level-cache = <&L3_0>; 93 }; 94 95 }; 96 97 CPU2: cpu@200 { 98 device_type = "cpu"; 99 compatible = "qcom,kryo485"; 100 reg = <0x0 0x200>; 101 enable-method = "psci"; 102 capacity-dmips-mhz = <602>; 103 next-level-cache = <&L2_200>; 104 qcom,freq-domain = <&cpufreq_hw 0>; 105 operating-points-v2 = <&cpu0_opp_table>; 106 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, 107 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 108 power-domains = <&CPU_PD2>; 109 power-domain-names = "psci"; 110 #cooling-cells = <2>; 111 clocks = <&cpufreq_hw 0>; 112 113 L2_200: l2-cache { 114 compatible = "cache"; 115 cache-level = <2>; 116 cache-unified; 117 next-level-cache = <&L3_0>; 118 }; 119 }; 120 121 CPU3: cpu@300 { 122 device_type = "cpu"; 123 compatible = "qcom,kryo485"; 124 reg = <0x0 0x300>; 125 enable-method = "psci"; 126 capacity-dmips-mhz = <602>; 127 next-level-cache = <&L2_300>; 128 qcom,freq-domain = <&cpufreq_hw 0>; 129 operating-points-v2 = <&cpu0_opp_table>; 130 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, 131 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 132 power-domains = <&CPU_PD3>; 133 power-domain-names = "psci"; 134 #cooling-cells = <2>; 135 clocks = <&cpufreq_hw 0>; 136 137 L2_300: l2-cache { 138 compatible = "cache"; 139 cache-unified; 140 cache-level = <2>; 141 next-level-cache = <&L3_0>; 142 }; 143 }; 144 145 CPU4: cpu@400 { 146 device_type = "cpu"; 147 compatible = "qcom,kryo485"; 148 reg = <0x0 0x400>; 149 enable-method = "psci"; 150 capacity-dmips-mhz = <1024>; 151 next-level-cache = <&L2_400>; 152 qcom,freq-domain = <&cpufreq_hw 1>; 153 operating-points-v2 = <&cpu4_opp_table>; 154 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, 155 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 156 power-domains = <&CPU_PD4>; 157 power-domain-names = "psci"; 158 #cooling-cells = <2>; 159 clocks = <&cpufreq_hw 1>; 160 161 L2_400: l2-cache { 162 compatible = "cache"; 163 cache-unified; 164 cache-level = <2>; 165 next-level-cache = <&L3_0>; 166 }; 167 }; 168 169 CPU5: cpu@500 { 170 device_type = "cpu"; 171 compatible = "qcom,kryo485"; 172 reg = <0x0 0x500>; 173 enable-method = "psci"; 174 capacity-dmips-mhz = <1024>; 175 next-level-cache = <&L2_500>; 176 qcom,freq-domain = <&cpufreq_hw 1>; 177 operating-points-v2 = <&cpu4_opp_table>; 178 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, 179 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 180 power-domains = <&CPU_PD5>; 181 power-domain-names = "psci"; 182 #cooling-cells = <2>; 183 clocks = <&cpufreq_hw 1>; 184 185 L2_500: l2-cache { 186 compatible = "cache"; 187 cache-unified; 188 cache-level = <2>; 189 next-level-cache = <&L3_0>; 190 }; 191 }; 192 193 CPU6: cpu@600 { 194 device_type = "cpu"; 195 compatible = "qcom,kryo485"; 196 reg = <0x0 0x600>; 197 enable-method = "psci"; 198 capacity-dmips-mhz = <1024>; 199 next-level-cache = <&L2_600>; 200 qcom,freq-domain = <&cpufreq_hw 1>; 201 operating-points-v2 = <&cpu4_opp_table>; 202 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, 203 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 204 power-domains = <&CPU_PD6>; 205 power-domain-names = "psci"; 206 #cooling-cells = <2>; 207 clocks = <&cpufreq_hw 1>; 208 209 L2_600: l2-cache { 210 compatible = "cache"; 211 cache-unified; 212 cache-level = <2>; 213 next-level-cache = <&L3_0>; 214 }; 215 }; 216 217 CPU7: cpu@700 { 218 device_type = "cpu"; 219 compatible = "qcom,kryo485"; 220 reg = <0x0 0x700>; 221 enable-method = "psci"; 222 capacity-dmips-mhz = <1024>; 223 next-level-cache = <&L2_700>; 224 qcom,freq-domain = <&cpufreq_hw 1>; 225 operating-points-v2 = <&cpu4_opp_table>; 226 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, 227 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 228 power-domains = <&CPU_PD7>; 229 power-domain-names = "psci"; 230 #cooling-cells = <2>; 231 clocks = <&cpufreq_hw 1>; 232 233 L2_700: l2-cache { 234 compatible = "cache"; 235 cache-unified; 236 cache-level = <2>; 237 next-level-cache = <&L3_0>; 238 }; 239 }; 240 241 cpu-map { 242 cluster0 { 243 core0 { 244 cpu = <&CPU0>; 245 }; 246 247 core1 { 248 cpu = <&CPU1>; 249 }; 250 251 core2 { 252 cpu = <&CPU2>; 253 }; 254 255 core3 { 256 cpu = <&CPU3>; 257 }; 258 259 core4 { 260 cpu = <&CPU4>; 261 }; 262 263 core5 { 264 cpu = <&CPU5>; 265 }; 266 267 core6 { 268 cpu = <&CPU6>; 269 }; 270 271 core7 { 272 cpu = <&CPU7>; 273 }; 274 }; 275 }; 276 277 idle-states { 278 entry-method = "psci"; 279 280 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 281 compatible = "arm,idle-state"; 282 arm,psci-suspend-param = <0x40000004>; 283 entry-latency-us = <355>; 284 exit-latency-us = <909>; 285 min-residency-us = <3934>; 286 local-timer-stop; 287 }; 288 289 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 290 compatible = "arm,idle-state"; 291 arm,psci-suspend-param = <0x40000004>; 292 entry-latency-us = <2411>; 293 exit-latency-us = <1461>; 294 min-residency-us = <4488>; 295 local-timer-stop; 296 }; 297 }; 298 299 domain-idle-states { 300 CLUSTER_SLEEP_APSS_OFF: cluster-sleep-0 { 301 compatible = "domain-idle-state"; 302 arm,psci-suspend-param = <0x41000044>; 303 entry-latency-us = <3300>; 304 exit-latency-us = <3300>; 305 min-residency-us = <6000>; 306 }; 307 308 CLUSTER_SLEEP_AOSS_SLEEP: cluster-sleep-1 { 309 compatible = "domain-idle-state"; 310 arm,psci-suspend-param = <0x4100a344>; 311 entry-latency-us = <3263>; 312 exit-latency-us = <6562>; 313 min-residency-us = <9987>; 314 }; 315 }; 316 }; 317 318 cpu0_opp_table: opp-table-cpu0 { 319 compatible = "operating-points-v2"; 320 opp-shared; 321 322 opp-300000000 { 323 opp-hz = /bits/ 64 <300000000>; 324 opp-peak-kBps = <800000 9600000>; 325 }; 326 327 opp-422400000 { 328 opp-hz = /bits/ 64 <422400000>; 329 opp-peak-kBps = <800000 9600000>; 330 }; 331 332 opp-537600000 { 333 opp-hz = /bits/ 64 <537600000>; 334 opp-peak-kBps = <800000 12902400>; 335 }; 336 337 opp-652800000 { 338 opp-hz = /bits/ 64 <652800000>; 339 opp-peak-kBps = <800000 12902400>; 340 }; 341 342 opp-768000000 { 343 opp-hz = /bits/ 64 <768000000>; 344 opp-peak-kBps = <800000 15974400>; 345 }; 346 347 opp-883200000 { 348 opp-hz = /bits/ 64 <883200000>; 349 opp-peak-kBps = <1804000 19660800>; 350 }; 351 352 opp-998400000 { 353 opp-hz = /bits/ 64 <998400000>; 354 opp-peak-kBps = <1804000 19660800>; 355 }; 356 357 opp-1113600000 { 358 opp-hz = /bits/ 64 <1113600000>; 359 opp-peak-kBps = <1804000 22732800>; 360 }; 361 362 opp-1228800000 { 363 opp-hz = /bits/ 64 <1228800000>; 364 opp-peak-kBps = <1804000 22732800>; 365 }; 366 367 opp-1363200000 { 368 opp-hz = /bits/ 64 <1363200000>; 369 opp-peak-kBps = <2188000 25804800>; 370 }; 371 372 opp-1478400000 { 373 opp-hz = /bits/ 64 <1478400000>; 374 opp-peak-kBps = <2188000 31948800>; 375 }; 376 377 opp-1574400000 { 378 opp-hz = /bits/ 64 <1574400000>; 379 opp-peak-kBps = <3072000 31948800>; 380 }; 381 382 opp-1670400000 { 383 opp-hz = /bits/ 64 <1670400000>; 384 opp-peak-kBps = <3072000 31948800>; 385 }; 386 387 opp-1766400000 { 388 opp-hz = /bits/ 64 <1766400000>; 389 opp-peak-kBps = <3072000 31948800>; 390 }; 391 }; 392 393 cpu4_opp_table: opp-table-cpu4 { 394 compatible = "operating-points-v2"; 395 opp-shared; 396 397 opp-825600000 { 398 opp-hz = /bits/ 64 <825600000>; 399 opp-peak-kBps = <1804000 15974400>; 400 }; 401 402 opp-940800000 { 403 opp-hz = /bits/ 64 <940800000>; 404 opp-peak-kBps = <2188000 19660800>; 405 }; 406 407 opp-1056000000 { 408 opp-hz = /bits/ 64 <1056000000>; 409 opp-peak-kBps = <2188000 22732800>; 410 }; 411 412 opp-1171200000 { 413 opp-hz = /bits/ 64 <1171200000>; 414 opp-peak-kBps = <3072000 25804800>; 415 }; 416 417 opp-1286400000 { 418 opp-hz = /bits/ 64 <1286400000>; 419 opp-peak-kBps = <3072000 31948800>; 420 }; 421 422 opp-1420800000 { 423 opp-hz = /bits/ 64 <1420800000>; 424 opp-peak-kBps = <4068000 31948800>; 425 }; 426 427 opp-1536000000 { 428 opp-hz = /bits/ 64 <1536000000>; 429 opp-peak-kBps = <4068000 31948800>; 430 }; 431 432 opp-1651200000 { 433 opp-hz = /bits/ 64 <1651200000>; 434 opp-peak-kBps = <4068000 40550400>; 435 }; 436 437 opp-1766400000 { 438 opp-hz = /bits/ 64 <1766400000>; 439 opp-peak-kBps = <4068000 40550400>; 440 }; 441 442 opp-1881600000 { 443 opp-hz = /bits/ 64 <1881600000>; 444 opp-peak-kBps = <4068000 43008000>; 445 }; 446 447 opp-1996800000 { 448 opp-hz = /bits/ 64 <1996800000>; 449 opp-peak-kBps = <6220000 43008000>; 450 }; 451 452 opp-2131200000 { 453 opp-hz = /bits/ 64 <2131200000>; 454 opp-peak-kBps = <6220000 49152000>; 455 }; 456 457 opp-2246400000 { 458 opp-hz = /bits/ 64 <2246400000>; 459 opp-peak-kBps = <7216000 49152000>; 460 }; 461 462 opp-2361600000 { 463 opp-hz = /bits/ 64 <2361600000>; 464 opp-peak-kBps = <8368000 49152000>; 465 }; 466 467 opp-2457600000 { 468 opp-hz = /bits/ 64 <2457600000>; 469 opp-peak-kBps = <8368000 51609600>; 470 }; 471 472 opp-2553600000 { 473 opp-hz = /bits/ 64 <2553600000>; 474 opp-peak-kBps = <8368000 51609600>; 475 }; 476 477 opp-2649600000 { 478 opp-hz = /bits/ 64 <2649600000>; 479 opp-peak-kBps = <8368000 51609600>; 480 }; 481 482 opp-2745600000 { 483 opp-hz = /bits/ 64 <2745600000>; 484 opp-peak-kBps = <8368000 51609600>; 485 }; 486 487 opp-2841600000 { 488 opp-hz = /bits/ 64 <2841600000>; 489 opp-peak-kBps = <8368000 51609600>; 490 }; 491 492 opp-2918400000 { 493 opp-hz = /bits/ 64 <2918400000>; 494 opp-peak-kBps = <8368000 51609600>; 495 }; 496 497 opp-2995200000 { 498 opp-hz = /bits/ 64 <2995200000>; 499 opp-peak-kBps = <8368000 51609600>; 500 }; 501 }; 502 503 firmware { 504 scm: scm { 505 compatible = "qcom,scm-sc8180x", "qcom,scm"; 506 }; 507 }; 508 509 camnoc_virt: interconnect-camnoc-virt { 510 compatible = "qcom,sc8180x-camnoc-virt"; 511 #interconnect-cells = <2>; 512 qcom,bcm-voters = <&apps_bcm_voter>; 513 }; 514 515 mc_virt: interconnect-mc-virt { 516 compatible = "qcom,sc8180x-mc-virt"; 517 #interconnect-cells = <2>; 518 qcom,bcm-voters = <&apps_bcm_voter>; 519 }; 520 521 qup_virt: interconnect-qup-virt { 522 compatible = "qcom,sc8180x-qup-virt"; 523 #interconnect-cells = <2>; 524 qcom,bcm-voters = <&apps_bcm_voter>; 525 }; 526 527 memory@80000000 { 528 device_type = "memory"; 529 /* We expect the bootloader to fill in the size */ 530 reg = <0x0 0x80000000 0x0 0x0>; 531 }; 532 533 pmu { 534 compatible = "arm,armv8-pmuv3"; 535 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; 536 }; 537 538 psci { 539 compatible = "arm,psci-1.0"; 540 method = "smc"; 541 542 CPU_PD0: power-domain-cpu0 { 543 #power-domain-cells = <0>; 544 power-domains = <&CLUSTER_PD>; 545 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 546 }; 547 548 CPU_PD1: power-domain-cpu1 { 549 #power-domain-cells = <0>; 550 power-domains = <&CLUSTER_PD>; 551 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 552 }; 553 554 CPU_PD2: power-domain-cpu2 { 555 #power-domain-cells = <0>; 556 power-domains = <&CLUSTER_PD>; 557 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 558 }; 559 560 CPU_PD3: power-domain-cpu3 { 561 #power-domain-cells = <0>; 562 power-domains = <&CLUSTER_PD>; 563 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 564 }; 565 566 CPU_PD4: power-domain-cpu4 { 567 #power-domain-cells = <0>; 568 power-domains = <&CLUSTER_PD>; 569 domain-idle-states = <&BIG_CPU_SLEEP_0>; 570 }; 571 572 CPU_PD5: power-domain-cpu5 { 573 #power-domain-cells = <0>; 574 power-domains = <&CLUSTER_PD>; 575 domain-idle-states = <&BIG_CPU_SLEEP_0>; 576 }; 577 578 CPU_PD6: power-domain-cpu6 { 579 #power-domain-cells = <0>; 580 power-domains = <&CLUSTER_PD>; 581 domain-idle-states = <&BIG_CPU_SLEEP_0>; 582 }; 583 584 CPU_PD7: power-domain-cpu7 { 585 #power-domain-cells = <0>; 586 power-domains = <&CLUSTER_PD>; 587 domain-idle-states = <&BIG_CPU_SLEEP_0>; 588 }; 589 590 CLUSTER_PD: power-domain-cpu-cluster0 { 591 #power-domain-cells = <0>; 592 domain-idle-states = <&CLUSTER_SLEEP_APSS_OFF &CLUSTER_SLEEP_AOSS_SLEEP>; 593 }; 594 }; 595 596 reserved-memory { 597 #address-cells = <2>; 598 #size-cells = <2>; 599 ranges; 600 601 hyp_mem: hyp@85700000 { 602 reg = <0x0 0x85700000 0x0 0x600000>; 603 no-map; 604 }; 605 606 xbl_mem: xbl@85d00000 { 607 reg = <0x0 0x85d00000 0x0 0x140000>; 608 no-map; 609 }; 610 611 aop_mem: aop@85f00000 { 612 reg = <0x0 0x85f00000 0x0 0x20000>; 613 no-map; 614 }; 615 616 aop_cmd_db: cmd-db@85f20000 { 617 compatible = "qcom,cmd-db"; 618 reg = <0x0 0x85f20000 0x0 0x20000>; 619 no-map; 620 }; 621 622 reserved@85f40000 { 623 reg = <0x0 0x85f40000 0x0 0x10000>; 624 no-map; 625 }; 626 627 smem_mem: smem@86000000 { 628 compatible = "qcom,smem"; 629 reg = <0x0 0x86000000 0x0 0x200000>; 630 no-map; 631 hwlocks = <&tcsr_mutex 3>; 632 }; 633 634 reserved@86200000 { 635 reg = <0x0 0x86200000 0x0 0x3900000>; 636 no-map; 637 }; 638 639 reserved@89b00000 { 640 reg = <0x0 0x89b00000 0x0 0x1c00000>; 641 no-map; 642 }; 643 644 reserved@9d400000 { 645 reg = <0x0 0x9d400000 0x0 0x1000000>; 646 no-map; 647 }; 648 649 reserved@9e400000 { 650 reg = <0x0 0x9e400000 0x0 0x1400000>; 651 no-map; 652 }; 653 654 reserved@9f800000 { 655 reg = <0x0 0x9f800000 0x0 0x800000>; 656 no-map; 657 }; 658 }; 659 660 smp2p-cdsp { 661 compatible = "qcom,smp2p"; 662 qcom,smem = <94>, <432>; 663 664 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; 665 666 mboxes = <&apss_shared 6>; 667 668 qcom,local-pid = <0>; 669 qcom,remote-pid = <5>; 670 671 cdsp_smp2p_out: master-kernel { 672 qcom,entry-name = "master-kernel"; 673 #qcom,smem-state-cells = <1>; 674 }; 675 676 cdsp_smp2p_in: slave-kernel { 677 qcom,entry-name = "slave-kernel"; 678 679 interrupt-controller; 680 #interrupt-cells = <2>; 681 }; 682 }; 683 684 smp2p-lpass { 685 compatible = "qcom,smp2p"; 686 qcom,smem = <443>, <429>; 687 688 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 689 690 mboxes = <&apss_shared 10>; 691 692 qcom,local-pid = <0>; 693 qcom,remote-pid = <2>; 694 695 adsp_smp2p_out: master-kernel { 696 qcom,entry-name = "master-kernel"; 697 #qcom,smem-state-cells = <1>; 698 }; 699 700 adsp_smp2p_in: slave-kernel { 701 qcom,entry-name = "slave-kernel"; 702 703 interrupt-controller; 704 #interrupt-cells = <2>; 705 }; 706 }; 707 708 smp2p-mpss { 709 compatible = "qcom,smp2p"; 710 qcom,smem = <435>, <428>; 711 712 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 713 714 mboxes = <&apss_shared 14>; 715 716 qcom,local-pid = <0>; 717 qcom,remote-pid = <1>; 718 719 modem_smp2p_out: master-kernel { 720 qcom,entry-name = "master-kernel"; 721 #qcom,smem-state-cells = <1>; 722 }; 723 724 modem_smp2p_in: slave-kernel { 725 qcom,entry-name = "slave-kernel"; 726 727 interrupt-controller; 728 #interrupt-cells = <2>; 729 }; 730 731 modem_smp2p_ipa_out: ipa-ap-to-modem { 732 qcom,entry-name = "ipa"; 733 #qcom,smem-state-cells = <1>; 734 }; 735 736 modem_smp2p_ipa_in: ipa-modem-to-ap { 737 qcom,entry-name = "ipa"; 738 interrupt-controller; 739 #interrupt-cells = <2>; 740 }; 741 742 modem_smp2p_wlan_in: wlan-wpss-to-ap { 743 qcom,entry-name = "wlan"; 744 interrupt-controller; 745 #interrupt-cells = <2>; 746 }; 747 }; 748 749 smp2p-slpi { 750 compatible = "qcom,smp2p"; 751 qcom,smem = <481>, <430>; 752 753 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>; 754 755 mboxes = <&apss_shared 26>; 756 757 qcom,local-pid = <0>; 758 qcom,remote-pid = <3>; 759 760 slpi_smp2p_out: master-kernel { 761 qcom,entry-name = "master-kernel"; 762 #qcom,smem-state-cells = <1>; 763 }; 764 765 slpi_smp2p_in: slave-kernel { 766 qcom,entry-name = "slave-kernel"; 767 768 interrupt-controller; 769 #interrupt-cells = <2>; 770 }; 771 }; 772 773 soc: soc@0 { 774 compatible = "simple-bus"; 775 #address-cells = <2>; 776 #size-cells = <2>; 777 ranges = <0 0 0 0 0x10 0>; 778 dma-ranges = <0 0 0 0 0x10 0>; 779 780 gcc: clock-controller@100000 { 781 compatible = "qcom,gcc-sc8180x"; 782 reg = <0x0 0x00100000 0x0 0x1f0000>; 783 #clock-cells = <1>; 784 #reset-cells = <1>; 785 #power-domain-cells = <1>; 786 clocks = <&rpmhcc RPMH_CXO_CLK>, 787 <&rpmhcc RPMH_CXO_CLK_A>, 788 <&sleep_clk>; 789 clock-names = "bi_tcxo", 790 "bi_tcxo_ao", 791 "sleep_clk"; 792 power-domains = <&rpmhpd SC8180X_CX>; 793 }; 794 795 qupv3_id_0: geniqup@8c0000 { 796 compatible = "qcom,geni-se-qup"; 797 reg = <0 0x008c0000 0 0x6000>; 798 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 799 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 800 clock-names = "m-ahb", "s-ahb"; 801 #address-cells = <2>; 802 #size-cells = <2>; 803 ranges; 804 iommus = <&apps_smmu 0x4c3 0>; 805 status = "disabled"; 806 807 i2c0: i2c@880000 { 808 compatible = "qcom,geni-i2c"; 809 reg = <0 0x00880000 0 0x4000>; 810 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 811 clock-names = "se"; 812 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 813 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 814 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 815 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 816 interconnect-names = "qup-core", "qup-config", "qup-memory"; 817 #address-cells = <1>; 818 #size-cells = <0>; 819 status = "disabled"; 820 }; 821 822 spi0: spi@880000 { 823 compatible = "qcom,geni-spi"; 824 reg = <0 0x00880000 0 0x4000>; 825 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 826 clock-names = "se"; 827 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 828 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 829 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 830 interconnect-names = "qup-core", "qup-config"; 831 #address-cells = <1>; 832 #size-cells = <0>; 833 status = "disabled"; 834 }; 835 836 uart0: serial@880000 { 837 compatible = "qcom,geni-uart"; 838 reg = <0 0x00880000 0 0x4000>; 839 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 840 clock-names = "se"; 841 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 842 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 843 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 844 interconnect-names = "qup-core", "qup-config"; 845 status = "disabled"; 846 }; 847 848 i2c1: i2c@884000 { 849 compatible = "qcom,geni-i2c"; 850 reg = <0 0x00884000 0 0x4000>; 851 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 852 clock-names = "se"; 853 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 854 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 855 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 856 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 857 interconnect-names = "qup-core", "qup-config", "qup-memory"; 858 #address-cells = <1>; 859 #size-cells = <0>; 860 status = "disabled"; 861 }; 862 863 spi1: spi@884000 { 864 compatible = "qcom,geni-spi"; 865 reg = <0 0x00884000 0 0x4000>; 866 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 867 clock-names = "se"; 868 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 869 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 870 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 871 interconnect-names = "qup-core", "qup-config"; 872 #address-cells = <1>; 873 #size-cells = <0>; 874 status = "disabled"; 875 }; 876 877 uart1: serial@884000 { 878 compatible = "qcom,geni-uart"; 879 reg = <0 0x00884000 0 0x4000>; 880 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 881 clock-names = "se"; 882 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 883 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 884 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 885 interconnect-names = "qup-core", "qup-config"; 886 status = "disabled"; 887 }; 888 889 i2c2: i2c@888000 { 890 compatible = "qcom,geni-i2c"; 891 reg = <0 0x00888000 0 0x4000>; 892 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 893 clock-names = "se"; 894 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 895 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 896 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 897 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 898 interconnect-names = "qup-core", "qup-config", "qup-memory"; 899 #address-cells = <1>; 900 #size-cells = <0>; 901 status = "disabled"; 902 }; 903 904 spi2: spi@888000 { 905 compatible = "qcom,geni-spi"; 906 reg = <0 0x00888000 0 0x4000>; 907 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 908 clock-names = "se"; 909 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 910 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 911 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 912 interconnect-names = "qup-core", "qup-config"; 913 #address-cells = <1>; 914 #size-cells = <0>; 915 status = "disabled"; 916 }; 917 918 uart2: serial@888000 { 919 compatible = "qcom,geni-uart"; 920 reg = <0 0x00888000 0 0x4000>; 921 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 922 clock-names = "se"; 923 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 924 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 925 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 926 interconnect-names = "qup-core", "qup-config"; 927 status = "disabled"; 928 }; 929 930 i2c3: i2c@88c000 { 931 compatible = "qcom,geni-i2c"; 932 reg = <0 0x0088c000 0 0x4000>; 933 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 934 clock-names = "se"; 935 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 936 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 937 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 938 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 939 interconnect-names = "qup-core", "qup-config", "qup-memory"; 940 #address-cells = <1>; 941 #size-cells = <0>; 942 status = "disabled"; 943 }; 944 945 spi3: spi@88c000 { 946 compatible = "qcom,geni-spi"; 947 reg = <0 0x0088c000 0 0x4000>; 948 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 949 clock-names = "se"; 950 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 951 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 952 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 953 interconnect-names = "qup-core", "qup-config"; 954 #address-cells = <1>; 955 #size-cells = <0>; 956 status = "disabled"; 957 }; 958 959 uart3: serial@88c000 { 960 compatible = "qcom,geni-uart"; 961 reg = <0 0x0088c000 0 0x4000>; 962 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 963 clock-names = "se"; 964 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 965 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 966 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 967 interconnect-names = "qup-core", "qup-config"; 968 status = "disabled"; 969 }; 970 971 i2c4: i2c@890000 { 972 compatible = "qcom,geni-i2c"; 973 reg = <0 0x00890000 0 0x4000>; 974 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 975 clock-names = "se"; 976 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 977 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 978 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 979 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 980 interconnect-names = "qup-core", "qup-config", "qup-memory"; 981 #address-cells = <1>; 982 #size-cells = <0>; 983 status = "disabled"; 984 }; 985 986 spi4: spi@890000 { 987 compatible = "qcom,geni-spi"; 988 reg = <0 0x00890000 0 0x4000>; 989 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 990 clock-names = "se"; 991 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 992 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 993 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 994 interconnect-names = "qup-core", "qup-config"; 995 #address-cells = <1>; 996 #size-cells = <0>; 997 status = "disabled"; 998 }; 999 1000 uart4: serial@890000 { 1001 compatible = "qcom,geni-uart"; 1002 reg = <0 0x00890000 0 0x4000>; 1003 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1004 clock-names = "se"; 1005 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1006 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1007 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 1008 interconnect-names = "qup-core", "qup-config"; 1009 status = "disabled"; 1010 }; 1011 1012 i2c5: i2c@894000 { 1013 compatible = "qcom,geni-i2c"; 1014 reg = <0 0x00894000 0 0x4000>; 1015 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1016 clock-names = "se"; 1017 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1018 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1019 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1020 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1021 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1022 #address-cells = <1>; 1023 #size-cells = <0>; 1024 status = "disabled"; 1025 }; 1026 1027 spi5: spi@894000 { 1028 compatible = "qcom,geni-spi"; 1029 reg = <0 0x00894000 0 0x4000>; 1030 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1031 clock-names = "se"; 1032 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1033 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1034 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 1035 interconnect-names = "qup-core", "qup-config"; 1036 #address-cells = <1>; 1037 #size-cells = <0>; 1038 status = "disabled"; 1039 }; 1040 1041 uart5: serial@894000 { 1042 compatible = "qcom,geni-uart"; 1043 reg = <0 0x00894000 0 0x4000>; 1044 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1045 clock-names = "se"; 1046 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1047 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1048 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 1049 interconnect-names = "qup-core", "qup-config"; 1050 status = "disabled"; 1051 }; 1052 1053 i2c6: i2c@898000 { 1054 compatible = "qcom,geni-i2c"; 1055 reg = <0 0x00898000 0 0x4000>; 1056 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1057 clock-names = "se"; 1058 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1059 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1060 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1061 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1062 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1063 #address-cells = <1>; 1064 #size-cells = <0>; 1065 status = "disabled"; 1066 }; 1067 1068 spi6: spi@898000 { 1069 compatible = "qcom,geni-spi"; 1070 reg = <0 0x00898000 0 0x4000>; 1071 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1072 clock-names = "se"; 1073 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1074 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1075 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 1076 interconnect-names = "qup-core", "qup-config"; 1077 #address-cells = <1>; 1078 #size-cells = <0>; 1079 status = "disabled"; 1080 }; 1081 1082 uart6: serial@898000 { 1083 compatible = "qcom,geni-uart"; 1084 reg = <0 0x00898000 0 0x4000>; 1085 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1086 clock-names = "se"; 1087 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1088 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1089 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 1090 interconnect-names = "qup-core", "qup-config"; 1091 status = "disabled"; 1092 }; 1093 1094 i2c7: i2c@89c000 { 1095 compatible = "qcom,geni-i2c"; 1096 reg = <0 0x0089c000 0 0x4000>; 1097 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1098 clock-names = "se"; 1099 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1100 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1101 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1102 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1103 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1104 #address-cells = <1>; 1105 #size-cells = <0>; 1106 status = "disabled"; 1107 }; 1108 1109 spi7: spi@89c000 { 1110 compatible = "qcom,geni-spi"; 1111 reg = <0 0x0089c000 0 0x4000>; 1112 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1113 clock-names = "se"; 1114 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1115 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1116 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 1117 interconnect-names = "qup-core", "qup-config"; 1118 #address-cells = <1>; 1119 #size-cells = <0>; 1120 status = "disabled"; 1121 }; 1122 1123 uart7: serial@89c000 { 1124 compatible = "qcom,geni-uart"; 1125 reg = <0 0x0089c000 0 0x4000>; 1126 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1127 clock-names = "se"; 1128 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1129 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1130 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 1131 interconnect-names = "qup-core", "qup-config"; 1132 status = "disabled"; 1133 }; 1134 }; 1135 1136 qupv3_id_1: geniqup@ac0000 { 1137 compatible = "qcom,geni-se-qup"; 1138 reg = <0x0 0x00ac0000 0x0 0x6000>; 1139 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1140 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1141 clock-names = "m-ahb", "s-ahb"; 1142 #address-cells = <2>; 1143 #size-cells = <2>; 1144 ranges; 1145 iommus = <&apps_smmu 0x603 0>; 1146 status = "disabled"; 1147 1148 i2c8: i2c@a80000 { 1149 compatible = "qcom,geni-i2c"; 1150 reg = <0 0x00a80000 0 0x4000>; 1151 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1152 clock-names = "se"; 1153 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1154 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1155 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1156 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1157 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1158 #address-cells = <1>; 1159 #size-cells = <0>; 1160 status = "disabled"; 1161 }; 1162 1163 spi8: spi@a80000 { 1164 compatible = "qcom,geni-spi"; 1165 reg = <0 0x00a80000 0 0x4000>; 1166 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1167 clock-names = "se"; 1168 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1169 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1170 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1171 interconnect-names = "qup-core", "qup-config"; 1172 #address-cells = <1>; 1173 #size-cells = <0>; 1174 status = "disabled"; 1175 }; 1176 1177 uart8: serial@a80000 { 1178 compatible = "qcom,geni-uart"; 1179 reg = <0 0x00a80000 0 0x4000>; 1180 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1181 clock-names = "se"; 1182 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1183 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1184 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1185 interconnect-names = "qup-core", "qup-config"; 1186 status = "disabled"; 1187 }; 1188 1189 i2c9: i2c@a84000 { 1190 compatible = "qcom,geni-i2c"; 1191 reg = <0 0x00a84000 0 0x4000>; 1192 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1193 clock-names = "se"; 1194 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1195 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1196 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1197 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1198 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1199 #address-cells = <1>; 1200 #size-cells = <0>; 1201 status = "disabled"; 1202 }; 1203 1204 spi9: spi@a84000 { 1205 compatible = "qcom,geni-spi"; 1206 reg = <0 0x00a84000 0 0x4000>; 1207 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1208 clock-names = "se"; 1209 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1210 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1211 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1212 interconnect-names = "qup-core", "qup-config"; 1213 #address-cells = <1>; 1214 #size-cells = <0>; 1215 status = "disabled"; 1216 }; 1217 1218 uart9: serial@a84000 { 1219 compatible = "qcom,geni-debug-uart"; 1220 reg = <0 0x00a84000 0 0x4000>; 1221 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1222 clock-names = "se"; 1223 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1224 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1225 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1226 interconnect-names = "qup-core", "qup-config"; 1227 status = "disabled"; 1228 }; 1229 1230 i2c10: i2c@a88000 { 1231 compatible = "qcom,geni-i2c"; 1232 reg = <0 0x00a88000 0 0x4000>; 1233 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1234 clock-names = "se"; 1235 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1236 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1237 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1238 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1239 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1240 #address-cells = <1>; 1241 #size-cells = <0>; 1242 status = "disabled"; 1243 }; 1244 1245 spi10: spi@a88000 { 1246 compatible = "qcom,geni-spi"; 1247 reg = <0 0x00a88000 0 0x4000>; 1248 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1249 clock-names = "se"; 1250 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1251 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1252 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1253 interconnect-names = "qup-core", "qup-config"; 1254 #address-cells = <1>; 1255 #size-cells = <0>; 1256 status = "disabled"; 1257 }; 1258 1259 uart10: serial@a88000 { 1260 compatible = "qcom,geni-uart"; 1261 reg = <0 0x00a88000 0 0x4000>; 1262 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1263 clock-names = "se"; 1264 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1265 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1266 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1267 interconnect-names = "qup-core", "qup-config"; 1268 status = "disabled"; 1269 }; 1270 1271 i2c11: i2c@a8c000 { 1272 compatible = "qcom,geni-i2c"; 1273 reg = <0 0x00a8c000 0 0x4000>; 1274 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1275 clock-names = "se"; 1276 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1277 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1278 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1279 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1280 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1281 #address-cells = <1>; 1282 #size-cells = <0>; 1283 status = "disabled"; 1284 }; 1285 1286 spi11: spi@a8c000 { 1287 compatible = "qcom,geni-spi"; 1288 reg = <0 0x00a8c000 0 0x4000>; 1289 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1290 clock-names = "se"; 1291 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1292 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1293 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1294 interconnect-names = "qup-core", "qup-config"; 1295 #address-cells = <1>; 1296 #size-cells = <0>; 1297 status = "disabled"; 1298 }; 1299 1300 uart11: serial@a8c000 { 1301 compatible = "qcom,geni-uart"; 1302 reg = <0 0x00a8c000 0 0x4000>; 1303 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1304 clock-names = "se"; 1305 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1306 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1307 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1308 interconnect-names = "qup-core", "qup-config"; 1309 status = "disabled"; 1310 }; 1311 1312 i2c12: i2c@a90000 { 1313 compatible = "qcom,geni-i2c"; 1314 reg = <0 0x00a90000 0 0x4000>; 1315 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1316 clock-names = "se"; 1317 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1318 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1319 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1320 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1321 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1322 #address-cells = <1>; 1323 #size-cells = <0>; 1324 status = "disabled"; 1325 }; 1326 1327 spi12: spi@a90000 { 1328 compatible = "qcom,geni-spi"; 1329 reg = <0 0x00a90000 0 0x4000>; 1330 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1331 clock-names = "se"; 1332 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1333 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1334 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1335 interconnect-names = "qup-core", "qup-config"; 1336 #address-cells = <1>; 1337 #size-cells = <0>; 1338 status = "disabled"; 1339 }; 1340 1341 uart12: serial@a90000 { 1342 compatible = "qcom,geni-uart"; 1343 reg = <0 0x00a90000 0 0x4000>; 1344 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1345 clock-names = "se"; 1346 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1347 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1348 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1349 interconnect-names = "qup-core", "qup-config"; 1350 status = "disabled"; 1351 }; 1352 1353 i2c16: i2c@a94000 { 1354 compatible = "qcom,geni-i2c"; 1355 reg = <0 0x00a94000 0 0x4000>; 1356 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1357 clock-names = "se"; 1358 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1359 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1360 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1361 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1362 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1363 #address-cells = <1>; 1364 #size-cells = <0>; 1365 status = "disabled"; 1366 }; 1367 1368 spi16: spi@a94000 { 1369 compatible = "qcom,geni-spi"; 1370 reg = <0 0x00a94000 0 0x4000>; 1371 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1372 clock-names = "se"; 1373 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1374 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1375 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1376 interconnect-names = "qup-core", "qup-config"; 1377 #address-cells = <1>; 1378 #size-cells = <0>; 1379 status = "disabled"; 1380 }; 1381 1382 uart16: serial@a94000 { 1383 compatible = "qcom,geni-uart"; 1384 reg = <0 0x00a94000 0 0x4000>; 1385 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1386 clock-names = "se"; 1387 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1388 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1389 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1390 interconnect-names = "qup-core", "qup-config"; 1391 status = "disabled"; 1392 }; 1393 }; 1394 1395 qupv3_id_2: geniqup@cc0000 { 1396 compatible = "qcom,geni-se-qup"; 1397 reg = <0x0 0x00cc0000 0x0 0x6000>; 1398 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 1399 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 1400 clock-names = "m-ahb", "s-ahb"; 1401 #address-cells = <2>; 1402 #size-cells = <2>; 1403 ranges; 1404 iommus = <&apps_smmu 0x7a3 0>; 1405 status = "disabled"; 1406 1407 i2c17: i2c@c80000 { 1408 compatible = "qcom,geni-i2c"; 1409 reg = <0 0x00c80000 0 0x4000>; 1410 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1411 clock-names = "se"; 1412 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1413 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1414 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1415 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1416 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1417 #address-cells = <1>; 1418 #size-cells = <0>; 1419 status = "disabled"; 1420 }; 1421 1422 spi17: spi@c80000 { 1423 compatible = "qcom,geni-spi"; 1424 reg = <0 0x00c80000 0 0x4000>; 1425 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1426 clock-names = "se"; 1427 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1428 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1429 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1430 interconnect-names = "qup-core", "qup-config"; 1431 #address-cells = <1>; 1432 #size-cells = <0>; 1433 status = "disabled"; 1434 }; 1435 1436 uart17: serial@c80000 { 1437 compatible = "qcom,geni-uart"; 1438 reg = <0 0x00c80000 0 0x4000>; 1439 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1440 clock-names = "se"; 1441 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1442 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1443 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1444 interconnect-names = "qup-core", "qup-config"; 1445 status = "disabled"; 1446 }; 1447 1448 i2c18: i2c@c84000 { 1449 compatible = "qcom,geni-i2c"; 1450 reg = <0 0x00c84000 0 0x4000>; 1451 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1452 clock-names = "se"; 1453 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1454 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1455 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1456 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1457 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1458 #address-cells = <1>; 1459 #size-cells = <0>; 1460 status = "disabled"; 1461 }; 1462 1463 spi18: spi@c84000 { 1464 compatible = "qcom,geni-spi"; 1465 reg = <0 0x00c84000 0 0x4000>; 1466 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1467 clock-names = "se"; 1468 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1469 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1470 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1471 interconnect-names = "qup-core", "qup-config"; 1472 #address-cells = <1>; 1473 #size-cells = <0>; 1474 status = "disabled"; 1475 }; 1476 1477 uart18: serial@c84000 { 1478 compatible = "qcom,geni-uart"; 1479 reg = <0 0x00c84000 0 0x4000>; 1480 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1481 clock-names = "se"; 1482 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1483 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1484 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1485 interconnect-names = "qup-core", "qup-config"; 1486 status = "disabled"; 1487 }; 1488 1489 i2c19: i2c@c88000 { 1490 compatible = "qcom,geni-i2c"; 1491 reg = <0 0x00c88000 0 0x4000>; 1492 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1493 clock-names = "se"; 1494 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1495 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1496 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1497 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1498 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1499 #address-cells = <1>; 1500 #size-cells = <0>; 1501 status = "disabled"; 1502 }; 1503 1504 spi19: spi@c88000 { 1505 compatible = "qcom,geni-spi"; 1506 reg = <0 0x00c88000 0 0x4000>; 1507 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1508 clock-names = "se"; 1509 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1510 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1511 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1512 interconnect-names = "qup-core", "qup-config"; 1513 #address-cells = <1>; 1514 #size-cells = <0>; 1515 status = "disabled"; 1516 }; 1517 1518 uart19: serial@c88000 { 1519 compatible = "qcom,geni-uart"; 1520 reg = <0 0x00c88000 0 0x4000>; 1521 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1522 clock-names = "se"; 1523 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1524 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1525 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1526 interconnect-names = "qup-core", "qup-config"; 1527 status = "disabled"; 1528 }; 1529 1530 i2c13: i2c@c8c000 { 1531 compatible = "qcom,geni-i2c"; 1532 reg = <0 0x00c8c000 0 0x4000>; 1533 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1534 clock-names = "se"; 1535 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1536 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1537 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1538 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1539 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1540 #address-cells = <1>; 1541 #size-cells = <0>; 1542 status = "disabled"; 1543 }; 1544 1545 spi13: spi@c8c000 { 1546 compatible = "qcom,geni-spi"; 1547 reg = <0 0x00c8c000 0 0x4000>; 1548 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1549 clock-names = "se"; 1550 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1551 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1552 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1553 interconnect-names = "qup-core", "qup-config"; 1554 #address-cells = <1>; 1555 #size-cells = <0>; 1556 status = "disabled"; 1557 }; 1558 1559 uart13: serial@c8c000 { 1560 compatible = "qcom,geni-uart"; 1561 reg = <0 0x00c8c000 0 0x4000>; 1562 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1563 clock-names = "se"; 1564 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1565 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1566 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1567 interconnect-names = "qup-core", "qup-config"; 1568 status = "disabled"; 1569 }; 1570 1571 i2c14: i2c@c90000 { 1572 compatible = "qcom,geni-i2c"; 1573 reg = <0 0x00c90000 0 0x4000>; 1574 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1575 clock-names = "se"; 1576 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1577 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1578 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1579 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1580 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1581 #address-cells = <1>; 1582 #size-cells = <0>; 1583 status = "disabled"; 1584 }; 1585 1586 spi14: spi@c90000 { 1587 compatible = "qcom,geni-spi"; 1588 reg = <0 0x00c90000 0 0x4000>; 1589 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1590 clock-names = "se"; 1591 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1592 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1593 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1594 interconnect-names = "qup-core", "qup-config"; 1595 #address-cells = <1>; 1596 #size-cells = <0>; 1597 status = "disabled"; 1598 }; 1599 1600 uart14: serial@c90000 { 1601 compatible = "qcom,geni-uart"; 1602 reg = <0 0x00c90000 0 0x4000>; 1603 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1604 clock-names = "se"; 1605 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1606 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1607 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1608 interconnect-names = "qup-core", "qup-config"; 1609 status = "disabled"; 1610 }; 1611 1612 i2c15: i2c@c94000 { 1613 compatible = "qcom,geni-i2c"; 1614 reg = <0 0x00c94000 0 0x4000>; 1615 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1616 clock-names = "se"; 1617 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1618 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1619 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1620 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1621 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1622 #address-cells = <1>; 1623 #size-cells = <0>; 1624 status = "disabled"; 1625 }; 1626 1627 spi15: spi@c94000 { 1628 compatible = "qcom,geni-spi"; 1629 reg = <0 0x00c94000 0 0x4000>; 1630 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1631 clock-names = "se"; 1632 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1633 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1634 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1635 interconnect-names = "qup-core", "qup-config"; 1636 #address-cells = <1>; 1637 #size-cells = <0>; 1638 status = "disabled"; 1639 }; 1640 1641 uart15: serial@c94000 { 1642 compatible = "qcom,geni-uart"; 1643 reg = <0 0x00c94000 0 0x4000>; 1644 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1645 clock-names = "se"; 1646 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1647 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1648 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1649 interconnect-names = "qup-core", "qup-config"; 1650 status = "disabled"; 1651 }; 1652 }; 1653 1654 config_noc: interconnect@1500000 { 1655 compatible = "qcom,sc8180x-config-noc"; 1656 reg = <0 0x01500000 0 0x7400>; 1657 #interconnect-cells = <2>; 1658 qcom,bcm-voters = <&apps_bcm_voter>; 1659 }; 1660 1661 system_noc: interconnect@1620000 { 1662 compatible = "qcom,sc8180x-system-noc"; 1663 reg = <0 0x01620000 0 0x19400>; 1664 #interconnect-cells = <2>; 1665 qcom,bcm-voters = <&apps_bcm_voter>; 1666 }; 1667 1668 aggre1_noc: interconnect@16e0000 { 1669 compatible = "qcom,sc8180x-aggre1-noc"; 1670 reg = <0 0x016e0000 0 0xd080>; 1671 #interconnect-cells = <2>; 1672 qcom,bcm-voters = <&apps_bcm_voter>; 1673 }; 1674 1675 aggre2_noc: interconnect@1700000 { 1676 compatible = "qcom,sc8180x-aggre2-noc"; 1677 reg = <0 0x01700000 0 0x20000>; 1678 #interconnect-cells = <2>; 1679 qcom,bcm-voters = <&apps_bcm_voter>; 1680 }; 1681 1682 compute_noc: interconnect@1720000 { 1683 compatible = "qcom,sc8180x-compute-noc"; 1684 reg = <0 0x01720000 0 0x7000>; 1685 #interconnect-cells = <2>; 1686 qcom,bcm-voters = <&apps_bcm_voter>; 1687 }; 1688 1689 mmss_noc: interconnect@1740000 { 1690 compatible = "qcom,sc8180x-mmss-noc"; 1691 reg = <0 0x01740000 0 0x1c100>; 1692 #interconnect-cells = <2>; 1693 qcom,bcm-voters = <&apps_bcm_voter>; 1694 }; 1695 1696 pcie0: pci@1c00000 { 1697 compatible = "qcom,pcie-sc8180x"; 1698 reg = <0 0x01c00000 0 0x3000>, 1699 <0 0x60000000 0 0xf1d>, 1700 <0 0x60000f20 0 0xa8>, 1701 <0 0x60001000 0 0x1000>, 1702 <0 0x60100000 0 0x100000>; 1703 reg-names = "parf", 1704 "dbi", 1705 "elbi", 1706 "atu", 1707 "config"; 1708 device_type = "pci"; 1709 linux,pci-domain = <0>; 1710 bus-range = <0x00 0xff>; 1711 num-lanes = <2>; 1712 1713 #address-cells = <3>; 1714 #size-cells = <2>; 1715 1716 ranges = <0x01000000 0x0 0x60200000 0x0 0x60200000 0x0 0x100000>, 1717 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; 1718 1719 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 1720 interrupt-names = "msi"; 1721 #interrupt-cells = <1>; 1722 interrupt-map-mask = <0 0 0 0x7>; 1723 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1724 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1725 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1726 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1727 1728 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1729 <&gcc GCC_PCIE_0_AUX_CLK>, 1730 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1731 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1732 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1733 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1734 <&gcc GCC_PCIE_0_CLKREF_CLK>, 1735 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; 1736 clock-names = "pipe", 1737 "aux", 1738 "cfg", 1739 "bus_master", 1740 "bus_slave", 1741 "slave_q2a", 1742 "ref", 1743 "tbu"; 1744 1745 assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>; 1746 assigned-clock-rates = <19200000>; 1747 1748 iommus = <&apps_smmu 0x1d80 0x7f>; 1749 iommu-map = <0x0 &apps_smmu 0x1d80 0x1>, 1750 <0x100 &apps_smmu 0x1d81 0x1>; 1751 1752 resets = <&gcc GCC_PCIE_0_BCR>; 1753 reset-names = "pci"; 1754 1755 power-domains = <&gcc PCIE_0_GDSC>; 1756 1757 interconnects = <&aggre2_noc MASTER_PCIE 0 &mc_virt SLAVE_EBI_CH0 0>, 1758 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>; 1759 interconnect-names = "pcie-mem", "cpu-pcie"; 1760 1761 phys = <&pcie0_phy>; 1762 phy-names = "pciephy"; 1763 dma-coherent; 1764 1765 status = "disabled"; 1766 }; 1767 1768 pcie0_phy: phy@1c06000 { 1769 compatible = "qcom,sc8180x-qmp-pcie-phy"; 1770 reg = <0 0x01c06000 0 0x1000>; 1771 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1772 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1773 <&gcc GCC_PCIE_0_CLKREF_CLK>, 1774 <&gcc GCC_PCIE0_PHY_REFGEN_CLK>, 1775 <&gcc GCC_PCIE_0_PIPE_CLK>; 1776 clock-names = "aux", 1777 "cfg_ahb", 1778 "ref", 1779 "refgen", 1780 "pipe"; 1781 #clock-cells = <0>; 1782 clock-output-names = "pcie_0_pipe_clk"; 1783 #phy-cells = <0>; 1784 1785 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1786 reset-names = "phy"; 1787 1788 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; 1789 assigned-clock-rates = <100000000>; 1790 1791 status = "disabled"; 1792 }; 1793 1794 pcie3: pci@1c08000 { 1795 compatible = "qcom,pcie-sc8180x"; 1796 reg = <0 0x01c08000 0 0x3000>, 1797 <0 0x40000000 0 0xf1d>, 1798 <0 0x40000f20 0 0xa8>, 1799 <0 0x40001000 0 0x1000>, 1800 <0 0x40100000 0 0x100000>; 1801 reg-names = "parf", 1802 "dbi", 1803 "elbi", 1804 "atu", 1805 "config"; 1806 device_type = "pci"; 1807 linux,pci-domain = <3>; 1808 bus-range = <0x00 0xff>; 1809 num-lanes = <2>; 1810 1811 #address-cells = <3>; 1812 #size-cells = <2>; 1813 1814 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, 1815 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1816 1817 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 1818 interrupt-names = "msi"; 1819 #interrupt-cells = <1>; 1820 interrupt-map-mask = <0 0 0 0x7>; 1821 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1822 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1823 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1824 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1825 1826 clocks = <&gcc GCC_PCIE_3_PIPE_CLK>, 1827 <&gcc GCC_PCIE_3_AUX_CLK>, 1828 <&gcc GCC_PCIE_3_CFG_AHB_CLK>, 1829 <&gcc GCC_PCIE_3_MSTR_AXI_CLK>, 1830 <&gcc GCC_PCIE_3_SLV_AXI_CLK>, 1831 <&gcc GCC_PCIE_3_SLV_Q2A_AXI_CLK>, 1832 <&gcc GCC_PCIE_3_CLKREF_CLK>, 1833 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; 1834 clock-names = "pipe", 1835 "aux", 1836 "cfg", 1837 "bus_master", 1838 "bus_slave", 1839 "slave_q2a", 1840 "ref", 1841 "tbu"; 1842 1843 assigned-clocks = <&gcc GCC_PCIE_3_AUX_CLK>; 1844 assigned-clock-rates = <19200000>; 1845 1846 iommus = <&apps_smmu 0x1e00 0x7f>; 1847 iommu-map = <0x0 &apps_smmu 0x1e00 0x1>, 1848 <0x100 &apps_smmu 0x1e01 0x1>; 1849 1850 resets = <&gcc GCC_PCIE_3_BCR>; 1851 reset-names = "pci"; 1852 1853 power-domains = <&gcc PCIE_3_GDSC>; 1854 1855 interconnects = <&aggre2_noc MASTER_PCIE_3 0 &mc_virt SLAVE_EBI_CH0 0>, 1856 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>; 1857 interconnect-names = "pcie-mem", "cpu-pcie"; 1858 1859 phys = <&pcie3_phy>; 1860 phy-names = "pciephy"; 1861 dma-coherent; 1862 1863 status = "disabled"; 1864 }; 1865 1866 pcie3_phy: phy@1c0c000 { 1867 compatible = "qcom,sc8180x-qmp-pcie-phy"; 1868 reg = <0 0x01c0c000 0 0x1000>; 1869 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1870 <&gcc GCC_PCIE_3_CFG_AHB_CLK>, 1871 <&gcc GCC_PCIE_3_CLKREF_CLK>, 1872 <&gcc GCC_PCIE3_PHY_REFGEN_CLK>, 1873 <&gcc GCC_PCIE_3_PIPE_CLK>; 1874 clock-names = "aux", 1875 "cfg_ahb", 1876 "ref", 1877 "refgen", 1878 "pipe"; 1879 #clock-cells = <0>; 1880 clock-output-names = "pcie_3_pipe_clk"; 1881 1882 #phy-cells = <0>; 1883 1884 resets = <&gcc GCC_PCIE_3_PHY_BCR>; 1885 reset-names = "phy"; 1886 1887 assigned-clocks = <&gcc GCC_PCIE3_PHY_REFGEN_CLK>; 1888 assigned-clock-rates = <100000000>; 1889 1890 status = "disabled"; 1891 }; 1892 1893 pcie1: pci@1c10000 { 1894 compatible = "qcom,pcie-sc8180x"; 1895 reg = <0 0x01c10000 0 0x3000>, 1896 <0 0x68000000 0 0xf1d>, 1897 <0 0x68000f20 0 0xa8>, 1898 <0 0x68001000 0 0x1000>, 1899 <0 0x68100000 0 0x100000>; 1900 reg-names = "parf", 1901 "dbi", 1902 "elbi", 1903 "atu", 1904 "config"; 1905 device_type = "pci"; 1906 linux,pci-domain = <1>; 1907 bus-range = <0x00 0xff>; 1908 num-lanes = <2>; 1909 1910 #address-cells = <3>; 1911 #size-cells = <2>; 1912 1913 ranges = <0x01000000 0x0 0x68200000 0x0 0x68200000 0x0 0x100000>, 1914 <0x02000000 0x0 0x68300000 0x0 0x68300000 0x0 0x3d00000>; 1915 1916 interrupts = <GIC_SPI 755 IRQ_TYPE_LEVEL_HIGH>; 1917 interrupt-names = "msi"; 1918 #interrupt-cells = <1>; 1919 interrupt-map-mask = <0 0 0 0x7>; 1920 interrupt-map = <0 0 0 1 &intc 0 747 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1921 <0 0 0 2 &intc 0 746 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1922 <0 0 0 3 &intc 0 745 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1923 <0 0 0 4 &intc 0 744 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1924 1925 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1926 <&gcc GCC_PCIE_1_AUX_CLK>, 1927 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1928 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1929 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1930 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1931 <&gcc GCC_PCIE_1_CLKREF_CLK>, 1932 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; 1933 clock-names = "pipe", 1934 "aux", 1935 "cfg", 1936 "bus_master", 1937 "bus_slave", 1938 "slave_q2a", 1939 "ref", 1940 "tbu"; 1941 1942 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 1943 assigned-clock-rates = <19200000>; 1944 1945 iommus = <&apps_smmu 0x1c80 0x7f>; 1946 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 1947 <0x100 &apps_smmu 0x1c81 0x1>; 1948 1949 resets = <&gcc GCC_PCIE_1_BCR>; 1950 reset-names = "pci"; 1951 1952 power-domains = <&gcc PCIE_1_GDSC>; 1953 1954 interconnects = <&aggre2_noc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI_CH0 0>, 1955 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>; 1956 interconnect-names = "pcie-mem", "cpu-pcie"; 1957 1958 phys = <&pcie1_phy>; 1959 phy-names = "pciephy"; 1960 dma-coherent; 1961 1962 status = "disabled"; 1963 }; 1964 1965 pcie1_phy: phy@1c16000 { 1966 compatible = "qcom,sc8180x-qmp-pcie-phy"; 1967 reg = <0 0x01c16000 0 0x1000>; 1968 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1969 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1970 <&gcc GCC_PCIE_1_CLKREF_CLK>, 1971 <&gcc GCC_PCIE1_PHY_REFGEN_CLK>, 1972 <&gcc GCC_PCIE_1_PIPE_CLK>; 1973 clock-names = "aux", 1974 "cfg_ahb", 1975 "ref", 1976 "refgen", 1977 "pipe"; 1978 #clock-cells = <0>; 1979 clock-output-names = "pcie_1_pipe_clk"; 1980 1981 #phy-cells = <0>; 1982 1983 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 1984 reset-names = "phy"; 1985 1986 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; 1987 assigned-clock-rates = <100000000>; 1988 1989 status = "disabled"; 1990 }; 1991 1992 pcie2: pci@1c18000 { 1993 compatible = "qcom,pcie-sc8180x"; 1994 reg = <0 0x01c18000 0 0x3000>, 1995 <0 0x70000000 0 0xf1d>, 1996 <0 0x70000f20 0 0xa8>, 1997 <0 0x70001000 0 0x1000>, 1998 <0 0x70100000 0 0x100000>; 1999 reg-names = "parf", 2000 "dbi", 2001 "elbi", 2002 "atu", 2003 "config"; 2004 device_type = "pci"; 2005 linux,pci-domain = <2>; 2006 bus-range = <0x00 0xff>; 2007 num-lanes = <4>; 2008 2009 #address-cells = <3>; 2010 #size-cells = <2>; 2011 2012 ranges = <0x01000000 0x0 0x70200000 0x0 0x70200000 0x0 0x100000>, 2013 <0x02000000 0x0 0x70300000 0x0 0x70300000 0x0 0x3d00000>; 2014 2015 interrupts = <GIC_SPI 671 IRQ_TYPE_LEVEL_HIGH>; 2016 interrupt-names = "msi"; 2017 #interrupt-cells = <1>; 2018 interrupt-map-mask = <0 0 0 0x7>; 2019 interrupt-map = <0 0 0 1 &intc 0 663 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 2020 <0 0 0 2 &intc 0 662 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 2021 <0 0 0 3 &intc 0 661 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 2022 <0 0 0 4 &intc 0 660 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 2023 2024 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>, 2025 <&gcc GCC_PCIE_2_AUX_CLK>, 2026 <&gcc GCC_PCIE_2_CFG_AHB_CLK>, 2027 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>, 2028 <&gcc GCC_PCIE_2_SLV_AXI_CLK>, 2029 <&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>, 2030 <&gcc GCC_PCIE_2_CLKREF_CLK>, 2031 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; 2032 clock-names = "pipe", 2033 "aux", 2034 "cfg", 2035 "bus_master", 2036 "bus_slave", 2037 "slave_q2a", 2038 "ref", 2039 "tbu"; 2040 2041 assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>; 2042 assigned-clock-rates = <19200000>; 2043 2044 iommus = <&apps_smmu 0x1d00 0x7f>; 2045 iommu-map = <0x0 &apps_smmu 0x1d00 0x1>, 2046 <0x100 &apps_smmu 0x1d01 0x1>; 2047 2048 resets = <&gcc GCC_PCIE_2_BCR>; 2049 reset-names = "pci"; 2050 2051 power-domains = <&gcc PCIE_2_GDSC>; 2052 2053 interconnects = <&aggre2_noc MASTER_PCIE_2 0 &mc_virt SLAVE_EBI_CH0 0>, 2054 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>; 2055 interconnect-names = "pcie-mem", "cpu-pcie"; 2056 2057 phys = <&pcie2_phy>; 2058 phy-names = "pciephy"; 2059 dma-coherent; 2060 2061 status = "disabled"; 2062 }; 2063 2064 pcie2_phy: phy@1c1c000 { 2065 compatible = "qcom,sc8180x-qmp-pcie-phy"; 2066 reg = <0 0x01c1c000 0 0x1000>; 2067 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 2068 <&gcc GCC_PCIE_2_CFG_AHB_CLK>, 2069 <&gcc GCC_PCIE_2_CLKREF_CLK>, 2070 <&gcc GCC_PCIE2_PHY_REFGEN_CLK>, 2071 <&gcc GCC_PCIE_2_PIPE_CLK>; 2072 clock-names = "aux", 2073 "cfg_ahb", 2074 "ref", 2075 "refgen", 2076 "pipe"; 2077 #clock-cells = <0>; 2078 clock-output-names = "pcie_2_pipe_clk"; 2079 2080 #phy-cells = <0>; 2081 2082 resets = <&gcc GCC_PCIE_2_PHY_BCR>; 2083 reset-names = "phy"; 2084 2085 assigned-clocks = <&gcc GCC_PCIE2_PHY_REFGEN_CLK>; 2086 assigned-clock-rates = <100000000>; 2087 2088 status = "disabled"; 2089 }; 2090 2091 ufs_mem_hc: ufshc@1d84000 { 2092 compatible = "qcom,sc8180x-ufshc", "qcom,ufshc", 2093 "jedec,ufs-2.0"; 2094 reg = <0 0x01d84000 0 0x2500>; 2095 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2096 phys = <&ufs_mem_phy_lanes>; 2097 phy-names = "ufsphy"; 2098 lanes-per-direction = <2>; 2099 #reset-cells = <1>; 2100 resets = <&gcc GCC_UFS_PHY_BCR>; 2101 reset-names = "rst"; 2102 2103 iommus = <&apps_smmu 0x300 0>; 2104 2105 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 2106 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2107 <&gcc GCC_UFS_PHY_AHB_CLK>, 2108 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2109 <&rpmhcc RPMH_CXO_CLK>, 2110 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2111 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2112 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 2113 clock-names = "core_clk", 2114 "bus_aggr_clk", 2115 "iface_clk", 2116 "core_clk_unipro", 2117 "ref_clk", 2118 "tx_lane0_sync_clk", 2119 "rx_lane0_sync_clk", 2120 "rx_lane1_sync_clk"; 2121 freq-table-hz = <37500000 300000000>, 2122 <0 0>, 2123 <0 0>, 2124 <37500000 300000000>, 2125 <0 0>, 2126 <0 0>, 2127 <0 0>, 2128 <0 0>; 2129 2130 status = "disabled"; 2131 }; 2132 2133 ufs_mem_phy: phy-wrapper@1d87000 { 2134 compatible = "qcom,sc8180x-qmp-ufs-phy"; 2135 reg = <0 0x01d87000 0 0x1c0>; 2136 #address-cells = <2>; 2137 #size-cells = <2>; 2138 ranges; 2139 clocks = <&rpmhcc RPMH_CXO_CLK>, 2140 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 2141 clock-names = "ref", 2142 "ref_aux"; 2143 2144 resets = <&ufs_mem_hc 0>; 2145 reset-names = "ufsphy"; 2146 status = "disabled"; 2147 2148 ufs_mem_phy_lanes: phy@1d87400 { 2149 reg = <0 0x01d87400 0 0x108>, 2150 <0 0x01d87600 0 0x1e0>, 2151 <0 0x01d87c00 0 0x1dc>, 2152 <0 0x01d87800 0 0x108>, 2153 <0 0x01d87a00 0 0x1e0>; 2154 #phy-cells = <0>; 2155 }; 2156 }; 2157 2158 ipa_virt: interconnect@1e00000 { 2159 compatible = "qcom,sc8180x-ipa-virt"; 2160 reg = <0 0x01e00000 0 0x1000>; 2161 #interconnect-cells = <2>; 2162 qcom,bcm-voters = <&apps_bcm_voter>; 2163 }; 2164 2165 tcsr_mutex: hwlock@1f40000 { 2166 compatible = "qcom,tcsr-mutex"; 2167 reg = <0x0 0x01f40000 0x0 0x40000>; 2168 #hwlock-cells = <1>; 2169 }; 2170 2171 gpu: gpu@2c00000 { 2172 compatible = "qcom,adreno-680.1", "qcom,adreno"; 2173 #stream-id-cells = <16>; 2174 2175 reg = <0 0x02c00000 0 0x40000>; 2176 reg-names = "kgsl_3d0_reg_memory"; 2177 2178 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2179 2180 iommus = <&adreno_smmu 0 0xc01>; 2181 2182 operating-points-v2 = <&gpu_opp_table>; 2183 2184 interconnects = <&gem_noc MASTER_GRAPHICS_3D 0 &mc_virt SLAVE_EBI_CH0 0>; 2185 interconnect-names = "gfx-mem"; 2186 2187 qcom,gmu = <&gmu>; 2188 status = "disabled"; 2189 2190 gpu_opp_table: opp-table { 2191 compatible = "operating-points-v2"; 2192 2193 opp-514000000 { 2194 opp-hz = /bits/ 64 <514000000>; 2195 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 2196 }; 2197 2198 opp-500000000 { 2199 opp-hz = /bits/ 64 <500000000>; 2200 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2201 }; 2202 2203 opp-461000000 { 2204 opp-hz = /bits/ 64 <461000000>; 2205 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2206 }; 2207 2208 opp-405000000 { 2209 opp-hz = /bits/ 64 <405000000>; 2210 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2211 }; 2212 2213 opp-315000000 { 2214 opp-hz = /bits/ 64 <315000000>; 2215 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2216 }; 2217 2218 opp-256000000 { 2219 opp-hz = /bits/ 64 <256000000>; 2220 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2221 }; 2222 2223 opp-177000000 { 2224 opp-hz = /bits/ 64 <177000000>; 2225 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2226 }; 2227 }; 2228 }; 2229 2230 gmu: gmu@2c6a000 { 2231 compatible = "qcom,adreno-gmu-680.1", "qcom,adreno-gmu"; 2232 2233 reg = <0 0x02c6a000 0 0x30000>, 2234 <0 0x0b290000 0 0x10000>, 2235 <0 0x0b490000 0 0x10000>; 2236 reg-names = "gmu", 2237 "gmu_pdc", 2238 "gmu_pdc_seq"; 2239 2240 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2241 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2242 interrupt-names = "hfi", "gmu"; 2243 2244 clocks = <&gpucc GPU_CC_AHB_CLK>, 2245 <&gpucc GPU_CC_CX_GMU_CLK>, 2246 <&gpucc GPU_CC_CXO_CLK>, 2247 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2248 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 2249 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc"; 2250 2251 power-domains = <&gpucc GPU_CX_GDSC>, 2252 <&gpucc GPU_GX_GDSC>; 2253 power-domain-names = "cx", "gx"; 2254 2255 iommus = <&adreno_smmu 5 0xc00>; 2256 2257 operating-points-v2 = <&gmu_opp_table>; 2258 2259 gmu_opp_table: opp-table { 2260 compatible = "operating-points-v2"; 2261 2262 opp-200000000 { 2263 opp-hz = /bits/ 64 <200000000>; 2264 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2265 }; 2266 2267 opp-500000000 { 2268 opp-hz = /bits/ 64 <500000000>; 2269 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2270 }; 2271 }; 2272 }; 2273 2274 gpucc: clock-controller@2c90000 { 2275 compatible = "qcom,sc8180x-gpucc"; 2276 reg = <0 0x02c90000 0 0x9000>; 2277 clocks = <&rpmhcc RPMH_CXO_CLK>, 2278 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2279 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2280 clock-names = "bi_tcxo", 2281 "gcc_gpu_gpll0_clk_src", 2282 "gcc_gpu_gpll0_div_clk_src"; 2283 #clock-cells = <1>; 2284 #reset-cells = <1>; 2285 #power-domain-cells = <1>; 2286 }; 2287 2288 adreno_smmu: iommu@2ca0000 { 2289 compatible = "qcom,sc8180x-smmu-500", "qcom,adreno-smmu", 2290 "qcom,smmu-500", "arm,mmu-500"; 2291 reg = <0 0x02ca0000 0 0x10000>; 2292 #iommu-cells = <2>; 2293 #global-interrupts = <1>; 2294 interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>, 2295 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2296 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2297 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2298 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2299 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 2300 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 2301 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>, 2302 <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>; 2303 clocks = <&gpucc GPU_CC_AHB_CLK>, 2304 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2305 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 2306 clock-names = "ahb", "bus", "iface"; 2307 2308 power-domains = <&gpucc GPU_CX_GDSC>; 2309 }; 2310 2311 tlmm: pinctrl@3100000 { 2312 compatible = "qcom,sc8180x-tlmm"; 2313 reg = <0 0x03100000 0 0x300000>, 2314 <0 0x03500000 0 0x700000>, 2315 <0 0x03d00000 0 0x300000>; 2316 reg-names = "west", "east", "south"; 2317 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 2318 gpio-controller; 2319 #gpio-cells = <2>; 2320 interrupt-controller; 2321 #interrupt-cells = <2>; 2322 gpio-ranges = <&tlmm 0 0 191>; 2323 wakeup-parent = <&pdc>; 2324 }; 2325 2326 remoteproc_mpss: remoteproc@4080000 { 2327 compatible = "qcom,sc8180x-mpss-pas"; 2328 reg = <0x0 0x04080000 0x0 0x4040>; 2329 2330 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, 2331 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2332 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2333 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2334 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2335 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2336 interrupt-names = "wdog", "fatal", "ready", "handover", 2337 "stop-ack", "shutdown-ack"; 2338 2339 clocks = <&rpmhcc RPMH_CXO_CLK>; 2340 clock-names = "xo"; 2341 2342 power-domains = <&rpmhpd SC8180X_CX>, 2343 <&rpmhpd SC8180X_MSS>; 2344 power-domain-names = "cx", "mss"; 2345 2346 qcom,qmp = <&aoss_qmp>; 2347 2348 qcom,smem-states = <&modem_smp2p_out 0>; 2349 qcom,smem-state-names = "stop"; 2350 2351 glink-edge { 2352 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 2353 label = "modem"; 2354 qcom,remote-pid = <1>; 2355 mboxes = <&apss_shared 12>; 2356 }; 2357 }; 2358 2359 remoteproc_cdsp: remoteproc@8300000 { 2360 compatible = "qcom,sc8180x-cdsp-pas"; 2361 reg = <0x0 0x08300000 0x0 0x4040>; 2362 2363 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 2364 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2365 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2366 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2367 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2368 interrupt-names = "wdog", "fatal", "ready", 2369 "handover", "stop-ack"; 2370 2371 clocks = <&rpmhcc RPMH_CXO_CLK>; 2372 clock-names = "xo"; 2373 2374 power-domains = <&rpmhpd SC8180X_CX>; 2375 power-domain-names = "cx"; 2376 2377 qcom,qmp = <&aoss_qmp>; 2378 2379 qcom,smem-states = <&cdsp_smp2p_out 0>; 2380 qcom,smem-state-names = "stop"; 2381 2382 status = "disabled"; 2383 2384 glink-edge { 2385 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>; 2386 label = "cdsp"; 2387 qcom,remote-pid = <5>; 2388 mboxes = <&apss_shared 4>; 2389 }; 2390 }; 2391 2392 usb_prim_hsphy: phy@88e2000 { 2393 compatible = "qcom,sc8180x-usb-hs-phy", 2394 "qcom,usb-snps-hs-7nm-phy"; 2395 reg = <0 0x088e2000 0 0x400>; 2396 clocks = <&rpmhcc RPMH_CXO_CLK>; 2397 clock-names = "ref"; 2398 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2399 2400 #phy-cells = <0>; 2401 2402 status = "disabled"; 2403 }; 2404 2405 usb_sec_hsphy: phy@88e3000 { 2406 compatible = "qcom,sc8180x-usb-hs-phy", 2407 "qcom,usb-snps-hs-7nm-phy"; 2408 reg = <0 0x088e3000 0 0x400>; 2409 clocks = <&rpmhcc RPMH_CXO_CLK>; 2410 clock-names = "ref"; 2411 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 2412 2413 #phy-cells = <0>; 2414 2415 status = "disabled"; 2416 }; 2417 2418 usb_prim_qmpphy: phy@88e9000 { 2419 compatible = "qcom,sc8180x-qmp-usb3-dp-phy"; 2420 reg = <0 0x088e9000 0 0x18c>, 2421 <0 0x088e8000 0 0x38>, 2422 <0 0x088ea000 0 0x40>; 2423 reg-names = "reg-base", "dp_com"; 2424 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2425 <&rpmhcc RPMH_CXO_CLK>, 2426 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 2427 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 2428 clock-names = "aux", 2429 "ref_clk_src", 2430 "ref", 2431 "com_aux"; 2432 resets = <&gcc GCC_USB3_DP_PHY_PRIM_SP0_BCR>, 2433 <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>; 2434 reset-names = "phy", "common"; 2435 2436 #clock-cells = <1>; 2437 #address-cells = <2>; 2438 #size-cells = <2>; 2439 ranges; 2440 2441 status = "disabled"; 2442 2443 ports { 2444 #address-cells = <1>; 2445 #size-cells = <0>; 2446 2447 port@0 { 2448 reg = <0>; 2449 2450 usb_prim_qmpphy_out: endpoint {}; 2451 }; 2452 2453 port@2 { 2454 reg = <2>; 2455 2456 usb_prim_qmpphy_dp_in: endpoint {}; 2457 }; 2458 }; 2459 2460 usb_prim_ssphy: usb3-phy@88e9200 { 2461 reg = <0 0x088e9200 0 0x200>, 2462 <0 0x088e9400 0 0x200>, 2463 <0 0x088e9c00 0 0x218>, 2464 <0 0x088e9600 0 0x200>, 2465 <0 0x088e9800 0 0x200>, 2466 <0 0x088e9a00 0 0x100>; 2467 #phy-cells = <0>; 2468 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2469 clock-names = "pipe0"; 2470 clock-output-names = "usb3_prim_phy_pipe_clk_src"; 2471 }; 2472 2473 usb_prim_dpphy: dp-phy@88ea200 { 2474 reg = <0 0x088ea200 0 0x200>, 2475 <0 0x088ea400 0 0x200>, 2476 <0 0x088eaa00 0 0x200>, 2477 <0 0x088ea600 0 0x200>, 2478 <0 0x088ea800 0 0x200>; 2479 #clock-cells = <1>; 2480 #phy-cells = <0>; 2481 }; 2482 }; 2483 2484 usb_sec_qmpphy: phy@88ee000 { 2485 compatible = "qcom,sc8180x-qmp-usb3-dp-phy"; 2486 reg = <0 0x088ee000 0 0x18c>, 2487 <0 0x088ed000 0 0x10>, 2488 <0 0x088ef000 0 0x40>; 2489 reg-names = "reg-base", "dp_com"; 2490 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 2491 <&rpmhcc RPMH_CXO_CLK>, 2492 <&gcc GCC_USB3_SEC_CLKREF_CLK>, 2493 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; 2494 clock-names = "aux", 2495 "ref_clk_src", 2496 "ref", 2497 "com_aux"; 2498 resets = <&gcc GCC_USB3_DP_PHY_SEC_BCR>, 2499 <&gcc GCC_USB3_PHY_SEC_BCR>; 2500 reset-names = "phy", "common"; 2501 2502 #clock-cells = <1>; 2503 #address-cells = <2>; 2504 #size-cells = <2>; 2505 ranges; 2506 2507 status = "disabled"; 2508 2509 ports { 2510 #address-cells = <1>; 2511 #size-cells = <0>; 2512 2513 port@0 { 2514 reg = <0>; 2515 2516 usb_sec_qmpphy_out: endpoint {}; 2517 }; 2518 2519 port@2 { 2520 reg = <2>; 2521 2522 usb_sec_qmpphy_dp_in: endpoint {}; 2523 }; 2524 }; 2525 2526 usb_sec_ssphy: usb3-phy@88e9200 { 2527 reg = <0 0x088ee200 0 0x200>, 2528 <0 0x088ee400 0 0x200>, 2529 <0 0x088eec00 0 0x218>, 2530 <0 0x088ee600 0 0x200>, 2531 <0 0x088ee800 0 0x200>, 2532 <0 0x088eea00 0 0x100>; 2533 #phy-cells = <0>; 2534 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 2535 clock-names = "pipe0"; 2536 clock-output-names = "usb3_sec_phy_pipe_clk_src"; 2537 }; 2538 2539 usb_sec_dpphy: dp-phy@88ef200 { 2540 reg = <0 0x088ef200 0 0x200>, 2541 <0 0x088ef400 0 0x200>, 2542 <0 0x088efa00 0 0x200>, 2543 <0 0x088ef600 0 0x200>, 2544 <0 0x088ef800 0 0x200>; 2545 #clock-cells = <1>; 2546 #phy-cells = <0>; 2547 clock-output-names = "qmp_dptx1_phy_pll_link_clk", 2548 "qmp_dptx1_phy_pll_vco_div_clk"; 2549 }; 2550 }; 2551 2552 system-cache-controller@9200000 { 2553 compatible = "qcom,sc8180x-llcc"; 2554 reg = <0 0x09200000 0 0x50000>, <0 0x09280000 0 0x50000>, 2555 <0 0x09300000 0 0x50000>, <0 0x09380000 0 0x50000>, 2556 <0 0x09600000 0 0x50000>; 2557 reg-names = "llcc0_base", "llcc1_base", "llcc2_base", 2558 "llcc3_base", "llcc_broadcast_base"; 2559 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 2560 }; 2561 2562 gem_noc: interconnect@9680000 { 2563 compatible = "qcom,sc8180x-gem-noc"; 2564 reg = <0 0x09680000 0 0x58200>; 2565 #interconnect-cells = <2>; 2566 qcom,bcm-voters = <&apps_bcm_voter>; 2567 }; 2568 2569 usb_prim: usb@a6f8800 { 2570 compatible = "qcom,sc8180x-dwc3", "qcom,dwc3"; 2571 reg = <0 0x0a6f8800 0 0x400>; 2572 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 2573 <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, 2574 <&pdc 8 IRQ_TYPE_EDGE_BOTH>, 2575 <&pdc 9 IRQ_TYPE_EDGE_BOTH>; 2576 interrupt-names = "hs_phy_irq", 2577 "ss_phy_irq", 2578 "dm_hs_phy_irq", 2579 "dp_hs_phy_irq"; 2580 2581 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 2582 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 2583 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2584 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2585 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 2586 <&gcc GCC_USB3_SEC_CLKREF_CLK>; 2587 clock-names = "cfg_noc", 2588 "core", 2589 "iface", 2590 "mock_utmi", 2591 "sleep", 2592 "xo"; 2593 resets = <&gcc GCC_USB30_PRIM_BCR>; 2594 power-domains = <&gcc USB30_PRIM_GDSC>; 2595 2596 interconnects = <&aggre1_noc MASTER_USB3 0 &mc_virt SLAVE_EBI_CH0 0>, 2597 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>; 2598 interconnect-names = "usb-ddr", "apps-usb"; 2599 2600 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2601 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 2602 assigned-clock-rates = <19200000>, <200000000>; 2603 2604 #address-cells = <2>; 2605 #size-cells = <2>; 2606 ranges; 2607 dma-ranges; 2608 2609 status = "disabled"; 2610 2611 usb_prim_dwc3: usb@a600000 { 2612 compatible = "snps,dwc3"; 2613 reg = <0 0x0a600000 0 0xcd00>; 2614 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 2615 iommus = <&apps_smmu 0x140 0>; 2616 snps,dis_u2_susphy_quirk; 2617 snps,dis_enblslpm_quirk; 2618 phys = <&usb_prim_hsphy>, <&usb_prim_ssphy>; 2619 phy-names = "usb2-phy", "usb3-phy"; 2620 2621 port { 2622 usb_prim_role_switch: endpoint { 2623 }; 2624 }; 2625 }; 2626 }; 2627 2628 usb_sec: usb@a8f8800 { 2629 compatible = "qcom,sc8180x-dwc3", "qcom,dwc3"; 2630 reg = <0 0x0a8f8800 0 0x400>; 2631 2632 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 2633 <&gcc GCC_USB30_SEC_MASTER_CLK>, 2634 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 2635 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2636 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 2637 <&gcc GCC_USB3_SEC_CLKREF_CLK>; 2638 clock-names = "cfg_noc", 2639 "core", 2640 "iface", 2641 "mock_utmi", 2642 "sleep", 2643 "xo"; 2644 resets = <&gcc GCC_USB30_SEC_BCR>; 2645 power-domains = <&gcc USB30_SEC_GDSC>; 2646 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 2647 <&pdc 40 IRQ_TYPE_LEVEL_HIGH>, 2648 <&pdc 10 IRQ_TYPE_EDGE_BOTH>, 2649 <&pdc 11 IRQ_TYPE_EDGE_BOTH>; 2650 interrupt-names = "hs_phy_irq", "ss_phy_irq", 2651 "dm_hs_phy_irq", "dp_hs_phy_irq"; 2652 2653 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2654 <&gcc GCC_USB30_SEC_MASTER_CLK>; 2655 assigned-clock-rates = <19200000>, <200000000>; 2656 2657 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI_CH0 0>, 2658 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3_1 0>; 2659 interconnect-names = "usb-ddr", "apps-usb"; 2660 2661 #address-cells = <2>; 2662 #size-cells = <2>; 2663 ranges; 2664 dma-ranges; 2665 2666 status = "disabled"; 2667 2668 usb_sec_dwc3: usb@a800000 { 2669 compatible = "snps,dwc3"; 2670 reg = <0 0x0a800000 0 0xcd00>; 2671 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 2672 iommus = <&apps_smmu 0x160 0>; 2673 snps,dis_u2_susphy_quirk; 2674 snps,dis_enblslpm_quirk; 2675 phys = <&usb_sec_hsphy>, <&usb_sec_ssphy>; 2676 phy-names = "usb2-phy", "usb3-phy"; 2677 2678 port { 2679 usb_sec_role_switch: endpoint { 2680 }; 2681 }; 2682 }; 2683 }; 2684 2685 mdss: mdss@ae00000 { 2686 compatible = "qcom,sc8180x-mdss"; 2687 reg = <0 0x0ae00000 0 0x1000>; 2688 reg-names = "mdss"; 2689 2690 power-domains = <&dispcc MDSS_GDSC>; 2691 2692 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2693 <&gcc GCC_DISP_HF_AXI_CLK>, 2694 <&gcc GCC_DISP_SF_AXI_CLK>, 2695 <&dispcc DISP_CC_MDSS_MDP_CLK>; 2696 clock-names = "iface", 2697 "bus", 2698 "nrt_bus", 2699 "core"; 2700 2701 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 2702 2703 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2704 interrupt-controller; 2705 #interrupt-cells = <1>; 2706 2707 interconnects = <&mmss_noc MASTER_MDP_PORT0 0 &mc_virt SLAVE_EBI_CH0 0>, 2708 <&mmss_noc MASTER_MDP_PORT1 0 &mc_virt SLAVE_EBI_CH0 0>; 2709 interconnect-names = "mdp0-mem", "mdp1-mem"; 2710 2711 iommus = <&apps_smmu 0x800 0x420>; 2712 2713 #address-cells = <2>; 2714 #size-cells = <2>; 2715 ranges; 2716 2717 status = "disabled"; 2718 2719 mdss_mdp: mdp@ae01000 { 2720 compatible = "qcom,sc8180x-dpu"; 2721 reg = <0 0x0ae01000 0 0x8f000>, 2722 <0 0x0aeb0000 0 0x2008>; 2723 reg-names = "mdp", "vbif"; 2724 2725 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2726 <&gcc GCC_DISP_HF_AXI_CLK>, 2727 <&dispcc DISP_CC_MDSS_MDP_CLK>, 2728 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2729 clock-names = "iface", 2730 "bus", 2731 "core", 2732 "vsync"; 2733 2734 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2735 assigned-clock-rates = <19200000>; 2736 2737 operating-points-v2 = <&mdp_opp_table>; 2738 power-domains = <&rpmhpd SC8180X_MMCX>; 2739 2740 interrupt-parent = <&mdss>; 2741 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; 2742 2743 ports { 2744 #address-cells = <1>; 2745 #size-cells = <0>; 2746 2747 port@0 { 2748 reg = <0>; 2749 dpu_intf0_out: endpoint { 2750 remote-endpoint = <&dp0_in>; 2751 }; 2752 }; 2753 2754 port@1 { 2755 reg = <1>; 2756 dpu_intf1_out: endpoint { 2757 remote-endpoint = <&mdss_dsi0_in>; 2758 }; 2759 }; 2760 2761 port@2 { 2762 reg = <2>; 2763 dpu_intf2_out: endpoint { 2764 remote-endpoint = <&mdss_dsi1_in>; 2765 }; 2766 }; 2767 2768 port@4 { 2769 reg = <4>; 2770 dpu_intf4_out: endpoint { 2771 remote-endpoint = <&dp1_in>; 2772 }; 2773 }; 2774 2775 port@5 { 2776 reg = <5>; 2777 dpu_intf5_out: endpoint { 2778 remote-endpoint = <&edp_in>; 2779 }; 2780 }; 2781 }; 2782 2783 mdp_opp_table: opp-table { 2784 compatible = "operating-points-v2"; 2785 2786 opp-200000000 { 2787 opp-hz = /bits/ 64 <200000000>; 2788 required-opps = <&rpmhpd_opp_low_svs>; 2789 }; 2790 2791 opp-300000000 { 2792 opp-hz = /bits/ 64 <300000000>; 2793 required-opps = <&rpmhpd_opp_svs>; 2794 }; 2795 2796 opp-345000000 { 2797 opp-hz = /bits/ 64 <345000000>; 2798 required-opps = <&rpmhpd_opp_svs_l1>; 2799 }; 2800 2801 opp-460000000 { 2802 opp-hz = /bits/ 64 <460000000>; 2803 required-opps = <&rpmhpd_opp_nom>; 2804 }; 2805 }; 2806 }; 2807 2808 mdss_dsi0: dsi@ae94000 { 2809 compatible = "qcom,mdss-dsi-ctrl"; 2810 reg = <0 0x0ae94000 0 0x400>; 2811 reg-names = "dsi_ctrl"; 2812 2813 interrupt-parent = <&mdss>; 2814 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; 2815 2816 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 2817 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 2818 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 2819 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 2820 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2821 <&gcc GCC_DISP_HF_AXI_CLK>; 2822 clock-names = "byte", 2823 "byte_intf", 2824 "pixel", 2825 "core", 2826 "iface", 2827 "bus"; 2828 2829 operating-points-v2 = <&dsi_opp_table>; 2830 power-domains = <&rpmhpd SC8180X_MMCX>; 2831 2832 phys = <&mdss_dsi0_phy>; 2833 phy-names = "dsi"; 2834 2835 status = "disabled"; 2836 2837 ports { 2838 #address-cells = <1>; 2839 #size-cells = <0>; 2840 2841 port@0 { 2842 reg = <0>; 2843 mdss_dsi0_in: endpoint { 2844 remote-endpoint = <&dpu_intf1_out>; 2845 }; 2846 }; 2847 2848 port@1 { 2849 reg = <1>; 2850 mdss_dsi0_out: endpoint { 2851 }; 2852 }; 2853 }; 2854 2855 dsi_opp_table: opp-table { 2856 compatible = "operating-points-v2"; 2857 2858 opp-187500000 { 2859 opp-hz = /bits/ 64 <187500000>; 2860 required-opps = <&rpmhpd_opp_low_svs>; 2861 }; 2862 2863 opp-300000000 { 2864 opp-hz = /bits/ 64 <300000000>; 2865 required-opps = <&rpmhpd_opp_svs>; 2866 }; 2867 2868 opp-358000000 { 2869 opp-hz = /bits/ 64 <358000000>; 2870 required-opps = <&rpmhpd_opp_svs_l1>; 2871 }; 2872 }; 2873 }; 2874 2875 mdss_dsi0_phy: dsi-phy@ae94400 { 2876 compatible = "qcom,dsi-phy-7nm"; 2877 reg = <0 0x0ae94400 0 0x200>, 2878 <0 0x0ae94600 0 0x280>, 2879 <0 0x0ae94900 0 0x260>; 2880 reg-names = "dsi_phy", 2881 "dsi_phy_lane", 2882 "dsi_pll"; 2883 2884 #clock-cells = <1>; 2885 #phy-cells = <0>; 2886 2887 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2888 <&rpmhcc RPMH_CXO_CLK>; 2889 clock-names = "iface", "ref"; 2890 2891 status = "disabled"; 2892 }; 2893 2894 mdss_dsi1: dsi@ae96000 { 2895 compatible = "qcom,mdss-dsi-ctrl"; 2896 reg = <0 0x0ae96000 0 0x400>; 2897 reg-names = "dsi_ctrl"; 2898 2899 interrupt-parent = <&mdss>; 2900 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; 2901 2902 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 2903 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 2904 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 2905 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 2906 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2907 <&gcc GCC_DISP_HF_AXI_CLK>; 2908 clock-names = "byte", 2909 "byte_intf", 2910 "pixel", 2911 "core", 2912 "iface", 2913 "bus"; 2914 2915 operating-points-v2 = <&dsi_opp_table>; 2916 power-domains = <&rpmhpd SC8180X_MMCX>; 2917 2918 phys = <&mdss_dsi1_phy>; 2919 phy-names = "dsi"; 2920 2921 status = "disabled"; 2922 2923 ports { 2924 #address-cells = <1>; 2925 #size-cells = <0>; 2926 2927 port@0 { 2928 reg = <0>; 2929 mdss_dsi1_in: endpoint { 2930 remote-endpoint = <&dpu_intf2_out>; 2931 }; 2932 }; 2933 2934 port@1 { 2935 reg = <1>; 2936 mdss_dsi1_out: endpoint { 2937 }; 2938 }; 2939 }; 2940 }; 2941 2942 mdss_dsi1_phy: dsi-phy@ae96400 { 2943 compatible = "qcom,dsi-phy-7nm"; 2944 reg = <0 0x0ae96400 0 0x200>, 2945 <0 0x0ae96600 0 0x280>, 2946 <0 0x0ae96900 0 0x260>; 2947 reg-names = "dsi_phy", 2948 "dsi_phy_lane", 2949 "dsi_pll"; 2950 2951 #clock-cells = <1>; 2952 #phy-cells = <0>; 2953 2954 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2955 <&rpmhcc RPMH_CXO_CLK>; 2956 clock-names = "iface", "ref"; 2957 2958 status = "disabled"; 2959 }; 2960 2961 mdss_dp0: displayport-controller@ae90000 { 2962 compatible = "qcom,sc8180x-dp"; 2963 reg = <0 0xae90000 0 0x200>, 2964 <0 0xae90200 0 0x200>, 2965 <0 0xae90400 0 0x600>, 2966 <0 0xae90a00 0 0x400>; 2967 interrupt-parent = <&mdss>; 2968 interrupts = <12>; 2969 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2970 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 2971 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 2972 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 2973 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 2974 clock-names = "core_iface", 2975 "core_aux", 2976 "ctrl_link", 2977 "ctrl_link_iface", 2978 "stream_pixel"; 2979 2980 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 2981 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 2982 assigned-clock-parents = <&usb_prim_dpphy 0>, <&usb_prim_dpphy 1>; 2983 2984 phys = <&usb_prim_dpphy>; 2985 phy-names = "dp"; 2986 2987 #sound-dai-cells = <0>; 2988 2989 operating-points-v2 = <&dp0_opp_table>; 2990 power-domains = <&rpmhpd SC8180X_MMCX>; 2991 2992 status = "disabled"; 2993 2994 ports { 2995 #address-cells = <1>; 2996 #size-cells = <0>; 2997 2998 port@0 { 2999 reg = <0>; 3000 dp0_in: endpoint { 3001 remote-endpoint = <&dpu_intf0_out>; 3002 }; 3003 }; 3004 3005 port@1 { 3006 reg = <1>; 3007 mdss_dp0_out: endpoint { 3008 }; 3009 }; 3010 }; 3011 3012 dp0_opp_table: opp-table { 3013 compatible = "operating-points-v2"; 3014 3015 opp-160000000 { 3016 opp-hz = /bits/ 64 <160000000>; 3017 required-opps = <&rpmhpd_opp_low_svs>; 3018 }; 3019 3020 opp-270000000 { 3021 opp-hz = /bits/ 64 <270000000>; 3022 required-opps = <&rpmhpd_opp_svs>; 3023 }; 3024 3025 opp-540000000 { 3026 opp-hz = /bits/ 64 <540000000>; 3027 required-opps = <&rpmhpd_opp_svs_l1>; 3028 }; 3029 3030 opp-810000000 { 3031 opp-hz = /bits/ 64 <810000000>; 3032 required-opps = <&rpmhpd_opp_nom>; 3033 }; 3034 }; 3035 }; 3036 3037 mdss_dp1: displayport-controller@ae98000 { 3038 compatible = "qcom,sc8180x-dp"; 3039 reg = <0 0xae98000 0 0x200>, 3040 <0 0xae98200 0 0x200>, 3041 <0 0xae98400 0 0x600>, 3042 <0 0xae98a00 0 0x400>; 3043 interrupt-parent = <&mdss>; 3044 interrupts = <13>; 3045 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3046 <&dispcc DISP_CC_MDSS_DP_AUX1_CLK>, 3047 <&dispcc DISP_CC_MDSS_DP_LINK1_CLK>, 3048 <&dispcc DISP_CC_MDSS_DP_LINK1_INTF_CLK>, 3049 <&dispcc DISP_CC_MDSS_DP_PIXEL2_CLK>; 3050 clock-names = "core_iface", 3051 "core_aux", 3052 "ctrl_link", 3053 "ctrl_link_iface", 3054 "stream_pixel"; 3055 3056 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK1_CLK_SRC>, 3057 <&dispcc DISP_CC_MDSS_DP_PIXEL2_CLK_SRC>; 3058 assigned-clock-parents = <&usb_sec_dpphy 0>, <&usb_sec_dpphy 1>; 3059 3060 phys = <&usb_sec_dpphy>; 3061 phy-names = "dp"; 3062 3063 #sound-dai-cells = <0>; 3064 3065 operating-points-v2 = <&dp0_opp_table>; 3066 power-domains = <&rpmhpd SC8180X_MMCX>; 3067 3068 status = "disabled"; 3069 3070 ports { 3071 #address-cells = <1>; 3072 #size-cells = <0>; 3073 3074 port@0 { 3075 reg = <0>; 3076 dp1_in: endpoint { 3077 remote-endpoint = <&dpu_intf4_out>; 3078 }; 3079 }; 3080 3081 port@1 { 3082 reg = <1>; 3083 mdss_dp1_out: endpoint { 3084 }; 3085 }; 3086 }; 3087 3088 dp1_opp_table: opp-table { 3089 compatible = "operating-points-v2"; 3090 3091 opp-160000000 { 3092 opp-hz = /bits/ 64 <160000000>; 3093 required-opps = <&rpmhpd_opp_low_svs>; 3094 }; 3095 3096 opp-270000000 { 3097 opp-hz = /bits/ 64 <270000000>; 3098 required-opps = <&rpmhpd_opp_svs>; 3099 }; 3100 3101 opp-540000000 { 3102 opp-hz = /bits/ 64 <540000000>; 3103 required-opps = <&rpmhpd_opp_svs_l1>; 3104 }; 3105 3106 opp-810000000 { 3107 opp-hz = /bits/ 64 <810000000>; 3108 required-opps = <&rpmhpd_opp_nom>; 3109 }; 3110 }; 3111 }; 3112 3113 mdss_edp: displayport-controller@ae9a000 { 3114 compatible = "qcom,sc8180x-edp"; 3115 reg = <0 0xae9a000 0 0x200>, 3116 <0 0xae9a200 0 0x200>, 3117 <0 0xae9a400 0 0x600>, 3118 <0 0xae9aa00 0 0x400>; 3119 interrupt-parent = <&mdss>; 3120 interrupts = <14>; 3121 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3122 <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>, 3123 <&dispcc DISP_CC_MDSS_EDP_LINK_CLK>, 3124 <&dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>, 3125 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>; 3126 clock-names = "core_iface", 3127 "core_aux", 3128 "ctrl_link", 3129 "ctrl_link_iface", 3130 "stream_pixel"; 3131 3132 assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>, 3133 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>; 3134 assigned-clock-parents = <&edp_phy 0>, <&edp_phy 1>; 3135 3136 phys = <&edp_phy>; 3137 phy-names = "dp"; 3138 3139 #sound-dai-cells = <0>; 3140 3141 operating-points-v2 = <&edp_opp_table>; 3142 power-domains = <&rpmhpd SC8180X_MMCX>; 3143 3144 status = "disabled"; 3145 3146 ports { 3147 #address-cells = <1>; 3148 #size-cells = <0>; 3149 3150 port@0 { 3151 reg = <0>; 3152 edp_in: endpoint { 3153 remote-endpoint = <&dpu_intf5_out>; 3154 }; 3155 }; 3156 }; 3157 3158 edp_opp_table: opp-table { 3159 compatible = "operating-points-v2"; 3160 3161 opp-160000000 { 3162 opp-hz = /bits/ 64 <160000000>; 3163 required-opps = <&rpmhpd_opp_low_svs>; 3164 }; 3165 3166 opp-270000000 { 3167 opp-hz = /bits/ 64 <270000000>; 3168 required-opps = <&rpmhpd_opp_svs>; 3169 }; 3170 3171 opp-540000000 { 3172 opp-hz = /bits/ 64 <540000000>; 3173 required-opps = <&rpmhpd_opp_svs_l1>; 3174 }; 3175 3176 opp-810000000 { 3177 opp-hz = /bits/ 64 <810000000>; 3178 required-opps = <&rpmhpd_opp_nom>; 3179 }; 3180 }; 3181 }; 3182 }; 3183 3184 edp_phy: phy@aec2a00 { 3185 compatible = "qcom,sc8180x-edp-phy"; 3186 reg = <0 0x0aec2a00 0 0x1c0>, 3187 <0 0x0aec2200 0 0xa0>, 3188 <0 0x0aec2600 0 0xa0>, 3189 <0 0x0aec2000 0 0x19c>; 3190 3191 clocks = <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>, 3192 <&dispcc DISP_CC_MDSS_AHB_CLK>; 3193 clock-names = "aux", "cfg_ahb"; 3194 3195 power-domains = <&rpmhpd SC8180X_MX>; 3196 3197 #clock-cells = <1>; 3198 #phy-cells = <0>; 3199 }; 3200 3201 dispcc: clock-controller@af00000 { 3202 compatible = "qcom,sc8180x-dispcc"; 3203 reg = <0 0x0af00000 0 0x20000>; 3204 clocks = <&rpmhcc RPMH_CXO_CLK>, 3205 <&sleep_clk>, 3206 <&usb_prim_dpphy 0>, 3207 <&usb_prim_dpphy 1>, 3208 <&usb_sec_dpphy 0>, 3209 <&usb_sec_dpphy 1>, 3210 <&edp_phy 0>, 3211 <&edp_phy 1>; 3212 clock-names = "bi_tcxo", 3213 "sleep_clk", 3214 "dp_phy_pll_link_clk", 3215 "dp_phy_pll_vco_div_clk", 3216 "dptx1_phy_pll_link_clk", 3217 "dptx1_phy_pll_vco_div_clk", 3218 "edp_phy_pll_link_clk", 3219 "edp_phy_pll_vco_div_clk"; 3220 power-domains = <&rpmhpd SC8180X_MMCX>; 3221 required-opps = <&rpmhpd_opp_low_svs>; 3222 #clock-cells = <1>; 3223 #reset-cells = <1>; 3224 #power-domain-cells = <1>; 3225 }; 3226 3227 pdc: interrupt-controller@b220000 { 3228 compatible = "qcom,sc8180x-pdc", "qcom,pdc"; 3229 reg = <0 0x0b220000 0 0x30000>; 3230 qcom,pdc-ranges = <0 480 94>, <94 609 31>; 3231 #interrupt-cells = <2>; 3232 interrupt-parent = <&intc>; 3233 interrupt-controller; 3234 }; 3235 3236 tsens0: thermal-sensor@c263000 { 3237 compatible = "qcom,sc8180x-tsens", "qcom,tsens-v2"; 3238 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 3239 <0 0x0c222000 0 0x1ff>; /* SROT */ 3240 #qcom,sensors = <16>; 3241 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 3242 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 3243 interrupt-names = "uplow", "critical"; 3244 #thermal-sensor-cells = <1>; 3245 }; 3246 3247 tsens1: thermal-sensor@c265000 { 3248 compatible = "qcom,sc8180x-tsens", "qcom,tsens-v2"; 3249 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 3250 <0 0x0c223000 0 0x1ff>; /* SROT */ 3251 #qcom,sensors = <9>; 3252 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 3253 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 3254 interrupt-names = "uplow", "critical"; 3255 #thermal-sensor-cells = <1>; 3256 }; 3257 3258 aoss_qmp: power-controller@c300000 { 3259 compatible = "qcom,sc8180x-aoss-qmp", "qcom,aoss-qmp"; 3260 reg = <0x0 0x0c300000 0x0 0x400>; 3261 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; 3262 mboxes = <&apss_shared 0>; 3263 3264 #clock-cells = <0>; 3265 #power-domain-cells = <1>; 3266 }; 3267 3268 spmi_bus: spmi@c440000 { 3269 compatible = "qcom,spmi-pmic-arb"; 3270 reg = <0x0 0x0c440000 0x0 0x0001100>, 3271 <0x0 0x0c600000 0x0 0x2000000>, 3272 <0x0 0x0e600000 0x0 0x0100000>, 3273 <0x0 0x0e700000 0x0 0x00a0000>, 3274 <0x0 0x0c40a000 0x0 0x0026000>; 3275 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 3276 interrupt-names = "periph_irq"; 3277 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>; 3278 qcom,ee = <0>; 3279 qcom,channel = <0>; 3280 #address-cells = <2>; 3281 #size-cells = <0>; 3282 interrupt-controller; 3283 #interrupt-cells = <4>; 3284 cell-index = <0>; 3285 }; 3286 3287 apps_smmu: iommu@15000000 { 3288 compatible = "qcom,sc8180x-smmu-500", "arm,mmu-500"; 3289 reg = <0 0x15000000 0 0x100000>; 3290 #iommu-cells = <2>; 3291 #global-interrupts = <1>; 3292 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3293 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3294 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3295 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3296 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3297 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3298 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3299 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3300 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3301 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3302 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3303 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3304 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3305 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3306 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3307 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3308 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3309 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3310 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3311 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3312 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3313 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3314 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3315 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3316 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3317 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3318 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3319 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3320 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3321 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3322 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3323 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3324 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3325 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3326 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3327 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3328 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3329 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3330 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3331 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3332 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3333 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3334 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3335 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3336 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3337 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3338 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3339 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3340 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3341 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3342 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3343 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3344 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3345 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3346 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3347 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3348 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3349 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3350 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3351 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3352 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3353 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3354 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3355 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3356 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3357 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3358 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 3359 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 3360 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 3361 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 3362 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 3363 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 3364 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3365 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3366 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3367 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3368 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3369 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3370 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3371 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 3372 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 3373 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 3374 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 3375 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 3376 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>, 3377 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, 3378 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 3379 <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>, 3380 <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>, 3381 <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>, 3382 <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>, 3383 <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>, 3384 <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>, 3385 <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>, 3386 <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>, 3387 <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH>, 3388 <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH>, 3389 <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>, 3390 <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>, 3391 <GIC_SPI 768 IRQ_TYPE_LEVEL_HIGH>, 3392 <GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH>, 3393 <GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>, 3394 <GIC_SPI 771 IRQ_TYPE_LEVEL_HIGH>, 3395 <GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>, 3396 <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>, 3397 <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>, 3398 <GIC_SPI 775 IRQ_TYPE_LEVEL_HIGH>; 3399 3400 }; 3401 3402 remoteproc_adsp: remoteproc@17300000 { 3403 compatible = "qcom,sc8180x-adsp-pas"; 3404 reg = <0x0 0x17300000 0x0 0x4040>; 3405 3406 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 3407 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3408 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3409 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3410 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 3411 interrupt-names = "wdog", "fatal", "ready", 3412 "handover", "stop-ack"; 3413 3414 clocks = <&rpmhcc RPMH_CXO_CLK>; 3415 clock-names = "xo"; 3416 3417 power-domains = <&rpmhpd SC8180X_CX>; 3418 power-domain-names = "cx"; 3419 3420 qcom,qmp = <&aoss_qmp>; 3421 3422 qcom,smem-states = <&adsp_smp2p_out 0>; 3423 qcom,smem-state-names = "stop"; 3424 3425 status = "disabled"; 3426 3427 remoteproc_adsp_glink: glink-edge { 3428 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 3429 label = "lpass"; 3430 qcom,remote-pid = <2>; 3431 mboxes = <&apss_shared 8>; 3432 }; 3433 }; 3434 3435 intc: interrupt-controller@17a00000 { 3436 compatible = "arm,gic-v3"; 3437 interrupt-controller; 3438 #interrupt-cells = <3>; 3439 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 3440 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 3441 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3442 }; 3443 3444 apss_shared: mailbox@17c00000 { 3445 compatible = "qcom,sc8180x-apss-shared"; 3446 reg = <0x0 0x17c00000 0x0 0x1000>; 3447 #mbox-cells = <1>; 3448 }; 3449 3450 timer@17c20000 { 3451 compatible = "arm,armv7-timer-mem"; 3452 reg = <0x0 0x17c20000 0x0 0x1000>; 3453 3454 #address-cells = <1>; 3455 #size-cells = <1>; 3456 ranges = <0 0 0 0x20000000>; 3457 3458 frame@17c21000 { 3459 reg = <0x17c21000 0x1000>, 3460 <0x17c22000 0x1000>; 3461 frame-number = <0>; 3462 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3463 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3464 }; 3465 3466 frame@17c23000 { 3467 reg = <0x17c23000 0x1000>; 3468 frame-number = <1>; 3469 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3470 status = "disabled"; 3471 }; 3472 3473 frame@17c25000 { 3474 reg = <0x17c25000 0x1000>; 3475 frame-number = <2>; 3476 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3477 status = "disabled"; 3478 }; 3479 3480 frame@17c27000 { 3481 reg = <0x17c26000 0x1000>; 3482 frame-number = <3>; 3483 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3484 status = "disabled"; 3485 }; 3486 3487 frame@17c29000 { 3488 reg = <0x17c29000 0x1000>; 3489 frame-number = <4>; 3490 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3491 status = "disabled"; 3492 }; 3493 3494 frame@17c2b000 { 3495 reg = <0x17c2b000 0x1000>; 3496 frame-number = <5>; 3497 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3498 status = "disabled"; 3499 }; 3500 3501 frame@17c2d000 { 3502 reg = <0x17c2d000 0x1000>; 3503 frame-number = <6>; 3504 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3505 status = "disabled"; 3506 }; 3507 }; 3508 3509 apps_rsc: rsc@18200000 { 3510 compatible = "qcom,rpmh-rsc"; 3511 reg = <0x0 0x18200000 0x0 0x10000>, 3512 <0x0 0x18210000 0x0 0x10000>, 3513 <0x0 0x18220000 0x0 0x10000>; 3514 reg-names = "drv-0", "drv-1", "drv-2"; 3515 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3516 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3517 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3518 qcom,tcs-offset = <0xd00>; 3519 qcom,drv-id = <2>; 3520 qcom,tcs-config = <ACTIVE_TCS 2>, 3521 <SLEEP_TCS 1>, 3522 <WAKE_TCS 1>, 3523 <CONTROL_TCS 0>; 3524 label = "apps_rsc"; 3525 power-domains = <&CLUSTER_PD>; 3526 3527 apps_bcm_voter: bcm-voter { 3528 compatible = "qcom,bcm-voter"; 3529 }; 3530 3531 rpmhcc: clock-controller { 3532 compatible = "qcom,sc8180x-rpmh-clk"; 3533 #clock-cells = <1>; 3534 clock-names = "xo"; 3535 clocks = <&xo_board_clk>; 3536 }; 3537 3538 rpmhpd: power-controller { 3539 compatible = "qcom,sc8180x-rpmhpd"; 3540 #power-domain-cells = <1>; 3541 operating-points-v2 = <&rpmhpd_opp_table>; 3542 3543 rpmhpd_opp_table: opp-table { 3544 compatible = "operating-points-v2"; 3545 3546 rpmhpd_opp_ret: opp1 { 3547 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3548 }; 3549 3550 rpmhpd_opp_min_svs: opp2 { 3551 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3552 }; 3553 3554 rpmhpd_opp_low_svs: opp3 { 3555 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3556 }; 3557 3558 rpmhpd_opp_svs: opp4 { 3559 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3560 }; 3561 3562 rpmhpd_opp_svs_l1: opp5 { 3563 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3564 }; 3565 3566 rpmhpd_opp_nom: opp6 { 3567 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3568 }; 3569 3570 rpmhpd_opp_nom_l1: opp7 { 3571 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3572 }; 3573 3574 rpmhpd_opp_nom_l2: opp8 { 3575 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 3576 }; 3577 3578 rpmhpd_opp_turbo: opp9 { 3579 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3580 }; 3581 3582 rpmhpd_opp_turbo_l1: opp10 { 3583 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3584 }; 3585 }; 3586 }; 3587 }; 3588 3589 osm_l3: interconnect@18321000 { 3590 compatible = "qcom,sc8180x-osm-l3", "qcom,osm-l3"; 3591 reg = <0 0x18321000 0 0x1400>; 3592 3593 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 3594 clock-names = "xo", "alternate"; 3595 3596 #interconnect-cells = <1>; 3597 }; 3598 3599 lmh@18350800 { 3600 compatible = "qcom,sc8180x-lmh"; 3601 reg = <0 0x18350800 0 0x400>; 3602 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 3603 cpus = <&CPU4>; 3604 qcom,lmh-temp-arm-millicelsius = <65000>; 3605 qcom,lmh-temp-low-millicelsius = <94500>; 3606 qcom,lmh-temp-high-millicelsius = <95000>; 3607 interrupt-controller; 3608 #interrupt-cells = <1>; 3609 }; 3610 3611 lmh@18358800 { 3612 compatible = "qcom,sc8180x-lmh"; 3613 reg = <0 0x18358800 0 0x400>; 3614 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 3615 cpus = <&CPU0>; 3616 qcom,lmh-temp-arm-millicelsius = <65000>; 3617 qcom,lmh-temp-low-millicelsius = <94500>; 3618 qcom,lmh-temp-high-millicelsius = <95000>; 3619 interrupt-controller; 3620 #interrupt-cells = <1>; 3621 }; 3622 3623 cpufreq_hw: cpufreq@18323000 { 3624 compatible = "qcom,cpufreq-hw"; 3625 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>; 3626 reg-names = "freq-domain0", "freq-domain1"; 3627 3628 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 3629 clock-names = "xo", "alternate"; 3630 3631 #freq-domain-cells = <1>; 3632 #clock-cells = <1>; 3633 }; 3634 3635 wifi: wifi@18800000 { 3636 compatible = "qcom,wcn3990-wifi"; 3637 reg = <0 0x18800000 0 0x800000>; 3638 reg-names = "membase"; 3639 clock-names = "cxo_ref_clk_pin"; 3640 clocks = <&rpmhcc RPMH_RF_CLK2>; 3641 interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 3642 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 3643 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 3644 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 3645 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 3646 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 3647 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 3648 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 3649 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 3650 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 3651 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 3652 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 3653 iommus = <&apps_smmu 0x0640 0x1>; 3654 qcom,msa-fixed-perm; 3655 status = "disabled"; 3656 }; 3657 }; 3658 3659 thermal-zones { 3660 cpu0-thermal { 3661 polling-delay-passive = <250>; 3662 polling-delay = <1000>; 3663 3664 thermal-sensors = <&tsens0 1>; 3665 3666 trips { 3667 cpu-crit { 3668 temperature = <110000>; 3669 hysteresis = <1000>; 3670 type = "critical"; 3671 }; 3672 }; 3673 }; 3674 3675 cpu1-thermal { 3676 polling-delay-passive = <250>; 3677 polling-delay = <1000>; 3678 3679 thermal-sensors = <&tsens0 2>; 3680 3681 trips { 3682 cpu-crit { 3683 temperature = <110000>; 3684 hysteresis = <1000>; 3685 type = "critical"; 3686 }; 3687 }; 3688 }; 3689 3690 cpu2-thermal { 3691 polling-delay-passive = <250>; 3692 polling-delay = <1000>; 3693 3694 thermal-sensors = <&tsens0 3>; 3695 3696 trips { 3697 cpu-crit { 3698 temperature = <110000>; 3699 hysteresis = <1000>; 3700 type = "critical"; 3701 }; 3702 }; 3703 }; 3704 3705 cpu3-thermal { 3706 polling-delay-passive = <250>; 3707 polling-delay = <1000>; 3708 3709 thermal-sensors = <&tsens0 4>; 3710 3711 trips { 3712 cpu-crit { 3713 temperature = <110000>; 3714 hysteresis = <1000>; 3715 type = "critical"; 3716 }; 3717 }; 3718 }; 3719 3720 cpu4-top-thermal { 3721 polling-delay-passive = <250>; 3722 polling-delay = <1000>; 3723 3724 thermal-sensors = <&tsens0 7>; 3725 3726 trips { 3727 cpu-crit { 3728 temperature = <110000>; 3729 hysteresis = <1000>; 3730 type = "critical"; 3731 }; 3732 }; 3733 }; 3734 3735 cpu5-top-thermal { 3736 polling-delay-passive = <250>; 3737 polling-delay = <1000>; 3738 3739 thermal-sensors = <&tsens0 8>; 3740 3741 trips { 3742 cpu-crit { 3743 temperature = <110000>; 3744 hysteresis = <1000>; 3745 type = "critical"; 3746 }; 3747 }; 3748 }; 3749 3750 cpu6-top-thermal { 3751 polling-delay-passive = <250>; 3752 polling-delay = <1000>; 3753 3754 thermal-sensors = <&tsens0 9>; 3755 3756 trips { 3757 cpu-crit { 3758 temperature = <110000>; 3759 hysteresis = <1000>; 3760 type = "critical"; 3761 }; 3762 }; 3763 }; 3764 3765 cpu7-top-thermal { 3766 polling-delay-passive = <250>; 3767 polling-delay = <1000>; 3768 3769 thermal-sensors = <&tsens0 10>; 3770 3771 trips { 3772 cpu-crit { 3773 temperature = <110000>; 3774 hysteresis = <1000>; 3775 type = "critical"; 3776 }; 3777 }; 3778 }; 3779 3780 cpu4-bottom-thermal { 3781 polling-delay-passive = <250>; 3782 polling-delay = <1000>; 3783 3784 thermal-sensors = <&tsens0 11>; 3785 3786 trips { 3787 cpu-crit { 3788 temperature = <110000>; 3789 hysteresis = <1000>; 3790 type = "critical"; 3791 }; 3792 }; 3793 }; 3794 3795 cpu5-bottom-thermal { 3796 polling-delay-passive = <250>; 3797 polling-delay = <1000>; 3798 3799 thermal-sensors = <&tsens0 12>; 3800 3801 trips { 3802 cpu-crit { 3803 temperature = <110000>; 3804 hysteresis = <1000>; 3805 type = "critical"; 3806 }; 3807 }; 3808 }; 3809 3810 cpu6-bottom-thermal { 3811 polling-delay-passive = <250>; 3812 polling-delay = <1000>; 3813 3814 thermal-sensors = <&tsens0 13>; 3815 3816 trips { 3817 cpu-crit { 3818 temperature = <110000>; 3819 hysteresis = <1000>; 3820 type = "critical"; 3821 }; 3822 }; 3823 }; 3824 3825 cpu7-bottom-thermal { 3826 polling-delay-passive = <250>; 3827 polling-delay = <1000>; 3828 3829 thermal-sensors = <&tsens0 14>; 3830 3831 trips { 3832 cpu-crit { 3833 temperature = <110000>; 3834 hysteresis = <1000>; 3835 type = "critical"; 3836 }; 3837 }; 3838 }; 3839 3840 aoss0-thermal { 3841 polling-delay-passive = <250>; 3842 polling-delay = <1000>; 3843 3844 thermal-sensors = <&tsens0 0>; 3845 3846 trips { 3847 trip-point0 { 3848 temperature = <90000>; 3849 hysteresis = <2000>; 3850 type = "hot"; 3851 }; 3852 }; 3853 }; 3854 3855 cluster0-thermal { 3856 polling-delay-passive = <250>; 3857 polling-delay = <1000>; 3858 3859 thermal-sensors = <&tsens0 5>; 3860 3861 trips { 3862 cluster-crit { 3863 temperature = <110000>; 3864 hysteresis = <2000>; 3865 type = "critical"; 3866 }; 3867 }; 3868 }; 3869 3870 cluster1-thermal { 3871 polling-delay-passive = <250>; 3872 polling-delay = <1000>; 3873 3874 thermal-sensors = <&tsens0 6>; 3875 3876 trips { 3877 cluster-crit { 3878 temperature = <110000>; 3879 hysteresis = <2000>; 3880 type = "critical"; 3881 }; 3882 }; 3883 }; 3884 3885 gpu-top-thermal { 3886 polling-delay-passive = <250>; 3887 polling-delay = <1000>; 3888 3889 thermal-sensors = <&tsens0 15>; 3890 3891 trips { 3892 trip-point0 { 3893 temperature = <90000>; 3894 hysteresis = <2000>; 3895 type = "hot"; 3896 }; 3897 }; 3898 }; 3899 3900 aoss1-thermal { 3901 polling-delay-passive = <250>; 3902 polling-delay = <1000>; 3903 3904 thermal-sensors = <&tsens1 0>; 3905 3906 trips { 3907 trip-point0 { 3908 temperature = <90000>; 3909 hysteresis = <2000>; 3910 type = "hot"; 3911 }; 3912 }; 3913 }; 3914 3915 wlan-thermal { 3916 polling-delay-passive = <250>; 3917 polling-delay = <1000>; 3918 3919 thermal-sensors = <&tsens1 1>; 3920 3921 trips { 3922 trip-point0 { 3923 temperature = <90000>; 3924 hysteresis = <2000>; 3925 type = "hot"; 3926 }; 3927 }; 3928 }; 3929 3930 video-thermal { 3931 polling-delay-passive = <250>; 3932 polling-delay = <1000>; 3933 3934 thermal-sensors = <&tsens1 2>; 3935 3936 trips { 3937 trip-point0 { 3938 temperature = <90000>; 3939 hysteresis = <2000>; 3940 type = "hot"; 3941 }; 3942 }; 3943 }; 3944 3945 mem-thermal { 3946 polling-delay-passive = <250>; 3947 polling-delay = <1000>; 3948 3949 thermal-sensors = <&tsens1 3>; 3950 3951 trips { 3952 trip-point0 { 3953 temperature = <90000>; 3954 hysteresis = <2000>; 3955 type = "hot"; 3956 }; 3957 }; 3958 }; 3959 3960 q6-hvx-thermal { 3961 polling-delay-passive = <250>; 3962 polling-delay = <1000>; 3963 3964 thermal-sensors = <&tsens1 4>; 3965 3966 trips { 3967 trip-point0 { 3968 temperature = <90000>; 3969 hysteresis = <2000>; 3970 type = "hot"; 3971 }; 3972 }; 3973 }; 3974 3975 camera-thermal { 3976 polling-delay-passive = <250>; 3977 polling-delay = <1000>; 3978 3979 thermal-sensors = <&tsens1 5>; 3980 3981 trips { 3982 trip-point0 { 3983 temperature = <90000>; 3984 hysteresis = <2000>; 3985 type = "hot"; 3986 }; 3987 }; 3988 }; 3989 3990 compute-thermal { 3991 polling-delay-passive = <250>; 3992 polling-delay = <1000>; 3993 3994 thermal-sensors = <&tsens1 6>; 3995 3996 trips { 3997 trip-point0 { 3998 temperature = <90000>; 3999 hysteresis = <2000>; 4000 type = "hot"; 4001 }; 4002 }; 4003 }; 4004 4005 mdm-dsp-thermal { 4006 polling-delay-passive = <250>; 4007 polling-delay = <1000>; 4008 4009 thermal-sensors = <&tsens1 7>; 4010 4011 trips { 4012 trip-point0 { 4013 temperature = <90000>; 4014 hysteresis = <2000>; 4015 type = "hot"; 4016 }; 4017 }; 4018 }; 4019 4020 npu-thermal { 4021 polling-delay-passive = <250>; 4022 polling-delay = <1000>; 4023 4024 thermal-sensors = <&tsens1 8>; 4025 4026 trips { 4027 trip-point0 { 4028 temperature = <90000>; 4029 hysteresis = <2000>; 4030 type = "hot"; 4031 }; 4032 }; 4033 }; 4034 4035 gpu-bottom-thermal { 4036 polling-delay-passive = <250>; 4037 polling-delay = <1000>; 4038 4039 thermal-sensors = <&tsens1 11>; 4040 4041 trips { 4042 trip-point0 { 4043 temperature = <90000>; 4044 hysteresis = <2000>; 4045 type = "hot"; 4046 }; 4047 }; 4048 }; 4049 }; 4050 4051 timer { 4052 compatible = "arm,armv8-timer"; 4053 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 4054 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 4055 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 4056 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 4057 }; 4058}; 4059