1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2020-2023, Linaro Limited 5 */ 6 7#include <dt-bindings/clock/qcom,dispcc-sm8250.h> 8#include <dt-bindings/clock/qcom,gcc-sc8180x.h> 9#include <dt-bindings/clock/qcom,gpucc-sm8150.h> 10#include <dt-bindings/clock/qcom,rpmh.h> 11#include <dt-bindings/interconnect/qcom,osm-l3.h> 12#include <dt-bindings/interconnect/qcom,sc8180x.h> 13#include <dt-bindings/interrupt-controller/arm-gic.h> 14#include <dt-bindings/power/qcom-rpmpd.h> 15#include <dt-bindings/soc/qcom,rpmh-rsc.h> 16#include <dt-bindings/thermal/thermal.h> 17 18/ { 19 interrupt-parent = <&intc>; 20 21 #address-cells = <2>; 22 #size-cells = <2>; 23 24 clocks { 25 xo_board_clk: xo-board { 26 compatible = "fixed-clock"; 27 #clock-cells = <0>; 28 clock-frequency = <38400000>; 29 }; 30 31 sleep_clk: sleep-clk { 32 compatible = "fixed-clock"; 33 #clock-cells = <0>; 34 clock-frequency = <32764>; 35 clock-output-names = "sleep_clk"; 36 }; 37 }; 38 39 cpus { 40 #address-cells = <2>; 41 #size-cells = <0>; 42 43 CPU0: cpu@0 { 44 device_type = "cpu"; 45 compatible = "qcom,kryo485"; 46 reg = <0x0 0x0>; 47 enable-method = "psci"; 48 capacity-dmips-mhz = <602>; 49 next-level-cache = <&L2_0>; 50 qcom,freq-domain = <&cpufreq_hw 0>; 51 operating-points-v2 = <&cpu0_opp_table>; 52 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, 53 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 54 power-domains = <&CPU_PD0>; 55 power-domain-names = "psci"; 56 #cooling-cells = <2>; 57 clocks = <&cpufreq_hw 0>; 58 59 L2_0: l2-cache { 60 compatible = "cache"; 61 cache-level = <2>; 62 cache-unified; 63 next-level-cache = <&L3_0>; 64 L3_0: l3-cache { 65 compatible = "cache"; 66 cache-level = <3>; 67 cache-unified; 68 }; 69 }; 70 }; 71 72 CPU1: cpu@100 { 73 device_type = "cpu"; 74 compatible = "qcom,kryo485"; 75 reg = <0x0 0x100>; 76 enable-method = "psci"; 77 capacity-dmips-mhz = <602>; 78 next-level-cache = <&L2_100>; 79 qcom,freq-domain = <&cpufreq_hw 0>; 80 operating-points-v2 = <&cpu0_opp_table>; 81 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, 82 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 83 power-domains = <&CPU_PD1>; 84 power-domain-names = "psci"; 85 #cooling-cells = <2>; 86 clocks = <&cpufreq_hw 0>; 87 88 L2_100: l2-cache { 89 compatible = "cache"; 90 cache-level = <2>; 91 cache-unified; 92 next-level-cache = <&L3_0>; 93 }; 94 95 }; 96 97 CPU2: cpu@200 { 98 device_type = "cpu"; 99 compatible = "qcom,kryo485"; 100 reg = <0x0 0x200>; 101 enable-method = "psci"; 102 capacity-dmips-mhz = <602>; 103 next-level-cache = <&L2_200>; 104 qcom,freq-domain = <&cpufreq_hw 0>; 105 operating-points-v2 = <&cpu0_opp_table>; 106 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, 107 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 108 power-domains = <&CPU_PD2>; 109 power-domain-names = "psci"; 110 #cooling-cells = <2>; 111 clocks = <&cpufreq_hw 0>; 112 113 L2_200: l2-cache { 114 compatible = "cache"; 115 cache-level = <2>; 116 cache-unified; 117 next-level-cache = <&L3_0>; 118 }; 119 }; 120 121 CPU3: cpu@300 { 122 device_type = "cpu"; 123 compatible = "qcom,kryo485"; 124 reg = <0x0 0x300>; 125 enable-method = "psci"; 126 capacity-dmips-mhz = <602>; 127 next-level-cache = <&L2_300>; 128 qcom,freq-domain = <&cpufreq_hw 0>; 129 operating-points-v2 = <&cpu0_opp_table>; 130 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, 131 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 132 power-domains = <&CPU_PD3>; 133 power-domain-names = "psci"; 134 #cooling-cells = <2>; 135 clocks = <&cpufreq_hw 0>; 136 137 L2_300: l2-cache { 138 compatible = "cache"; 139 cache-unified; 140 cache-level = <2>; 141 next-level-cache = <&L3_0>; 142 }; 143 }; 144 145 CPU4: cpu@400 { 146 device_type = "cpu"; 147 compatible = "qcom,kryo485"; 148 reg = <0x0 0x400>; 149 enable-method = "psci"; 150 capacity-dmips-mhz = <1024>; 151 next-level-cache = <&L2_400>; 152 qcom,freq-domain = <&cpufreq_hw 1>; 153 operating-points-v2 = <&cpu4_opp_table>; 154 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, 155 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 156 power-domains = <&CPU_PD4>; 157 power-domain-names = "psci"; 158 #cooling-cells = <2>; 159 clocks = <&cpufreq_hw 1>; 160 161 L2_400: l2-cache { 162 compatible = "cache"; 163 cache-unified; 164 cache-level = <2>; 165 next-level-cache = <&L3_0>; 166 }; 167 }; 168 169 CPU5: cpu@500 { 170 device_type = "cpu"; 171 compatible = "qcom,kryo485"; 172 reg = <0x0 0x500>; 173 enable-method = "psci"; 174 capacity-dmips-mhz = <1024>; 175 next-level-cache = <&L2_500>; 176 qcom,freq-domain = <&cpufreq_hw 1>; 177 operating-points-v2 = <&cpu4_opp_table>; 178 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, 179 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 180 power-domains = <&CPU_PD5>; 181 power-domain-names = "psci"; 182 #cooling-cells = <2>; 183 clocks = <&cpufreq_hw 1>; 184 185 L2_500: l2-cache { 186 compatible = "cache"; 187 cache-unified; 188 cache-level = <2>; 189 next-level-cache = <&L3_0>; 190 }; 191 }; 192 193 CPU6: cpu@600 { 194 device_type = "cpu"; 195 compatible = "qcom,kryo485"; 196 reg = <0x0 0x600>; 197 enable-method = "psci"; 198 capacity-dmips-mhz = <1024>; 199 next-level-cache = <&L2_600>; 200 qcom,freq-domain = <&cpufreq_hw 1>; 201 operating-points-v2 = <&cpu4_opp_table>; 202 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, 203 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 204 power-domains = <&CPU_PD6>; 205 power-domain-names = "psci"; 206 #cooling-cells = <2>; 207 clocks = <&cpufreq_hw 1>; 208 209 L2_600: l2-cache { 210 compatible = "cache"; 211 cache-unified; 212 cache-level = <2>; 213 next-level-cache = <&L3_0>; 214 }; 215 }; 216 217 CPU7: cpu@700 { 218 device_type = "cpu"; 219 compatible = "qcom,kryo485"; 220 reg = <0x0 0x700>; 221 enable-method = "psci"; 222 capacity-dmips-mhz = <1024>; 223 next-level-cache = <&L2_700>; 224 qcom,freq-domain = <&cpufreq_hw 1>; 225 operating-points-v2 = <&cpu4_opp_table>; 226 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, 227 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 228 power-domains = <&CPU_PD7>; 229 power-domain-names = "psci"; 230 #cooling-cells = <2>; 231 clocks = <&cpufreq_hw 1>; 232 233 L2_700: l2-cache { 234 compatible = "cache"; 235 cache-unified; 236 cache-level = <2>; 237 next-level-cache = <&L3_0>; 238 }; 239 }; 240 241 cpu-map { 242 cluster0 { 243 core0 { 244 cpu = <&CPU0>; 245 }; 246 247 core1 { 248 cpu = <&CPU1>; 249 }; 250 251 core2 { 252 cpu = <&CPU2>; 253 }; 254 255 core3 { 256 cpu = <&CPU3>; 257 }; 258 259 core4 { 260 cpu = <&CPU4>; 261 }; 262 263 core5 { 264 cpu = <&CPU5>; 265 }; 266 267 core6 { 268 cpu = <&CPU6>; 269 }; 270 271 core7 { 272 cpu = <&CPU7>; 273 }; 274 }; 275 }; 276 277 idle-states { 278 entry-method = "psci"; 279 280 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 281 compatible = "arm,idle-state"; 282 arm,psci-suspend-param = <0x40000004>; 283 entry-latency-us = <355>; 284 exit-latency-us = <909>; 285 min-residency-us = <3934>; 286 local-timer-stop; 287 }; 288 289 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 290 compatible = "arm,idle-state"; 291 arm,psci-suspend-param = <0x40000004>; 292 entry-latency-us = <241>; 293 exit-latency-us = <1461>; 294 min-residency-us = <4488>; 295 local-timer-stop; 296 }; 297 }; 298 299 domain-idle-states { 300 CLUSTER_SLEEP_0: cluster-sleep-0 { 301 compatible = "domain-idle-state"; 302 arm,psci-suspend-param = <0x4100a344>; 303 entry-latency-us = <3263>; 304 exit-latency-us = <6562>; 305 min-residency-us = <9987>; 306 }; 307 }; 308 }; 309 310 cpu0_opp_table: opp-table-cpu0 { 311 compatible = "operating-points-v2"; 312 opp-shared; 313 314 opp-300000000 { 315 opp-hz = /bits/ 64 <300000000>; 316 opp-peak-kBps = <800000 9600000>; 317 }; 318 319 opp-422400000 { 320 opp-hz = /bits/ 64 <422400000>; 321 opp-peak-kBps = <800000 9600000>; 322 }; 323 324 opp-537600000 { 325 opp-hz = /bits/ 64 <537600000>; 326 opp-peak-kBps = <800000 12902400>; 327 }; 328 329 opp-652800000 { 330 opp-hz = /bits/ 64 <652800000>; 331 opp-peak-kBps = <800000 12902400>; 332 }; 333 334 opp-768000000 { 335 opp-hz = /bits/ 64 <768000000>; 336 opp-peak-kBps = <800000 15974400>; 337 }; 338 339 opp-883200000 { 340 opp-hz = /bits/ 64 <883200000>; 341 opp-peak-kBps = <1804000 19660800>; 342 }; 343 344 opp-998400000 { 345 opp-hz = /bits/ 64 <998400000>; 346 opp-peak-kBps = <1804000 19660800>; 347 }; 348 349 opp-1113600000 { 350 opp-hz = /bits/ 64 <1113600000>; 351 opp-peak-kBps = <1804000 22732800>; 352 }; 353 354 opp-1228800000 { 355 opp-hz = /bits/ 64 <1228800000>; 356 opp-peak-kBps = <1804000 22732800>; 357 }; 358 359 opp-1363200000 { 360 opp-hz = /bits/ 64 <1363200000>; 361 opp-peak-kBps = <2188000 25804800>; 362 }; 363 364 opp-1478400000 { 365 opp-hz = /bits/ 64 <1478400000>; 366 opp-peak-kBps = <2188000 31948800>; 367 }; 368 369 opp-1574400000 { 370 opp-hz = /bits/ 64 <1574400000>; 371 opp-peak-kBps = <3072000 31948800>; 372 }; 373 374 opp-1670400000 { 375 opp-hz = /bits/ 64 <1670400000>; 376 opp-peak-kBps = <3072000 31948800>; 377 }; 378 379 opp-1766400000 { 380 opp-hz = /bits/ 64 <1766400000>; 381 opp-peak-kBps = <3072000 31948800>; 382 }; 383 }; 384 385 cpu4_opp_table: opp-table-cpu4 { 386 compatible = "operating-points-v2"; 387 opp-shared; 388 389 opp-825600000 { 390 opp-hz = /bits/ 64 <825600000>; 391 opp-peak-kBps = <1804000 15974400>; 392 }; 393 394 opp-940800000 { 395 opp-hz = /bits/ 64 <940800000>; 396 opp-peak-kBps = <2188000 19660800>; 397 }; 398 399 opp-1056000000 { 400 opp-hz = /bits/ 64 <1056000000>; 401 opp-peak-kBps = <2188000 22732800>; 402 }; 403 404 opp-1171200000 { 405 opp-hz = /bits/ 64 <1171200000>; 406 opp-peak-kBps = <3072000 25804800>; 407 }; 408 409 opp-1286400000 { 410 opp-hz = /bits/ 64 <1286400000>; 411 opp-peak-kBps = <3072000 31948800>; 412 }; 413 414 opp-1420800000 { 415 opp-hz = /bits/ 64 <1420800000>; 416 opp-peak-kBps = <4068000 31948800>; 417 }; 418 419 opp-1536000000 { 420 opp-hz = /bits/ 64 <1536000000>; 421 opp-peak-kBps = <4068000 31948800>; 422 }; 423 424 opp-1651200000 { 425 opp-hz = /bits/ 64 <1651200000>; 426 opp-peak-kBps = <4068000 40550400>; 427 }; 428 429 opp-1766400000 { 430 opp-hz = /bits/ 64 <1766400000>; 431 opp-peak-kBps = <4068000 40550400>; 432 }; 433 434 opp-1881600000 { 435 opp-hz = /bits/ 64 <1881600000>; 436 opp-peak-kBps = <4068000 43008000>; 437 }; 438 439 opp-1996800000 { 440 opp-hz = /bits/ 64 <1996800000>; 441 opp-peak-kBps = <6220000 43008000>; 442 }; 443 444 opp-2131200000 { 445 opp-hz = /bits/ 64 <2131200000>; 446 opp-peak-kBps = <6220000 49152000>; 447 }; 448 449 opp-2246400000 { 450 opp-hz = /bits/ 64 <2246400000>; 451 opp-peak-kBps = <7216000 49152000>; 452 }; 453 454 opp-2361600000 { 455 opp-hz = /bits/ 64 <2361600000>; 456 opp-peak-kBps = <8368000 49152000>; 457 }; 458 459 opp-2457600000 { 460 opp-hz = /bits/ 64 <2457600000>; 461 opp-peak-kBps = <8368000 51609600>; 462 }; 463 464 opp-2553600000 { 465 opp-hz = /bits/ 64 <2553600000>; 466 opp-peak-kBps = <8368000 51609600>; 467 }; 468 469 opp-2649600000 { 470 opp-hz = /bits/ 64 <2649600000>; 471 opp-peak-kBps = <8368000 51609600>; 472 }; 473 474 opp-2745600000 { 475 opp-hz = /bits/ 64 <2745600000>; 476 opp-peak-kBps = <8368000 51609600>; 477 }; 478 479 opp-2841600000 { 480 opp-hz = /bits/ 64 <2841600000>; 481 opp-peak-kBps = <8368000 51609600>; 482 }; 483 484 opp-2918400000 { 485 opp-hz = /bits/ 64 <2918400000>; 486 opp-peak-kBps = <8368000 51609600>; 487 }; 488 489 opp-2995200000 { 490 opp-hz = /bits/ 64 <2995200000>; 491 opp-peak-kBps = <8368000 51609600>; 492 }; 493 }; 494 495 firmware { 496 scm: scm { 497 compatible = "qcom,scm-sc8180x", "qcom,scm"; 498 }; 499 }; 500 501 camnoc_virt: interconnect-camnoc-virt { 502 compatible = "qcom,sc8180x-camnoc-virt"; 503 #interconnect-cells = <2>; 504 qcom,bcm-voters = <&apps_bcm_voter>; 505 }; 506 507 mc_virt: interconnect-mc-virt { 508 compatible = "qcom,sc8180x-mc-virt"; 509 #interconnect-cells = <2>; 510 qcom,bcm-voters = <&apps_bcm_voter>; 511 }; 512 513 qup_virt: interconnect-qup-virt { 514 compatible = "qcom,sc8180x-qup-virt"; 515 #interconnect-cells = <2>; 516 qcom,bcm-voters = <&apps_bcm_voter>; 517 }; 518 519 memory@80000000 { 520 device_type = "memory"; 521 /* We expect the bootloader to fill in the size */ 522 reg = <0x0 0x80000000 0x0 0x0>; 523 }; 524 525 pmu { 526 compatible = "arm,armv8-pmuv3"; 527 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; 528 }; 529 530 psci { 531 compatible = "arm,psci-1.0"; 532 method = "smc"; 533 534 CPU_PD0: power-domain-cpu0 { 535 #power-domain-cells = <0>; 536 power-domains = <&CLUSTER_PD>; 537 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 538 }; 539 540 CPU_PD1: power-domain-cpu1 { 541 #power-domain-cells = <0>; 542 power-domains = <&CLUSTER_PD>; 543 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 544 }; 545 546 CPU_PD2: power-domain-cpu2 { 547 #power-domain-cells = <0>; 548 power-domains = <&CLUSTER_PD>; 549 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 550 }; 551 552 CPU_PD3: power-domain-cpu3 { 553 #power-domain-cells = <0>; 554 power-domains = <&CLUSTER_PD>; 555 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 556 }; 557 558 CPU_PD4: power-domain-cpu4 { 559 #power-domain-cells = <0>; 560 power-domains = <&CLUSTER_PD>; 561 domain-idle-states = <&BIG_CPU_SLEEP_0>; 562 }; 563 564 CPU_PD5: power-domain-cpu5 { 565 #power-domain-cells = <0>; 566 power-domains = <&CLUSTER_PD>; 567 domain-idle-states = <&BIG_CPU_SLEEP_0>; 568 }; 569 570 CPU_PD6: power-domain-cpu6 { 571 #power-domain-cells = <0>; 572 power-domains = <&CLUSTER_PD>; 573 domain-idle-states = <&BIG_CPU_SLEEP_0>; 574 }; 575 576 CPU_PD7: power-domain-cpu7 { 577 #power-domain-cells = <0>; 578 power-domains = <&CLUSTER_PD>; 579 domain-idle-states = <&BIG_CPU_SLEEP_0>; 580 }; 581 582 CLUSTER_PD: power-domain-cpu-cluster0 { 583 #power-domain-cells = <0>; 584 domain-idle-states = <&CLUSTER_SLEEP_0>; 585 }; 586 }; 587 588 reserved-memory { 589 #address-cells = <2>; 590 #size-cells = <2>; 591 ranges; 592 593 hyp_mem: hyp@85700000 { 594 reg = <0x0 0x85700000 0x0 0x600000>; 595 no-map; 596 }; 597 598 xbl_mem: xbl@85d00000 { 599 reg = <0x0 0x85d00000 0x0 0x140000>; 600 no-map; 601 }; 602 603 aop_mem: aop@85f00000 { 604 reg = <0x0 0x85f00000 0x0 0x20000>; 605 no-map; 606 }; 607 608 aop_cmd_db: cmd-db@85f20000 { 609 compatible = "qcom,cmd-db"; 610 reg = <0x0 0x85f20000 0x0 0x20000>; 611 no-map; 612 }; 613 614 reserved@85f40000 { 615 reg = <0x0 0x85f40000 0x0 0x10000>; 616 no-map; 617 }; 618 619 smem_mem: smem@86000000 { 620 compatible = "qcom,smem"; 621 reg = <0x0 0x86000000 0x0 0x200000>; 622 no-map; 623 hwlocks = <&tcsr_mutex 3>; 624 }; 625 626 reserved@86200000 { 627 reg = <0x0 0x86200000 0x0 0x3900000>; 628 no-map; 629 }; 630 631 reserved@89b00000 { 632 reg = <0x0 0x89b00000 0x0 0x1c00000>; 633 no-map; 634 }; 635 636 reserved@9d400000 { 637 reg = <0x0 0x9d400000 0x0 0x1000000>; 638 no-map; 639 }; 640 641 reserved@9e400000 { 642 reg = <0x0 0x9e400000 0x0 0x1400000>; 643 no-map; 644 }; 645 646 reserved@9f800000 { 647 reg = <0x0 0x9f800000 0x0 0x800000>; 648 no-map; 649 }; 650 }; 651 652 smp2p-cdsp { 653 compatible = "qcom,smp2p"; 654 qcom,smem = <94>, <432>; 655 656 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; 657 658 mboxes = <&apss_shared 6>; 659 660 qcom,local-pid = <0>; 661 qcom,remote-pid = <5>; 662 663 cdsp_smp2p_out: master-kernel { 664 qcom,entry-name = "master-kernel"; 665 #qcom,smem-state-cells = <1>; 666 }; 667 668 cdsp_smp2p_in: slave-kernel { 669 qcom,entry-name = "slave-kernel"; 670 671 interrupt-controller; 672 #interrupt-cells = <2>; 673 }; 674 }; 675 676 smp2p-lpass { 677 compatible = "qcom,smp2p"; 678 qcom,smem = <443>, <429>; 679 680 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 681 682 mboxes = <&apss_shared 10>; 683 684 qcom,local-pid = <0>; 685 qcom,remote-pid = <2>; 686 687 adsp_smp2p_out: master-kernel { 688 qcom,entry-name = "master-kernel"; 689 #qcom,smem-state-cells = <1>; 690 }; 691 692 adsp_smp2p_in: slave-kernel { 693 qcom,entry-name = "slave-kernel"; 694 695 interrupt-controller; 696 #interrupt-cells = <2>; 697 }; 698 }; 699 700 smp2p-mpss { 701 compatible = "qcom,smp2p"; 702 qcom,smem = <435>, <428>; 703 704 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 705 706 mboxes = <&apss_shared 14>; 707 708 qcom,local-pid = <0>; 709 qcom,remote-pid = <1>; 710 711 modem_smp2p_out: master-kernel { 712 qcom,entry-name = "master-kernel"; 713 #qcom,smem-state-cells = <1>; 714 }; 715 716 modem_smp2p_in: slave-kernel { 717 qcom,entry-name = "slave-kernel"; 718 719 interrupt-controller; 720 #interrupt-cells = <2>; 721 }; 722 723 modem_smp2p_ipa_out: ipa-ap-to-modem { 724 qcom,entry-name = "ipa"; 725 #qcom,smem-state-cells = <1>; 726 }; 727 728 modem_smp2p_ipa_in: ipa-modem-to-ap { 729 qcom,entry-name = "ipa"; 730 interrupt-controller; 731 #interrupt-cells = <2>; 732 }; 733 734 modem_smp2p_wlan_in: wlan-wpss-to-ap { 735 qcom,entry-name = "wlan"; 736 interrupt-controller; 737 #interrupt-cells = <2>; 738 }; 739 }; 740 741 smp2p-slpi { 742 compatible = "qcom,smp2p"; 743 qcom,smem = <481>, <430>; 744 745 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>; 746 747 mboxes = <&apss_shared 26>; 748 749 qcom,local-pid = <0>; 750 qcom,remote-pid = <3>; 751 752 slpi_smp2p_out: master-kernel { 753 qcom,entry-name = "master-kernel"; 754 #qcom,smem-state-cells = <1>; 755 }; 756 757 slpi_smp2p_in: slave-kernel { 758 qcom,entry-name = "slave-kernel"; 759 760 interrupt-controller; 761 #interrupt-cells = <2>; 762 }; 763 }; 764 765 soc: soc@0 { 766 compatible = "simple-bus"; 767 #address-cells = <2>; 768 #size-cells = <2>; 769 ranges = <0 0 0 0 0x10 0>; 770 dma-ranges = <0 0 0 0 0x10 0>; 771 772 gcc: clock-controller@100000 { 773 compatible = "qcom,gcc-sc8180x"; 774 reg = <0x0 0x00100000 0x0 0x1f0000>; 775 #clock-cells = <1>; 776 #reset-cells = <1>; 777 #power-domain-cells = <1>; 778 clocks = <&rpmhcc RPMH_CXO_CLK>, 779 <&rpmhcc RPMH_CXO_CLK_A>, 780 <&sleep_clk>; 781 clock-names = "bi_tcxo", 782 "bi_tcxo_ao", 783 "sleep_clk"; 784 }; 785 786 qupv3_id_0: geniqup@8c0000 { 787 compatible = "qcom,geni-se-qup"; 788 reg = <0 0x008c0000 0 0x6000>; 789 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 790 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 791 clock-names = "m-ahb", "s-ahb"; 792 #address-cells = <2>; 793 #size-cells = <2>; 794 ranges; 795 iommus = <&apps_smmu 0x4c3 0>; 796 status = "disabled"; 797 798 i2c0: i2c@880000 { 799 compatible = "qcom,geni-i2c"; 800 reg = <0 0x00880000 0 0x4000>; 801 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 802 clock-names = "se"; 803 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 804 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 805 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 806 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 807 interconnect-names = "qup-core", "qup-config", "qup-memory"; 808 #address-cells = <1>; 809 #size-cells = <0>; 810 status = "disabled"; 811 }; 812 813 spi0: spi@880000 { 814 compatible = "qcom,geni-spi"; 815 reg = <0 0x00880000 0 0x4000>; 816 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 817 clock-names = "se"; 818 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 819 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 820 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 821 interconnect-names = "qup-core", "qup-config"; 822 #address-cells = <1>; 823 #size-cells = <0>; 824 status = "disabled"; 825 }; 826 827 uart0: serial@880000 { 828 compatible = "qcom,geni-uart"; 829 reg = <0 0x00880000 0 0x4000>; 830 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 831 clock-names = "se"; 832 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 833 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 834 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 835 interconnect-names = "qup-core", "qup-config"; 836 status = "disabled"; 837 }; 838 839 i2c1: i2c@884000 { 840 compatible = "qcom,geni-i2c"; 841 reg = <0 0x00884000 0 0x4000>; 842 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 843 clock-names = "se"; 844 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 845 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 846 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 847 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 848 interconnect-names = "qup-core", "qup-config", "qup-memory"; 849 #address-cells = <1>; 850 #size-cells = <0>; 851 status = "disabled"; 852 }; 853 854 spi1: spi@884000 { 855 compatible = "qcom,geni-spi"; 856 reg = <0 0x00884000 0 0x4000>; 857 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 858 clock-names = "se"; 859 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 860 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 861 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 862 interconnect-names = "qup-core", "qup-config"; 863 #address-cells = <1>; 864 #size-cells = <0>; 865 status = "disabled"; 866 }; 867 868 uart1: serial@884000 { 869 compatible = "qcom,geni-uart"; 870 reg = <0 0x00884000 0 0x4000>; 871 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 872 clock-names = "se"; 873 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 874 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 875 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 876 interconnect-names = "qup-core", "qup-config"; 877 status = "disabled"; 878 }; 879 880 i2c2: i2c@888000 { 881 compatible = "qcom,geni-i2c"; 882 reg = <0 0x00888000 0 0x4000>; 883 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 884 clock-names = "se"; 885 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 886 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 887 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 888 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 889 interconnect-names = "qup-core", "qup-config", "qup-memory"; 890 #address-cells = <1>; 891 #size-cells = <0>; 892 status = "disabled"; 893 }; 894 895 spi2: spi@888000 { 896 compatible = "qcom,geni-spi"; 897 reg = <0 0x00888000 0 0x4000>; 898 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 899 clock-names = "se"; 900 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 901 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 902 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 903 interconnect-names = "qup-core", "qup-config"; 904 #address-cells = <1>; 905 #size-cells = <0>; 906 status = "disabled"; 907 }; 908 909 uart2: serial@888000 { 910 compatible = "qcom,geni-uart"; 911 reg = <0 0x00888000 0 0x4000>; 912 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 913 clock-names = "se"; 914 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 915 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 916 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 917 interconnect-names = "qup-core", "qup-config"; 918 status = "disabled"; 919 }; 920 921 i2c3: i2c@88c000 { 922 compatible = "qcom,geni-i2c"; 923 reg = <0 0x0088c000 0 0x4000>; 924 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 925 clock-names = "se"; 926 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 927 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 928 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 929 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 930 interconnect-names = "qup-core", "qup-config", "qup-memory"; 931 #address-cells = <1>; 932 #size-cells = <0>; 933 status = "disabled"; 934 }; 935 936 spi3: spi@88c000 { 937 compatible = "qcom,geni-spi"; 938 reg = <0 0x0088c000 0 0x4000>; 939 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 940 clock-names = "se"; 941 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 942 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 943 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 944 interconnect-names = "qup-core", "qup-config"; 945 #address-cells = <1>; 946 #size-cells = <0>; 947 status = "disabled"; 948 }; 949 950 uart3: serial@88c000 { 951 compatible = "qcom,geni-uart"; 952 reg = <0 0x0088c000 0 0x4000>; 953 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 954 clock-names = "se"; 955 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 956 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 957 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 958 interconnect-names = "qup-core", "qup-config"; 959 status = "disabled"; 960 }; 961 962 i2c4: i2c@890000 { 963 compatible = "qcom,geni-i2c"; 964 reg = <0 0x00890000 0 0x4000>; 965 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 966 clock-names = "se"; 967 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 968 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 969 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 970 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 971 interconnect-names = "qup-core", "qup-config", "qup-memory"; 972 #address-cells = <1>; 973 #size-cells = <0>; 974 status = "disabled"; 975 }; 976 977 spi4: spi@890000 { 978 compatible = "qcom,geni-spi"; 979 reg = <0 0x00890000 0 0x4000>; 980 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 981 clock-names = "se"; 982 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 983 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 984 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 985 interconnect-names = "qup-core", "qup-config"; 986 #address-cells = <1>; 987 #size-cells = <0>; 988 status = "disabled"; 989 }; 990 991 uart4: serial@890000 { 992 compatible = "qcom,geni-uart"; 993 reg = <0 0x00890000 0 0x4000>; 994 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 995 clock-names = "se"; 996 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 997 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 998 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 999 interconnect-names = "qup-core", "qup-config"; 1000 status = "disabled"; 1001 }; 1002 1003 i2c5: i2c@894000 { 1004 compatible = "qcom,geni-i2c"; 1005 reg = <0 0x00894000 0 0x4000>; 1006 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1007 clock-names = "se"; 1008 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1009 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1010 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1011 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1012 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1013 #address-cells = <1>; 1014 #size-cells = <0>; 1015 status = "disabled"; 1016 }; 1017 1018 spi5: spi@894000 { 1019 compatible = "qcom,geni-spi"; 1020 reg = <0 0x00894000 0 0x4000>; 1021 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1022 clock-names = "se"; 1023 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1024 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1025 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 1026 interconnect-names = "qup-core", "qup-config"; 1027 #address-cells = <1>; 1028 #size-cells = <0>; 1029 status = "disabled"; 1030 }; 1031 1032 uart5: serial@894000 { 1033 compatible = "qcom,geni-uart"; 1034 reg = <0 0x00894000 0 0x4000>; 1035 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1036 clock-names = "se"; 1037 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1038 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1039 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 1040 interconnect-names = "qup-core", "qup-config"; 1041 status = "disabled"; 1042 }; 1043 1044 i2c6: i2c@898000 { 1045 compatible = "qcom,geni-i2c"; 1046 reg = <0 0x00898000 0 0x4000>; 1047 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1048 clock-names = "se"; 1049 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1050 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1051 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1052 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1053 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1054 #address-cells = <1>; 1055 #size-cells = <0>; 1056 status = "disabled"; 1057 }; 1058 1059 spi6: spi@898000 { 1060 compatible = "qcom,geni-spi"; 1061 reg = <0 0x00898000 0 0x4000>; 1062 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1063 clock-names = "se"; 1064 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1065 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1066 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 1067 interconnect-names = "qup-core", "qup-config"; 1068 #address-cells = <1>; 1069 #size-cells = <0>; 1070 status = "disabled"; 1071 }; 1072 1073 uart6: serial@898000 { 1074 compatible = "qcom,geni-uart"; 1075 reg = <0 0x00898000 0 0x4000>; 1076 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1077 clock-names = "se"; 1078 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1079 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1080 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 1081 interconnect-names = "qup-core", "qup-config"; 1082 status = "disabled"; 1083 }; 1084 1085 i2c7: i2c@89c000 { 1086 compatible = "qcom,geni-i2c"; 1087 reg = <0 0x0089c000 0 0x4000>; 1088 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1089 clock-names = "se"; 1090 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1091 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1092 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1093 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1094 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1095 #address-cells = <1>; 1096 #size-cells = <0>; 1097 status = "disabled"; 1098 }; 1099 1100 spi7: spi@89c000 { 1101 compatible = "qcom,geni-spi"; 1102 reg = <0 0x0089c000 0 0x4000>; 1103 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1104 clock-names = "se"; 1105 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1106 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1107 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 1108 interconnect-names = "qup-core", "qup-config"; 1109 #address-cells = <1>; 1110 #size-cells = <0>; 1111 status = "disabled"; 1112 }; 1113 1114 uart7: serial@89c000 { 1115 compatible = "qcom,geni-uart"; 1116 reg = <0 0x0089c000 0 0x4000>; 1117 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1118 clock-names = "se"; 1119 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1120 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1121 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 1122 interconnect-names = "qup-core", "qup-config"; 1123 status = "disabled"; 1124 }; 1125 }; 1126 1127 qupv3_id_1: geniqup@ac0000 { 1128 compatible = "qcom,geni-se-qup"; 1129 reg = <0x0 0x00ac0000 0x0 0x6000>; 1130 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1131 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1132 clock-names = "m-ahb", "s-ahb"; 1133 #address-cells = <2>; 1134 #size-cells = <2>; 1135 ranges; 1136 iommus = <&apps_smmu 0x603 0>; 1137 status = "disabled"; 1138 1139 i2c8: i2c@a80000 { 1140 compatible = "qcom,geni-i2c"; 1141 reg = <0 0x00a80000 0 0x4000>; 1142 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1143 clock-names = "se"; 1144 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1145 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1146 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1147 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1148 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1149 #address-cells = <1>; 1150 #size-cells = <0>; 1151 status = "disabled"; 1152 }; 1153 1154 spi8: spi@a80000 { 1155 compatible = "qcom,geni-spi"; 1156 reg = <0 0x00a80000 0 0x4000>; 1157 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1158 clock-names = "se"; 1159 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1160 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1161 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1162 interconnect-names = "qup-core", "qup-config"; 1163 #address-cells = <1>; 1164 #size-cells = <0>; 1165 status = "disabled"; 1166 }; 1167 1168 uart8: serial@a80000 { 1169 compatible = "qcom,geni-uart"; 1170 reg = <0 0x00a80000 0 0x4000>; 1171 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1172 clock-names = "se"; 1173 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1174 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1175 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1176 interconnect-names = "qup-core", "qup-config"; 1177 status = "disabled"; 1178 }; 1179 1180 i2c9: i2c@a84000 { 1181 compatible = "qcom,geni-i2c"; 1182 reg = <0 0x00a84000 0 0x4000>; 1183 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1184 clock-names = "se"; 1185 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1186 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1187 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1188 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1189 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1190 #address-cells = <1>; 1191 #size-cells = <0>; 1192 status = "disabled"; 1193 }; 1194 1195 spi9: spi@a84000 { 1196 compatible = "qcom,geni-spi"; 1197 reg = <0 0x00a84000 0 0x4000>; 1198 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1199 clock-names = "se"; 1200 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1201 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1202 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1203 interconnect-names = "qup-core", "qup-config"; 1204 #address-cells = <1>; 1205 #size-cells = <0>; 1206 status = "disabled"; 1207 }; 1208 1209 uart9: serial@a84000 { 1210 compatible = "qcom,geni-debug-uart"; 1211 reg = <0 0x00a84000 0 0x4000>; 1212 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1213 clock-names = "se"; 1214 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1215 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1216 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1217 interconnect-names = "qup-core", "qup-config"; 1218 status = "disabled"; 1219 }; 1220 1221 i2c10: i2c@a88000 { 1222 compatible = "qcom,geni-i2c"; 1223 reg = <0 0x00a88000 0 0x4000>; 1224 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1225 clock-names = "se"; 1226 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1227 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1228 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1229 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1230 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1231 #address-cells = <1>; 1232 #size-cells = <0>; 1233 status = "disabled"; 1234 }; 1235 1236 spi10: spi@a88000 { 1237 compatible = "qcom,geni-spi"; 1238 reg = <0 0x00a88000 0 0x4000>; 1239 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1240 clock-names = "se"; 1241 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1242 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1243 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1244 interconnect-names = "qup-core", "qup-config"; 1245 #address-cells = <1>; 1246 #size-cells = <0>; 1247 status = "disabled"; 1248 }; 1249 1250 uart10: serial@a88000 { 1251 compatible = "qcom,geni-uart"; 1252 reg = <0 0x00a88000 0 0x4000>; 1253 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1254 clock-names = "se"; 1255 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1256 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1257 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1258 interconnect-names = "qup-core", "qup-config"; 1259 status = "disabled"; 1260 }; 1261 1262 i2c11: i2c@a8c000 { 1263 compatible = "qcom,geni-i2c"; 1264 reg = <0 0x00a8c000 0 0x4000>; 1265 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1266 clock-names = "se"; 1267 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1268 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1269 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1270 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1271 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1272 #address-cells = <1>; 1273 #size-cells = <0>; 1274 status = "disabled"; 1275 }; 1276 1277 spi11: spi@a8c000 { 1278 compatible = "qcom,geni-spi"; 1279 reg = <0 0x00a8c000 0 0x4000>; 1280 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1281 clock-names = "se"; 1282 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1283 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1284 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1285 interconnect-names = "qup-core", "qup-config"; 1286 #address-cells = <1>; 1287 #size-cells = <0>; 1288 status = "disabled"; 1289 }; 1290 1291 uart11: serial@a8c000 { 1292 compatible = "qcom,geni-uart"; 1293 reg = <0 0x00a8c000 0 0x4000>; 1294 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1295 clock-names = "se"; 1296 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1297 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1298 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1299 interconnect-names = "qup-core", "qup-config"; 1300 status = "disabled"; 1301 }; 1302 1303 i2c12: i2c@a90000 { 1304 compatible = "qcom,geni-i2c"; 1305 reg = <0 0x00a90000 0 0x4000>; 1306 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1307 clock-names = "se"; 1308 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1309 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1310 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1311 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1312 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1313 #address-cells = <1>; 1314 #size-cells = <0>; 1315 status = "disabled"; 1316 }; 1317 1318 spi12: spi@a90000 { 1319 compatible = "qcom,geni-spi"; 1320 reg = <0 0x00a90000 0 0x4000>; 1321 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1322 clock-names = "se"; 1323 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1324 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1325 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1326 interconnect-names = "qup-core", "qup-config"; 1327 #address-cells = <1>; 1328 #size-cells = <0>; 1329 status = "disabled"; 1330 }; 1331 1332 uart12: serial@a90000 { 1333 compatible = "qcom,geni-uart"; 1334 reg = <0 0x00a90000 0 0x4000>; 1335 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1336 clock-names = "se"; 1337 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1338 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1339 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1340 interconnect-names = "qup-core", "qup-config"; 1341 status = "disabled"; 1342 }; 1343 1344 i2c16: i2c@a94000 { 1345 compatible = "qcom,geni-i2c"; 1346 reg = <0 0x00a94000 0 0x4000>; 1347 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1348 clock-names = "se"; 1349 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1350 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1351 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1352 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1353 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1354 #address-cells = <1>; 1355 #size-cells = <0>; 1356 status = "disabled"; 1357 }; 1358 1359 spi16: spi@a94000 { 1360 compatible = "qcom,geni-spi"; 1361 reg = <0 0x00a94000 0 0x4000>; 1362 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1363 clock-names = "se"; 1364 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1365 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1366 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1367 interconnect-names = "qup-core", "qup-config"; 1368 #address-cells = <1>; 1369 #size-cells = <0>; 1370 status = "disabled"; 1371 }; 1372 1373 uart16: serial@a94000 { 1374 compatible = "qcom,geni-uart"; 1375 reg = <0 0x00a94000 0 0x4000>; 1376 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1377 clock-names = "se"; 1378 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1379 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1380 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1381 interconnect-names = "qup-core", "qup-config"; 1382 status = "disabled"; 1383 }; 1384 }; 1385 1386 qupv3_id_2: geniqup@cc0000 { 1387 compatible = "qcom,geni-se-qup"; 1388 reg = <0x0 0x00cc0000 0x0 0x6000>; 1389 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 1390 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 1391 clock-names = "m-ahb", "s-ahb"; 1392 #address-cells = <2>; 1393 #size-cells = <2>; 1394 ranges; 1395 iommus = <&apps_smmu 0x7a3 0>; 1396 status = "disabled"; 1397 1398 i2c17: i2c@c80000 { 1399 compatible = "qcom,geni-i2c"; 1400 reg = <0 0x00c80000 0 0x4000>; 1401 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1402 clock-names = "se"; 1403 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1404 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1405 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1406 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1407 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1408 #address-cells = <1>; 1409 #size-cells = <0>; 1410 status = "disabled"; 1411 }; 1412 1413 spi17: spi@c80000 { 1414 compatible = "qcom,geni-spi"; 1415 reg = <0 0x00c80000 0 0x4000>; 1416 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1417 clock-names = "se"; 1418 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1419 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1420 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1421 interconnect-names = "qup-core", "qup-config"; 1422 #address-cells = <1>; 1423 #size-cells = <0>; 1424 status = "disabled"; 1425 }; 1426 1427 uart17: serial@c80000 { 1428 compatible = "qcom,geni-uart"; 1429 reg = <0 0x00c80000 0 0x4000>; 1430 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1431 clock-names = "se"; 1432 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1433 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1434 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1435 interconnect-names = "qup-core", "qup-config"; 1436 status = "disabled"; 1437 }; 1438 1439 i2c18: i2c@c84000 { 1440 compatible = "qcom,geni-i2c"; 1441 reg = <0 0x00c84000 0 0x4000>; 1442 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1443 clock-names = "se"; 1444 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1445 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1446 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1447 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1448 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1449 #address-cells = <1>; 1450 #size-cells = <0>; 1451 status = "disabled"; 1452 }; 1453 1454 spi18: spi@c84000 { 1455 compatible = "qcom,geni-spi"; 1456 reg = <0 0x00c84000 0 0x4000>; 1457 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1458 clock-names = "se"; 1459 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1460 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1461 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1462 interconnect-names = "qup-core", "qup-config"; 1463 #address-cells = <1>; 1464 #size-cells = <0>; 1465 status = "disabled"; 1466 }; 1467 1468 uart18: serial@c84000 { 1469 compatible = "qcom,geni-uart"; 1470 reg = <0 0x00c84000 0 0x4000>; 1471 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1472 clock-names = "se"; 1473 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1474 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1475 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1476 interconnect-names = "qup-core", "qup-config"; 1477 status = "disabled"; 1478 }; 1479 1480 i2c19: i2c@c88000 { 1481 compatible = "qcom,geni-i2c"; 1482 reg = <0 0x00c88000 0 0x4000>; 1483 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1484 clock-names = "se"; 1485 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1486 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1487 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1488 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1489 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1490 #address-cells = <1>; 1491 #size-cells = <0>; 1492 status = "disabled"; 1493 }; 1494 1495 spi19: spi@c88000 { 1496 compatible = "qcom,geni-spi"; 1497 reg = <0 0x00c88000 0 0x4000>; 1498 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1499 clock-names = "se"; 1500 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1501 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1502 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1503 interconnect-names = "qup-core", "qup-config"; 1504 #address-cells = <1>; 1505 #size-cells = <0>; 1506 status = "disabled"; 1507 }; 1508 1509 uart19: serial@c88000 { 1510 compatible = "qcom,geni-uart"; 1511 reg = <0 0x00c88000 0 0x4000>; 1512 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1513 clock-names = "se"; 1514 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1515 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1516 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1517 interconnect-names = "qup-core", "qup-config"; 1518 status = "disabled"; 1519 }; 1520 1521 i2c13: i2c@c8c000 { 1522 compatible = "qcom,geni-i2c"; 1523 reg = <0 0x00c8c000 0 0x4000>; 1524 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1525 clock-names = "se"; 1526 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1527 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1528 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1529 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1530 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1531 #address-cells = <1>; 1532 #size-cells = <0>; 1533 status = "disabled"; 1534 }; 1535 1536 spi13: spi@c8c000 { 1537 compatible = "qcom,geni-spi"; 1538 reg = <0 0x00c8c000 0 0x4000>; 1539 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1540 clock-names = "se"; 1541 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1542 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1543 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1544 interconnect-names = "qup-core", "qup-config"; 1545 #address-cells = <1>; 1546 #size-cells = <0>; 1547 status = "disabled"; 1548 }; 1549 1550 uart13: serial@c8c000 { 1551 compatible = "qcom,geni-uart"; 1552 reg = <0 0x00c8c000 0 0x4000>; 1553 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1554 clock-names = "se"; 1555 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1556 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1557 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1558 interconnect-names = "qup-core", "qup-config"; 1559 status = "disabled"; 1560 }; 1561 1562 i2c14: i2c@c90000 { 1563 compatible = "qcom,geni-i2c"; 1564 reg = <0 0x00c90000 0 0x4000>; 1565 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1566 clock-names = "se"; 1567 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1568 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1569 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1570 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1571 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1572 #address-cells = <1>; 1573 #size-cells = <0>; 1574 status = "disabled"; 1575 }; 1576 1577 spi14: spi@c90000 { 1578 compatible = "qcom,geni-spi"; 1579 reg = <0 0x00c90000 0 0x4000>; 1580 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1581 clock-names = "se"; 1582 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1583 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1584 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1585 interconnect-names = "qup-core", "qup-config"; 1586 #address-cells = <1>; 1587 #size-cells = <0>; 1588 status = "disabled"; 1589 }; 1590 1591 uart14: serial@c90000 { 1592 compatible = "qcom,geni-uart"; 1593 reg = <0 0x00c90000 0 0x4000>; 1594 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1595 clock-names = "se"; 1596 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1597 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1598 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1599 interconnect-names = "qup-core", "qup-config"; 1600 status = "disabled"; 1601 }; 1602 1603 i2c15: i2c@c94000 { 1604 compatible = "qcom,geni-i2c"; 1605 reg = <0 0x00c94000 0 0x4000>; 1606 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1607 clock-names = "se"; 1608 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1609 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1610 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1611 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1612 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1613 #address-cells = <1>; 1614 #size-cells = <0>; 1615 status = "disabled"; 1616 }; 1617 1618 spi15: spi@c94000 { 1619 compatible = "qcom,geni-spi"; 1620 reg = <0 0x00c94000 0 0x4000>; 1621 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1622 clock-names = "se"; 1623 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1624 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1625 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1626 interconnect-names = "qup-core", "qup-config"; 1627 #address-cells = <1>; 1628 #size-cells = <0>; 1629 status = "disabled"; 1630 }; 1631 1632 uart15: serial@c94000 { 1633 compatible = "qcom,geni-uart"; 1634 reg = <0 0x00c94000 0 0x4000>; 1635 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1636 clock-names = "se"; 1637 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1638 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1639 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1640 interconnect-names = "qup-core", "qup-config"; 1641 status = "disabled"; 1642 }; 1643 }; 1644 1645 config_noc: interconnect@1500000 { 1646 compatible = "qcom,sc8180x-config-noc"; 1647 reg = <0 0x01500000 0 0x7400>; 1648 #interconnect-cells = <2>; 1649 qcom,bcm-voters = <&apps_bcm_voter>; 1650 }; 1651 1652 system_noc: interconnect@1620000 { 1653 compatible = "qcom,sc8180x-system-noc"; 1654 reg = <0 0x01620000 0 0x19400>; 1655 #interconnect-cells = <2>; 1656 qcom,bcm-voters = <&apps_bcm_voter>; 1657 }; 1658 1659 aggre1_noc: interconnect@16e0000 { 1660 compatible = "qcom,sc8180x-aggre1-noc"; 1661 reg = <0 0x016e0000 0 0xd080>; 1662 #interconnect-cells = <2>; 1663 qcom,bcm-voters = <&apps_bcm_voter>; 1664 }; 1665 1666 aggre2_noc: interconnect@1700000 { 1667 compatible = "qcom,sc8180x-aggre2-noc"; 1668 reg = <0 0x01700000 0 0x20000>; 1669 #interconnect-cells = <2>; 1670 qcom,bcm-voters = <&apps_bcm_voter>; 1671 }; 1672 1673 compute_noc: interconnect@1720000 { 1674 compatible = "qcom,sc8180x-compute-noc"; 1675 reg = <0 0x01720000 0 0x7000>; 1676 #interconnect-cells = <2>; 1677 qcom,bcm-voters = <&apps_bcm_voter>; 1678 }; 1679 1680 mmss_noc: interconnect@1740000 { 1681 compatible = "qcom,sc8180x-mmss-noc"; 1682 reg = <0 0x01740000 0 0x1c100>; 1683 #interconnect-cells = <2>; 1684 qcom,bcm-voters = <&apps_bcm_voter>; 1685 }; 1686 1687 pcie0: pci@1c00000 { 1688 compatible = "qcom,pcie-sc8180x"; 1689 reg = <0 0x01c00000 0 0x3000>, 1690 <0 0x60000000 0 0xf1d>, 1691 <0 0x60000f20 0 0xa8>, 1692 <0 0x60001000 0 0x1000>, 1693 <0 0x60100000 0 0x100000>; 1694 reg-names = "parf", 1695 "dbi", 1696 "elbi", 1697 "atu", 1698 "config"; 1699 device_type = "pci"; 1700 linux,pci-domain = <0>; 1701 bus-range = <0x00 0xff>; 1702 num-lanes = <2>; 1703 1704 #address-cells = <3>; 1705 #size-cells = <2>; 1706 1707 ranges = <0x01000000 0x0 0x60200000 0x0 0x60200000 0x0 0x100000>, 1708 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; 1709 1710 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 1711 interrupt-names = "msi"; 1712 #interrupt-cells = <1>; 1713 interrupt-map-mask = <0 0 0 0x7>; 1714 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1715 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1716 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1717 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1718 1719 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1720 <&gcc GCC_PCIE_0_AUX_CLK>, 1721 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1722 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1723 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1724 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1725 <&gcc GCC_PCIE_0_CLKREF_CLK>, 1726 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; 1727 clock-names = "pipe", 1728 "aux", 1729 "cfg", 1730 "bus_master", 1731 "bus_slave", 1732 "slave_q2a", 1733 "ref", 1734 "tbu"; 1735 1736 assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>; 1737 assigned-clock-rates = <19200000>; 1738 1739 iommus = <&apps_smmu 0x1d80 0x7f>; 1740 iommu-map = <0x0 &apps_smmu 0x1d80 0x1>, 1741 <0x100 &apps_smmu 0x1d81 0x1>; 1742 1743 resets = <&gcc GCC_PCIE_0_BCR>; 1744 reset-names = "pci"; 1745 1746 power-domains = <&gcc PCIE_0_GDSC>; 1747 1748 interconnects = <&aggre2_noc MASTER_PCIE 0 &mc_virt SLAVE_EBI_CH0 0>, 1749 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>; 1750 interconnect-names = "pcie-mem", "cpu-pcie"; 1751 1752 phys = <&pcie0_phy>; 1753 phy-names = "pciephy"; 1754 dma-coherent; 1755 1756 status = "disabled"; 1757 }; 1758 1759 pcie0_phy: phy@1c06000 { 1760 compatible = "qcom,sc8180x-qmp-pcie-phy"; 1761 reg = <0 0x01c06000 0 0x1000>; 1762 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1763 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1764 <&gcc GCC_PCIE_0_CLKREF_CLK>, 1765 <&gcc GCC_PCIE0_PHY_REFGEN_CLK>, 1766 <&gcc GCC_PCIE_0_PIPE_CLK>; 1767 clock-names = "aux", 1768 "cfg_ahb", 1769 "ref", 1770 "refgen", 1771 "pipe"; 1772 #clock-cells = <0>; 1773 clock-output-names = "pcie_0_pipe_clk"; 1774 #phy-cells = <0>; 1775 1776 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1777 reset-names = "phy"; 1778 1779 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; 1780 assigned-clock-rates = <100000000>; 1781 1782 status = "disabled"; 1783 }; 1784 1785 pcie3: pci@1c08000 { 1786 compatible = "qcom,pcie-sc8180x"; 1787 reg = <0 0x01c08000 0 0x3000>, 1788 <0 0x40000000 0 0xf1d>, 1789 <0 0x40000f20 0 0xa8>, 1790 <0 0x40001000 0 0x1000>, 1791 <0 0x40100000 0 0x100000>; 1792 reg-names = "parf", 1793 "dbi", 1794 "elbi", 1795 "atu", 1796 "config"; 1797 device_type = "pci"; 1798 linux,pci-domain = <3>; 1799 bus-range = <0x00 0xff>; 1800 num-lanes = <2>; 1801 1802 #address-cells = <3>; 1803 #size-cells = <2>; 1804 1805 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, 1806 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1807 1808 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 1809 interrupt-names = "msi"; 1810 #interrupt-cells = <1>; 1811 interrupt-map-mask = <0 0 0 0x7>; 1812 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1813 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1814 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1815 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1816 1817 clocks = <&gcc GCC_PCIE_3_PIPE_CLK>, 1818 <&gcc GCC_PCIE_3_AUX_CLK>, 1819 <&gcc GCC_PCIE_3_CFG_AHB_CLK>, 1820 <&gcc GCC_PCIE_3_MSTR_AXI_CLK>, 1821 <&gcc GCC_PCIE_3_SLV_AXI_CLK>, 1822 <&gcc GCC_PCIE_3_SLV_Q2A_AXI_CLK>, 1823 <&gcc GCC_PCIE_3_CLKREF_CLK>, 1824 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; 1825 clock-names = "pipe", 1826 "aux", 1827 "cfg", 1828 "bus_master", 1829 "bus_slave", 1830 "slave_q2a", 1831 "ref", 1832 "tbu"; 1833 1834 assigned-clocks = <&gcc GCC_PCIE_3_AUX_CLK>; 1835 assigned-clock-rates = <19200000>; 1836 1837 iommus = <&apps_smmu 0x1e00 0x7f>; 1838 iommu-map = <0x0 &apps_smmu 0x1e00 0x1>, 1839 <0x100 &apps_smmu 0x1e01 0x1>; 1840 1841 resets = <&gcc GCC_PCIE_3_BCR>; 1842 reset-names = "pci"; 1843 1844 power-domains = <&gcc PCIE_3_GDSC>; 1845 1846 interconnects = <&aggre2_noc MASTER_PCIE_3 0 &mc_virt SLAVE_EBI_CH0 0>, 1847 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>; 1848 interconnect-names = "pcie-mem", "cpu-pcie"; 1849 1850 phys = <&pcie3_phy>; 1851 phy-names = "pciephy"; 1852 dma-coherent; 1853 1854 status = "disabled"; 1855 }; 1856 1857 pcie3_phy: phy@1c0c000 { 1858 compatible = "qcom,sc8180x-qmp-pcie-phy"; 1859 reg = <0 0x01c0c000 0 0x1000>; 1860 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1861 <&gcc GCC_PCIE_3_CFG_AHB_CLK>, 1862 <&gcc GCC_PCIE_3_CLKREF_CLK>, 1863 <&gcc GCC_PCIE3_PHY_REFGEN_CLK>, 1864 <&gcc GCC_PCIE_3_PIPE_CLK>; 1865 clock-names = "aux", 1866 "cfg_ahb", 1867 "ref", 1868 "refgen", 1869 "pipe"; 1870 #clock-cells = <0>; 1871 clock-output-names = "pcie_3_pipe_clk"; 1872 1873 #phy-cells = <0>; 1874 1875 resets = <&gcc GCC_PCIE_3_PHY_BCR>; 1876 reset-names = "phy"; 1877 1878 assigned-clocks = <&gcc GCC_PCIE3_PHY_REFGEN_CLK>; 1879 assigned-clock-rates = <100000000>; 1880 1881 status = "disabled"; 1882 }; 1883 1884 pcie1: pci@1c10000 { 1885 compatible = "qcom,pcie-sc8180x"; 1886 reg = <0 0x01c10000 0 0x3000>, 1887 <0 0x68000000 0 0xf1d>, 1888 <0 0x68000f20 0 0xa8>, 1889 <0 0x68001000 0 0x1000>, 1890 <0 0x68100000 0 0x100000>; 1891 reg-names = "parf", 1892 "dbi", 1893 "elbi", 1894 "atu", 1895 "config"; 1896 device_type = "pci"; 1897 linux,pci-domain = <1>; 1898 bus-range = <0x00 0xff>; 1899 num-lanes = <2>; 1900 1901 #address-cells = <3>; 1902 #size-cells = <2>; 1903 1904 ranges = <0x01000000 0x0 0x68200000 0x0 0x68200000 0x0 0x100000>, 1905 <0x02000000 0x0 0x68300000 0x0 0x68300000 0x0 0x3d00000>; 1906 1907 interrupts = <GIC_SPI 755 IRQ_TYPE_LEVEL_HIGH>; 1908 interrupt-names = "msi"; 1909 #interrupt-cells = <1>; 1910 interrupt-map-mask = <0 0 0 0x7>; 1911 interrupt-map = <0 0 0 1 &intc 0 747 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1912 <0 0 0 2 &intc 0 746 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1913 <0 0 0 3 &intc 0 745 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1914 <0 0 0 4 &intc 0 744 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1915 1916 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1917 <&gcc GCC_PCIE_1_AUX_CLK>, 1918 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1919 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1920 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1921 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1922 <&gcc GCC_PCIE_1_CLKREF_CLK>, 1923 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; 1924 clock-names = "pipe", 1925 "aux", 1926 "cfg", 1927 "bus_master", 1928 "bus_slave", 1929 "slave_q2a", 1930 "ref", 1931 "tbu"; 1932 1933 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 1934 assigned-clock-rates = <19200000>; 1935 1936 iommus = <&apps_smmu 0x1c80 0x7f>; 1937 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 1938 <0x100 &apps_smmu 0x1c81 0x1>; 1939 1940 resets = <&gcc GCC_PCIE_1_BCR>; 1941 reset-names = "pci"; 1942 1943 power-domains = <&gcc PCIE_1_GDSC>; 1944 1945 interconnects = <&aggre2_noc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI_CH0 0>, 1946 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>; 1947 interconnect-names = "pcie-mem", "cpu-pcie"; 1948 1949 phys = <&pcie1_phy>; 1950 phy-names = "pciephy"; 1951 dma-coherent; 1952 1953 status = "disabled"; 1954 }; 1955 1956 pcie1_phy: phy@1c16000 { 1957 compatible = "qcom,sc8180x-qmp-pcie-phy"; 1958 reg = <0 0x01c16000 0 0x1000>; 1959 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1960 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1961 <&gcc GCC_PCIE_1_CLKREF_CLK>, 1962 <&gcc GCC_PCIE1_PHY_REFGEN_CLK>, 1963 <&gcc GCC_PCIE_1_PIPE_CLK>; 1964 clock-names = "aux", 1965 "cfg_ahb", 1966 "ref", 1967 "refgen", 1968 "pipe"; 1969 #clock-cells = <0>; 1970 clock-output-names = "pcie_1_pipe_clk"; 1971 1972 #phy-cells = <0>; 1973 1974 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 1975 reset-names = "phy"; 1976 1977 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; 1978 assigned-clock-rates = <100000000>; 1979 1980 status = "disabled"; 1981 }; 1982 1983 pcie2: pci@1c18000 { 1984 compatible = "qcom,pcie-sc8180x"; 1985 reg = <0 0x01c18000 0 0x3000>, 1986 <0 0x70000000 0 0xf1d>, 1987 <0 0x70000f20 0 0xa8>, 1988 <0 0x70001000 0 0x1000>, 1989 <0 0x70100000 0 0x100000>; 1990 reg-names = "parf", 1991 "dbi", 1992 "elbi", 1993 "atu", 1994 "config"; 1995 device_type = "pci"; 1996 linux,pci-domain = <2>; 1997 bus-range = <0x00 0xff>; 1998 num-lanes = <4>; 1999 2000 #address-cells = <3>; 2001 #size-cells = <2>; 2002 2003 ranges = <0x01000000 0x0 0x70200000 0x0 0x70200000 0x0 0x100000>, 2004 <0x02000000 0x0 0x70300000 0x0 0x70300000 0x0 0x3d00000>; 2005 2006 interrupts = <GIC_SPI 671 IRQ_TYPE_LEVEL_HIGH>; 2007 interrupt-names = "msi"; 2008 #interrupt-cells = <1>; 2009 interrupt-map-mask = <0 0 0 0x7>; 2010 interrupt-map = <0 0 0 1 &intc 0 663 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 2011 <0 0 0 2 &intc 0 662 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 2012 <0 0 0 3 &intc 0 661 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 2013 <0 0 0 4 &intc 0 660 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 2014 2015 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>, 2016 <&gcc GCC_PCIE_2_AUX_CLK>, 2017 <&gcc GCC_PCIE_2_CFG_AHB_CLK>, 2018 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>, 2019 <&gcc GCC_PCIE_2_SLV_AXI_CLK>, 2020 <&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>, 2021 <&gcc GCC_PCIE_2_CLKREF_CLK>, 2022 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; 2023 clock-names = "pipe", 2024 "aux", 2025 "cfg", 2026 "bus_master", 2027 "bus_slave", 2028 "slave_q2a", 2029 "ref", 2030 "tbu"; 2031 2032 assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>; 2033 assigned-clock-rates = <19200000>; 2034 2035 iommus = <&apps_smmu 0x1d00 0x7f>; 2036 iommu-map = <0x0 &apps_smmu 0x1d00 0x1>, 2037 <0x100 &apps_smmu 0x1d01 0x1>; 2038 2039 resets = <&gcc GCC_PCIE_2_BCR>; 2040 reset-names = "pci"; 2041 2042 power-domains = <&gcc PCIE_2_GDSC>; 2043 2044 interconnects = <&aggre2_noc MASTER_PCIE_2 0 &mc_virt SLAVE_EBI_CH0 0>, 2045 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>; 2046 interconnect-names = "pcie-mem", "cpu-pcie"; 2047 2048 phys = <&pcie2_phy>; 2049 phy-names = "pciephy"; 2050 dma-coherent; 2051 2052 status = "disabled"; 2053 }; 2054 2055 pcie2_phy: phy@1c1c000 { 2056 compatible = "qcom,sc8180x-qmp-pcie-phy"; 2057 reg = <0 0x01c1c000 0 0x1000>; 2058 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 2059 <&gcc GCC_PCIE_2_CFG_AHB_CLK>, 2060 <&gcc GCC_PCIE_2_CLKREF_CLK>, 2061 <&gcc GCC_PCIE2_PHY_REFGEN_CLK>, 2062 <&gcc GCC_PCIE_2_PIPE_CLK>; 2063 clock-names = "aux", 2064 "cfg_ahb", 2065 "ref", 2066 "refgen", 2067 "pipe"; 2068 #clock-cells = <0>; 2069 clock-output-names = "pcie_2_pipe_clk"; 2070 2071 #phy-cells = <0>; 2072 2073 resets = <&gcc GCC_PCIE_2_PHY_BCR>; 2074 reset-names = "phy"; 2075 2076 assigned-clocks = <&gcc GCC_PCIE2_PHY_REFGEN_CLK>; 2077 assigned-clock-rates = <100000000>; 2078 2079 status = "disabled"; 2080 }; 2081 2082 ufs_mem_hc: ufshc@1d84000 { 2083 compatible = "qcom,sc8180x-ufshc", "qcom,ufshc", 2084 "jedec,ufs-2.0"; 2085 reg = <0 0x01d84000 0 0x2500>; 2086 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2087 phys = <&ufs_mem_phy_lanes>; 2088 phy-names = "ufsphy"; 2089 lanes-per-direction = <2>; 2090 #reset-cells = <1>; 2091 resets = <&gcc GCC_UFS_PHY_BCR>; 2092 reset-names = "rst"; 2093 2094 iommus = <&apps_smmu 0x300 0>; 2095 2096 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 2097 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2098 <&gcc GCC_UFS_PHY_AHB_CLK>, 2099 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2100 <&rpmhcc RPMH_CXO_CLK>, 2101 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2102 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2103 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 2104 clock-names = "core_clk", 2105 "bus_aggr_clk", 2106 "iface_clk", 2107 "core_clk_unipro", 2108 "ref_clk", 2109 "tx_lane0_sync_clk", 2110 "rx_lane0_sync_clk", 2111 "rx_lane1_sync_clk"; 2112 freq-table-hz = <37500000 300000000>, 2113 <0 0>, 2114 <0 0>, 2115 <37500000 300000000>, 2116 <0 0>, 2117 <0 0>, 2118 <0 0>, 2119 <0 0>; 2120 2121 status = "disabled"; 2122 }; 2123 2124 ufs_mem_phy: phy-wrapper@1d87000 { 2125 compatible = "qcom,sc8180x-qmp-ufs-phy"; 2126 reg = <0 0x01d87000 0 0x1c0>; 2127 #address-cells = <2>; 2128 #size-cells = <2>; 2129 ranges; 2130 clocks = <&rpmhcc RPMH_CXO_CLK>, 2131 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 2132 clock-names = "ref", 2133 "ref_aux"; 2134 2135 resets = <&ufs_mem_hc 0>; 2136 reset-names = "ufsphy"; 2137 status = "disabled"; 2138 2139 ufs_mem_phy_lanes: phy@1d87400 { 2140 reg = <0 0x01d87400 0 0x108>, 2141 <0 0x01d87600 0 0x1e0>, 2142 <0 0x01d87c00 0 0x1dc>, 2143 <0 0x01d87800 0 0x108>, 2144 <0 0x01d87a00 0 0x1e0>; 2145 #phy-cells = <0>; 2146 }; 2147 }; 2148 2149 ipa_virt: interconnect@1e00000 { 2150 compatible = "qcom,sc8180x-ipa-virt"; 2151 reg = <0 0x01e00000 0 0x1000>; 2152 #interconnect-cells = <2>; 2153 qcom,bcm-voters = <&apps_bcm_voter>; 2154 }; 2155 2156 tcsr_mutex: hwlock@1f40000 { 2157 compatible = "qcom,tcsr-mutex"; 2158 reg = <0x0 0x01f40000 0x0 0x40000>; 2159 #hwlock-cells = <1>; 2160 }; 2161 2162 gpu: gpu@2c00000 { 2163 compatible = "qcom,adreno-680.1", "qcom,adreno"; 2164 #stream-id-cells = <16>; 2165 2166 reg = <0 0x02c00000 0 0x40000>; 2167 reg-names = "kgsl_3d0_reg_memory"; 2168 2169 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2170 2171 iommus = <&adreno_smmu 0 0xc01>; 2172 2173 operating-points-v2 = <&gpu_opp_table>; 2174 2175 interconnects = <&gem_noc MASTER_GRAPHICS_3D 0 &mc_virt SLAVE_EBI_CH0 0>; 2176 interconnect-names = "gfx-mem"; 2177 2178 qcom,gmu = <&gmu>; 2179 status = "disabled"; 2180 2181 gpu_opp_table: opp-table { 2182 compatible = "operating-points-v2"; 2183 2184 opp-514000000 { 2185 opp-hz = /bits/ 64 <514000000>; 2186 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 2187 }; 2188 2189 opp-500000000 { 2190 opp-hz = /bits/ 64 <500000000>; 2191 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2192 }; 2193 2194 opp-461000000 { 2195 opp-hz = /bits/ 64 <461000000>; 2196 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2197 }; 2198 2199 opp-405000000 { 2200 opp-hz = /bits/ 64 <405000000>; 2201 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2202 }; 2203 2204 opp-315000000 { 2205 opp-hz = /bits/ 64 <315000000>; 2206 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2207 }; 2208 2209 opp-256000000 { 2210 opp-hz = /bits/ 64 <256000000>; 2211 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2212 }; 2213 2214 opp-177000000 { 2215 opp-hz = /bits/ 64 <177000000>; 2216 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2217 }; 2218 }; 2219 }; 2220 2221 gmu: gmu@2c6a000 { 2222 compatible = "qcom,adreno-gmu-680.1", "qcom,adreno-gmu"; 2223 2224 reg = <0 0x02c6a000 0 0x30000>, 2225 <0 0x0b290000 0 0x10000>, 2226 <0 0x0b490000 0 0x10000>; 2227 reg-names = "gmu", 2228 "gmu_pdc", 2229 "gmu_pdc_seq"; 2230 2231 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2232 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2233 interrupt-names = "hfi", "gmu"; 2234 2235 clocks = <&gpucc GPU_CC_AHB_CLK>, 2236 <&gpucc GPU_CC_CX_GMU_CLK>, 2237 <&gpucc GPU_CC_CXO_CLK>, 2238 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2239 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 2240 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc"; 2241 2242 power-domains = <&gpucc GPU_CX_GDSC>, 2243 <&gpucc GPU_GX_GDSC>; 2244 power-domain-names = "cx", "gx"; 2245 2246 iommus = <&adreno_smmu 5 0xc00>; 2247 2248 operating-points-v2 = <&gmu_opp_table>; 2249 2250 gmu_opp_table: opp-table { 2251 compatible = "operating-points-v2"; 2252 2253 opp-200000000 { 2254 opp-hz = /bits/ 64 <200000000>; 2255 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2256 }; 2257 2258 opp-500000000 { 2259 opp-hz = /bits/ 64 <500000000>; 2260 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2261 }; 2262 }; 2263 }; 2264 2265 gpucc: clock-controller@2c90000 { 2266 compatible = "qcom,sc8180x-gpucc"; 2267 reg = <0 0x02c90000 0 0x9000>; 2268 clocks = <&rpmhcc RPMH_CXO_CLK>, 2269 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2270 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2271 clock-names = "bi_tcxo", 2272 "gcc_gpu_gpll0_clk_src", 2273 "gcc_gpu_gpll0_div_clk_src"; 2274 #clock-cells = <1>; 2275 #reset-cells = <1>; 2276 #power-domain-cells = <1>; 2277 }; 2278 2279 adreno_smmu: iommu@2ca0000 { 2280 compatible = "qcom,sc8180x-smmu-500", "qcom,adreno-smmu", 2281 "qcom,smmu-500", "arm,mmu-500"; 2282 reg = <0 0x02ca0000 0 0x10000>; 2283 #iommu-cells = <2>; 2284 #global-interrupts = <1>; 2285 interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>, 2286 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2287 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2288 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2289 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2290 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 2291 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 2292 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>, 2293 <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>; 2294 clocks = <&gpucc GPU_CC_AHB_CLK>, 2295 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2296 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 2297 clock-names = "ahb", "bus", "iface"; 2298 2299 power-domains = <&gpucc GPU_CX_GDSC>; 2300 }; 2301 2302 tlmm: pinctrl@3100000 { 2303 compatible = "qcom,sc8180x-tlmm"; 2304 reg = <0 0x03100000 0 0x300000>, 2305 <0 0x03500000 0 0x700000>, 2306 <0 0x03d00000 0 0x300000>; 2307 reg-names = "west", "east", "south"; 2308 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 2309 gpio-controller; 2310 #gpio-cells = <2>; 2311 interrupt-controller; 2312 #interrupt-cells = <2>; 2313 gpio-ranges = <&tlmm 0 0 191>; 2314 wakeup-parent = <&pdc>; 2315 }; 2316 2317 remoteproc_mpss: remoteproc@4080000 { 2318 compatible = "qcom,sc8180x-mpss-pas"; 2319 reg = <0x0 0x04080000 0x0 0x4040>; 2320 2321 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, 2322 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2323 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2324 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2325 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2326 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2327 interrupt-names = "wdog", "fatal", "ready", "handover", 2328 "stop-ack", "shutdown-ack"; 2329 2330 clocks = <&rpmhcc RPMH_CXO_CLK>; 2331 clock-names = "xo"; 2332 2333 power-domains = <&rpmhpd SC8180X_CX>, 2334 <&rpmhpd SC8180X_MSS>; 2335 power-domain-names = "cx", "mss"; 2336 2337 qcom,qmp = <&aoss_qmp>; 2338 2339 qcom,smem-states = <&modem_smp2p_out 0>; 2340 qcom,smem-state-names = "stop"; 2341 2342 glink-edge { 2343 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 2344 label = "modem"; 2345 qcom,remote-pid = <1>; 2346 mboxes = <&apss_shared 12>; 2347 }; 2348 }; 2349 2350 remoteproc_cdsp: remoteproc@8300000 { 2351 compatible = "qcom,sc8180x-cdsp-pas"; 2352 reg = <0x0 0x08300000 0x0 0x4040>; 2353 2354 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 2355 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2356 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2357 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2358 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2359 interrupt-names = "wdog", "fatal", "ready", 2360 "handover", "stop-ack"; 2361 2362 clocks = <&rpmhcc RPMH_CXO_CLK>; 2363 clock-names = "xo"; 2364 2365 power-domains = <&rpmhpd SC8180X_CX>; 2366 power-domain-names = "cx"; 2367 2368 qcom,qmp = <&aoss_qmp>; 2369 2370 qcom,smem-states = <&cdsp_smp2p_out 0>; 2371 qcom,smem-state-names = "stop"; 2372 2373 status = "disabled"; 2374 2375 glink-edge { 2376 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>; 2377 label = "cdsp"; 2378 qcom,remote-pid = <5>; 2379 mboxes = <&apss_shared 4>; 2380 }; 2381 }; 2382 2383 usb_prim_hsphy: phy@88e2000 { 2384 compatible = "qcom,sc8180x-usb-hs-phy", 2385 "qcom,usb-snps-hs-7nm-phy"; 2386 reg = <0 0x088e2000 0 0x400>; 2387 clocks = <&rpmhcc RPMH_CXO_CLK>; 2388 clock-names = "ref"; 2389 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2390 2391 #phy-cells = <0>; 2392 2393 status = "disabled"; 2394 }; 2395 2396 usb_sec_hsphy: phy@88e3000 { 2397 compatible = "qcom,sc8180x-usb-hs-phy", 2398 "qcom,usb-snps-hs-7nm-phy"; 2399 reg = <0 0x088e3000 0 0x400>; 2400 clocks = <&rpmhcc RPMH_CXO_CLK>; 2401 clock-names = "ref"; 2402 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 2403 2404 #phy-cells = <0>; 2405 2406 status = "disabled"; 2407 }; 2408 2409 usb_prim_qmpphy: phy@88e9000 { 2410 compatible = "qcom,sc8180x-qmp-usb3-dp-phy"; 2411 reg = <0 0x088e9000 0 0x18c>, 2412 <0 0x088e8000 0 0x38>, 2413 <0 0x088ea000 0 0x40>; 2414 reg-names = "reg-base", "dp_com"; 2415 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2416 <&rpmhcc RPMH_CXO_CLK>, 2417 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 2418 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 2419 clock-names = "aux", 2420 "ref_clk_src", 2421 "ref", 2422 "com_aux"; 2423 resets = <&gcc GCC_USB3_DP_PHY_PRIM_SP0_BCR>, 2424 <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>; 2425 reset-names = "phy", "common"; 2426 2427 #clock-cells = <1>; 2428 #address-cells = <2>; 2429 #size-cells = <2>; 2430 ranges; 2431 2432 status = "disabled"; 2433 2434 ports { 2435 #address-cells = <1>; 2436 #size-cells = <0>; 2437 2438 port@0 { 2439 reg = <0>; 2440 2441 usb_prim_qmpphy_out: endpoint {}; 2442 }; 2443 2444 port@2 { 2445 reg = <2>; 2446 2447 usb_prim_qmpphy_dp_in: endpoint {}; 2448 }; 2449 }; 2450 2451 usb_prim_ssphy: usb3-phy@88e9200 { 2452 reg = <0 0x088e9200 0 0x200>, 2453 <0 0x088e9400 0 0x200>, 2454 <0 0x088e9c00 0 0x218>, 2455 <0 0x088e9600 0 0x200>, 2456 <0 0x088e9800 0 0x200>, 2457 <0 0x088e9a00 0 0x100>; 2458 #phy-cells = <0>; 2459 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2460 clock-names = "pipe0"; 2461 clock-output-names = "usb3_prim_phy_pipe_clk_src"; 2462 }; 2463 2464 usb_prim_dpphy: dp-phy@88ea200 { 2465 reg = <0 0x088ea200 0 0x200>, 2466 <0 0x088ea400 0 0x200>, 2467 <0 0x088eaa00 0 0x200>, 2468 <0 0x088ea600 0 0x200>, 2469 <0 0x088ea800 0 0x200>; 2470 #clock-cells = <1>; 2471 #phy-cells = <0>; 2472 }; 2473 }; 2474 2475 usb_sec_qmpphy: phy@88ee000 { 2476 compatible = "qcom,sc8180x-qmp-usb3-dp-phy"; 2477 reg = <0 0x088ee000 0 0x18c>, 2478 <0 0x088ed000 0 0x10>, 2479 <0 0x088ef000 0 0x40>; 2480 reg-names = "reg-base", "dp_com"; 2481 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 2482 <&rpmhcc RPMH_CXO_CLK>, 2483 <&gcc GCC_USB3_SEC_CLKREF_CLK>, 2484 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; 2485 clock-names = "aux", 2486 "ref_clk_src", 2487 "ref", 2488 "com_aux"; 2489 resets = <&gcc GCC_USB3_DP_PHY_SEC_BCR>, 2490 <&gcc GCC_USB3_PHY_SEC_BCR>; 2491 reset-names = "phy", "common"; 2492 2493 #clock-cells = <1>; 2494 #address-cells = <2>; 2495 #size-cells = <2>; 2496 ranges; 2497 2498 status = "disabled"; 2499 2500 ports { 2501 #address-cells = <1>; 2502 #size-cells = <0>; 2503 2504 port@0 { 2505 reg = <0>; 2506 2507 usb_sec_qmpphy_out: endpoint {}; 2508 }; 2509 2510 port@2 { 2511 reg = <2>; 2512 2513 usb_sec_qmpphy_dp_in: endpoint {}; 2514 }; 2515 }; 2516 2517 usb_sec_ssphy: usb3-phy@88e9200 { 2518 reg = <0 0x088ee200 0 0x200>, 2519 <0 0x088ee400 0 0x200>, 2520 <0 0x088eec00 0 0x218>, 2521 <0 0x088ee600 0 0x200>, 2522 <0 0x088ee800 0 0x200>, 2523 <0 0x088eea00 0 0x100>; 2524 #phy-cells = <0>; 2525 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 2526 clock-names = "pipe0"; 2527 clock-output-names = "usb3_sec_phy_pipe_clk_src"; 2528 }; 2529 2530 usb_sec_dpphy: dp-phy@88ef200 { 2531 reg = <0 0x088ef200 0 0x200>, 2532 <0 0x088ef400 0 0x200>, 2533 <0 0x088efa00 0 0x200>, 2534 <0 0x088ef600 0 0x200>, 2535 <0 0x088ef800 0 0x200>; 2536 #clock-cells = <1>; 2537 #phy-cells = <0>; 2538 clock-output-names = "qmp_dptx1_phy_pll_link_clk", 2539 "qmp_dptx1_phy_pll_vco_div_clk"; 2540 }; 2541 }; 2542 2543 system-cache-controller@9200000 { 2544 compatible = "qcom,sc8180x-llcc"; 2545 reg = <0 0x09200000 0 0x50000>, <0 0x09280000 0 0x50000>, 2546 <0 0x09300000 0 0x50000>, <0 0x09380000 0 0x50000>, 2547 <0 0x09600000 0 0x50000>; 2548 reg-names = "llcc0_base", "llcc1_base", "llcc2_base", 2549 "llcc3_base", "llcc_broadcast_base"; 2550 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 2551 }; 2552 2553 gem_noc: interconnect@9680000 { 2554 compatible = "qcom,sc8180x-gem-noc"; 2555 reg = <0 0x09680000 0 0x58200>; 2556 #interconnect-cells = <2>; 2557 qcom,bcm-voters = <&apps_bcm_voter>; 2558 }; 2559 2560 usb_prim: usb@a6f8800 { 2561 compatible = "qcom,sc8180x-dwc3", "qcom,dwc3"; 2562 reg = <0 0x0a6f8800 0 0x400>; 2563 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 2564 <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, 2565 <&pdc 8 IRQ_TYPE_EDGE_BOTH>, 2566 <&pdc 9 IRQ_TYPE_EDGE_BOTH>; 2567 interrupt-names = "hs_phy_irq", 2568 "ss_phy_irq", 2569 "dm_hs_phy_irq", 2570 "dp_hs_phy_irq"; 2571 2572 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 2573 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 2574 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2575 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2576 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 2577 <&gcc GCC_USB3_SEC_CLKREF_CLK>; 2578 clock-names = "cfg_noc", 2579 "core", 2580 "iface", 2581 "mock_utmi", 2582 "sleep", 2583 "xo"; 2584 resets = <&gcc GCC_USB30_PRIM_BCR>; 2585 power-domains = <&gcc USB30_PRIM_GDSC>; 2586 2587 interconnects = <&aggre1_noc MASTER_USB3 0 &mc_virt SLAVE_EBI_CH0 0>, 2588 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>; 2589 interconnect-names = "usb-ddr", "apps-usb"; 2590 2591 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2592 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 2593 assigned-clock-rates = <19200000>, <200000000>; 2594 2595 #address-cells = <2>; 2596 #size-cells = <2>; 2597 ranges; 2598 dma-ranges; 2599 2600 status = "disabled"; 2601 2602 usb_prim_dwc3: usb@a600000 { 2603 compatible = "snps,dwc3"; 2604 reg = <0 0x0a600000 0 0xcd00>; 2605 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 2606 iommus = <&apps_smmu 0x140 0>; 2607 snps,dis_u2_susphy_quirk; 2608 snps,dis_enblslpm_quirk; 2609 phys = <&usb_prim_hsphy>, <&usb_prim_ssphy>; 2610 phy-names = "usb2-phy", "usb3-phy"; 2611 2612 port { 2613 usb_prim_role_switch: endpoint { 2614 }; 2615 }; 2616 }; 2617 }; 2618 2619 usb_sec: usb@a8f8800 { 2620 compatible = "qcom,sc8180x-dwc3", "qcom,dwc3"; 2621 reg = <0 0x0a8f8800 0 0x400>; 2622 2623 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 2624 <&gcc GCC_USB30_SEC_MASTER_CLK>, 2625 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 2626 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2627 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 2628 <&gcc GCC_USB3_SEC_CLKREF_CLK>; 2629 clock-names = "cfg_noc", 2630 "core", 2631 "iface", 2632 "mock_utmi", 2633 "sleep", 2634 "xo"; 2635 resets = <&gcc GCC_USB30_SEC_BCR>; 2636 power-domains = <&gcc USB30_SEC_GDSC>; 2637 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 2638 <&pdc 7 IRQ_TYPE_LEVEL_HIGH>, 2639 <&pdc 10 IRQ_TYPE_EDGE_BOTH>, 2640 <&pdc 11 IRQ_TYPE_EDGE_BOTH>; 2641 interrupt-names = "hs_phy_irq", "ss_phy_irq", 2642 "dm_hs_phy_irq", "dp_hs_phy_irq"; 2643 2644 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2645 <&gcc GCC_USB30_SEC_MASTER_CLK>; 2646 assigned-clock-rates = <19200000>, <200000000>; 2647 2648 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI_CH0 0>, 2649 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3_1 0>; 2650 interconnect-names = "usb-ddr", "apps-usb"; 2651 2652 #address-cells = <2>; 2653 #size-cells = <2>; 2654 ranges; 2655 dma-ranges; 2656 2657 status = "disabled"; 2658 2659 usb_sec_dwc3: usb@a800000 { 2660 compatible = "snps,dwc3"; 2661 reg = <0 0x0a800000 0 0xcd00>; 2662 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 2663 iommus = <&apps_smmu 0x160 0>; 2664 snps,dis_u2_susphy_quirk; 2665 snps,dis_enblslpm_quirk; 2666 phys = <&usb_sec_hsphy>, <&usb_sec_ssphy>; 2667 phy-names = "usb2-phy", "usb3-phy"; 2668 2669 port { 2670 usb_sec_role_switch: endpoint { 2671 }; 2672 }; 2673 }; 2674 }; 2675 2676 mdss: mdss@ae00000 { 2677 compatible = "qcom,sc8180x-mdss"; 2678 reg = <0 0x0ae00000 0 0x1000>; 2679 reg-names = "mdss"; 2680 2681 power-domains = <&dispcc MDSS_GDSC>; 2682 2683 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2684 <&gcc GCC_DISP_HF_AXI_CLK>, 2685 <&gcc GCC_DISP_SF_AXI_CLK>, 2686 <&dispcc DISP_CC_MDSS_MDP_CLK>; 2687 clock-names = "iface", 2688 "bus", 2689 "nrt_bus", 2690 "core"; 2691 2692 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 2693 2694 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2695 interrupt-controller; 2696 #interrupt-cells = <1>; 2697 2698 interconnects = <&mmss_noc MASTER_MDP_PORT0 0 &mc_virt SLAVE_EBI_CH0 0>, 2699 <&mmss_noc MASTER_MDP_PORT1 0 &mc_virt SLAVE_EBI_CH0 0>; 2700 interconnect-names = "mdp0-mem", "mdp1-mem"; 2701 2702 iommus = <&apps_smmu 0x800 0x420>; 2703 2704 #address-cells = <2>; 2705 #size-cells = <2>; 2706 ranges; 2707 2708 status = "disabled"; 2709 2710 mdss_mdp: mdp@ae01000 { 2711 compatible = "qcom,sc8180x-dpu"; 2712 reg = <0 0x0ae01000 0 0x8f000>, 2713 <0 0x0aeb0000 0 0x2008>; 2714 reg-names = "mdp", "vbif"; 2715 2716 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2717 <&gcc GCC_DISP_HF_AXI_CLK>, 2718 <&dispcc DISP_CC_MDSS_MDP_CLK>, 2719 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2720 clock-names = "iface", 2721 "bus", 2722 "core", 2723 "vsync"; 2724 2725 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, 2726 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2727 assigned-clock-rates = <460000000>, 2728 <19200000>; 2729 2730 operating-points-v2 = <&mdp_opp_table>; 2731 power-domains = <&rpmhpd SC8180X_MMCX>; 2732 2733 interrupt-parent = <&mdss>; 2734 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; 2735 2736 ports { 2737 #address-cells = <1>; 2738 #size-cells = <0>; 2739 2740 port@0 { 2741 reg = <0>; 2742 dpu_intf0_out: endpoint { 2743 remote-endpoint = <&dp0_in>; 2744 }; 2745 }; 2746 2747 port@1 { 2748 reg = <1>; 2749 dpu_intf1_out: endpoint { 2750 remote-endpoint = <&mdss_dsi0_in>; 2751 }; 2752 }; 2753 2754 port@2 { 2755 reg = <2>; 2756 dpu_intf2_out: endpoint { 2757 remote-endpoint = <&mdss_dsi1_in>; 2758 }; 2759 }; 2760 2761 port@4 { 2762 reg = <4>; 2763 dpu_intf4_out: endpoint { 2764 remote-endpoint = <&dp1_in>; 2765 }; 2766 }; 2767 2768 port@5 { 2769 reg = <5>; 2770 dpu_intf5_out: endpoint { 2771 remote-endpoint = <&edp_in>; 2772 }; 2773 }; 2774 }; 2775 2776 mdp_opp_table: opp-table { 2777 compatible = "operating-points-v2"; 2778 2779 opp-200000000 { 2780 opp-hz = /bits/ 64 <200000000>; 2781 required-opps = <&rpmhpd_opp_low_svs>; 2782 }; 2783 2784 opp-300000000 { 2785 opp-hz = /bits/ 64 <300000000>; 2786 required-opps = <&rpmhpd_opp_svs>; 2787 }; 2788 2789 opp-345000000 { 2790 opp-hz = /bits/ 64 <345000000>; 2791 required-opps = <&rpmhpd_opp_svs_l1>; 2792 }; 2793 2794 opp-460000000 { 2795 opp-hz = /bits/ 64 <460000000>; 2796 required-opps = <&rpmhpd_opp_nom>; 2797 }; 2798 }; 2799 }; 2800 2801 mdss_dsi0: dsi@ae94000 { 2802 compatible = "qcom,mdss-dsi-ctrl"; 2803 reg = <0 0x0ae94000 0 0x400>; 2804 reg-names = "dsi_ctrl"; 2805 2806 interrupt-parent = <&mdss>; 2807 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; 2808 2809 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 2810 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 2811 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 2812 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 2813 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2814 <&gcc GCC_DISP_HF_AXI_CLK>; 2815 clock-names = "byte", 2816 "byte_intf", 2817 "pixel", 2818 "core", 2819 "iface", 2820 "bus"; 2821 2822 operating-points-v2 = <&dsi_opp_table>; 2823 power-domains = <&rpmhpd SC8180X_MMCX>; 2824 2825 phys = <&mdss_dsi0_phy>; 2826 phy-names = "dsi"; 2827 2828 status = "disabled"; 2829 2830 ports { 2831 #address-cells = <1>; 2832 #size-cells = <0>; 2833 2834 port@0 { 2835 reg = <0>; 2836 mdss_dsi0_in: endpoint { 2837 remote-endpoint = <&dpu_intf1_out>; 2838 }; 2839 }; 2840 2841 port@1 { 2842 reg = <1>; 2843 mdss_dsi0_out: endpoint { 2844 }; 2845 }; 2846 }; 2847 2848 dsi_opp_table: opp-table { 2849 compatible = "operating-points-v2"; 2850 2851 opp-187500000 { 2852 opp-hz = /bits/ 64 <187500000>; 2853 required-opps = <&rpmhpd_opp_low_svs>; 2854 }; 2855 2856 opp-300000000 { 2857 opp-hz = /bits/ 64 <300000000>; 2858 required-opps = <&rpmhpd_opp_svs>; 2859 }; 2860 2861 opp-358000000 { 2862 opp-hz = /bits/ 64 <358000000>; 2863 required-opps = <&rpmhpd_opp_svs_l1>; 2864 }; 2865 }; 2866 }; 2867 2868 mdss_dsi0_phy: dsi-phy@ae94400 { 2869 compatible = "qcom,dsi-phy-7nm"; 2870 reg = <0 0x0ae94400 0 0x200>, 2871 <0 0x0ae94600 0 0x280>, 2872 <0 0x0ae94900 0 0x260>; 2873 reg-names = "dsi_phy", 2874 "dsi_phy_lane", 2875 "dsi_pll"; 2876 2877 #clock-cells = <1>; 2878 #phy-cells = <0>; 2879 2880 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2881 <&rpmhcc RPMH_CXO_CLK>; 2882 clock-names = "iface", "ref"; 2883 2884 status = "disabled"; 2885 }; 2886 2887 mdss_dsi1: dsi@ae96000 { 2888 compatible = "qcom,mdss-dsi-ctrl"; 2889 reg = <0 0x0ae96000 0 0x400>; 2890 reg-names = "dsi_ctrl"; 2891 2892 interrupt-parent = <&mdss>; 2893 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; 2894 2895 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 2896 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 2897 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 2898 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 2899 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2900 <&gcc GCC_DISP_HF_AXI_CLK>; 2901 clock-names = "byte", 2902 "byte_intf", 2903 "pixel", 2904 "core", 2905 "iface", 2906 "bus"; 2907 2908 operating-points-v2 = <&dsi_opp_table>; 2909 power-domains = <&rpmhpd SC8180X_MMCX>; 2910 2911 phys = <&mdss_dsi1_phy>; 2912 phy-names = "dsi"; 2913 2914 status = "disabled"; 2915 2916 ports { 2917 #address-cells = <1>; 2918 #size-cells = <0>; 2919 2920 port@0 { 2921 reg = <0>; 2922 mdss_dsi1_in: endpoint { 2923 remote-endpoint = <&dpu_intf2_out>; 2924 }; 2925 }; 2926 2927 port@1 { 2928 reg = <1>; 2929 mdss_dsi1_out: endpoint { 2930 }; 2931 }; 2932 }; 2933 }; 2934 2935 mdss_dsi1_phy: dsi-phy@ae96400 { 2936 compatible = "qcom,dsi-phy-7nm"; 2937 reg = <0 0x0ae96400 0 0x200>, 2938 <0 0x0ae96600 0 0x280>, 2939 <0 0x0ae96900 0 0x260>; 2940 reg-names = "dsi_phy", 2941 "dsi_phy_lane", 2942 "dsi_pll"; 2943 2944 #clock-cells = <1>; 2945 #phy-cells = <0>; 2946 2947 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2948 <&rpmhcc RPMH_CXO_CLK>; 2949 clock-names = "iface", "ref"; 2950 2951 status = "disabled"; 2952 }; 2953 2954 mdss_dp0: displayport-controller@ae90000 { 2955 compatible = "qcom,sc8180x-dp"; 2956 reg = <0 0xae90000 0 0x200>, 2957 <0 0xae90200 0 0x200>, 2958 <0 0xae90400 0 0x600>, 2959 <0 0xae90a00 0 0x400>; 2960 interrupt-parent = <&mdss>; 2961 interrupts = <12>; 2962 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2963 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 2964 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 2965 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 2966 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 2967 clock-names = "core_iface", 2968 "core_aux", 2969 "ctrl_link", 2970 "ctrl_link_iface", 2971 "stream_pixel"; 2972 2973 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 2974 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 2975 assigned-clock-parents = <&usb_prim_dpphy 0>, <&usb_prim_dpphy 1>; 2976 2977 phys = <&usb_prim_dpphy>; 2978 phy-names = "dp"; 2979 2980 #sound-dai-cells = <0>; 2981 2982 operating-points-v2 = <&dp0_opp_table>; 2983 power-domains = <&rpmhpd SC8180X_MMCX>; 2984 2985 status = "disabled"; 2986 2987 ports { 2988 #address-cells = <1>; 2989 #size-cells = <0>; 2990 2991 port@0 { 2992 reg = <0>; 2993 dp0_in: endpoint { 2994 remote-endpoint = <&dpu_intf0_out>; 2995 }; 2996 }; 2997 2998 port@1 { 2999 reg = <1>; 3000 mdss_dp0_out: endpoint { 3001 }; 3002 }; 3003 }; 3004 3005 dp0_opp_table: opp-table { 3006 compatible = "operating-points-v2"; 3007 3008 opp-160000000 { 3009 opp-hz = /bits/ 64 <160000000>; 3010 required-opps = <&rpmhpd_opp_low_svs>; 3011 }; 3012 3013 opp-270000000 { 3014 opp-hz = /bits/ 64 <270000000>; 3015 required-opps = <&rpmhpd_opp_svs>; 3016 }; 3017 3018 opp-540000000 { 3019 opp-hz = /bits/ 64 <540000000>; 3020 required-opps = <&rpmhpd_opp_svs_l1>; 3021 }; 3022 3023 opp-810000000 { 3024 opp-hz = /bits/ 64 <810000000>; 3025 required-opps = <&rpmhpd_opp_nom>; 3026 }; 3027 }; 3028 }; 3029 3030 mdss_dp1: displayport-controller@ae98000 { 3031 compatible = "qcom,sc8180x-dp"; 3032 reg = <0 0xae98000 0 0x200>, 3033 <0 0xae98200 0 0x200>, 3034 <0 0xae98400 0 0x600>, 3035 <0 0xae98a00 0 0x400>; 3036 interrupt-parent = <&mdss>; 3037 interrupts = <13>; 3038 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3039 <&dispcc DISP_CC_MDSS_DP_AUX1_CLK>, 3040 <&dispcc DISP_CC_MDSS_DP_LINK1_CLK>, 3041 <&dispcc DISP_CC_MDSS_DP_LINK1_INTF_CLK>, 3042 <&dispcc DISP_CC_MDSS_DP_PIXEL2_CLK>; 3043 clock-names = "core_iface", 3044 "core_aux", 3045 "ctrl_link", 3046 "ctrl_link_iface", 3047 "stream_pixel"; 3048 3049 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK1_CLK_SRC>, 3050 <&dispcc DISP_CC_MDSS_DP_PIXEL2_CLK_SRC>; 3051 assigned-clock-parents = <&usb_sec_dpphy 0>, <&usb_sec_dpphy 1>; 3052 3053 phys = <&usb_sec_dpphy>; 3054 phy-names = "dp"; 3055 3056 #sound-dai-cells = <0>; 3057 3058 operating-points-v2 = <&dp0_opp_table>; 3059 power-domains = <&rpmhpd SC8180X_MMCX>; 3060 3061 status = "disabled"; 3062 3063 ports { 3064 #address-cells = <1>; 3065 #size-cells = <0>; 3066 3067 port@0 { 3068 reg = <0>; 3069 dp1_in: endpoint { 3070 remote-endpoint = <&dpu_intf4_out>; 3071 }; 3072 }; 3073 3074 port@1 { 3075 reg = <1>; 3076 mdss_dp1_out: endpoint { 3077 }; 3078 }; 3079 }; 3080 3081 dp1_opp_table: opp-table { 3082 compatible = "operating-points-v2"; 3083 3084 opp-160000000 { 3085 opp-hz = /bits/ 64 <160000000>; 3086 required-opps = <&rpmhpd_opp_low_svs>; 3087 }; 3088 3089 opp-270000000 { 3090 opp-hz = /bits/ 64 <270000000>; 3091 required-opps = <&rpmhpd_opp_svs>; 3092 }; 3093 3094 opp-540000000 { 3095 opp-hz = /bits/ 64 <540000000>; 3096 required-opps = <&rpmhpd_opp_svs_l1>; 3097 }; 3098 3099 opp-810000000 { 3100 opp-hz = /bits/ 64 <810000000>; 3101 required-opps = <&rpmhpd_opp_nom>; 3102 }; 3103 }; 3104 }; 3105 3106 mdss_edp: displayport-controller@ae9a000 { 3107 compatible = "qcom,sc8180x-edp"; 3108 reg = <0 0xae9a000 0 0x200>, 3109 <0 0xae9a200 0 0x200>, 3110 <0 0xae9a400 0 0x600>, 3111 <0 0xae9aa00 0 0x400>; 3112 interrupt-parent = <&mdss>; 3113 interrupts = <14>; 3114 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3115 <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>, 3116 <&dispcc DISP_CC_MDSS_EDP_LINK_CLK>, 3117 <&dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>, 3118 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>; 3119 clock-names = "core_iface", 3120 "core_aux", 3121 "ctrl_link", 3122 "ctrl_link_iface", 3123 "stream_pixel"; 3124 3125 assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>, 3126 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>; 3127 assigned-clock-parents = <&edp_phy 0>, <&edp_phy 1>; 3128 3129 phys = <&edp_phy>; 3130 phy-names = "dp"; 3131 3132 #sound-dai-cells = <0>; 3133 3134 operating-points-v2 = <&edp_opp_table>; 3135 power-domains = <&rpmhpd SC8180X_MMCX>; 3136 3137 status = "disabled"; 3138 3139 ports { 3140 #address-cells = <1>; 3141 #size-cells = <0>; 3142 3143 port@0 { 3144 reg = <0>; 3145 edp_in: endpoint { 3146 remote-endpoint = <&dpu_intf5_out>; 3147 }; 3148 }; 3149 }; 3150 3151 edp_opp_table: opp-table { 3152 compatible = "operating-points-v2"; 3153 3154 opp-160000000 { 3155 opp-hz = /bits/ 64 <160000000>; 3156 required-opps = <&rpmhpd_opp_low_svs>; 3157 }; 3158 3159 opp-270000000 { 3160 opp-hz = /bits/ 64 <270000000>; 3161 required-opps = <&rpmhpd_opp_svs>; 3162 }; 3163 3164 opp-540000000 { 3165 opp-hz = /bits/ 64 <540000000>; 3166 required-opps = <&rpmhpd_opp_svs_l1>; 3167 }; 3168 3169 opp-810000000 { 3170 opp-hz = /bits/ 64 <810000000>; 3171 required-opps = <&rpmhpd_opp_nom>; 3172 }; 3173 }; 3174 }; 3175 }; 3176 3177 edp_phy: phy@aec2a00 { 3178 compatible = "qcom,sc8180x-edp-phy"; 3179 reg = <0 0x0aec2a00 0 0x1c0>, 3180 <0 0x0aec2200 0 0xa0>, 3181 <0 0x0aec2600 0 0xa0>, 3182 <0 0x0aec2000 0 0x19c>; 3183 3184 clocks = <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>, 3185 <&dispcc DISP_CC_MDSS_AHB_CLK>; 3186 clock-names = "aux", "cfg_ahb"; 3187 3188 power-domains = <&dispcc MDSS_GDSC>; 3189 3190 #clock-cells = <1>; 3191 #phy-cells = <0>; 3192 }; 3193 3194 dispcc: clock-controller@af00000 { 3195 compatible = "qcom,sc8180x-dispcc"; 3196 reg = <0 0x0af00000 0 0x20000>; 3197 clocks = <&rpmhcc RPMH_CXO_CLK>, 3198 <&sleep_clk>, 3199 <&usb_prim_dpphy 0>, 3200 <&usb_prim_dpphy 1>, 3201 <&usb_sec_dpphy 0>, 3202 <&usb_sec_dpphy 1>, 3203 <&edp_phy 0>, 3204 <&edp_phy 1>; 3205 clock-names = "bi_tcxo", 3206 "sleep_clk", 3207 "dp_phy_pll_link_clk", 3208 "dp_phy_pll_vco_div_clk", 3209 "dptx1_phy_pll_link_clk", 3210 "dptx1_phy_pll_vco_div_clk", 3211 "edp_phy_pll_link_clk", 3212 "edp_phy_pll_vco_div_clk"; 3213 power-domains = <&rpmhpd SC8180X_MMCX>; 3214 #clock-cells = <1>; 3215 #reset-cells = <1>; 3216 #power-domain-cells = <1>; 3217 }; 3218 3219 pdc: interrupt-controller@b220000 { 3220 compatible = "qcom,sc8180x-pdc", "qcom,pdc"; 3221 reg = <0 0x0b220000 0 0x30000>; 3222 qcom,pdc-ranges = <0 480 94>, <94 609 31>; 3223 #interrupt-cells = <2>; 3224 interrupt-parent = <&intc>; 3225 interrupt-controller; 3226 }; 3227 3228 tsens0: thermal-sensor@c263000 { 3229 compatible = "qcom,sc8180x-tsens", "qcom,tsens-v2"; 3230 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 3231 <0 0x0c222000 0 0x1ff>; /* SROT */ 3232 #qcom,sensors = <16>; 3233 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 3234 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 3235 interrupt-names = "uplow", "critical"; 3236 #thermal-sensor-cells = <1>; 3237 }; 3238 3239 tsens1: thermal-sensor@c265000 { 3240 compatible = "qcom,sc8180x-tsens", "qcom,tsens-v2"; 3241 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 3242 <0 0x0c223000 0 0x1ff>; /* SROT */ 3243 #qcom,sensors = <9>; 3244 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 3245 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 3246 interrupt-names = "uplow", "critical"; 3247 #thermal-sensor-cells = <1>; 3248 }; 3249 3250 aoss_qmp: power-controller@c300000 { 3251 compatible = "qcom,sc8180x-aoss-qmp", "qcom,aoss-qmp"; 3252 reg = <0x0 0x0c300000 0x0 0x100000>; 3253 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; 3254 mboxes = <&apss_shared 0>; 3255 3256 #clock-cells = <0>; 3257 #power-domain-cells = <1>; 3258 }; 3259 3260 spmi_bus: spmi@c440000 { 3261 compatible = "qcom,spmi-pmic-arb"; 3262 reg = <0x0 0x0c440000 0x0 0x0001100>, 3263 <0x0 0x0c600000 0x0 0x2000000>, 3264 <0x0 0x0e600000 0x0 0x0100000>, 3265 <0x0 0x0e700000 0x0 0x00a0000>, 3266 <0x0 0x0c40a000 0x0 0x0026000>; 3267 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 3268 interrupt-names = "periph_irq"; 3269 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>; 3270 qcom,ee = <0>; 3271 qcom,channel = <0>; 3272 #address-cells = <2>; 3273 #size-cells = <0>; 3274 interrupt-controller; 3275 #interrupt-cells = <4>; 3276 cell-index = <0>; 3277 }; 3278 3279 apps_smmu: iommu@15000000 { 3280 compatible = "qcom,sc8180x-smmu-500", "arm,mmu-500"; 3281 reg = <0 0x15000000 0 0x100000>; 3282 #iommu-cells = <2>; 3283 #global-interrupts = <1>; 3284 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3285 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3286 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3287 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3288 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3289 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3290 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3291 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3292 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3293 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3294 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3295 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3296 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3297 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3298 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3299 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3300 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3301 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3302 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3303 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3304 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3305 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3306 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3307 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3308 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3309 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3310 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3311 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3312 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3313 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3314 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3315 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3316 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3317 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3318 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3319 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3320 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3321 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3322 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3323 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3324 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3325 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3326 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3327 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3328 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3329 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3330 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3331 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3332 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3333 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3334 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3335 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3336 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3337 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3338 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3339 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3340 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3341 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3342 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3343 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3344 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3345 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3346 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3347 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3348 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3349 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3350 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 3351 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 3352 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 3353 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 3354 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 3355 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 3356 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3357 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3358 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3359 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3360 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3361 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3362 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3363 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 3364 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 3365 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 3366 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 3367 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 3368 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>, 3369 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, 3370 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 3371 <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>, 3372 <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>, 3373 <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>, 3374 <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>, 3375 <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>, 3376 <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>, 3377 <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>, 3378 <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>, 3379 <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH>, 3380 <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH>, 3381 <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>, 3382 <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>, 3383 <GIC_SPI 768 IRQ_TYPE_LEVEL_HIGH>, 3384 <GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH>, 3385 <GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>, 3386 <GIC_SPI 771 IRQ_TYPE_LEVEL_HIGH>, 3387 <GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>, 3388 <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>, 3389 <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>, 3390 <GIC_SPI 775 IRQ_TYPE_LEVEL_HIGH>; 3391 3392 }; 3393 3394 remoteproc_adsp: remoteproc@17300000 { 3395 compatible = "qcom,sc8180x-adsp-pas"; 3396 reg = <0x0 0x17300000 0x0 0x4040>; 3397 3398 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 3399 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3400 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3401 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3402 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 3403 interrupt-names = "wdog", "fatal", "ready", 3404 "handover", "stop-ack"; 3405 3406 clocks = <&rpmhcc RPMH_CXO_CLK>; 3407 clock-names = "xo"; 3408 3409 power-domains = <&rpmhpd SC8180X_CX>; 3410 power-domain-names = "cx"; 3411 3412 qcom,qmp = <&aoss_qmp>; 3413 3414 qcom,smem-states = <&adsp_smp2p_out 0>; 3415 qcom,smem-state-names = "stop"; 3416 3417 status = "disabled"; 3418 3419 remoteproc_adsp_glink: glink-edge { 3420 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 3421 label = "lpass"; 3422 qcom,remote-pid = <2>; 3423 mboxes = <&apss_shared 8>; 3424 }; 3425 }; 3426 3427 intc: interrupt-controller@17a00000 { 3428 compatible = "arm,gic-v3"; 3429 interrupt-controller; 3430 #interrupt-cells = <3>; 3431 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 3432 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 3433 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3434 }; 3435 3436 apss_shared: mailbox@17c00000 { 3437 compatible = "qcom,sc8180x-apss-shared"; 3438 reg = <0x0 0x17c00000 0x0 0x1000>; 3439 #mbox-cells = <1>; 3440 }; 3441 3442 timer@17c20000 { 3443 compatible = "arm,armv7-timer-mem"; 3444 reg = <0x0 0x17c20000 0x0 0x1000>; 3445 3446 #address-cells = <1>; 3447 #size-cells = <1>; 3448 ranges = <0 0 0 0x20000000>; 3449 3450 frame@17c21000 { 3451 reg = <0x17c21000 0x1000>, 3452 <0x17c22000 0x1000>; 3453 frame-number = <0>; 3454 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3455 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3456 }; 3457 3458 frame@17c23000 { 3459 reg = <0x17c23000 0x1000>; 3460 frame-number = <1>; 3461 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3462 status = "disabled"; 3463 }; 3464 3465 frame@17c25000 { 3466 reg = <0x17c25000 0x1000>; 3467 frame-number = <2>; 3468 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3469 status = "disabled"; 3470 }; 3471 3472 frame@17c27000 { 3473 reg = <0x17c26000 0x1000>; 3474 frame-number = <3>; 3475 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3476 status = "disabled"; 3477 }; 3478 3479 frame@17c29000 { 3480 reg = <0x17c29000 0x1000>; 3481 frame-number = <4>; 3482 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3483 status = "disabled"; 3484 }; 3485 3486 frame@17c2b000 { 3487 reg = <0x17c2b000 0x1000>; 3488 frame-number = <5>; 3489 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3490 status = "disabled"; 3491 }; 3492 3493 frame@17c2d000 { 3494 reg = <0x17c2d000 0x1000>; 3495 frame-number = <6>; 3496 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3497 status = "disabled"; 3498 }; 3499 }; 3500 3501 apps_rsc: rsc@18200000 { 3502 compatible = "qcom,rpmh-rsc"; 3503 reg = <0x0 0x18200000 0x0 0x10000>, 3504 <0x0 0x18210000 0x0 0x10000>, 3505 <0x0 0x18220000 0x0 0x10000>; 3506 reg-names = "drv-0", "drv-1", "drv-2"; 3507 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3508 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3509 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3510 qcom,tcs-offset = <0xd00>; 3511 qcom,drv-id = <2>; 3512 qcom,tcs-config = <ACTIVE_TCS 2>, 3513 <SLEEP_TCS 1>, 3514 <WAKE_TCS 1>, 3515 <CONTROL_TCS 0>; 3516 label = "apps_rsc"; 3517 power-domains = <&CLUSTER_PD>; 3518 3519 apps_bcm_voter: bcm-voter { 3520 compatible = "qcom,bcm-voter"; 3521 }; 3522 3523 rpmhcc: clock-controller { 3524 compatible = "qcom,sc8180x-rpmh-clk"; 3525 #clock-cells = <1>; 3526 clock-names = "xo"; 3527 clocks = <&xo_board_clk>; 3528 }; 3529 3530 rpmhpd: power-controller { 3531 compatible = "qcom,sc8180x-rpmhpd"; 3532 #power-domain-cells = <1>; 3533 operating-points-v2 = <&rpmhpd_opp_table>; 3534 3535 rpmhpd_opp_table: opp-table { 3536 compatible = "operating-points-v2"; 3537 3538 rpmhpd_opp_ret: opp1 { 3539 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3540 }; 3541 3542 rpmhpd_opp_min_svs: opp2 { 3543 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3544 }; 3545 3546 rpmhpd_opp_low_svs: opp3 { 3547 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3548 }; 3549 3550 rpmhpd_opp_svs: opp4 { 3551 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3552 }; 3553 3554 rpmhpd_opp_svs_l1: opp5 { 3555 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3556 }; 3557 3558 rpmhpd_opp_nom: opp6 { 3559 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3560 }; 3561 3562 rpmhpd_opp_nom_l1: opp7 { 3563 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3564 }; 3565 3566 rpmhpd_opp_nom_l2: opp8 { 3567 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 3568 }; 3569 3570 rpmhpd_opp_turbo: opp9 { 3571 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3572 }; 3573 3574 rpmhpd_opp_turbo_l1: opp10 { 3575 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3576 }; 3577 }; 3578 }; 3579 }; 3580 3581 osm_l3: interconnect@18321000 { 3582 compatible = "qcom,sc8180x-osm-l3", "qcom,osm-l3"; 3583 reg = <0 0x18321000 0 0x1400>; 3584 3585 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 3586 clock-names = "xo", "alternate"; 3587 3588 #interconnect-cells = <1>; 3589 }; 3590 3591 lmh@18350800 { 3592 compatible = "qcom,sc8180x-lmh"; 3593 reg = <0 0x18350800 0 0x400>; 3594 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 3595 cpus = <&CPU4>; 3596 qcom,lmh-temp-arm-millicelsius = <65000>; 3597 qcom,lmh-temp-low-millicelsius = <94500>; 3598 qcom,lmh-temp-high-millicelsius = <95000>; 3599 interrupt-controller; 3600 #interrupt-cells = <1>; 3601 }; 3602 3603 lmh@18358800 { 3604 compatible = "qcom,sc8180x-lmh"; 3605 reg = <0 0x18358800 0 0x400>; 3606 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 3607 cpus = <&CPU0>; 3608 qcom,lmh-temp-arm-millicelsius = <65000>; 3609 qcom,lmh-temp-low-millicelsius = <94500>; 3610 qcom,lmh-temp-high-millicelsius = <95000>; 3611 interrupt-controller; 3612 #interrupt-cells = <1>; 3613 }; 3614 3615 cpufreq_hw: cpufreq@18323000 { 3616 compatible = "qcom,cpufreq-hw"; 3617 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>; 3618 reg-names = "freq-domain0", "freq-domain1"; 3619 3620 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 3621 clock-names = "xo", "alternate"; 3622 3623 #freq-domain-cells = <1>; 3624 #clock-cells = <1>; 3625 }; 3626 3627 wifi: wifi@18800000 { 3628 compatible = "qcom,wcn3990-wifi"; 3629 reg = <0 0x18800000 0 0x800000>; 3630 reg-names = "membase"; 3631 clock-names = "cxo_ref_clk_pin"; 3632 clocks = <&rpmhcc RPMH_RF_CLK2>; 3633 interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 3634 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 3635 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 3636 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 3637 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 3638 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 3639 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 3640 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 3641 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 3642 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 3643 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 3644 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 3645 iommus = <&apps_smmu 0x0640 0x1>; 3646 qcom,msa-fixed-perm; 3647 status = "disabled"; 3648 }; 3649 }; 3650 3651 thermal-zones { 3652 cpu0-thermal { 3653 polling-delay-passive = <250>; 3654 polling-delay = <1000>; 3655 3656 thermal-sensors = <&tsens0 1>; 3657 3658 trips { 3659 cpu-crit { 3660 temperature = <110000>; 3661 hysteresis = <1000>; 3662 type = "critical"; 3663 }; 3664 }; 3665 }; 3666 3667 cpu1-thermal { 3668 polling-delay-passive = <250>; 3669 polling-delay = <1000>; 3670 3671 thermal-sensors = <&tsens0 2>; 3672 3673 trips { 3674 cpu-crit { 3675 temperature = <110000>; 3676 hysteresis = <1000>; 3677 type = "critical"; 3678 }; 3679 }; 3680 }; 3681 3682 cpu2-thermal { 3683 polling-delay-passive = <250>; 3684 polling-delay = <1000>; 3685 3686 thermal-sensors = <&tsens0 3>; 3687 3688 trips { 3689 cpu-crit { 3690 temperature = <110000>; 3691 hysteresis = <1000>; 3692 type = "critical"; 3693 }; 3694 }; 3695 }; 3696 3697 cpu3-thermal { 3698 polling-delay-passive = <250>; 3699 polling-delay = <1000>; 3700 3701 thermal-sensors = <&tsens0 4>; 3702 3703 trips { 3704 cpu-crit { 3705 temperature = <110000>; 3706 hysteresis = <1000>; 3707 type = "critical"; 3708 }; 3709 }; 3710 }; 3711 3712 cpu4-top-thermal { 3713 polling-delay-passive = <250>; 3714 polling-delay = <1000>; 3715 3716 thermal-sensors = <&tsens0 7>; 3717 3718 trips { 3719 cpu-crit { 3720 temperature = <110000>; 3721 hysteresis = <1000>; 3722 type = "critical"; 3723 }; 3724 }; 3725 }; 3726 3727 cpu5-top-thermal { 3728 polling-delay-passive = <250>; 3729 polling-delay = <1000>; 3730 3731 thermal-sensors = <&tsens0 8>; 3732 3733 trips { 3734 cpu-crit { 3735 temperature = <110000>; 3736 hysteresis = <1000>; 3737 type = "critical"; 3738 }; 3739 }; 3740 }; 3741 3742 cpu6-top-thermal { 3743 polling-delay-passive = <250>; 3744 polling-delay = <1000>; 3745 3746 thermal-sensors = <&tsens0 9>; 3747 3748 trips { 3749 cpu-crit { 3750 temperature = <110000>; 3751 hysteresis = <1000>; 3752 type = "critical"; 3753 }; 3754 }; 3755 }; 3756 3757 cpu7-top-thermal { 3758 polling-delay-passive = <250>; 3759 polling-delay = <1000>; 3760 3761 thermal-sensors = <&tsens0 10>; 3762 3763 trips { 3764 cpu-crit { 3765 temperature = <110000>; 3766 hysteresis = <1000>; 3767 type = "critical"; 3768 }; 3769 }; 3770 }; 3771 3772 cpu4-bottom-thermal { 3773 polling-delay-passive = <250>; 3774 polling-delay = <1000>; 3775 3776 thermal-sensors = <&tsens0 11>; 3777 3778 trips { 3779 cpu-crit { 3780 temperature = <110000>; 3781 hysteresis = <1000>; 3782 type = "critical"; 3783 }; 3784 }; 3785 }; 3786 3787 cpu5-bottom-thermal { 3788 polling-delay-passive = <250>; 3789 polling-delay = <1000>; 3790 3791 thermal-sensors = <&tsens0 12>; 3792 3793 trips { 3794 cpu-crit { 3795 temperature = <110000>; 3796 hysteresis = <1000>; 3797 type = "critical"; 3798 }; 3799 }; 3800 }; 3801 3802 cpu6-bottom-thermal { 3803 polling-delay-passive = <250>; 3804 polling-delay = <1000>; 3805 3806 thermal-sensors = <&tsens0 13>; 3807 3808 trips { 3809 cpu-crit { 3810 temperature = <110000>; 3811 hysteresis = <1000>; 3812 type = "critical"; 3813 }; 3814 }; 3815 }; 3816 3817 cpu7-bottom-thermal { 3818 polling-delay-passive = <250>; 3819 polling-delay = <1000>; 3820 3821 thermal-sensors = <&tsens0 14>; 3822 3823 trips { 3824 cpu-crit { 3825 temperature = <110000>; 3826 hysteresis = <1000>; 3827 type = "critical"; 3828 }; 3829 }; 3830 }; 3831 3832 aoss0-thermal { 3833 polling-delay-passive = <250>; 3834 polling-delay = <1000>; 3835 3836 thermal-sensors = <&tsens0 0>; 3837 3838 trips { 3839 trip-point0 { 3840 temperature = <90000>; 3841 hysteresis = <2000>; 3842 type = "hot"; 3843 }; 3844 }; 3845 }; 3846 3847 cluster0-thermal { 3848 polling-delay-passive = <250>; 3849 polling-delay = <1000>; 3850 3851 thermal-sensors = <&tsens0 5>; 3852 3853 trips { 3854 cluster-crit { 3855 temperature = <110000>; 3856 hysteresis = <2000>; 3857 type = "critical"; 3858 }; 3859 }; 3860 }; 3861 3862 cluster1-thermal { 3863 polling-delay-passive = <250>; 3864 polling-delay = <1000>; 3865 3866 thermal-sensors = <&tsens0 6>; 3867 3868 trips { 3869 cluster-crit { 3870 temperature = <110000>; 3871 hysteresis = <2000>; 3872 type = "critical"; 3873 }; 3874 }; 3875 }; 3876 3877 gpu-top-thermal { 3878 polling-delay-passive = <250>; 3879 polling-delay = <1000>; 3880 3881 thermal-sensors = <&tsens0 15>; 3882 3883 trips { 3884 trip-point0 { 3885 temperature = <90000>; 3886 hysteresis = <2000>; 3887 type = "hot"; 3888 }; 3889 }; 3890 }; 3891 3892 aoss1-thermal { 3893 polling-delay-passive = <250>; 3894 polling-delay = <1000>; 3895 3896 thermal-sensors = <&tsens1 0>; 3897 3898 trips { 3899 trip-point0 { 3900 temperature = <90000>; 3901 hysteresis = <2000>; 3902 type = "hot"; 3903 }; 3904 }; 3905 }; 3906 3907 wlan-thermal { 3908 polling-delay-passive = <250>; 3909 polling-delay = <1000>; 3910 3911 thermal-sensors = <&tsens1 1>; 3912 3913 trips { 3914 trip-point0 { 3915 temperature = <90000>; 3916 hysteresis = <2000>; 3917 type = "hot"; 3918 }; 3919 }; 3920 }; 3921 3922 video-thermal { 3923 polling-delay-passive = <250>; 3924 polling-delay = <1000>; 3925 3926 thermal-sensors = <&tsens1 2>; 3927 3928 trips { 3929 trip-point0 { 3930 temperature = <90000>; 3931 hysteresis = <2000>; 3932 type = "hot"; 3933 }; 3934 }; 3935 }; 3936 3937 mem-thermal { 3938 polling-delay-passive = <250>; 3939 polling-delay = <1000>; 3940 3941 thermal-sensors = <&tsens1 3>; 3942 3943 trips { 3944 trip-point0 { 3945 temperature = <90000>; 3946 hysteresis = <2000>; 3947 type = "hot"; 3948 }; 3949 }; 3950 }; 3951 3952 q6-hvx-thermal { 3953 polling-delay-passive = <250>; 3954 polling-delay = <1000>; 3955 3956 thermal-sensors = <&tsens1 4>; 3957 3958 trips { 3959 trip-point0 { 3960 temperature = <90000>; 3961 hysteresis = <2000>; 3962 type = "hot"; 3963 }; 3964 }; 3965 }; 3966 3967 camera-thermal { 3968 polling-delay-passive = <250>; 3969 polling-delay = <1000>; 3970 3971 thermal-sensors = <&tsens1 5>; 3972 3973 trips { 3974 trip-point0 { 3975 temperature = <90000>; 3976 hysteresis = <2000>; 3977 type = "hot"; 3978 }; 3979 }; 3980 }; 3981 3982 compute-thermal { 3983 polling-delay-passive = <250>; 3984 polling-delay = <1000>; 3985 3986 thermal-sensors = <&tsens1 6>; 3987 3988 trips { 3989 trip-point0 { 3990 temperature = <90000>; 3991 hysteresis = <2000>; 3992 type = "hot"; 3993 }; 3994 }; 3995 }; 3996 3997 mdm-dsp-thermal { 3998 polling-delay-passive = <250>; 3999 polling-delay = <1000>; 4000 4001 thermal-sensors = <&tsens1 7>; 4002 4003 trips { 4004 trip-point0 { 4005 temperature = <90000>; 4006 hysteresis = <2000>; 4007 type = "hot"; 4008 }; 4009 }; 4010 }; 4011 4012 npu-thermal { 4013 polling-delay-passive = <250>; 4014 polling-delay = <1000>; 4015 4016 thermal-sensors = <&tsens1 8>; 4017 4018 trips { 4019 trip-point0 { 4020 temperature = <90000>; 4021 hysteresis = <2000>; 4022 type = "hot"; 4023 }; 4024 }; 4025 }; 4026 4027 gpu-bottom-thermal { 4028 polling-delay-passive = <250>; 4029 polling-delay = <1000>; 4030 4031 thermal-sensors = <&tsens1 11>; 4032 4033 trips { 4034 trip-point0 { 4035 temperature = <90000>; 4036 hysteresis = <2000>; 4037 type = "hot"; 4038 }; 4039 }; 4040 }; 4041 }; 4042 4043 timer { 4044 compatible = "arm,armv8-timer"; 4045 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 4046 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 4047 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 4048 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 4049 }; 4050}; 4051