1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * sc7280 SoC device tree source 4 * 5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 6 */ 7#include <dt-bindings/clock/qcom,camcc-sc7280.h> 8#include <dt-bindings/clock/qcom,dispcc-sc7280.h> 9#include <dt-bindings/clock/qcom,gcc-sc7280.h> 10#include <dt-bindings/clock/qcom,gpucc-sc7280.h> 11#include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h> 12#include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h> 13#include <dt-bindings/clock/qcom,rpmh.h> 14#include <dt-bindings/clock/qcom,videocc-sc7280.h> 15#include <dt-bindings/dma/qcom-gpi.h> 16#include <dt-bindings/gpio/gpio.h> 17#include <dt-bindings/interconnect/qcom,osm-l3.h> 18#include <dt-bindings/interconnect/qcom,sc7280.h> 19#include <dt-bindings/interrupt-controller/arm-gic.h> 20#include <dt-bindings/mailbox/qcom-ipcc.h> 21#include <dt-bindings/power/qcom-rpmpd.h> 22#include <dt-bindings/reset/qcom,sdm845-aoss.h> 23#include <dt-bindings/reset/qcom,sdm845-pdc.h> 24#include <dt-bindings/soc/qcom,rpmh-rsc.h> 25#include <dt-bindings/sound/qcom,lpass.h> 26#include <dt-bindings/thermal/thermal.h> 27 28/ { 29 interrupt-parent = <&intc>; 30 31 #address-cells = <2>; 32 #size-cells = <2>; 33 34 chosen { }; 35 36 aliases { 37 i2c0 = &i2c0; 38 i2c1 = &i2c1; 39 i2c2 = &i2c2; 40 i2c3 = &i2c3; 41 i2c4 = &i2c4; 42 i2c5 = &i2c5; 43 i2c6 = &i2c6; 44 i2c7 = &i2c7; 45 i2c8 = &i2c8; 46 i2c9 = &i2c9; 47 i2c10 = &i2c10; 48 i2c11 = &i2c11; 49 i2c12 = &i2c12; 50 i2c13 = &i2c13; 51 i2c14 = &i2c14; 52 i2c15 = &i2c15; 53 mmc1 = &sdhc_1; 54 mmc2 = &sdhc_2; 55 spi0 = &spi0; 56 spi1 = &spi1; 57 spi2 = &spi2; 58 spi3 = &spi3; 59 spi4 = &spi4; 60 spi5 = &spi5; 61 spi6 = &spi6; 62 spi7 = &spi7; 63 spi8 = &spi8; 64 spi9 = &spi9; 65 spi10 = &spi10; 66 spi11 = &spi11; 67 spi12 = &spi12; 68 spi13 = &spi13; 69 spi14 = &spi14; 70 spi15 = &spi15; 71 }; 72 73 clocks { 74 xo_board: xo-board { 75 compatible = "fixed-clock"; 76 clock-frequency = <76800000>; 77 #clock-cells = <0>; 78 }; 79 80 sleep_clk: sleep-clk { 81 compatible = "fixed-clock"; 82 clock-frequency = <32000>; 83 #clock-cells = <0>; 84 }; 85 }; 86 87 reserved-memory { 88 #address-cells = <2>; 89 #size-cells = <2>; 90 ranges; 91 92 wlan_ce_mem: memory@4cd000 { 93 no-map; 94 reg = <0x0 0x004cd000 0x0 0x1000>; 95 }; 96 97 hyp_mem: memory@80000000 { 98 reg = <0x0 0x80000000 0x0 0x600000>; 99 no-map; 100 }; 101 102 xbl_mem: memory@80600000 { 103 reg = <0x0 0x80600000 0x0 0x200000>; 104 no-map; 105 }; 106 107 aop_mem: memory@80800000 { 108 reg = <0x0 0x80800000 0x0 0x60000>; 109 no-map; 110 }; 111 112 aop_cmd_db_mem: memory@80860000 { 113 reg = <0x0 0x80860000 0x0 0x20000>; 114 compatible = "qcom,cmd-db"; 115 no-map; 116 }; 117 118 reserved_xbl_uefi_log: memory@80880000 { 119 reg = <0x0 0x80884000 0x0 0x10000>; 120 no-map; 121 }; 122 123 sec_apps_mem: memory@808ff000 { 124 reg = <0x0 0x808ff000 0x0 0x1000>; 125 no-map; 126 }; 127 128 smem_mem: memory@80900000 { 129 reg = <0x0 0x80900000 0x0 0x200000>; 130 no-map; 131 }; 132 133 cpucp_mem: memory@80b00000 { 134 no-map; 135 reg = <0x0 0x80b00000 0x0 0x100000>; 136 }; 137 138 wlan_fw_mem: memory@80c00000 { 139 reg = <0x0 0x80c00000 0x0 0xc00000>; 140 no-map; 141 }; 142 143 video_mem: memory@8b200000 { 144 reg = <0x0 0x8b200000 0x0 0x500000>; 145 no-map; 146 }; 147 148 ipa_fw_mem: memory@8b700000 { 149 reg = <0 0x8b700000 0 0x10000>; 150 no-map; 151 }; 152 153 rmtfs_mem: memory@9c900000 { 154 compatible = "qcom,rmtfs-mem"; 155 reg = <0x0 0x9c900000 0x0 0x280000>; 156 no-map; 157 158 qcom,client-id = <1>; 159 qcom,vmid = <15>; 160 }; 161 }; 162 163 cpus { 164 #address-cells = <2>; 165 #size-cells = <0>; 166 167 CPU0: cpu@0 { 168 device_type = "cpu"; 169 compatible = "qcom,kryo"; 170 reg = <0x0 0x0>; 171 clocks = <&cpufreq_hw 0>; 172 enable-method = "psci"; 173 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 174 &LITTLE_CPU_SLEEP_1 175 &CLUSTER_SLEEP_0>; 176 next-level-cache = <&L2_0>; 177 operating-points-v2 = <&cpu0_opp_table>; 178 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 179 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 180 qcom,freq-domain = <&cpufreq_hw 0>; 181 #cooling-cells = <2>; 182 L2_0: l2-cache { 183 compatible = "cache"; 184 cache-level = <2>; 185 cache-unified; 186 next-level-cache = <&L3_0>; 187 L3_0: l3-cache { 188 compatible = "cache"; 189 cache-level = <3>; 190 cache-unified; 191 }; 192 }; 193 }; 194 195 CPU1: cpu@100 { 196 device_type = "cpu"; 197 compatible = "qcom,kryo"; 198 reg = <0x0 0x100>; 199 clocks = <&cpufreq_hw 0>; 200 enable-method = "psci"; 201 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 202 &LITTLE_CPU_SLEEP_1 203 &CLUSTER_SLEEP_0>; 204 next-level-cache = <&L2_100>; 205 operating-points-v2 = <&cpu0_opp_table>; 206 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 207 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 208 qcom,freq-domain = <&cpufreq_hw 0>; 209 #cooling-cells = <2>; 210 L2_100: l2-cache { 211 compatible = "cache"; 212 cache-level = <2>; 213 cache-unified; 214 next-level-cache = <&L3_0>; 215 }; 216 }; 217 218 CPU2: cpu@200 { 219 device_type = "cpu"; 220 compatible = "qcom,kryo"; 221 reg = <0x0 0x200>; 222 clocks = <&cpufreq_hw 0>; 223 enable-method = "psci"; 224 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 225 &LITTLE_CPU_SLEEP_1 226 &CLUSTER_SLEEP_0>; 227 next-level-cache = <&L2_200>; 228 operating-points-v2 = <&cpu0_opp_table>; 229 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 230 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 231 qcom,freq-domain = <&cpufreq_hw 0>; 232 #cooling-cells = <2>; 233 L2_200: l2-cache { 234 compatible = "cache"; 235 cache-level = <2>; 236 cache-unified; 237 next-level-cache = <&L3_0>; 238 }; 239 }; 240 241 CPU3: cpu@300 { 242 device_type = "cpu"; 243 compatible = "qcom,kryo"; 244 reg = <0x0 0x300>; 245 clocks = <&cpufreq_hw 0>; 246 enable-method = "psci"; 247 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 248 &LITTLE_CPU_SLEEP_1 249 &CLUSTER_SLEEP_0>; 250 next-level-cache = <&L2_300>; 251 operating-points-v2 = <&cpu0_opp_table>; 252 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 253 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 254 qcom,freq-domain = <&cpufreq_hw 0>; 255 #cooling-cells = <2>; 256 L2_300: l2-cache { 257 compatible = "cache"; 258 cache-level = <2>; 259 cache-unified; 260 next-level-cache = <&L3_0>; 261 }; 262 }; 263 264 CPU4: cpu@400 { 265 device_type = "cpu"; 266 compatible = "qcom,kryo"; 267 reg = <0x0 0x400>; 268 clocks = <&cpufreq_hw 1>; 269 enable-method = "psci"; 270 cpu-idle-states = <&BIG_CPU_SLEEP_0 271 &BIG_CPU_SLEEP_1 272 &CLUSTER_SLEEP_0>; 273 next-level-cache = <&L2_400>; 274 operating-points-v2 = <&cpu4_opp_table>; 275 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 276 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 277 qcom,freq-domain = <&cpufreq_hw 1>; 278 #cooling-cells = <2>; 279 L2_400: l2-cache { 280 compatible = "cache"; 281 cache-level = <2>; 282 cache-unified; 283 next-level-cache = <&L3_0>; 284 }; 285 }; 286 287 CPU5: cpu@500 { 288 device_type = "cpu"; 289 compatible = "qcom,kryo"; 290 reg = <0x0 0x500>; 291 clocks = <&cpufreq_hw 1>; 292 enable-method = "psci"; 293 cpu-idle-states = <&BIG_CPU_SLEEP_0 294 &BIG_CPU_SLEEP_1 295 &CLUSTER_SLEEP_0>; 296 next-level-cache = <&L2_500>; 297 operating-points-v2 = <&cpu4_opp_table>; 298 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 299 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 300 qcom,freq-domain = <&cpufreq_hw 1>; 301 #cooling-cells = <2>; 302 L2_500: l2-cache { 303 compatible = "cache"; 304 cache-level = <2>; 305 cache-unified; 306 next-level-cache = <&L3_0>; 307 }; 308 }; 309 310 CPU6: cpu@600 { 311 device_type = "cpu"; 312 compatible = "qcom,kryo"; 313 reg = <0x0 0x600>; 314 clocks = <&cpufreq_hw 1>; 315 enable-method = "psci"; 316 cpu-idle-states = <&BIG_CPU_SLEEP_0 317 &BIG_CPU_SLEEP_1 318 &CLUSTER_SLEEP_0>; 319 next-level-cache = <&L2_600>; 320 operating-points-v2 = <&cpu4_opp_table>; 321 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 322 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 323 qcom,freq-domain = <&cpufreq_hw 1>; 324 #cooling-cells = <2>; 325 L2_600: l2-cache { 326 compatible = "cache"; 327 cache-level = <2>; 328 cache-unified; 329 next-level-cache = <&L3_0>; 330 }; 331 }; 332 333 CPU7: cpu@700 { 334 device_type = "cpu"; 335 compatible = "qcom,kryo"; 336 reg = <0x0 0x700>; 337 clocks = <&cpufreq_hw 2>; 338 enable-method = "psci"; 339 cpu-idle-states = <&BIG_CPU_SLEEP_0 340 &BIG_CPU_SLEEP_1 341 &CLUSTER_SLEEP_0>; 342 next-level-cache = <&L2_700>; 343 operating-points-v2 = <&cpu7_opp_table>; 344 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 345 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 346 qcom,freq-domain = <&cpufreq_hw 2>; 347 #cooling-cells = <2>; 348 L2_700: l2-cache { 349 compatible = "cache"; 350 cache-level = <2>; 351 cache-unified; 352 next-level-cache = <&L3_0>; 353 }; 354 }; 355 356 cpu-map { 357 cluster0 { 358 core0 { 359 cpu = <&CPU0>; 360 }; 361 362 core1 { 363 cpu = <&CPU1>; 364 }; 365 366 core2 { 367 cpu = <&CPU2>; 368 }; 369 370 core3 { 371 cpu = <&CPU3>; 372 }; 373 374 core4 { 375 cpu = <&CPU4>; 376 }; 377 378 core5 { 379 cpu = <&CPU5>; 380 }; 381 382 core6 { 383 cpu = <&CPU6>; 384 }; 385 386 core7 { 387 cpu = <&CPU7>; 388 }; 389 }; 390 }; 391 392 idle-states { 393 entry-method = "psci"; 394 395 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 396 compatible = "arm,idle-state"; 397 idle-state-name = "little-power-down"; 398 arm,psci-suspend-param = <0x40000003>; 399 entry-latency-us = <549>; 400 exit-latency-us = <901>; 401 min-residency-us = <1774>; 402 local-timer-stop; 403 }; 404 405 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 406 compatible = "arm,idle-state"; 407 idle-state-name = "little-rail-power-down"; 408 arm,psci-suspend-param = <0x40000004>; 409 entry-latency-us = <702>; 410 exit-latency-us = <915>; 411 min-residency-us = <4001>; 412 local-timer-stop; 413 }; 414 415 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 416 compatible = "arm,idle-state"; 417 idle-state-name = "big-power-down"; 418 arm,psci-suspend-param = <0x40000003>; 419 entry-latency-us = <523>; 420 exit-latency-us = <1244>; 421 min-residency-us = <2207>; 422 local-timer-stop; 423 }; 424 425 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 426 compatible = "arm,idle-state"; 427 idle-state-name = "big-rail-power-down"; 428 arm,psci-suspend-param = <0x40000004>; 429 entry-latency-us = <526>; 430 exit-latency-us = <1854>; 431 min-residency-us = <5555>; 432 local-timer-stop; 433 }; 434 435 CLUSTER_SLEEP_0: cluster-sleep-0 { 436 compatible = "arm,idle-state"; 437 idle-state-name = "cluster-power-down"; 438 arm,psci-suspend-param = <0x40003444>; 439 entry-latency-us = <3263>; 440 exit-latency-us = <6562>; 441 min-residency-us = <9926>; 442 local-timer-stop; 443 }; 444 }; 445 }; 446 447 cpu0_opp_table: opp-table-cpu0 { 448 compatible = "operating-points-v2"; 449 opp-shared; 450 451 cpu0_opp_300mhz: opp-300000000 { 452 opp-hz = /bits/ 64 <300000000>; 453 opp-peak-kBps = <800000 9600000>; 454 }; 455 456 cpu0_opp_691mhz: opp-691200000 { 457 opp-hz = /bits/ 64 <691200000>; 458 opp-peak-kBps = <800000 17817600>; 459 }; 460 461 cpu0_opp_806mhz: opp-806400000 { 462 opp-hz = /bits/ 64 <806400000>; 463 opp-peak-kBps = <800000 20889600>; 464 }; 465 466 cpu0_opp_941mhz: opp-940800000 { 467 opp-hz = /bits/ 64 <940800000>; 468 opp-peak-kBps = <1804000 24576000>; 469 }; 470 471 cpu0_opp_1152mhz: opp-1152000000 { 472 opp-hz = /bits/ 64 <1152000000>; 473 opp-peak-kBps = <2188000 27033600>; 474 }; 475 476 cpu0_opp_1325mhz: opp-1324800000 { 477 opp-hz = /bits/ 64 <1324800000>; 478 opp-peak-kBps = <2188000 33792000>; 479 }; 480 481 cpu0_opp_1517mhz: opp-1516800000 { 482 opp-hz = /bits/ 64 <1516800000>; 483 opp-peak-kBps = <3072000 38092800>; 484 }; 485 486 cpu0_opp_1651mhz: opp-1651200000 { 487 opp-hz = /bits/ 64 <1651200000>; 488 opp-peak-kBps = <3072000 41779200>; 489 }; 490 491 cpu0_opp_1805mhz: opp-1804800000 { 492 opp-hz = /bits/ 64 <1804800000>; 493 opp-peak-kBps = <4068000 48537600>; 494 }; 495 496 cpu0_opp_1958mhz: opp-1958400000 { 497 opp-hz = /bits/ 64 <1958400000>; 498 opp-peak-kBps = <4068000 48537600>; 499 }; 500 501 cpu0_opp_2016mhz: opp-2016000000 { 502 opp-hz = /bits/ 64 <2016000000>; 503 opp-peak-kBps = <6220000 48537600>; 504 }; 505 }; 506 507 cpu4_opp_table: opp-table-cpu4 { 508 compatible = "operating-points-v2"; 509 opp-shared; 510 511 cpu4_opp_691mhz: opp-691200000 { 512 opp-hz = /bits/ 64 <691200000>; 513 opp-peak-kBps = <1804000 9600000>; 514 }; 515 516 cpu4_opp_941mhz: opp-940800000 { 517 opp-hz = /bits/ 64 <940800000>; 518 opp-peak-kBps = <2188000 17817600>; 519 }; 520 521 cpu4_opp_1229mhz: opp-1228800000 { 522 opp-hz = /bits/ 64 <1228800000>; 523 opp-peak-kBps = <4068000 24576000>; 524 }; 525 526 cpu4_opp_1344mhz: opp-1344000000 { 527 opp-hz = /bits/ 64 <1344000000>; 528 opp-peak-kBps = <4068000 24576000>; 529 }; 530 531 cpu4_opp_1517mhz: opp-1516800000 { 532 opp-hz = /bits/ 64 <1516800000>; 533 opp-peak-kBps = <4068000 24576000>; 534 }; 535 536 cpu4_opp_1651mhz: opp-1651200000 { 537 opp-hz = /bits/ 64 <1651200000>; 538 opp-peak-kBps = <6220000 38092800>; 539 }; 540 541 cpu4_opp_1901mhz: opp-1900800000 { 542 opp-hz = /bits/ 64 <1900800000>; 543 opp-peak-kBps = <6220000 44851200>; 544 }; 545 546 cpu4_opp_2054mhz: opp-2054400000 { 547 opp-hz = /bits/ 64 <2054400000>; 548 opp-peak-kBps = <6220000 44851200>; 549 }; 550 551 cpu4_opp_2112mhz: opp-2112000000 { 552 opp-hz = /bits/ 64 <2112000000>; 553 opp-peak-kBps = <6220000 44851200>; 554 }; 555 556 cpu4_opp_2131mhz: opp-2131200000 { 557 opp-hz = /bits/ 64 <2131200000>; 558 opp-peak-kBps = <6220000 44851200>; 559 }; 560 561 cpu4_opp_2208mhz: opp-2208000000 { 562 opp-hz = /bits/ 64 <2208000000>; 563 opp-peak-kBps = <6220000 44851200>; 564 }; 565 566 cpu4_opp_2400mhz: opp-2400000000 { 567 opp-hz = /bits/ 64 <2400000000>; 568 opp-peak-kBps = <8532000 48537600>; 569 }; 570 571 cpu4_opp_2611mhz: opp-2611200000 { 572 opp-hz = /bits/ 64 <2611200000>; 573 opp-peak-kBps = <8532000 48537600>; 574 }; 575 }; 576 577 cpu7_opp_table: opp-table-cpu7 { 578 compatible = "operating-points-v2"; 579 opp-shared; 580 581 cpu7_opp_806mhz: opp-806400000 { 582 opp-hz = /bits/ 64 <806400000>; 583 opp-peak-kBps = <1804000 9600000>; 584 }; 585 586 cpu7_opp_1056mhz: opp-1056000000 { 587 opp-hz = /bits/ 64 <1056000000>; 588 opp-peak-kBps = <2188000 17817600>; 589 }; 590 591 cpu7_opp_1325mhz: opp-1324800000 { 592 opp-hz = /bits/ 64 <1324800000>; 593 opp-peak-kBps = <4068000 24576000>; 594 }; 595 596 cpu7_opp_1517mhz: opp-1516800000 { 597 opp-hz = /bits/ 64 <1516800000>; 598 opp-peak-kBps = <4068000 24576000>; 599 }; 600 601 cpu7_opp_1766mhz: opp-1766400000 { 602 opp-hz = /bits/ 64 <1766400000>; 603 opp-peak-kBps = <6220000 38092800>; 604 }; 605 606 cpu7_opp_1862mhz: opp-1862400000 { 607 opp-hz = /bits/ 64 <1862400000>; 608 opp-peak-kBps = <6220000 38092800>; 609 }; 610 611 cpu7_opp_2035mhz: opp-2035200000 { 612 opp-hz = /bits/ 64 <2035200000>; 613 opp-peak-kBps = <6220000 38092800>; 614 }; 615 616 cpu7_opp_2112mhz: opp-2112000000 { 617 opp-hz = /bits/ 64 <2112000000>; 618 opp-peak-kBps = <6220000 44851200>; 619 }; 620 621 cpu7_opp_2208mhz: opp-2208000000 { 622 opp-hz = /bits/ 64 <2208000000>; 623 opp-peak-kBps = <6220000 44851200>; 624 }; 625 626 cpu7_opp_2381mhz: opp-2380800000 { 627 opp-hz = /bits/ 64 <2380800000>; 628 opp-peak-kBps = <6832000 44851200>; 629 }; 630 631 cpu7_opp_2400mhz: opp-2400000000 { 632 opp-hz = /bits/ 64 <2400000000>; 633 opp-peak-kBps = <8532000 48537600>; 634 }; 635 636 cpu7_opp_2515mhz: opp-2515200000 { 637 opp-hz = /bits/ 64 <2515200000>; 638 opp-peak-kBps = <8532000 48537600>; 639 }; 640 641 cpu7_opp_2707mhz: opp-2707200000 { 642 opp-hz = /bits/ 64 <2707200000>; 643 opp-peak-kBps = <8532000 48537600>; 644 }; 645 646 cpu7_opp_3014mhz: opp-3014400000 { 647 opp-hz = /bits/ 64 <3014400000>; 648 opp-peak-kBps = <8532000 48537600>; 649 }; 650 }; 651 652 memory@80000000 { 653 device_type = "memory"; 654 /* We expect the bootloader to fill in the size */ 655 reg = <0 0x80000000 0 0>; 656 }; 657 658 firmware { 659 scm { 660 compatible = "qcom,scm-sc7280", "qcom,scm"; 661 }; 662 }; 663 664 clk_virt: interconnect { 665 compatible = "qcom,sc7280-clk-virt"; 666 #interconnect-cells = <2>; 667 qcom,bcm-voters = <&apps_bcm_voter>; 668 }; 669 670 smem { 671 compatible = "qcom,smem"; 672 memory-region = <&smem_mem>; 673 hwlocks = <&tcsr_mutex 3>; 674 }; 675 676 smp2p-adsp { 677 compatible = "qcom,smp2p"; 678 qcom,smem = <443>, <429>; 679 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 680 IPCC_MPROC_SIGNAL_SMP2P 681 IRQ_TYPE_EDGE_RISING>; 682 mboxes = <&ipcc IPCC_CLIENT_LPASS 683 IPCC_MPROC_SIGNAL_SMP2P>; 684 685 qcom,local-pid = <0>; 686 qcom,remote-pid = <2>; 687 688 adsp_smp2p_out: master-kernel { 689 qcom,entry-name = "master-kernel"; 690 #qcom,smem-state-cells = <1>; 691 }; 692 693 adsp_smp2p_in: slave-kernel { 694 qcom,entry-name = "slave-kernel"; 695 interrupt-controller; 696 #interrupt-cells = <2>; 697 }; 698 }; 699 700 smp2p-cdsp { 701 compatible = "qcom,smp2p"; 702 qcom,smem = <94>, <432>; 703 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 704 IPCC_MPROC_SIGNAL_SMP2P 705 IRQ_TYPE_EDGE_RISING>; 706 mboxes = <&ipcc IPCC_CLIENT_CDSP 707 IPCC_MPROC_SIGNAL_SMP2P>; 708 709 qcom,local-pid = <0>; 710 qcom,remote-pid = <5>; 711 712 cdsp_smp2p_out: master-kernel { 713 qcom,entry-name = "master-kernel"; 714 #qcom,smem-state-cells = <1>; 715 }; 716 717 cdsp_smp2p_in: slave-kernel { 718 qcom,entry-name = "slave-kernel"; 719 interrupt-controller; 720 #interrupt-cells = <2>; 721 }; 722 }; 723 724 smp2p-mpss { 725 compatible = "qcom,smp2p"; 726 qcom,smem = <435>, <428>; 727 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 728 IPCC_MPROC_SIGNAL_SMP2P 729 IRQ_TYPE_EDGE_RISING>; 730 mboxes = <&ipcc IPCC_CLIENT_MPSS 731 IPCC_MPROC_SIGNAL_SMP2P>; 732 733 qcom,local-pid = <0>; 734 qcom,remote-pid = <1>; 735 736 modem_smp2p_out: master-kernel { 737 qcom,entry-name = "master-kernel"; 738 #qcom,smem-state-cells = <1>; 739 }; 740 741 modem_smp2p_in: slave-kernel { 742 qcom,entry-name = "slave-kernel"; 743 interrupt-controller; 744 #interrupt-cells = <2>; 745 }; 746 747 ipa_smp2p_out: ipa-ap-to-modem { 748 qcom,entry-name = "ipa"; 749 #qcom,smem-state-cells = <1>; 750 }; 751 752 ipa_smp2p_in: ipa-modem-to-ap { 753 qcom,entry-name = "ipa"; 754 interrupt-controller; 755 #interrupt-cells = <2>; 756 }; 757 }; 758 759 smp2p-wpss { 760 compatible = "qcom,smp2p"; 761 qcom,smem = <617>, <616>; 762 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 763 IPCC_MPROC_SIGNAL_SMP2P 764 IRQ_TYPE_EDGE_RISING>; 765 mboxes = <&ipcc IPCC_CLIENT_WPSS 766 IPCC_MPROC_SIGNAL_SMP2P>; 767 768 qcom,local-pid = <0>; 769 qcom,remote-pid = <13>; 770 771 wpss_smp2p_out: master-kernel { 772 qcom,entry-name = "master-kernel"; 773 #qcom,smem-state-cells = <1>; 774 }; 775 776 wpss_smp2p_in: slave-kernel { 777 qcom,entry-name = "slave-kernel"; 778 interrupt-controller; 779 #interrupt-cells = <2>; 780 }; 781 782 wlan_smp2p_out: wlan-ap-to-wpss { 783 qcom,entry-name = "wlan"; 784 #qcom,smem-state-cells = <1>; 785 }; 786 787 wlan_smp2p_in: wlan-wpss-to-ap { 788 qcom,entry-name = "wlan"; 789 interrupt-controller; 790 #interrupt-cells = <2>; 791 }; 792 }; 793 794 pmu { 795 compatible = "arm,armv8-pmuv3"; 796 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 797 }; 798 799 psci { 800 compatible = "arm,psci-1.0"; 801 method = "smc"; 802 }; 803 804 qspi_opp_table: opp-table-qspi { 805 compatible = "operating-points-v2"; 806 807 opp-75000000 { 808 opp-hz = /bits/ 64 <75000000>; 809 required-opps = <&rpmhpd_opp_low_svs>; 810 }; 811 812 opp-150000000 { 813 opp-hz = /bits/ 64 <150000000>; 814 required-opps = <&rpmhpd_opp_svs>; 815 }; 816 817 opp-200000000 { 818 opp-hz = /bits/ 64 <200000000>; 819 required-opps = <&rpmhpd_opp_svs_l1>; 820 }; 821 822 opp-300000000 { 823 opp-hz = /bits/ 64 <300000000>; 824 required-opps = <&rpmhpd_opp_nom>; 825 }; 826 }; 827 828 qup_opp_table: opp-table-qup { 829 compatible = "operating-points-v2"; 830 831 opp-75000000 { 832 opp-hz = /bits/ 64 <75000000>; 833 required-opps = <&rpmhpd_opp_low_svs>; 834 }; 835 836 opp-100000000 { 837 opp-hz = /bits/ 64 <100000000>; 838 required-opps = <&rpmhpd_opp_svs>; 839 }; 840 841 opp-128000000 { 842 opp-hz = /bits/ 64 <128000000>; 843 required-opps = <&rpmhpd_opp_nom>; 844 }; 845 }; 846 847 soc: soc@0 { 848 #address-cells = <2>; 849 #size-cells = <2>; 850 ranges = <0 0 0 0 0x10 0>; 851 dma-ranges = <0 0 0 0 0x10 0>; 852 compatible = "simple-bus"; 853 854 gcc: clock-controller@100000 { 855 compatible = "qcom,gcc-sc7280"; 856 reg = <0 0x00100000 0 0x1f0000>; 857 clocks = <&rpmhcc RPMH_CXO_CLK>, 858 <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, 859 <0>, <&pcie1_lane>, 860 <0>, <0>, <0>, <0>; 861 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", 862 "pcie_0_pipe_clk", "pcie_1_pipe_clk", 863 "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk", 864 "ufs_phy_tx_symbol_0_clk", 865 "usb3_phy_wrapper_gcc_usb30_pipe_clk"; 866 #clock-cells = <1>; 867 #reset-cells = <1>; 868 #power-domain-cells = <1>; 869 power-domains = <&rpmhpd SC7280_CX>; 870 }; 871 872 ipcc: mailbox@408000 { 873 compatible = "qcom,sc7280-ipcc", "qcom,ipcc"; 874 reg = <0 0x00408000 0 0x1000>; 875 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 876 interrupt-controller; 877 #interrupt-cells = <3>; 878 #mbox-cells = <2>; 879 }; 880 881 qfprom: efuse@784000 { 882 compatible = "qcom,sc7280-qfprom", "qcom,qfprom"; 883 reg = <0 0x00784000 0 0xa20>, 884 <0 0x00780000 0 0xa20>, 885 <0 0x00782000 0 0x120>, 886 <0 0x00786000 0 0x1fff>; 887 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>; 888 clock-names = "core"; 889 power-domains = <&rpmhpd SC7280_MX>; 890 #address-cells = <1>; 891 #size-cells = <1>; 892 893 gpu_speed_bin: gpu_speed_bin@1e9 { 894 reg = <0x1e9 0x2>; 895 bits = <5 8>; 896 }; 897 }; 898 899 sdhc_1: mmc@7c4000 { 900 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 901 pinctrl-names = "default", "sleep"; 902 pinctrl-0 = <&sdc1_clk>, <&sdc1_cmd>, <&sdc1_data>, <&sdc1_rclk>; 903 pinctrl-1 = <&sdc1_clk_sleep>, <&sdc1_cmd_sleep>, <&sdc1_data_sleep>, <&sdc1_rclk_sleep>; 904 status = "disabled"; 905 906 reg = <0 0x007c4000 0 0x1000>, 907 <0 0x007c5000 0 0x1000>; 908 reg-names = "hc", "cqhci"; 909 910 iommus = <&apps_smmu 0xc0 0x0>; 911 interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>, 912 <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>; 913 interrupt-names = "hc_irq", "pwr_irq"; 914 915 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 916 <&gcc GCC_SDCC1_APPS_CLK>, 917 <&rpmhcc RPMH_CXO_CLK>; 918 clock-names = "iface", "core", "xo"; 919 interconnects = <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>, 920 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_1 0>; 921 interconnect-names = "sdhc-ddr","cpu-sdhc"; 922 power-domains = <&rpmhpd SC7280_CX>; 923 operating-points-v2 = <&sdhc1_opp_table>; 924 925 bus-width = <8>; 926 supports-cqe; 927 928 qcom,dll-config = <0x0007642c>; 929 qcom,ddr-config = <0x80040868>; 930 931 mmc-ddr-1_8v; 932 mmc-hs200-1_8v; 933 mmc-hs400-1_8v; 934 mmc-hs400-enhanced-strobe; 935 936 resets = <&gcc GCC_SDCC1_BCR>; 937 938 sdhc1_opp_table: opp-table { 939 compatible = "operating-points-v2"; 940 941 opp-100000000 { 942 opp-hz = /bits/ 64 <100000000>; 943 required-opps = <&rpmhpd_opp_low_svs>; 944 opp-peak-kBps = <1800000 400000>; 945 opp-avg-kBps = <100000 0>; 946 }; 947 948 opp-384000000 { 949 opp-hz = /bits/ 64 <384000000>; 950 required-opps = <&rpmhpd_opp_nom>; 951 opp-peak-kBps = <5400000 1600000>; 952 opp-avg-kBps = <390000 0>; 953 }; 954 }; 955 }; 956 957 gpi_dma0: dma-controller@900000 { 958 #dma-cells = <3>; 959 compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma"; 960 reg = <0 0x00900000 0 0x60000>; 961 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 962 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 963 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 964 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 965 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 966 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 967 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 968 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 969 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 970 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 971 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 972 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 973 dma-channels = <12>; 974 dma-channel-mask = <0x7f>; 975 iommus = <&apps_smmu 0x0136 0x0>; 976 status = "disabled"; 977 }; 978 979 qupv3_id_0: geniqup@9c0000 { 980 compatible = "qcom,geni-se-qup"; 981 reg = <0 0x009c0000 0 0x2000>; 982 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 983 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 984 clock-names = "m-ahb", "s-ahb"; 985 #address-cells = <2>; 986 #size-cells = <2>; 987 ranges; 988 iommus = <&apps_smmu 0x123 0x0>; 989 status = "disabled"; 990 991 i2c0: i2c@980000 { 992 compatible = "qcom,geni-i2c"; 993 reg = <0 0x00980000 0 0x4000>; 994 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 995 clock-names = "se"; 996 pinctrl-names = "default"; 997 pinctrl-0 = <&qup_i2c0_data_clk>; 998 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 999 #address-cells = <1>; 1000 #size-cells = <0>; 1001 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1002 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1003 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1004 interconnect-names = "qup-core", "qup-config", 1005 "qup-memory"; 1006 power-domains = <&rpmhpd SC7280_CX>; 1007 required-opps = <&rpmhpd_opp_low_svs>; 1008 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1009 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1010 dma-names = "tx", "rx"; 1011 status = "disabled"; 1012 }; 1013 1014 spi0: spi@980000 { 1015 compatible = "qcom,geni-spi"; 1016 reg = <0 0x00980000 0 0x4000>; 1017 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1018 clock-names = "se"; 1019 pinctrl-names = "default"; 1020 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 1021 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1022 #address-cells = <1>; 1023 #size-cells = <0>; 1024 power-domains = <&rpmhpd SC7280_CX>; 1025 operating-points-v2 = <&qup_opp_table>; 1026 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1027 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1028 interconnect-names = "qup-core", "qup-config"; 1029 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1030 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1031 dma-names = "tx", "rx"; 1032 status = "disabled"; 1033 }; 1034 1035 uart0: serial@980000 { 1036 compatible = "qcom,geni-uart"; 1037 reg = <0 0x00980000 0 0x4000>; 1038 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1039 clock-names = "se"; 1040 pinctrl-names = "default"; 1041 pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, <&qup_uart0_tx>, <&qup_uart0_rx>; 1042 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1043 power-domains = <&rpmhpd SC7280_CX>; 1044 operating-points-v2 = <&qup_opp_table>; 1045 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1046 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1047 interconnect-names = "qup-core", "qup-config"; 1048 status = "disabled"; 1049 }; 1050 1051 i2c1: i2c@984000 { 1052 compatible = "qcom,geni-i2c"; 1053 reg = <0 0x00984000 0 0x4000>; 1054 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1055 clock-names = "se"; 1056 pinctrl-names = "default"; 1057 pinctrl-0 = <&qup_i2c1_data_clk>; 1058 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1059 #address-cells = <1>; 1060 #size-cells = <0>; 1061 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1062 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1063 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1064 interconnect-names = "qup-core", "qup-config", 1065 "qup-memory"; 1066 power-domains = <&rpmhpd SC7280_CX>; 1067 required-opps = <&rpmhpd_opp_low_svs>; 1068 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1069 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1070 dma-names = "tx", "rx"; 1071 status = "disabled"; 1072 }; 1073 1074 spi1: spi@984000 { 1075 compatible = "qcom,geni-spi"; 1076 reg = <0 0x00984000 0 0x4000>; 1077 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1078 clock-names = "se"; 1079 pinctrl-names = "default"; 1080 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1081 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1082 #address-cells = <1>; 1083 #size-cells = <0>; 1084 power-domains = <&rpmhpd SC7280_CX>; 1085 operating-points-v2 = <&qup_opp_table>; 1086 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1087 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1088 interconnect-names = "qup-core", "qup-config"; 1089 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1090 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1091 dma-names = "tx", "rx"; 1092 status = "disabled"; 1093 }; 1094 1095 uart1: serial@984000 { 1096 compatible = "qcom,geni-uart"; 1097 reg = <0 0x00984000 0 0x4000>; 1098 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1099 clock-names = "se"; 1100 pinctrl-names = "default"; 1101 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>; 1102 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1103 power-domains = <&rpmhpd SC7280_CX>; 1104 operating-points-v2 = <&qup_opp_table>; 1105 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1106 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1107 interconnect-names = "qup-core", "qup-config"; 1108 status = "disabled"; 1109 }; 1110 1111 i2c2: i2c@988000 { 1112 compatible = "qcom,geni-i2c"; 1113 reg = <0 0x00988000 0 0x4000>; 1114 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1115 clock-names = "se"; 1116 pinctrl-names = "default"; 1117 pinctrl-0 = <&qup_i2c2_data_clk>; 1118 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1119 #address-cells = <1>; 1120 #size-cells = <0>; 1121 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1122 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1123 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1124 interconnect-names = "qup-core", "qup-config", 1125 "qup-memory"; 1126 power-domains = <&rpmhpd SC7280_CX>; 1127 required-opps = <&rpmhpd_opp_low_svs>; 1128 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1129 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1130 dma-names = "tx", "rx"; 1131 status = "disabled"; 1132 }; 1133 1134 spi2: spi@988000 { 1135 compatible = "qcom,geni-spi"; 1136 reg = <0 0x00988000 0 0x4000>; 1137 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1138 clock-names = "se"; 1139 pinctrl-names = "default"; 1140 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1141 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1142 #address-cells = <1>; 1143 #size-cells = <0>; 1144 power-domains = <&rpmhpd SC7280_CX>; 1145 operating-points-v2 = <&qup_opp_table>; 1146 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1147 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1148 interconnect-names = "qup-core", "qup-config"; 1149 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1150 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1151 dma-names = "tx", "rx"; 1152 status = "disabled"; 1153 }; 1154 1155 uart2: serial@988000 { 1156 compatible = "qcom,geni-uart"; 1157 reg = <0 0x00988000 0 0x4000>; 1158 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1159 clock-names = "se"; 1160 pinctrl-names = "default"; 1161 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, <&qup_uart2_tx>, <&qup_uart2_rx>; 1162 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1163 power-domains = <&rpmhpd SC7280_CX>; 1164 operating-points-v2 = <&qup_opp_table>; 1165 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1166 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1167 interconnect-names = "qup-core", "qup-config"; 1168 status = "disabled"; 1169 }; 1170 1171 i2c3: i2c@98c000 { 1172 compatible = "qcom,geni-i2c"; 1173 reg = <0 0x0098c000 0 0x4000>; 1174 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1175 clock-names = "se"; 1176 pinctrl-names = "default"; 1177 pinctrl-0 = <&qup_i2c3_data_clk>; 1178 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1179 #address-cells = <1>; 1180 #size-cells = <0>; 1181 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1182 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1183 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1184 interconnect-names = "qup-core", "qup-config", 1185 "qup-memory"; 1186 power-domains = <&rpmhpd SC7280_CX>; 1187 required-opps = <&rpmhpd_opp_low_svs>; 1188 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1189 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1190 dma-names = "tx", "rx"; 1191 status = "disabled"; 1192 }; 1193 1194 spi3: spi@98c000 { 1195 compatible = "qcom,geni-spi"; 1196 reg = <0 0x0098c000 0 0x4000>; 1197 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1198 clock-names = "se"; 1199 pinctrl-names = "default"; 1200 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 1201 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1202 #address-cells = <1>; 1203 #size-cells = <0>; 1204 power-domains = <&rpmhpd SC7280_CX>; 1205 operating-points-v2 = <&qup_opp_table>; 1206 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1207 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1208 interconnect-names = "qup-core", "qup-config"; 1209 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1210 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1211 dma-names = "tx", "rx"; 1212 status = "disabled"; 1213 }; 1214 1215 uart3: serial@98c000 { 1216 compatible = "qcom,geni-uart"; 1217 reg = <0 0x0098c000 0 0x4000>; 1218 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1219 clock-names = "se"; 1220 pinctrl-names = "default"; 1221 pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, <&qup_uart3_tx>, <&qup_uart3_rx>; 1222 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1223 power-domains = <&rpmhpd SC7280_CX>; 1224 operating-points-v2 = <&qup_opp_table>; 1225 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1226 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1227 interconnect-names = "qup-core", "qup-config"; 1228 status = "disabled"; 1229 }; 1230 1231 i2c4: i2c@990000 { 1232 compatible = "qcom,geni-i2c"; 1233 reg = <0 0x00990000 0 0x4000>; 1234 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1235 clock-names = "se"; 1236 pinctrl-names = "default"; 1237 pinctrl-0 = <&qup_i2c4_data_clk>; 1238 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1239 #address-cells = <1>; 1240 #size-cells = <0>; 1241 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1242 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1243 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1244 interconnect-names = "qup-core", "qup-config", 1245 "qup-memory"; 1246 power-domains = <&rpmhpd SC7280_CX>; 1247 required-opps = <&rpmhpd_opp_low_svs>; 1248 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1249 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1250 dma-names = "tx", "rx"; 1251 status = "disabled"; 1252 }; 1253 1254 spi4: spi@990000 { 1255 compatible = "qcom,geni-spi"; 1256 reg = <0 0x00990000 0 0x4000>; 1257 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1258 clock-names = "se"; 1259 pinctrl-names = "default"; 1260 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1261 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1262 #address-cells = <1>; 1263 #size-cells = <0>; 1264 power-domains = <&rpmhpd SC7280_CX>; 1265 operating-points-v2 = <&qup_opp_table>; 1266 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1267 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1268 interconnect-names = "qup-core", "qup-config"; 1269 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1270 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1271 dma-names = "tx", "rx"; 1272 status = "disabled"; 1273 }; 1274 1275 uart4: serial@990000 { 1276 compatible = "qcom,geni-uart"; 1277 reg = <0 0x00990000 0 0x4000>; 1278 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1279 clock-names = "se"; 1280 pinctrl-names = "default"; 1281 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, <&qup_uart4_tx>, <&qup_uart4_rx>; 1282 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1283 power-domains = <&rpmhpd SC7280_CX>; 1284 operating-points-v2 = <&qup_opp_table>; 1285 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1286 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1287 interconnect-names = "qup-core", "qup-config"; 1288 status = "disabled"; 1289 }; 1290 1291 i2c5: i2c@994000 { 1292 compatible = "qcom,geni-i2c"; 1293 reg = <0 0x00994000 0 0x4000>; 1294 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1295 clock-names = "se"; 1296 pinctrl-names = "default"; 1297 pinctrl-0 = <&qup_i2c5_data_clk>; 1298 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1299 #address-cells = <1>; 1300 #size-cells = <0>; 1301 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1302 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1303 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1304 interconnect-names = "qup-core", "qup-config", 1305 "qup-memory"; 1306 power-domains = <&rpmhpd SC7280_CX>; 1307 required-opps = <&rpmhpd_opp_low_svs>; 1308 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1309 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1310 dma-names = "tx", "rx"; 1311 status = "disabled"; 1312 }; 1313 1314 spi5: spi@994000 { 1315 compatible = "qcom,geni-spi"; 1316 reg = <0 0x00994000 0 0x4000>; 1317 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1318 clock-names = "se"; 1319 pinctrl-names = "default"; 1320 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 1321 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1322 #address-cells = <1>; 1323 #size-cells = <0>; 1324 power-domains = <&rpmhpd SC7280_CX>; 1325 operating-points-v2 = <&qup_opp_table>; 1326 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1327 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1328 interconnect-names = "qup-core", "qup-config"; 1329 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1330 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1331 dma-names = "tx", "rx"; 1332 status = "disabled"; 1333 }; 1334 1335 uart5: serial@994000 { 1336 compatible = "qcom,geni-uart"; 1337 reg = <0 0x00994000 0 0x4000>; 1338 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1339 clock-names = "se"; 1340 pinctrl-names = "default"; 1341 pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, <&qup_uart5_tx>, <&qup_uart5_rx>; 1342 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1343 power-domains = <&rpmhpd SC7280_CX>; 1344 operating-points-v2 = <&qup_opp_table>; 1345 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1346 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1347 interconnect-names = "qup-core", "qup-config"; 1348 status = "disabled"; 1349 }; 1350 1351 i2c6: i2c@998000 { 1352 compatible = "qcom,geni-i2c"; 1353 reg = <0 0x00998000 0 0x4000>; 1354 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1355 clock-names = "se"; 1356 pinctrl-names = "default"; 1357 pinctrl-0 = <&qup_i2c6_data_clk>; 1358 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1359 #address-cells = <1>; 1360 #size-cells = <0>; 1361 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1362 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1363 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1364 interconnect-names = "qup-core", "qup-config", 1365 "qup-memory"; 1366 power-domains = <&rpmhpd SC7280_CX>; 1367 required-opps = <&rpmhpd_opp_low_svs>; 1368 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1369 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1370 dma-names = "tx", "rx"; 1371 status = "disabled"; 1372 }; 1373 1374 spi6: spi@998000 { 1375 compatible = "qcom,geni-spi"; 1376 reg = <0 0x00998000 0 0x4000>; 1377 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1378 clock-names = "se"; 1379 pinctrl-names = "default"; 1380 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1381 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1382 #address-cells = <1>; 1383 #size-cells = <0>; 1384 power-domains = <&rpmhpd SC7280_CX>; 1385 operating-points-v2 = <&qup_opp_table>; 1386 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1387 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1388 interconnect-names = "qup-core", "qup-config"; 1389 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1390 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1391 dma-names = "tx", "rx"; 1392 status = "disabled"; 1393 }; 1394 1395 uart6: serial@998000 { 1396 compatible = "qcom,geni-uart"; 1397 reg = <0 0x00998000 0 0x4000>; 1398 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1399 clock-names = "se"; 1400 pinctrl-names = "default"; 1401 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, <&qup_uart6_tx>, <&qup_uart6_rx>; 1402 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1403 power-domains = <&rpmhpd SC7280_CX>; 1404 operating-points-v2 = <&qup_opp_table>; 1405 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1406 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1407 interconnect-names = "qup-core", "qup-config"; 1408 status = "disabled"; 1409 }; 1410 1411 i2c7: i2c@99c000 { 1412 compatible = "qcom,geni-i2c"; 1413 reg = <0 0x0099c000 0 0x4000>; 1414 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1415 clock-names = "se"; 1416 pinctrl-names = "default"; 1417 pinctrl-0 = <&qup_i2c7_data_clk>; 1418 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1419 #address-cells = <1>; 1420 #size-cells = <0>; 1421 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1422 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1423 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1424 interconnect-names = "qup-core", "qup-config", 1425 "qup-memory"; 1426 power-domains = <&rpmhpd SC7280_CX>; 1427 required-opps = <&rpmhpd_opp_low_svs>; 1428 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1429 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1430 dma-names = "tx", "rx"; 1431 status = "disabled"; 1432 }; 1433 1434 spi7: spi@99c000 { 1435 compatible = "qcom,geni-spi"; 1436 reg = <0 0x0099c000 0 0x4000>; 1437 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1438 clock-names = "se"; 1439 pinctrl-names = "default"; 1440 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 1441 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1442 #address-cells = <1>; 1443 #size-cells = <0>; 1444 power-domains = <&rpmhpd SC7280_CX>; 1445 operating-points-v2 = <&qup_opp_table>; 1446 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1447 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1448 interconnect-names = "qup-core", "qup-config"; 1449 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1450 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1451 dma-names = "tx", "rx"; 1452 status = "disabled"; 1453 }; 1454 1455 uart7: serial@99c000 { 1456 compatible = "qcom,geni-uart"; 1457 reg = <0 0x0099c000 0 0x4000>; 1458 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1459 clock-names = "se"; 1460 pinctrl-names = "default"; 1461 pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, <&qup_uart7_tx>, <&qup_uart7_rx>; 1462 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1463 power-domains = <&rpmhpd SC7280_CX>; 1464 operating-points-v2 = <&qup_opp_table>; 1465 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1466 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1467 interconnect-names = "qup-core", "qup-config"; 1468 status = "disabled"; 1469 }; 1470 }; 1471 1472 gpi_dma1: dma-controller@a00000 { 1473 #dma-cells = <3>; 1474 compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma"; 1475 reg = <0 0x00a00000 0 0x60000>; 1476 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1477 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1478 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1479 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1480 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1481 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1482 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1483 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1484 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1485 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1486 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1487 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1488 dma-channels = <12>; 1489 dma-channel-mask = <0x1e>; 1490 iommus = <&apps_smmu 0x56 0x0>; 1491 status = "disabled"; 1492 }; 1493 1494 qupv3_id_1: geniqup@ac0000 { 1495 compatible = "qcom,geni-se-qup"; 1496 reg = <0 0x00ac0000 0 0x2000>; 1497 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1498 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1499 clock-names = "m-ahb", "s-ahb"; 1500 #address-cells = <2>; 1501 #size-cells = <2>; 1502 ranges; 1503 iommus = <&apps_smmu 0x43 0x0>; 1504 status = "disabled"; 1505 1506 i2c8: i2c@a80000 { 1507 compatible = "qcom,geni-i2c"; 1508 reg = <0 0x00a80000 0 0x4000>; 1509 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1510 clock-names = "se"; 1511 pinctrl-names = "default"; 1512 pinctrl-0 = <&qup_i2c8_data_clk>; 1513 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1514 #address-cells = <1>; 1515 #size-cells = <0>; 1516 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1517 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1518 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1519 interconnect-names = "qup-core", "qup-config", 1520 "qup-memory"; 1521 power-domains = <&rpmhpd SC7280_CX>; 1522 required-opps = <&rpmhpd_opp_low_svs>; 1523 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1524 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1525 dma-names = "tx", "rx"; 1526 status = "disabled"; 1527 }; 1528 1529 spi8: spi@a80000 { 1530 compatible = "qcom,geni-spi"; 1531 reg = <0 0x00a80000 0 0x4000>; 1532 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1533 clock-names = "se"; 1534 pinctrl-names = "default"; 1535 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1536 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1537 #address-cells = <1>; 1538 #size-cells = <0>; 1539 power-domains = <&rpmhpd SC7280_CX>; 1540 operating-points-v2 = <&qup_opp_table>; 1541 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1542 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1543 interconnect-names = "qup-core", "qup-config"; 1544 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1545 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1546 dma-names = "tx", "rx"; 1547 status = "disabled"; 1548 }; 1549 1550 uart8: serial@a80000 { 1551 compatible = "qcom,geni-uart"; 1552 reg = <0 0x00a80000 0 0x4000>; 1553 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1554 clock-names = "se"; 1555 pinctrl-names = "default"; 1556 pinctrl-0 = <&qup_uart8_cts>, <&qup_uart8_rts>, <&qup_uart8_tx>, <&qup_uart8_rx>; 1557 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1558 power-domains = <&rpmhpd SC7280_CX>; 1559 operating-points-v2 = <&qup_opp_table>; 1560 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1561 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1562 interconnect-names = "qup-core", "qup-config"; 1563 status = "disabled"; 1564 }; 1565 1566 i2c9: i2c@a84000 { 1567 compatible = "qcom,geni-i2c"; 1568 reg = <0 0x00a84000 0 0x4000>; 1569 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1570 clock-names = "se"; 1571 pinctrl-names = "default"; 1572 pinctrl-0 = <&qup_i2c9_data_clk>; 1573 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1574 #address-cells = <1>; 1575 #size-cells = <0>; 1576 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1577 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1578 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1579 interconnect-names = "qup-core", "qup-config", 1580 "qup-memory"; 1581 power-domains = <&rpmhpd SC7280_CX>; 1582 required-opps = <&rpmhpd_opp_low_svs>; 1583 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1584 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1585 dma-names = "tx", "rx"; 1586 status = "disabled"; 1587 }; 1588 1589 spi9: spi@a84000 { 1590 compatible = "qcom,geni-spi"; 1591 reg = <0 0x00a84000 0 0x4000>; 1592 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1593 clock-names = "se"; 1594 pinctrl-names = "default"; 1595 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1596 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1597 #address-cells = <1>; 1598 #size-cells = <0>; 1599 power-domains = <&rpmhpd SC7280_CX>; 1600 operating-points-v2 = <&qup_opp_table>; 1601 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1602 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1603 interconnect-names = "qup-core", "qup-config"; 1604 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1605 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1606 dma-names = "tx", "rx"; 1607 status = "disabled"; 1608 }; 1609 1610 uart9: serial@a84000 { 1611 compatible = "qcom,geni-uart"; 1612 reg = <0 0x00a84000 0 0x4000>; 1613 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1614 clock-names = "se"; 1615 pinctrl-names = "default"; 1616 pinctrl-0 = <&qup_uart9_cts>, <&qup_uart9_rts>, <&qup_uart9_tx>, <&qup_uart9_rx>; 1617 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1618 power-domains = <&rpmhpd SC7280_CX>; 1619 operating-points-v2 = <&qup_opp_table>; 1620 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1621 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1622 interconnect-names = "qup-core", "qup-config"; 1623 status = "disabled"; 1624 }; 1625 1626 i2c10: i2c@a88000 { 1627 compatible = "qcom,geni-i2c"; 1628 reg = <0 0x00a88000 0 0x4000>; 1629 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1630 clock-names = "se"; 1631 pinctrl-names = "default"; 1632 pinctrl-0 = <&qup_i2c10_data_clk>; 1633 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1634 #address-cells = <1>; 1635 #size-cells = <0>; 1636 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1637 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1638 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1639 interconnect-names = "qup-core", "qup-config", 1640 "qup-memory"; 1641 power-domains = <&rpmhpd SC7280_CX>; 1642 required-opps = <&rpmhpd_opp_low_svs>; 1643 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1644 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1645 dma-names = "tx", "rx"; 1646 status = "disabled"; 1647 }; 1648 1649 spi10: spi@a88000 { 1650 compatible = "qcom,geni-spi"; 1651 reg = <0 0x00a88000 0 0x4000>; 1652 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1653 clock-names = "se"; 1654 pinctrl-names = "default"; 1655 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1656 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1657 #address-cells = <1>; 1658 #size-cells = <0>; 1659 power-domains = <&rpmhpd SC7280_CX>; 1660 operating-points-v2 = <&qup_opp_table>; 1661 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1662 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1663 interconnect-names = "qup-core", "qup-config"; 1664 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1665 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1666 dma-names = "tx", "rx"; 1667 status = "disabled"; 1668 }; 1669 1670 uart10: serial@a88000 { 1671 compatible = "qcom,geni-uart"; 1672 reg = <0 0x00a88000 0 0x4000>; 1673 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1674 clock-names = "se"; 1675 pinctrl-names = "default"; 1676 pinctrl-0 = <&qup_uart10_cts>, <&qup_uart10_rts>, <&qup_uart10_tx>, <&qup_uart10_rx>; 1677 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1678 power-domains = <&rpmhpd SC7280_CX>; 1679 operating-points-v2 = <&qup_opp_table>; 1680 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1681 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1682 interconnect-names = "qup-core", "qup-config"; 1683 status = "disabled"; 1684 }; 1685 1686 i2c11: i2c@a8c000 { 1687 compatible = "qcom,geni-i2c"; 1688 reg = <0 0x00a8c000 0 0x4000>; 1689 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1690 clock-names = "se"; 1691 pinctrl-names = "default"; 1692 pinctrl-0 = <&qup_i2c11_data_clk>; 1693 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1694 #address-cells = <1>; 1695 #size-cells = <0>; 1696 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1697 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1698 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1699 interconnect-names = "qup-core", "qup-config", 1700 "qup-memory"; 1701 power-domains = <&rpmhpd SC7280_CX>; 1702 required-opps = <&rpmhpd_opp_low_svs>; 1703 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1704 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1705 dma-names = "tx", "rx"; 1706 status = "disabled"; 1707 }; 1708 1709 spi11: spi@a8c000 { 1710 compatible = "qcom,geni-spi"; 1711 reg = <0 0x00a8c000 0 0x4000>; 1712 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1713 clock-names = "se"; 1714 pinctrl-names = "default"; 1715 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1716 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1717 #address-cells = <1>; 1718 #size-cells = <0>; 1719 power-domains = <&rpmhpd SC7280_CX>; 1720 operating-points-v2 = <&qup_opp_table>; 1721 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1722 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1723 interconnect-names = "qup-core", "qup-config"; 1724 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1725 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1726 dma-names = "tx", "rx"; 1727 status = "disabled"; 1728 }; 1729 1730 uart11: serial@a8c000 { 1731 compatible = "qcom,geni-uart"; 1732 reg = <0 0x00a8c000 0 0x4000>; 1733 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1734 clock-names = "se"; 1735 pinctrl-names = "default"; 1736 pinctrl-0 = <&qup_uart11_cts>, <&qup_uart11_rts>, <&qup_uart11_tx>, <&qup_uart11_rx>; 1737 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1738 power-domains = <&rpmhpd SC7280_CX>; 1739 operating-points-v2 = <&qup_opp_table>; 1740 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1741 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1742 interconnect-names = "qup-core", "qup-config"; 1743 status = "disabled"; 1744 }; 1745 1746 i2c12: i2c@a90000 { 1747 compatible = "qcom,geni-i2c"; 1748 reg = <0 0x00a90000 0 0x4000>; 1749 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1750 clock-names = "se"; 1751 pinctrl-names = "default"; 1752 pinctrl-0 = <&qup_i2c12_data_clk>; 1753 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1754 #address-cells = <1>; 1755 #size-cells = <0>; 1756 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1757 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1758 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1759 interconnect-names = "qup-core", "qup-config", 1760 "qup-memory"; 1761 power-domains = <&rpmhpd SC7280_CX>; 1762 required-opps = <&rpmhpd_opp_low_svs>; 1763 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1764 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1765 dma-names = "tx", "rx"; 1766 status = "disabled"; 1767 }; 1768 1769 spi12: spi@a90000 { 1770 compatible = "qcom,geni-spi"; 1771 reg = <0 0x00a90000 0 0x4000>; 1772 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1773 clock-names = "se"; 1774 pinctrl-names = "default"; 1775 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1776 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1777 #address-cells = <1>; 1778 #size-cells = <0>; 1779 power-domains = <&rpmhpd SC7280_CX>; 1780 operating-points-v2 = <&qup_opp_table>; 1781 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1782 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1783 interconnect-names = "qup-core", "qup-config"; 1784 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1785 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1786 dma-names = "tx", "rx"; 1787 status = "disabled"; 1788 }; 1789 1790 uart12: serial@a90000 { 1791 compatible = "qcom,geni-uart"; 1792 reg = <0 0x00a90000 0 0x4000>; 1793 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1794 clock-names = "se"; 1795 pinctrl-names = "default"; 1796 pinctrl-0 = <&qup_uart12_cts>, <&qup_uart12_rts>, <&qup_uart12_tx>, <&qup_uart12_rx>; 1797 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1798 power-domains = <&rpmhpd SC7280_CX>; 1799 operating-points-v2 = <&qup_opp_table>; 1800 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1801 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1802 interconnect-names = "qup-core", "qup-config"; 1803 status = "disabled"; 1804 }; 1805 1806 i2c13: i2c@a94000 { 1807 compatible = "qcom,geni-i2c"; 1808 reg = <0 0x00a94000 0 0x4000>; 1809 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1810 clock-names = "se"; 1811 pinctrl-names = "default"; 1812 pinctrl-0 = <&qup_i2c13_data_clk>; 1813 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1814 #address-cells = <1>; 1815 #size-cells = <0>; 1816 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1817 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1818 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1819 interconnect-names = "qup-core", "qup-config", 1820 "qup-memory"; 1821 power-domains = <&rpmhpd SC7280_CX>; 1822 required-opps = <&rpmhpd_opp_low_svs>; 1823 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1824 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1825 dma-names = "tx", "rx"; 1826 status = "disabled"; 1827 }; 1828 1829 spi13: spi@a94000 { 1830 compatible = "qcom,geni-spi"; 1831 reg = <0 0x00a94000 0 0x4000>; 1832 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1833 clock-names = "se"; 1834 pinctrl-names = "default"; 1835 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1836 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1837 #address-cells = <1>; 1838 #size-cells = <0>; 1839 power-domains = <&rpmhpd SC7280_CX>; 1840 operating-points-v2 = <&qup_opp_table>; 1841 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1842 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1843 interconnect-names = "qup-core", "qup-config"; 1844 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1845 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1846 dma-names = "tx", "rx"; 1847 status = "disabled"; 1848 }; 1849 1850 uart13: serial@a94000 { 1851 compatible = "qcom,geni-uart"; 1852 reg = <0 0x00a94000 0 0x4000>; 1853 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1854 clock-names = "se"; 1855 pinctrl-names = "default"; 1856 pinctrl-0 = <&qup_uart13_cts>, <&qup_uart13_rts>, <&qup_uart13_tx>, <&qup_uart13_rx>; 1857 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1858 power-domains = <&rpmhpd SC7280_CX>; 1859 operating-points-v2 = <&qup_opp_table>; 1860 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1861 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1862 interconnect-names = "qup-core", "qup-config"; 1863 status = "disabled"; 1864 }; 1865 1866 i2c14: i2c@a98000 { 1867 compatible = "qcom,geni-i2c"; 1868 reg = <0 0x00a98000 0 0x4000>; 1869 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1870 clock-names = "se"; 1871 pinctrl-names = "default"; 1872 pinctrl-0 = <&qup_i2c14_data_clk>; 1873 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1874 #address-cells = <1>; 1875 #size-cells = <0>; 1876 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1877 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1878 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1879 interconnect-names = "qup-core", "qup-config", 1880 "qup-memory"; 1881 power-domains = <&rpmhpd SC7280_CX>; 1882 required-opps = <&rpmhpd_opp_low_svs>; 1883 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1884 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1885 dma-names = "tx", "rx"; 1886 status = "disabled"; 1887 }; 1888 1889 spi14: spi@a98000 { 1890 compatible = "qcom,geni-spi"; 1891 reg = <0 0x00a98000 0 0x4000>; 1892 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1893 clock-names = "se"; 1894 pinctrl-names = "default"; 1895 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 1896 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1897 #address-cells = <1>; 1898 #size-cells = <0>; 1899 power-domains = <&rpmhpd SC7280_CX>; 1900 operating-points-v2 = <&qup_opp_table>; 1901 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1902 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1903 interconnect-names = "qup-core", "qup-config"; 1904 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 1905 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 1906 dma-names = "tx", "rx"; 1907 status = "disabled"; 1908 }; 1909 1910 uart14: serial@a98000 { 1911 compatible = "qcom,geni-uart"; 1912 reg = <0 0x00a98000 0 0x4000>; 1913 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1914 clock-names = "se"; 1915 pinctrl-names = "default"; 1916 pinctrl-0 = <&qup_uart14_cts>, <&qup_uart14_rts>, <&qup_uart14_tx>, <&qup_uart14_rx>; 1917 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1918 power-domains = <&rpmhpd SC7280_CX>; 1919 operating-points-v2 = <&qup_opp_table>; 1920 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1921 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1922 interconnect-names = "qup-core", "qup-config"; 1923 status = "disabled"; 1924 }; 1925 1926 i2c15: i2c@a9c000 { 1927 compatible = "qcom,geni-i2c"; 1928 reg = <0 0x00a9c000 0 0x4000>; 1929 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1930 clock-names = "se"; 1931 pinctrl-names = "default"; 1932 pinctrl-0 = <&qup_i2c15_data_clk>; 1933 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1934 #address-cells = <1>; 1935 #size-cells = <0>; 1936 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1937 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1938 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1939 interconnect-names = "qup-core", "qup-config", 1940 "qup-memory"; 1941 power-domains = <&rpmhpd SC7280_CX>; 1942 required-opps = <&rpmhpd_opp_low_svs>; 1943 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, 1944 <&gpi_dma1 1 7 QCOM_GPI_I2C>; 1945 dma-names = "tx", "rx"; 1946 status = "disabled"; 1947 }; 1948 1949 spi15: spi@a9c000 { 1950 compatible = "qcom,geni-spi"; 1951 reg = <0 0x00a9c000 0 0x4000>; 1952 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1953 clock-names = "se"; 1954 pinctrl-names = "default"; 1955 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 1956 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1957 #address-cells = <1>; 1958 #size-cells = <0>; 1959 power-domains = <&rpmhpd SC7280_CX>; 1960 operating-points-v2 = <&qup_opp_table>; 1961 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1962 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1963 interconnect-names = "qup-core", "qup-config"; 1964 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, 1965 <&gpi_dma1 1 7 QCOM_GPI_SPI>; 1966 dma-names = "tx", "rx"; 1967 status = "disabled"; 1968 }; 1969 1970 uart15: serial@a9c000 { 1971 compatible = "qcom,geni-uart"; 1972 reg = <0 0x00a9c000 0 0x4000>; 1973 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1974 clock-names = "se"; 1975 pinctrl-names = "default"; 1976 pinctrl-0 = <&qup_uart15_cts>, <&qup_uart15_rts>, <&qup_uart15_tx>, <&qup_uart15_rx>; 1977 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1978 power-domains = <&rpmhpd SC7280_CX>; 1979 operating-points-v2 = <&qup_opp_table>; 1980 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1981 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1982 interconnect-names = "qup-core", "qup-config"; 1983 status = "disabled"; 1984 }; 1985 }; 1986 1987 cnoc2: interconnect@1500000 { 1988 reg = <0 0x01500000 0 0x1000>; 1989 compatible = "qcom,sc7280-cnoc2"; 1990 #interconnect-cells = <2>; 1991 qcom,bcm-voters = <&apps_bcm_voter>; 1992 }; 1993 1994 cnoc3: interconnect@1502000 { 1995 reg = <0 0x01502000 0 0x1000>; 1996 compatible = "qcom,sc7280-cnoc3"; 1997 #interconnect-cells = <2>; 1998 qcom,bcm-voters = <&apps_bcm_voter>; 1999 }; 2000 2001 mc_virt: interconnect@1580000 { 2002 reg = <0 0x01580000 0 0x4>; 2003 compatible = "qcom,sc7280-mc-virt"; 2004 #interconnect-cells = <2>; 2005 qcom,bcm-voters = <&apps_bcm_voter>; 2006 }; 2007 2008 system_noc: interconnect@1680000 { 2009 reg = <0 0x01680000 0 0x15480>; 2010 compatible = "qcom,sc7280-system-noc"; 2011 #interconnect-cells = <2>; 2012 qcom,bcm-voters = <&apps_bcm_voter>; 2013 }; 2014 2015 aggre1_noc: interconnect@16e0000 { 2016 compatible = "qcom,sc7280-aggre1-noc"; 2017 reg = <0 0x016e0000 0 0x1c080>; 2018 #interconnect-cells = <2>; 2019 qcom,bcm-voters = <&apps_bcm_voter>; 2020 }; 2021 2022 aggre2_noc: interconnect@1700000 { 2023 reg = <0 0x01700000 0 0x2b080>; 2024 compatible = "qcom,sc7280-aggre2-noc"; 2025 #interconnect-cells = <2>; 2026 qcom,bcm-voters = <&apps_bcm_voter>; 2027 }; 2028 2029 mmss_noc: interconnect@1740000 { 2030 reg = <0 0x01740000 0 0x1e080>; 2031 compatible = "qcom,sc7280-mmss-noc"; 2032 #interconnect-cells = <2>; 2033 qcom,bcm-voters = <&apps_bcm_voter>; 2034 }; 2035 2036 wifi: wifi@17a10040 { 2037 compatible = "qcom,wcn6750-wifi"; 2038 reg = <0 0x17a10040 0 0x0>; 2039 iommus = <&apps_smmu 0x1c00 0x1>; 2040 interrupts = <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>, 2041 <GIC_SPI 769 IRQ_TYPE_EDGE_RISING>, 2042 <GIC_SPI 770 IRQ_TYPE_EDGE_RISING>, 2043 <GIC_SPI 771 IRQ_TYPE_EDGE_RISING>, 2044 <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>, 2045 <GIC_SPI 773 IRQ_TYPE_EDGE_RISING>, 2046 <GIC_SPI 774 IRQ_TYPE_EDGE_RISING>, 2047 <GIC_SPI 775 IRQ_TYPE_EDGE_RISING>, 2048 <GIC_SPI 776 IRQ_TYPE_EDGE_RISING>, 2049 <GIC_SPI 777 IRQ_TYPE_EDGE_RISING>, 2050 <GIC_SPI 778 IRQ_TYPE_EDGE_RISING>, 2051 <GIC_SPI 779 IRQ_TYPE_EDGE_RISING>, 2052 <GIC_SPI 780 IRQ_TYPE_EDGE_RISING>, 2053 <GIC_SPI 781 IRQ_TYPE_EDGE_RISING>, 2054 <GIC_SPI 782 IRQ_TYPE_EDGE_RISING>, 2055 <GIC_SPI 783 IRQ_TYPE_EDGE_RISING>, 2056 <GIC_SPI 784 IRQ_TYPE_EDGE_RISING>, 2057 <GIC_SPI 785 IRQ_TYPE_EDGE_RISING>, 2058 <GIC_SPI 786 IRQ_TYPE_EDGE_RISING>, 2059 <GIC_SPI 787 IRQ_TYPE_EDGE_RISING>, 2060 <GIC_SPI 788 IRQ_TYPE_EDGE_RISING>, 2061 <GIC_SPI 789 IRQ_TYPE_EDGE_RISING>, 2062 <GIC_SPI 790 IRQ_TYPE_EDGE_RISING>, 2063 <GIC_SPI 791 IRQ_TYPE_EDGE_RISING>, 2064 <GIC_SPI 792 IRQ_TYPE_EDGE_RISING>, 2065 <GIC_SPI 793 IRQ_TYPE_EDGE_RISING>, 2066 <GIC_SPI 794 IRQ_TYPE_EDGE_RISING>, 2067 <GIC_SPI 795 IRQ_TYPE_EDGE_RISING>, 2068 <GIC_SPI 796 IRQ_TYPE_EDGE_RISING>, 2069 <GIC_SPI 797 IRQ_TYPE_EDGE_RISING>, 2070 <GIC_SPI 798 IRQ_TYPE_EDGE_RISING>, 2071 <GIC_SPI 799 IRQ_TYPE_EDGE_RISING>; 2072 qcom,rproc = <&remoteproc_wpss>; 2073 memory-region = <&wlan_fw_mem>, <&wlan_ce_mem>; 2074 status = "disabled"; 2075 qcom,smem-states = <&wlan_smp2p_out 0>; 2076 qcom,smem-state-names = "wlan-smp2p-out"; 2077 }; 2078 2079 pcie1: pci@1c08000 { 2080 compatible = "qcom,pcie-sc7280"; 2081 reg = <0 0x01c08000 0 0x3000>, 2082 <0 0x40000000 0 0xf1d>, 2083 <0 0x40000f20 0 0xa8>, 2084 <0 0x40001000 0 0x1000>, 2085 <0 0x40100000 0 0x100000>; 2086 2087 reg-names = "parf", "dbi", "elbi", "atu", "config"; 2088 device_type = "pci"; 2089 linux,pci-domain = <1>; 2090 bus-range = <0x00 0xff>; 2091 num-lanes = <2>; 2092 2093 #address-cells = <3>; 2094 #size-cells = <2>; 2095 2096 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 2097 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 2098 2099 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 2100 interrupt-names = "msi"; 2101 #interrupt-cells = <1>; 2102 interrupt-map-mask = <0 0 0 0x7>; 2103 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, 2104 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, 2105 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, 2106 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; 2107 2108 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 2109 <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, 2110 <&pcie1_lane>, 2111 <&rpmhcc RPMH_CXO_CLK>, 2112 <&gcc GCC_PCIE_1_AUX_CLK>, 2113 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2114 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 2115 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 2116 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 2117 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 2118 <&gcc GCC_DDRSS_PCIE_SF_CLK>, 2119 <&gcc GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK>, 2120 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; 2121 2122 clock-names = "pipe", 2123 "pipe_mux", 2124 "phy_pipe", 2125 "ref", 2126 "aux", 2127 "cfg", 2128 "bus_master", 2129 "bus_slave", 2130 "slave_q2a", 2131 "tbu", 2132 "ddrss_sf_tbu", 2133 "aggre0", 2134 "aggre1"; 2135 2136 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 2137 assigned-clock-rates = <19200000>; 2138 2139 resets = <&gcc GCC_PCIE_1_BCR>; 2140 reset-names = "pci"; 2141 2142 power-domains = <&gcc GCC_PCIE_1_GDSC>; 2143 2144 phys = <&pcie1_lane>; 2145 phy-names = "pciephy"; 2146 2147 pinctrl-names = "default"; 2148 pinctrl-0 = <&pcie1_clkreq_n>; 2149 2150 dma-coherent; 2151 2152 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 2153 <0x100 &apps_smmu 0x1c81 0x1>; 2154 2155 status = "disabled"; 2156 }; 2157 2158 pcie1_phy: phy@1c0e000 { 2159 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy"; 2160 reg = <0 0x01c0e000 0 0x1c0>; 2161 #address-cells = <2>; 2162 #size-cells = <2>; 2163 ranges; 2164 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 2165 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2166 <&gcc GCC_PCIE_CLKREF_EN>, 2167 <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 2168 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 2169 2170 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 2171 reset-names = "phy"; 2172 2173 assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 2174 assigned-clock-rates = <100000000>; 2175 2176 status = "disabled"; 2177 2178 pcie1_lane: phy@1c0e200 { 2179 reg = <0 0x01c0e200 0 0x170>, 2180 <0 0x01c0e400 0 0x200>, 2181 <0 0x01c0ea00 0 0x1f0>, 2182 <0 0x01c0e600 0 0x170>, 2183 <0 0x01c0e800 0 0x200>, 2184 <0 0x01c0ee00 0 0xf4>; 2185 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 2186 clock-names = "pipe0"; 2187 2188 #phy-cells = <0>; 2189 #clock-cells = <0>; 2190 clock-output-names = "pcie_1_pipe_clk"; 2191 }; 2192 }; 2193 2194 ipa: ipa@1e40000 { 2195 compatible = "qcom,sc7280-ipa"; 2196 2197 iommus = <&apps_smmu 0x480 0x0>, 2198 <&apps_smmu 0x482 0x0>; 2199 reg = <0 0x01e40000 0 0x8000>, 2200 <0 0x01e50000 0 0x4ad0>, 2201 <0 0x01e04000 0 0x23000>; 2202 reg-names = "ipa-reg", 2203 "ipa-shared", 2204 "gsi"; 2205 2206 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>, 2207 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 2208 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2209 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 2210 interrupt-names = "ipa", 2211 "gsi", 2212 "ipa-clock-query", 2213 "ipa-setup-ready"; 2214 2215 clocks = <&rpmhcc RPMH_IPA_CLK>; 2216 clock-names = "core"; 2217 2218 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 2219 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_IPA_CFG 0>; 2220 interconnect-names = "memory", 2221 "config"; 2222 2223 qcom,qmp = <&aoss_qmp>; 2224 2225 qcom,smem-states = <&ipa_smp2p_out 0>, 2226 <&ipa_smp2p_out 1>; 2227 qcom,smem-state-names = "ipa-clock-enabled-valid", 2228 "ipa-clock-enabled"; 2229 2230 status = "disabled"; 2231 }; 2232 2233 tcsr_mutex: hwlock@1f40000 { 2234 compatible = "qcom,tcsr-mutex"; 2235 reg = <0 0x01f40000 0 0x20000>; 2236 #hwlock-cells = <1>; 2237 }; 2238 2239 tcsr_1: syscon@1f60000 { 2240 compatible = "qcom,sc7280-tcsr", "syscon"; 2241 reg = <0 0x01f60000 0 0x20000>; 2242 }; 2243 2244 tcsr_2: syscon@1fc0000 { 2245 compatible = "qcom,sc7280-tcsr", "syscon"; 2246 reg = <0 0x01fc0000 0 0x30000>; 2247 }; 2248 2249 lpasscc: lpasscc@3000000 { 2250 compatible = "qcom,sc7280-lpasscc"; 2251 reg = <0 0x03000000 0 0x40>, 2252 <0 0x03c04000 0 0x4>; 2253 reg-names = "qdsp6ss", "top_cc"; 2254 clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>; 2255 clock-names = "iface"; 2256 #clock-cells = <1>; 2257 }; 2258 2259 lpass_rx_macro: codec@3200000 { 2260 compatible = "qcom,sc7280-lpass-rx-macro"; 2261 reg = <0 0x03200000 0 0x1000>; 2262 2263 pinctrl-names = "default"; 2264 pinctrl-0 = <&lpass_rx_swr_clk>, <&lpass_rx_swr_data>; 2265 2266 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>, 2267 <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>, 2268 <&lpass_va_macro>; 2269 clock-names = "mclk", "npl", "fsgen"; 2270 2271 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, 2272 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2273 power-domain-names = "macro", "dcodec"; 2274 2275 #clock-cells = <0>; 2276 #sound-dai-cells = <1>; 2277 2278 status = "disabled"; 2279 }; 2280 2281 swr0: soundwire@3210000 { 2282 compatible = "qcom,soundwire-v1.6.0"; 2283 reg = <0 0x03210000 0 0x2000>; 2284 2285 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 2286 clocks = <&lpass_rx_macro>; 2287 clock-names = "iface"; 2288 2289 qcom,din-ports = <0>; 2290 qcom,dout-ports = <5>; 2291 2292 resets = <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>; 2293 reset-names = "swr_audio_cgcr"; 2294 2295 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>; 2296 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x3f 0x1f 0x03 0x03>; 2297 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x01>; 2298 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>; 2299 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; 2300 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>; 2301 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>; 2302 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>; 2303 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>; 2304 2305 #sound-dai-cells = <1>; 2306 #address-cells = <2>; 2307 #size-cells = <0>; 2308 2309 status = "disabled"; 2310 }; 2311 2312 lpass_tx_macro: codec@3220000 { 2313 compatible = "qcom,sc7280-lpass-tx-macro"; 2314 reg = <0 0x03220000 0 0x1000>; 2315 2316 pinctrl-names = "default"; 2317 pinctrl-0 = <&lpass_tx_swr_clk>, <&lpass_tx_swr_data>; 2318 2319 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>, 2320 <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>, 2321 <&lpass_va_macro>; 2322 clock-names = "mclk", "npl", "fsgen"; 2323 2324 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, 2325 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2326 power-domain-names = "macro", "dcodec"; 2327 2328 #clock-cells = <0>; 2329 #sound-dai-cells = <1>; 2330 2331 status = "disabled"; 2332 }; 2333 2334 swr1: soundwire@3230000 { 2335 compatible = "qcom,soundwire-v1.6.0"; 2336 reg = <0 0x03230000 0 0x2000>; 2337 2338 interrupts-extended = <&intc GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, 2339 <&pdc 130 IRQ_TYPE_LEVEL_HIGH>; 2340 clocks = <&lpass_tx_macro>; 2341 clock-names = "iface"; 2342 2343 qcom,din-ports = <3>; 2344 qcom,dout-ports = <0>; 2345 2346 resets = <&lpass_audiocc LPASS_AUDIO_SWR_TX_CGCR>; 2347 reset-names = "swr_audio_cgcr"; 2348 2349 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x03 0x03>; 2350 qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02>; 2351 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00>; 2352 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff>; 2353 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff>; 2354 qcom,ports-word-length = /bits/ 8 <0xff 0x00 0xff>; 2355 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff>; 2356 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff>; 2357 qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00>; 2358 2359 #sound-dai-cells = <1>; 2360 #address-cells = <2>; 2361 #size-cells = <0>; 2362 2363 status = "disabled"; 2364 }; 2365 2366 lpass_audiocc: clock-controller@3300000 { 2367 compatible = "qcom,sc7280-lpassaudiocc"; 2368 reg = <0 0x03300000 0 0x30000>, 2369 <0 0x032a9000 0 0x1000>; 2370 clocks = <&rpmhcc RPMH_CXO_CLK>, 2371 <&lpass_aon LPASS_AON_CC_MAIN_RCG_CLK_SRC>; 2372 clock-names = "bi_tcxo", "lpass_aon_cc_main_rcg_clk_src"; 2373 power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2374 #clock-cells = <1>; 2375 #power-domain-cells = <1>; 2376 #reset-cells = <1>; 2377 }; 2378 2379 lpass_va_macro: codec@3370000 { 2380 compatible = "qcom,sc7280-lpass-va-macro"; 2381 reg = <0 0x03370000 0 0x1000>; 2382 2383 pinctrl-names = "default"; 2384 pinctrl-0 = <&lpass_dmic01_clk>, <&lpass_dmic01_data>; 2385 2386 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>; 2387 clock-names = "mclk"; 2388 2389 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, 2390 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2391 power-domain-names = "macro", "dcodec"; 2392 2393 #clock-cells = <0>; 2394 #sound-dai-cells = <1>; 2395 2396 status = "disabled"; 2397 }; 2398 2399 lpass_aon: clock-controller@3380000 { 2400 compatible = "qcom,sc7280-lpassaoncc"; 2401 reg = <0 0x03380000 0 0x30000>; 2402 clocks = <&rpmhcc RPMH_CXO_CLK>, 2403 <&rpmhcc RPMH_CXO_CLK_A>, 2404 <&lpass_core LPASS_CORE_CC_CORE_CLK>; 2405 clock-names = "bi_tcxo", "bi_tcxo_ao", "iface"; 2406 #clock-cells = <1>; 2407 #power-domain-cells = <1>; 2408 }; 2409 2410 lpass_core: clock-controller@3900000 { 2411 compatible = "qcom,sc7280-lpasscorecc"; 2412 reg = <0 0x03900000 0 0x50000>; 2413 clocks = <&rpmhcc RPMH_CXO_CLK>; 2414 clock-names = "bi_tcxo"; 2415 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>; 2416 #clock-cells = <1>; 2417 #power-domain-cells = <1>; 2418 }; 2419 2420 lpass_cpu: audio@3987000 { 2421 compatible = "qcom,sc7280-lpass-cpu"; 2422 2423 reg = <0 0x03987000 0 0x68000>, 2424 <0 0x03b00000 0 0x29000>, 2425 <0 0x03260000 0 0xc000>, 2426 <0 0x03280000 0 0x29000>, 2427 <0 0x03340000 0 0x29000>, 2428 <0 0x0336c000 0 0x3000>; 2429 reg-names = "lpass-hdmiif", 2430 "lpass-lpaif", 2431 "lpass-rxtx-cdc-dma-lpm", 2432 "lpass-rxtx-lpaif", 2433 "lpass-va-lpaif", 2434 "lpass-va-cdc-dma-lpm"; 2435 2436 iommus = <&apps_smmu 0x1820 0>, 2437 <&apps_smmu 0x1821 0>, 2438 <&apps_smmu 0x1832 0>; 2439 2440 power-domains = <&rpmhpd SC7280_LCX>; 2441 power-domain-names = "lcx"; 2442 required-opps = <&rpmhpd_opp_nom>; 2443 2444 clocks = <&lpass_aon LPASS_AON_CC_AUDIO_HM_H_CLK>, 2445 <&lpass_core LPASS_CORE_CC_EXT_MCLK0_CLK>, 2446 <&lpass_core LPASS_CORE_CC_SYSNOC_MPORT_CORE_CLK>, 2447 <&lpass_core LPASS_CORE_CC_EXT_IF0_IBIT_CLK>, 2448 <&lpass_core LPASS_CORE_CC_EXT_IF1_IBIT_CLK>, 2449 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM_CLK>, 2450 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM0_CLK>, 2451 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM1_CLK>, 2452 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM2_CLK>, 2453 <&lpass_aon LPASS_AON_CC_VA_MEM0_CLK>; 2454 clock-names = "aon_cc_audio_hm_h", 2455 "audio_cc_ext_mclk0", 2456 "core_cc_sysnoc_mport_core", 2457 "core_cc_ext_if0_ibit", 2458 "core_cc_ext_if1_ibit", 2459 "audio_cc_codec_mem", 2460 "audio_cc_codec_mem0", 2461 "audio_cc_codec_mem1", 2462 "audio_cc_codec_mem2", 2463 "aon_cc_va_mem0"; 2464 2465 #sound-dai-cells = <1>; 2466 #address-cells = <1>; 2467 #size-cells = <0>; 2468 2469 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 2470 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 2471 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 2472 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 2473 interrupt-names = "lpass-irq-lpaif", 2474 "lpass-irq-hdmi", 2475 "lpass-irq-vaif", 2476 "lpass-irq-rxtxif"; 2477 2478 status = "disabled"; 2479 }; 2480 2481 lpass_hm: clock-controller@3c00000 { 2482 compatible = "qcom,sc7280-lpasshm"; 2483 reg = <0 0x03c00000 0 0x28>; 2484 clocks = <&rpmhcc RPMH_CXO_CLK>; 2485 clock-names = "bi_tcxo"; 2486 #clock-cells = <1>; 2487 #power-domain-cells = <1>; 2488 }; 2489 2490 lpass_ag_noc: interconnect@3c40000 { 2491 reg = <0 0x03c40000 0 0xf080>; 2492 compatible = "qcom,sc7280-lpass-ag-noc"; 2493 #interconnect-cells = <2>; 2494 qcom,bcm-voters = <&apps_bcm_voter>; 2495 }; 2496 2497 lpass_tlmm: pinctrl@33c0000 { 2498 compatible = "qcom,sc7280-lpass-lpi-pinctrl"; 2499 reg = <0 0x033c0000 0x0 0x20000>, 2500 <0 0x03550000 0x0 0x10000>; 2501 qcom,adsp-bypass-mode; 2502 gpio-controller; 2503 #gpio-cells = <2>; 2504 gpio-ranges = <&lpass_tlmm 0 0 15>; 2505 2506 lpass_dmic01_clk: dmic01-clk-state { 2507 pins = "gpio6"; 2508 function = "dmic1_clk"; 2509 }; 2510 2511 lpass_dmic01_data: dmic01-data-state { 2512 pins = "gpio7"; 2513 function = "dmic1_data"; 2514 }; 2515 2516 lpass_dmic23_clk: dmic23-clk-state { 2517 pins = "gpio8"; 2518 function = "dmic2_clk"; 2519 }; 2520 2521 lpass_dmic23_data: dmic23-data-state { 2522 pins = "gpio9"; 2523 function = "dmic2_data"; 2524 }; 2525 2526 lpass_rx_swr_clk: rx-swr-clk-state { 2527 pins = "gpio3"; 2528 function = "swr_rx_clk"; 2529 }; 2530 2531 lpass_rx_swr_data: rx-swr-data-state { 2532 pins = "gpio4", "gpio5"; 2533 function = "swr_rx_data"; 2534 }; 2535 2536 lpass_tx_swr_clk: tx-swr-clk-state { 2537 pins = "gpio0"; 2538 function = "swr_tx_clk"; 2539 }; 2540 2541 lpass_tx_swr_data: tx-swr-data-state { 2542 pins = "gpio1", "gpio2", "gpio14"; 2543 function = "swr_tx_data"; 2544 }; 2545 }; 2546 2547 gpu: gpu@3d00000 { 2548 compatible = "qcom,adreno-635.0", "qcom,adreno"; 2549 reg = <0 0x03d00000 0 0x40000>, 2550 <0 0x03d9e000 0 0x1000>, 2551 <0 0x03d61000 0 0x800>; 2552 reg-names = "kgsl_3d0_reg_memory", 2553 "cx_mem", 2554 "cx_dbgc"; 2555 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2556 iommus = <&adreno_smmu 0 0x401>; 2557 operating-points-v2 = <&gpu_opp_table>; 2558 qcom,gmu = <&gmu>; 2559 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 2560 interconnect-names = "gfx-mem"; 2561 #cooling-cells = <2>; 2562 2563 nvmem-cells = <&gpu_speed_bin>; 2564 nvmem-cell-names = "speed_bin"; 2565 2566 gpu_opp_table: opp-table { 2567 compatible = "operating-points-v2"; 2568 2569 opp-315000000 { 2570 opp-hz = /bits/ 64 <315000000>; 2571 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2572 opp-peak-kBps = <1804000>; 2573 opp-supported-hw = <0x03>; 2574 }; 2575 2576 opp-450000000 { 2577 opp-hz = /bits/ 64 <450000000>; 2578 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2579 opp-peak-kBps = <4068000>; 2580 opp-supported-hw = <0x03>; 2581 }; 2582 2583 /* Only applicable for SKUs which has 550Mhz as Fmax */ 2584 opp-550000000-0 { 2585 opp-hz = /bits/ 64 <550000000>; 2586 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2587 opp-peak-kBps = <8368000>; 2588 opp-supported-hw = <0x01>; 2589 }; 2590 2591 opp-550000000-1 { 2592 opp-hz = /bits/ 64 <550000000>; 2593 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2594 opp-peak-kBps = <6832000>; 2595 opp-supported-hw = <0x02>; 2596 }; 2597 2598 opp-608000000 { 2599 opp-hz = /bits/ 64 <608000000>; 2600 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 2601 opp-peak-kBps = <8368000>; 2602 opp-supported-hw = <0x02>; 2603 }; 2604 2605 opp-700000000 { 2606 opp-hz = /bits/ 64 <700000000>; 2607 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2608 opp-peak-kBps = <8532000>; 2609 opp-supported-hw = <0x02>; 2610 }; 2611 2612 opp-812000000 { 2613 opp-hz = /bits/ 64 <812000000>; 2614 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2615 opp-peak-kBps = <8532000>; 2616 opp-supported-hw = <0x02>; 2617 }; 2618 2619 opp-840000000 { 2620 opp-hz = /bits/ 64 <840000000>; 2621 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2622 opp-peak-kBps = <8532000>; 2623 opp-supported-hw = <0x02>; 2624 }; 2625 2626 opp-900000000 { 2627 opp-hz = /bits/ 64 <900000000>; 2628 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 2629 opp-peak-kBps = <8532000>; 2630 opp-supported-hw = <0x02>; 2631 }; 2632 }; 2633 }; 2634 2635 gmu: gmu@3d6a000 { 2636 compatible = "qcom,adreno-gmu-635.0", "qcom,adreno-gmu"; 2637 reg = <0 0x03d6a000 0 0x34000>, 2638 <0 0x3de0000 0 0x10000>, 2639 <0 0x0b290000 0 0x10000>; 2640 reg-names = "gmu", "rscc", "gmu_pdc"; 2641 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2642 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2643 interrupt-names = "hfi", "gmu"; 2644 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 2645 <&gpucc GPU_CC_CXO_CLK>, 2646 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2647 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2648 <&gpucc GPU_CC_AHB_CLK>, 2649 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2650 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; 2651 clock-names = "gmu", 2652 "cxo", 2653 "axi", 2654 "memnoc", 2655 "ahb", 2656 "hub", 2657 "smmu_vote"; 2658 power-domains = <&gpucc GPU_CC_CX_GDSC>, 2659 <&gpucc GPU_CC_GX_GDSC>; 2660 power-domain-names = "cx", 2661 "gx"; 2662 iommus = <&adreno_smmu 5 0x400>; 2663 operating-points-v2 = <&gmu_opp_table>; 2664 2665 gmu_opp_table: opp-table { 2666 compatible = "operating-points-v2"; 2667 2668 opp-200000000 { 2669 opp-hz = /bits/ 64 <200000000>; 2670 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2671 }; 2672 }; 2673 }; 2674 2675 gpucc: clock-controller@3d90000 { 2676 compatible = "qcom,sc7280-gpucc"; 2677 reg = <0 0x03d90000 0 0x9000>; 2678 clocks = <&rpmhcc RPMH_CXO_CLK>, 2679 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2680 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2681 clock-names = "bi_tcxo", 2682 "gcc_gpu_gpll0_clk_src", 2683 "gcc_gpu_gpll0_div_clk_src"; 2684 #clock-cells = <1>; 2685 #reset-cells = <1>; 2686 #power-domain-cells = <1>; 2687 }; 2688 2689 dma@117f000 { 2690 compatible = "qcom,sc7280-dcc", "qcom,dcc"; 2691 reg = <0x0 0x0117f000 0x0 0x1000>, 2692 <0x0 0x01112000 0x0 0x6000>; 2693 }; 2694 2695 adreno_smmu: iommu@3da0000 { 2696 compatible = "qcom,sc7280-smmu-500", "qcom,adreno-smmu", 2697 "qcom,smmu-500", "arm,mmu-500"; 2698 reg = <0 0x03da0000 0 0x20000>; 2699 #iommu-cells = <2>; 2700 #global-interrupts = <2>; 2701 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 2702 <GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>, 2703 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 2704 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 2705 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 2706 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2707 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2708 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2709 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2710 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 2711 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 2712 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 2713 2714 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2715 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 2716 <&gpucc GPU_CC_AHB_CLK>, 2717 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 2718 <&gpucc GPU_CC_CX_GMU_CLK>, 2719 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2720 <&gpucc GPU_CC_HUB_AON_CLK>; 2721 clock-names = "gcc_gpu_memnoc_gfx_clk", 2722 "gcc_gpu_snoc_dvm_gfx_clk", 2723 "gpu_cc_ahb_clk", 2724 "gpu_cc_hlos1_vote_gpu_smmu_clk", 2725 "gpu_cc_cx_gmu_clk", 2726 "gpu_cc_hub_cx_int_clk", 2727 "gpu_cc_hub_aon_clk"; 2728 2729 power-domains = <&gpucc GPU_CC_CX_GDSC>; 2730 }; 2731 2732 remoteproc_mpss: remoteproc@4080000 { 2733 compatible = "qcom,sc7280-mpss-pas"; 2734 reg = <0 0x04080000 0 0x10000>, <0 0x04180000 0 0x48>; 2735 reg-names = "qdsp6", "rmb"; 2736 2737 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 2738 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2739 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2740 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2741 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2742 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2743 interrupt-names = "wdog", "fatal", "ready", "handover", 2744 "stop-ack", "shutdown-ack"; 2745 2746 clocks = <&rpmhcc RPMH_CXO_CLK>; 2747 clock-names = "xo"; 2748 2749 power-domains = <&rpmhpd SC7280_CX>, 2750 <&rpmhpd SC7280_MSS>; 2751 power-domain-names = "cx", "mss"; 2752 2753 memory-region = <&mpss_mem>; 2754 2755 qcom,qmp = <&aoss_qmp>; 2756 2757 qcom,smem-states = <&modem_smp2p_out 0>; 2758 qcom,smem-state-names = "stop"; 2759 2760 status = "disabled"; 2761 2762 glink-edge { 2763 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 2764 IPCC_MPROC_SIGNAL_GLINK_QMP 2765 IRQ_TYPE_EDGE_RISING>; 2766 mboxes = <&ipcc IPCC_CLIENT_MPSS 2767 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2768 label = "modem"; 2769 qcom,remote-pid = <1>; 2770 }; 2771 }; 2772 2773 stm@6002000 { 2774 compatible = "arm,coresight-stm", "arm,primecell"; 2775 reg = <0 0x06002000 0 0x1000>, 2776 <0 0x16280000 0 0x180000>; 2777 reg-names = "stm-base", "stm-stimulus-base"; 2778 2779 clocks = <&aoss_qmp>; 2780 clock-names = "apb_pclk"; 2781 2782 out-ports { 2783 port { 2784 stm_out: endpoint { 2785 remote-endpoint = <&funnel0_in7>; 2786 }; 2787 }; 2788 }; 2789 }; 2790 2791 funnel@6041000 { 2792 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2793 reg = <0 0x06041000 0 0x1000>; 2794 2795 clocks = <&aoss_qmp>; 2796 clock-names = "apb_pclk"; 2797 2798 out-ports { 2799 port { 2800 funnel0_out: endpoint { 2801 remote-endpoint = <&merge_funnel_in0>; 2802 }; 2803 }; 2804 }; 2805 2806 in-ports { 2807 #address-cells = <1>; 2808 #size-cells = <0>; 2809 2810 port@7 { 2811 reg = <7>; 2812 funnel0_in7: endpoint { 2813 remote-endpoint = <&stm_out>; 2814 }; 2815 }; 2816 }; 2817 }; 2818 2819 funnel@6042000 { 2820 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2821 reg = <0 0x06042000 0 0x1000>; 2822 2823 clocks = <&aoss_qmp>; 2824 clock-names = "apb_pclk"; 2825 2826 out-ports { 2827 port { 2828 funnel1_out: endpoint { 2829 remote-endpoint = <&merge_funnel_in1>; 2830 }; 2831 }; 2832 }; 2833 2834 in-ports { 2835 #address-cells = <1>; 2836 #size-cells = <0>; 2837 2838 port@4 { 2839 reg = <4>; 2840 funnel1_in4: endpoint { 2841 remote-endpoint = <&apss_merge_funnel_out>; 2842 }; 2843 }; 2844 }; 2845 }; 2846 2847 funnel@6045000 { 2848 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2849 reg = <0 0x06045000 0 0x1000>; 2850 2851 clocks = <&aoss_qmp>; 2852 clock-names = "apb_pclk"; 2853 2854 out-ports { 2855 port { 2856 merge_funnel_out: endpoint { 2857 remote-endpoint = <&swao_funnel_in>; 2858 }; 2859 }; 2860 }; 2861 2862 in-ports { 2863 #address-cells = <1>; 2864 #size-cells = <0>; 2865 2866 port@0 { 2867 reg = <0>; 2868 merge_funnel_in0: endpoint { 2869 remote-endpoint = <&funnel0_out>; 2870 }; 2871 }; 2872 2873 port@1 { 2874 reg = <1>; 2875 merge_funnel_in1: endpoint { 2876 remote-endpoint = <&funnel1_out>; 2877 }; 2878 }; 2879 }; 2880 }; 2881 2882 replicator@6046000 { 2883 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2884 reg = <0 0x06046000 0 0x1000>; 2885 2886 clocks = <&aoss_qmp>; 2887 clock-names = "apb_pclk"; 2888 2889 out-ports { 2890 port { 2891 replicator_out: endpoint { 2892 remote-endpoint = <&etr_in>; 2893 }; 2894 }; 2895 }; 2896 2897 in-ports { 2898 port { 2899 replicator_in: endpoint { 2900 remote-endpoint = <&swao_replicator_out>; 2901 }; 2902 }; 2903 }; 2904 }; 2905 2906 etr@6048000 { 2907 compatible = "arm,coresight-tmc", "arm,primecell"; 2908 reg = <0 0x06048000 0 0x1000>; 2909 iommus = <&apps_smmu 0x04c0 0>; 2910 2911 clocks = <&aoss_qmp>; 2912 clock-names = "apb_pclk"; 2913 arm,scatter-gather; 2914 2915 in-ports { 2916 port { 2917 etr_in: endpoint { 2918 remote-endpoint = <&replicator_out>; 2919 }; 2920 }; 2921 }; 2922 }; 2923 2924 funnel@6b04000 { 2925 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2926 reg = <0 0x06b04000 0 0x1000>; 2927 2928 clocks = <&aoss_qmp>; 2929 clock-names = "apb_pclk"; 2930 2931 out-ports { 2932 port { 2933 swao_funnel_out: endpoint { 2934 remote-endpoint = <&etf_in>; 2935 }; 2936 }; 2937 }; 2938 2939 in-ports { 2940 #address-cells = <1>; 2941 #size-cells = <0>; 2942 2943 port@7 { 2944 reg = <7>; 2945 swao_funnel_in: endpoint { 2946 remote-endpoint = <&merge_funnel_out>; 2947 }; 2948 }; 2949 }; 2950 }; 2951 2952 etf@6b05000 { 2953 compatible = "arm,coresight-tmc", "arm,primecell"; 2954 reg = <0 0x06b05000 0 0x1000>; 2955 2956 clocks = <&aoss_qmp>; 2957 clock-names = "apb_pclk"; 2958 2959 out-ports { 2960 port { 2961 etf_out: endpoint { 2962 remote-endpoint = <&swao_replicator_in>; 2963 }; 2964 }; 2965 }; 2966 2967 in-ports { 2968 port { 2969 etf_in: endpoint { 2970 remote-endpoint = <&swao_funnel_out>; 2971 }; 2972 }; 2973 }; 2974 }; 2975 2976 replicator@6b06000 { 2977 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2978 reg = <0 0x06b06000 0 0x1000>; 2979 2980 clocks = <&aoss_qmp>; 2981 clock-names = "apb_pclk"; 2982 qcom,replicator-loses-context; 2983 2984 out-ports { 2985 port { 2986 swao_replicator_out: endpoint { 2987 remote-endpoint = <&replicator_in>; 2988 }; 2989 }; 2990 }; 2991 2992 in-ports { 2993 port { 2994 swao_replicator_in: endpoint { 2995 remote-endpoint = <&etf_out>; 2996 }; 2997 }; 2998 }; 2999 }; 3000 3001 etm@7040000 { 3002 compatible = "arm,coresight-etm4x", "arm,primecell"; 3003 reg = <0 0x07040000 0 0x1000>; 3004 3005 cpu = <&CPU0>; 3006 3007 clocks = <&aoss_qmp>; 3008 clock-names = "apb_pclk"; 3009 arm,coresight-loses-context-with-cpu; 3010 qcom,skip-power-up; 3011 3012 out-ports { 3013 port { 3014 etm0_out: endpoint { 3015 remote-endpoint = <&apss_funnel_in0>; 3016 }; 3017 }; 3018 }; 3019 }; 3020 3021 etm@7140000 { 3022 compatible = "arm,coresight-etm4x", "arm,primecell"; 3023 reg = <0 0x07140000 0 0x1000>; 3024 3025 cpu = <&CPU1>; 3026 3027 clocks = <&aoss_qmp>; 3028 clock-names = "apb_pclk"; 3029 arm,coresight-loses-context-with-cpu; 3030 qcom,skip-power-up; 3031 3032 out-ports { 3033 port { 3034 etm1_out: endpoint { 3035 remote-endpoint = <&apss_funnel_in1>; 3036 }; 3037 }; 3038 }; 3039 }; 3040 3041 etm@7240000 { 3042 compatible = "arm,coresight-etm4x", "arm,primecell"; 3043 reg = <0 0x07240000 0 0x1000>; 3044 3045 cpu = <&CPU2>; 3046 3047 clocks = <&aoss_qmp>; 3048 clock-names = "apb_pclk"; 3049 arm,coresight-loses-context-with-cpu; 3050 qcom,skip-power-up; 3051 3052 out-ports { 3053 port { 3054 etm2_out: endpoint { 3055 remote-endpoint = <&apss_funnel_in2>; 3056 }; 3057 }; 3058 }; 3059 }; 3060 3061 etm@7340000 { 3062 compatible = "arm,coresight-etm4x", "arm,primecell"; 3063 reg = <0 0x07340000 0 0x1000>; 3064 3065 cpu = <&CPU3>; 3066 3067 clocks = <&aoss_qmp>; 3068 clock-names = "apb_pclk"; 3069 arm,coresight-loses-context-with-cpu; 3070 qcom,skip-power-up; 3071 3072 out-ports { 3073 port { 3074 etm3_out: endpoint { 3075 remote-endpoint = <&apss_funnel_in3>; 3076 }; 3077 }; 3078 }; 3079 }; 3080 3081 etm@7440000 { 3082 compatible = "arm,coresight-etm4x", "arm,primecell"; 3083 reg = <0 0x07440000 0 0x1000>; 3084 3085 cpu = <&CPU4>; 3086 3087 clocks = <&aoss_qmp>; 3088 clock-names = "apb_pclk"; 3089 arm,coresight-loses-context-with-cpu; 3090 qcom,skip-power-up; 3091 3092 out-ports { 3093 port { 3094 etm4_out: endpoint { 3095 remote-endpoint = <&apss_funnel_in4>; 3096 }; 3097 }; 3098 }; 3099 }; 3100 3101 etm@7540000 { 3102 compatible = "arm,coresight-etm4x", "arm,primecell"; 3103 reg = <0 0x07540000 0 0x1000>; 3104 3105 cpu = <&CPU5>; 3106 3107 clocks = <&aoss_qmp>; 3108 clock-names = "apb_pclk"; 3109 arm,coresight-loses-context-with-cpu; 3110 qcom,skip-power-up; 3111 3112 out-ports { 3113 port { 3114 etm5_out: endpoint { 3115 remote-endpoint = <&apss_funnel_in5>; 3116 }; 3117 }; 3118 }; 3119 }; 3120 3121 etm@7640000 { 3122 compatible = "arm,coresight-etm4x", "arm,primecell"; 3123 reg = <0 0x07640000 0 0x1000>; 3124 3125 cpu = <&CPU6>; 3126 3127 clocks = <&aoss_qmp>; 3128 clock-names = "apb_pclk"; 3129 arm,coresight-loses-context-with-cpu; 3130 qcom,skip-power-up; 3131 3132 out-ports { 3133 port { 3134 etm6_out: endpoint { 3135 remote-endpoint = <&apss_funnel_in6>; 3136 }; 3137 }; 3138 }; 3139 }; 3140 3141 etm@7740000 { 3142 compatible = "arm,coresight-etm4x", "arm,primecell"; 3143 reg = <0 0x07740000 0 0x1000>; 3144 3145 cpu = <&CPU7>; 3146 3147 clocks = <&aoss_qmp>; 3148 clock-names = "apb_pclk"; 3149 arm,coresight-loses-context-with-cpu; 3150 qcom,skip-power-up; 3151 3152 out-ports { 3153 port { 3154 etm7_out: endpoint { 3155 remote-endpoint = <&apss_funnel_in7>; 3156 }; 3157 }; 3158 }; 3159 }; 3160 3161 funnel@7800000 { /* APSS Funnel */ 3162 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3163 reg = <0 0x07800000 0 0x1000>; 3164 3165 clocks = <&aoss_qmp>; 3166 clock-names = "apb_pclk"; 3167 3168 out-ports { 3169 port { 3170 apss_funnel_out: endpoint { 3171 remote-endpoint = <&apss_merge_funnel_in>; 3172 }; 3173 }; 3174 }; 3175 3176 in-ports { 3177 #address-cells = <1>; 3178 #size-cells = <0>; 3179 3180 port@0 { 3181 reg = <0>; 3182 apss_funnel_in0: endpoint { 3183 remote-endpoint = <&etm0_out>; 3184 }; 3185 }; 3186 3187 port@1 { 3188 reg = <1>; 3189 apss_funnel_in1: endpoint { 3190 remote-endpoint = <&etm1_out>; 3191 }; 3192 }; 3193 3194 port@2 { 3195 reg = <2>; 3196 apss_funnel_in2: endpoint { 3197 remote-endpoint = <&etm2_out>; 3198 }; 3199 }; 3200 3201 port@3 { 3202 reg = <3>; 3203 apss_funnel_in3: endpoint { 3204 remote-endpoint = <&etm3_out>; 3205 }; 3206 }; 3207 3208 port@4 { 3209 reg = <4>; 3210 apss_funnel_in4: endpoint { 3211 remote-endpoint = <&etm4_out>; 3212 }; 3213 }; 3214 3215 port@5 { 3216 reg = <5>; 3217 apss_funnel_in5: endpoint { 3218 remote-endpoint = <&etm5_out>; 3219 }; 3220 }; 3221 3222 port@6 { 3223 reg = <6>; 3224 apss_funnel_in6: endpoint { 3225 remote-endpoint = <&etm6_out>; 3226 }; 3227 }; 3228 3229 port@7 { 3230 reg = <7>; 3231 apss_funnel_in7: endpoint { 3232 remote-endpoint = <&etm7_out>; 3233 }; 3234 }; 3235 }; 3236 }; 3237 3238 funnel@7810000 { 3239 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3240 reg = <0 0x07810000 0 0x1000>; 3241 3242 clocks = <&aoss_qmp>; 3243 clock-names = "apb_pclk"; 3244 3245 out-ports { 3246 port { 3247 apss_merge_funnel_out: endpoint { 3248 remote-endpoint = <&funnel1_in4>; 3249 }; 3250 }; 3251 }; 3252 3253 in-ports { 3254 port { 3255 apss_merge_funnel_in: endpoint { 3256 remote-endpoint = <&apss_funnel_out>; 3257 }; 3258 }; 3259 }; 3260 }; 3261 3262 sdhc_2: mmc@8804000 { 3263 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 3264 pinctrl-names = "default", "sleep"; 3265 pinctrl-0 = <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>; 3266 pinctrl-1 = <&sdc2_clk_sleep>, <&sdc2_cmd_sleep>, <&sdc2_data_sleep>; 3267 status = "disabled"; 3268 3269 reg = <0 0x08804000 0 0x1000>; 3270 3271 iommus = <&apps_smmu 0x100 0x0>; 3272 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 3273 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 3274 interrupt-names = "hc_irq", "pwr_irq"; 3275 3276 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3277 <&gcc GCC_SDCC2_APPS_CLK>, 3278 <&rpmhcc RPMH_CXO_CLK>; 3279 clock-names = "iface", "core", "xo"; 3280 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 3281 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>; 3282 interconnect-names = "sdhc-ddr","cpu-sdhc"; 3283 power-domains = <&rpmhpd SC7280_CX>; 3284 operating-points-v2 = <&sdhc2_opp_table>; 3285 3286 bus-width = <4>; 3287 3288 qcom,dll-config = <0x0007642c>; 3289 3290 resets = <&gcc GCC_SDCC2_BCR>; 3291 3292 sdhc2_opp_table: opp-table { 3293 compatible = "operating-points-v2"; 3294 3295 opp-100000000 { 3296 opp-hz = /bits/ 64 <100000000>; 3297 required-opps = <&rpmhpd_opp_low_svs>; 3298 opp-peak-kBps = <1800000 400000>; 3299 opp-avg-kBps = <100000 0>; 3300 }; 3301 3302 opp-202000000 { 3303 opp-hz = /bits/ 64 <202000000>; 3304 required-opps = <&rpmhpd_opp_nom>; 3305 opp-peak-kBps = <5400000 1600000>; 3306 opp-avg-kBps = <200000 0>; 3307 }; 3308 }; 3309 }; 3310 3311 usb_1_hsphy: phy@88e3000 { 3312 compatible = "qcom,sc7280-usb-hs-phy", 3313 "qcom,usb-snps-hs-7nm-phy"; 3314 reg = <0 0x088e3000 0 0x400>; 3315 status = "disabled"; 3316 #phy-cells = <0>; 3317 3318 clocks = <&rpmhcc RPMH_CXO_CLK>; 3319 clock-names = "ref"; 3320 3321 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3322 }; 3323 3324 usb_2_hsphy: phy@88e4000 { 3325 compatible = "qcom,sc7280-usb-hs-phy", 3326 "qcom,usb-snps-hs-7nm-phy"; 3327 reg = <0 0x088e4000 0 0x400>; 3328 status = "disabled"; 3329 #phy-cells = <0>; 3330 3331 clocks = <&rpmhcc RPMH_CXO_CLK>; 3332 clock-names = "ref"; 3333 3334 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3335 }; 3336 3337 usb_1_qmpphy: phy-wrapper@88e9000 { 3338 compatible = "qcom,sc7280-qmp-usb3-dp-phy", 3339 "qcom,sm8250-qmp-usb3-dp-phy"; 3340 reg = <0 0x088e9000 0 0x200>, 3341 <0 0x088e8000 0 0x40>, 3342 <0 0x088ea000 0 0x200>; 3343 status = "disabled"; 3344 #address-cells = <2>; 3345 #size-cells = <2>; 3346 ranges; 3347 3348 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3349 <&rpmhcc RPMH_CXO_CLK>, 3350 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 3351 clock-names = "aux", "ref_clk_src", "com_aux"; 3352 3353 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 3354 <&gcc GCC_USB3_PHY_PRIM_BCR>; 3355 reset-names = "phy", "common"; 3356 3357 usb_1_ssphy: usb3-phy@88e9200 { 3358 reg = <0 0x088e9200 0 0x200>, 3359 <0 0x088e9400 0 0x200>, 3360 <0 0x088e9c00 0 0x400>, 3361 <0 0x088e9600 0 0x200>, 3362 <0 0x088e9800 0 0x200>, 3363 <0 0x088e9a00 0 0x100>; 3364 #clock-cells = <0>; 3365 #phy-cells = <0>; 3366 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3367 clock-names = "pipe0"; 3368 clock-output-names = "usb3_phy_pipe_clk_src"; 3369 }; 3370 3371 dp_phy: dp-phy@88ea200 { 3372 reg = <0 0x088ea200 0 0x200>, 3373 <0 0x088ea400 0 0x200>, 3374 <0 0x088eaa00 0 0x200>, 3375 <0 0x088ea600 0 0x200>, 3376 <0 0x088ea800 0 0x200>; 3377 #phy-cells = <0>; 3378 #clock-cells = <1>; 3379 }; 3380 }; 3381 3382 usb_2: usb@8cf8800 { 3383 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 3384 reg = <0 0x08cf8800 0 0x400>; 3385 status = "disabled"; 3386 #address-cells = <2>; 3387 #size-cells = <2>; 3388 ranges; 3389 dma-ranges; 3390 3391 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 3392 <&gcc GCC_USB30_SEC_MASTER_CLK>, 3393 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 3394 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 3395 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>; 3396 clock-names = "cfg_noc", 3397 "core", 3398 "iface", 3399 "sleep", 3400 "mock_utmi"; 3401 3402 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3403 <&gcc GCC_USB30_SEC_MASTER_CLK>; 3404 assigned-clock-rates = <19200000>, <200000000>; 3405 3406 interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 3407 <&pdc 12 IRQ_TYPE_EDGE_RISING>, 3408 <&pdc 13 IRQ_TYPE_EDGE_RISING>; 3409 interrupt-names = "hs_phy_irq", 3410 "dp_hs_phy_irq", 3411 "dm_hs_phy_irq"; 3412 3413 power-domains = <&gcc GCC_USB30_SEC_GDSC>; 3414 required-opps = <&rpmhpd_opp_nom>; 3415 3416 resets = <&gcc GCC_USB30_SEC_BCR>; 3417 3418 interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>, 3419 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB2 0>; 3420 interconnect-names = "usb-ddr", "apps-usb"; 3421 3422 usb_2_dwc3: usb@8c00000 { 3423 compatible = "snps,dwc3"; 3424 reg = <0 0x08c00000 0 0xe000>; 3425 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 3426 iommus = <&apps_smmu 0xa0 0x0>; 3427 snps,dis_u2_susphy_quirk; 3428 snps,dis_enblslpm_quirk; 3429 phys = <&usb_2_hsphy>; 3430 phy-names = "usb2-phy"; 3431 maximum-speed = "high-speed"; 3432 usb-role-switch; 3433 port { 3434 usb2_role_switch: endpoint { 3435 remote-endpoint = <&eud_ep>; 3436 }; 3437 }; 3438 }; 3439 }; 3440 3441 qspi: spi@88dc000 { 3442 compatible = "qcom,sc7280-qspi", "qcom,qspi-v1"; 3443 reg = <0 0x088dc000 0 0x1000>; 3444 #address-cells = <1>; 3445 #size-cells = <0>; 3446 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 3447 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 3448 <&gcc GCC_QSPI_CORE_CLK>; 3449 clock-names = "iface", "core"; 3450 interconnects = <&gem_noc MASTER_APPSS_PROC 0 3451 &cnoc2 SLAVE_QSPI_0 0>; 3452 interconnect-names = "qspi-config"; 3453 power-domains = <&rpmhpd SC7280_CX>; 3454 operating-points-v2 = <&qspi_opp_table>; 3455 status = "disabled"; 3456 }; 3457 3458 remoteproc_wpss: remoteproc@8a00000 { 3459 compatible = "qcom,sc7280-wpss-pil"; 3460 reg = <0 0x08a00000 0 0x10000>; 3461 3462 interrupts-extended = <&intc GIC_SPI 587 IRQ_TYPE_EDGE_RISING>, 3463 <&wpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3464 <&wpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3465 <&wpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3466 <&wpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 3467 <&wpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 3468 interrupt-names = "wdog", "fatal", "ready", "handover", 3469 "stop-ack", "shutdown-ack"; 3470 3471 clocks = <&gcc GCC_WPSS_AHB_BDG_MST_CLK>, 3472 <&gcc GCC_WPSS_AHB_CLK>, 3473 <&gcc GCC_WPSS_RSCP_CLK>, 3474 <&rpmhcc RPMH_CXO_CLK>; 3475 clock-names = "ahb_bdg", "ahb", 3476 "rscp", "xo"; 3477 3478 power-domains = <&rpmhpd SC7280_CX>, 3479 <&rpmhpd SC7280_MX>; 3480 power-domain-names = "cx", "mx"; 3481 3482 memory-region = <&wpss_mem>; 3483 3484 qcom,qmp = <&aoss_qmp>; 3485 3486 qcom,smem-states = <&wpss_smp2p_out 0>; 3487 qcom,smem-state-names = "stop"; 3488 3489 resets = <&aoss_reset AOSS_CC_WCSS_RESTART>, 3490 <&pdc_reset PDC_WPSS_SYNC_RESET>; 3491 reset-names = "restart", "pdc_sync"; 3492 3493 qcom,halt-regs = <&tcsr_1 0x17000>; 3494 3495 status = "disabled"; 3496 3497 glink-edge { 3498 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 3499 IPCC_MPROC_SIGNAL_GLINK_QMP 3500 IRQ_TYPE_EDGE_RISING>; 3501 mboxes = <&ipcc IPCC_CLIENT_WPSS 3502 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3503 3504 label = "wpss"; 3505 qcom,remote-pid = <13>; 3506 }; 3507 }; 3508 3509 pmu@9091000 { 3510 compatible = "qcom,sc7280-llcc-bwmon"; 3511 reg = <0 0x09091000 0 0x1000>; 3512 3513 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 3514 3515 interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>; 3516 3517 operating-points-v2 = <&llcc_bwmon_opp_table>; 3518 3519 llcc_bwmon_opp_table: opp-table { 3520 compatible = "operating-points-v2"; 3521 3522 opp-0 { 3523 opp-peak-kBps = <800000>; 3524 }; 3525 opp-1 { 3526 opp-peak-kBps = <1804000>; 3527 }; 3528 opp-2 { 3529 opp-peak-kBps = <2188000>; 3530 }; 3531 opp-3 { 3532 opp-peak-kBps = <3072000>; 3533 }; 3534 opp-4 { 3535 opp-peak-kBps = <4068000>; 3536 }; 3537 opp-5 { 3538 opp-peak-kBps = <6220000>; 3539 }; 3540 opp-6 { 3541 opp-peak-kBps = <6832000>; 3542 }; 3543 opp-7 { 3544 opp-peak-kBps = <8532000>; 3545 }; 3546 }; 3547 }; 3548 3549 pmu@90b6400 { 3550 compatible = "qcom,sc7280-cpu-bwmon", "qcom,sdm845-bwmon"; 3551 reg = <0 0x090b6400 0 0x600>; 3552 3553 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 3554 3555 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>; 3556 operating-points-v2 = <&cpu_bwmon_opp_table>; 3557 3558 cpu_bwmon_opp_table: opp-table { 3559 compatible = "operating-points-v2"; 3560 3561 opp-0 { 3562 opp-peak-kBps = <2400000>; 3563 }; 3564 opp-1 { 3565 opp-peak-kBps = <4800000>; 3566 }; 3567 opp-2 { 3568 opp-peak-kBps = <7456000>; 3569 }; 3570 opp-3 { 3571 opp-peak-kBps = <9600000>; 3572 }; 3573 opp-4 { 3574 opp-peak-kBps = <12896000>; 3575 }; 3576 opp-5 { 3577 opp-peak-kBps = <14928000>; 3578 }; 3579 opp-6 { 3580 opp-peak-kBps = <17056000>; 3581 }; 3582 }; 3583 }; 3584 3585 dc_noc: interconnect@90e0000 { 3586 reg = <0 0x090e0000 0 0x5080>; 3587 compatible = "qcom,sc7280-dc-noc"; 3588 #interconnect-cells = <2>; 3589 qcom,bcm-voters = <&apps_bcm_voter>; 3590 }; 3591 3592 gem_noc: interconnect@9100000 { 3593 reg = <0 0x09100000 0 0xe2200>; 3594 compatible = "qcom,sc7280-gem-noc"; 3595 #interconnect-cells = <2>; 3596 qcom,bcm-voters = <&apps_bcm_voter>; 3597 }; 3598 3599 system-cache-controller@9200000 { 3600 compatible = "qcom,sc7280-llcc"; 3601 reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, 3602 <0 0x09600000 0 0x58000>; 3603 reg-names = "llcc0_base", "llcc1_base", "llcc_broadcast_base"; 3604 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 3605 }; 3606 3607 eud: eud@88e0000 { 3608 compatible = "qcom,sc7280-eud","qcom,eud"; 3609 reg = <0 0x088e0000 0 0x2000>, 3610 <0 0x088e2000 0 0x1000>; 3611 interrupts-extended = <&pdc 11 IRQ_TYPE_LEVEL_HIGH>; 3612 ports { 3613 #address-cells = <1>; 3614 #size-cells = <0>; 3615 3616 port@0 { 3617 reg = <0>; 3618 eud_ep: endpoint { 3619 remote-endpoint = <&usb2_role_switch>; 3620 }; 3621 }; 3622 port@1 { 3623 reg = <1>; 3624 eud_con: endpoint { 3625 remote-endpoint = <&con_eud>; 3626 }; 3627 }; 3628 }; 3629 }; 3630 3631 eud_typec: connector { 3632 compatible = "usb-c-connector"; 3633 ports { 3634 #address-cells = <1>; 3635 #size-cells = <0>; 3636 3637 port@0 { 3638 reg = <0>; 3639 con_eud: endpoint { 3640 remote-endpoint = <&eud_con>; 3641 }; 3642 }; 3643 }; 3644 }; 3645 3646 nsp_noc: interconnect@a0c0000 { 3647 reg = <0 0x0a0c0000 0 0x10000>; 3648 compatible = "qcom,sc7280-nsp-noc"; 3649 #interconnect-cells = <2>; 3650 qcom,bcm-voters = <&apps_bcm_voter>; 3651 }; 3652 3653 usb_1: usb@a6f8800 { 3654 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 3655 reg = <0 0x0a6f8800 0 0x400>; 3656 status = "disabled"; 3657 #address-cells = <2>; 3658 #size-cells = <2>; 3659 ranges; 3660 dma-ranges; 3661 3662 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3663 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3664 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3665 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 3666 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 3667 clock-names = "cfg_noc", 3668 "core", 3669 "iface", 3670 "sleep", 3671 "mock_utmi"; 3672 3673 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3674 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3675 assigned-clock-rates = <19200000>, <200000000>; 3676 3677 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 3678 <&pdc 14 IRQ_TYPE_LEVEL_HIGH>, 3679 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 3680 <&pdc 17 IRQ_TYPE_EDGE_BOTH>; 3681 interrupt-names = "hs_phy_irq", 3682 "dp_hs_phy_irq", 3683 "dm_hs_phy_irq", 3684 "ss_phy_irq"; 3685 3686 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 3687 required-opps = <&rpmhpd_opp_nom>; 3688 3689 resets = <&gcc GCC_USB30_PRIM_BCR>; 3690 3691 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 3692 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB3_0 0>; 3693 interconnect-names = "usb-ddr", "apps-usb"; 3694 3695 wakeup-source; 3696 3697 usb_1_dwc3: usb@a600000 { 3698 compatible = "snps,dwc3"; 3699 reg = <0 0x0a600000 0 0xe000>; 3700 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 3701 iommus = <&apps_smmu 0xe0 0x0>; 3702 snps,dis_u2_susphy_quirk; 3703 snps,dis_enblslpm_quirk; 3704 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 3705 phy-names = "usb2-phy", "usb3-phy"; 3706 maximum-speed = "super-speed"; 3707 }; 3708 }; 3709 3710 venus: video-codec@aa00000 { 3711 compatible = "qcom,sc7280-venus"; 3712 reg = <0 0x0aa00000 0 0xd0600>; 3713 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 3714 3715 clocks = <&videocc VIDEO_CC_MVSC_CORE_CLK>, 3716 <&videocc VIDEO_CC_MVSC_CTL_AXI_CLK>, 3717 <&videocc VIDEO_CC_VENUS_AHB_CLK>, 3718 <&videocc VIDEO_CC_MVS0_CORE_CLK>, 3719 <&videocc VIDEO_CC_MVS0_AXI_CLK>; 3720 clock-names = "core", "bus", "iface", 3721 "vcodec_core", "vcodec_bus"; 3722 3723 power-domains = <&videocc MVSC_GDSC>, 3724 <&videocc MVS0_GDSC>, 3725 <&rpmhpd SC7280_CX>; 3726 power-domain-names = "venus", "vcodec0", "cx"; 3727 operating-points-v2 = <&venus_opp_table>; 3728 3729 interconnects = <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_VENUS_CFG 0>, 3730 <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>; 3731 interconnect-names = "cpu-cfg", "video-mem"; 3732 3733 iommus = <&apps_smmu 0x2180 0x20>, 3734 <&apps_smmu 0x2184 0x20>; 3735 memory-region = <&video_mem>; 3736 3737 video-decoder { 3738 compatible = "venus-decoder"; 3739 }; 3740 3741 video-encoder { 3742 compatible = "venus-encoder"; 3743 }; 3744 3745 video-firmware { 3746 iommus = <&apps_smmu 0x21a2 0x0>; 3747 }; 3748 3749 venus_opp_table: opp-table { 3750 compatible = "operating-points-v2"; 3751 3752 opp-133330000 { 3753 opp-hz = /bits/ 64 <133330000>; 3754 required-opps = <&rpmhpd_opp_low_svs>; 3755 }; 3756 3757 opp-240000000 { 3758 opp-hz = /bits/ 64 <240000000>; 3759 required-opps = <&rpmhpd_opp_svs>; 3760 }; 3761 3762 opp-335000000 { 3763 opp-hz = /bits/ 64 <335000000>; 3764 required-opps = <&rpmhpd_opp_svs_l1>; 3765 }; 3766 3767 opp-424000000 { 3768 opp-hz = /bits/ 64 <424000000>; 3769 required-opps = <&rpmhpd_opp_nom>; 3770 }; 3771 3772 opp-460000048 { 3773 opp-hz = /bits/ 64 <460000048>; 3774 required-opps = <&rpmhpd_opp_turbo>; 3775 }; 3776 }; 3777 }; 3778 3779 videocc: clock-controller@aaf0000 { 3780 compatible = "qcom,sc7280-videocc"; 3781 reg = <0 0x0aaf0000 0 0x10000>; 3782 clocks = <&rpmhcc RPMH_CXO_CLK>, 3783 <&rpmhcc RPMH_CXO_CLK_A>; 3784 clock-names = "bi_tcxo", "bi_tcxo_ao"; 3785 #clock-cells = <1>; 3786 #reset-cells = <1>; 3787 #power-domain-cells = <1>; 3788 }; 3789 3790 camcc: clock-controller@ad00000 { 3791 compatible = "qcom,sc7280-camcc"; 3792 reg = <0 0x0ad00000 0 0x10000>; 3793 clocks = <&rpmhcc RPMH_CXO_CLK>, 3794 <&rpmhcc RPMH_CXO_CLK_A>, 3795 <&sleep_clk>; 3796 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; 3797 #clock-cells = <1>; 3798 #reset-cells = <1>; 3799 #power-domain-cells = <1>; 3800 }; 3801 3802 dispcc: clock-controller@af00000 { 3803 compatible = "qcom,sc7280-dispcc"; 3804 reg = <0 0x0af00000 0 0x20000>; 3805 clocks = <&rpmhcc RPMH_CXO_CLK>, 3806 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 3807 <&mdss_dsi_phy 0>, 3808 <&mdss_dsi_phy 1>, 3809 <&dp_phy 0>, 3810 <&dp_phy 1>, 3811 <&mdss_edp_phy 0>, 3812 <&mdss_edp_phy 1>; 3813 clock-names = "bi_tcxo", 3814 "gcc_disp_gpll0_clk", 3815 "dsi0_phy_pll_out_byteclk", 3816 "dsi0_phy_pll_out_dsiclk", 3817 "dp_phy_pll_link_clk", 3818 "dp_phy_pll_vco_div_clk", 3819 "edp_phy_pll_link_clk", 3820 "edp_phy_pll_vco_div_clk"; 3821 #clock-cells = <1>; 3822 #reset-cells = <1>; 3823 #power-domain-cells = <1>; 3824 }; 3825 3826 mdss: display-subsystem@ae00000 { 3827 compatible = "qcom,sc7280-mdss"; 3828 reg = <0 0x0ae00000 0 0x1000>; 3829 reg-names = "mdss"; 3830 3831 power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; 3832 3833 clocks = <&gcc GCC_DISP_AHB_CLK>, 3834 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3835 <&dispcc DISP_CC_MDSS_MDP_CLK>; 3836 clock-names = "iface", 3837 "ahb", 3838 "core"; 3839 3840 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 3841 interrupt-controller; 3842 #interrupt-cells = <1>; 3843 3844 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>; 3845 interconnect-names = "mdp0-mem"; 3846 3847 iommus = <&apps_smmu 0x900 0x402>; 3848 3849 #address-cells = <2>; 3850 #size-cells = <2>; 3851 ranges; 3852 3853 status = "disabled"; 3854 3855 mdss_mdp: display-controller@ae01000 { 3856 compatible = "qcom,sc7280-dpu"; 3857 reg = <0 0x0ae01000 0 0x8f030>, 3858 <0 0x0aeb0000 0 0x2008>; 3859 reg-names = "mdp", "vbif"; 3860 3861 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 3862 <&gcc GCC_DISP_SF_AXI_CLK>, 3863 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3864 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 3865 <&dispcc DISP_CC_MDSS_MDP_CLK>, 3866 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3867 clock-names = "bus", 3868 "nrt_bus", 3869 "iface", 3870 "lut", 3871 "core", 3872 "vsync"; 3873 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>, 3874 <&dispcc DISP_CC_MDSS_AHB_CLK>; 3875 assigned-clock-rates = <19200000>, 3876 <19200000>; 3877 operating-points-v2 = <&mdp_opp_table>; 3878 power-domains = <&rpmhpd SC7280_CX>; 3879 3880 interrupt-parent = <&mdss>; 3881 interrupts = <0>; 3882 3883 status = "disabled"; 3884 3885 ports { 3886 #address-cells = <1>; 3887 #size-cells = <0>; 3888 3889 port@0 { 3890 reg = <0>; 3891 dpu_intf1_out: endpoint { 3892 remote-endpoint = <&dsi0_in>; 3893 }; 3894 }; 3895 3896 port@1 { 3897 reg = <1>; 3898 dpu_intf5_out: endpoint { 3899 remote-endpoint = <&edp_in>; 3900 }; 3901 }; 3902 3903 port@2 { 3904 reg = <2>; 3905 dpu_intf0_out: endpoint { 3906 remote-endpoint = <&dp_in>; 3907 }; 3908 }; 3909 }; 3910 3911 mdp_opp_table: opp-table { 3912 compatible = "operating-points-v2"; 3913 3914 opp-200000000 { 3915 opp-hz = /bits/ 64 <200000000>; 3916 required-opps = <&rpmhpd_opp_low_svs>; 3917 }; 3918 3919 opp-300000000 { 3920 opp-hz = /bits/ 64 <300000000>; 3921 required-opps = <&rpmhpd_opp_svs>; 3922 }; 3923 3924 opp-380000000 { 3925 opp-hz = /bits/ 64 <380000000>; 3926 required-opps = <&rpmhpd_opp_svs_l1>; 3927 }; 3928 3929 opp-506666667 { 3930 opp-hz = /bits/ 64 <506666667>; 3931 required-opps = <&rpmhpd_opp_nom>; 3932 }; 3933 }; 3934 }; 3935 3936 mdss_dsi: dsi@ae94000 { 3937 compatible = "qcom,sc7280-dsi-ctrl", 3938 "qcom,mdss-dsi-ctrl"; 3939 reg = <0 0x0ae94000 0 0x400>; 3940 reg-names = "dsi_ctrl"; 3941 3942 interrupt-parent = <&mdss>; 3943 interrupts = <4>; 3944 3945 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 3946 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 3947 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 3948 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 3949 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3950 <&gcc GCC_DISP_HF_AXI_CLK>; 3951 clock-names = "byte", 3952 "byte_intf", 3953 "pixel", 3954 "core", 3955 "iface", 3956 "bus"; 3957 3958 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 3959 assigned-clock-parents = <&mdss_dsi_phy 0>, <&mdss_dsi_phy 1>; 3960 3961 operating-points-v2 = <&dsi_opp_table>; 3962 power-domains = <&rpmhpd SC7280_CX>; 3963 3964 phys = <&mdss_dsi_phy>; 3965 3966 #address-cells = <1>; 3967 #size-cells = <0>; 3968 3969 status = "disabled"; 3970 3971 ports { 3972 #address-cells = <1>; 3973 #size-cells = <0>; 3974 3975 port@0 { 3976 reg = <0>; 3977 dsi0_in: endpoint { 3978 remote-endpoint = <&dpu_intf1_out>; 3979 }; 3980 }; 3981 3982 port@1 { 3983 reg = <1>; 3984 dsi0_out: endpoint { 3985 }; 3986 }; 3987 }; 3988 3989 dsi_opp_table: opp-table { 3990 compatible = "operating-points-v2"; 3991 3992 opp-187500000 { 3993 opp-hz = /bits/ 64 <187500000>; 3994 required-opps = <&rpmhpd_opp_low_svs>; 3995 }; 3996 3997 opp-300000000 { 3998 opp-hz = /bits/ 64 <300000000>; 3999 required-opps = <&rpmhpd_opp_svs>; 4000 }; 4001 4002 opp-358000000 { 4003 opp-hz = /bits/ 64 <358000000>; 4004 required-opps = <&rpmhpd_opp_svs_l1>; 4005 }; 4006 }; 4007 }; 4008 4009 mdss_dsi_phy: phy@ae94400 { 4010 compatible = "qcom,sc7280-dsi-phy-7nm"; 4011 reg = <0 0x0ae94400 0 0x200>, 4012 <0 0x0ae94600 0 0x280>, 4013 <0 0x0ae94900 0 0x280>; 4014 reg-names = "dsi_phy", 4015 "dsi_phy_lane", 4016 "dsi_pll"; 4017 4018 #clock-cells = <1>; 4019 #phy-cells = <0>; 4020 4021 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4022 <&rpmhcc RPMH_CXO_CLK>; 4023 clock-names = "iface", "ref"; 4024 4025 status = "disabled"; 4026 }; 4027 4028 mdss_edp: edp@aea0000 { 4029 compatible = "qcom,sc7280-edp"; 4030 pinctrl-names = "default"; 4031 pinctrl-0 = <&edp_hot_plug_det>; 4032 4033 reg = <0 0x0aea0000 0 0x200>, 4034 <0 0x0aea0200 0 0x200>, 4035 <0 0x0aea0400 0 0xc00>, 4036 <0 0x0aea1000 0 0x400>; 4037 4038 interrupt-parent = <&mdss>; 4039 interrupts = <14>; 4040 4041 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4042 <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>, 4043 <&dispcc DISP_CC_MDSS_EDP_LINK_CLK>, 4044 <&dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>, 4045 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>; 4046 clock-names = "core_iface", 4047 "core_aux", 4048 "ctrl_link", 4049 "ctrl_link_iface", 4050 "stream_pixel"; 4051 assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>, 4052 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>; 4053 assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>; 4054 4055 phys = <&mdss_edp_phy>; 4056 phy-names = "dp"; 4057 4058 operating-points-v2 = <&edp_opp_table>; 4059 power-domains = <&rpmhpd SC7280_CX>; 4060 4061 status = "disabled"; 4062 4063 ports { 4064 #address-cells = <1>; 4065 #size-cells = <0>; 4066 4067 port@0 { 4068 reg = <0>; 4069 edp_in: endpoint { 4070 remote-endpoint = <&dpu_intf5_out>; 4071 }; 4072 }; 4073 4074 port@1 { 4075 reg = <1>; 4076 mdss_edp_out: endpoint { }; 4077 }; 4078 }; 4079 4080 edp_opp_table: opp-table { 4081 compatible = "operating-points-v2"; 4082 4083 opp-160000000 { 4084 opp-hz = /bits/ 64 <160000000>; 4085 required-opps = <&rpmhpd_opp_low_svs>; 4086 }; 4087 4088 opp-270000000 { 4089 opp-hz = /bits/ 64 <270000000>; 4090 required-opps = <&rpmhpd_opp_svs>; 4091 }; 4092 4093 opp-540000000 { 4094 opp-hz = /bits/ 64 <540000000>; 4095 required-opps = <&rpmhpd_opp_nom>; 4096 }; 4097 4098 opp-810000000 { 4099 opp-hz = /bits/ 64 <810000000>; 4100 required-opps = <&rpmhpd_opp_nom>; 4101 }; 4102 }; 4103 }; 4104 4105 mdss_edp_phy: phy@aec2a00 { 4106 compatible = "qcom,sc7280-edp-phy"; 4107 4108 reg = <0 0x0aec2a00 0 0x19c>, 4109 <0 0x0aec2200 0 0xa0>, 4110 <0 0x0aec2600 0 0xa0>, 4111 <0 0x0aec2000 0 0x1c0>; 4112 4113 clocks = <&rpmhcc RPMH_CXO_CLK>, 4114 <&gcc GCC_EDP_CLKREF_EN>; 4115 clock-names = "aux", 4116 "cfg_ahb"; 4117 4118 #clock-cells = <1>; 4119 #phy-cells = <0>; 4120 4121 status = "disabled"; 4122 }; 4123 4124 mdss_dp: displayport-controller@ae90000 { 4125 compatible = "qcom,sc7280-dp"; 4126 4127 reg = <0 0x0ae90000 0 0x200>, 4128 <0 0x0ae90200 0 0x200>, 4129 <0 0x0ae90400 0 0xc00>, 4130 <0 0x0ae91000 0 0x400>, 4131 <0 0x0ae91400 0 0x400>; 4132 4133 interrupt-parent = <&mdss>; 4134 interrupts = <12>; 4135 4136 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4137 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 4138 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 4139 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 4140 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 4141 clock-names = "core_iface", 4142 "core_aux", 4143 "ctrl_link", 4144 "ctrl_link_iface", 4145 "stream_pixel"; 4146 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 4147 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 4148 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>; 4149 phys = <&dp_phy>; 4150 phy-names = "dp"; 4151 4152 operating-points-v2 = <&dp_opp_table>; 4153 power-domains = <&rpmhpd SC7280_CX>; 4154 4155 #sound-dai-cells = <0>; 4156 4157 status = "disabled"; 4158 4159 ports { 4160 #address-cells = <1>; 4161 #size-cells = <0>; 4162 4163 port@0 { 4164 reg = <0>; 4165 dp_in: endpoint { 4166 remote-endpoint = <&dpu_intf0_out>; 4167 }; 4168 }; 4169 4170 port@1 { 4171 reg = <1>; 4172 mdss_dp_out: endpoint { }; 4173 }; 4174 }; 4175 4176 dp_opp_table: opp-table { 4177 compatible = "operating-points-v2"; 4178 4179 opp-160000000 { 4180 opp-hz = /bits/ 64 <160000000>; 4181 required-opps = <&rpmhpd_opp_low_svs>; 4182 }; 4183 4184 opp-270000000 { 4185 opp-hz = /bits/ 64 <270000000>; 4186 required-opps = <&rpmhpd_opp_svs>; 4187 }; 4188 4189 opp-540000000 { 4190 opp-hz = /bits/ 64 <540000000>; 4191 required-opps = <&rpmhpd_opp_svs_l1>; 4192 }; 4193 4194 opp-810000000 { 4195 opp-hz = /bits/ 64 <810000000>; 4196 required-opps = <&rpmhpd_opp_nom>; 4197 }; 4198 }; 4199 }; 4200 }; 4201 4202 pdc: interrupt-controller@b220000 { 4203 compatible = "qcom,sc7280-pdc", "qcom,pdc"; 4204 reg = <0 0x0b220000 0 0x30000>; 4205 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, 4206 <55 306 4>, <59 312 3>, <62 374 2>, 4207 <64 434 2>, <66 438 3>, <69 86 1>, 4208 <70 520 54>, <124 609 31>, <155 63 1>, 4209 <156 716 12>; 4210 #interrupt-cells = <2>; 4211 interrupt-parent = <&intc>; 4212 interrupt-controller; 4213 }; 4214 4215 pdc_reset: reset-controller@b5e0000 { 4216 compatible = "qcom,sc7280-pdc-global"; 4217 reg = <0 0x0b5e0000 0 0x20000>; 4218 #reset-cells = <1>; 4219 }; 4220 4221 tsens0: thermal-sensor@c263000 { 4222 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 4223 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 4224 <0 0x0c222000 0 0x1ff>; /* SROT */ 4225 #qcom,sensors = <15>; 4226 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 4227 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 4228 interrupt-names = "uplow","critical"; 4229 #thermal-sensor-cells = <1>; 4230 }; 4231 4232 tsens1: thermal-sensor@c265000 { 4233 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 4234 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 4235 <0 0x0c223000 0 0x1ff>; /* SROT */ 4236 #qcom,sensors = <12>; 4237 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 4238 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 4239 interrupt-names = "uplow","critical"; 4240 #thermal-sensor-cells = <1>; 4241 }; 4242 4243 aoss_reset: reset-controller@c2a0000 { 4244 compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc"; 4245 reg = <0 0x0c2a0000 0 0x31000>; 4246 #reset-cells = <1>; 4247 }; 4248 4249 aoss_qmp: power-management@c300000 { 4250 compatible = "qcom,sc7280-aoss-qmp", "qcom,aoss-qmp"; 4251 reg = <0 0x0c300000 0 0x400>; 4252 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 4253 IPCC_MPROC_SIGNAL_GLINK_QMP 4254 IRQ_TYPE_EDGE_RISING>; 4255 mboxes = <&ipcc IPCC_CLIENT_AOP 4256 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4257 4258 #clock-cells = <0>; 4259 }; 4260 4261 sram@c3f0000 { 4262 compatible = "qcom,rpmh-stats"; 4263 reg = <0 0x0c3f0000 0 0x400>; 4264 }; 4265 4266 spmi_bus: spmi@c440000 { 4267 compatible = "qcom,spmi-pmic-arb"; 4268 reg = <0 0x0c440000 0 0x1100>, 4269 <0 0x0c600000 0 0x2000000>, 4270 <0 0x0e600000 0 0x100000>, 4271 <0 0x0e700000 0 0xa0000>, 4272 <0 0x0c40a000 0 0x26000>; 4273 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 4274 interrupt-names = "periph_irq"; 4275 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 4276 qcom,ee = <0>; 4277 qcom,channel = <0>; 4278 #address-cells = <2>; 4279 #size-cells = <0>; 4280 interrupt-controller; 4281 #interrupt-cells = <4>; 4282 }; 4283 4284 tlmm: pinctrl@f100000 { 4285 compatible = "qcom,sc7280-pinctrl"; 4286 reg = <0 0x0f100000 0 0x300000>; 4287 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 4288 gpio-controller; 4289 #gpio-cells = <2>; 4290 interrupt-controller; 4291 #interrupt-cells = <2>; 4292 gpio-ranges = <&tlmm 0 0 175>; 4293 wakeup-parent = <&pdc>; 4294 4295 dp_hot_plug_det: dp-hot-plug-det-state { 4296 pins = "gpio47"; 4297 function = "dp_hot"; 4298 }; 4299 4300 edp_hot_plug_det: edp-hot-plug-det-state { 4301 pins = "gpio60"; 4302 function = "edp_hot"; 4303 }; 4304 4305 mi2s0_data0: mi2s0-data0-state { 4306 pins = "gpio98"; 4307 function = "mi2s0_data0"; 4308 }; 4309 4310 mi2s0_data1: mi2s0-data1-state { 4311 pins = "gpio99"; 4312 function = "mi2s0_data1"; 4313 }; 4314 4315 mi2s0_mclk: mi2s0-mclk-state { 4316 pins = "gpio96"; 4317 function = "pri_mi2s"; 4318 }; 4319 4320 mi2s0_sclk: mi2s0-sclk-state { 4321 pins = "gpio97"; 4322 function = "mi2s0_sck"; 4323 }; 4324 4325 mi2s0_ws: mi2s0-ws-state { 4326 pins = "gpio100"; 4327 function = "mi2s0_ws"; 4328 }; 4329 4330 mi2s1_data0: mi2s1-data0-state { 4331 pins = "gpio107"; 4332 function = "mi2s1_data0"; 4333 }; 4334 4335 mi2s1_sclk: mi2s1-sclk-state { 4336 pins = "gpio106"; 4337 function = "mi2s1_sck"; 4338 }; 4339 4340 mi2s1_ws: mi2s1-ws-state { 4341 pins = "gpio108"; 4342 function = "mi2s1_ws"; 4343 }; 4344 4345 pcie1_clkreq_n: pcie1-clkreq-n-state { 4346 pins = "gpio79"; 4347 function = "pcie1_clkreqn"; 4348 }; 4349 4350 qspi_clk: qspi-clk-state { 4351 pins = "gpio14"; 4352 function = "qspi_clk"; 4353 }; 4354 4355 qspi_cs0: qspi-cs0-state { 4356 pins = "gpio15"; 4357 function = "qspi_cs"; 4358 }; 4359 4360 qspi_cs1: qspi-cs1-state { 4361 pins = "gpio19"; 4362 function = "qspi_cs"; 4363 }; 4364 4365 qspi_data0: qspi-data0-state { 4366 pins = "gpio12"; 4367 function = "qspi_data"; 4368 }; 4369 4370 qspi_data1: qspi-data1-state { 4371 pins = "gpio13"; 4372 function = "qspi_data"; 4373 }; 4374 4375 qspi_data23: qspi-data23-state { 4376 pins = "gpio16", "gpio17"; 4377 function = "qspi_data"; 4378 }; 4379 4380 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 4381 pins = "gpio0", "gpio1"; 4382 function = "qup00"; 4383 }; 4384 4385 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 4386 pins = "gpio4", "gpio5"; 4387 function = "qup01"; 4388 }; 4389 4390 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 4391 pins = "gpio8", "gpio9"; 4392 function = "qup02"; 4393 }; 4394 4395 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 4396 pins = "gpio12", "gpio13"; 4397 function = "qup03"; 4398 }; 4399 4400 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 4401 pins = "gpio16", "gpio17"; 4402 function = "qup04"; 4403 }; 4404 4405 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 4406 pins = "gpio20", "gpio21"; 4407 function = "qup05"; 4408 }; 4409 4410 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 4411 pins = "gpio24", "gpio25"; 4412 function = "qup06"; 4413 }; 4414 4415 qup_i2c7_data_clk: qup-i2c7-data-clk-state { 4416 pins = "gpio28", "gpio29"; 4417 function = "qup07"; 4418 }; 4419 4420 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 4421 pins = "gpio32", "gpio33"; 4422 function = "qup10"; 4423 }; 4424 4425 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 4426 pins = "gpio36", "gpio37"; 4427 function = "qup11"; 4428 }; 4429 4430 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 4431 pins = "gpio40", "gpio41"; 4432 function = "qup12"; 4433 }; 4434 4435 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 4436 pins = "gpio44", "gpio45"; 4437 function = "qup13"; 4438 }; 4439 4440 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 4441 pins = "gpio48", "gpio49"; 4442 function = "qup14"; 4443 }; 4444 4445 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 4446 pins = "gpio52", "gpio53"; 4447 function = "qup15"; 4448 }; 4449 4450 qup_i2c14_data_clk: qup-i2c14-data-clk-state { 4451 pins = "gpio56", "gpio57"; 4452 function = "qup16"; 4453 }; 4454 4455 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 4456 pins = "gpio60", "gpio61"; 4457 function = "qup17"; 4458 }; 4459 4460 qup_spi0_data_clk: qup-spi0-data-clk-state { 4461 pins = "gpio0", "gpio1", "gpio2"; 4462 function = "qup00"; 4463 }; 4464 4465 qup_spi0_cs: qup-spi0-cs-state { 4466 pins = "gpio3"; 4467 function = "qup00"; 4468 }; 4469 4470 qup_spi0_cs_gpio: qup-spi0-cs-gpio-state { 4471 pins = "gpio3"; 4472 function = "gpio"; 4473 }; 4474 4475 qup_spi1_data_clk: qup-spi1-data-clk-state { 4476 pins = "gpio4", "gpio5", "gpio6"; 4477 function = "qup01"; 4478 }; 4479 4480 qup_spi1_cs: qup-spi1-cs-state { 4481 pins = "gpio7"; 4482 function = "qup01"; 4483 }; 4484 4485 qup_spi1_cs_gpio: qup-spi1-cs-gpio-state { 4486 pins = "gpio7"; 4487 function = "gpio"; 4488 }; 4489 4490 qup_spi2_data_clk: qup-spi2-data-clk-state { 4491 pins = "gpio8", "gpio9", "gpio10"; 4492 function = "qup02"; 4493 }; 4494 4495 qup_spi2_cs: qup-spi2-cs-state { 4496 pins = "gpio11"; 4497 function = "qup02"; 4498 }; 4499 4500 qup_spi2_cs_gpio: qup-spi2-cs-gpio-state { 4501 pins = "gpio11"; 4502 function = "gpio"; 4503 }; 4504 4505 qup_spi3_data_clk: qup-spi3-data-clk-state { 4506 pins = "gpio12", "gpio13", "gpio14"; 4507 function = "qup03"; 4508 }; 4509 4510 qup_spi3_cs: qup-spi3-cs-state { 4511 pins = "gpio15"; 4512 function = "qup03"; 4513 }; 4514 4515 qup_spi3_cs_gpio: qup-spi3-cs-gpio-state { 4516 pins = "gpio15"; 4517 function = "gpio"; 4518 }; 4519 4520 qup_spi4_data_clk: qup-spi4-data-clk-state { 4521 pins = "gpio16", "gpio17", "gpio18"; 4522 function = "qup04"; 4523 }; 4524 4525 qup_spi4_cs: qup-spi4-cs-state { 4526 pins = "gpio19"; 4527 function = "qup04"; 4528 }; 4529 4530 qup_spi4_cs_gpio: qup-spi4-cs-gpio-state { 4531 pins = "gpio19"; 4532 function = "gpio"; 4533 }; 4534 4535 qup_spi5_data_clk: qup-spi5-data-clk-state { 4536 pins = "gpio20", "gpio21", "gpio22"; 4537 function = "qup05"; 4538 }; 4539 4540 qup_spi5_cs: qup-spi5-cs-state { 4541 pins = "gpio23"; 4542 function = "qup05"; 4543 }; 4544 4545 qup_spi5_cs_gpio: qup-spi5-cs-gpio-state { 4546 pins = "gpio23"; 4547 function = "gpio"; 4548 }; 4549 4550 qup_spi6_data_clk: qup-spi6-data-clk-state { 4551 pins = "gpio24", "gpio25", "gpio26"; 4552 function = "qup06"; 4553 }; 4554 4555 qup_spi6_cs: qup-spi6-cs-state { 4556 pins = "gpio27"; 4557 function = "qup06"; 4558 }; 4559 4560 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state { 4561 pins = "gpio27"; 4562 function = "gpio"; 4563 }; 4564 4565 qup_spi7_data_clk: qup-spi7-data-clk-state { 4566 pins = "gpio28", "gpio29", "gpio30"; 4567 function = "qup07"; 4568 }; 4569 4570 qup_spi7_cs: qup-spi7-cs-state { 4571 pins = "gpio31"; 4572 function = "qup07"; 4573 }; 4574 4575 qup_spi7_cs_gpio: qup-spi7-cs-gpio-state { 4576 pins = "gpio31"; 4577 function = "gpio"; 4578 }; 4579 4580 qup_spi8_data_clk: qup-spi8-data-clk-state { 4581 pins = "gpio32", "gpio33", "gpio34"; 4582 function = "qup10"; 4583 }; 4584 4585 qup_spi8_cs: qup-spi8-cs-state { 4586 pins = "gpio35"; 4587 function = "qup10"; 4588 }; 4589 4590 qup_spi8_cs_gpio: qup-spi8-cs-gpio-state { 4591 pins = "gpio35"; 4592 function = "gpio"; 4593 }; 4594 4595 qup_spi9_data_clk: qup-spi9-data-clk-state { 4596 pins = "gpio36", "gpio37", "gpio38"; 4597 function = "qup11"; 4598 }; 4599 4600 qup_spi9_cs: qup-spi9-cs-state { 4601 pins = "gpio39"; 4602 function = "qup11"; 4603 }; 4604 4605 qup_spi9_cs_gpio: qup-spi9-cs-gpio-state { 4606 pins = "gpio39"; 4607 function = "gpio"; 4608 }; 4609 4610 qup_spi10_data_clk: qup-spi10-data-clk-state { 4611 pins = "gpio40", "gpio41", "gpio42"; 4612 function = "qup12"; 4613 }; 4614 4615 qup_spi10_cs: qup-spi10-cs-state { 4616 pins = "gpio43"; 4617 function = "qup12"; 4618 }; 4619 4620 qup_spi10_cs_gpio: qup-spi10-cs-gpio-state { 4621 pins = "gpio43"; 4622 function = "gpio"; 4623 }; 4624 4625 qup_spi11_data_clk: qup-spi11-data-clk-state { 4626 pins = "gpio44", "gpio45", "gpio46"; 4627 function = "qup13"; 4628 }; 4629 4630 qup_spi11_cs: qup-spi11-cs-state { 4631 pins = "gpio47"; 4632 function = "qup13"; 4633 }; 4634 4635 qup_spi11_cs_gpio: qup-spi11-cs-gpio-state { 4636 pins = "gpio47"; 4637 function = "gpio"; 4638 }; 4639 4640 qup_spi12_data_clk: qup-spi12-data-clk-state { 4641 pins = "gpio48", "gpio49", "gpio50"; 4642 function = "qup14"; 4643 }; 4644 4645 qup_spi12_cs: qup-spi12-cs-state { 4646 pins = "gpio51"; 4647 function = "qup14"; 4648 }; 4649 4650 qup_spi12_cs_gpio: qup-spi12-cs-gpio-state { 4651 pins = "gpio51"; 4652 function = "gpio"; 4653 }; 4654 4655 qup_spi13_data_clk: qup-spi13-data-clk-state { 4656 pins = "gpio52", "gpio53", "gpio54"; 4657 function = "qup15"; 4658 }; 4659 4660 qup_spi13_cs: qup-spi13-cs-state { 4661 pins = "gpio55"; 4662 function = "qup15"; 4663 }; 4664 4665 qup_spi13_cs_gpio: qup-spi13-cs-gpio-state { 4666 pins = "gpio55"; 4667 function = "gpio"; 4668 }; 4669 4670 qup_spi14_data_clk: qup-spi14-data-clk-state { 4671 pins = "gpio56", "gpio57", "gpio58"; 4672 function = "qup16"; 4673 }; 4674 4675 qup_spi14_cs: qup-spi14-cs-state { 4676 pins = "gpio59"; 4677 function = "qup16"; 4678 }; 4679 4680 qup_spi14_cs_gpio: qup-spi14-cs-gpio-state { 4681 pins = "gpio59"; 4682 function = "gpio"; 4683 }; 4684 4685 qup_spi15_data_clk: qup-spi15-data-clk-state { 4686 pins = "gpio60", "gpio61", "gpio62"; 4687 function = "qup17"; 4688 }; 4689 4690 qup_spi15_cs: qup-spi15-cs-state { 4691 pins = "gpio63"; 4692 function = "qup17"; 4693 }; 4694 4695 qup_spi15_cs_gpio: qup-spi15-cs-gpio-state { 4696 pins = "gpio63"; 4697 function = "gpio"; 4698 }; 4699 4700 qup_uart0_cts: qup-uart0-cts-state { 4701 pins = "gpio0"; 4702 function = "qup00"; 4703 }; 4704 4705 qup_uart0_rts: qup-uart0-rts-state { 4706 pins = "gpio1"; 4707 function = "qup00"; 4708 }; 4709 4710 qup_uart0_tx: qup-uart0-tx-state { 4711 pins = "gpio2"; 4712 function = "qup00"; 4713 }; 4714 4715 qup_uart0_rx: qup-uart0-rx-state { 4716 pins = "gpio3"; 4717 function = "qup00"; 4718 }; 4719 4720 qup_uart1_cts: qup-uart1-cts-state { 4721 pins = "gpio4"; 4722 function = "qup01"; 4723 }; 4724 4725 qup_uart1_rts: qup-uart1-rts-state { 4726 pins = "gpio5"; 4727 function = "qup01"; 4728 }; 4729 4730 qup_uart1_tx: qup-uart1-tx-state { 4731 pins = "gpio6"; 4732 function = "qup01"; 4733 }; 4734 4735 qup_uart1_rx: qup-uart1-rx-state { 4736 pins = "gpio7"; 4737 function = "qup01"; 4738 }; 4739 4740 qup_uart2_cts: qup-uart2-cts-state { 4741 pins = "gpio8"; 4742 function = "qup02"; 4743 }; 4744 4745 qup_uart2_rts: qup-uart2-rts-state { 4746 pins = "gpio9"; 4747 function = "qup02"; 4748 }; 4749 4750 qup_uart2_tx: qup-uart2-tx-state { 4751 pins = "gpio10"; 4752 function = "qup02"; 4753 }; 4754 4755 qup_uart2_rx: qup-uart2-rx-state { 4756 pins = "gpio11"; 4757 function = "qup02"; 4758 }; 4759 4760 qup_uart3_cts: qup-uart3-cts-state { 4761 pins = "gpio12"; 4762 function = "qup03"; 4763 }; 4764 4765 qup_uart3_rts: qup-uart3-rts-state { 4766 pins = "gpio13"; 4767 function = "qup03"; 4768 }; 4769 4770 qup_uart3_tx: qup-uart3-tx-state { 4771 pins = "gpio14"; 4772 function = "qup03"; 4773 }; 4774 4775 qup_uart3_rx: qup-uart3-rx-state { 4776 pins = "gpio15"; 4777 function = "qup03"; 4778 }; 4779 4780 qup_uart4_cts: qup-uart4-cts-state { 4781 pins = "gpio16"; 4782 function = "qup04"; 4783 }; 4784 4785 qup_uart4_rts: qup-uart4-rts-state { 4786 pins = "gpio17"; 4787 function = "qup04"; 4788 }; 4789 4790 qup_uart4_tx: qup-uart4-tx-state { 4791 pins = "gpio18"; 4792 function = "qup04"; 4793 }; 4794 4795 qup_uart4_rx: qup-uart4-rx-state { 4796 pins = "gpio19"; 4797 function = "qup04"; 4798 }; 4799 4800 qup_uart5_cts: qup-uart5-cts-state { 4801 pins = "gpio20"; 4802 function = "qup05"; 4803 }; 4804 4805 qup_uart5_rts: qup-uart5-rts-state { 4806 pins = "gpio21"; 4807 function = "qup05"; 4808 }; 4809 4810 qup_uart5_tx: qup-uart5-tx-state { 4811 pins = "gpio22"; 4812 function = "qup05"; 4813 }; 4814 4815 qup_uart5_rx: qup-uart5-rx-state { 4816 pins = "gpio23"; 4817 function = "qup05"; 4818 }; 4819 4820 qup_uart6_cts: qup-uart6-cts-state { 4821 pins = "gpio24"; 4822 function = "qup06"; 4823 }; 4824 4825 qup_uart6_rts: qup-uart6-rts-state { 4826 pins = "gpio25"; 4827 function = "qup06"; 4828 }; 4829 4830 qup_uart6_tx: qup-uart6-tx-state { 4831 pins = "gpio26"; 4832 function = "qup06"; 4833 }; 4834 4835 qup_uart6_rx: qup-uart6-rx-state { 4836 pins = "gpio27"; 4837 function = "qup06"; 4838 }; 4839 4840 qup_uart7_cts: qup-uart7-cts-state { 4841 pins = "gpio28"; 4842 function = "qup07"; 4843 }; 4844 4845 qup_uart7_rts: qup-uart7-rts-state { 4846 pins = "gpio29"; 4847 function = "qup07"; 4848 }; 4849 4850 qup_uart7_tx: qup-uart7-tx-state { 4851 pins = "gpio30"; 4852 function = "qup07"; 4853 }; 4854 4855 qup_uart7_rx: qup-uart7-rx-state { 4856 pins = "gpio31"; 4857 function = "qup07"; 4858 }; 4859 4860 qup_uart8_cts: qup-uart8-cts-state { 4861 pins = "gpio32"; 4862 function = "qup10"; 4863 }; 4864 4865 qup_uart8_rts: qup-uart8-rts-state { 4866 pins = "gpio33"; 4867 function = "qup10"; 4868 }; 4869 4870 qup_uart8_tx: qup-uart8-tx-state { 4871 pins = "gpio34"; 4872 function = "qup10"; 4873 }; 4874 4875 qup_uart8_rx: qup-uart8-rx-state { 4876 pins = "gpio35"; 4877 function = "qup10"; 4878 }; 4879 4880 qup_uart9_cts: qup-uart9-cts-state { 4881 pins = "gpio36"; 4882 function = "qup11"; 4883 }; 4884 4885 qup_uart9_rts: qup-uart9-rts-state { 4886 pins = "gpio37"; 4887 function = "qup11"; 4888 }; 4889 4890 qup_uart9_tx: qup-uart9-tx-state { 4891 pins = "gpio38"; 4892 function = "qup11"; 4893 }; 4894 4895 qup_uart9_rx: qup-uart9-rx-state { 4896 pins = "gpio39"; 4897 function = "qup11"; 4898 }; 4899 4900 qup_uart10_cts: qup-uart10-cts-state { 4901 pins = "gpio40"; 4902 function = "qup12"; 4903 }; 4904 4905 qup_uart10_rts: qup-uart10-rts-state { 4906 pins = "gpio41"; 4907 function = "qup12"; 4908 }; 4909 4910 qup_uart10_tx: qup-uart10-tx-state { 4911 pins = "gpio42"; 4912 function = "qup12"; 4913 }; 4914 4915 qup_uart10_rx: qup-uart10-rx-state { 4916 pins = "gpio43"; 4917 function = "qup12"; 4918 }; 4919 4920 qup_uart11_cts: qup-uart11-cts-state { 4921 pins = "gpio44"; 4922 function = "qup13"; 4923 }; 4924 4925 qup_uart11_rts: qup-uart11-rts-state { 4926 pins = "gpio45"; 4927 function = "qup13"; 4928 }; 4929 4930 qup_uart11_tx: qup-uart11-tx-state { 4931 pins = "gpio46"; 4932 function = "qup13"; 4933 }; 4934 4935 qup_uart11_rx: qup-uart11-rx-state { 4936 pins = "gpio47"; 4937 function = "qup13"; 4938 }; 4939 4940 qup_uart12_cts: qup-uart12-cts-state { 4941 pins = "gpio48"; 4942 function = "qup14"; 4943 }; 4944 4945 qup_uart12_rts: qup-uart12-rts-state { 4946 pins = "gpio49"; 4947 function = "qup14"; 4948 }; 4949 4950 qup_uart12_tx: qup-uart12-tx-state { 4951 pins = "gpio50"; 4952 function = "qup14"; 4953 }; 4954 4955 qup_uart12_rx: qup-uart12-rx-state { 4956 pins = "gpio51"; 4957 function = "qup14"; 4958 }; 4959 4960 qup_uart13_cts: qup-uart13-cts-state { 4961 pins = "gpio52"; 4962 function = "qup15"; 4963 }; 4964 4965 qup_uart13_rts: qup-uart13-rts-state { 4966 pins = "gpio53"; 4967 function = "qup15"; 4968 }; 4969 4970 qup_uart13_tx: qup-uart13-tx-state { 4971 pins = "gpio54"; 4972 function = "qup15"; 4973 }; 4974 4975 qup_uart13_rx: qup-uart13-rx-state { 4976 pins = "gpio55"; 4977 function = "qup15"; 4978 }; 4979 4980 qup_uart14_cts: qup-uart14-cts-state { 4981 pins = "gpio56"; 4982 function = "qup16"; 4983 }; 4984 4985 qup_uart14_rts: qup-uart14-rts-state { 4986 pins = "gpio57"; 4987 function = "qup16"; 4988 }; 4989 4990 qup_uart14_tx: qup-uart14-tx-state { 4991 pins = "gpio58"; 4992 function = "qup16"; 4993 }; 4994 4995 qup_uart14_rx: qup-uart14-rx-state { 4996 pins = "gpio59"; 4997 function = "qup16"; 4998 }; 4999 5000 qup_uart15_cts: qup-uart15-cts-state { 5001 pins = "gpio60"; 5002 function = "qup17"; 5003 }; 5004 5005 qup_uart15_rts: qup-uart15-rts-state { 5006 pins = "gpio61"; 5007 function = "qup17"; 5008 }; 5009 5010 qup_uart15_tx: qup-uart15-tx-state { 5011 pins = "gpio62"; 5012 function = "qup17"; 5013 }; 5014 5015 qup_uart15_rx: qup-uart15-rx-state { 5016 pins = "gpio63"; 5017 function = "qup17"; 5018 }; 5019 5020 sdc1_clk: sdc1-clk-state { 5021 pins = "sdc1_clk"; 5022 }; 5023 5024 sdc1_cmd: sdc1-cmd-state { 5025 pins = "sdc1_cmd"; 5026 }; 5027 5028 sdc1_data: sdc1-data-state { 5029 pins = "sdc1_data"; 5030 }; 5031 5032 sdc1_rclk: sdc1-rclk-state { 5033 pins = "sdc1_rclk"; 5034 }; 5035 5036 sdc1_clk_sleep: sdc1-clk-sleep-state { 5037 pins = "sdc1_clk"; 5038 drive-strength = <2>; 5039 bias-bus-hold; 5040 }; 5041 5042 sdc1_cmd_sleep: sdc1-cmd-sleep-state { 5043 pins = "sdc1_cmd"; 5044 drive-strength = <2>; 5045 bias-bus-hold; 5046 }; 5047 5048 sdc1_data_sleep: sdc1-data-sleep-state { 5049 pins = "sdc1_data"; 5050 drive-strength = <2>; 5051 bias-bus-hold; 5052 }; 5053 5054 sdc1_rclk_sleep: sdc1-rclk-sleep-state { 5055 pins = "sdc1_rclk"; 5056 drive-strength = <2>; 5057 bias-bus-hold; 5058 }; 5059 5060 sdc2_clk: sdc2-clk-state { 5061 pins = "sdc2_clk"; 5062 }; 5063 5064 sdc2_cmd: sdc2-cmd-state { 5065 pins = "sdc2_cmd"; 5066 }; 5067 5068 sdc2_data: sdc2-data-state { 5069 pins = "sdc2_data"; 5070 }; 5071 5072 sdc2_clk_sleep: sdc2-clk-sleep-state { 5073 pins = "sdc2_clk"; 5074 drive-strength = <2>; 5075 bias-bus-hold; 5076 }; 5077 5078 sdc2_cmd_sleep: sdc2-cmd-sleep-state { 5079 pins = "sdc2_cmd"; 5080 drive-strength = <2>; 5081 bias-bus-hold; 5082 }; 5083 5084 sdc2_data_sleep: sdc2-data-sleep-state { 5085 pins = "sdc2_data"; 5086 drive-strength = <2>; 5087 bias-bus-hold; 5088 }; 5089 }; 5090 5091 sram@146a5000 { 5092 compatible = "qcom,sc7280-imem", "syscon", "simple-mfd"; 5093 reg = <0 0x146a5000 0 0x6000>; 5094 5095 #address-cells = <1>; 5096 #size-cells = <1>; 5097 5098 ranges = <0 0 0x146a5000 0x6000>; 5099 5100 pil-reloc@594c { 5101 compatible = "qcom,pil-reloc-info"; 5102 reg = <0x594c 0xc8>; 5103 }; 5104 }; 5105 5106 apps_smmu: iommu@15000000 { 5107 compatible = "qcom,sc7280-smmu-500", "arm,mmu-500"; 5108 reg = <0 0x15000000 0 0x100000>; 5109 #iommu-cells = <2>; 5110 #global-interrupts = <1>; 5111 dma-coherent; 5112 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 5113 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 5114 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 5115 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 5116 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 5117 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 5118 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 5119 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 5120 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 5121 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 5122 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 5123 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 5124 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 5125 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 5126 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 5127 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 5128 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 5129 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 5130 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 5131 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 5132 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 5133 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 5134 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 5135 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 5136 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 5137 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 5138 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 5139 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 5140 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 5141 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 5142 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 5143 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 5144 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 5145 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 5146 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 5147 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 5148 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 5149 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 5150 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 5151 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 5152 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 5153 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 5154 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 5155 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 5156 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 5157 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 5158 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 5159 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 5160 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 5161 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 5162 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 5163 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 5164 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 5165 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 5166 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 5167 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 5168 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 5169 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 5170 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 5171 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 5172 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 5173 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 5174 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 5175 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 5176 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 5177 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 5178 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 5179 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 5180 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 5181 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 5182 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 5183 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 5184 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 5185 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 5186 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 5187 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 5188 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 5189 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 5190 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 5191 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 5192 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 5193 }; 5194 5195 intc: interrupt-controller@17a00000 { 5196 compatible = "arm,gic-v3"; 5197 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 5198 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 5199 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 5200 #interrupt-cells = <3>; 5201 interrupt-controller; 5202 #address-cells = <2>; 5203 #size-cells = <2>; 5204 ranges; 5205 5206 msi-controller@17a40000 { 5207 compatible = "arm,gic-v3-its"; 5208 reg = <0 0x17a40000 0 0x20000>; 5209 msi-controller; 5210 #msi-cells = <1>; 5211 status = "disabled"; 5212 }; 5213 }; 5214 5215 watchdog@17c10000 { 5216 compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt"; 5217 reg = <0 0x17c10000 0 0x1000>; 5218 clocks = <&sleep_clk>; 5219 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 5220 }; 5221 5222 timer@17c20000 { 5223 #address-cells = <1>; 5224 #size-cells = <1>; 5225 ranges = <0 0 0 0x20000000>; 5226 compatible = "arm,armv7-timer-mem"; 5227 reg = <0 0x17c20000 0 0x1000>; 5228 5229 frame@17c21000 { 5230 frame-number = <0>; 5231 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 5232 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 5233 reg = <0x17c21000 0x1000>, 5234 <0x17c22000 0x1000>; 5235 }; 5236 5237 frame@17c23000 { 5238 frame-number = <1>; 5239 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 5240 reg = <0x17c23000 0x1000>; 5241 status = "disabled"; 5242 }; 5243 5244 frame@17c25000 { 5245 frame-number = <2>; 5246 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 5247 reg = <0x17c25000 0x1000>; 5248 status = "disabled"; 5249 }; 5250 5251 frame@17c27000 { 5252 frame-number = <3>; 5253 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 5254 reg = <0x17c27000 0x1000>; 5255 status = "disabled"; 5256 }; 5257 5258 frame@17c29000 { 5259 frame-number = <4>; 5260 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 5261 reg = <0x17c29000 0x1000>; 5262 status = "disabled"; 5263 }; 5264 5265 frame@17c2b000 { 5266 frame-number = <5>; 5267 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 5268 reg = <0x17c2b000 0x1000>; 5269 status = "disabled"; 5270 }; 5271 5272 frame@17c2d000 { 5273 frame-number = <6>; 5274 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 5275 reg = <0x17c2d000 0x1000>; 5276 status = "disabled"; 5277 }; 5278 }; 5279 5280 apps_rsc: rsc@18200000 { 5281 compatible = "qcom,rpmh-rsc"; 5282 reg = <0 0x18200000 0 0x10000>, 5283 <0 0x18210000 0 0x10000>, 5284 <0 0x18220000 0 0x10000>; 5285 reg-names = "drv-0", "drv-1", "drv-2"; 5286 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 5287 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 5288 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 5289 qcom,tcs-offset = <0xd00>; 5290 qcom,drv-id = <2>; 5291 qcom,tcs-config = <ACTIVE_TCS 2>, 5292 <SLEEP_TCS 3>, 5293 <WAKE_TCS 3>, 5294 <CONTROL_TCS 1>; 5295 5296 apps_bcm_voter: bcm-voter { 5297 compatible = "qcom,bcm-voter"; 5298 }; 5299 5300 rpmhpd: power-controller { 5301 compatible = "qcom,sc7280-rpmhpd"; 5302 #power-domain-cells = <1>; 5303 operating-points-v2 = <&rpmhpd_opp_table>; 5304 5305 rpmhpd_opp_table: opp-table { 5306 compatible = "operating-points-v2"; 5307 5308 rpmhpd_opp_ret: opp1 { 5309 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 5310 }; 5311 5312 rpmhpd_opp_low_svs: opp2 { 5313 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 5314 }; 5315 5316 rpmhpd_opp_svs: opp3 { 5317 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 5318 }; 5319 5320 rpmhpd_opp_svs_l1: opp4 { 5321 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 5322 }; 5323 5324 rpmhpd_opp_svs_l2: opp5 { 5325 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 5326 }; 5327 5328 rpmhpd_opp_nom: opp6 { 5329 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 5330 }; 5331 5332 rpmhpd_opp_nom_l1: opp7 { 5333 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 5334 }; 5335 5336 rpmhpd_opp_turbo: opp8 { 5337 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 5338 }; 5339 5340 rpmhpd_opp_turbo_l1: opp9 { 5341 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 5342 }; 5343 }; 5344 }; 5345 5346 rpmhcc: clock-controller { 5347 compatible = "qcom,sc7280-rpmh-clk"; 5348 clocks = <&xo_board>; 5349 clock-names = "xo"; 5350 #clock-cells = <1>; 5351 }; 5352 }; 5353 5354 epss_l3: interconnect@18590000 { 5355 compatible = "qcom,sc7280-epss-l3", "qcom,epss-l3"; 5356 reg = <0 0x18590000 0 0x1000>; 5357 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 5358 clock-names = "xo", "alternate"; 5359 #interconnect-cells = <1>; 5360 }; 5361 5362 cpufreq_hw: cpufreq@18591000 { 5363 compatible = "qcom,sc7280-cpufreq-epss", "qcom,cpufreq-epss"; 5364 reg = <0 0x18591000 0 0x1000>, 5365 <0 0x18592000 0 0x1000>, 5366 <0 0x18593000 0 0x1000>; 5367 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 5368 clock-names = "xo", "alternate"; 5369 #freq-domain-cells = <1>; 5370 #clock-cells = <1>; 5371 }; 5372 }; 5373 5374 thermal_zones: thermal-zones { 5375 cpu0-thermal { 5376 polling-delay-passive = <250>; 5377 polling-delay = <0>; 5378 5379 thermal-sensors = <&tsens0 1>; 5380 5381 trips { 5382 cpu0_alert0: trip-point0 { 5383 temperature = <90000>; 5384 hysteresis = <2000>; 5385 type = "passive"; 5386 }; 5387 5388 cpu0_alert1: trip-point1 { 5389 temperature = <95000>; 5390 hysteresis = <2000>; 5391 type = "passive"; 5392 }; 5393 5394 cpu0_crit: cpu-crit { 5395 temperature = <110000>; 5396 hysteresis = <0>; 5397 type = "critical"; 5398 }; 5399 }; 5400 5401 cooling-maps { 5402 map0 { 5403 trip = <&cpu0_alert0>; 5404 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5405 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5406 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5407 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5408 }; 5409 map1 { 5410 trip = <&cpu0_alert1>; 5411 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5412 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5413 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5414 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5415 }; 5416 }; 5417 }; 5418 5419 cpu1-thermal { 5420 polling-delay-passive = <250>; 5421 polling-delay = <0>; 5422 5423 thermal-sensors = <&tsens0 2>; 5424 5425 trips { 5426 cpu1_alert0: trip-point0 { 5427 temperature = <90000>; 5428 hysteresis = <2000>; 5429 type = "passive"; 5430 }; 5431 5432 cpu1_alert1: trip-point1 { 5433 temperature = <95000>; 5434 hysteresis = <2000>; 5435 type = "passive"; 5436 }; 5437 5438 cpu1_crit: cpu-crit { 5439 temperature = <110000>; 5440 hysteresis = <0>; 5441 type = "critical"; 5442 }; 5443 }; 5444 5445 cooling-maps { 5446 map0 { 5447 trip = <&cpu1_alert0>; 5448 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5449 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5450 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5451 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5452 }; 5453 map1 { 5454 trip = <&cpu1_alert1>; 5455 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5456 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5457 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5458 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5459 }; 5460 }; 5461 }; 5462 5463 cpu2-thermal { 5464 polling-delay-passive = <250>; 5465 polling-delay = <0>; 5466 5467 thermal-sensors = <&tsens0 3>; 5468 5469 trips { 5470 cpu2_alert0: trip-point0 { 5471 temperature = <90000>; 5472 hysteresis = <2000>; 5473 type = "passive"; 5474 }; 5475 5476 cpu2_alert1: trip-point1 { 5477 temperature = <95000>; 5478 hysteresis = <2000>; 5479 type = "passive"; 5480 }; 5481 5482 cpu2_crit: cpu-crit { 5483 temperature = <110000>; 5484 hysteresis = <0>; 5485 type = "critical"; 5486 }; 5487 }; 5488 5489 cooling-maps { 5490 map0 { 5491 trip = <&cpu2_alert0>; 5492 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5493 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5494 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5495 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5496 }; 5497 map1 { 5498 trip = <&cpu2_alert1>; 5499 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5500 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5501 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5502 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5503 }; 5504 }; 5505 }; 5506 5507 cpu3-thermal { 5508 polling-delay-passive = <250>; 5509 polling-delay = <0>; 5510 5511 thermal-sensors = <&tsens0 4>; 5512 5513 trips { 5514 cpu3_alert0: trip-point0 { 5515 temperature = <90000>; 5516 hysteresis = <2000>; 5517 type = "passive"; 5518 }; 5519 5520 cpu3_alert1: trip-point1 { 5521 temperature = <95000>; 5522 hysteresis = <2000>; 5523 type = "passive"; 5524 }; 5525 5526 cpu3_crit: cpu-crit { 5527 temperature = <110000>; 5528 hysteresis = <0>; 5529 type = "critical"; 5530 }; 5531 }; 5532 5533 cooling-maps { 5534 map0 { 5535 trip = <&cpu3_alert0>; 5536 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5537 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5538 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5539 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5540 }; 5541 map1 { 5542 trip = <&cpu3_alert1>; 5543 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5544 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5545 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5546 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5547 }; 5548 }; 5549 }; 5550 5551 cpu4-thermal { 5552 polling-delay-passive = <250>; 5553 polling-delay = <0>; 5554 5555 thermal-sensors = <&tsens0 7>; 5556 5557 trips { 5558 cpu4_alert0: trip-point0 { 5559 temperature = <90000>; 5560 hysteresis = <2000>; 5561 type = "passive"; 5562 }; 5563 5564 cpu4_alert1: trip-point1 { 5565 temperature = <95000>; 5566 hysteresis = <2000>; 5567 type = "passive"; 5568 }; 5569 5570 cpu4_crit: cpu-crit { 5571 temperature = <110000>; 5572 hysteresis = <0>; 5573 type = "critical"; 5574 }; 5575 }; 5576 5577 cooling-maps { 5578 map0 { 5579 trip = <&cpu4_alert0>; 5580 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5581 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5582 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5583 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5584 }; 5585 map1 { 5586 trip = <&cpu4_alert1>; 5587 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5588 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5589 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5590 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5591 }; 5592 }; 5593 }; 5594 5595 cpu5-thermal { 5596 polling-delay-passive = <250>; 5597 polling-delay = <0>; 5598 5599 thermal-sensors = <&tsens0 8>; 5600 5601 trips { 5602 cpu5_alert0: trip-point0 { 5603 temperature = <90000>; 5604 hysteresis = <2000>; 5605 type = "passive"; 5606 }; 5607 5608 cpu5_alert1: trip-point1 { 5609 temperature = <95000>; 5610 hysteresis = <2000>; 5611 type = "passive"; 5612 }; 5613 5614 cpu5_crit: cpu-crit { 5615 temperature = <110000>; 5616 hysteresis = <0>; 5617 type = "critical"; 5618 }; 5619 }; 5620 5621 cooling-maps { 5622 map0 { 5623 trip = <&cpu5_alert0>; 5624 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5625 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5626 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5627 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5628 }; 5629 map1 { 5630 trip = <&cpu5_alert1>; 5631 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5632 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5633 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5634 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5635 }; 5636 }; 5637 }; 5638 5639 cpu6-thermal { 5640 polling-delay-passive = <250>; 5641 polling-delay = <0>; 5642 5643 thermal-sensors = <&tsens0 9>; 5644 5645 trips { 5646 cpu6_alert0: trip-point0 { 5647 temperature = <90000>; 5648 hysteresis = <2000>; 5649 type = "passive"; 5650 }; 5651 5652 cpu6_alert1: trip-point1 { 5653 temperature = <95000>; 5654 hysteresis = <2000>; 5655 type = "passive"; 5656 }; 5657 5658 cpu6_crit: cpu-crit { 5659 temperature = <110000>; 5660 hysteresis = <0>; 5661 type = "critical"; 5662 }; 5663 }; 5664 5665 cooling-maps { 5666 map0 { 5667 trip = <&cpu6_alert0>; 5668 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5669 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5670 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5671 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5672 }; 5673 map1 { 5674 trip = <&cpu6_alert1>; 5675 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5676 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5677 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5678 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5679 }; 5680 }; 5681 }; 5682 5683 cpu7-thermal { 5684 polling-delay-passive = <250>; 5685 polling-delay = <0>; 5686 5687 thermal-sensors = <&tsens0 10>; 5688 5689 trips { 5690 cpu7_alert0: trip-point0 { 5691 temperature = <90000>; 5692 hysteresis = <2000>; 5693 type = "passive"; 5694 }; 5695 5696 cpu7_alert1: trip-point1 { 5697 temperature = <95000>; 5698 hysteresis = <2000>; 5699 type = "passive"; 5700 }; 5701 5702 cpu7_crit: cpu-crit { 5703 temperature = <110000>; 5704 hysteresis = <0>; 5705 type = "critical"; 5706 }; 5707 }; 5708 5709 cooling-maps { 5710 map0 { 5711 trip = <&cpu7_alert0>; 5712 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5713 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5714 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5715 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5716 }; 5717 map1 { 5718 trip = <&cpu7_alert1>; 5719 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5720 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5721 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5722 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5723 }; 5724 }; 5725 }; 5726 5727 cpu8-thermal { 5728 polling-delay-passive = <250>; 5729 polling-delay = <0>; 5730 5731 thermal-sensors = <&tsens0 11>; 5732 5733 trips { 5734 cpu8_alert0: trip-point0 { 5735 temperature = <90000>; 5736 hysteresis = <2000>; 5737 type = "passive"; 5738 }; 5739 5740 cpu8_alert1: trip-point1 { 5741 temperature = <95000>; 5742 hysteresis = <2000>; 5743 type = "passive"; 5744 }; 5745 5746 cpu8_crit: cpu-crit { 5747 temperature = <110000>; 5748 hysteresis = <0>; 5749 type = "critical"; 5750 }; 5751 }; 5752 5753 cooling-maps { 5754 map0 { 5755 trip = <&cpu8_alert0>; 5756 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5757 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5758 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5759 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5760 }; 5761 map1 { 5762 trip = <&cpu8_alert1>; 5763 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5764 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5765 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5766 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5767 }; 5768 }; 5769 }; 5770 5771 cpu9-thermal { 5772 polling-delay-passive = <250>; 5773 polling-delay = <0>; 5774 5775 thermal-sensors = <&tsens0 12>; 5776 5777 trips { 5778 cpu9_alert0: trip-point0 { 5779 temperature = <90000>; 5780 hysteresis = <2000>; 5781 type = "passive"; 5782 }; 5783 5784 cpu9_alert1: trip-point1 { 5785 temperature = <95000>; 5786 hysteresis = <2000>; 5787 type = "passive"; 5788 }; 5789 5790 cpu9_crit: cpu-crit { 5791 temperature = <110000>; 5792 hysteresis = <0>; 5793 type = "critical"; 5794 }; 5795 }; 5796 5797 cooling-maps { 5798 map0 { 5799 trip = <&cpu9_alert0>; 5800 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5801 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5802 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5803 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5804 }; 5805 map1 { 5806 trip = <&cpu9_alert1>; 5807 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5808 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5809 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5810 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5811 }; 5812 }; 5813 }; 5814 5815 cpu10-thermal { 5816 polling-delay-passive = <250>; 5817 polling-delay = <0>; 5818 5819 thermal-sensors = <&tsens0 13>; 5820 5821 trips { 5822 cpu10_alert0: trip-point0 { 5823 temperature = <90000>; 5824 hysteresis = <2000>; 5825 type = "passive"; 5826 }; 5827 5828 cpu10_alert1: trip-point1 { 5829 temperature = <95000>; 5830 hysteresis = <2000>; 5831 type = "passive"; 5832 }; 5833 5834 cpu10_crit: cpu-crit { 5835 temperature = <110000>; 5836 hysteresis = <0>; 5837 type = "critical"; 5838 }; 5839 }; 5840 5841 cooling-maps { 5842 map0 { 5843 trip = <&cpu10_alert0>; 5844 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5845 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5846 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5847 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5848 }; 5849 map1 { 5850 trip = <&cpu10_alert1>; 5851 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5852 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5853 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5854 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5855 }; 5856 }; 5857 }; 5858 5859 cpu11-thermal { 5860 polling-delay-passive = <250>; 5861 polling-delay = <0>; 5862 5863 thermal-sensors = <&tsens0 14>; 5864 5865 trips { 5866 cpu11_alert0: trip-point0 { 5867 temperature = <90000>; 5868 hysteresis = <2000>; 5869 type = "passive"; 5870 }; 5871 5872 cpu11_alert1: trip-point1 { 5873 temperature = <95000>; 5874 hysteresis = <2000>; 5875 type = "passive"; 5876 }; 5877 5878 cpu11_crit: cpu-crit { 5879 temperature = <110000>; 5880 hysteresis = <0>; 5881 type = "critical"; 5882 }; 5883 }; 5884 5885 cooling-maps { 5886 map0 { 5887 trip = <&cpu11_alert0>; 5888 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5889 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5890 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5891 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5892 }; 5893 map1 { 5894 trip = <&cpu11_alert1>; 5895 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5896 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5897 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5898 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5899 }; 5900 }; 5901 }; 5902 5903 aoss0-thermal { 5904 polling-delay-passive = <0>; 5905 polling-delay = <0>; 5906 5907 thermal-sensors = <&tsens0 0>; 5908 5909 trips { 5910 aoss0_alert0: trip-point0 { 5911 temperature = <90000>; 5912 hysteresis = <2000>; 5913 type = "hot"; 5914 }; 5915 5916 aoss0_crit: aoss0-crit { 5917 temperature = <110000>; 5918 hysteresis = <0>; 5919 type = "critical"; 5920 }; 5921 }; 5922 }; 5923 5924 aoss1-thermal { 5925 polling-delay-passive = <0>; 5926 polling-delay = <0>; 5927 5928 thermal-sensors = <&tsens1 0>; 5929 5930 trips { 5931 aoss1_alert0: trip-point0 { 5932 temperature = <90000>; 5933 hysteresis = <2000>; 5934 type = "hot"; 5935 }; 5936 5937 aoss1_crit: aoss1-crit { 5938 temperature = <110000>; 5939 hysteresis = <0>; 5940 type = "critical"; 5941 }; 5942 }; 5943 }; 5944 5945 cpuss0-thermal { 5946 polling-delay-passive = <0>; 5947 polling-delay = <0>; 5948 5949 thermal-sensors = <&tsens0 5>; 5950 5951 trips { 5952 cpuss0_alert0: trip-point0 { 5953 temperature = <90000>; 5954 hysteresis = <2000>; 5955 type = "hot"; 5956 }; 5957 cpuss0_crit: cluster0-crit { 5958 temperature = <110000>; 5959 hysteresis = <0>; 5960 type = "critical"; 5961 }; 5962 }; 5963 }; 5964 5965 cpuss1-thermal { 5966 polling-delay-passive = <0>; 5967 polling-delay = <0>; 5968 5969 thermal-sensors = <&tsens0 6>; 5970 5971 trips { 5972 cpuss1_alert0: trip-point0 { 5973 temperature = <90000>; 5974 hysteresis = <2000>; 5975 type = "hot"; 5976 }; 5977 cpuss1_crit: cluster0-crit { 5978 temperature = <110000>; 5979 hysteresis = <0>; 5980 type = "critical"; 5981 }; 5982 }; 5983 }; 5984 5985 gpuss0-thermal { 5986 polling-delay-passive = <100>; 5987 polling-delay = <0>; 5988 5989 thermal-sensors = <&tsens1 1>; 5990 5991 trips { 5992 gpuss0_alert0: trip-point0 { 5993 temperature = <95000>; 5994 hysteresis = <2000>; 5995 type = "passive"; 5996 }; 5997 5998 gpuss0_crit: gpuss0-crit { 5999 temperature = <110000>; 6000 hysteresis = <0>; 6001 type = "critical"; 6002 }; 6003 }; 6004 6005 cooling-maps { 6006 map0 { 6007 trip = <&gpuss0_alert0>; 6008 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6009 }; 6010 }; 6011 }; 6012 6013 gpuss1-thermal { 6014 polling-delay-passive = <100>; 6015 polling-delay = <0>; 6016 6017 thermal-sensors = <&tsens1 2>; 6018 6019 trips { 6020 gpuss1_alert0: trip-point0 { 6021 temperature = <95000>; 6022 hysteresis = <2000>; 6023 type = "passive"; 6024 }; 6025 6026 gpuss1_crit: gpuss1-crit { 6027 temperature = <110000>; 6028 hysteresis = <0>; 6029 type = "critical"; 6030 }; 6031 }; 6032 6033 cooling-maps { 6034 map0 { 6035 trip = <&gpuss1_alert0>; 6036 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6037 }; 6038 }; 6039 }; 6040 6041 nspss0-thermal { 6042 polling-delay-passive = <0>; 6043 polling-delay = <0>; 6044 6045 thermal-sensors = <&tsens1 3>; 6046 6047 trips { 6048 nspss0_alert0: trip-point0 { 6049 temperature = <90000>; 6050 hysteresis = <2000>; 6051 type = "hot"; 6052 }; 6053 6054 nspss0_crit: nspss0-crit { 6055 temperature = <110000>; 6056 hysteresis = <0>; 6057 type = "critical"; 6058 }; 6059 }; 6060 }; 6061 6062 nspss1-thermal { 6063 polling-delay-passive = <0>; 6064 polling-delay = <0>; 6065 6066 thermal-sensors = <&tsens1 4>; 6067 6068 trips { 6069 nspss1_alert0: trip-point0 { 6070 temperature = <90000>; 6071 hysteresis = <2000>; 6072 type = "hot"; 6073 }; 6074 6075 nspss1_crit: nspss1-crit { 6076 temperature = <110000>; 6077 hysteresis = <0>; 6078 type = "critical"; 6079 }; 6080 }; 6081 }; 6082 6083 video-thermal { 6084 polling-delay-passive = <0>; 6085 polling-delay = <0>; 6086 6087 thermal-sensors = <&tsens1 5>; 6088 6089 trips { 6090 video_alert0: trip-point0 { 6091 temperature = <90000>; 6092 hysteresis = <2000>; 6093 type = "hot"; 6094 }; 6095 6096 video_crit: video-crit { 6097 temperature = <110000>; 6098 hysteresis = <0>; 6099 type = "critical"; 6100 }; 6101 }; 6102 }; 6103 6104 ddr-thermal { 6105 polling-delay-passive = <0>; 6106 polling-delay = <0>; 6107 6108 thermal-sensors = <&tsens1 6>; 6109 6110 trips { 6111 ddr_alert0: trip-point0 { 6112 temperature = <90000>; 6113 hysteresis = <2000>; 6114 type = "hot"; 6115 }; 6116 6117 ddr_crit: ddr-crit { 6118 temperature = <110000>; 6119 hysteresis = <0>; 6120 type = "critical"; 6121 }; 6122 }; 6123 }; 6124 6125 mdmss0-thermal { 6126 polling-delay-passive = <0>; 6127 polling-delay = <0>; 6128 6129 thermal-sensors = <&tsens1 7>; 6130 6131 trips { 6132 mdmss0_alert0: trip-point0 { 6133 temperature = <90000>; 6134 hysteresis = <2000>; 6135 type = "hot"; 6136 }; 6137 6138 mdmss0_crit: mdmss0-crit { 6139 temperature = <110000>; 6140 hysteresis = <0>; 6141 type = "critical"; 6142 }; 6143 }; 6144 }; 6145 6146 mdmss1-thermal { 6147 polling-delay-passive = <0>; 6148 polling-delay = <0>; 6149 6150 thermal-sensors = <&tsens1 8>; 6151 6152 trips { 6153 mdmss1_alert0: trip-point0 { 6154 temperature = <90000>; 6155 hysteresis = <2000>; 6156 type = "hot"; 6157 }; 6158 6159 mdmss1_crit: mdmss1-crit { 6160 temperature = <110000>; 6161 hysteresis = <0>; 6162 type = "critical"; 6163 }; 6164 }; 6165 }; 6166 6167 mdmss2-thermal { 6168 polling-delay-passive = <0>; 6169 polling-delay = <0>; 6170 6171 thermal-sensors = <&tsens1 9>; 6172 6173 trips { 6174 mdmss2_alert0: trip-point0 { 6175 temperature = <90000>; 6176 hysteresis = <2000>; 6177 type = "hot"; 6178 }; 6179 6180 mdmss2_crit: mdmss2-crit { 6181 temperature = <110000>; 6182 hysteresis = <0>; 6183 type = "critical"; 6184 }; 6185 }; 6186 }; 6187 6188 mdmss3-thermal { 6189 polling-delay-passive = <0>; 6190 polling-delay = <0>; 6191 6192 thermal-sensors = <&tsens1 10>; 6193 6194 trips { 6195 mdmss3_alert0: trip-point0 { 6196 temperature = <90000>; 6197 hysteresis = <2000>; 6198 type = "hot"; 6199 }; 6200 6201 mdmss3_crit: mdmss3-crit { 6202 temperature = <110000>; 6203 hysteresis = <0>; 6204 type = "critical"; 6205 }; 6206 }; 6207 }; 6208 6209 camera0-thermal { 6210 polling-delay-passive = <0>; 6211 polling-delay = <0>; 6212 6213 thermal-sensors = <&tsens1 11>; 6214 6215 trips { 6216 camera0_alert0: trip-point0 { 6217 temperature = <90000>; 6218 hysteresis = <2000>; 6219 type = "hot"; 6220 }; 6221 6222 camera0_crit: camera0-crit { 6223 temperature = <110000>; 6224 hysteresis = <0>; 6225 type = "critical"; 6226 }; 6227 }; 6228 }; 6229 }; 6230 6231 timer { 6232 compatible = "arm,armv8-timer"; 6233 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 6234 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 6235 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 6236 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 6237 }; 6238}; 6239