1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * sc7280 Qcard device tree source 4 * 5 * Qcard PCB has the processor, RAM, eMMC (if stuffed), and eDP connector (if 6 * stuffed) on it. This device tree tries to encapsulate all the things that 7 * all boards using Qcard will have in common. Given that there are stuffing 8 * options, some things may be left with status "disabled" and enabled in 9 * the actual board device tree files. 10 * 11 * Copyright 2022 Google LLC. 12 */ 13 14#include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h> 15#include <dt-bindings/iio/qcom,spmi-adc7-pmr735a.h> 16#include <dt-bindings/pinctrl/qcom,pmic-gpio.h> 17#include <dt-bindings/regulator/qcom,rpmh-regulator.h> 18 19#include "sc7280.dtsi" 20 21/* PMICs depend on spmi_bus label and so must come after SoC */ 22#include "pm7325.dtsi" 23#include "pm8350c.dtsi" 24#include "pmk8350.dtsi" 25 26/ { 27 aliases { 28 bluetooth0 = &bluetooth; 29 serial0 = &uart5; 30 serial1 = &uart7; 31 wifi0 = &wifi; 32 }; 33 34 wcd9385: audio-codec-1 { 35 compatible = "qcom,wcd9385-codec"; 36 pinctrl-names = "default", "sleep"; 37 pinctrl-0 = <&wcd_reset_n>, <&us_euro_hs_sel>; 38 pinctrl-1 = <&wcd_reset_n_sleep>, <&us_euro_hs_sel>; 39 40 reset-gpios = <&tlmm 83 GPIO_ACTIVE_LOW>; 41 us-euro-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>; 42 43 qcom,rx-device = <&wcd_rx>; 44 qcom,tx-device = <&wcd_tx>; 45 46 vdd-rxtx-supply = <&vreg_l18b_1p8>; 47 vdd-io-supply = <&vreg_l18b_1p8>; 48 vdd-buck-supply = <&vreg_l17b_1p8>; 49 vdd-mic-bias-supply = <&vreg_bob>; 50 51 qcom,micbias1-microvolt = <1800000>; 52 qcom,micbias2-microvolt = <1800000>; 53 qcom,micbias3-microvolt = <1800000>; 54 qcom,micbias4-microvolt = <1800000>; 55 56 qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 57 500000 500000 500000>; 58 qcom,mbhc-headset-vthreshold-microvolt = <1700000>; 59 qcom,mbhc-headphone-vthreshold-microvolt = <50000>; 60 #sound-dai-cells = <1>; 61 62 status = "disabled"; 63 }; 64 65 pm8350c_pwm_backlight: backlight { 66 compatible = "pwm-backlight"; 67 status = "disabled"; 68 69 enable-gpios = <&pm8350c_gpios 7 GPIO_ACTIVE_HIGH>; 70 pinctrl-names = "default"; 71 pinctrl-0 = <&pmic_edp_bl_en>; 72 pwms = <&pm8350c_pwm 3 65535>; 73 }; 74}; 75 76&apps_rsc { 77 /* 78 * Regulators are given labels corresponding to the various names 79 * they are referred to on schematics. They are also given labels 80 * corresponding to named voltage inputs on the SoC or components 81 * bundled with the SoC (like radio companion chips). We totally 82 * ignore it when one regulator is the input to another regulator. 83 * That's handled automatically by the initial config given to 84 * RPMH by the firmware. 85 * 86 * Regulators that the HLOS (High Level OS) doesn't touch at all 87 * are left out of here since they are managed elsewhere. 88 */ 89 90 regulators-0 { 91 compatible = "qcom,pm7325-rpmh-regulators"; 92 qcom,pmic-id = "b"; 93 94 vdd19_pmu_pcie_i: 95 vdd19_pmu_rfa_i: 96 vreg_s1b_1p856: smps1 { 97 regulator-min-microvolt = <1856000>; 98 regulator-max-microvolt = <2040000>; 99 }; 100 101 vdd_pmu_aon_i: 102 vdd09_pmu_rfa_i: 103 vdd095_mx_pmu: 104 vdd095_pmu: 105 vreg_s7b_0p952: smps7 { 106 regulator-min-microvolt = <535000>; 107 regulator-max-microvolt = <1120000>; 108 }; 109 110 vdd13_pmu_rfa_i: 111 vdd13_pmu_pcie_i: 112 vreg_s8b_1p256: smps8 { 113 regulator-min-microvolt = <1256000>; 114 regulator-max-microvolt = <1500000>; 115 }; 116 117 vdd_a_usbssdp_0_core: 118 vreg_l1b_0p912: ldo1 { 119 regulator-min-microvolt = <825000>; 120 regulator-max-microvolt = <925000>; 121 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 122 }; 123 124 vdd_a_usbhs_3p1: 125 vreg_l2b_3p072: ldo2 { 126 regulator-min-microvolt = <2700000>; 127 regulator-max-microvolt = <3544000>; 128 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 129 }; 130 131 vdd_a_csi_0_1_1p2: 132 vdd_a_csi_2_3_1p2: 133 vdd_a_csi_4_1p2: 134 vdd_a_dsi_0_1p2: 135 vdd_a_edp_0_1p2: 136 vdd_a_qlink_0_1p2: 137 vdd_a_qlink_1_1p2: 138 vdd_a_pcie_0_1p2: 139 vdd_a_pcie_1_1p2: 140 vdd_a_ufs_0_1p2: 141 vdd_a_usbssdp_0_1p2: 142 vreg_l6b_1p2: ldo6 { 143 regulator-min-microvolt = <1140000>; 144 regulator-max-microvolt = <1260000>; 145 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 146 }; 147 148 /* 149 * Despite the fact that this is named to be 2.5V on the 150 * schematic, it powers eMMC which doesn't accept 2.5V 151 */ 152 vreg_l7b_2p5: ldo7 { 153 regulator-min-microvolt = <2960000>; 154 regulator-max-microvolt = <2960000>; 155 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 156 }; 157 158 vreg_l17b_1p8: ldo17 { 159 regulator-min-microvolt = <1700000>; 160 regulator-max-microvolt = <1900000>; 161 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 162 }; 163 164 vdd_px_wcd9385: 165 vdd_txrx: 166 vddpx_0: 167 vddpx_3: 168 vddpx_7: 169 vreg_l18b_1p8: ldo18 { 170 regulator-min-microvolt = <1800000>; 171 regulator-max-microvolt = <2000000>; 172 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 173 }; 174 175 vdd_1p8: 176 vdd_px_sdr735: 177 vdd_pxm: 178 vdd18_io: 179 vddio_px_1: 180 vddio_px_2: 181 vddio_px_3: 182 vddpx_ts: 183 vddpx_wl4otp: 184 vreg_l19b_1p8: ldo19 { 185 regulator-min-microvolt = <1800000>; 186 regulator-max-microvolt = <1800000>; 187 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 188 }; 189 }; 190 191 regulators-1 { 192 compatible = "qcom,pm8350c-rpmh-regulators"; 193 qcom,pmic-id = "c"; 194 195 vdd22_wlbtpa_ch0: 196 vdd22_wlbtpa_ch1: 197 vdd22_wlbtppa_ch0: 198 vdd22_wlbtppa_ch1: 199 vdd22_wlpa5g_ch0: 200 vdd22_wlpa5g_ch1: 201 vdd22_wlppa5g_ch0: 202 vdd22_wlppa5g_ch1: 203 vreg_s1c_2p2: smps1 { 204 regulator-min-microvolt = <2190000>; 205 regulator-max-microvolt = <2210000>; 206 }; 207 208 lp4_vdd2_1p052: 209 vreg_s9c_0p676: smps9 { 210 regulator-min-microvolt = <1010000>; 211 regulator-max-microvolt = <1170000>; 212 }; 213 214 vdda_apc_cs_1p8: 215 vdda_gfx_cs_1p8: 216 vdda_turing_q6_cs_1p8: 217 vdd_a_cxo_1p8: 218 vdd_a_qrefs_1p8: 219 vdd_a_usbhs_1p8: 220 vdd_qfprom: 221 vreg_l1c_1p8: ldo1 { 222 regulator-min-microvolt = <1800000>; 223 regulator-max-microvolt = <1980000>; 224 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 225 }; 226 227 vreg_l2c_1p8: ldo2 { 228 regulator-min-microvolt = <1620000>; 229 regulator-max-microvolt = <1980000>; 230 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 231 }; 232 233 /* 234 * The initial design of this regulator was to use it as 3.3V, 235 * but due to later changes in design it was changed to 1.8V. 236 * The original name is kept due to same schematic. 237 */ 238 ts_avccio: 239 vreg_l3c_3p0: ldo3 { 240 regulator-min-microvolt = <1800000>; 241 regulator-max-microvolt = <1800000>; 242 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 243 }; 244 245 vddpx_5: 246 vreg_l4c_1p8_3p0: ldo4 { 247 regulator-min-microvolt = <1620000>; 248 regulator-max-microvolt = <3300000>; 249 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 250 }; 251 252 vddpx_6: 253 vreg_l5c_1p8_3p0: ldo5 { 254 regulator-min-microvolt = <1620000>; 255 regulator-max-microvolt = <3300000>; 256 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 257 }; 258 259 vddpx_2: 260 vreg_l6c_2p96: ldo6 { 261 regulator-min-microvolt = <1800000>; 262 regulator-max-microvolt = <2950000>; 263 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 264 }; 265 266 vreg_l7c_3p0: ldo7 { 267 regulator-min-microvolt = <3000000>; 268 regulator-max-microvolt = <3544000>; 269 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 270 }; 271 272 vreg_l8c_1p8: ldo8 { 273 regulator-min-microvolt = <1620000>; 274 regulator-max-microvolt = <2000000>; 275 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 276 }; 277 278 vreg_l9c_2p96: ldo9 { 279 regulator-min-microvolt = <2960000>; 280 regulator-max-microvolt = <2960000>; 281 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 282 }; 283 284 vdd_a_csi_0_1_0p9: 285 vdd_a_csi_2_3_0p9: 286 vdd_a_csi_4_0p9: 287 vdd_a_dsi_0_0p9: 288 vdd_a_dsi_0_pll_0p9: 289 vdd_a_edp_0_0p9: 290 vdd_a_gnss_0p9: 291 vdd_a_pcie_0_core: 292 vdd_a_pcie_1_core: 293 vdd_a_qlink_0_0p9: 294 vdd_a_qlink_0_0p9_ck: 295 vdd_a_qlink_1_0p9: 296 vdd_a_qlink_1_0p9_ck: 297 vdd_a_qrefs_0p875_0: 298 vdd_a_qrefs_0p875_1: 299 vdd_a_qrefs_0p875_2: 300 vdd_a_qrefs_0p875_3: 301 vdd_a_qrefs_0p875_4_5: 302 vdd_a_qrefs_0p875_6: 303 vdd_a_qrefs_0p875_7: 304 vdd_a_qrefs_0p875_8: 305 vdd_a_qrefs_0p875_9: 306 vdd_a_ufs_0_core: 307 vdd_a_usbhs_core: 308 vreg_l10c_0p88: ldo10 { 309 regulator-min-microvolt = <720000>; 310 regulator-max-microvolt = <1050000>; 311 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 312 }; 313 314 vreg_l11c_2p8: ldo11 { 315 regulator-min-microvolt = <2800000>; 316 regulator-max-microvolt = <3544000>; 317 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 318 }; 319 320 vreg_l12c_1p8: ldo12 { 321 regulator-min-microvolt = <1650000>; 322 regulator-max-microvolt = <2000000>; 323 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 324 }; 325 326 vreg_l13c_3p0: ldo13 { 327 regulator-min-microvolt = <2700000>; 328 regulator-max-microvolt = <3544000>; 329 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 330 }; 331 332 vdd_flash: 333 vdd_iris_rgb: 334 vdd_mic_bias: 335 vreg_bob: bob { 336 regulator-min-microvolt = <3008000>; 337 regulator-max-microvolt = <3960000>; 338 regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>; 339 }; 340 }; 341}; 342 343/* ADDITIONS TO NODES DEFINED IN PARENT DEVICE TREE FILES */ 344 345&lpass_va_macro { 346 vdd-micb-supply = <&vreg_bob>; 347}; 348 349/* NOTE: Not all Qcards have eDP connector stuffed */ 350&mdss_edp { 351 aux-bus { 352 edp_panel: panel { 353 compatible = "edp-panel"; 354 355 backlight = <&pm8350c_pwm_backlight>; 356 357 port { 358 edp_panel_in: endpoint { 359 remote-endpoint = <&mdss_edp_out>; 360 }; 361 }; 362 }; 363 }; 364}; 365 366&mdss_edp_out { 367 remote-endpoint = <&edp_panel_in>; 368}; 369 370&mdss_edp_phy { 371 vdda-pll-supply = <&vdd_a_edp_0_0p9>; 372 vdda-phy-supply = <&vdd_a_edp_0_1p2>; 373}; 374 375&pcie1_phy { 376 vdda-phy-supply = <&vreg_l10c_0p88>; 377 vdda-pll-supply = <&vreg_l6b_1p2>; 378}; 379 380&pm8350c_pwm { 381 pinctrl-names = "default"; 382 pinctrl-0 = <&pmic_edp_bl_pwm>; 383}; 384 385&pmk8350_vadc { 386 pmk8350-die-temp@3 { 387 reg = <PMK8350_ADC7_DIE_TEMP>; 388 label = "pmk8350_die_temp"; 389 qcom,pre-scaling = <1 1>; 390 }; 391 392 pmr735a-die-temp@403 { 393 reg = <PMR735A_ADC7_DIE_TEMP>; 394 label = "pmr735a_die_temp"; 395 qcom,pre-scaling = <1 1>; 396 }; 397}; 398 399&qfprom { 400 vcc-supply = <&vdd_qfprom>; 401}; 402 403/* For eMMC. NOTE: not all Qcards have eMMC stuffed */ 404&sdhc_1 { 405 vmmc-supply = <&vreg_l7b_2p5>; 406 vqmmc-supply = <&vreg_l19b_1p8>; 407 408 non-removable; 409 no-sd; 410 no-sdio; 411}; 412 413&swr0 { 414 wcd_rx: codec@0,4 { 415 compatible = "sdw20217010d00"; 416 reg = <0 4>; 417 #sound-dai-cells = <1>; 418 qcom,rx-port-mapping = <1 2 3 4 5>; 419 }; 420}; 421 422&swr1 { 423 wcd_tx: codec@0,3 { 424 compatible = "sdw20217010d00"; 425 reg = <0 3>; 426 #sound-dai-cells = <1>; 427 qcom,tx-port-mapping = <1 2 3 4>; 428 }; 429}; 430 431uart_dbg: &uart5 { 432 compatible = "qcom,geni-debug-uart"; 433 status = "okay"; 434}; 435 436mos_bt_uart: &uart7 { 437 status = "okay"; 438 439 /delete-property/ interrupts; 440 interrupts-extended = <&intc GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>, 441 <&tlmm 31 IRQ_TYPE_EDGE_FALLING>; 442 pinctrl-names = "default", "sleep"; 443 pinctrl-1 = <&qup_uart7_sleep_cts>, <&qup_uart7_sleep_rts>, <&qup_uart7_sleep_tx>, <&qup_uart7_sleep_rx>; 444 445 bluetooth: bluetooth { 446 compatible = "qcom,wcn6750-bt"; 447 pinctrl-names = "default"; 448 pinctrl-0 = <&mos_bt_en>; 449 enable-gpios = <&tlmm 85 GPIO_ACTIVE_HIGH>; 450 swctrl-gpios = <&tlmm 86 GPIO_ACTIVE_HIGH>; 451 vddaon-supply = <&vreg_s7b_0p952>; 452 vddbtcxmx-supply = <&vreg_s7b_0p952>; 453 vddrfacmn-supply = <&vreg_s7b_0p952>; 454 vddrfa0p8-supply = <&vreg_s7b_0p952>; 455 vddrfa1p7-supply = <&vdd19_pmu_rfa_i>; 456 vddrfa1p2-supply = <&vdd13_pmu_rfa_i>; 457 vddrfa2p2-supply = <&vreg_s1c_2p2>; 458 vddasd-supply = <&vreg_l11c_2p8>; 459 vddio-supply = <&vreg_l18b_1p8>; 460 max-speed = <3200000>; 461 }; 462}; 463 464&usb_1_hsphy { 465 vdda-pll-supply = <&vdd_a_usbhs_core>; 466 vdda33-supply = <&vdd_a_usbhs_3p1>; 467 vdda18-supply = <&vdd_a_usbhs_1p8>; 468}; 469 470&usb_1_qmpphy { 471 vdda-phy-supply = <&vdd_a_usbssdp_0_1p2>; 472 vdda-pll-supply = <&vdd_a_usbssdp_0_core>; 473}; 474 475&usb_2_hsphy { 476 vdda-pll-supply = <&vdd_a_usbhs_core>; 477 vdda33-supply = <&vdd_a_usbhs_3p1>; 478 vdda18-supply = <&vdd_a_usbhs_1p8>; 479}; 480 481/* 482 * PINCTRL - ADDITIONS TO NODES IN PARENT DEVICE TREE FILES 483 * 484 * NOTE: In general if pins leave the Qcard then the pinctrl goes in the 485 * baseboard or board device tree, not here. 486 */ 487 488/* No external pull for eDP HPD, so set the internal one. */ 489&edp_hot_plug_det { 490 bias-pull-down; 491}; 492 493/* 494 * For ts_i2c 495 * 496 * Technically this i2c bus actually leaves the Qcard, but it leaves directly 497 * via the eDP connector (it doesn't hit the baseboard). The external pulls 498 * are on Qcard. 499 */ 500&qup_i2c13_data_clk { 501 /* Has external pull */ 502 bias-disable; 503 drive-strength = <2>; 504}; 505 506/* For mos_bt_uart */ 507&qup_uart7_cts { 508 /* 509 * Configure a bias-bus-hold on CTS to lower power 510 * usage when Bluetooth is turned off. Bus hold will 511 * maintain a low power state regardless of whether 512 * the Bluetooth module drives the pin in either 513 * direction or leaves the pin fully unpowered. 514 */ 515 bias-bus-hold; 516}; 517 518/* For mos_bt_uart */ 519&qup_uart7_rts { 520 /* We'll drive RTS, so no pull */ 521 bias-disable; 522 drive-strength = <2>; 523}; 524 525/* For mos_bt_uart */ 526&qup_uart7_tx { 527 /* We'll drive TX, so no pull */ 528 bias-disable; 529 drive-strength = <2>; 530}; 531 532/* For mos_bt_uart */ 533&qup_uart7_rx { 534 /* 535 * Configure a pull-up on RX. This is needed to avoid 536 * garbage data when the TX pin of the Bluetooth module is 537 * in tri-state (module powered off or not driving the 538 * signal yet). 539 */ 540 bias-pull-up; 541}; 542 543/* eMMC, if stuffed, is straight on the Qcard */ 544&sdc1_clk { 545 bias-disable; 546 drive-strength = <16>; 547}; 548 549&sdc1_cmd { 550 bias-pull-up; 551 drive-strength = <10>; 552}; 553 554&sdc1_data { 555 bias-pull-up; 556 drive-strength = <10>; 557}; 558 559&sdc1_rclk { 560 bias-pull-down; 561}; 562 563/* 564 * PINCTRL - QCARD 565 * 566 * This has entries that are defined by Qcard even if they go to the main 567 * board. In cases where the pulls may be board dependent we defer those 568 * settings to the board device tree. Drive strengths tend to be assinged here 569 * but could conceivably be overwridden by board device trees. 570 */ 571 572&pm8350c_gpios { 573 pmic_edp_bl_en: pmic-edp-bl-en-state { 574 pins = "gpio7"; 575 function = "normal"; 576 bias-disable; 577 qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>; 578 579 /* Force backlight to be disabled to match state at boot. */ 580 output-low; 581 }; 582 583 pmic_edp_bl_pwm: pmic-edp-bl-pwm-state { 584 pins = "gpio8"; 585 function = "func1"; 586 bias-disable; 587 qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>; 588 output-low; 589 power-source = <0>; 590 }; 591}; 592 593&tlmm { 594 mos_bt_en: mos-bt-en-state { 595 pins = "gpio85"; 596 function = "gpio"; 597 drive-strength = <2>; 598 output-low; 599 }; 600 601 /* For mos_bt_uart */ 602 qup_uart7_sleep_cts: qup-uart7-sleep-cts-state { 603 pins = "gpio28"; 604 function = "gpio"; 605 /* 606 * Configure a bias-bus-hold on CTS to lower power 607 * usage when Bluetooth is turned off. Bus hold will 608 * maintain a low power state regardless of whether 609 * the Bluetooth module drives the pin in either 610 * direction or leaves the pin fully unpowered. 611 */ 612 bias-bus-hold; 613 }; 614 615 /* For mos_bt_uart */ 616 qup_uart7_sleep_rts: qup-uart7-sleep-rts-state { 617 pins = "gpio29"; 618 function = "gpio"; 619 /* 620 * Configure pull-down on RTS. As RTS is active low 621 * signal, pull it low to indicate the BT SoC that it 622 * can wakeup the system anytime from suspend state by 623 * pulling RX low (by sending wakeup bytes). 624 */ 625 bias-pull-down; 626 }; 627 628 /* For mos_bt_uart */ 629 qup_uart7_sleep_rx: qup-uart7-sleep-rx-state { 630 pins = "gpio31"; 631 function = "gpio"; 632 /* 633 * Configure a pull-up on RX. This is needed to avoid 634 * garbage data when the TX pin of the Bluetooth module 635 * is floating which may cause spurious wakeups. 636 */ 637 bias-pull-up; 638 }; 639 640 /* For mos_bt_uart */ 641 qup_uart7_sleep_tx: qup-uart7-sleep-tx-state { 642 pins = "gpio30"; 643 function = "gpio"; 644 /* 645 * Configure pull-up on TX when it isn't actively driven 646 * to prevent BT SoC from receiving garbage during sleep. 647 */ 648 bias-pull-up; 649 }; 650 651 ts_int_conn: ts-int-conn-state { 652 pins = "gpio55"; 653 function = "gpio"; 654 bias-pull-up; 655 }; 656 657 ts_rst_conn: ts-rst-conn-state { 658 pins = "gpio54"; 659 function = "gpio"; 660 drive-strength = <2>; 661 }; 662 663 us_euro_hs_sel: us-euro-hs-sel-state { 664 pins = "gpio81"; 665 function = "gpio"; 666 bias-pull-down; 667 drive-strength = <2>; 668 }; 669 670 wcd_reset_n: wcd-reset-n-state { 671 pins = "gpio83"; 672 function = "gpio"; 673 drive-strength = <8>; 674 }; 675 676 wcd_reset_n_sleep: wcd-reset-n-sleep-state { 677 pins = "gpio83"; 678 function = "gpio"; 679 drive-strength = <8>; 680 bias-disable; 681 }; 682}; 683