1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * sc7280 Qcard device tree source
4 *
5 * Qcard PCB has the processor, RAM, eMMC (if stuffed), and eDP connector (if
6 * stuffed) on it. This device tree tries to encapsulate all the things that
7 * all boards using Qcard will have in common. Given that there are stuffing
8 * options, some things may be left with status "disabled" and enabled in
9 * the actual board device tree files.
10 *
11 * Copyright 2022 Google LLC.
12 */
13
14#include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h>
15#include <dt-bindings/iio/qcom,spmi-adc7-pmr735a.h>
16#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
17#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
18
19#include "sc7280.dtsi"
20
21/* PMICs depend on spmi_bus label and so must come after SoC */
22#include "pm7325.dtsi"
23#include "pm8350c.dtsi"
24#include "pmk8350.dtsi"
25
26/ {
27	aliases {
28		bluetooth0 = &bluetooth;
29		serial0 = &uart5;
30		serial1 = &uart7;
31		wifi0 = &wifi;
32	};
33
34	wcd9385: audio-codec-1 {
35		compatible = "qcom,wcd9385-codec";
36		pinctrl-names = "default", "sleep";
37		pinctrl-0 = <&wcd_reset_n>, <&us_euro_hs_sel>;
38		pinctrl-1 = <&wcd_reset_n_sleep>, <&us_euro_hs_sel>;
39
40		reset-gpios = <&tlmm 83 GPIO_ACTIVE_LOW>;
41		us-euro-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>;
42
43		qcom,rx-device = <&wcd_rx>;
44		qcom,tx-device = <&wcd_tx>;
45
46		vdd-rxtx-supply = <&vreg_l18b_1p8>;
47		vdd-io-supply = <&vreg_l18b_1p8>;
48		vdd-buck-supply = <&vreg_l17b_1p8>;
49		vdd-mic-bias-supply = <&vreg_bob>;
50
51		qcom,micbias1-microvolt = <1800000>;
52		qcom,micbias2-microvolt = <1800000>;
53		qcom,micbias3-microvolt = <1800000>;
54		qcom,micbias4-microvolt = <1800000>;
55
56		qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000
57							  500000 500000 500000>;
58		qcom,mbhc-headset-vthreshold-microvolt = <1700000>;
59		qcom,mbhc-headphone-vthreshold-microvolt = <50000>;
60		#sound-dai-cells = <1>;
61
62		status = "disabled";
63	};
64
65	pm8350c_pwm_backlight: backlight {
66		compatible = "pwm-backlight";
67		status = "disabled";
68
69		enable-gpios = <&pm8350c_gpios 7 GPIO_ACTIVE_HIGH>;
70		pinctrl-names = "default";
71		pinctrl-0 = <&pmic_edp_bl_en>;
72		pwms = <&pm8350c_pwm 3 65535>;
73	};
74};
75
76&apps_rsc {
77	/*
78	 * Regulators are given labels corresponding to the various names
79	 * they are referred to on schematics. They are also given labels
80	 * corresponding to named voltage inputs on the SoC or components
81	 * bundled with the SoC (like radio companion chips). We totally
82	 * ignore it when one regulator is the input to another regulator.
83	 * That's handled automatically by the initial config given to
84	 * RPMH by the firmware.
85	 *
86	 * Regulators that the HLOS (High Level OS) doesn't touch at all
87	 * are left out of here since they are managed elsewhere.
88	 */
89
90	regulators-0 {
91		compatible = "qcom,pm7325-rpmh-regulators";
92		qcom,pmic-id = "b";
93
94		vdd19_pmu_pcie_i:
95		vdd19_pmu_rfa_i:
96		vreg_s1b_1p856: smps1 {
97			regulator-min-microvolt = <1856000>;
98			regulator-max-microvolt = <2040000>;
99		};
100
101		vdd_pmu_aon_i:
102		vdd09_pmu_rfa_i:
103		vdd095_mx_pmu:
104		vdd095_pmu:
105		vreg_s7b_0p952: smps7 {
106			regulator-min-microvolt = <535000>;
107			regulator-max-microvolt = <1120000>;
108		};
109
110		vdd13_pmu_rfa_i:
111		vdd13_pmu_pcie_i:
112		vreg_s8b_1p256: smps8 {
113			regulator-min-microvolt = <1256000>;
114			regulator-max-microvolt = <1500000>;
115		};
116
117		vdd_a_usbssdp_0_core:
118		vreg_l1b_0p912: ldo1 {
119			regulator-min-microvolt = <825000>;
120			regulator-max-microvolt = <925000>;
121			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
122		};
123
124		vdd_a_usbhs_3p1:
125		vreg_l2b_3p072: ldo2 {
126			regulator-min-microvolt = <2700000>;
127			regulator-max-microvolt = <3544000>;
128			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
129		};
130
131		vdd_a_csi_0_1_1p2:
132		vdd_a_csi_2_3_1p2:
133		vdd_a_csi_4_1p2:
134		vdd_a_dsi_0_1p2:
135		vdd_a_edp_0_1p2:
136		vdd_a_qlink_0_1p2:
137		vdd_a_qlink_1_1p2:
138		vdd_a_pcie_0_1p2:
139		vdd_a_pcie_1_1p2:
140		vdd_a_ufs_0_1p2:
141		vdd_a_usbssdp_0_1p2:
142		vreg_l6b_1p2: ldo6 {
143			regulator-min-microvolt = <1140000>;
144			regulator-max-microvolt = <1260000>;
145			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
146		};
147
148		/*
149		 * Despite the fact that this is named to be 2.5V on the
150		 * schematic, it powers eMMC which doesn't accept 2.5V
151		 */
152		vreg_l7b_2p5: ldo7 {
153			regulator-min-microvolt = <2960000>;
154			regulator-max-microvolt = <2960000>;
155			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
156		};
157
158		vreg_l17b_1p8: ldo17 {
159			regulator-min-microvolt = <1700000>;
160			regulator-max-microvolt = <1900000>;
161			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
162		};
163
164		vdd_px_wcd9385:
165		vdd_txrx:
166		vddpx_0:
167		vddpx_3:
168		vddpx_7:
169		vreg_l18b_1p8: ldo18 {
170			regulator-min-microvolt = <1800000>;
171			regulator-max-microvolt = <2000000>;
172			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
173		};
174
175		vdd_1p8:
176		vdd_px_sdr735:
177		vdd_pxm:
178		vdd18_io:
179		vddio_px_1:
180		vddio_px_2:
181		vddio_px_3:
182		vddpx_ts:
183		vddpx_wl4otp:
184		vreg_l19b_1p8: ldo19 {
185			regulator-min-microvolt = <1800000>;
186			regulator-max-microvolt = <1800000>;
187			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
188		};
189	};
190
191	regulators-1 {
192		compatible = "qcom,pm8350c-rpmh-regulators";
193		qcom,pmic-id = "c";
194
195		vdd22_wlbtpa_ch0:
196		vdd22_wlbtpa_ch1:
197		vdd22_wlbtppa_ch0:
198		vdd22_wlbtppa_ch1:
199		vdd22_wlpa5g_ch0:
200		vdd22_wlpa5g_ch1:
201		vdd22_wlppa5g_ch0:
202		vdd22_wlppa5g_ch1:
203		vreg_s1c_2p2: smps1 {
204			regulator-min-microvolt = <2190000>;
205			regulator-max-microvolt = <2210000>;
206		};
207
208		lp4_vdd2_1p052:
209		vreg_s9c_0p676: smps9 {
210			regulator-min-microvolt = <1010000>;
211			regulator-max-microvolt = <1170000>;
212		};
213
214		vdda_apc_cs_1p8:
215		vdda_gfx_cs_1p8:
216		vdda_turing_q6_cs_1p8:
217		vdd_a_cxo_1p8:
218		vdd_a_qrefs_1p8:
219		vdd_a_usbhs_1p8:
220		vdd_qfprom:
221		vreg_l1c_1p8: ldo1 {
222			regulator-min-microvolt = <1800000>;
223			regulator-max-microvolt = <1980000>;
224			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
225		};
226
227		vreg_l2c_1p8: ldo2 {
228			regulator-min-microvolt = <1620000>;
229			regulator-max-microvolt = <1980000>;
230			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
231		};
232
233		/*
234		 * The initial design of this regulator was to use it as 3.3V,
235		 * but due to later changes in design it was changed to 1.8V.
236		 * The original name is kept due to same schematic.
237		 */
238		ts_avccio:
239		vreg_l3c_3p0: ldo3 {
240			regulator-min-microvolt = <1800000>;
241			regulator-max-microvolt = <1800000>;
242			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
243		};
244
245		vddpx_5:
246		vreg_l4c_1p8_3p0: ldo4 {
247			regulator-min-microvolt = <1620000>;
248			regulator-max-microvolt = <3300000>;
249			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
250		};
251
252		vddpx_6:
253		vreg_l5c_1p8_3p0: ldo5 {
254			regulator-min-microvolt = <1620000>;
255			regulator-max-microvolt = <3300000>;
256			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
257		};
258
259		vddpx_2:
260		vreg_l6c_2p96: ldo6 {
261			regulator-min-microvolt = <1800000>;
262			regulator-max-microvolt = <2950000>;
263			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
264		};
265
266		vreg_l7c_3p0: ldo7 {
267			regulator-min-microvolt = <3000000>;
268			regulator-max-microvolt = <3544000>;
269			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
270		};
271
272		vreg_l8c_1p8: ldo8 {
273			regulator-min-microvolt = <1620000>;
274			regulator-max-microvolt = <2000000>;
275			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
276		};
277
278		vreg_l9c_2p96: ldo9 {
279			regulator-min-microvolt = <2960000>;
280			regulator-max-microvolt = <2960000>;
281			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
282		};
283
284		vdd_a_csi_0_1_0p9:
285		vdd_a_csi_2_3_0p9:
286		vdd_a_csi_4_0p9:
287		vdd_a_dsi_0_0p9:
288		vdd_a_dsi_0_pll_0p9:
289		vdd_a_edp_0_0p9:
290		vdd_a_gnss_0p9:
291		vdd_a_pcie_0_core:
292		vdd_a_pcie_1_core:
293		vdd_a_qlink_0_0p9:
294		vdd_a_qlink_0_0p9_ck:
295		vdd_a_qlink_1_0p9:
296		vdd_a_qlink_1_0p9_ck:
297		vdd_a_qrefs_0p875_0:
298		vdd_a_qrefs_0p875_1:
299		vdd_a_qrefs_0p875_2:
300		vdd_a_qrefs_0p875_3:
301		vdd_a_qrefs_0p875_4_5:
302		vdd_a_qrefs_0p875_6:
303		vdd_a_qrefs_0p875_7:
304		vdd_a_qrefs_0p875_8:
305		vdd_a_qrefs_0p875_9:
306		vdd_a_ufs_0_core:
307		vdd_a_usbhs_core:
308		vreg_l10c_0p88: ldo10 {
309			regulator-min-microvolt = <720000>;
310			regulator-max-microvolt = <1050000>;
311			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
312		};
313
314		vreg_l11c_2p8: ldo11 {
315			regulator-min-microvolt = <2800000>;
316			regulator-max-microvolt = <3544000>;
317			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
318		};
319
320		vreg_l12c_1p8: ldo12 {
321			regulator-min-microvolt = <1650000>;
322			regulator-max-microvolt = <2000000>;
323			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
324		};
325
326		vreg_l13c_3p0: ldo13 {
327			regulator-min-microvolt = <2700000>;
328			regulator-max-microvolt = <3544000>;
329			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
330		};
331
332		vdd_flash:
333		vdd_iris_rgb:
334		vdd_mic_bias:
335		vreg_bob: bob {
336			regulator-min-microvolt = <3008000>;
337			regulator-max-microvolt = <3960000>;
338			regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
339		};
340	};
341};
342
343/* ADDITIONS TO NODES DEFINED IN PARENT DEVICE TREE FILES */
344
345&lpass_va_macro {
346	vdd-micb-supply = <&vreg_bob>;
347};
348
349/* NOTE: Not all Qcards have eDP connector stuffed */
350&mdss_edp {
351	aux-bus {
352		edp_panel: panel {
353			compatible = "edp-panel";
354
355			backlight = <&pm8350c_pwm_backlight>;
356
357			port {
358				edp_panel_in: endpoint {
359					remote-endpoint = <&mdss_edp_out>;
360				};
361			};
362		};
363	};
364};
365
366&mdss_edp_out {
367	remote-endpoint = <&edp_panel_in>;
368};
369
370&mdss_edp_phy {
371	vdda-pll-supply = <&vdd_a_edp_0_0p9>;
372	vdda-phy-supply = <&vdd_a_edp_0_1p2>;
373};
374
375&pcie1_phy {
376	vdda-phy-supply = <&vreg_l10c_0p88>;
377	vdda-pll-supply = <&vreg_l6b_1p2>;
378};
379
380&pm8350c_pwm {
381	pinctrl-names = "default";
382	pinctrl-0 = <&pmic_edp_bl_pwm>;
383};
384
385&pmk8350_vadc {
386	channel@3 {
387		reg = <PMK8350_ADC7_DIE_TEMP>;
388		label = "pmk8350_die_temp";
389		qcom,pre-scaling = <1 1>;
390	};
391
392	channel@403 {
393		reg = <PMR735A_ADC7_DIE_TEMP>;
394		label = "pmr735a_die_temp";
395		qcom,pre-scaling = <1 1>;
396	};
397};
398
399&qfprom {
400	vcc-supply = <&vdd_qfprom>;
401};
402
403/* For eMMC. NOTE: not all Qcards have eMMC stuffed */
404&sdhc_1 {
405	vmmc-supply = <&vreg_l7b_2p5>;
406	vqmmc-supply = <&vreg_l19b_1p8>;
407
408	non-removable;
409	no-sd;
410	no-sdio;
411};
412
413&swr0 {
414	wcd_rx: codec@0,4 {
415		compatible = "sdw20217010d00";
416		reg = <0 4>;
417		qcom,rx-port-mapping = <1 2 3 4 5>;
418	};
419};
420
421&swr1 {
422	wcd_tx: codec@0,3 {
423		compatible = "sdw20217010d00";
424		reg = <0 3>;
425		qcom,tx-port-mapping = <1 2 3 4>;
426	};
427};
428
429uart_dbg: &uart5 {
430	compatible = "qcom,geni-debug-uart";
431	status = "okay";
432};
433
434mos_bt_uart: &uart7 {
435	status = "okay";
436
437	/delete-property/ interrupts;
438	interrupts-extended = <&intc GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>,
439				<&tlmm 31 IRQ_TYPE_EDGE_FALLING>;
440	pinctrl-names = "default", "sleep";
441	pinctrl-1 = <&qup_uart7_sleep_cts>, <&qup_uart7_sleep_rts>, <&qup_uart7_sleep_tx>, <&qup_uart7_sleep_rx>;
442
443	bluetooth: bluetooth {
444		compatible = "qcom,wcn6750-bt";
445		pinctrl-names = "default";
446		pinctrl-0 = <&mos_bt_en>;
447		enable-gpios = <&tlmm 85 GPIO_ACTIVE_HIGH>;
448		swctrl-gpios = <&tlmm 86 GPIO_ACTIVE_HIGH>;
449		vddaon-supply = <&vreg_s7b_0p952>;
450		vddbtcxmx-supply = <&vreg_s7b_0p952>;
451		vddrfacmn-supply = <&vreg_s7b_0p952>;
452		vddrfa0p8-supply = <&vreg_s7b_0p952>;
453		vddrfa1p7-supply = <&vdd19_pmu_rfa_i>;
454		vddrfa1p2-supply = <&vdd13_pmu_rfa_i>;
455		vddrfa2p2-supply = <&vreg_s1c_2p2>;
456		vddasd-supply = <&vreg_l11c_2p8>;
457		vddio-supply = <&vreg_l18b_1p8>;
458		max-speed = <3200000>;
459	};
460};
461
462&usb_1_hsphy {
463	vdda-pll-supply = <&vdd_a_usbhs_core>;
464	vdda33-supply = <&vdd_a_usbhs_3p1>;
465	vdda18-supply = <&vdd_a_usbhs_1p8>;
466};
467
468&usb_1_qmpphy {
469	vdda-phy-supply = <&vdd_a_usbssdp_0_1p2>;
470	vdda-pll-supply = <&vdd_a_usbssdp_0_core>;
471};
472
473&usb_2_hsphy {
474	vdda-pll-supply = <&vdd_a_usbhs_core>;
475	vdda33-supply = <&vdd_a_usbhs_3p1>;
476	vdda18-supply = <&vdd_a_usbhs_1p8>;
477};
478
479/*
480 * PINCTRL - ADDITIONS TO NODES IN PARENT DEVICE TREE FILES
481 *
482 * NOTE: In general if pins leave the Qcard then the pinctrl goes in the
483 * baseboard or board device tree, not here.
484 */
485
486/* No external pull for eDP HPD, so set the internal one. */
487&edp_hot_plug_det {
488	bias-pull-down;
489};
490
491/*
492 * For ts_i2c
493 *
494 * Technically this i2c bus actually leaves the Qcard, but it leaves directly
495 * via the eDP connector (it doesn't hit the baseboard). The external pulls
496 * are on Qcard.
497 */
498&qup_i2c13_data_clk {
499	/* Has external pull */
500	bias-disable;
501	drive-strength = <2>;
502};
503
504/* For mos_bt_uart */
505&qup_uart7_cts {
506	/*
507	 * Configure a bias-bus-hold on CTS to lower power
508	 * usage when Bluetooth is turned off. Bus hold will
509	 * maintain a low power state regardless of whether
510	 * the Bluetooth module drives the pin in either
511	 * direction or leaves the pin fully unpowered.
512	 */
513	bias-bus-hold;
514};
515
516/* For mos_bt_uart */
517&qup_uart7_rts {
518	/* We'll drive RTS, so no pull */
519	bias-disable;
520	drive-strength = <2>;
521};
522
523/* For mos_bt_uart */
524&qup_uart7_tx {
525	/* We'll drive TX, so no pull */
526	bias-disable;
527	drive-strength = <2>;
528};
529
530/* For mos_bt_uart */
531&qup_uart7_rx {
532	/*
533	 * Configure a pull-up on RX. This is needed to avoid
534	 * garbage data when the TX pin of the Bluetooth module is
535	 * in tri-state (module powered off or not driving the
536	 * signal yet).
537	 */
538	bias-pull-up;
539};
540
541/* eMMC, if stuffed, is straight on the Qcard */
542&sdc1_clk {
543	bias-disable;
544	drive-strength = <16>;
545};
546
547&sdc1_cmd {
548	bias-pull-up;
549	drive-strength = <10>;
550};
551
552&sdc1_data {
553	bias-pull-up;
554	drive-strength = <10>;
555};
556
557&sdc1_rclk {
558	bias-pull-down;
559};
560
561/*
562 * PINCTRL - QCARD
563 *
564 * This has entries that are defined by Qcard even if they go to the main
565 * board. In cases where the pulls may be board dependent we defer those
566 * settings to the board device tree. Drive strengths tend to be assinged here
567 * but could conceivably be overwridden by board device trees.
568 */
569
570&pm8350c_gpios {
571	pmic_edp_bl_en: pmic-edp-bl-en-state {
572		pins = "gpio7";
573		function = "normal";
574		bias-disable;
575		qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>;
576
577		/* Force backlight to be disabled to match state at boot. */
578		output-low;
579	};
580
581	pmic_edp_bl_pwm: pmic-edp-bl-pwm-state {
582		pins = "gpio8";
583		function = "func1";
584		bias-disable;
585		qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>;
586		output-low;
587		power-source = <0>;
588	};
589};
590
591&tlmm {
592	mos_bt_en: mos-bt-en-state {
593		pins = "gpio85";
594		function = "gpio";
595		drive-strength = <2>;
596		output-low;
597	};
598
599	/* For mos_bt_uart */
600	qup_uart7_sleep_cts: qup-uart7-sleep-cts-state {
601		pins = "gpio28";
602		function = "gpio";
603		/*
604		 * Configure a bias-bus-hold on CTS to lower power
605		 * usage when Bluetooth is turned off. Bus hold will
606		 * maintain a low power state regardless of whether
607		 * the Bluetooth module drives the pin in either
608		 * direction or leaves the pin fully unpowered.
609		 */
610		bias-bus-hold;
611	};
612
613	/* For mos_bt_uart */
614	qup_uart7_sleep_rts: qup-uart7-sleep-rts-state {
615		pins = "gpio29";
616		function = "gpio";
617		/*
618		 * Configure pull-down on RTS. As RTS is active low
619		 * signal, pull it low to indicate the BT SoC that it
620		 * can wakeup the system anytime from suspend state by
621		 * pulling RX low (by sending wakeup bytes).
622		 */
623		bias-pull-down;
624	};
625
626	/* For mos_bt_uart */
627	qup_uart7_sleep_rx: qup-uart7-sleep-rx-state {
628		pins = "gpio31";
629		function = "gpio";
630		/*
631		 * Configure a pull-up on RX. This is needed to avoid
632		 * garbage data when the TX pin of the Bluetooth module
633		 * is floating which may cause spurious wakeups.
634		 */
635		bias-pull-up;
636	};
637
638	/* For mos_bt_uart */
639	qup_uart7_sleep_tx: qup-uart7-sleep-tx-state {
640		pins = "gpio30";
641		function = "gpio";
642		/*
643		 * Configure pull-up on TX when it isn't actively driven
644		 * to prevent BT SoC from receiving garbage during sleep.
645		 */
646		bias-pull-up;
647	};
648
649	ts_int_conn: ts-int-conn-state {
650		pins = "gpio55";
651		function = "gpio";
652		bias-pull-up;
653	};
654
655	ts_rst_conn: ts-rst-conn-state {
656		pins = "gpio54";
657		function = "gpio";
658		drive-strength = <2>;
659	};
660
661	us_euro_hs_sel: us-euro-hs-sel-state {
662		pins = "gpio81";
663		function = "gpio";
664		bias-pull-down;
665		drive-strength = <2>;
666	};
667
668	wcd_reset_n: wcd-reset-n-state {
669		pins = "gpio83";
670		function = "gpio";
671		drive-strength = <8>;
672	};
673
674	wcd_reset_n_sleep: wcd-reset-n-sleep-state {
675		pins = "gpio83";
676		function = "gpio";
677		drive-strength = <8>;
678		bias-disable;
679	};
680};
681