1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Google Herobrine board device tree source
4 *
5 * Copyright 2022 Google LLC.
6 */
7
8/dts-v1/;
9
10#include "sc7280-herobrine.dtsi"
11
12/ {
13	model = "Google Herobrine (rev1+)";
14	compatible = "google,herobrine", "qcom,sc7280";
15};
16
17/*
18 * ADDITIONS TO FIXED REGULATORS DEFINED IN PARENT DEVICE TREE FILES
19 *
20 * Sort order matches the order in the parent files (parents before children).
21 */
22
23&pp3300_codec {
24	status = "okay";
25};
26
27&pp3300_fp_mcu {
28	status = "okay";
29};
30
31&pp2850_vcm_wf_cam {
32	status = "okay";
33};
34
35&pp2850_wf_cam {
36	status = "okay";
37};
38
39&pp1800_wf_cam {
40	status = "okay";
41};
42
43&pp1200_wf_cam {
44	status = "okay";
45};
46
47/* ADDITIONS TO NODES DEFINED IN PARENT DEVICE TREE FILES */
48
49&ap_spi_fp {
50	status = "okay";
51};
52
53/*
54 * Although the trackpad is really part of the herobrine baseboard, we'll
55 * put the actual definition in the board device tree since different boards
56 * might hook up different trackpads (or no i2c trackpad at all in the case
57 * of tablets / detachables).
58 */
59ap_tp_i2c: &i2c0 {
60	status = "okay";
61	clock-frequency = <400000>;
62
63	trackpad: trackpad@15 {
64		compatible = "elan,ekth3000";
65		reg = <0x15>;
66		pinctrl-names = "default";
67		pinctrl-0 = <&tp_int_odl>;
68
69		interrupt-parent = <&tlmm>;
70		interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
71
72		vcc-supply = <&pp3300_z1>;
73
74		wakeup-source;
75	};
76};
77
78/*
79 * The touchscreen connector might come off the Qcard, at least in the case of
80 * eDP. Like the trackpad, we'll put it in the board device tree file since
81 * different boards have different touchscreens.
82 */
83ts_i2c: &i2c13 {
84	status = "okay";
85	clock-frequency = <400000>;
86
87	ap_ts: touchscreen@5c {
88		compatible = "hid-over-i2c";
89		reg = <0x5c>;
90		pinctrl-names = "default";
91		pinctrl-0 = <&ts_int_conn>, <&ts_rst_conn>;
92
93		interrupt-parent = <&tlmm>;
94		interrupts = <55 IRQ_TYPE_LEVEL_LOW>;
95
96		post-power-on-delay-ms = <500>;
97		hid-descr-addr = <0x0000>;
98
99		vdd-supply = <&ts_avdd>;
100	};
101};
102
103&mdss_edp {
104	status = "okay";
105};
106
107&mdss_edp_phy {
108	status = "okay";
109};
110
111/* For nvme */
112&pcie1 {
113	status = "okay";
114};
115
116/* For nvme */
117&pcie1_phy {
118	status = "okay";
119};
120
121/* For eMMC */
122&sdhc_1 {
123	status = "okay";
124};
125
126/* For SD Card */
127&sdhc_2 {
128	status = "okay";
129};
130
131/* PINCTRL - BOARD-SPECIFIC */
132
133/*
134 * Methodology for gpio-line-names:
135 * - If a pin goes to herobrine board and is named it gets that name.
136 * - If a pin goes to herobrine board and is not named, it gets no name.
137 * - If a pin is totally internal to Qcard then it gets Qcard name.
138 * - If a pin is not hooked up on Qcard, it gets no name.
139 */
140
141&pm8350c_gpios {
142	gpio-line-names = "FLASH_STROBE_1",		/* 1 */
143			  "AP_SUSPEND",
144			  "PM8008_1_RST_N",
145			  "",
146			  "",
147			  "",
148			  "PMIC_EDP_BL_EN",
149			  "PMIC_EDP_BL_PWM",
150			  "";
151};
152
153&tlmm {
154	gpio-line-names = "AP_TP_I2C_SDA",		/* 0 */
155			  "AP_TP_I2C_SCL",
156			  "SSD_RST_L",
157			  "PE_WAKE_ODL",
158			  "AP_SAR_SDA",
159			  "AP_SAR_SCL",
160			  "PRB_SC_GPIO_6",
161			  "TP_INT_ODL",
162			  "HP_I2C_SDA",
163			  "HP_I2C_SCL",
164
165			  "GNSS_L1_EN",			/* 10 */
166			  "GNSS_L5_EN",
167			  "SPI_AP_MOSI",
168			  "SPI_AP_MISO",
169			  "SPI_AP_CLK",
170			  "SPI_AP_CS0_L",
171			  /*
172			   * AP_FLASH_WP is crossystem ABI. Schematics
173			   * call it BIOS_FLASH_WP_OD.
174			   */
175			  "AP_FLASH_WP",
176			  "",
177			  "AP_EC_INT_L",
178			  "",
179
180			  "UF_CAM_RST_L",		/* 20 */
181			  "WF_CAM_RST_L",
182			  "UART_AP_TX_DBG_RX",
183			  "UART_DBG_TX_AP_RX",
184			  "",
185			  "PM8008_IRQ_1",
186			  "HOST2WLAN_SOL",
187			  "WLAN2HOST_SOL",
188			  "MOS_BT_UART_CTS",
189			  "MOS_BT_UART_RFR",
190
191			  "MOS_BT_UART_TX",		/* 30 */
192			  "MOS_BT_UART_RX",
193			  "PRB_SC_GPIO_32",
194			  "HUB_RST_L",
195			  "",
196			  "",
197			  "AP_SPI_FP_MISO",
198			  "AP_SPI_FP_MOSI",
199			  "AP_SPI_FP_CLK",
200			  "AP_SPI_FP_CS_L",
201
202			  "AP_EC_SPI_MISO",		/* 40 */
203			  "AP_EC_SPI_MOSI",
204			  "AP_EC_SPI_CLK",
205			  "AP_EC_SPI_CS_L",
206			  "LCM_RST_L",
207			  "EARLY_EUD_N",
208			  "",
209			  "DP_HOT_PLUG_DET",
210			  "IO_BRD_MLB_ID0",
211			  "IO_BRD_MLB_ID1",
212
213			  "IO_BRD_MLB_ID2",		/* 50 */
214			  "SSD_EN",
215			  "TS_I2C_SDA_CONN",
216			  "TS_I2C_CLK_CONN",
217			  "TS_RST_CONN",
218			  "TS_INT_CONN",
219			  "AP_I2C_TPM_SDA",
220			  "AP_I2C_TPM_SCL",
221			  "PRB_SC_GPIO_58",
222			  "PRB_SC_GPIO_59",
223
224			  "EDP_HOT_PLUG_DET_N",		/* 60 */
225			  "FP_TO_AP_IRQ_L",
226			  "",
227			  "AMP_EN",
228			  "CAM0_MCLK_GPIO_64",
229			  "CAM1_MCLK_GPIO_65",
230			  "WF_CAM_MCLK",
231			  "PRB_SC_GPIO_67",
232			  "FPMCU_BOOT0",
233			  "UF_CAM_SDA",
234
235			  "UF_CAM_SCL",			/* 70 */
236			  "",
237			  "",
238			  "WF_CAM_SDA",
239			  "WF_CAM_SCL",
240			  "",
241			  "",
242			  "EN_FP_RAILS",
243			  "FP_RST_L",
244			  "PCIE1_CLKREQ_ODL",
245
246			  "EN_PP3300_DX_EDP",		/* 80 */
247			  "SC_GPIO_81",
248			  "FORCED_USB_BOOT",
249			  "WCD_RESET_N",
250			  "MOS_WLAN_EN",
251			  "MOS_BT_EN",
252			  "MOS_SW_CTRL",
253			  "MOS_PCIE0_RST",
254			  "MOS_PCIE0_CLKREQ_N",
255			  "MOS_PCIE0_WAKE_N",
256
257			  "MOS_LAA_AS_EN",		/* 90 */
258			  "SD_CD_ODL",
259			  "",
260			  "",
261			  "MOS_BT_WLAN_SLIMBUS_CLK",
262			  "MOS_BT_WLAN_SLIMBUS_DAT0",
263			  "HP_MCLK",
264			  "HP_BCLK",
265			  "HP_DOUT",
266			  "HP_DIN",
267
268			  "HP_LRCLK",			/* 100 */
269			  "HP_IRQ",
270			  "",
271			  "",
272			  "GSC_AP_INT_ODL",
273			  "EN_PP3300_CODEC",
274			  "AMP_BCLK",
275			  "AMP_DIN",
276			  "AMP_LRCLK",
277			  "UIM1_DATA_GPIO_109",
278
279			  "UIM1_CLK_GPIO_110",		/* 110 */
280			  "UIM1_RESET_GPIO_111",
281			  "PRB_SC_GPIO_112",
282			  "UIM0_DATA",
283			  "UIM0_CLK",
284			  "UIM0_RST",
285			  "UIM0_PRESENT_ODL",
286			  "SDM_RFFE0_CLK",
287			  "SDM_RFFE0_DATA",
288			  "WF_CAM_EN",
289
290			  "FASTBOOT_SEL_0",		/* 120 */
291			  "SC_GPIO_121",
292			  "FASTBOOT_SEL_1",
293			  "SC_GPIO_123",
294			  "FASTBOOT_SEL_2",
295			  "SM_RFFE4_CLK_GRFC_8",
296			  "SM_RFFE4_DATA_GRFC_9",
297			  "WLAN_COEX_UART1_RX",
298			  "WLAN_COEX_UART1_TX",
299			  "PRB_SC_GPIO_129",
300
301			  "LCM_ID0",			/* 130 */
302			  "LCM_ID1",
303			  "",
304			  "SDR_QLINK_REQ",
305			  "SDR_QLINK_EN",
306			  "QLINK0_WMSS_RESET_N",
307			  "SMR526_QLINK1_REQ",
308			  "SMR526_QLINK1_EN",
309			  "SMR526_QLINK1_WMSS_RESET_N",
310			  "PRB_SC_GPIO_139",
311
312			  "SAR1_IRQ_ODL",		/* 140 */
313			  "SAR0_IRQ_ODL",
314			  "PRB_SC_GPIO_142",
315			  "",
316			  "WCD_SWR_TX_CLK",
317			  "WCD_SWR_TX_DATA0",
318			  "WCD_SWR_TX_DATA1",
319			  "WCD_SWR_RX_CLK",
320			  "WCD_SWR_RX_DATA0",
321			  "WCD_SWR_RX_DATA1",
322
323			  "DMIC01_CLK",			/* 150 */
324			  "DMIC01_DATA",
325			  "DMIC23_CLK",
326			  "DMIC23_DATA",
327			  "",
328			  "",
329			  "EC_IN_RW_ODL",
330			  "HUB_EN",
331			  "WCD_SWR_TX_DATA2",
332			  "",
333
334			  "",				/* 160 */
335			  "",
336			  "",
337			  "",
338			  "",
339			  "",
340			  "",
341			  "",
342			  "",
343			  "",
344
345			  "",				/* 170 */
346			  "MOS_BLE_UART_TX",
347			  "MOS_BLE_UART_RX",
348			  "",
349			  "",
350			  "";
351};
352